# Copyright 2023 Dual Tachyon
# https://github.com/DualTachyon
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
#     http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.

[SYSCON]
@ = 0x40000000, 0x800

CLK_SEL = 0x0000
> SYS, 0, 1
= RCHF, 0
= DIV_CLK, 1

> DIV, 1, 3
= 1, 0
= 2, 1
= 4, 2
= 8, 3
= 16, 4
= 32, 5

> SRC, 4, 3
= RCHF, 0
= RCLF, 1
= XTAH, 2
= XTAL, 3
= PLL, 4

> W_PLL, 7, 1
= RCHF, 0
= XTAH, 1

# The documentation doesn't match the firmware!
> R_SARADC_SMPL, 9, 2
= DIV1, 0
= DIV2, 1
= DIV4, 2
= DIV8, 3

> W_SARADC_SMPL, 10, 2
= DIV1, 0
= DIV2, 1
= DIV4, 2
= DIV8, 3

> R_PLL, 11, 1
= RCHF, 0
= XTAH, 1

DIV_CLK_GATE = 0x0004
> DIV_CLK_GATE, 0, 1
= DISABLE, 0
= ENABLE, 1

DEV_CLK_GATE = 0x0008
> GPIOA, 0, 1
= DISABLE, 0
= ENABLE, 1

> GPIOB, 1, 1
= DISABLE, 0
= ENABLE, 1

> GPIOC, 2, 1
= DISABLE, 0
= ENABLE, 1

> IIC0, 4, 1
= DISABLE, 0
= ENABLE, 1

> IIC1, 5, 1
= DISABLE, 0
= ENABLE, 1

> UART0, 6, 1
= DISABLE, 0
= ENABLE, 1

> UART1, 7, 1
= DISABLE, 0
= ENABLE, 1

> UART2, 8, 1
= DISABLE, 0
= ENABLE, 1

> SPI0, 10, 1
= DISABLE, 0
= ENABLE, 1

> SPI1, 11, 1
= DISABLE, 0
= ENABLE, 1

> TIMER_BASE0, 12, 1
= DISABLE, 0
= ENABLE, 1

> TIMER_BASE1, 13, 1
= DISABLE, 0
= ENABLE, 1

> TIMER_BASE2, 14, 1
= DISABLE, 0
= ENABLE, 1

> TIMER_PLUS0, 15, 1
= DISABLE, 0
= ENABLE, 1

> TIMER_PLUS1, 16, 1
= DISABLE, 0
= ENABLE, 1

> PWM_BASE0, 17, 1
= DISABLE, 0
= ENABLE, 1

> PWM_BASE1, 18, 1
= DISABLE, 0
= ENABLE, 1

> PWM_PLUS0, 20, 1
= DISABLE, 0
= ENABLE, 1

> PWM_PLUS1, 21, 1
= DISABLE, 0
= ENABLE, 1

> RTC, 22, 1
= DISABLE, 0
= ENABLE, 1

> IWDT, 23, 1
= DISABLE, 0
= ENABLE, 1

> WWDT, 24, 1
= DISABLE, 0
= ENABLE, 1

> SARADC, 25, 1
= DISABLE, 0
= ENABLE, 1

> CRC, 27, 1
= DISABLE, 0
= ENABLE, 1

> AES, 28, 1
= DISABLE, 0
= ENABLE, 1

RC_FREQ_DELTA = 0x0078
> RCLF_DELTA, 0, 10
> RCLF_SIG, 10, 1
> RCHF_DELTA, 11, 20
> RCHF_SIG, 31, 1

VREF_VOLT_DELTA = 0x007C

CHIP_ID0 = 0x0080
CHIP_ID1 = 0x0084
CHIP_ID2 = 0x0088
CHIP_ID3 = 0x008C

