Initial commit
This commit is contained in:
OneOfEleven
@@ -0,0 +1,181 @@
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/*-----------------------------------------------------------------------------
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* Name: CV_CAL1Cache.c
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* Purpose: CMSIS CORE validation tests implementation
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*-----------------------------------------------------------------------------
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* Copyright (c) 2017 ARM Limited. All rights reserved.
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*----------------------------------------------------------------------------*/
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#include "CV_Framework.h"
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#include "cmsis_cv.h"
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/*-----------------------------------------------------------------------------
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* Test implementation
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*----------------------------------------------------------------------------*/
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/*-----------------------------------------------------------------------------
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* Test cases
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*----------------------------------------------------------------------------*/
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/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
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void TC_CAL1Cache_EnDisable(void) {
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uint32_t orig = __get_SCTLR();
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L1C_EnableCaches();
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uint32_t sctlr = __get_SCTLR();
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ASSERT_TRUE((sctlr & SCTLR_I_Msk) == SCTLR_I_Msk);
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ASSERT_TRUE((sctlr & SCTLR_C_Msk) == SCTLR_C_Msk);
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L1C_CleanDCacheAll();
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L1C_DisableCaches();
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sctlr = __get_SCTLR();
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ASSERT_TRUE((sctlr & SCTLR_I_Msk) == 0U);
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ASSERT_TRUE((sctlr & SCTLR_C_Msk) == 0U);
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__set_SCTLR(orig);
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__ISB();
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}
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/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
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void TC_CAL1Cache_EnDisableBTAC(void) {
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uint32_t orig = __get_SCTLR();
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L1C_EnableBTAC();
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uint32_t sctlr = __get_SCTLR();
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ASSERT_TRUE((sctlr & SCTLR_Z_Msk) == SCTLR_Z_Msk);
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L1C_DisableBTAC();
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sctlr = __get_SCTLR();
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#if __CORTEX_A == 7
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// On Cortex-A7 SCTLR_Z is RAO/WI.
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ASSERT_TRUE((sctlr & SCTLR_Z_Msk) == SCTLR_Z_Msk);
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#else
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ASSERT_TRUE((sctlr & SCTLR_Z_Msk) == 0U);
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#endif
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__set_SCTLR(orig);
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__ISB();
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}
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/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
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void TC_CAL1Cache_log2_up(void) {
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uint8_t log2 = __log2_up(0U);
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ASSERT_TRUE(log2 == 0U);
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log2 = __log2_up(1U);
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ASSERT_TRUE(log2 == 0U);
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log2 = __log2_up(2U);
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ASSERT_TRUE(log2 == 1U);
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log2 = __log2_up(3U);
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ASSERT_TRUE(log2 == 2U);
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log2 = __log2_up(4U);
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ASSERT_TRUE(log2 == 2U);
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log2 = __log2_up(0x80000000U);
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ASSERT_TRUE(log2 == 31U);
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log2 = __log2_up(0x80000001U);
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ASSERT_TRUE(log2 == 32U);
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log2 = __log2_up(0xFFFFFFFFU);
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ASSERT_TRUE(log2 == 32U);
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}
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/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
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void TC_CAL1Cache_InvalidateDCacheAll(void) {
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/* setup */
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uint32_t orig = __get_SCTLR();
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volatile uint32_t value = 0x0815U;
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L1C_EnableCaches();
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L1C_CleanDCacheAll();
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/* test cached value gets lost */
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// WHEN a value is written
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value = 0x4711U;
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// ... and the cache is invalidated
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L1C_InvalidateDCacheAll();
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// ... and the cache is disabled
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L1C_DisableCaches();
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// THEN the new value has been lost
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ASSERT_TRUE(value == 0x0815U);
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/* tear down */
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L1C_InvalidateDCacheAll();
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__set_SCTLR(orig);
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__ISB();
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}
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/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
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void TC_CAL1Cache_CleanDCacheAll(void) {
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/* setup */
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uint32_t orig = __get_SCTLR();
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uint32_t value = 0x0815U;
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L1C_EnableCaches();
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L1C_CleanDCacheAll();
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/* test cached value is preserved */
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// WHEN a value is written
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value = 0x4711U;
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// ... and the cache is cleaned
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L1C_CleanDCacheAll();
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// ... and the cache is disabled
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L1C_DisableCaches();
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// THEN the new value is preserved
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ASSERT_TRUE(value == 0x4711U);
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/* tear down */
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L1C_InvalidateDCacheAll();
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__set_SCTLR(orig);
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__ISB();
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}
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/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
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void TC_CAL1Cache_CleanInvalidateDCacheAll(void) {
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/* setup */
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uint32_t orig = __get_SCTLR();
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uint32_t value = 0x0815U;
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L1C_EnableCaches();
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L1C_CleanDCacheAll();
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/* test cached value is preserved */
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// WHEN a value is written
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value = 0x4711U;
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// ... and the cache is cleaned/invalidated
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L1C_CleanInvalidateDCacheAll();
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// ... and the cache is disabled
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L1C_DisableCaches();
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// THEN the new value is preserved
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ASSERT_TRUE(value == 0x4711U);
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/* tear down */
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L1C_InvalidateDCacheAll();
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__set_SCTLR(orig);
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__ISB();
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}
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@@ -0,0 +1,56 @@
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/*-----------------------------------------------------------------------------
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* Name: CV_CML1Cache.c
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* Purpose: CMSIS CORE validation tests implementation
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*-----------------------------------------------------------------------------
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* Copyright (c) 2020 - 2021 ARM Limited. All rights reserved.
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*----------------------------------------------------------------------------*/
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#include "CV_Framework.h"
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#include "cmsis_cv.h"
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/*-----------------------------------------------------------------------------
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* Test implementation
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*----------------------------------------------------------------------------*/
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/*-----------------------------------------------------------------------------
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* Test cases
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*----------------------------------------------------------------------------*/
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/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
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void TC_CML1Cache_EnDisableICache(void) {
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#ifdef __ICACHE_PRESENT
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SCB_EnableICache();
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ASSERT_TRUE((SCB->CCR & SCB_CCR_IC_Msk) == SCB_CCR_IC_Msk);
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SCB_DisableICache();
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ASSERT_TRUE((SCB->CCR & SCB_CCR_IC_Msk) == 0U);
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#endif
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}
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/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
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void TC_CML1Cache_EnDisableDCache(void) {
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#ifdef __DCACHE_PRESENT
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SCB_EnableDCache();
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ASSERT_TRUE((SCB->CCR & SCB_CCR_DC_Msk) == SCB_CCR_DC_Msk);
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SCB_DisableDCache();
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ASSERT_TRUE((SCB->CCR & SCB_CCR_DC_Msk) == 0U);
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#endif
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}
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/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
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#ifdef __DCACHE_PRESENT
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static uint32_t TC_CML1Cache_CleanDCacheByAddrWhileDisabled_Values[] = { 42U, 0U, 8U, 15U };
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#endif
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void TC_CML1Cache_CleanDCacheByAddrWhileDisabled(void) {
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#ifdef __DCACHE_PRESENT
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SCB_DisableDCache();
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SCB_CleanDCache_by_Addr(TC_CML1Cache_CleanDCacheByAddrWhileDisabled_Values, sizeof(TC_CML1Cache_CleanDCacheByAddrWhileDisabled_Values)/sizeof(TC_CML1Cache_CleanDCacheByAddrWhileDisabled_Values[0]));
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ASSERT_TRUE((SCB->CCR & SCB_CCR_DC_Msk) == 0U);
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#endif
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}
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@@ -0,0 +1,284 @@
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/*-----------------------------------------------------------------------------
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* Name: CV_CoreFunc.c
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* Purpose: CMSIS CORE validation tests implementation
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*-----------------------------------------------------------------------------
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* Copyright (c) 2017 ARM Limited. All rights reserved.
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*----------------------------------------------------------------------------*/
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#include "CV_Framework.h"
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#include "cmsis_cv.h"
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/*-----------------------------------------------------------------------------
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* Test implementation
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*----------------------------------------------------------------------------*/
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/*-----------------------------------------------------------------------------
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* Test cases
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*----------------------------------------------------------------------------*/
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/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
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void TC_CoreAFunc_IRQ(void) {
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uint32_t orig = __get_CPSR();
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__enable_irq();
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uint32_t cpsr = __get_CPSR();
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ASSERT_TRUE((cpsr & CPSR_I_Msk) == 0U);
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__disable_irq();
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cpsr = __get_CPSR();
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ASSERT_TRUE((cpsr & CPSR_I_Msk) == CPSR_I_Msk);
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__set_CPSR(orig);
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}
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/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
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void TC_CoreAFunc_FaultIRQ(void) {
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uint32_t orig = __get_CPSR();
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__enable_fault_irq();
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uint32_t cpsr = __get_CPSR();
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ASSERT_TRUE((cpsr & CPSR_F_Msk) == 0U);
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__disable_fault_irq();
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cpsr = __get_CPSR();
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ASSERT_TRUE((cpsr & CPSR_F_Msk) == CPSR_F_Msk);
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__set_CPSR(orig);
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}
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/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
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void TC_CoreAFunc_FPSCR(void) {
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volatile float f1 = 47.11f;
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volatile float f2 = 8.15f;
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volatile float f3 = f1 / f2;
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uint32_t fpscr = __get_FPSCR();
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__set_FPSCR(fpscr);
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ASSERT_TRUE(fpscr == __get_FPSCR());
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ASSERT_TRUE((f3 < 5.781f) && (f3 > 5.780f));
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}
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/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
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#if defined(__CC_ARM)
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#define __SUBS(Rd, Rm, Rn) __ASM volatile("SUBS " # Rd ", " # Rm ", " # Rn)
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#define __ADDS(Rd, Rm, Rn) __ASM volatile("ADDS " # Rd ", " # Rm ", " # Rn)
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#elif defined( __GNUC__ ) && defined(__thumb__)
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#define __SUBS(Rd, Rm, Rn) __ASM volatile("SUB %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
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#define __ADDS(Rd, Rm, Rn) __ASM volatile("ADD %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
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#else
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#define __SUBS(Rd, Rm, Rn) __ASM volatile("SUBS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
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#define __ADDS(Rd, Rm, Rn) __ASM volatile("ADDS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn))
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#endif
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void TC_CoreAFunc_CPSR(void) {
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uint32_t result;
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uint32_t cpsr = __get_CPSR();
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__set_CPSR(cpsr & CPSR_M_Msk);
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// Check negative flag
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int32_t Rm = 5;
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int32_t Rn = 7;
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__SUBS(Rm, Rm, Rn);
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result = __get_CPSR();
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ASSERT_TRUE((result & CPSR_N_Msk) == CPSR_N_Msk);
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// Check zero and compare flag
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Rm = 5;
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__SUBS(Rm, Rm, Rm);
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result = __get_CPSR();
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ASSERT_TRUE((result & CPSR_Z_Msk) == CPSR_Z_Msk);
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ASSERT_TRUE((result & CPSR_C_Msk) == CPSR_C_Msk);
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// Check overflow flag
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Rm = 5;
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Rn = INT32_MAX;
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__ADDS(Rm, Rm, Rn);
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result = __get_CPSR();
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ASSERT_TRUE((result & CPSR_V_Msk) == CPSR_V_Msk);
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}
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/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
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void TC_CoreAFunc_Mode(void) {
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uint32_t mode = __get_mode();
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__set_mode(mode);
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ASSERT_TRUE(mode == __get_mode());
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}
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/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
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static uint32_t TC_CoreAFunc_SP_orig;
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static uint32_t TC_CoreAFunc_SP_sp;
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static uint32_t TC_CoreAFunc_SP_result;
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void TC_CoreAFunc_SP(void) {
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TC_CoreAFunc_SP_orig = __get_SP();
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TC_CoreAFunc_SP_sp = TC_CoreAFunc_SP_orig + 0x12345678U;
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__set_SP(TC_CoreAFunc_SP_sp);
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TC_CoreAFunc_SP_result = __get_SP();
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__set_SP(TC_CoreAFunc_SP_orig);
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ASSERT_TRUE(TC_CoreAFunc_SP_result == TC_CoreAFunc_SP_sp);
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}
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/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
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static uint32_t TC_CoreAFunc_SP_usr_orig;
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static uint32_t TC_CoreAFunc_SP_usr_sp;
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static uint32_t TC_CoreAFunc_SP_usr_result;
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void TC_CoreAFunc_SP_usr(void) {
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TC_CoreAFunc_SP_usr_orig = __get_SP_usr();
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TC_CoreAFunc_SP_usr_sp = TC_CoreAFunc_SP_usr_orig + 0x12345678U;
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__set_SP(TC_CoreAFunc_SP_usr_sp);
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TC_CoreAFunc_SP_usr_result = __get_SP_usr();
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__set_SP(TC_CoreAFunc_SP_usr_orig);
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ASSERT_TRUE(TC_CoreAFunc_SP_usr_result == TC_CoreAFunc_SP_usr_sp);
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}
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/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
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void TC_CoreAFunc_FPEXC(void) {
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uint32_t fpexc = __get_FPEXC();
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__set_FPEXC(fpexc);
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ASSERT_TRUE(fpexc == __get_FPEXC());
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}
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/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
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void TC_CoreAFunc_ACTLR(void) {
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uint32_t actlr = __get_ACTLR();
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__set_ACTLR(actlr);
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ASSERT_TRUE(actlr == __get_ACTLR());
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}
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/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
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void TC_CoreAFunc_CPACR(void) {
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uint32_t cpacr = __get_CPACR();
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__set_CPACR(cpacr);
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ASSERT_TRUE(cpacr == __get_CPACR());
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}
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/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
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void TC_CoreAFunc_DFSR(void) {
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uint32_t dfsr = __get_DFSR();
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__set_DFSR(dfsr);
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ASSERT_TRUE(dfsr == __get_DFSR());
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}
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/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
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void TC_CoreAFunc_IFSR(void) {
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uint32_t ifsr = __get_IFSR();
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__set_IFSR(ifsr);
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ASSERT_TRUE(ifsr == __get_IFSR());
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}
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/*0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
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void TC_CoreAFunc_ISR(void) {
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uint32_t isr = __get_ISR();
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ASSERT_TRUE(isr == __get_ISR());
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}
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/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
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void TC_CoreAFunc_CBAR(void) {
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uint32_t cbar = __get_CBAR();
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ASSERT_TRUE(cbar == __get_CBAR());
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}
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/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
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void TC_CoreAFunc_TTBR0(void) {
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uint32_t ttbr0 = __get_TTBR0();
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__set_TTBR0(ttbr0);
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ASSERT_TRUE(ttbr0 == __get_TTBR0());
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}
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/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
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void TC_CoreAFunc_DACR(void) {
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uint32_t dacr = __get_DACR();
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__set_DACR(dacr);
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ASSERT_TRUE(dacr == __get_DACR());
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}
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/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
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void TC_CoreAFunc_SCTLR(void) {
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uint32_t sctlr = __get_SCTLR();
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__set_SCTLR(sctlr);
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ASSERT_TRUE(sctlr == __get_SCTLR());
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
void TC_CoreAFunc_ACTRL(void) {
|
||||
uint32_t actrl = __get_ACTRL();
|
||||
__set_ACTRL(actrl);
|
||||
|
||||
ASSERT_TRUE(actrl == __get_ACTRL());
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
void TC_CoreAFunc_MPIDR(void) {
|
||||
uint32_t mpidr = __get_MPIDR();
|
||||
|
||||
ASSERT_TRUE(mpidr == __get_MPIDR());
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
static uint8_t vectorRAM[32U] __attribute__((aligned(32U)));
|
||||
|
||||
void TC_CoreAFunc_VBAR(void) {
|
||||
uint32_t vbar = __get_VBAR();
|
||||
|
||||
memcpy(vectorRAM, (void*)vbar, sizeof(vectorRAM));
|
||||
|
||||
__set_VBAR((uint32_t)vectorRAM);
|
||||
ASSERT_TRUE(((uint32_t)vectorRAM) == __get_VBAR());
|
||||
|
||||
__set_VBAR(vbar);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
void TC_CoreAFunc_MVBAR(void) {
|
||||
uint32_t mvbar = __get_MVBAR();
|
||||
|
||||
memcpy(vectorRAM, (void*)mvbar, sizeof(vectorRAM));
|
||||
|
||||
__set_MVBAR((uint32_t)vectorRAM);
|
||||
ASSERT_TRUE(((uint32_t)vectorRAM) == __get_MVBAR());
|
||||
|
||||
__set_MVBAR(mvbar);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
|
||||
void TC_CoreAFunc_FPU_Enable(void) {
|
||||
uint32_t fpexc = __get_FPEXC();
|
||||
__set_FPEXC(fpexc & ~0x40000000u); // disable FPU
|
||||
|
||||
uint32_t cp15;
|
||||
__get_CP(15, 0, cp15, 1, 0, 2);
|
||||
|
||||
cp15 &= ~0x00F00000u;
|
||||
__set_CP(15, 0, cp15, 1, 0, 2); // disable FPU access
|
||||
|
||||
__FPU_Enable();
|
||||
|
||||
__get_CP(15, 0, cp15, 1, 0, 2);
|
||||
ASSERT_TRUE((cp15 & 0x00F00000u) == 0x00F00000u);
|
||||
|
||||
fpexc = __get_FPEXC();
|
||||
ASSERT_TRUE((fpexc & 0x40000000u) == 0x40000000u);
|
||||
}
|
||||
|
||||
@@ -0,0 +1,723 @@
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Name: CV_CoreFunc.c
|
||||
* Purpose: CMSIS CORE validation tests implementation
|
||||
*-----------------------------------------------------------------------------
|
||||
* Copyright (c) 2017 - 2023 Arm Limited. All rights reserved.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
#include "CV_Framework.h"
|
||||
#include "cmsis_cv.h"
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Test implementation
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
static volatile uint32_t irqTaken = 0U;
|
||||
#if defined(__CORTEX_M) && (__CORTEX_M > 0)
|
||||
static volatile uint32_t irqActive = 0U;
|
||||
#endif
|
||||
|
||||
static void TC_CoreFunc_EnDisIRQIRQHandler(void) {
|
||||
++irqTaken;
|
||||
#if defined(__CORTEX_M) && (__CORTEX_M > 0)
|
||||
irqActive = NVIC_GetActive(Interrupt0_IRQn);
|
||||
#endif
|
||||
}
|
||||
|
||||
static volatile uint32_t irqIPSR = 0U;
|
||||
static volatile uint32_t irqXPSR = 0U;
|
||||
|
||||
static void TC_CoreFunc_IPSR_IRQHandler(void) {
|
||||
irqIPSR = __get_IPSR();
|
||||
irqXPSR = __get_xPSR();
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Test cases
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreFunc_EnDisIRQ
|
||||
\details
|
||||
Check expected behavior of interrupt related control functions:
|
||||
- __disable_irq() and __enable_irq()
|
||||
- NVIC_EnableIRQ, NVIC_DisableIRQ, and NVIC_GetEnableIRQ
|
||||
- NVIC_SetPendingIRQ, NVIC_ClearPendingIRQ, and NVIC_GetPendingIRQ
|
||||
- NVIC_GetActive (not on Cortex-M0/M0+)
|
||||
*/
|
||||
void TC_CoreFunc_EnDisIRQ (void)
|
||||
{
|
||||
// Globally disable all interrupt servicing
|
||||
__disable_irq();
|
||||
|
||||
// Enable the interrupt
|
||||
NVIC_EnableIRQ(Interrupt0_IRQn);
|
||||
ASSERT_TRUE(NVIC_GetEnableIRQ(Interrupt0_IRQn) != 0U);
|
||||
|
||||
// Clear its pending state
|
||||
NVIC_ClearPendingIRQ(Interrupt0_IRQn);
|
||||
ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) == 0U);
|
||||
|
||||
// Register test interrupt handler.
|
||||
TST_IRQHandler = TC_CoreFunc_EnDisIRQIRQHandler;
|
||||
irqTaken = 0U;
|
||||
#if defined(__CORTEX_M) && (__CORTEX_M > 0)
|
||||
irqActive = UINT32_MAX;
|
||||
#endif
|
||||
|
||||
// Set the interrupt pending state
|
||||
NVIC_SetPendingIRQ(Interrupt0_IRQn);
|
||||
for(uint32_t i = 10U; i > 0U; --i) {__NOP();}
|
||||
|
||||
// Interrupt is not taken
|
||||
ASSERT_TRUE(irqTaken == 0U);
|
||||
ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) != 0U);
|
||||
#if defined(__CORTEX_M) && (__CORTEX_M > 0)
|
||||
ASSERT_TRUE(NVIC_GetActive(Interrupt0_IRQn) == 0U);
|
||||
#endif
|
||||
|
||||
// Globally enable interrupt servicing
|
||||
__enable_irq();
|
||||
|
||||
for(uint32_t i = 10U; i > 0U; --i) {__NOP();}
|
||||
|
||||
// Interrupt was taken
|
||||
ASSERT_TRUE(irqTaken == 1U);
|
||||
#if defined(__CORTEX_M) && (__CORTEX_M > 0)
|
||||
ASSERT_TRUE(irqActive != 0U);
|
||||
ASSERT_TRUE(NVIC_GetActive(Interrupt0_IRQn) == 0U);
|
||||
#endif
|
||||
|
||||
// Interrupt it not pending anymore.
|
||||
ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) == 0U);
|
||||
|
||||
// Disable interrupt
|
||||
NVIC_DisableIRQ(Interrupt0_IRQn);
|
||||
ASSERT_TRUE(NVIC_GetEnableIRQ(Interrupt0_IRQn) == 0U);
|
||||
|
||||
// Set interrupt pending
|
||||
NVIC_SetPendingIRQ(Interrupt0_IRQn);
|
||||
for(uint32_t i = 10U; i > 0U; --i) {__NOP();}
|
||||
|
||||
// Interrupt is not taken again
|
||||
ASSERT_TRUE(irqTaken == 1U);
|
||||
ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) != 0U);
|
||||
|
||||
// Clear interrupt pending
|
||||
NVIC_ClearPendingIRQ(Interrupt0_IRQn);
|
||||
for(uint32_t i = 10U; i > 0U; --i) {__NOP();}
|
||||
|
||||
// Interrupt it not pending anymore.
|
||||
ASSERT_TRUE(NVIC_GetPendingIRQ(Interrupt0_IRQn) == 0U);
|
||||
|
||||
// Globally disable interrupt servicing
|
||||
__disable_irq();
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreFunc_IRQPrio
|
||||
\details
|
||||
Check expected behavior of interrupt priority control functions:
|
||||
- NVIC_SetPriority, NVIC_GetPriority
|
||||
*/
|
||||
void TC_CoreFunc_IRQPrio (void)
|
||||
{
|
||||
/* Test Exception Priority */
|
||||
uint32_t orig = NVIC_GetPriority(SVCall_IRQn);
|
||||
|
||||
NVIC_SetPriority(SVCall_IRQn, orig+1U);
|
||||
uint32_t prio = NVIC_GetPriority(SVCall_IRQn);
|
||||
|
||||
ASSERT_TRUE(prio == orig+1U);
|
||||
|
||||
NVIC_SetPriority(SVCall_IRQn, orig);
|
||||
|
||||
/* Test Interrupt Priority */
|
||||
orig = NVIC_GetPriority(Interrupt0_IRQn);
|
||||
|
||||
NVIC_SetPriority(Interrupt0_IRQn, orig+1U);
|
||||
prio = NVIC_GetPriority(Interrupt0_IRQn);
|
||||
|
||||
ASSERT_TRUE(prio == orig+1U);
|
||||
|
||||
NVIC_SetPriority(Interrupt0_IRQn, orig);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/** Helper function for TC_CoreFunc_EncDecIRQPrio
|
||||
\details
|
||||
The helper encodes and decodes the given priority configuration.
|
||||
\param[in] prigroup The PRIGROUP setting to be considered for encoding/decoding.
|
||||
\param[in] pre The preempt priority value.
|
||||
\param[in] sub The subpriority value.
|
||||
*/
|
||||
static void TC_CoreFunc_EncDecIRQPrio_Step(uint32_t prigroup, uint32_t pre, uint32_t sub) {
|
||||
uint32_t prio = NVIC_EncodePriority(prigroup, pre, sub);
|
||||
|
||||
uint32_t ret_pre = UINT32_MAX;
|
||||
uint32_t ret_sub = UINT32_MAX;
|
||||
|
||||
NVIC_DecodePriority(prio, prigroup, &ret_pre, &ret_sub);
|
||||
|
||||
ASSERT_TRUE(ret_pre == pre);
|
||||
ASSERT_TRUE(ret_sub == sub);
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Test case: TC_CoreFunc_EncDecIRQPrio
|
||||
\details
|
||||
Check expected behavior of interrupt priority encoding/decoding functions:
|
||||
- NVIC_EncodePriority, NVIC_DecodePriority
|
||||
*/
|
||||
void TC_CoreFunc_EncDecIRQPrio (void)
|
||||
{
|
||||
/* Check only the valid range of PRIGROUP and preempt-/sub-priority values. */
|
||||
static const uint32_t priobits = (__NVIC_PRIO_BITS > 7U) ? 7U : __NVIC_PRIO_BITS;
|
||||
for(uint32_t prigroup = 7U-priobits; prigroup<7U; prigroup++) {
|
||||
for(uint32_t pre = 0U; pre<(128U>>prigroup); pre++) {
|
||||
for(uint32_t sub = 0U; sub<(256U>>(8U-__NVIC_PRIO_BITS+7U-prigroup)); sub++) {
|
||||
TC_CoreFunc_EncDecIRQPrio_Step(prigroup, pre, sub);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreFunc_IRQVect
|
||||
\details
|
||||
Check expected behavior of interrupt vector relocation functions:
|
||||
- NVIC_SetVector, NVIC_GetVector
|
||||
*/
|
||||
void TC_CoreFunc_IRQVect(void) {
|
||||
#if defined(__VTOR_PRESENT) && __VTOR_PRESENT
|
||||
/* relocate vector table */
|
||||
extern const VECTOR_TABLE_Type __VECTOR_TABLE[48];
|
||||
static VECTOR_TABLE_Type vectors[sizeof(__VECTOR_TABLE)/sizeof(__VECTOR_TABLE[0])] __ALIGNED(1024) __NO_INIT;
|
||||
memcpy(vectors, __VECTOR_TABLE, sizeof(__VECTOR_TABLE));
|
||||
|
||||
const uint32_t orig_vtor = SCB->VTOR;
|
||||
const uint32_t vtor = ((uint32_t)vectors) & SCB_VTOR_TBLOFF_Msk;
|
||||
SCB->VTOR = vtor;
|
||||
|
||||
ASSERT_TRUE(vtor == SCB->VTOR);
|
||||
|
||||
/* check exception vectors */
|
||||
extern void HardFault_Handler(void);
|
||||
extern void SVC_Handler(void);
|
||||
extern void PendSV_Handler(void);
|
||||
extern void SysTick_Handler(void);
|
||||
|
||||
ASSERT_TRUE(NVIC_GetVector(HardFault_IRQn) == (uint32_t)HardFault_Handler);
|
||||
ASSERT_TRUE(NVIC_GetVector(SVCall_IRQn) == (uint32_t)SVC_Handler);
|
||||
ASSERT_TRUE(NVIC_GetVector(PendSV_IRQn) == (uint32_t)PendSV_Handler);
|
||||
ASSERT_TRUE(NVIC_GetVector(SysTick_IRQn) == (uint32_t)SysTick_Handler);
|
||||
|
||||
/* reconfigure WDT IRQ vector */
|
||||
extern void Interrupt0_Handler(void);
|
||||
|
||||
const uint32_t wdtvec = NVIC_GetVector(Interrupt0_IRQn);
|
||||
ASSERT_TRUE(wdtvec == (uint32_t)Interrupt0_Handler);
|
||||
|
||||
NVIC_SetVector(Interrupt0_IRQn, wdtvec + 32U);
|
||||
|
||||
ASSERT_TRUE(NVIC_GetVector(Interrupt0_IRQn) == (wdtvec + 32U));
|
||||
|
||||
/* restore vector table */
|
||||
SCB->VTOR = orig_vtor;
|
||||
#endif
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreFunc_GetCtrl
|
||||
\details
|
||||
- Check if __set_CONTROL and __get_CONTROL() sets/gets control register
|
||||
*/
|
||||
void TC_CoreFunc_Control (void) {
|
||||
// don't use stack for this variables
|
||||
static uint32_t orig;
|
||||
static uint32_t ctrl;
|
||||
static uint32_t result;
|
||||
|
||||
orig = __get_CONTROL();
|
||||
ctrl = orig;
|
||||
result = UINT32_MAX;
|
||||
|
||||
#ifdef CONTROL_SPSEL_Msk
|
||||
// SPSEL set to 0 (MSP)
|
||||
ASSERT_TRUE((ctrl & CONTROL_SPSEL_Msk) == 0U);
|
||||
|
||||
// SPSEL set to 1 (PSP)
|
||||
ctrl |= CONTROL_SPSEL_Msk;
|
||||
|
||||
// Move MSP to PSP
|
||||
__set_PSP(__get_MSP());
|
||||
#endif
|
||||
|
||||
__set_CONTROL(ctrl);
|
||||
__ISB();
|
||||
|
||||
result = __get_CONTROL();
|
||||
|
||||
__set_CONTROL(orig);
|
||||
__ISB();
|
||||
|
||||
ASSERT_TRUE(result == ctrl);
|
||||
ASSERT_TRUE(__get_CONTROL() == orig);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreFunc_IPSR
|
||||
\details
|
||||
- Check if __get_IPSR intrinsic is available
|
||||
- Check if __get_xPSR intrinsic is available
|
||||
- Result differentiates between thread and exception modes
|
||||
*/
|
||||
void TC_CoreFunc_IPSR (void) {
|
||||
uint32_t result = __get_IPSR();
|
||||
ASSERT_TRUE(result == 0U); // Thread Mode
|
||||
|
||||
result = __get_xPSR();
|
||||
ASSERT_TRUE((result & xPSR_ISR_Msk) == 0U); // Thread Mode
|
||||
|
||||
TST_IRQHandler = TC_CoreFunc_IPSR_IRQHandler;
|
||||
irqIPSR = 0U;
|
||||
irqXPSR = 0U;
|
||||
|
||||
NVIC_ClearPendingIRQ(Interrupt0_IRQn);
|
||||
NVIC_EnableIRQ(Interrupt0_IRQn);
|
||||
__enable_irq();
|
||||
|
||||
NVIC_SetPendingIRQ(Interrupt0_IRQn);
|
||||
for(uint32_t i = 10U; i > 0U; --i) {__NOP();}
|
||||
|
||||
__disable_irq();
|
||||
NVIC_DisableIRQ(Interrupt0_IRQn);
|
||||
|
||||
ASSERT_TRUE(irqIPSR != 0U); // Exception Mode
|
||||
ASSERT_TRUE((irqXPSR & xPSR_ISR_Msk) != 0U); // Exception Mode
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
|
||||
#if defined(__CC_ARM)
|
||||
#define SUBS(Rd, Rm, Rn) __ASM volatile("SUBS " # Rd ", " # Rm ", " # Rn)
|
||||
#define ADDS(Rd, Rm, Rn) __ASM volatile("ADDS " # Rd ", " # Rm ", " # Rn)
|
||||
#elif defined( __GNUC__ ) && (!defined(__ti__)) && (!defined(__ARMCC_VERSION)) && (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__))
|
||||
#define SUBS(Rd, Rm, Rn) __ASM volatile("SUB %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn) : "cc")
|
||||
#define ADDS(Rd, Rm, Rn) __ASM volatile("ADD %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn) : "cc")
|
||||
#elif defined(_lint)
|
||||
//lint -save -e(9026) allow function-like macro
|
||||
#define SUBS(Rd, Rm, Rn) ((Rd) = (Rm) - (Rn))
|
||||
#define ADDS(Rd, Rm, Rn) ((Rd) = (Rm) + (Rn))
|
||||
//lint -restore
|
||||
#else
|
||||
#define SUBS(Rd, Rm, Rn) __ASM volatile("SUBS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn) : "cc")
|
||||
#define ADDS(Rd, Rm, Rn) __ASM volatile("ADDS %0, %1, %2" : "=r"(Rd) : "r"(Rm), "r"(Rn) : "cc")
|
||||
#endif
|
||||
|
||||
/**
|
||||
\brief Test case: TC_CoreFunc_APSR
|
||||
\details
|
||||
- Check if __get_APSR intrinsic is available
|
||||
- Check if __get_xPSR intrinsic is available
|
||||
- Check negative, zero and overflow flags
|
||||
*/
|
||||
void TC_CoreFunc_APSR (void) {
|
||||
volatile uint32_t result;
|
||||
//lint -esym(838, Rm) unused values
|
||||
//lint -esym(438, Rm) unused values
|
||||
|
||||
// Check negative flag
|
||||
volatile int32_t Rm = 5;
|
||||
volatile int32_t Rn = 7;
|
||||
SUBS(Rm, Rm, Rn);
|
||||
result = __get_APSR();
|
||||
ASSERT_TRUE((result & APSR_N_Msk) == APSR_N_Msk);
|
||||
|
||||
Rm = 5;
|
||||
Rn = 7;
|
||||
SUBS(Rm, Rm, Rn);
|
||||
result = __get_xPSR();
|
||||
ASSERT_TRUE((result & xPSR_N_Msk) == xPSR_N_Msk);
|
||||
|
||||
// Check zero and compare flag
|
||||
Rm = 5;
|
||||
SUBS(Rm, Rm, Rm);
|
||||
result = __get_APSR();
|
||||
ASSERT_TRUE((result & APSR_Z_Msk) == APSR_Z_Msk);
|
||||
ASSERT_TRUE((result & APSR_C_Msk) == APSR_C_Msk);
|
||||
|
||||
Rm = 5;
|
||||
SUBS(Rm, Rm, Rm);
|
||||
result = __get_xPSR();
|
||||
ASSERT_TRUE((result & xPSR_Z_Msk) == xPSR_Z_Msk);
|
||||
ASSERT_TRUE((result & APSR_C_Msk) == APSR_C_Msk);
|
||||
|
||||
// Check overflow flag
|
||||
Rm = 5;
|
||||
Rn = INT32_MAX;
|
||||
ADDS(Rm, Rm, Rn);
|
||||
result = __get_APSR();
|
||||
ASSERT_TRUE((result & APSR_V_Msk) == APSR_V_Msk);
|
||||
|
||||
Rm = 5;
|
||||
Rn = INT32_MAX;
|
||||
ADDS(Rm, Rm, Rn);
|
||||
result = __get_xPSR();
|
||||
ASSERT_TRUE((result & xPSR_V_Msk) == xPSR_V_Msk);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreFunc_PSP
|
||||
\details
|
||||
- Check if __get_PSP and __set_PSP intrinsic can be used to manipulate process stack pointer.
|
||||
*/
|
||||
void TC_CoreFunc_PSP (void) {
|
||||
// don't use stack for this variables
|
||||
static uint32_t orig;
|
||||
static uint32_t psp;
|
||||
static uint32_t result;
|
||||
|
||||
orig = __get_PSP();
|
||||
|
||||
psp = orig + 0x12345678U;
|
||||
__set_PSP(psp);
|
||||
|
||||
result = __get_PSP();
|
||||
|
||||
__set_PSP(orig);
|
||||
|
||||
ASSERT_TRUE(result == psp);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreFunc_MSP
|
||||
\details
|
||||
- Check if __get_MSP and __set_MSP intrinsic can be used to manipulate main stack pointer.
|
||||
*/
|
||||
void TC_CoreFunc_MSP (void) {
|
||||
// don't use stack for this variables
|
||||
static uint32_t orig;
|
||||
static uint32_t msp;
|
||||
static uint32_t result;
|
||||
static uint32_t ctrl;
|
||||
|
||||
ctrl = __get_CONTROL();
|
||||
orig = __get_MSP();
|
||||
|
||||
__set_PSP(orig);
|
||||
__set_CONTROL(ctrl | CONTROL_SPSEL_Msk); // switch to PSP
|
||||
|
||||
msp = orig + 0x12345678U;
|
||||
__set_MSP(msp);
|
||||
|
||||
result = __get_MSP();
|
||||
|
||||
__set_MSP(orig);
|
||||
|
||||
__set_CONTROL(ctrl);
|
||||
|
||||
ASSERT_TRUE(result == msp);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreFunc_PSPLIM
|
||||
\details
|
||||
- Check if __get_PSPLIM and __set_PSPLIM intrinsic can be used to manipulate process stack pointer limit.
|
||||
*/
|
||||
void TC_CoreFunc_PSPLIM (void) {
|
||||
#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
// don't use stack for this variables
|
||||
static uint32_t orig;
|
||||
static uint32_t psplim;
|
||||
static uint32_t result;
|
||||
|
||||
orig = __get_PSPLIM();
|
||||
|
||||
psplim = orig + 0x12345678U;
|
||||
__set_PSPLIM(psplim);
|
||||
|
||||
result = __get_PSPLIM();
|
||||
|
||||
__set_PSPLIM(orig);
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
|
||||
!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)) )
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
ASSERT_TRUE(result == 0U);
|
||||
#else
|
||||
ASSERT_TRUE(result == psplim);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreFunc_PSPLIM_NS
|
||||
\details
|
||||
- Check if __TZ_get_PSPLIM_NS and __TZ_set_PSPLIM_NS intrinsic can be used to manipulate process stack pointer limit.
|
||||
*/
|
||||
void TC_CoreFunc_PSPLIM_NS (void) {
|
||||
#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
|
||||
#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
|
||||
uint32_t orig;
|
||||
uint32_t psplim;
|
||||
uint32_t result;
|
||||
|
||||
orig = __TZ_get_PSPLIM_NS();
|
||||
|
||||
psplim = orig + 0x12345678U;
|
||||
__TZ_set_PSPLIM_NS(psplim);
|
||||
|
||||
result = __TZ_get_PSPLIM_NS();
|
||||
|
||||
__TZ_set_PSPLIM_NS(orig);
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
|
||||
!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
|
||||
// without main extensions, the non-secure PSPLIM is RAZ/WI
|
||||
ASSERT_TRUE(result == 0U);
|
||||
#else
|
||||
ASSERT_TRUE(result == psplim);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreFunc_MSPLIM
|
||||
\details
|
||||
- Check if __get_MSPLIM and __set_MSPLIM intrinsic can be used to manipulate main stack pointer limit.
|
||||
*/
|
||||
void TC_CoreFunc_MSPLIM (void) {
|
||||
#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
// don't use stack for this variables
|
||||
static uint32_t orig;
|
||||
static uint32_t msplim;
|
||||
static uint32_t result;
|
||||
static uint32_t ctrl;
|
||||
|
||||
ctrl = __get_CONTROL();
|
||||
__set_CONTROL(ctrl | CONTROL_SPSEL_Msk); // switch to PSP
|
||||
|
||||
orig = __get_MSPLIM();
|
||||
|
||||
msplim = orig + 0x12345678U;
|
||||
__set_MSPLIM(msplim);
|
||||
|
||||
result = __get_MSPLIM();
|
||||
|
||||
__set_MSPLIM(orig);
|
||||
|
||||
__set_CONTROL(ctrl);
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
|
||||
!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
|
||||
(!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3)) )
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
ASSERT_TRUE(result == 0U);
|
||||
#else
|
||||
ASSERT_TRUE(result == msplim);
|
||||
#endif
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreFunc_MSPLIM_NS
|
||||
\details
|
||||
- Check if __TZ_get_MSPLIM_NS and __TZ_set_MSPLIM_NS intrinsic can be used to manipulate process stack pointer limit.
|
||||
*/
|
||||
void TC_CoreFunc_MSPLIM_NS (void) {
|
||||
#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
|
||||
#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3))
|
||||
uint32_t orig;
|
||||
uint32_t msplim;
|
||||
uint32_t result;
|
||||
|
||||
orig = __TZ_get_MSPLIM_NS();
|
||||
|
||||
msplim = orig + 0x12345678U;
|
||||
__TZ_set_MSPLIM_NS(msplim);
|
||||
|
||||
result = __TZ_get_MSPLIM_NS();
|
||||
|
||||
__TZ_set_MSPLIM_NS(orig);
|
||||
|
||||
#if (!(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) && \
|
||||
!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
|
||||
// without main extensions, the non-secure MSPLIM is RAZ/WI
|
||||
ASSERT_TRUE(result == 0U);
|
||||
#else
|
||||
ASSERT_TRUE(result == msplim);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreFunc_PRIMASK
|
||||
\details
|
||||
- Check if __get_PRIMASK and __set_PRIMASK intrinsic can be used to manipulate PRIMASK.
|
||||
- Check if __enable_irq and __disable_irq are reflected in PRIMASK.
|
||||
*/
|
||||
void TC_CoreFunc_PRIMASK (void) {
|
||||
uint32_t orig = __get_PRIMASK();
|
||||
|
||||
// toggle primask
|
||||
uint32_t primask = (orig & ~0x01U) | (~orig & 0x01U);
|
||||
|
||||
__set_PRIMASK(primask);
|
||||
uint32_t result = __get_PRIMASK();
|
||||
ASSERT_TRUE(result == primask);
|
||||
|
||||
__disable_irq();
|
||||
result = __get_PRIMASK();
|
||||
ASSERT_TRUE((result & 0x01U) == 1U);
|
||||
|
||||
__enable_irq();
|
||||
result = __get_PRIMASK();
|
||||
ASSERT_TRUE((result & 0x01U) == 0U);
|
||||
|
||||
__disable_irq();
|
||||
result = __get_PRIMASK();
|
||||
ASSERT_TRUE((result & 0x01U) == 1U);
|
||||
|
||||
__set_PRIMASK(orig);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreFunc_FAULTMASK
|
||||
\details
|
||||
- Check if __get_FAULTMASK and __set_FAULTMASK intrinsic can be used to manipulate FAULTMASK.
|
||||
- Check if __enable_fault_irq and __disable_fault_irq are reflected in FAULTMASK.
|
||||
*/
|
||||
void TC_CoreFunc_FAULTMASK (void) {
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
|
||||
|
||||
uint32_t orig = __get_FAULTMASK();
|
||||
|
||||
// toggle faultmask
|
||||
uint32_t faultmask = (orig & ~0x01U) | (~orig & 0x01U);
|
||||
|
||||
__set_FAULTMASK(faultmask);
|
||||
uint32_t result = __get_FAULTMASK();
|
||||
ASSERT_TRUE(result == faultmask);
|
||||
|
||||
__disable_fault_irq();
|
||||
result = __get_FAULTMASK();
|
||||
ASSERT_TRUE((result & 0x01U) == 1U);
|
||||
|
||||
__enable_fault_irq();
|
||||
result = __get_FAULTMASK();
|
||||
ASSERT_TRUE((result & 0x01U) == 0U);
|
||||
|
||||
__disable_fault_irq();
|
||||
result = __get_FAULTMASK();
|
||||
ASSERT_TRUE((result & 0x01U) == 1U);
|
||||
|
||||
__set_FAULTMASK(orig);
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreFunc_BASEPRI
|
||||
\details
|
||||
- Check if __get_BASEPRI and __set_BASEPRI intrinsic can be used to manipulate BASEPRI.
|
||||
- Check if __set_BASEPRI_MAX intrinsic can be used to manipulate BASEPRI.
|
||||
*/
|
||||
void TC_CoreFunc_BASEPRI(void) {
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
|
||||
|
||||
uint32_t orig = __get_BASEPRI();
|
||||
|
||||
uint32_t basepri = ~orig & 0x80U;
|
||||
__set_BASEPRI(basepri);
|
||||
uint32_t result = __get_BASEPRI();
|
||||
|
||||
ASSERT_TRUE(result == basepri);
|
||||
|
||||
__set_BASEPRI(orig);
|
||||
|
||||
__set_BASEPRI_MAX(basepri);
|
||||
result = __get_BASEPRI();
|
||||
|
||||
ASSERT_TRUE(result == basepri);
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreFunc_FPUType
|
||||
\details
|
||||
Check SCB_GetFPUType returns information.
|
||||
*/
|
||||
void TC_CoreFunc_FPUType(void) {
|
||||
uint32_t fpuType = SCB_GetFPUType();
|
||||
#if defined(__FPU_PRESENT) && (__FPU_PRESENT != 0)
|
||||
ASSERT_TRUE(fpuType > 0U);
|
||||
#else
|
||||
ASSERT_TRUE(fpuType == 0U);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreFunc_FPSCR
|
||||
\details
|
||||
- Check if __get_FPSCR and __set_FPSCR intrinsics can be used
|
||||
*/
|
||||
void TC_CoreFunc_FPSCR(void) {
|
||||
uint32_t fpscr = __get_FPSCR();
|
||||
__ISB();
|
||||
__DSB();
|
||||
|
||||
__set_FPSCR(~fpscr);
|
||||
__ISB();
|
||||
__DSB();
|
||||
|
||||
uint32_t result = __get_FPSCR();
|
||||
|
||||
__set_FPSCR(fpscr);
|
||||
|
||||
#if (defined (__FPU_USED ) && (__FPU_USED == 1U))
|
||||
ASSERT_TRUE(result != fpscr);
|
||||
#else
|
||||
ASSERT_TRUE(result == 0U);
|
||||
#endif
|
||||
}
|
||||
@@ -0,0 +1,821 @@
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Name: CV_CoreInstr.c
|
||||
* Purpose: CMSIS CORE validation tests implementation
|
||||
*-----------------------------------------------------------------------------
|
||||
* Copyright (c) 2017 - 2021 Arm Limited. All rights reserved.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
#include "CV_Framework.h"
|
||||
#include "cmsis_cv.h"
|
||||
|
||||
#if defined(__CORTEX_M)
|
||||
#elif defined(__CORTEX_A)
|
||||
#include "irq_ctrl.h"
|
||||
#else
|
||||
#error __CORTEX_M or __CORTEX_A must be defined!
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Test implementation
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Test cases
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreInstr_NOP
|
||||
\details
|
||||
- Check if __NOP instrinsic is available
|
||||
- No real assertion is deployed, just a compile time check.
|
||||
*/
|
||||
void TC_CoreInstr_NOP (void) {
|
||||
__NOP();
|
||||
ASSERT_TRUE(1U == 1U);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreInstr_SEV
|
||||
\details
|
||||
- Check if __SEV instrinsic is available
|
||||
- No real assertion is deployed, just a compile time check.
|
||||
*/
|
||||
void TC_CoreInstr_SEV (void) {
|
||||
__SEV();
|
||||
ASSERT_TRUE(1U == 1U);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreInstr_BKPT
|
||||
\details
|
||||
- Check if __BKPT instrinsic is available
|
||||
- No real assertion is deployed, just a compile time check.
|
||||
*/
|
||||
void TC_CoreInstr_BKPT (void) {
|
||||
__BKPT(0xABU);
|
||||
ASSERT_TRUE(1U == 1U);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreInstr_ISB
|
||||
\details
|
||||
- Check if __ISB instrinsic is available
|
||||
- No real assertion is deployed, just a compile time check.
|
||||
*/
|
||||
void TC_CoreInstr_ISB (void) {
|
||||
__ISB();
|
||||
ASSERT_TRUE(1U == 1U);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreInstr_DSB
|
||||
\details
|
||||
- Check if __DSB instrinsic is available
|
||||
- No real assertion is deployed, just a compile time check.
|
||||
*/
|
||||
void TC_CoreInstr_DSB (void) {
|
||||
__DSB();
|
||||
ASSERT_TRUE(1U == 1U);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreInstr_DMB
|
||||
\details
|
||||
- Check if __DNB instrinsic is available
|
||||
- No real assertion is deployed, just a compile time check.
|
||||
*/
|
||||
void TC_CoreInstr_DMB (void) {
|
||||
__DMB();
|
||||
ASSERT_TRUE(1U == 1U);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreInstr_WFI
|
||||
\details
|
||||
- Check if __WFI instrinsic is available
|
||||
- No real assertion is deployed, just a compile time check.
|
||||
*/
|
||||
void TC_CoreInstr_WFI (void) {
|
||||
__WFI();
|
||||
ASSERT_TRUE(1U == 1U);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreInstr_WFE
|
||||
\details
|
||||
- Check if __WFE instrinsic is available
|
||||
- No real assertion is deployed, just a compile time check.
|
||||
*/
|
||||
void TC_CoreInstr_WFE (void) {
|
||||
__WFE();
|
||||
ASSERT_TRUE(1U == 1U);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreInstr_REV
|
||||
\details
|
||||
- Check if __REV instrinsic swaps all bytes in a word.
|
||||
*/
|
||||
void TC_CoreInstr_REV (void) {
|
||||
volatile uint32_t op1_u32;
|
||||
volatile uint32_t res_u32;
|
||||
|
||||
op1_u32 = 0x47110815U;
|
||||
res_u32 = __REV(op1_u32);
|
||||
ASSERT_TRUE(res_u32 == 0x15081147U);
|
||||
|
||||
op1_u32 = 0x80000000U;
|
||||
res_u32 = __REV(op1_u32);
|
||||
ASSERT_TRUE(res_u32 == 0x00000080U);
|
||||
|
||||
op1_u32 = 0x00000080U;
|
||||
res_u32 = __REV(op1_u32);
|
||||
ASSERT_TRUE(res_u32 == 0x80000000U);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreInstr_REV16
|
||||
\details
|
||||
- Check if __REV16 instrinsic swaps the bytes in both halfwords independendly.
|
||||
*/
|
||||
void TC_CoreInstr_REV16(void) {
|
||||
volatile uint32_t op1_u32;
|
||||
volatile uint32_t res_u32;
|
||||
|
||||
op1_u32 = 0x47110815U;
|
||||
res_u32 = __REV16(op1_u32);
|
||||
ASSERT_TRUE(res_u32 == 0x11471508U);
|
||||
|
||||
op1_u32 = 0x00001234U;
|
||||
res_u32 = __REV16(op1_u32);
|
||||
ASSERT_TRUE(res_u32 == 0x00003412U);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreInstr_REVSH
|
||||
\details
|
||||
- Check if __REVSH instrinsic swaps bytes in a signed halfword keeping the sign.
|
||||
*/
|
||||
void TC_CoreInstr_REVSH(void) {
|
||||
volatile int16_t value = 0U;
|
||||
int16_t result = 0U;
|
||||
|
||||
value = 0x4711;
|
||||
result = __REVSH(value);
|
||||
ASSERT_TRUE(result == 0x1147);
|
||||
|
||||
value = (int16_t)0x8000;
|
||||
result = __REVSH(value);
|
||||
ASSERT_TRUE(result == 0x0080);
|
||||
|
||||
value = 0x0080;
|
||||
result = __REVSH(value);
|
||||
ASSERT_TRUE(result == (int16_t)0x8000);
|
||||
|
||||
value = -0x1234;
|
||||
result = __REVSH(value);
|
||||
ASSERT_TRUE(result == (int16_t)0xcced);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreInstr_RBIT
|
||||
\details
|
||||
- Check if __RBIT instrinsic revserses the bit order of arbitrary words.
|
||||
*/
|
||||
void TC_CoreInstr_RBIT (void) {
|
||||
volatile uint32_t value = 0U;
|
||||
uint32_t result = 0U;
|
||||
|
||||
value = 0xAAAAAAAAU;
|
||||
result = __RBIT(value);
|
||||
ASSERT_TRUE(result == 0x55555555U);
|
||||
|
||||
value = 0x55555555U;
|
||||
result = __RBIT(value);
|
||||
ASSERT_TRUE(result == 0xAAAAAAAAU);
|
||||
|
||||
value = 0x00000001U;
|
||||
result = __RBIT(value);
|
||||
ASSERT_TRUE(result == 0x80000000U);
|
||||
|
||||
value = 0x80000000U;
|
||||
result = __RBIT(value);
|
||||
ASSERT_TRUE(result == 0x00000001U);
|
||||
|
||||
value = 0xDEADBEEFU;
|
||||
result = __RBIT(value);
|
||||
ASSERT_TRUE(result == 0xF77DB57BU);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreInstr_ROR
|
||||
\details
|
||||
- Check if __ROR instrinsic moves all bits as expected.
|
||||
*/
|
||||
void TC_CoreInstr_ROR(void) {
|
||||
volatile uint32_t value = 0U;
|
||||
uint32_t result = 0U;
|
||||
|
||||
value = 0x00000001U;
|
||||
result = __ROR(value, 1U);
|
||||
ASSERT_TRUE(result == 0x80000000U);
|
||||
|
||||
value = 0x80000000U;
|
||||
result = __ROR(value, 1U);
|
||||
ASSERT_TRUE(result == 0x40000000U);
|
||||
|
||||
value = 0x40000000U;
|
||||
result = __ROR(value, 30U);
|
||||
ASSERT_TRUE(result == 0x00000001U);
|
||||
|
||||
value = 0x00000001U;
|
||||
result = __ROR(value, 32U);
|
||||
ASSERT_TRUE(result == 0x00000001U);
|
||||
|
||||
value = 0x08154711U;
|
||||
result = __ROR(value, 8U);
|
||||
ASSERT_TRUE(result == 0x11081547U);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreInstr_CLZ
|
||||
\details
|
||||
- Check if __CLZ instrinsic counts leading zeros.
|
||||
*/
|
||||
void TC_CoreInstr_CLZ (void) {
|
||||
volatile uint32_t value = 0U;
|
||||
uint32_t result = 0U;
|
||||
|
||||
value = 0x00000000U;
|
||||
result = __CLZ(value);
|
||||
ASSERT_TRUE(result == 32);
|
||||
|
||||
value = 0x00000001U;
|
||||
result = __CLZ(value);
|
||||
ASSERT_TRUE(result == 31);
|
||||
|
||||
value = 0x40000000U;
|
||||
result = __CLZ(value);
|
||||
ASSERT_TRUE(result == 1);
|
||||
|
||||
value = 0x80000000U;
|
||||
result = __CLZ(value);
|
||||
ASSERT_TRUE(result == 0);
|
||||
|
||||
value = 0xFFFFFFFFU;
|
||||
result = __CLZ(value);
|
||||
ASSERT_TRUE(result == 0);
|
||||
|
||||
value = 0x80000001U;
|
||||
result = __CLZ(value);
|
||||
ASSERT_TRUE(result == 0);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreInstr_SSAT
|
||||
\details
|
||||
- Check if __SSAT instrinsic saturates signed integer values.
|
||||
*/
|
||||
void TC_CoreInstr_SSAT (void) {
|
||||
volatile int32_t value = 0;
|
||||
int32_t result = 0;
|
||||
|
||||
value = INT32_MAX;
|
||||
result = __SSAT(value, 32U);
|
||||
ASSERT_TRUE(result == INT32_MAX);
|
||||
|
||||
value = INT32_MAX;
|
||||
result = __SSAT(value, 16U);
|
||||
ASSERT_TRUE(result == INT16_MAX);
|
||||
|
||||
value = INT32_MAX;
|
||||
result = __SSAT(value, 8U);
|
||||
ASSERT_TRUE(result == INT8_MAX);
|
||||
|
||||
value = INT32_MAX;
|
||||
result = __SSAT(value, 1U);
|
||||
ASSERT_TRUE(result == 0);
|
||||
|
||||
value = INT32_MIN;
|
||||
result = __SSAT(value, 32U);
|
||||
ASSERT_TRUE(result == INT32_MIN);
|
||||
|
||||
value = INT32_MIN;
|
||||
result = __SSAT(value, 16U);
|
||||
ASSERT_TRUE(result == INT16_MIN);
|
||||
|
||||
value = INT32_MIN;
|
||||
result = __SSAT(value, 8U);
|
||||
ASSERT_TRUE(result == INT8_MIN);
|
||||
|
||||
value = INT32_MIN;
|
||||
result = __SSAT(value, 1U);
|
||||
ASSERT_TRUE(result == -1);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreInstr_USAT
|
||||
\details
|
||||
- Check if __USAT instrinsic saturates unsigned integer values.
|
||||
*/
|
||||
void TC_CoreInstr_USAT (void) {
|
||||
volatile int32_t value = 0U;
|
||||
uint32_t result = 0U;
|
||||
|
||||
value = INT32_MAX;
|
||||
result = __USAT(value, 31U);
|
||||
ASSERT_TRUE(result == (UINT32_MAX >> 1U));
|
||||
|
||||
value = INT32_MAX;
|
||||
result = __USAT(value, 16U);
|
||||
ASSERT_TRUE(result == UINT16_MAX);
|
||||
|
||||
value = INT32_MAX;
|
||||
result = __USAT(value, 8U);
|
||||
ASSERT_TRUE(result == UINT8_MAX);
|
||||
|
||||
value = INT32_MAX;
|
||||
result = __USAT(value, 0U);
|
||||
ASSERT_TRUE(result == 0U);
|
||||
|
||||
value = INT32_MIN;
|
||||
result = __USAT(value, 31U);
|
||||
ASSERT_TRUE(result == 0U);
|
||||
|
||||
value = INT32_MIN;
|
||||
result = __USAT(value, 16U);
|
||||
ASSERT_TRUE(result == 0U);
|
||||
|
||||
value = INT32_MIN;
|
||||
result = __USAT(value, 8U);
|
||||
ASSERT_TRUE(result == 0U);
|
||||
|
||||
value = INT32_MIN;
|
||||
result = __USAT(value, 0U);
|
||||
ASSERT_TRUE(result == 0U);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_CoreInstr_RRX
|
||||
\details
|
||||
- Check if __USAT instrinsic saturates unsigned integer values.
|
||||
*/
|
||||
void TC_CoreInstr_RRX (void) {
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
|
||||
|
||||
volatile uint32_t value = 0U;
|
||||
volatile uint32_t result = 0U;
|
||||
volatile xPSR_Type xPSR;
|
||||
|
||||
value = 0x80000002;
|
||||
xPSR.w = __get_xPSR();
|
||||
result = __RRX(value);
|
||||
ASSERT_TRUE(result == (0x40000001 | (uint32_t)(xPSR.b.C << 31)));
|
||||
#endif
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \
|
||||
(defined(__CORTEX_A) ) )
|
||||
|
||||
/// Exclusive byte value
|
||||
static volatile uint8_t TC_CoreInstr_LoadStoreExclusive_byte = 0x47U;
|
||||
|
||||
/// Exclusive halfword value
|
||||
static volatile uint16_t TC_CoreInstr_LoadStoreExclusive_hword = 0x0815U;
|
||||
|
||||
/// Exclusive word value
|
||||
static volatile uint32_t TC_CoreInstr_LoadStoreExclusive_word = 0x08154711U;
|
||||
|
||||
/**
|
||||
\brief Interrupt function for TC_CoreInstr_LoadStoreExclusive
|
||||
\details
|
||||
The interrupt manipulates all the global data
|
||||
which disrupts the exclusive sequences in the test
|
||||
*/
|
||||
static void TC_CoreInstr_LoadStoreExclusive_IRQHandler(void) {
|
||||
|
||||
const uint8_t b = __LDREXB(&TC_CoreInstr_LoadStoreExclusive_byte);
|
||||
__STREXB((uint8_t)~b, &TC_CoreInstr_LoadStoreExclusive_byte);
|
||||
|
||||
const uint16_t hw = __LDREXH(&TC_CoreInstr_LoadStoreExclusive_hword);
|
||||
__STREXH((uint16_t)~hw, &TC_CoreInstr_LoadStoreExclusive_hword);
|
||||
|
||||
const uint32_t w = __LDREXW(&TC_CoreInstr_LoadStoreExclusive_word);
|
||||
__STREXW((uint32_t)~w, &TC_CoreInstr_LoadStoreExclusive_word);
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Helper function for TC_CoreInstr_LoadStoreExclusive to enable test interrupt.
|
||||
\details
|
||||
This helper function implements interrupt enabling according to target
|
||||
architecture, i.e. Cortex-A or Cortex-M.
|
||||
*/
|
||||
static void TC_CoreInstr_LoadStoreExclusive_IRQEnable(void) {
|
||||
#if defined(__CORTEX_M)
|
||||
TST_IRQHandler = TC_CoreInstr_LoadStoreExclusive_IRQHandler;
|
||||
NVIC_EnableIRQ(Interrupt0_IRQn);
|
||||
#elif defined(__CORTEX_A)
|
||||
IRQ_SetHandler(SGI0_IRQn, TC_CoreInstr_LoadStoreExclusive_IRQHandler);
|
||||
IRQ_Enable(SGI0_IRQn);
|
||||
#else
|
||||
#error __CORTEX_M or __CORTEX_A must be defined!
|
||||
#endif
|
||||
__enable_irq();
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Helper function for TC_CoreInstr_LoadStoreExclusive to set test interrupt pending.
|
||||
\details
|
||||
This helper function implements set pending the test interrupt according to target
|
||||
architecture, i.e. Cortex-A or Cortex-M.
|
||||
*/
|
||||
static void TC_CoreInstr_LoadStoreExclusive_IRQPend(void) {
|
||||
#if defined(__CORTEX_M)
|
||||
NVIC_SetPendingIRQ(Interrupt0_IRQn);
|
||||
#elif defined(__CORTEX_A)
|
||||
IRQ_SetPending(SGI0_IRQn);
|
||||
#else
|
||||
#error __CORTEX_M or __CORTEX_A must be defined!
|
||||
#endif
|
||||
for(uint32_t i = 10U; i > 0U; --i) {}
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Helper function for TC_CoreInstr_LoadStoreExclusive to disable test interrupt.
|
||||
\details
|
||||
This helper function implements interrupt disabling according to target
|
||||
architecture, i.e. Cortex-A or Cortex-M.
|
||||
*/
|
||||
static void TC_CoreInstr_LoadStoreExclusive_IRQDisable(void) {
|
||||
__disable_irq();
|
||||
#if defined(__CORTEX_M)
|
||||
NVIC_DisableIRQ(Interrupt0_IRQn);
|
||||
TST_IRQHandler = NULL;
|
||||
#elif defined(__CORTEX_A)
|
||||
IRQ_Disable(SGI0_IRQn);
|
||||
IRQ_SetHandler(SGI0_IRQn, NULL);
|
||||
#else
|
||||
#error __CORTEX_M or __CORTEX_A must be defined!
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
\brief Test case: TC_CoreInstr_LoadStoreExclusive
|
||||
\details
|
||||
Checks exclusive load and store instructions:
|
||||
- LDREXB, LDREXH, LDREXW
|
||||
- STREXB, STREXH, STREXW
|
||||
- CLREX
|
||||
*/
|
||||
void TC_CoreInstr_LoadStoreExclusive (void) {
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \
|
||||
(defined(__CORTEX_A) ) )
|
||||
uint8_t u8, u8Inv;
|
||||
uint16_t u16, u16Inv;
|
||||
uint32_t u32, u32Inv;
|
||||
uint32_t result;
|
||||
|
||||
/* 1. Test exclusives without interruption */
|
||||
u8 = __LDREXB(&TC_CoreInstr_LoadStoreExclusive_byte);
|
||||
ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreExclusive_byte);
|
||||
|
||||
result = __STREXB(u8+1U, &TC_CoreInstr_LoadStoreExclusive_byte);
|
||||
ASSERT_TRUE(result == 0U);
|
||||
ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_byte == u8+1U);
|
||||
|
||||
u16 = __LDREXH(&TC_CoreInstr_LoadStoreExclusive_hword);
|
||||
ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreExclusive_hword);
|
||||
|
||||
result = __STREXH(u16+1U, &TC_CoreInstr_LoadStoreExclusive_hword);
|
||||
ASSERT_TRUE(result == 0U);
|
||||
ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_hword == u16+1U);
|
||||
|
||||
u32 = __LDREXW(&TC_CoreInstr_LoadStoreExclusive_word);
|
||||
ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreExclusive_word);
|
||||
|
||||
result = __STREXW(u32+1U, &TC_CoreInstr_LoadStoreExclusive_word);
|
||||
ASSERT_TRUE(result == 0U);
|
||||
ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_word == u32+1U);
|
||||
|
||||
/* 2. Test exclusives with clear */
|
||||
u8 = __LDREXB(&TC_CoreInstr_LoadStoreExclusive_byte);
|
||||
ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreExclusive_byte);
|
||||
|
||||
__CLREX();
|
||||
|
||||
result = __STREXB(u8+1U, &TC_CoreInstr_LoadStoreExclusive_byte);
|
||||
ASSERT_TRUE(result == 1U);
|
||||
ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_byte == u8);
|
||||
|
||||
u16 = __LDREXH(&TC_CoreInstr_LoadStoreExclusive_hword);
|
||||
ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreExclusive_hword);
|
||||
|
||||
__CLREX();
|
||||
|
||||
result = __STREXH(u16+1U, &TC_CoreInstr_LoadStoreExclusive_hword);
|
||||
ASSERT_TRUE(result == 1U);
|
||||
ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_hword == u16);
|
||||
|
||||
u32 = __LDREXW(&TC_CoreInstr_LoadStoreExclusive_word);
|
||||
ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreExclusive_word);
|
||||
|
||||
__CLREX();
|
||||
|
||||
result = __STREXW(u32+1U, &TC_CoreInstr_LoadStoreExclusive_word);
|
||||
ASSERT_TRUE(result == 1U);
|
||||
ASSERT_TRUE(TC_CoreInstr_LoadStoreExclusive_word == u32);
|
||||
|
||||
/* 3. Test exclusives with interruption */
|
||||
TC_CoreInstr_LoadStoreExclusive_IRQEnable();
|
||||
|
||||
u8 = __LDREXB(&TC_CoreInstr_LoadStoreExclusive_byte);
|
||||
ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreExclusive_byte);
|
||||
|
||||
TC_CoreInstr_LoadStoreExclusive_IRQPend();
|
||||
|
||||
result = __STREXB(u8+1U, &TC_CoreInstr_LoadStoreExclusive_byte);
|
||||
ASSERT_TRUE(result == 1U);
|
||||
u8Inv = (uint8_t)~u8;
|
||||
ASSERT_TRUE(u8Inv == TC_CoreInstr_LoadStoreExclusive_byte);
|
||||
|
||||
u16 = __LDREXH(&TC_CoreInstr_LoadStoreExclusive_hword);
|
||||
ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreExclusive_hword);
|
||||
|
||||
TC_CoreInstr_LoadStoreExclusive_IRQPend();
|
||||
|
||||
result = __STREXH(u16+1U, &TC_CoreInstr_LoadStoreExclusive_hword);
|
||||
ASSERT_TRUE(result == 1U);
|
||||
u16Inv = (uint16_t)~u16;
|
||||
ASSERT_TRUE(u16Inv == TC_CoreInstr_LoadStoreExclusive_hword);
|
||||
|
||||
u32 = __LDREXW(&TC_CoreInstr_LoadStoreExclusive_word);
|
||||
ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreExclusive_word);
|
||||
|
||||
TC_CoreInstr_LoadStoreExclusive_IRQPend();
|
||||
|
||||
result = __STREXW(u32+1U, &TC_CoreInstr_LoadStoreExclusive_word);
|
||||
ASSERT_TRUE(result == 1U);
|
||||
u32Inv = (uint32_t)~u32;
|
||||
ASSERT_TRUE(u32Inv == TC_CoreInstr_LoadStoreExclusive_word);
|
||||
|
||||
TC_CoreInstr_LoadStoreExclusive_IRQDisable();
|
||||
#endif
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
|
||||
|
||||
/// byte value unprivileged access
|
||||
static volatile uint8_t TC_CoreInstr_LoadStoreUnpriv_byte = 0x47U;
|
||||
|
||||
/// halfword value unprivileged access
|
||||
static volatile uint16_t TC_CoreInstr_LoadStoreUnpriv_hword = 0x0815U;
|
||||
|
||||
/// word value unprivileged access
|
||||
static volatile uint32_t TC_CoreInstr_LoadStoreUnpriv_word = 0x08154711U;
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Test case: TC_CoreInstr_LoadStoreUnpriv
|
||||
\details
|
||||
Checks load/store unprivileged instructions:
|
||||
- LDRBT, LDRHT, LDRT
|
||||
- STRBT, STRHT, STRT
|
||||
*/
|
||||
void TC_CoreInstr_LoadStoreUnpriv (void) {
|
||||
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
|
||||
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) )
|
||||
uint8_t u8 = 0U;
|
||||
uint16_t u16 = 0U;
|
||||
uint32_t u32 = 0U;
|
||||
|
||||
/* 1. Test without interruption */
|
||||
u8 = __LDRBT(&TC_CoreInstr_LoadStoreUnpriv_byte);
|
||||
ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreUnpriv_byte);
|
||||
|
||||
__STRBT(u8+1U, &TC_CoreInstr_LoadStoreUnpriv_byte);
|
||||
ASSERT_TRUE(TC_CoreInstr_LoadStoreUnpriv_byte == u8+1U);
|
||||
|
||||
u16 = __LDRHT(&TC_CoreInstr_LoadStoreUnpriv_hword);
|
||||
ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreUnpriv_hword);
|
||||
|
||||
__STRHT(u16+1U, &TC_CoreInstr_LoadStoreUnpriv_hword);
|
||||
ASSERT_TRUE(TC_CoreInstr_LoadStoreUnpriv_hword == u16+1U);
|
||||
|
||||
u32 = __LDRT(&TC_CoreInstr_LoadStoreUnpriv_word);
|
||||
ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreUnpriv_word);
|
||||
|
||||
__STRT(u32+1U, &TC_CoreInstr_LoadStoreUnpriv_word);
|
||||
ASSERT_TRUE(TC_CoreInstr_LoadStoreUnpriv_word == u32+1U);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
|
||||
/// byte value unprivileged access
|
||||
static volatile uint8_t TC_CoreInstr_LoadStoreAcquire_byte = 0x47U;
|
||||
|
||||
/// halfword value unprivileged access
|
||||
static volatile uint16_t TC_CoreInstr_LoadStoreAcquire_hword = 0x0815U;
|
||||
|
||||
/// word value unprivileged access
|
||||
static volatile uint32_t TC_CoreInstr_LoadStoreAcquire_word = 0x08154711U;
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Test case: TC_CoreInstr_LoadStoreAquire
|
||||
\details
|
||||
Checks Load-Acquire and Store-Release instructions:
|
||||
- LDAB, LDAH, LDA
|
||||
- STLB, STLH, STL
|
||||
*/
|
||||
void TC_CoreInstr_LoadStoreAcquire (void) {
|
||||
#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
uint8_t u8 = 0U;
|
||||
uint16_t u16 = 0U;
|
||||
uint32_t u32 = 0U;
|
||||
|
||||
/* 1. Test without interruption */
|
||||
u8 = __LDAB(&TC_CoreInstr_LoadStoreAcquire_byte);
|
||||
ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreAcquire_byte);
|
||||
|
||||
__STLB(u8+1U, &TC_CoreInstr_LoadStoreAcquire_byte);
|
||||
ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquire_byte == u8+1U);
|
||||
|
||||
u16 = __LDAH(&TC_CoreInstr_LoadStoreAcquire_hword);
|
||||
ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreAcquire_hword);
|
||||
|
||||
__STLH(u16+1U, &TC_CoreInstr_LoadStoreAcquire_hword);
|
||||
ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquire_hword == u16+1U);
|
||||
|
||||
u32 = __LDA(&TC_CoreInstr_LoadStoreAcquire_word);
|
||||
ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreAcquire_word);
|
||||
|
||||
__STL(u32+1U, &TC_CoreInstr_LoadStoreAcquire_word);
|
||||
ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquire_word == u32+1U);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
|
||||
/// byte value unprivileged access
|
||||
static volatile uint8_t TC_CoreInstr_LoadStoreAcquireExclusive_byte = 0x47U;
|
||||
|
||||
/// halfword value unprivileged access
|
||||
static volatile uint16_t TC_CoreInstr_LoadStoreAcquireExclusive_hword = 0x0815U;
|
||||
|
||||
/// word value unprivileged access
|
||||
static volatile uint32_t TC_CoreInstr_LoadStoreAcquireExclusive_word = 0x08154711U;
|
||||
#endif
|
||||
|
||||
|
||||
/**
|
||||
\brief Test case: TC_CoreInstr_LoadStoreAquire
|
||||
\details
|
||||
Checks Load-Acquire and Store-Release exclusive instructions:
|
||||
- LDAEXB, LDAEXH, LDAEX
|
||||
- STLEXB, STLEXH, STLEX
|
||||
*/
|
||||
void TC_CoreInstr_LoadStoreAcquireExclusive (void) {
|
||||
#if ((defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
|
||||
(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
|
||||
uint8_t u8 = 0U;
|
||||
uint16_t u16 = 0U;
|
||||
uint32_t u32 = 0U;
|
||||
uint32_t result = 0U;
|
||||
|
||||
/* 1. Test without interruption */
|
||||
u8 = __LDAEXB(&TC_CoreInstr_LoadStoreAcquireExclusive_byte);
|
||||
ASSERT_TRUE(u8 == TC_CoreInstr_LoadStoreAcquireExclusive_byte);
|
||||
|
||||
result = __STLEXB(u8+1U, &TC_CoreInstr_LoadStoreAcquireExclusive_byte);
|
||||
ASSERT_TRUE(result == 0U);
|
||||
ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquireExclusive_byte == u8+1U);
|
||||
|
||||
u16 = __LDAEXH(&TC_CoreInstr_LoadStoreAcquireExclusive_hword);
|
||||
ASSERT_TRUE(u16 == TC_CoreInstr_LoadStoreAcquireExclusive_hword);
|
||||
|
||||
result = __STLEXH(u16+1U, &TC_CoreInstr_LoadStoreAcquireExclusive_hword);
|
||||
ASSERT_TRUE(result == 0U);
|
||||
ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquireExclusive_hword == u16+1U);
|
||||
|
||||
u32 = __LDAEX(&TC_CoreInstr_LoadStoreAcquireExclusive_word);
|
||||
ASSERT_TRUE(u32 == TC_CoreInstr_LoadStoreAcquireExclusive_word);
|
||||
|
||||
result = __STLEX(u32+1U, &TC_CoreInstr_LoadStoreAcquireExclusive_word);
|
||||
ASSERT_TRUE(result == 0U);
|
||||
ASSERT_TRUE(TC_CoreInstr_LoadStoreAcquireExclusive_word == u32+1U);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Test case: TC_CoreInstr_UnalignedUint16
|
||||
\details
|
||||
Checks macro functions to access unaligned uint16_t values:
|
||||
- __UNALIGNED_UINT16_READ
|
||||
- __UNALIGNED_UINT16_WRITE
|
||||
*/
|
||||
void TC_CoreInstr_UnalignedUint16(void) {
|
||||
uint8_t buffer[3] = { 0U, 0U, 0U };
|
||||
uint16_t val;
|
||||
|
||||
for(int i=0; i<2; i++) {
|
||||
__UNALIGNED_UINT16_WRITE(&(buffer[i]), 0x4711U);
|
||||
ASSERT_TRUE(buffer[i] == 0x11U);
|
||||
ASSERT_TRUE(buffer[i+1] == 0x47U);
|
||||
ASSERT_TRUE(buffer[(i+2)%3] == 0x00U);
|
||||
|
||||
buffer[i] = 0x12U;
|
||||
buffer[i+1] = 0x46U;
|
||||
|
||||
val = __UNALIGNED_UINT16_READ(&(buffer[i]));
|
||||
ASSERT_TRUE(val == 0x4612U);
|
||||
|
||||
buffer[i] = 0x00U;
|
||||
buffer[i+1] = 0x00U;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Test case: TC_CoreInstr_UnalignedUint32
|
||||
\details
|
||||
Checks macro functions to access unaligned uint32_t values:
|
||||
- __UNALIGNED_UINT32_READ
|
||||
- __UNALIGNED_UINT32_WRITE
|
||||
*/
|
||||
void TC_CoreInstr_UnalignedUint32(void) {
|
||||
uint8_t buffer[7] = { 0U, 0U, 0U, 0U, 0U, 0U, 0U };
|
||||
uint32_t val;
|
||||
|
||||
for(int i=0; i<4; i++) {
|
||||
__UNALIGNED_UINT32_WRITE(&(buffer[i]), 0x08154711UL);
|
||||
ASSERT_TRUE(buffer[i+0] == 0x11U);
|
||||
ASSERT_TRUE(buffer[i+1] == 0x47U);
|
||||
ASSERT_TRUE(buffer[i+2] == 0x15U);
|
||||
ASSERT_TRUE(buffer[i+3] == 0x08U);
|
||||
ASSERT_TRUE(buffer[(i+4)%7] == 0x00U);
|
||||
ASSERT_TRUE(buffer[(i+5)%7] == 0x00U);
|
||||
ASSERT_TRUE(buffer[(i+6)%7] == 0x00U);
|
||||
|
||||
buffer[i+0] = 0x12U;
|
||||
buffer[i+1] = 0x46U;
|
||||
buffer[i+2] = 0x14U;
|
||||
buffer[i+3] = 0x09U;
|
||||
|
||||
val = __UNALIGNED_UINT32_READ(&(buffer[i]));
|
||||
ASSERT_TRUE(val == 0x09144612UL);
|
||||
|
||||
buffer[i+0] = 0x00U;
|
||||
buffer[i+1] = 0x00U;
|
||||
buffer[i+2] = 0x00U;
|
||||
buffer[i+3] = 0x00U;
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,713 @@
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Name: CV_CoreSimd.c
|
||||
* Purpose: CMSIS CORE validation tests implementation
|
||||
*-----------------------------------------------------------------------------
|
||||
* Copyright (c) 2018 Arm Limited. All rights reserved.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
#include "CV_Framework.h"
|
||||
#include "cmsis_cv.h"
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Test implementation
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Test cases
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
\brief Test case: TC_CoreSimd_SatAddSub
|
||||
\details
|
||||
- Check Saturating addition and subtraction:
|
||||
__QADD
|
||||
__QSUB
|
||||
*/
|
||||
void TC_CoreSimd_SatAddSub (void) {
|
||||
#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
|
||||
volatile int32_t op1_s32, op2_s32;
|
||||
volatile int32_t res_s32;
|
||||
|
||||
/* --- __QADD Test ---------------------------------------------- */
|
||||
op1_s32 = (int32_t)0x80000003;
|
||||
op2_s32 = (int32_t)0x00000004;
|
||||
res_s32 = __QADD(op1_s32, op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0x80000007);
|
||||
|
||||
op1_s32 = (int32_t)0x80000000;
|
||||
op2_s32 = (int32_t)0x80000002;
|
||||
res_s32 = __QADD(op1_s32, op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0x80000000);
|
||||
|
||||
/* --- __QSUB Test ---------------------------------------------- */
|
||||
op1_s32 = (int32_t)0x80000003;
|
||||
op2_s32 = (int32_t)0x00000004;
|
||||
res_s32 = __QSUB(op1_s32, op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0x80000000);
|
||||
|
||||
op1_s32 = (int32_t)0x80000003;
|
||||
op2_s32 = (int32_t)0x00000002;
|
||||
res_s32 = __QSUB(op1_s32, op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0x80000001);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Test case: TC_CoreSimd_ParSat16
|
||||
\details
|
||||
- Check Parallel 16-bit saturation:
|
||||
__SSAT16
|
||||
__USAT16
|
||||
*/
|
||||
void TC_CoreSimd_ParSat16 (void) {
|
||||
#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
|
||||
volatile int32_t op1_s32;
|
||||
volatile int32_t res_s32;
|
||||
|
||||
/* --- __SSAT16 Test ---------------------------------------------- */
|
||||
op1_s32 = (int32_t)0x80030168;
|
||||
res_s32 = __SSAT16(op1_s32, 8);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0xFF80007F);
|
||||
|
||||
/* --- __USAT16 Test ---------------------------------------------- */
|
||||
op1_s32 = 0x0030168;
|
||||
res_s32 = __USAT16(op1_s32, 8);
|
||||
ASSERT_TRUE(res_s32 == 0x000300FF);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Test case: TC_CoreSimd_PackUnpack
|
||||
\details
|
||||
- Check Packing and unpacking:
|
||||
__SXTB16
|
||||
__SXTB16_RORn
|
||||
__SXTAB16
|
||||
__SXTAB16__RORn
|
||||
__UXTB16
|
||||
__UXTAB16
|
||||
*/
|
||||
void TC_CoreSimd_PackUnpack (void) {
|
||||
#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
|
||||
volatile int32_t op1_s32, op2_s32;
|
||||
volatile int32_t res_s32;
|
||||
|
||||
/* --- __SXTB16 Test ---------------------------------------------- */
|
||||
op1_s32 = (int32_t)0x80830168;
|
||||
res_s32 = __SXTB16(op1_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0xFF830068);
|
||||
|
||||
/* --- __SXTB16_ROR8 Test ----------------------------------------- */
|
||||
op1_s32 = (int32_t)0x80830168;
|
||||
res_s32 = __SXTB16_RORn(op1_s32, 8);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0xFF800001);
|
||||
|
||||
/* --- __SXTB16_ROR16 Test ---------------------------------------- */
|
||||
op1_s32 = (int32_t)0x80830168;
|
||||
res_s32 = __SXTB16_RORn(op1_s32, 16);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0x68FF83);
|
||||
|
||||
/* --- __SXTB16_ROR24 Test ---------------------------------------- */
|
||||
op1_s32 = (int32_t)0x80830168;
|
||||
res_s32 = __SXTB16_RORn(op1_s32, 24);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0x1FF80);
|
||||
|
||||
/* --- __SXTAB16 Test --------------------------------------------- */
|
||||
op1_s32 = (int32_t)0x000D0008;
|
||||
op2_s32 = (int32_t)0x80830168;
|
||||
res_s32 = __SXTAB16(op1_s32, op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0xFF900070);
|
||||
|
||||
/* --- __SXTAB16__ROR8 Test --------------------------------------- */
|
||||
op1_s32 = (int32_t)0x000A000A;
|
||||
op2_s32 = (int32_t)0x80830168;
|
||||
res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 8);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0xFF8A000B);
|
||||
|
||||
/* --- __SXTAB16__ROR8 Test --------------------------------------- */
|
||||
op1_s32 = (int32_t)0xFFF6FFF6;
|
||||
op2_s32 = (int32_t)0x80830168;
|
||||
res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 8);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0xFF76FFF7);
|
||||
|
||||
/* --- __SXTAB16__ROR16 Test -------------------------------------- */
|
||||
op1_s32 = (int32_t)0xFFF60015;
|
||||
op2_s32 = (int32_t)0x70880168;
|
||||
res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 16);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0x5EFF9D);
|
||||
|
||||
/* --- __SXTAB16__ROR24 Test -------------------------------------- */
|
||||
op1_s32 = (int32_t)0xFFF60015;
|
||||
op2_s32 = (int32_t)0x70880168;
|
||||
res_s32 = __SXTAB16_RORn(op1_s32, op2_s32, 24);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0xFFF70085);
|
||||
|
||||
/* --- __UXTB16 Test ---------------------------------------------- */
|
||||
op1_s32 = (int32_t)0x80830168;
|
||||
res_s32 = __UXTB16(op1_s32);
|
||||
ASSERT_TRUE(res_s32 == 0x00830068);
|
||||
|
||||
/* --- __UXTAB16 Test --------------------------------------------- */
|
||||
op1_s32 = 0x000D0008;
|
||||
op2_s32 = (int32_t)0x80830168;
|
||||
res_s32 = __UXTAB16(op1_s32, op2_s32);
|
||||
ASSERT_TRUE(res_s32 == 0x00900070);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Test case: TC_CoreSimd_ParSel
|
||||
\details
|
||||
- Check Parallel selection:
|
||||
__SEL
|
||||
*/
|
||||
void TC_CoreSimd_ParSel (void) {
|
||||
#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
|
||||
volatile uint32_t res_u32;
|
||||
|
||||
volatile int32_t op1_s32, op2_s32;
|
||||
volatile int32_t res_s32;
|
||||
|
||||
APSR_Type apsr;
|
||||
xPSR_Type xpsr;
|
||||
|
||||
/* --- __SEL Test ---------------------------------------------- */
|
||||
op1_s32 = 0x33221100;
|
||||
op2_s32 = 0x77665544;
|
||||
|
||||
res_s32 = __SADD8(0x80808080, 0x00000000); /* __sadd8 sets APSR.GE = 0x00 */
|
||||
res_u32 = __get_APSR();
|
||||
apsr.w = __get_APSR();
|
||||
ASSERT_TRUE( (res_u32 == apsr.w) );
|
||||
xpsr.w = __get_xPSR();
|
||||
ASSERT_TRUE( (((res_u32 >> 16) & 0x0F) == xpsr.b.GE) );
|
||||
res_s32 = __SEL(op1_s32, op2_s32); /* __sel APSR.GE = 0x00 */
|
||||
ASSERT_TRUE( res_s32 == 0x77665544);
|
||||
|
||||
res_s32 = __SADD8(0x80808000, 0x00000000); /* __sadd8 sets APSR.GE = 0x01 */
|
||||
res_u32 = __get_APSR();
|
||||
apsr.w = __get_APSR();
|
||||
ASSERT_TRUE( (res_u32 == apsr.w) );
|
||||
xpsr.w = __get_xPSR();
|
||||
ASSERT_TRUE( (((res_u32 >> 16) & 0x0F) == xpsr.b.GE) );
|
||||
res_s32 = __SEL(op1_s32, op2_s32); /* __sel APSR.GE = 0x01 */
|
||||
ASSERT_TRUE(res_s32 == 0x77665500);
|
||||
|
||||
res_s32 = __SADD8(0x80800080, 0x00000000); /* __sadd8 sets APSR.GE = 0x02 */
|
||||
res_u32 = __get_APSR();
|
||||
apsr.w = __get_APSR();
|
||||
ASSERT_TRUE( (res_u32 == apsr.w) );
|
||||
xpsr.w = __get_xPSR();
|
||||
ASSERT_TRUE( (((res_u32 >> 16) & 0x0F) == xpsr.b.GE) );
|
||||
res_s32 = __SEL(op1_s32, op2_s32); /* __sel APSR.GE = 0x02 */
|
||||
ASSERT_TRUE(res_s32 == 0x77661144);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Test case: TC_CoreSimd_ParAddSub8
|
||||
\details
|
||||
- Check Parallel 8-bit addition and subtraction:
|
||||
__SADD8 S Signed
|
||||
__SSUB8 Q Signed Saturating
|
||||
__SHADD8 SH Signed Halving
|
||||
__SHSUB8 U Unsigned
|
||||
__QADD8 UQ Unsigned Saturating
|
||||
__QSUB8 UH Unsigned Halving
|
||||
__UADD8
|
||||
__USUB8
|
||||
__UHADD8
|
||||
__UHSUB8
|
||||
__UQADD8
|
||||
__UQSUB8
|
||||
*/
|
||||
void TC_CoreSimd_ParAddSub8 (void) {
|
||||
#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
|
||||
volatile uint32_t op1_u32, op2_u32;
|
||||
volatile uint32_t res_u32;
|
||||
|
||||
volatile int32_t op1_s32, op2_s32;
|
||||
volatile int32_t res_s32;
|
||||
|
||||
/* --- __SADD8 Test ---------------------------------------------- */
|
||||
op1_s32 = (int32_t)0x87858381;
|
||||
op2_s32 = (int32_t)0x08060402;
|
||||
res_s32 = __SADD8(op1_s32, op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0x8F8B8783);
|
||||
|
||||
/* --- __SSUB8 Test ---------------------------------------------- */
|
||||
op1_s32 = (int32_t)0x8F8B8783;
|
||||
op2_s32 = (int32_t)0x08060402;
|
||||
res_s32 = __SSUB8(op1_s32, op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0x87858381);
|
||||
|
||||
/* --- __SHADD8 Test ---------------------------------------------- */
|
||||
op1_s32 = 0x07050302;
|
||||
op2_s32 = 0x08060402;
|
||||
res_s32 = __SHADD8(op1_s32, op2_s32);
|
||||
ASSERT_TRUE(res_s32 == 0x07050302);
|
||||
|
||||
/* --- __SHSUB8 Test ---------------------------------------------- */
|
||||
op1_s32 = (int32_t)0x8F8B8783;
|
||||
op2_s32 = 0x08060402;
|
||||
res_s32 = __SHSUB8(op1_s32, op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0xC3C2C1C0);
|
||||
|
||||
/* --- __QADD8 Test ---------------------------------------------- */
|
||||
op1_s32 = (int32_t)0x8085837F;
|
||||
op2_s32 = (int32_t)0xFF060402;
|
||||
res_s32 = __QADD8(op1_s32, op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0x808B877F);
|
||||
|
||||
/* --- __QSUB8 Test ---------------------------------------------- */
|
||||
op1_s32 = (int32_t)0x808B8783;
|
||||
op2_s32 = (int32_t)0x08060402;
|
||||
res_s32 = __QSUB8(op1_s32, op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0x80858381);
|
||||
|
||||
/* --- __UADD8 Test ---------------------------------------------- */
|
||||
op1_u32 = 0x07050301;
|
||||
op2_u32 = 0x08060402;
|
||||
res_u32 = __UADD8(op1_u32, op2_u32);
|
||||
ASSERT_TRUE(res_u32 == 0x0F0B0703);
|
||||
|
||||
/* --- __USUB8 Test ---------------------------------------------- */
|
||||
op1_u32 = 0x0F0B0703;
|
||||
op2_u32 = 0x08060402;
|
||||
res_u32 = __USUB8(op1_u32, op2_u32);
|
||||
ASSERT_TRUE(res_u32 == 0x07050301);
|
||||
|
||||
/* --- __UHADD8 Test ---------------------------------------------- */
|
||||
op1_u32 = 0x07050302;
|
||||
op2_u32 = 0x08060402;
|
||||
res_u32 = __UHADD8(op1_u32, op2_u32);
|
||||
ASSERT_TRUE(res_u32 == 0x07050302);
|
||||
|
||||
/* --- __UHSUB8 Test ---------------------------------------------- */
|
||||
op1_u32 = 0x0F0B0703;
|
||||
op2_u32 = 0x08060402;
|
||||
res_u32 = __UHSUB8(op1_u32, op2_u32);
|
||||
ASSERT_TRUE(res_u32 == 0x03020100);
|
||||
|
||||
/* --- __UQADD8 Test ---------------------------------------------- */
|
||||
op1_u32 = 0xFF050301;
|
||||
op2_u32 = 0x08060402;
|
||||
res_u32 = __UQADD8(op1_u32, op2_u32);
|
||||
ASSERT_TRUE(res_u32 == 0xFF0B0703);
|
||||
|
||||
/* --- __UQSUB8 Test ---------------------------------------------- */
|
||||
op1_u32 = 0x080B0702;
|
||||
op2_u32 = 0x0F060408;
|
||||
res_u32 = __UQSUB8(op1_u32, op2_u32);
|
||||
ASSERT_TRUE(res_u32 == 0x00050300);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Test case: TC_CoreSimd_AbsDif8
|
||||
\details
|
||||
- Check Sum of 8-bit absolute differences:
|
||||
__USAD8
|
||||
__USADA8
|
||||
*/
|
||||
void TC_CoreSimd_AbsDif8 (void) {
|
||||
#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
|
||||
volatile uint32_t op1_u32, op2_u32, op3_u32;
|
||||
volatile uint32_t res_u32;
|
||||
|
||||
/* --- __USAD8 Test ---------------------------------------------- */
|
||||
op1_u32 = 0x87858381;
|
||||
op2_u32 = 0x08060402;
|
||||
res_u32 = __USAD8(op1_u32, op2_u32);
|
||||
ASSERT_TRUE(res_u32 == 0x000001FC);
|
||||
|
||||
/* --- __USADA8 Test ---------------------------------------------- */
|
||||
op1_u32 = 0x87858381;
|
||||
op2_u32 = 0x08060402;
|
||||
op3_u32 = 0x00008000;
|
||||
res_u32 = __USADA8(op1_u32, op2_u32, op3_u32);
|
||||
ASSERT_TRUE(res_u32 == 0x000081FC);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Test case: TC_CoreSimd_ParAddSub16
|
||||
\details
|
||||
- Check Parallel 16-bit addition and subtraction:
|
||||
__SADD16
|
||||
__SSUB16
|
||||
__SASX
|
||||
__SSAX
|
||||
__SHADD16
|
||||
__SHSUB16
|
||||
__SHASX
|
||||
__SHSAX
|
||||
__QADD16
|
||||
__QSUB16
|
||||
__QASX
|
||||
__QSAX
|
||||
__UADD16
|
||||
__USUB16
|
||||
__UASX
|
||||
__USAX
|
||||
__UHADD16
|
||||
__UHSUB16
|
||||
__UHASX
|
||||
__UHSAX
|
||||
__UQSUB16
|
||||
__UQADD16
|
||||
__UQASX
|
||||
__UQSAX
|
||||
*/
|
||||
void TC_CoreSimd_ParAddSub16 (void) {
|
||||
#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
|
||||
volatile uint32_t op1_u32, op2_u32;
|
||||
volatile uint32_t res_u32;
|
||||
|
||||
volatile int32_t op1_s32, op2_s32;
|
||||
volatile int32_t res_s32;
|
||||
|
||||
/* --- __SADD16 Test ---------------------------------------------- */
|
||||
op1_s32 = (int32_t)0x80038001;
|
||||
op2_s32 = (int32_t)0x00040002;
|
||||
res_s32 = __SADD16(op1_s32, op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0x80078003);
|
||||
|
||||
/* --- __SSUB16 Test ---------------------------------------------- */
|
||||
op1_s32 = (int32_t)0x80078003;
|
||||
op2_s32 = (int32_t)0x00040002;
|
||||
res_s32 = __SSUB16(op1_s32, op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0x80038001);
|
||||
|
||||
/* --- __SASX Test ---------------------------------------------- */
|
||||
op1_s32 = (int32_t)0x80078003;
|
||||
op2_s32 = (int32_t)0x00040002;
|
||||
res_s32 = __SASX(op1_s32, op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0x80097FFF);
|
||||
|
||||
/* --- __SSAX Test ---------------------------------------------- */
|
||||
op1_s32 = (int32_t)0x80038007;
|
||||
op2_s32 = (int32_t)0x00020004;
|
||||
res_s32 = __SSAX(op1_s32, op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0x7FFF8009);
|
||||
|
||||
/* --- __SHADD16 Test ---------------------------------------------- */
|
||||
op1_s32 = (int32_t)0x80038001;
|
||||
op2_s32 = (int32_t)0x00040002;
|
||||
res_s32 = __SHADD16(op1_s32, op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0xC003C001);
|
||||
|
||||
/* --- __SHSUB16 Test ---------------------------------------------- */
|
||||
op1_s32 = (int32_t)0x80078003;
|
||||
op2_s32 = (int32_t)0x00040002;
|
||||
res_s32 = __SHSUB16(op1_s32, op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0xC001C000);
|
||||
|
||||
/* --- __SHASX Test ---------------------------------------------- */
|
||||
op1_s32 = (int32_t)0x80078003;
|
||||
op2_s32 = (int32_t)0x00040002;
|
||||
res_s32 = __SHASX(op1_s32, op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0xC004BFFF);
|
||||
|
||||
/* --- __SHSAX Test ---------------------------------------------- */
|
||||
op1_s32 = (int32_t)0x80038007;
|
||||
op2_s32 = (int32_t)0x00020004;
|
||||
res_s32 = __SHSAX(op1_s32, op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0xBFFFC004);
|
||||
|
||||
/* --- __QADD16 Test ---------------------------------------------- */
|
||||
op1_s32 = (int32_t)0x80038000;
|
||||
op2_s32 = (int32_t)0x00048002;
|
||||
res_s32 = __QADD16(op1_s32, op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0x80078000);
|
||||
|
||||
/* --- __QSUB16 Test ---------------------------------------------- */
|
||||
op1_s32 = (int32_t)0x80038003;
|
||||
op2_s32 = (int32_t)0x00040002;
|
||||
res_s32 = __QSUB16(op1_s32, op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0x80008001);
|
||||
|
||||
/* --- __QASX Test ---------------------------------------------- */
|
||||
op1_s32 = (int32_t)0x80078003;
|
||||
op2_s32 = (int32_t)0x00040002;
|
||||
res_s32 = __QASX(op1_s32, op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0x80098000);
|
||||
|
||||
/* --- __QSAX Test ---------------------------------------------- */
|
||||
op1_s32 = (int32_t)0x80038007;
|
||||
op2_s32 = (int32_t)0x00020004;
|
||||
res_s32 = __QSAX(op1_s32, op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0x80008009);
|
||||
|
||||
/* --- __UADD16 Test ---------------------------------------------- */
|
||||
op1_u32 = 0x00010002;
|
||||
op2_u32 = 0x00020004;
|
||||
res_u32 = __UADD16(op1_u32, op2_u32);
|
||||
ASSERT_TRUE(res_u32 == 0x00030006);
|
||||
|
||||
/* --- __USUB16 Test ---------------------------------------------- */
|
||||
op1_u32 = 0x00030006;
|
||||
op2_u32 = 0x00020004;
|
||||
res_u32 = __USUB16(op1_u32, op2_u32);
|
||||
ASSERT_TRUE(res_u32 == 0x00010002);
|
||||
|
||||
/* --- __UASX Test ---------------------------------------------- */
|
||||
op1_u32 = 0x80078003;
|
||||
op2_u32 = 0x00040002;
|
||||
res_u32 = __UASX(op1_u32, op2_u32);
|
||||
ASSERT_TRUE(res_u32 == 0x80097FFF);
|
||||
|
||||
/* --- __USAX Test ---------------------------------------------- */
|
||||
op1_u32 = 0x80038007;
|
||||
op2_u32 = 0x00020004;
|
||||
res_u32 = __USAX(op1_u32, op2_u32);
|
||||
ASSERT_TRUE(res_u32 == 0x7FFF8009);
|
||||
|
||||
/* --- __UHADD16 Test ---------------------------------------------- */
|
||||
op1_u32 = 0x00010002;
|
||||
op2_u32 = 0x00020004;
|
||||
res_u32 = __UHADD16(op1_u32, op2_u32);
|
||||
ASSERT_TRUE(res_u32 == 0x00010003);
|
||||
|
||||
/* --- __UHSUB16 Test ---------------------------------------------- */
|
||||
op1_u32 = 0x00030006;
|
||||
op2_u32 = 0x00020004;
|
||||
res_u32 = __UHSUB16(op1_u32, op2_u32);
|
||||
ASSERT_TRUE(res_u32 == 0x00000001);
|
||||
|
||||
/* --- __UHASX Test ---------------------------------------------- */
|
||||
op1_u32 = 0x80078003;
|
||||
op2_u32 = 0x00040002;
|
||||
res_u32 = __UHASX(op1_u32, op2_u32);
|
||||
ASSERT_TRUE(res_u32 == 0x40043FFF);
|
||||
|
||||
/* --- __UHSAX Test ---------------------------------------------- */
|
||||
op1_u32 = 0x80038007;
|
||||
op2_u32 = 0x00020004;
|
||||
res_u32 = __UHSAX(op1_u32, op2_u32);
|
||||
ASSERT_TRUE(res_u32 == 0x3FFF4004);
|
||||
|
||||
/* --- __UQADD16 Test ---------------------------------------------- */
|
||||
op1_u32 = 0xFFFE0002;
|
||||
op2_u32 = 0x00020004;
|
||||
res_u32 = __UQADD16(op1_u32, op2_u32);
|
||||
ASSERT_TRUE(res_u32 == 0xFFFF0006);
|
||||
|
||||
/* --- __UQSUB16 Test ---------------------------------------------- */
|
||||
op1_u32 = 0x00020006;
|
||||
op2_u32 = 0x00030004;
|
||||
res_u32 = __UQSUB16(op1_u32, op2_u32);
|
||||
ASSERT_TRUE(res_u32 == 0x00000002);
|
||||
|
||||
/* --- __UQASX Test ---------------------------------------------- */
|
||||
op1_u32 = 0xFFF80003;
|
||||
op2_u32 = 0x00040009;
|
||||
res_u32 = __UQASX(op1_u32, op2_u32);
|
||||
ASSERT_TRUE(res_u32 == 0xFFFF0000);
|
||||
|
||||
/* --- __UQSAX Test ---------------------------------------------- */
|
||||
op1_u32 = 0x0003FFF8;
|
||||
op2_u32 = 0x00090004;
|
||||
res_u32 = __UQSAX(op1_u32, op2_u32);
|
||||
ASSERT_TRUE(res_u32 == 0x0000FFFF);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Test case: TC_CoreSimd_ParMul16
|
||||
\details
|
||||
- Check Parallel 16-bit multiplication:
|
||||
__SMLAD
|
||||
__SMLADX
|
||||
__SMLALD
|
||||
__SMLALDX
|
||||
__SMLSD
|
||||
__SMLSDX
|
||||
__SMLSLD
|
||||
__SMLSLDX
|
||||
__SMUAD
|
||||
__SMUADX
|
||||
__SMUSD
|
||||
__SMUSDX
|
||||
*/
|
||||
void TC_CoreSimd_ParMul16 (void) {
|
||||
#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
|
||||
volatile int32_t op1_s32, op2_s32, op3_s32;
|
||||
volatile int32_t res_s32;
|
||||
|
||||
volatile int64_t op1_s64;
|
||||
volatile int64_t res_s64;
|
||||
|
||||
/* --- __SMLAD Test ---------------------------------------------- */
|
||||
op1_s32 = 0x00030002;
|
||||
op2_s32 = 0x00050004;
|
||||
op3_s32 = 0x20000000;
|
||||
res_s32 = __SMLAD(op1_s32, op2_s32, op3_s32);
|
||||
ASSERT_TRUE(res_s32 == 0x20000017);
|
||||
|
||||
/* --- __SMLADX Test ---------------------------------------------- */
|
||||
op1_s32 = 0x00030002;
|
||||
op2_s32 = 0x00050004;
|
||||
op3_s32 = 0x00000800;
|
||||
res_s32 = __SMLADX(op1_s32, op2_s32, op3_s32);
|
||||
ASSERT_TRUE(res_s32 == 0x00000816);
|
||||
|
||||
/* --- __SMLALD Test ---------------------------------------------- */
|
||||
op1_s32 = 0x00030002;
|
||||
op2_s32 = 0x00050004;
|
||||
op1_s64 = 0x00000000200000000LL;
|
||||
res_s64 = __SMLALD(op1_s32, op2_s32, op1_s64);
|
||||
ASSERT_TRUE(res_s64 == 0x0000000200000017LL);
|
||||
|
||||
/* --- __SMLALDX Test ---------------------------------------------- */
|
||||
op1_s32 = 0x00030002;
|
||||
op2_s32 = 0x00050004;
|
||||
op1_s64 = 0x00000000200000000LL;
|
||||
res_s64 = __SMLALDX(op1_s32, op2_s32, op1_s64);
|
||||
ASSERT_TRUE(res_s64 == 0x0000000200000016LL);
|
||||
|
||||
/* --- __SMLSD Test ---------------------------------------------- */
|
||||
op1_s32 = 0x00030006;
|
||||
op2_s32 = 0x00050004;
|
||||
op3_s32 = 0x00000800;
|
||||
res_s32 = __SMLSD(op1_s32, op2_s32, op3_s32);
|
||||
ASSERT_TRUE(res_s32 == 0x00000809);
|
||||
|
||||
/* --- __SMLSDX Test ---------------------------------------------- */
|
||||
op1_s32 = 0x00030002;
|
||||
op2_s32 = 0x00050004;
|
||||
op3_s32 = 0x00000800;
|
||||
res_s32 = __SMLSDX(op1_s32, op2_s32, op3_s32);
|
||||
ASSERT_TRUE(res_s32 == 0x000007FE);
|
||||
|
||||
/* --- __SMLSLD Test ---------------------------------------------- */
|
||||
op1_s32 = 0x00030006;
|
||||
op2_s32 = 0x00050004;
|
||||
op1_s64 = 0x00000000200000000LL;
|
||||
res_s64 = __SMLSLD(op1_s32, op2_s32, op1_s64);
|
||||
ASSERT_TRUE(res_s64 == 0x0000000200000009LL);
|
||||
|
||||
/* --- __SMLSLDX Test ---------------------------------------------- */
|
||||
op1_s32 = 0x00030006;
|
||||
op2_s32 = 0x00050004;
|
||||
op1_s64 = 0x00000000200000000LL;
|
||||
res_s64 = __SMLSLDX(op1_s32, op2_s32, op1_s64);
|
||||
ASSERT_TRUE(res_s64 == 0x0000000200000012LL);
|
||||
|
||||
/* --- __SMUAD Test ---------------------------------------------- */
|
||||
op1_s32 = 0x00030001;
|
||||
op2_s32 = 0x00040002;
|
||||
res_s32 = __SMUAD(op1_s32,op2_s32);
|
||||
ASSERT_TRUE(res_s32 == 0x0000000E);
|
||||
|
||||
op1_s32 = (int32_t)0xFFFDFFFF;
|
||||
op2_s32 = (int32_t)0x00040002;
|
||||
res_s32 = __SMUAD(op1_s32,op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0xFFFFFFF2);
|
||||
|
||||
/* --- __SMUADX Test ---------------------------------------------- */
|
||||
op1_s32 = 0x00030001;
|
||||
op2_s32 = 0x00040002;
|
||||
res_s32 = __SMUADX(op1_s32,op2_s32);
|
||||
ASSERT_TRUE(res_s32 == 0x0000000A);
|
||||
|
||||
op1_s32 = (int32_t)0xFFFDFFFF;
|
||||
op2_s32 = (int32_t)0x00040002;
|
||||
res_s32 = __SMUADX(op1_s32,op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0xFFFFFFF6);
|
||||
|
||||
/* --- __SMUSD Test ---------------------------------------------- */
|
||||
op1_s32 = (int32_t)0x00030001;
|
||||
op2_s32 = (int32_t)0x00040002;
|
||||
res_s32 = __SMUSD(op1_s32,op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0xFFFFFFF6);
|
||||
|
||||
op1_s32 = (int32_t)0xFFFDFFFF;
|
||||
op2_s32 = (int32_t)0x00040002;
|
||||
res_s32 = __SMUSD(op1_s32,op2_s32);
|
||||
ASSERT_TRUE(res_s32 == 0x0000000A);
|
||||
|
||||
/* --- __SMUSDX Test ---------------------------------------------- */
|
||||
op1_s32 = 0x00030001;
|
||||
op2_s32 = 0x00040002;
|
||||
res_s32 = __SMUSDX(op1_s32,op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0xFFFFFFFE);
|
||||
|
||||
op1_s32 = (int32_t)0xFFFDFFFF;
|
||||
op2_s32 = (int32_t)0x00040002;
|
||||
res_s32 = __SMUSDX(op1_s32,op2_s32);
|
||||
ASSERT_TRUE(res_s32 == (int32_t)0x00000002);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Test case: TC_CoreSimd_Part9
|
||||
\details
|
||||
- Check Packing Halfword:
|
||||
__PKHBT
|
||||
__PKHTB
|
||||
*/
|
||||
void TC_CoreSimd_Pack16 (void) {
|
||||
#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
|
||||
volatile uint32_t op1_u32, op2_u32;
|
||||
volatile uint32_t res_u32;
|
||||
|
||||
/* --- __PKHBT Test ---------------------------------------------- */
|
||||
op1_u32 = 0x00000111;
|
||||
op2_u32 = 0x22200000;
|
||||
res_u32 = __PKHBT(op1_u32, op2_u32, 0);
|
||||
ASSERT_TRUE(res_u32 == 0x22200111);
|
||||
|
||||
op1_u32 = 0x00000111;
|
||||
op2_u32 = 0x22200000;
|
||||
res_u32 = __PKHBT(op1_u32, op2_u32, 4);
|
||||
ASSERT_TRUE(res_u32 == 0x22000111);
|
||||
|
||||
/* --- __PKHTB Test ---------------------------------------------- */
|
||||
op1_u32 = 0x11100000;
|
||||
op2_u32 = 0x00000222;
|
||||
res_u32 = __PKHTB(op1_u32, op2_u32, 0);
|
||||
ASSERT_TRUE(res_u32 == 0x11100222);
|
||||
|
||||
op1_u32 = 0x11100000;
|
||||
op2_u32 = 0x00000222;
|
||||
res_u32 = __PKHTB(op1_u32, op2_u32, 4);
|
||||
ASSERT_TRUE(res_u32 == 0x11100022);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
\brief Test case: TC_CoreSimd_MulAcc32
|
||||
\details
|
||||
- Check Signed Most Significant Word Multiply Accumulate:
|
||||
__SMMLA
|
||||
*/
|
||||
void TC_CoreSimd_MulAcc32 (void) {
|
||||
#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
|
||||
(defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) )
|
||||
volatile int32_t op1_s32, op2_s32, op3_s32;
|
||||
volatile int32_t res_s32;
|
||||
|
||||
/* --- __SMMLA Test ---------------------------------------------- */
|
||||
op1_s32 = 0x00000200;
|
||||
op2_s32 = 0x00000004;
|
||||
op3_s32 = 0x00000100;
|
||||
res_s32 = __SMMLA(op1_s32, op2_s32, op3_s32);
|
||||
ASSERT_TRUE(res_s32 == 0x00000100);
|
||||
|
||||
op1_s32 = 0x40000000;
|
||||
op2_s32 = 0x00000010;
|
||||
op3_s32 = 0x00000300;
|
||||
res_s32 = __SMMLA(op1_s32, op2_s32, op3_s32);
|
||||
ASSERT_TRUE(res_s32 == 0x00000304);
|
||||
#endif
|
||||
}
|
||||
@@ -0,0 +1,104 @@
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Name: cv_framework.c
|
||||
* Purpose: Test framework entry point
|
||||
*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2017 ARM Limited. All rights reserved.
|
||||
*----------------------------------------------------------------------------*/
|
||||
#include "CV_Framework.h"
|
||||
#include "cmsis_cv.h"
|
||||
|
||||
/* Prototypes */
|
||||
void ts_cmsis_cv(void);
|
||||
void closeDebug(void);
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\defgroup framework_funcs Framework Functions
|
||||
\brief Functions in the Framework software component
|
||||
\details
|
||||
|
||||
@{
|
||||
*/
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Close the debug session.
|
||||
\details
|
||||
Debug session dead end - debug script should close session here.
|
||||
*/
|
||||
void closeDebug(void) {
|
||||
__NOP();
|
||||
// Test completed
|
||||
}
|
||||
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
|
||||
/**
|
||||
\brief This is CORE Validation test suite.
|
||||
\details
|
||||
Program flow:
|
||||
-# Test report statistics is initialized
|
||||
-# Test report headers are written to the standard output
|
||||
-# All defined test cases are executed:
|
||||
- Test case statistics is initialized
|
||||
- Test case report header is written to the standard output
|
||||
- Test case is executed
|
||||
- Test case results are written to the standard output
|
||||
- Test case report footer is written to the standard output
|
||||
- Test case is closed
|
||||
-# Test report footer is written to the standard output
|
||||
-# Debug session ends in dead loop
|
||||
*/
|
||||
void ts_cmsis_cv () {
|
||||
const char *fn;
|
||||
uint32_t tc, no;
|
||||
(void)ritf.Init (); /* Init test report */
|
||||
(void)ritf.Open (ts.ReportTitle, /* Write test report title */
|
||||
ts.Date, /* Write compilation date */
|
||||
ts.Time, /* Write compilation time */
|
||||
ts.FileName); /* Write module file name */
|
||||
|
||||
/* Execute all test cases */
|
||||
for (tc = 0; tc < ts.NumOfTC; tc++) {
|
||||
no = ts.TCBaseNum+tc; /* Test case number */
|
||||
fn = ts.TC[tc].TFName; /* Test function name string */
|
||||
(void)ritf.Open_TC (no, fn); /* Open test case #(Base + TC) */
|
||||
if (ts.TC[tc].en != 0U) {
|
||||
ts.TC[tc].TestFunc(); /* Execute test case if enabled */
|
||||
}
|
||||
(void)ritf.Close_TC (); /* Close test case */
|
||||
}
|
||||
(void)ritf.Close (); /* Close test report */
|
||||
|
||||
closeDebug(); /* Close debug session */
|
||||
}
|
||||
|
||||
/**
|
||||
\brief This is the entry point of the test framework.
|
||||
\details
|
||||
Program flow:
|
||||
-# Hardware is first initialized if Init callback function is provided
|
||||
-# Main thread is initialized
|
||||
*/
|
||||
void cmsis_cv (void) {
|
||||
|
||||
/* Init test suite */
|
||||
if (ts.Init != NULL) {
|
||||
ts.Init(); /* Init hardware */
|
||||
}
|
||||
|
||||
ts_cmsis_cv();
|
||||
}
|
||||
|
||||
void cmsis_cv_abort (const char *fn, uint32_t ln, char *desc) {
|
||||
(void)__set_result(fn, ln, FAILED, desc);
|
||||
(void)ritf.Close_TC();
|
||||
(void)ritf.Close();
|
||||
closeDebug();
|
||||
}
|
||||
|
||||
/**
|
||||
@}
|
||||
*/
|
||||
// end of group framework_funcs
|
||||
@@ -0,0 +1,70 @@
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Name: CV_GenTimer.c
|
||||
* Purpose: CMSIS CORE validation tests implementation
|
||||
*-----------------------------------------------------------------------------
|
||||
* Copyright (c) 2017 ARM Limited. All rights reserved.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
#include "CV_Framework.h"
|
||||
#include "cmsis_cv.h"
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Test implementation
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Test cases
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
void TC_GenTimer_CNTFRQ(void) {
|
||||
const uint32_t cntfrq1 = __get_CNTFRQ();
|
||||
__set_CNTFRQ(cntfrq1 + 1U);
|
||||
const uint32_t cntfrq2 = __get_CNTFRQ();
|
||||
|
||||
ASSERT_TRUE((cntfrq1 + 1U) == cntfrq2);
|
||||
|
||||
__set_CNTFRQ(cntfrq1);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
void TC_GenTimer_CNTP_TVAL(void) {
|
||||
const uint32_t cntp_tval1 = __get_CNTP_TVAL();
|
||||
__set_CNTP_TVAL(cntp_tval1 + 1U);
|
||||
const uint32_t cntp_tval2 = __get_CNTP_TVAL();
|
||||
|
||||
ASSERT_TRUE((cntp_tval2 - cntp_tval1) >= 1ULL);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
void TC_GenTimer_CNTP_CTL(void) {
|
||||
static const uint32_t CNTP_CTL_ENABLE = 0x01U;
|
||||
const uint32_t cntp_ctl = __get_CNTP_CTL();
|
||||
const uint32_t cntp_ctl_toggled = (cntp_ctl & (~CNTP_CTL_ENABLE)) | ((~cntp_ctl) & CNTP_CTL_ENABLE);
|
||||
__set_CNTP_CTL(cntp_ctl_toggled);
|
||||
|
||||
const uint32_t cntp_ctl_new = __get_CNTP_CTL();
|
||||
|
||||
ASSERT_TRUE((cntp_ctl_toggled & CNTP_CTL_ENABLE) == (cntp_ctl_new & CNTP_CTL_ENABLE));
|
||||
|
||||
__set_CNTP_CTL(cntp_ctl);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
void TC_GenTimer_CNTPCT(void) {
|
||||
const uint64_t cntpct1 = __get_CNTPCT();
|
||||
for(int i=0; i<10; i++);
|
||||
const uint64_t cntpct2 = __get_CNTPCT();
|
||||
|
||||
ASSERT_TRUE((cntpct2 - cntpct1) <= 120ULL);
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
void TC_GenTimer_CNTP_CVAL(void) {
|
||||
const uint64_t cntp_cval1 = __get_CNTP_CVAL();
|
||||
__set_CNTP_CVAL(cntp_cval1 + 1ULL);
|
||||
const uint64_t cntp_cval2 = __get_CNTP_CVAL();
|
||||
|
||||
ASSERT_TRUE((cntp_cval2 - cntp_cval1) >= 1ULL);
|
||||
}
|
||||
@@ -0,0 +1,121 @@
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Name: CV_MPU_ARMv7.c
|
||||
* Purpose: CMSIS CORE validation tests implementation
|
||||
*-----------------------------------------------------------------------------
|
||||
* Copyright (c) 2017 ARM Limited. All rights reserved.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
#include "CV_Framework.h"
|
||||
#include "cmsis_cv.h"
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Test implementation
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
#if defined(__MPU_PRESENT) && __MPU_PRESENT
|
||||
static void ClearMpu(void) {
|
||||
for(uint32_t i = 0U; i < 8U; ++i) {
|
||||
MPU->RNR = i;
|
||||
MPU->RBAR = 0U;
|
||||
MPU->RASR = 0U;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Test cases
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_MPU_SetClear
|
||||
\details
|
||||
- Check if ARM_MPU_Load correctly loads MPU table to registers.
|
||||
*/
|
||||
void TC_MPU_SetClear(void)
|
||||
{
|
||||
#if defined(__MPU_PRESENT) && __MPU_PRESENT
|
||||
static const ARM_MPU_Region_t table[] = {
|
||||
{ .RBAR = 0U, .RASR = 0U },
|
||||
{ .RBAR = ARM_MPU_RBAR(2U, 0x30000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_128MB) },
|
||||
{ .RBAR = 0x50000000U, .RASR = ARM_MPU_RASR(0U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_64MB) }
|
||||
};
|
||||
|
||||
#define ASSERT_MPU_REGION(rnr, region) \
|
||||
MPU->RNR = rnr; \
|
||||
ASSERT_TRUE((MPU->RBAR & MPU_RBAR_ADDR_Msk) == (region.RBAR & MPU_RBAR_ADDR_Msk)); \
|
||||
ASSERT_TRUE(MPU->RASR == region.RASR)
|
||||
|
||||
ClearMpu();
|
||||
|
||||
ARM_MPU_SetRegion(table[1].RBAR, table[1].RASR);
|
||||
|
||||
ASSERT_MPU_REGION(1U, table[0]);
|
||||
ASSERT_MPU_REGION(2U, table[1]);
|
||||
ASSERT_MPU_REGION(3U, table[0]);
|
||||
|
||||
ARM_MPU_SetRegionEx(5U, table[2].RBAR, table[2].RASR);
|
||||
|
||||
ASSERT_MPU_REGION(4U, table[0]);
|
||||
ASSERT_MPU_REGION(5U, table[2]);
|
||||
ASSERT_MPU_REGION(6U, table[0]);
|
||||
|
||||
ARM_MPU_ClrRegion(5U);
|
||||
|
||||
MPU->RNR = 5U;
|
||||
ASSERT_TRUE((MPU->RASR & MPU_RASR_ENABLE_Msk) == 0U);
|
||||
|
||||
#undef ASSERT_MPU_REGION
|
||||
#endif
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_MPU_Load
|
||||
\details
|
||||
- Check if ARM_MPU_Load correctly loads MPU table to registers.
|
||||
*/
|
||||
void TC_MPU_Load(void)
|
||||
{
|
||||
#if defined(__MPU_PRESENT) && __MPU_PRESENT
|
||||
static const ARM_MPU_Region_t table[] = {
|
||||
{ .RBAR = ARM_MPU_RBAR(0U, 0x10000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_32MB) },
|
||||
{ .RBAR = ARM_MPU_RBAR(1U, 0x20000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_64MB) },
|
||||
{ .RBAR = ARM_MPU_RBAR(2U, 0x30000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_128MB) },
|
||||
{ .RBAR = ARM_MPU_RBAR(3U, 0x40000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_256MB) },
|
||||
{ .RBAR = ARM_MPU_RBAR(4U, 0x50000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_512MB) },
|
||||
{ .RBAR = ARM_MPU_RBAR(5U, 0x60000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_16MB) },
|
||||
{ .RBAR = ARM_MPU_RBAR(6U, 0x70000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_8MB) },
|
||||
{ .RBAR = ARM_MPU_RBAR(7U, 0x80000000U), .RASR = ARM_MPU_RASR(1U, ARM_MPU_AP_FULL, 0U, 0U, 0U, 0U, 0U, ARM_MPU_REGION_SIZE_4MB) }
|
||||
};
|
||||
|
||||
#define ASSERT_MPU_REGION(rnr, table) \
|
||||
MPU->RNR = rnr; \
|
||||
ASSERT_TRUE((MPU->RBAR & MPU_RBAR_ADDR_Msk) == (table[rnr].RBAR & MPU_RBAR_ADDR_Msk)); \
|
||||
ASSERT_TRUE(MPU->RASR == table[rnr].RASR)
|
||||
|
||||
ClearMpu();
|
||||
|
||||
ARM_MPU_Load(&(table[0]), 1U);
|
||||
|
||||
ASSERT_MPU_REGION(0U, table);
|
||||
|
||||
ARM_MPU_Load(&(table[1]), 5U);
|
||||
|
||||
ASSERT_MPU_REGION(0U, table);
|
||||
ASSERT_MPU_REGION(1U, table);
|
||||
ASSERT_MPU_REGION(2U, table);
|
||||
ASSERT_MPU_REGION(3U, table);
|
||||
ASSERT_MPU_REGION(4U, table);
|
||||
ASSERT_MPU_REGION(5U, table);
|
||||
|
||||
ARM_MPU_Load(&(table[6]), 2U);
|
||||
|
||||
ASSERT_MPU_REGION(5U, table);
|
||||
ASSERT_MPU_REGION(6U, table);
|
||||
ASSERT_MPU_REGION(7U, table);
|
||||
|
||||
#undef ASSERT_MPU_REGION
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -0,0 +1,113 @@
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Name: CV_MPU_ARMv7.c
|
||||
* Purpose: CMSIS CORE validation tests implementation
|
||||
*-----------------------------------------------------------------------------
|
||||
* Copyright (c) 2017 ARM Limited. All rights reserved.
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
#include "CV_Framework.h"
|
||||
#include "cmsis_cv.h"
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Test implementation
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
#if defined(__MPU_PRESENT) && __MPU_PRESENT
|
||||
static void ClearMpu(void) {
|
||||
for(uint32_t i = 0U; i < 8U; ++i) {
|
||||
MPU->RNR = i;
|
||||
MPU->RBAR = 0U;
|
||||
MPU->RLAR = 0U;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Test cases
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_MPU_SetClear
|
||||
\details
|
||||
- Check if ARM_MPU_Load correctly loads MPU table to registers.
|
||||
*/
|
||||
void TC_MPU_SetClear(void)
|
||||
{
|
||||
#if defined(__MPU_PRESENT) && __MPU_PRESENT
|
||||
static const ARM_MPU_Region_t table[] = {
|
||||
{ .RBAR = 0U, .RLAR = 0U },
|
||||
{ .RBAR = ARM_MPU_RBAR(0x30000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x38000000U, 0U) }
|
||||
};
|
||||
|
||||
#define ASSERT_MPU_REGION(rnr, region) \
|
||||
MPU->RNR = rnr; \
|
||||
ASSERT_TRUE(MPU->RBAR == region.RBAR); \
|
||||
ASSERT_TRUE(MPU->RLAR == region.RLAR)
|
||||
|
||||
ClearMpu();
|
||||
|
||||
ARM_MPU_SetRegion(2U, table[1].RBAR, table[1].RLAR);
|
||||
|
||||
ASSERT_MPU_REGION(1U, table[0]);
|
||||
ASSERT_MPU_REGION(2U, table[1]);
|
||||
ASSERT_MPU_REGION(3U, table[0]);
|
||||
|
||||
ARM_MPU_ClrRegion(2U);
|
||||
|
||||
MPU->RNR = 2U;
|
||||
ASSERT_TRUE((MPU->RLAR & MPU_RLAR_EN_Msk) == 0U);
|
||||
|
||||
#undef ASSERT_MPU_REGION
|
||||
#endif
|
||||
}
|
||||
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
\brief Test case: TC_MPU_Load
|
||||
\details
|
||||
- Check if ARM_MPU_Load correctly loads MPU table to registers.
|
||||
*/
|
||||
void TC_MPU_Load(void)
|
||||
{
|
||||
#if defined(__MPU_PRESENT) && __MPU_PRESENT
|
||||
static const ARM_MPU_Region_t table[] = {
|
||||
{ .RBAR = ARM_MPU_RBAR(0x10000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x18000000U, 0U) },
|
||||
{ .RBAR = ARM_MPU_RBAR(0x20000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x27000000U, 0U) },
|
||||
{ .RBAR = ARM_MPU_RBAR(0x30000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x36000000U, 0U) },
|
||||
{ .RBAR = ARM_MPU_RBAR(0x40000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x45000000U, 0U) },
|
||||
{ .RBAR = ARM_MPU_RBAR(0x50000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x54000000U, 0U) },
|
||||
{ .RBAR = ARM_MPU_RBAR(0x60000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x63000000U, 0U) },
|
||||
{ .RBAR = ARM_MPU_RBAR(0x70000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x72000000U, 0U) },
|
||||
{ .RBAR = ARM_MPU_RBAR(0x80000000U, 0U, 1U, 1U, 1U), .RLAR = ARM_MPU_RLAR(0x31000000U, 0U) }
|
||||
};
|
||||
|
||||
#define ASSERT_MPU_REGION(rnr, table) \
|
||||
MPU->RNR = rnr; \
|
||||
ASSERT_TRUE(MPU->RBAR == table[rnr].RBAR); \
|
||||
ASSERT_TRUE(MPU->RLAR == table[rnr].RLAR)
|
||||
|
||||
ClearMpu();
|
||||
|
||||
ARM_MPU_Load(0U, &(table[0]), 1U);
|
||||
|
||||
ASSERT_MPU_REGION(0U, table);
|
||||
|
||||
ARM_MPU_Load(1U, &(table[1]), 5U);
|
||||
|
||||
ASSERT_MPU_REGION(0U, table);
|
||||
ASSERT_MPU_REGION(1U, table);
|
||||
ASSERT_MPU_REGION(2U, table);
|
||||
ASSERT_MPU_REGION(3U, table);
|
||||
ASSERT_MPU_REGION(4U, table);
|
||||
ASSERT_MPU_REGION(5U, table);
|
||||
|
||||
ARM_MPU_Load(6U, &(table[6]), 2U);
|
||||
|
||||
ASSERT_MPU_REGION(5U, table);
|
||||
ASSERT_MPU_REGION(6U, table);
|
||||
ASSERT_MPU_REGION(7U, table);
|
||||
|
||||
#undef ASSERT_MPU_REGION
|
||||
#endif
|
||||
}
|
||||
@@ -0,0 +1,393 @@
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Name: cv_report.c
|
||||
* Purpose: Report statistics and layout implementation
|
||||
*-----------------------------------------------------------------------------
|
||||
* Copyright (c) 2017 - 2018 Arm Limited. All rights reserved.
|
||||
*----------------------------------------------------------------------------*/
|
||||
#include "CV_Report.h"
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
|
||||
TEST_REPORT test_report;
|
||||
static AS_STAT current_assertions; /* Current test case assertions statistics */
|
||||
#define TAS (&test_report.assertions) /* Total assertions */
|
||||
#define CAS (¤t_assertions) /* Current assertions */
|
||||
|
||||
#ifdef DISABLE_SEMIHOSTING
|
||||
#if defined (__CC_ARM)
|
||||
#pragma import __use_no_semihosting
|
||||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
__ASM(".global __use_no_semihosting");
|
||||
#endif
|
||||
#define PRINT(x)
|
||||
#define FLUSH()
|
||||
void _sys_exit(int return_code) {}
|
||||
#else
|
||||
#define PRINT(x) MsgPrint x
|
||||
#define FLUSH() MsgFlush()
|
||||
#endif // DISABLE_SEMIHOSTING
|
||||
|
||||
static uint8_t Passed[] = "PASSED";
|
||||
static uint8_t Warning[] = "WARNING";
|
||||
static uint8_t Failed[] = "FAILED";
|
||||
static uint8_t NotExe[] = "NOT EXECUTED";
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Test report function prototypes
|
||||
*----------------------------------------------------------------------------*/
|
||||
static BOOL tr_Init (void);
|
||||
static BOOL tc_Init (void);
|
||||
static uint8_t *tr_Eval (void);
|
||||
static uint8_t *tc_Eval (void);
|
||||
static BOOL StatCount (TC_RES res);
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Printer function prototypes
|
||||
*----------------------------------------------------------------------------*/
|
||||
static void MsgPrint (const char *msg, ...);
|
||||
static void MsgFlush (void);
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Assert interface function prototypes
|
||||
*----------------------------------------------------------------------------*/
|
||||
static BOOL As_File_Result (TC_RES res);
|
||||
static BOOL As_File_Dbgi (TC_RES res, const char *fn, uint32_t ln, char *desc);
|
||||
|
||||
TC_ITF tcitf = {
|
||||
As_File_Result,
|
||||
As_File_Dbgi,
|
||||
};
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Test report interface function prototypes
|
||||
*----------------------------------------------------------------------------*/
|
||||
BOOL tr_File_Init (void);
|
||||
BOOL tr_File_Open (const char *title, const char *date, const char *time, const char *fn);
|
||||
BOOL tr_File_Close (void);
|
||||
BOOL tc_File_Open (uint32_t num, const char *fn);
|
||||
BOOL tc_File_Close (void);
|
||||
|
||||
REPORT_ITF ritf = {
|
||||
tr_File_Init,
|
||||
tr_File_Open,
|
||||
tr_File_Close,
|
||||
tc_File_Open,
|
||||
tc_File_Close
|
||||
};
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Init test report
|
||||
*----------------------------------------------------------------------------*/
|
||||
BOOL tr_File_Init (void) {
|
||||
return (tr_Init());
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Open test report
|
||||
*----------------------------------------------------------------------------*/
|
||||
#if (PRINT_XML_REPORT==1)
|
||||
BOOL tr_File_Open (const char *title, const char *date, const char *time, const char *fn) {
|
||||
PRINT(("<?xml version=\"1.0\"?>\n"));
|
||||
PRINT(("<?xml-stylesheet href=\"TR_Style.xsl\" type=\"text/xsl\" ?>\n"));
|
||||
PRINT(("<report>\n"));
|
||||
PRINT(("<test>\n"));
|
||||
PRINT(("<title>%s</title>\n", title));
|
||||
PRINT(("<date>%s</date>\n", date));
|
||||
PRINT(("<time>%s</time>\n", time));
|
||||
PRINT(("<file>%s</file>\n", fn));
|
||||
PRINT(("<test_cases>\n"));
|
||||
#else
|
||||
BOOL tr_File_Open (const char *title, const char *date, const char *time, const char __attribute__((unused)) *fn) {
|
||||
PRINT(("%s %s %s \n\n", title, date, time));
|
||||
#endif
|
||||
return (__TRUE);
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Open test case
|
||||
*----------------------------------------------------------------------------*/
|
||||
BOOL tc_File_Open (uint32_t num, const char *fn) {
|
||||
(void)tc_Init ();
|
||||
#if (PRINT_XML_REPORT==1)
|
||||
PRINT(("<tc>\n"));
|
||||
PRINT(("<no>%d</no>\n", num));
|
||||
PRINT(("<func>%s</func>\n", fn));
|
||||
PRINT(("<req></req>"));
|
||||
PRINT(("<meth></meth>"));
|
||||
PRINT(("<dbgi>\n"));
|
||||
#else
|
||||
PRINT(("TEST %02d: %-42s ", num, fn));
|
||||
#endif
|
||||
return (__TRUE);
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Close test case
|
||||
*----------------------------------------------------------------------------*/
|
||||
BOOL tc_File_Close (void) {
|
||||
uint8_t *res = tc_Eval();
|
||||
#if (PRINT_XML_REPORT==1)
|
||||
PRINT(("</dbgi>\n"));
|
||||
PRINT(("<res>%s</res>\n", res));
|
||||
PRINT(("</tc>\n"));
|
||||
#else
|
||||
if ((res==Passed)||(res==NotExe)) {
|
||||
PRINT(("%s\n", res));
|
||||
} else {
|
||||
PRINT(("\n"));
|
||||
}
|
||||
#endif
|
||||
FLUSH();
|
||||
return (__TRUE);
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Close test report
|
||||
*----------------------------------------------------------------------------*/
|
||||
BOOL tr_File_Close (void) {
|
||||
#if (PRINT_XML_REPORT==1)
|
||||
PRINT(("</test_cases>\n"));
|
||||
PRINT(("<summary>\n"));
|
||||
PRINT(("<tcnt>%d</tcnt>\n", test_report.tests));
|
||||
PRINT(("<exec>%d</exec>\n", test_report.executed));
|
||||
PRINT(("<pass>%d</pass>\n", test_report.passed));
|
||||
PRINT(("<fail>%d</fail>\n", test_report.failed));
|
||||
PRINT(("<warn>%d</warn>\n", test_report.warnings));
|
||||
PRINT(("<tres>%s</tres>\n", tr_Eval()));
|
||||
PRINT(("</summary>\n"));
|
||||
PRINT(("</test>\n"));
|
||||
PRINT(("</report>\n"));
|
||||
#else
|
||||
PRINT(("\nTest Summary: %d Tests, %d Executed, %d Passed, %d Failed, %d Warnings.\n",
|
||||
test_report.tests,
|
||||
test_report.executed,
|
||||
test_report.passed,
|
||||
test_report.failed,
|
||||
test_report.warnings));
|
||||
PRINT(("Test Result: %s\n", tr_Eval()));
|
||||
#endif
|
||||
FLUSH();
|
||||
return (__TRUE);
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Assertion result counter
|
||||
*----------------------------------------------------------------------------*/
|
||||
static BOOL As_File_Result (TC_RES res) {
|
||||
return (StatCount (res));
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Set debug information state
|
||||
*----------------------------------------------------------------------------*/
|
||||
#if (PRINT_XML_REPORT==1)
|
||||
static BOOL As_File_Dbgi (TC_RES __attribute__((unused)) res, const char *fn, uint32_t ln, char *desc) {
|
||||
PRINT(("<detail>\n"));
|
||||
if (desc!=NULL) PRINT(("<desc>%s</desc>\n", desc));
|
||||
PRINT(("<module>%s</module>\n", fn));
|
||||
PRINT(("<line>%d</line>\n", ln));
|
||||
PRINT(("</detail>\n"));
|
||||
#else
|
||||
static BOOL As_File_Dbgi (TC_RES res, const char *fn, uint32_t ln, char *desc) {
|
||||
PRINT(("\n %s (%d)", fn, ln));
|
||||
if (res==WARNING){ PRINT((" [WARNING]")); }
|
||||
if (res==FAILED) { PRINT((" [FAILED]")); }
|
||||
if (desc!=NULL) { PRINT((" %s", desc)); }
|
||||
#endif
|
||||
return (__TRUE);
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Init test report
|
||||
*----------------------------------------------------------------------------*/
|
||||
static BOOL tr_Init (void) {
|
||||
TAS->passed = 0;
|
||||
TAS->failed = 0;
|
||||
TAS->warnings = 0;
|
||||
return (__TRUE);
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Init test case
|
||||
*----------------------------------------------------------------------------*/
|
||||
static BOOL tc_Init (void) {
|
||||
CAS->passed = 0;
|
||||
CAS->failed = 0;
|
||||
CAS->warnings = 0;
|
||||
return (__TRUE);
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Evaluate test report results
|
||||
*----------------------------------------------------------------------------*/
|
||||
static uint8_t *tr_Eval (void) {
|
||||
if (test_report.failed > 0U) {
|
||||
/* Test fails if any test case failed */
|
||||
return (Failed);
|
||||
}
|
||||
else if (test_report.warnings > 0U) {
|
||||
/* Test warns if any test case warnings */
|
||||
return (Warning);
|
||||
}
|
||||
else if (test_report.passed > 0U) {
|
||||
/* Test passes if at least one test case passed */
|
||||
return (Passed);
|
||||
}
|
||||
else {
|
||||
/* No test cases were executed */
|
||||
return (NotExe);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Evaluate test case results
|
||||
*----------------------------------------------------------------------------*/
|
||||
static uint8_t *tc_Eval (void) {
|
||||
test_report.tests++;
|
||||
test_report.executed++;
|
||||
|
||||
if (CAS->failed > 0U) {
|
||||
/* Test case fails if any failed assertion recorded */
|
||||
test_report.failed++;
|
||||
return Failed;
|
||||
}
|
||||
else if (CAS->warnings > 0U) {
|
||||
/* Test case warns if any warnings assertion recorded */
|
||||
test_report.warnings++;
|
||||
return Warning;
|
||||
}
|
||||
else if (CAS->passed > 0U) {
|
||||
/* Test case passes if at least one assertion passed */
|
||||
test_report.passed++;
|
||||
return Passed;
|
||||
}
|
||||
else {
|
||||
/* Assert was not invoked - nothing to evaluate */
|
||||
test_report.executed--;
|
||||
return NotExe;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Statistics result counter
|
||||
*----------------------------------------------------------------------------*/
|
||||
static BOOL StatCount (TC_RES res) {
|
||||
switch (res) {
|
||||
case PASSED:
|
||||
CAS->passed++;
|
||||
TAS->passed++;
|
||||
break;
|
||||
|
||||
case WARNING:
|
||||
CAS->warnings++;
|
||||
TAS->warnings++;
|
||||
break;
|
||||
|
||||
case FAILED:
|
||||
CAS->failed++;
|
||||
TAS->failed++;
|
||||
break;
|
||||
|
||||
case NOT_EXECUTED:
|
||||
return (__FALSE);
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return (__TRUE);
|
||||
}
|
||||
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Set result
|
||||
*----------------------------------------------------------------------------*/
|
||||
TC_RES __set_result (const char *fn, uint32_t ln, TC_RES res, char* desc) {
|
||||
|
||||
// save assertion result
|
||||
switch (res) {
|
||||
case PASSED:
|
||||
if (TAS->passed < BUFFER_ASSERTIONS) {
|
||||
test_report.assertions.info.passed[TAS->passed].module = fn;
|
||||
test_report.assertions.info.passed[TAS->passed].line = ln;
|
||||
}
|
||||
break;
|
||||
case FAILED:
|
||||
if (TAS->failed < BUFFER_ASSERTIONS) {
|
||||
test_report.assertions.info.failed[TAS->failed].module = fn;
|
||||
test_report.assertions.info.failed[TAS->failed].line = ln;
|
||||
}
|
||||
break;
|
||||
case WARNING:
|
||||
if (TAS->warnings < BUFFER_ASSERTIONS) {
|
||||
test_report.assertions.info.warnings[TAS->warnings].module = fn;
|
||||
test_report.assertions.info.warnings[TAS->warnings].line = ln;
|
||||
}
|
||||
break;
|
||||
case NOT_EXECUTED:
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
// set debug info (if the test case didn't pass)
|
||||
if (res != PASSED) { (void)tcitf.Dbgi (res, fn, ln, desc); }
|
||||
// set result
|
||||
(void)tcitf.Result (res);
|
||||
return (res);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Assert true
|
||||
*----------------------------------------------------------------------------*/
|
||||
TC_RES __assert_true (const char *fn, uint32_t ln, uint32_t cond) {
|
||||
TC_RES res = FAILED;
|
||||
if (cond != 0U) { res = PASSED; }
|
||||
(void)__set_result(fn, ln, res, NULL);
|
||||
return (res);
|
||||
}
|
||||
|
||||
#ifndef DISABLE_SEMIHOSTING
|
||||
/*-----------------------------------------------------------------------------
|
||||
* MsgFlush: Flush the standard output
|
||||
*----------------------------------------------------------------------------*/
|
||||
static void MsgFlush(void) {
|
||||
(void)fflush(stdout);
|
||||
}
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang diagnostic push
|
||||
#pragma clang diagnostic ignored "-Wformat-nonliteral"
|
||||
#endif
|
||||
/*-----------------------------------------------------------------------------
|
||||
* MsgPrint: Print a message to the standard output
|
||||
*----------------------------------------------------------------------------*/
|
||||
static void MsgPrint (const char *msg, ...) {
|
||||
va_list args;
|
||||
va_start(args, msg);
|
||||
vprintf(msg, args);
|
||||
va_end(args);
|
||||
}
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang diagnostic pop
|
||||
#endif
|
||||
#endif // DISABLE_SEMIHOSTING
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* End of file
|
||||
*----------------------------------------------------------------------------*/
|
||||
@@ -0,0 +1,158 @@
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Name: CV_Config.h
|
||||
* Purpose: CV Config header
|
||||
*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2017 - 2018 Arm Limited. All rights reserved.
|
||||
*----------------------------------------------------------------------------*/
|
||||
#ifndef __CV_CONFIG_H
|
||||
#define __CV_CONFIG_H
|
||||
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
#define RTE_CV_COREINSTR 1
|
||||
#define RTE_CV_COREFUNC 1
|
||||
#define RTE_CV_CORESIMD 1
|
||||
#define RTE_CV_MPUFUNC (__MPU_PRESENT)
|
||||
#if defined __ICACHE_PRESENT || defined __DCACHE_PRESENT
|
||||
#define RTE_CV_L1CACHE (__ICACHE_PRESENT || __DCACHE_PRESENT)
|
||||
#endif
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <h> Common Test Settings
|
||||
// <o> Print Output Format <0=> Plain Text <1=> XML
|
||||
// <i> Set the test results output format to plain text or XML
|
||||
#ifndef PRINT_XML_REPORT
|
||||
#define PRINT_XML_REPORT 1
|
||||
#endif
|
||||
// <o> Buffer size for assertions results
|
||||
// <i> Set the buffer size for assertions results buffer
|
||||
#define BUFFER_ASSERTIONS 128U
|
||||
// </h>
|
||||
|
||||
// <h> Disable Test Cases
|
||||
// <i> Uncheck to disable an individual test case
|
||||
// <q0> TC_CoreInstr_NOP
|
||||
#define TC_COREINSTR_NOP_EN 1
|
||||
// <q0> TC_CoreInstr_SEV
|
||||
#define TC_COREINSTR_SEV_EN 1
|
||||
// <q0> TC_CoreInstr_BKPT
|
||||
#define TC_COREINSTR_BKPT_EN 1
|
||||
// <q0> TC_CoreInstr_ISB
|
||||
#define TC_COREINSTR_ISB_EN 1
|
||||
// <q0> TC_CoreInstr_DSB
|
||||
#define TC_COREINSTR_DSB_EN 1
|
||||
// <q0> TC_CoreInstr_DMB
|
||||
#define TC_COREINSTR_DMB_EN 1
|
||||
// <q0> TC_CoreInstr_WFI
|
||||
#define TC_COREINSTR_WFI_EN 0
|
||||
// <q0> TC_CoreInstr_WFE
|
||||
#define TC_COREINSTR_WFE_EN 0
|
||||
|
||||
// <q0> TC_CoreInstr_REV
|
||||
#define TC_COREINSTR_REV_EN 1
|
||||
// <q0> TC_CoreInstr_REV16
|
||||
#define TC_COREINSTR_REV16_EN 1
|
||||
// <q0> TC_CoreInstr_REVSH
|
||||
#define TC_COREINSTR_REVSH_EN 1
|
||||
// <q0> TC_CoreInstr_ROR
|
||||
#define TC_COREINSTR_ROR_EN 1
|
||||
// <q0> TC_CoreInstr_RBIT
|
||||
#define TC_COREINSTR_RBIT_EN 1
|
||||
// <q0> TC_CoreInstr_CLZ
|
||||
#define TC_COREINSTR_CLZ_EN 1
|
||||
// <q0> TC_CoreInstr_SSAT
|
||||
#define TC_COREINSTR_SSAT_EN 1
|
||||
// <q0> TC_CoreInstr_USAT
|
||||
#define TC_COREINSTR_USAT_EN 1
|
||||
// <q0> TC_CoreInstr_RRX
|
||||
#define TC_COREINSTR_RRX_EN 1
|
||||
// <q0> TC_CoreInstr_LoadStoreExlusive
|
||||
#define TC_COREINSTR_LOADSTOREEXCLUSIVE_EN 1
|
||||
// <q0> TC_CoreInstr_LoadStoreUnpriv
|
||||
#define TC_COREINSTR_LOADSTOREUNPRIV_EN 1
|
||||
// <q0> TC_CoreInstr_LoadStoreAcquire
|
||||
#define TC_COREINSTR_LOADSTOREACQUIRE_EN 1
|
||||
// <q0> TC_CoreInstr_LoadStoreAcquireExclusive
|
||||
#define TC_COREINSTR_LOADSTOREACQUIREEXCLUSIVE_EN 1
|
||||
// <q0> TC_CoreInstr_UnalignedUint16
|
||||
#define TC_COREINSTR_UNALIGNEDUINT16_EN 1
|
||||
// <q0> TC_CoreInstr_UnalignedUint32
|
||||
#define TC_COREINSTR_UNALIGNEDUINT32_EN 1
|
||||
|
||||
// <q0> TC_CoreSimd_SatAddSub
|
||||
#define TC_CORESIMD_SATADDSUB_EN 1
|
||||
// <q0> TC_CoreSimd_ParSat16
|
||||
#define TC_CORESIMD_PARSAT16_EN 1
|
||||
// <q0> TC_CoreSimd_PackUnpack
|
||||
#define TC_CORESIMD_PACKUNPACK_EN 1
|
||||
// <q0> TC_CoreSimd_ParSel
|
||||
#define TC_CORESIMD_PARSEL_EN 1
|
||||
// <q0> TC_CoreSimd_ParAddSub8
|
||||
#define TC_CORESIMD_PARADDSUB8_EN 1
|
||||
// <q0> TC_CoreSimd_AbsDif8
|
||||
#define TC_CORESIMD_ABSDIF8_EN 1
|
||||
// <q0> TC_CoreSimd_ParAddSub16
|
||||
#define TC_CORESIMD_PARADDSUB16_EN 1
|
||||
// <q0> TC_CoreSimd_ParMul16
|
||||
#define TC_CORESIMD_PARMUL16_EN 1
|
||||
// <q0> TC_CoreSimd_Pack16
|
||||
#define TC_CORESIMD_PACK16_EN 1
|
||||
// <q0> TC_CoreSimd_MulAcc32
|
||||
#define TC_CORESIMD_MULACC32_EN 1
|
||||
|
||||
// <q0> TC_CoreFunc_EnDisIRQ
|
||||
#define TC_COREFUNC_ENDISIRQ_EN 1
|
||||
// <q0> TC_CoreFunc_IRQPrio
|
||||
#define TC_COREFUNC_IRQPRIO_EN 1
|
||||
// <q0> TC_CoreFunc_EncDecIRQPrio
|
||||
#define TC_COREFUNC_ENCDECIRQPRIO_EN 1
|
||||
// <q0> TC_CoreFunc_IRQVect
|
||||
#define TC_COREFUNC_IRQVECT_EN 1
|
||||
// <q0> TC_CoreFunc_Control
|
||||
#define TC_COREFUNC_CONTROL_EN 1
|
||||
// <q0> TC_CoreFunc_IPSR
|
||||
#define TC_COREFUNC_IPSR_EN 1
|
||||
// <q0> TC_CoreFunc_APSR
|
||||
#define TC_COREFUNC_APSR_EN 1
|
||||
// <q0> TC_CoreFunc_PSP
|
||||
#define TC_COREFUNC_PSP_EN 1
|
||||
// <q0> TC_CoreFunc_MSP
|
||||
#define TC_COREFUNC_MSP_EN 1
|
||||
|
||||
// <q0> TC_CoreFunc_PSPLIM
|
||||
#define TC_COREFUNC_PSPLIM_EN 1
|
||||
// <q0> TC_CoreFunc_PSPLIM_NS
|
||||
#define TC_COREFUNC_PSPLIM_NS_EN 1
|
||||
// <q0> TC_CoreFunc_MSPLIM
|
||||
#define TC_COREFUNC_MSPLIM_EN 1
|
||||
// <q0> TC_CoreFunc_MSPLIM_NS
|
||||
#define TC_COREFUNC_MSPLIM_NS_EN 1
|
||||
// <q0> TC_CoreFunc_PRIMASK
|
||||
#define TC_COREFUNC_PRIMASK_EN 1
|
||||
// <q0> TC_CoreFunc_FAULTMASK
|
||||
#define TC_COREFUNC_FAULTMASK_EN 1
|
||||
// <q0> TC_CoreFunc_BASEPRI
|
||||
#define TC_COREFUNC_BASEPRI_EN 1
|
||||
// <q0> TC_CoreFunc_FPUType
|
||||
#define TC_COREFUNC_FPUTYPE_EN 1
|
||||
// <q0> TC_CoreFunc_FPSCR
|
||||
#define TC_COREFUNC_FPSCR_EN 1
|
||||
|
||||
// <q0> TC_MPU_SetClear
|
||||
#define TC_MPU_SETCLEAR_EN 1
|
||||
// <q0> TC_MPU_Load
|
||||
#define TC_MPU_LOAD_EN 1
|
||||
|
||||
// <q0> TC_CML1Cache_EnDisableICache
|
||||
#define TC_CML1CACHE_ENDISABLE_ICACHE 1
|
||||
// <q0> TC_CML1Cache_EnDisableDCache
|
||||
#define TC_CML1CACHE_ENDISABLE_DCACHE 1
|
||||
// <q0> TC_CML1Cache_CleanDCacheByAddrWhileDisabled
|
||||
#define TC_CML1CACHE_CLEANDCACHEBYADDRWHILEDISABLED 1
|
||||
|
||||
// </h>
|
||||
|
||||
#endif /* __CV_CONFIG_H */
|
||||
|
||||
@@ -0,0 +1,146 @@
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Name: CV_Config.h
|
||||
* Purpose: CV Config header
|
||||
*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2017 - 2018 Arm Limited. All rights reserved.
|
||||
*----------------------------------------------------------------------------*/
|
||||
#ifndef __CV_CONFIG_H
|
||||
#define __CV_CONFIG_H
|
||||
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <h> Common Test Settings
|
||||
// <o> Print Output Format <0=> Plain Text <1=> XML
|
||||
// <i> Set the test results output format to plain text or XML
|
||||
#ifndef PRINT_XML_REPORT
|
||||
#define PRINT_XML_REPORT 1
|
||||
#endif
|
||||
// <o> Buffer size for assertions results
|
||||
// <i> Set the buffer size for assertions results buffer
|
||||
#define BUFFER_ASSERTIONS 128U
|
||||
// </h>
|
||||
|
||||
// <h> Disable Test Cases
|
||||
// <i> Uncheck to disable an individual test case
|
||||
// <q0> TC_CoreInstr_NOP
|
||||
#define TC_COREINSTR_NOP_EN 1
|
||||
// <q0> TC_CoreInstr_SEV
|
||||
#define TC_COREINSTR_SEV_EN 1
|
||||
// <q0> TC_CoreInstr_BKPT
|
||||
#define TC_COREINSTR_BKPT_EN 1
|
||||
// <q0> TC_CoreInstr_ISB
|
||||
#define TC_COREINSTR_ISB_EN 1
|
||||
// <q0> TC_CoreInstr_DSB
|
||||
#define TC_COREINSTR_DSB_EN 1
|
||||
// <q0> TC_CoreInstr_DMB
|
||||
#define TC_COREINSTR_DMB_EN 1
|
||||
// <q0> TC_CoreInstr_WFI
|
||||
#define TC_COREINSTR_WFI_EN 0
|
||||
// <q0> TC_CoreInstr_WFE
|
||||
#define TC_COREINSTR_WFE_EN 0
|
||||
|
||||
// <q0> TC_CoreInstr_REV
|
||||
#define TC_COREINSTR_REV_EN 1
|
||||
// <q0> TC_CoreInstr_REV16
|
||||
#define TC_COREINSTR_REV16_EN 1
|
||||
// <q0> TC_CoreInstr_REVSH
|
||||
#define TC_COREINSTR_REVSH_EN 1
|
||||
// <q0> TC_CoreInstr_ROR
|
||||
#define TC_COREINSTR_ROR_EN 1
|
||||
// <q0> TC_CoreInstr_RBIT
|
||||
#define TC_COREINSTR_RBIT_EN 1
|
||||
// <q0> TC_CoreInstr_CLZ
|
||||
#define TC_COREINSTR_CLZ_EN 1
|
||||
// <q0> TC_CoreInstr_SSAT
|
||||
#define TC_COREINSTR_SSAT_EN 1
|
||||
// <q0> TC_CoreInstr_USAT
|
||||
#define TC_COREINSTR_USAT_EN 1
|
||||
// <q0> TC_CoreInstr_RRX
|
||||
#define TC_COREINSTR_RRX_EN 1
|
||||
// <q0> TC_CoreInstr_LoadStoreExlusive
|
||||
#define TC_COREINSTR_LOADSTOREEXCLUSIVE_EN 1
|
||||
// <q0> TC_CoreInstr_LoadStoreUnpriv
|
||||
#define TC_COREINSTR_LOADSTOREUNPRIV_EN 1
|
||||
// <q0> TC_CoreInstr_LoadStoreAcquire
|
||||
#define TC_COREINSTR_LOADSTOREACQUIRE_EN 1
|
||||
// <q0> TC_CoreInstr_LoadStoreAcquireExclusive
|
||||
#define TC_COREINSTR_LOADSTOREACQUIREEXCLUSIVE_EN 1
|
||||
|
||||
// <q0> TC_CoreSimd_SatAddSub
|
||||
#define TC_CORESIMD_SATADDSUB_EN 1
|
||||
// <q0> TC_CoreSimd_ParSat16
|
||||
#define TC_CORESIMD_PARSAT16_EN 1
|
||||
// <q0> TC_CoreSimd_PackUnpack
|
||||
#define TC_CORESIMD_PACKUNPACK_EN 1
|
||||
// <q0> TC_CoreSimd_ParSel
|
||||
#define TC_CORESIMD_PARSEL_EN 1
|
||||
// <q0> TC_CoreSimd_ParAddSub8
|
||||
#define TC_CORESIMD_PARADDSUB8_EN 1
|
||||
// <q0> TC_CoreSimd_AbsDif8
|
||||
#define TC_CORESIMD_ABSDIF8_EN 1
|
||||
// <q0> TC_CoreSimd_ParAddSub16
|
||||
#define TC_CORESIMD_PARADDSUB16_EN 1
|
||||
// <q0> TC_CoreSimd_ParMul16
|
||||
#define TC_CORESIMD_PARMUL16_EN 1
|
||||
// <q0> TC_CoreSimd_Pack16
|
||||
#define TC_CORESIMD_PACK16_EN 1
|
||||
// <q0> TC_CoreSimd_MulAcc32
|
||||
#define TC_CORESIMD_MULACC32_EN 1
|
||||
|
||||
// <q0> TC_CoreFunc_EnDisIRQ
|
||||
#define TC_COREFUNC_ENDISIRQ_EN 1
|
||||
// <q0> TC_CoreFunc_IRQPrio
|
||||
#define TC_COREFUNC_IRQPRIO_EN 1
|
||||
// <q0> TC_CoreFunc_EncDecIRQPrio
|
||||
#define TC_COREFUNC_ENCDECIRQPRIO_EN 1
|
||||
// <q0> TC_CoreFunc_IRQVect
|
||||
#define TC_COREFUNC_IRQVECT_EN 1
|
||||
// <q0> TC_CoreFunc_Control
|
||||
#define TC_COREFUNC_CONTROL_EN 1
|
||||
// <q0> TC_CoreFunc_IPSR
|
||||
#define TC_COREFUNC_IPSR_EN 1
|
||||
// <q0> TC_CoreFunc_APSR
|
||||
#define TC_COREFUNC_APSR_EN 1
|
||||
// <q0> TC_CoreFunc_PSP
|
||||
#define TC_COREFUNC_PSP_EN 1
|
||||
// <q0> TC_CoreFunc_MSP
|
||||
#define TC_COREFUNC_MSP_EN 1
|
||||
|
||||
// <q0> TC_CoreFunc_PSPLIM
|
||||
#define TC_COREFUNC_PSPLIM_EN 1
|
||||
// <q0> TC_CoreFunc_PSPLIM_NS
|
||||
#define TC_COREFUNC_PSPLIM_NS_EN 1
|
||||
// <q0> TC_CoreFunc_MSPLIM
|
||||
#define TC_COREFUNC_MSPLIM_EN 1
|
||||
// <q0> TC_CoreFunc_MSPLIM_NS
|
||||
#define TC_COREFUNC_MSPLIM_NS_EN 1
|
||||
// <q0> TC_CoreFunc_PRIMASK
|
||||
#define TC_COREFUNC_PRIMASK_EN 1
|
||||
// <q0> TC_CoreFunc_FAULTMASK
|
||||
#define TC_COREFUNC_FAULTMASK_EN 1
|
||||
// <q0> TC_CoreFunc_BASEPRI
|
||||
#define TC_COREFUNC_BASEPRI_EN 1
|
||||
// <q0> TC_CoreFunc_FPUType
|
||||
#define TC_COREFUNC_FPUTYPE_EN 1
|
||||
// <q0> TC_CoreFunc_FPSCR
|
||||
#define TC_COREFUNC_FPSCR_EN 1
|
||||
|
||||
// <q0> TC_MPU_SetClear
|
||||
#define TC_MPU_SETCLEAR_EN 1
|
||||
// <q0> TC_MPU_Load
|
||||
#define TC_MPU_LOAD_EN 1
|
||||
|
||||
// <q0> TC_CML1Cache_EnDisableICache
|
||||
#define TC_CML1CACHE_ENDISABLE_ICACHE 1
|
||||
// <q0> TC_CML1Cache_EnDisableDCache
|
||||
#define TC_CML1CACHE_ENDISABLE_DCACHE 1
|
||||
// <q0> TC_CML1Cache_CleanDCacheByAddrWhileDisabled
|
||||
#define TC_CML1CACHE_CLEANDCACHEBYADDRWHILEDISABLED 1
|
||||
|
||||
// </h>
|
||||
|
||||
#endif /* __CV_CONFIG_H */
|
||||
|
||||
@@ -0,0 +1,832 @@
|
||||
/**************************************************************************//**
|
||||
* @file partition_ARMCM23.h
|
||||
* @brief CMSIS-CORE Initial Setup for Secure / Non-Secure Zones for ARMCM23
|
||||
* @version V5.3.1
|
||||
* @date 09. July 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef PARTITION_ARMCM23_H
|
||||
#define PARTITION_ARMCM23_H
|
||||
|
||||
/*
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize Security Attribution Unit (SAU) CTRL register
|
||||
*/
|
||||
#define SAU_INIT_CTRL 1
|
||||
|
||||
/*
|
||||
// <q> Enable SAU
|
||||
// <i> Value for SAU->CTRL register bit ENABLE
|
||||
*/
|
||||
#define SAU_INIT_CTRL_ENABLE 1
|
||||
|
||||
/*
|
||||
// <o> When SAU is disabled
|
||||
// <0=> All Memory is Secure
|
||||
// <1=> All Memory is Non-Secure
|
||||
// <i> Value for SAU->CTRL register bit ALLNS
|
||||
// <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
|
||||
*/
|
||||
#define SAU_INIT_CTRL_ALLNS 0
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <h>Initialize Security Attribution Unit (SAU) Address Regions
|
||||
// <i>SAU configuration specifies regions to be one of:
|
||||
// <i> - Secure and Non-Secure Callable
|
||||
// <i> - Non-Secure
|
||||
// <i>Note: All memory regions not configured by SAU are Secure
|
||||
*/
|
||||
#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 0
|
||||
// <i> Setup SAU Region 0 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION0 1
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START0 0x00000000 /* start address of SAU region 0 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END0 0x001FFFFF /* end address of SAU region 0 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC0 1
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 1
|
||||
// <i> Setup SAU Region 1 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION1 1
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START1 0x00200000
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END1 0x003FFFFF
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC1 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 2
|
||||
// <i> Setup SAU Region 2 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION2 1
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START2 0x20200000
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END2 0x203FFFFF
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC2 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 3
|
||||
// <i> Setup SAU Region 3 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION3 1
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START3 0x40000000
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END3 0x40040000
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC3 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 4
|
||||
// <i> Setup SAU Region 4 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION4 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC4 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 5
|
||||
// <i> Setup SAU Region 5 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION5 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START5 0x00000000
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END5 0x00000000
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC5 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 6
|
||||
// <i> Setup SAU Region 6 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION6 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START6 0x00000000
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END6 0x00000000
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC6 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize SAU Region 7
|
||||
// <i> Setup SAU Region 7 memory attributes
|
||||
*/
|
||||
#define SAU_INIT_REGION7 0
|
||||
|
||||
/*
|
||||
// <o>Start Address <0-0xFFFFFFE0>
|
||||
*/
|
||||
#define SAU_INIT_START7 0x00000000
|
||||
|
||||
/*
|
||||
// <o>End Address <0x1F-0xFFFFFFFF>
|
||||
*/
|
||||
#define SAU_INIT_END7 0x00000000
|
||||
|
||||
/*
|
||||
// <o>Region is
|
||||
// <0=>Non-Secure
|
||||
// <1=>Secure, Non-Secure Callable
|
||||
*/
|
||||
#define SAU_INIT_NSC7 0
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// </h>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Setup behaviour of Sleep and Exception Handling
|
||||
*/
|
||||
#define SCB_CSR_AIRCR_INIT 1
|
||||
|
||||
/*
|
||||
// <o> Deep Sleep can be enabled by
|
||||
// <0=>Secure and Non-Secure state
|
||||
// <1=>Secure state only
|
||||
// <i> Value for SCB->CSR register bit DEEPSLEEPS
|
||||
*/
|
||||
#define SCB_CSR_DEEPSLEEPS_VAL 1
|
||||
|
||||
/*
|
||||
// <o>System reset request accessible from
|
||||
// <0=> Secure and Non-Secure state
|
||||
// <1=> Secure state only
|
||||
// <i> Value for SCB->AIRCR register bit SYSRESETREQS
|
||||
*/
|
||||
#define SCB_AIRCR_SYSRESETREQS_VAL 1
|
||||
|
||||
/*
|
||||
// <o>Priority of Non-Secure exceptions is
|
||||
// <0=> Not altered
|
||||
// <1=> Lowered to 0x80-0xFF
|
||||
// <i> Value for SCB->AIRCR register bit PRIS
|
||||
*/
|
||||
#define SCB_AIRCR_PRIS_VAL 1
|
||||
|
||||
/*
|
||||
// <o>BusFault, HardFault, and NMI target
|
||||
// <0=> Secure state
|
||||
// <1=> Non-Secure state
|
||||
// <i> Value for SCB->AIRCR register bit BFHFNMINS
|
||||
*/
|
||||
#define SCB_AIRCR_BFHFNMINS_VAL 0
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
// <e>Setup behaviour of single SysTick
|
||||
*/
|
||||
#define SCB_ICSR_INIT 0
|
||||
|
||||
/*
|
||||
// <o> in a single SysTick implementation, SysTick is
|
||||
// <0=>Secure
|
||||
// <1=>Non-Secure
|
||||
// <i> Value for SCB->ICSR register bit STTNS
|
||||
// <i> only for single SysTick implementation
|
||||
*/
|
||||
#define SCB_ICSR_STTNS_VAL 0
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
// <h>Setup Interrupt Target
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 0 (Interrupts 0..31)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS0 1
|
||||
|
||||
/*
|
||||
// Interrupts 0..31
|
||||
// <o.0> Interrupt 0 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> Interrupt 1 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> Interrupt 2 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> Interrupt 3 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> Interrupt 4 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> Interrupt 5 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> Interrupt 6 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> Interrupt 7 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> Interrupt 8 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> Interrupt 9 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> Interrupt 10 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> Interrupt 11 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> Interrupt 12 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> Interrupt 13 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> Interrupt 14 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> Interrupt 15 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> Interrupt 16 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> Interrupt 17 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> Interrupt 18 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> Interrupt 19 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> Interrupt 20 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> Interrupt 21 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> Interrupt 22 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> Interrupt 23 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> Interrupt 24 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> Interrupt 25 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> Interrupt 26 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> Interrupt 27 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> Interrupt 28 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> Interrupt 29 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> Interrupt 30 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> Interrupt 31 <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS0_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 1 (Interrupts 32..63)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS1 1
|
||||
|
||||
/*
|
||||
// Interrupts 32..63
|
||||
// <o.0> Interrupt 32 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> Interrupt 33 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> Interrupt 34 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> Interrupt 35 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> Interrupt 36 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> Interrupt 37 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> Interrupt 38 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> Interrupt 39 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> Interrupt 40 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> Interrupt 41 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> Interrupt 42 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> Interrupt 43 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> Interrupt 44 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> Interrupt 45 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> Interrupt 46 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> Interrupt 47 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> Interrupt 48 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> Interrupt 49 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> Interrupt 50 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> Interrupt 51 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> Interrupt 52 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> Interrupt 53 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> Interrupt 54 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> Interrupt 55 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> Interrupt 56 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> Interrupt 57 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> Interrupt 58 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> Interrupt 59 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> Interrupt 60 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> Interrupt 61 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> Interrupt 62 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> Interrupt 63 <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS1_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 2 (Interrupts 64..95)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS2 0
|
||||
|
||||
/*
|
||||
// Interrupts 64..95
|
||||
// <o.0> Interrupt 64 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> Interrupt 65 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> Interrupt 66 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> Interrupt 67 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> Interrupt 68 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> Interrupt 69 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> Interrupt 70 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> Interrupt 71 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> Interrupt 72 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> Interrupt 73 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> Interrupt 74 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> Interrupt 75 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> Interrupt 76 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> Interrupt 77 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> Interrupt 78 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> Interrupt 79 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> Interrupt 80 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> Interrupt 81 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> Interrupt 82 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> Interrupt 83 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> Interrupt 84 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> Interrupt 85 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> Interrupt 86 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> Interrupt 87 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> Interrupt 88 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> Interrupt 89 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> Interrupt 90 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> Interrupt 91 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> Interrupt 92 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> Interrupt 93 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> Interrupt 94 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> Interrupt 95 <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS2_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 3 (Interrupts 96..127)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS3 0
|
||||
|
||||
/*
|
||||
// Interrupts 96..127
|
||||
// <o.0> Interrupt 96 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> Interrupt 97 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> Interrupt 98 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> Interrupt 99 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> Interrupt 100 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> Interrupt 101 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> Interrupt 102 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> Interrupt 103 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> Interrupt 104 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> Interrupt 105 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> Interrupt 106 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> Interrupt 107 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> Interrupt 108 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> Interrupt 109 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> Interrupt 110 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> Interrupt 111 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> Interrupt 112 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> Interrupt 113 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> Interrupt 114 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> Interrupt 115 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> Interrupt 116 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> Interrupt 117 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> Interrupt 118 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> Interrupt 119 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> Interrupt 120 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> Interrupt 121 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> Interrupt 122 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> Interrupt 123 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> Interrupt 124 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> Interrupt 125 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> Interrupt 126 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> Interrupt 127 <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS3_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 4 (Interrupts 128..159)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS4 0
|
||||
|
||||
/*
|
||||
// Interrupts 128..159
|
||||
// <o.0> Interrupt 128 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> Interrupt 129 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> Interrupt 130 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> Interrupt 131 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> Interrupt 132 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> Interrupt 133 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> Interrupt 134 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> Interrupt 135 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> Interrupt 136 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> Interrupt 137 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> Interrupt 138 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> Interrupt 139 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> Interrupt 140 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> Interrupt 141 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> Interrupt 142 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> Interrupt 143 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> Interrupt 144 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> Interrupt 145 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> Interrupt 146 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> Interrupt 147 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> Interrupt 148 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> Interrupt 149 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> Interrupt 150 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> Interrupt 151 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> Interrupt 152 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> Interrupt 153 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> Interrupt 154 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> Interrupt 155 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> Interrupt 156 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> Interrupt 157 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> Interrupt 158 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> Interrupt 159 <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS4_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 5 (Interrupts 160..191)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS5 0
|
||||
|
||||
/*
|
||||
// Interrupts 160..191
|
||||
// <o.0> Interrupt 160 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> Interrupt 161 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> Interrupt 162 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> Interrupt 163 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> Interrupt 164 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> Interrupt 165 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> Interrupt 166 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> Interrupt 167 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> Interrupt 168 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> Interrupt 169 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> Interrupt 170 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> Interrupt 171 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> Interrupt 172 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> Interrupt 173 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> Interrupt 174 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> Interrupt 175 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> Interrupt 176 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> Interrupt 177 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> Interrupt 178 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> Interrupt 179 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> Interrupt 180 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> Interrupt 181 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> Interrupt 182 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> Interrupt 183 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> Interrupt 184 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> Interrupt 185 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> Interrupt 186 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> Interrupt 187 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> Interrupt 188 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> Interrupt 189 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> Interrupt 190 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> Interrupt 191 <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS5_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 6 (Interrupts 192..223)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS6 0
|
||||
|
||||
/*
|
||||
// Interrupts 192..223
|
||||
// <o.0> Interrupt 192 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> Interrupt 193 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> Interrupt 194 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> Interrupt 195 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> Interrupt 196 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> Interrupt 197 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> Interrupt 198 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> Interrupt 199 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> Interrupt 200 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> Interrupt 201 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> Interrupt 202 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> Interrupt 203 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> Interrupt 204 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> Interrupt 205 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> Interrupt 206 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> Interrupt 207 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> Interrupt 208 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> Interrupt 209 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> Interrupt 210 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> Interrupt 211 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> Interrupt 212 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> Interrupt 213 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> Interrupt 214 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> Interrupt 215 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> Interrupt 216 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> Interrupt 217 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> Interrupt 218 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> Interrupt 219 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> Interrupt 220 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> Interrupt 221 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> Interrupt 222 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> Interrupt 223 <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS6_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// <e>Initialize ITNS 7 (Interrupts 224..255)
|
||||
*/
|
||||
#define NVIC_INIT_ITNS7 0
|
||||
|
||||
/*
|
||||
// Interrupts 224..255
|
||||
// <o.0> Interrupt 224 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.1> Interrupt 225 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.2> Interrupt 226 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.3> Interrupt 227 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.4> Interrupt 228 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.5> Interrupt 229 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.6> Interrupt 230 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.7> Interrupt 231 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.8> Interrupt 232 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.9> Interrupt 233 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.10> Interrupt 234 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.11> Interrupt 235 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.12> Interrupt 236 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.13> Interrupt 237 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.14> Interrupt 238 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.15> Interrupt 239 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.16> Interrupt 240 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.17> Interrupt 241 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.18> Interrupt 242 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.19> Interrupt 243 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.20> Interrupt 244 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.21> Interrupt 245 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.22> Interrupt 246 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.23> Interrupt 247 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.24> Interrupt 248 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.25> Interrupt 249 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.26> Interrupt 250 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.27> Interrupt 251 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.28> Interrupt 252 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.29> Interrupt 253 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.30> Interrupt 254 <0=> Secure state <1=> Non-Secure state
|
||||
// <o.31> Interrupt 255 <0=> Secure state <1=> Non-Secure state
|
||||
*/
|
||||
#define NVIC_INIT_ITNS7_VAL 0x00000000
|
||||
|
||||
/*
|
||||
// </e>
|
||||
*/
|
||||
|
||||
/*
|
||||
// </h>
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/*
|
||||
max 128 SAU regions.
|
||||
SAU regions are defined in partition.h
|
||||
*/
|
||||
|
||||
#define SAU_INIT_REGION(n) \
|
||||
SAU->RNR = (n & SAU_RNR_REGION_Msk); \
|
||||
SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
|
||||
SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
|
||||
((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
|
||||
|
||||
/**
|
||||
\brief Setup a SAU Region
|
||||
\details Writes the region information contained in SAU_Region to the
|
||||
registers SAU_RNR, SAU_RBAR, and SAU_RLAR
|
||||
*/
|
||||
__STATIC_INLINE void TZ_SAU_Setup (void)
|
||||
{
|
||||
|
||||
#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
|
||||
|
||||
#if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
|
||||
SAU_INIT_REGION(0);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
|
||||
SAU_INIT_REGION(1);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
|
||||
SAU_INIT_REGION(2);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
|
||||
SAU_INIT_REGION(3);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
|
||||
SAU_INIT_REGION(4);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
|
||||
SAU_INIT_REGION(5);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
|
||||
SAU_INIT_REGION(6);
|
||||
#endif
|
||||
|
||||
#if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
|
||||
SAU_INIT_REGION(7);
|
||||
#endif
|
||||
|
||||
/* repeat this for all possible SAU regions */
|
||||
|
||||
#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
|
||||
|
||||
|
||||
#if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
|
||||
SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
|
||||
((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
|
||||
#endif
|
||||
|
||||
#if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
|
||||
SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) |
|
||||
((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
|
||||
|
||||
SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk |
|
||||
SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) |
|
||||
((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) |
|
||||
((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
|
||||
((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) |
|
||||
((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk);
|
||||
#endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
|
||||
|
||||
#if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U)
|
||||
SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk )) |
|
||||
((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk);
|
||||
#endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */
|
||||
|
||||
#if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
|
||||
NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
|
||||
NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
|
||||
NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
|
||||
NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U)
|
||||
NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U)
|
||||
NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U)
|
||||
NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL;
|
||||
#endif
|
||||
|
||||
#if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U)
|
||||
NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL;
|
||||
#endif
|
||||
|
||||
/* repeat this for all possible ITNS elements */
|
||||
|
||||
}
|
||||
|
||||
#endif /* PARTITION_ARMCM23_H */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,124 @@
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Name: CV_Config.h
|
||||
* Purpose: CV Config header
|
||||
*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2017 - 2021 ARM Limited. All rights reserved.
|
||||
*----------------------------------------------------------------------------*/
|
||||
#ifndef __CV_CONFIG_H
|
||||
#define __CV_CONFIG_H
|
||||
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
#define RTE_CV_COREINSTR 1
|
||||
#define RTE_CV_COREFUNC 1
|
||||
#define RTE_CV_L1CACHE 1
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <h> Common Test Settings
|
||||
// <o> Print Output Format <0=> Plain Text <1=> XML
|
||||
// <i> Set the test results output format to plain text or XML
|
||||
#ifndef PRINT_XML_REPORT
|
||||
#define PRINT_XML_REPORT 1
|
||||
#endif
|
||||
// <o> Buffer size for assertions results
|
||||
// <i> Set the buffer size for assertions results buffer
|
||||
#define BUFFER_ASSERTIONS 128U
|
||||
// </h>
|
||||
|
||||
// <h> Disable Test Cases
|
||||
// <i> Uncheck to disable an individual test case
|
||||
// <q0> TC_CoreInstr_NOP
|
||||
#define TC_COREINSTR_NOP_EN 1
|
||||
// <q0> TC_CoreInstr_REV
|
||||
#define TC_COREINSTR_REV_EN 1
|
||||
// <q0> TC_CoreInstr_REV16
|
||||
#define TC_COREINSTR_REV16_EN 1
|
||||
// <q0> TC_CoreInstr_REVSH
|
||||
#define TC_COREINSTR_REVSH_EN 1
|
||||
// <q0> TC_CoreInstr_ROR
|
||||
#define TC_COREINSTR_ROR_EN 1
|
||||
// <q0> TC_CoreInstr_RBIT
|
||||
#define TC_COREINSTR_RBIT_EN 1
|
||||
// <q0> TC_CoreInstr_CLZ
|
||||
#define TC_COREINSTR_CLZ_EN 1
|
||||
// <q0> TC_CoreInstr_Exclusives
|
||||
#define TC_COREINSTR_EXCLUSIVES_EN 1
|
||||
// <q0> TC_CoreInstr_SSAT
|
||||
#define TC_COREINSTR_SSAT_EN 1
|
||||
// <q0> TC_CoreInstr_USAT
|
||||
#define TC_COREINSTR_USAT_EN 1
|
||||
|
||||
// <q0> TC_CoreAFunc_IRQ
|
||||
#define TC_COREAFUNC_IRQ 1
|
||||
// <q0> TC_CoreAFunc_FaultIRQ
|
||||
#define TC_COREAFUNC_FAULTIRQ 1
|
||||
// <q0> TC_CoreAFunc_FPSCR
|
||||
#define TC_COREAFUNC_FPSCR 1
|
||||
// <q0> TC_CoreAFunc_CPSR
|
||||
#define TC_COREAFUNC_CPSR 1
|
||||
// <q0> TC_CoreAFunc_Mode
|
||||
#define TC_COREAFUNC_MODE 1
|
||||
// <q0> TC_CoreAFunc_SP
|
||||
#define TC_COREAFUNC_SP 1
|
||||
// <q0> TC_CoreAFunc_SP_usr
|
||||
#define TC_COREAFUNC_SP_USR 1
|
||||
// <q0> TC_CoreAFunc_FPEXC
|
||||
#define TC_COREAFUNC_FPEXC 1
|
||||
// <q0> TC_CoreAFunc_ACTLR
|
||||
#define TC_COREAFUNC_ACTLR 1
|
||||
// <q0> TC_CoreAFunc_CPACR
|
||||
#define TC_COREAFUNC_CPACR 1
|
||||
// <q0> TC_CoreAFunc_DFSR
|
||||
#define TC_COREAFUNC_DFSR 1
|
||||
// <q0> TC_CoreAFunc_IFSR
|
||||
#define TC_COREAFUNC_IFSR 1
|
||||
// <q0> TC_CoreAFunc_ISR
|
||||
#define TC_COREAFUNC_ISR 1
|
||||
// <q0> TC_CoreAFunc_CBAR
|
||||
#define TC_COREAFUNC_CBAR 1
|
||||
// <q0> TC_CoreAFunc_TTBR0
|
||||
#define TC_COREAFUNC_TTBR0 1
|
||||
// <q0> TC_CoreAFunc_DACR
|
||||
#define TC_COREAFUNC_DACR 1
|
||||
// <q0> TC_CoreAFunc_SCTLR
|
||||
#define TC_COREAFUNC_SCTLR 1
|
||||
// <q0> TC_CoreAFunc_ACTRL
|
||||
#define TC_COREAFUNC_ACTRL 1
|
||||
// <q0> TC_CoreAFunc_MPIDR
|
||||
#define TC_COREAFUNC_MPIDR 1
|
||||
// <q0> TC_CoreAFunc_VBAR
|
||||
#define TC_COREAFUNC_VBAR 1
|
||||
// <q0> TC_CoreAFunc_MVBAR
|
||||
#define TC_COREAFUNC_MVBAR 1
|
||||
// <q0> TC_CoreAFunc_FPU_Enable
|
||||
#define TC_COREAFUNC_FPU_ENABLE 1
|
||||
|
||||
// <q0> TC_GenTimer_CNTFRQ
|
||||
#define TC_GENTIMER_CNTFRQ 1
|
||||
// <q0> TC_GenTimer_CNTP_TVAL
|
||||
#define TC_GENTIMER_CNTP_TVAL 1
|
||||
// <q0> TC_GenTimer_CNTP_CTL
|
||||
#define TC_GENTIMER_CNTP_CTL 1
|
||||
// <q0> TC_GenTimer_CNTPCT
|
||||
#define TC_GENTIMER_CNTPCT 1
|
||||
// <q0> TC_GenTimer_CNTP_CVAL
|
||||
#define TC_GENTIMER_CNTP_CVAL 1
|
||||
|
||||
// <q0> TC_CAL1Cache_EnDisable
|
||||
#define TC_CAL1CACHE_ENDISABLE 1
|
||||
// <q0> TC_CAL1Cache_EnDisableBTAC
|
||||
#define TC_CAL1CACHE_ENDISABLEBTAC 1
|
||||
// <q0> TC_CAL1Cache_log2_up
|
||||
#define TC_CAL1CACHE_LOG2_UP 1
|
||||
// <q0> TC_CAL1Cache_InvalidateDCacheAll
|
||||
#define TC_CAL1CACHE_INVALIDATEDCACHEALL 1
|
||||
// <q0> TC_CAL1Cache_CleanDCacheAll
|
||||
#define TC_CAL1CACHE_CLEANDCACHEALL 1
|
||||
// <q0> TC_CAL1Cache_CleanInvalidateDCacheAll
|
||||
#define TC_CAL1CACHE_CLEANINVALIDATEDCACHEALL 1
|
||||
// </h>
|
||||
|
||||
#endif /* __CV_CONFIG_H */
|
||||
|
||||
@@ -0,0 +1,120 @@
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Name: CV_Config.h
|
||||
* Purpose: CV Config header
|
||||
*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2017 - 2021 ARM Limited. All rights reserved.
|
||||
*----------------------------------------------------------------------------*/
|
||||
#ifndef __CV_CONFIG_H
|
||||
#define __CV_CONFIG_H
|
||||
|
||||
#include "RTE_Components.h"
|
||||
#include CMSIS_device_header
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <h> Common Test Settings
|
||||
// <o> Print Output Format <0=> Plain Text <1=> XML
|
||||
// <i> Set the test results output format to plain text or XML
|
||||
#ifndef PRINT_XML_REPORT
|
||||
#define PRINT_XML_REPORT 0
|
||||
#endif
|
||||
// <o> Buffer size for assertions results
|
||||
// <i> Set the buffer size for assertions results buffer
|
||||
#define BUFFER_ASSERTIONS 128U
|
||||
// </h>
|
||||
|
||||
// <h> Disable Test Cases
|
||||
// <i> Uncheck to disable an individual test case
|
||||
// <q0> TC_CoreInstr_NOP
|
||||
#define TC_COREINSTR_NOP_EN 1
|
||||
// <q0> TC_CoreInstr_REV
|
||||
#define TC_COREINSTR_REV_EN 1
|
||||
// <q0> TC_CoreInstr_REV16
|
||||
#define TC_COREINSTR_REV16_EN 1
|
||||
// <q0> TC_CoreInstr_REVSH
|
||||
#define TC_COREINSTR_REVSH_EN 1
|
||||
// <q0> TC_CoreInstr_ROR
|
||||
#define TC_COREINSTR_ROR_EN 1
|
||||
// <q0> TC_CoreInstr_RBIT
|
||||
#define TC_COREINSTR_RBIT_EN 1
|
||||
// <q0> TC_CoreInstr_CLZ
|
||||
#define TC_COREINSTR_CLZ_EN 1
|
||||
// <q0> TC_CoreInstr_Exclusives
|
||||
#define TC_COREINSTR_EXCLUSIVES_EN 1
|
||||
// <q0> TC_CoreInstr_SSAT
|
||||
#define TC_COREINSTR_SSAT_EN 1
|
||||
// <q0> TC_CoreInstr_USAT
|
||||
#define TC_COREINSTR_USAT_EN 1
|
||||
|
||||
// <q0> TC_CoreAFunc_IRQ
|
||||
#define TC_COREAFUNC_IRQ 1
|
||||
// <q0> TC_CoreAFunc_FaultIRQ
|
||||
#define TC_COREAFUNC_FAULTIRQ 1
|
||||
// <q0> TC_CoreAFunc_FPSCR
|
||||
#define TC_COREAFUNC_FPSCR 1
|
||||
// <q0> TC_CoreAFunc_CPSR
|
||||
#define TC_COREAFUNC_CPSR 1
|
||||
// <q0> TC_CoreAFunc_Mode
|
||||
#define TC_COREAFUNC_MODE 1
|
||||
// <q0> TC_CoreAFunc_SP
|
||||
#define TC_COREAFUNC_SP 1
|
||||
// <q0> TC_CoreAFunc_SP_usr
|
||||
#define TC_COREAFUNC_SP_USR 1
|
||||
// <q0> TC_CoreAFunc_FPEXC
|
||||
#define TC_COREAFUNC_FPEXC 1
|
||||
// <q0> TC_CoreAFunc_ACTLR
|
||||
#define TC_COREAFUNC_ACTLR 1
|
||||
// <q0> TC_CoreAFunc_CPACR
|
||||
#define TC_COREAFUNC_CPACR 1
|
||||
// <q0> TC_CoreAFunc_DFSR
|
||||
#define TC_COREAFUNC_DFSR 1
|
||||
// <q0> TC_CoreAFunc_IFSR
|
||||
#define TC_COREAFUNC_IFSR 1
|
||||
// <q0> TC_CoreAFunc_ISR
|
||||
#define TC_COREAFUNC_ISR 1
|
||||
// <q0> TC_CoreAFunc_CBAR
|
||||
#define TC_COREAFUNC_CBAR 1
|
||||
// <q0> TC_CoreAFunc_TTBR0
|
||||
#define TC_COREAFUNC_TTBR0 1
|
||||
// <q0> TC_CoreAFunc_DACR
|
||||
#define TC_COREAFUNC_DACR 1
|
||||
// <q0> TC_CoreAFunc_SCTLR
|
||||
#define TC_COREAFUNC_SCTLR 1
|
||||
// <q0> TC_CoreAFunc_ACTRL
|
||||
#define TC_COREAFUNC_ACTRL 1
|
||||
// <q0> TC_CoreAFunc_MPIDR
|
||||
#define TC_COREAFUNC_MPIDR 1
|
||||
// <q0> TC_CoreAFunc_VBAR
|
||||
#define TC_COREAFUNC_VBAR 1
|
||||
// <q0> TC_CoreAFunc_MVBAR
|
||||
#define TC_COREAFUNC_MVBAR 1
|
||||
// <q0> TC_CoreAFunc_FPU_Enable
|
||||
#define TC_COREAFUNC_FPU_ENABLE 1
|
||||
|
||||
// <q0> TC_GenTimer_CNTFRQ
|
||||
#define TC_GENTIMER_CNTFRQ 1
|
||||
// <q0> TC_GenTimer_CNTP_TVAL
|
||||
#define TC_GENTIMER_CNTP_TVAL 1
|
||||
// <q0> TC_GenTimer_CNTP_CTL
|
||||
#define TC_GENTIMER_CNTP_CTL 1
|
||||
// <q0> TC_GenTimer_CNTPCT
|
||||
#define TC_GENTIMER_CNTPCT 1
|
||||
// <q0> TC_GenTimer_CNTP_CVAL
|
||||
#define TC_GENTIMER_CNTP_CVAL 1
|
||||
|
||||
// <q0> TC_CAL1Cache_EnDisable
|
||||
#define TC_CAL1CACHE_ENDISABLE 1
|
||||
// <q0> TC_CAL1Cache_EnDisableBTAC
|
||||
#define TC_CAL1CACHE_ENDISABLEBTAC 1
|
||||
// <q0> TC_CAL1Cache_log2_up
|
||||
#define TC_CAL1CACHE_LOG2_UP 1
|
||||
// <q0> TC_CAL1Cache_InvalidateDCacheAll
|
||||
#define TC_CAL1CACHE_INVALIDATEDCACHEALL 1
|
||||
// <q0> TC_CAL1Cache_CleanDCacheAll
|
||||
#define TC_CAL1CACHE_CLEANDCACHEALL 1
|
||||
// <q0> TC_CAL1Cache_CleanInvalidateDCacheAll
|
||||
#define TC_CAL1CACHE_CLEANINVALIDATEDCACHEALL 1
|
||||
// </h>
|
||||
|
||||
#endif /* __CV_CONFIG_H */
|
||||
|
||||
@@ -0,0 +1,189 @@
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Name: cmsis_cv.c
|
||||
* Purpose: Driver validation test cases entry point
|
||||
*----------------------------------------------------------------------------
|
||||
* Copyright (c) 2017 - 2021 Arm Limited. All rights reserved.
|
||||
*----------------------------------------------------------------------------*/
|
||||
#include "cmsis_cv.h"
|
||||
#include "RTE_Components.h"
|
||||
#include "CV_Framework.h"
|
||||
#include "CV_Config.h"
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Prototypes
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
void Interrupt0_Handler(void);
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Variables declarations
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
void (*TST_IRQHandler)(void);
|
||||
|
||||
void Interrupt0_Handler(void) {
|
||||
if (TST_IRQHandler != NULL) TST_IRQHandler();
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Init test suite
|
||||
*----------------------------------------------------------------------------*/
|
||||
static void TS_Init (void) {
|
||||
TST_IRQHandler = NULL;
|
||||
|
||||
#ifdef RTE_CV_MEASURETICKS
|
||||
StartCortexCycleCounter();
|
||||
#endif
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Test cases list
|
||||
*----------------------------------------------------------------------------*/
|
||||
static TEST_CASE TC_LIST[] = {
|
||||
#if defined(RTE_CV_COREINSTR) && RTE_CV_COREINSTR
|
||||
#if defined(__CORTEX_M)
|
||||
TCD ( TC_CoreInstr_NOP, TC_COREINSTR_NOP_EN ),
|
||||
TCD ( TC_CoreInstr_WFI, TC_COREINSTR_WFI_EN ),
|
||||
TCD ( TC_CoreInstr_WFE, TC_COREINSTR_WFE_EN ),
|
||||
TCD ( TC_CoreInstr_SEV, TC_COREINSTR_SEV_EN ),
|
||||
TCD ( TC_CoreInstr_BKPT, TC_COREINSTR_BKPT_EN ),
|
||||
TCD ( TC_CoreInstr_ISB, TC_COREINSTR_ISB_EN ),
|
||||
TCD ( TC_CoreInstr_DSB, TC_COREINSTR_DSB_EN ),
|
||||
TCD ( TC_CoreInstr_DMB, TC_COREINSTR_DMB_EN ),
|
||||
TCD ( TC_CoreInstr_REV, TC_COREINSTR_REV_EN ),
|
||||
TCD ( TC_CoreInstr_REV16, TC_COREINSTR_REV16_EN ),
|
||||
TCD ( TC_CoreInstr_REVSH, TC_COREINSTR_REVSH_EN ),
|
||||
TCD ( TC_CoreInstr_ROR, TC_COREINSTR_ROR_EN ),
|
||||
TCD ( TC_CoreInstr_RBIT, TC_COREINSTR_RBIT_EN ),
|
||||
TCD ( TC_CoreInstr_CLZ, TC_COREINSTR_CLZ_EN ),
|
||||
TCD ( TC_CoreInstr_SSAT, TC_COREINSTR_SSAT_EN ),
|
||||
TCD ( TC_CoreInstr_USAT, TC_COREINSTR_USAT_EN ),
|
||||
TCD ( TC_CoreInstr_RRX, TC_COREINSTR_RRX_EN ),
|
||||
TCD ( TC_CoreInstr_LoadStoreExclusive, TC_COREINSTR_LOADSTOREEXCLUSIVE_EN ),
|
||||
TCD ( TC_CoreInstr_LoadStoreUnpriv, TC_COREINSTR_LOADSTOREUNPRIV_EN ),
|
||||
TCD ( TC_CoreInstr_LoadStoreAcquire, TC_COREINSTR_LOADSTOREACQUIRE_EN ),
|
||||
TCD ( TC_CoreInstr_LoadStoreAcquireExclusive, TC_COREINSTR_LOADSTOREACQUIREEXCLUSIVE_EN ),
|
||||
TCD ( TC_CoreInstr_UnalignedUint16, TC_COREINSTR_UNALIGNEDUINT16_EN ),
|
||||
TCD ( TC_CoreInstr_UnalignedUint32, TC_COREINSTR_UNALIGNEDUINT32_EN ),
|
||||
|
||||
#elif defined(__CORTEX_A)
|
||||
TCD (TC_CoreInstr_NOP, TC_COREINSTR_NOP_EN ),
|
||||
TCD (TC_CoreInstr_REV, TC_COREINSTR_REV_EN ),
|
||||
TCD (TC_CoreInstr_REV16, TC_COREINSTR_REV16_EN ),
|
||||
TCD (TC_CoreInstr_REVSH, TC_COREINSTR_REVSH_EN ),
|
||||
TCD (TC_CoreInstr_ROR, TC_COREINSTR_ROR_EN ),
|
||||
TCD (TC_CoreInstr_RBIT, TC_COREINSTR_RBIT_EN ),
|
||||
TCD (TC_CoreInstr_CLZ, TC_COREINSTR_CLZ_EN ),
|
||||
TCD (TC_CoreInstr_SSAT, TC_COREINSTR_SSAT_EN ),
|
||||
TCD (TC_CoreInstr_USAT, TC_COREINSTR_USAT_EN ),
|
||||
TCD (TC_CoreInstr_LoadStoreExclusive, TC_COREINSTR_EXCLUSIVES_EN ),
|
||||
#endif
|
||||
#endif /* RTE_CV_COREINSTR */
|
||||
|
||||
#if defined (RTE_CV_CORESIMD) && RTE_CV_CORESIMD
|
||||
TCD ( TC_CoreSimd_SatAddSub, TC_CORESIMD_SATADDSUB_EN ),
|
||||
TCD ( TC_CoreSimd_ParSat16, TC_CORESIMD_PARSAT16_EN ),
|
||||
TCD ( TC_CoreSimd_PackUnpack, TC_CORESIMD_PACKUNPACK_EN ),
|
||||
TCD ( TC_CoreSimd_ParSel, TC_CORESIMD_PARSEL_EN ),
|
||||
TCD ( TC_CoreSimd_ParAddSub8, TC_CORESIMD_PARADDSUB8_EN ),
|
||||
TCD ( TC_CoreSimd_AbsDif8, TC_CORESIMD_ABSDIF8_EN ),
|
||||
TCD ( TC_CoreSimd_ParAddSub16, TC_CORESIMD_PARADDSUB16_EN ),
|
||||
TCD ( TC_CoreSimd_ParMul16, TC_CORESIMD_PARMUL16_EN ),
|
||||
TCD ( TC_CoreSimd_Pack16, TC_CORESIMD_PACK16_EN ),
|
||||
TCD ( TC_CoreSimd_MulAcc32, TC_CORESIMD_MULACC32_EN ),
|
||||
#endif /* RTE_CV_CORESIMD */
|
||||
|
||||
#if defined(RTE_CV_COREFUNC) && RTE_CV_COREFUNC
|
||||
#if defined(__CORTEX_M)
|
||||
TCD ( TC_CoreFunc_EnDisIRQ, TC_COREFUNC_ENDISIRQ_EN ),
|
||||
TCD ( TC_CoreFunc_IRQPrio, TC_COREFUNC_IRQPRIO_EN ),
|
||||
TCD ( TC_CoreFunc_EncDecIRQPrio, TC_COREFUNC_ENCDECIRQPRIO_EN ),
|
||||
TCD ( TC_CoreFunc_IRQVect, TC_COREFUNC_IRQVECT_EN ),
|
||||
TCD ( TC_CoreFunc_Control, TC_COREFUNC_CONTROL_EN ),
|
||||
TCD ( TC_CoreFunc_IPSR, TC_COREFUNC_IPSR_EN ),
|
||||
TCD ( TC_CoreFunc_APSR, TC_COREFUNC_APSR_EN ),
|
||||
TCD ( TC_CoreFunc_PSP, TC_COREFUNC_PSP_EN ),
|
||||
TCD ( TC_CoreFunc_MSP, TC_COREFUNC_MSP_EN ),
|
||||
TCD ( TC_CoreFunc_PSPLIM, TC_COREFUNC_PSPLIM_EN ),
|
||||
TCD ( TC_CoreFunc_PSPLIM_NS, TC_COREFUNC_PSPLIM_NS_EN ),
|
||||
TCD ( TC_CoreFunc_MSPLIM, TC_COREFUNC_MSPLIM_EN ),
|
||||
TCD ( TC_CoreFunc_MSPLIM_NS, TC_COREFUNC_MSPLIM_NS_EN ),
|
||||
TCD ( TC_CoreFunc_PRIMASK, TC_COREFUNC_PRIMASK_EN ),
|
||||
TCD ( TC_CoreFunc_FAULTMASK, TC_COREFUNC_FAULTMASK_EN ),
|
||||
TCD ( TC_CoreFunc_BASEPRI, TC_COREFUNC_BASEPRI_EN ),
|
||||
TCD ( TC_CoreFunc_FPUType, TC_COREFUNC_FPUTYPE_EN ),
|
||||
TCD ( TC_CoreFunc_FPSCR, TC_COREFUNC_FPSCR_EN ),
|
||||
|
||||
#elif defined(__CORTEX_A)
|
||||
TCD ( TC_CoreAFunc_IRQ, TC_COREAFUNC_IRQ ),
|
||||
TCD ( TC_CoreAFunc_FaultIRQ, TC_COREAFUNC_FAULTIRQ ),
|
||||
TCD ( TC_CoreAFunc_FPSCR, TC_COREAFUNC_FPSCR ),
|
||||
TCD ( TC_CoreAFunc_CPSR, TC_COREAFUNC_CPSR ),
|
||||
TCD ( TC_CoreAFunc_Mode, TC_COREAFUNC_MODE ),
|
||||
TCD ( TC_CoreAFunc_SP, TC_COREAFUNC_SP ),
|
||||
TCD ( TC_CoreAFunc_SP_usr, TC_COREAFUNC_SP_USR ),
|
||||
TCD ( TC_CoreAFunc_FPEXC, TC_COREAFUNC_FPEXC ),
|
||||
TCD ( TC_CoreAFunc_ACTLR, TC_COREAFUNC_ACTLR ),
|
||||
TCD ( TC_CoreAFunc_CPACR, TC_COREAFUNC_CPACR ),
|
||||
TCD ( TC_CoreAFunc_DFSR, TC_COREAFUNC_DFSR ),
|
||||
TCD ( TC_CoreAFunc_IFSR, TC_COREAFUNC_IFSR ),
|
||||
TCD ( TC_CoreAFunc_ISR, TC_COREAFUNC_ISR ),
|
||||
TCD ( TC_CoreAFunc_CBAR, TC_COREAFUNC_CBAR ),
|
||||
TCD ( TC_CoreAFunc_TTBR0, TC_COREAFUNC_TTBR0 ),
|
||||
TCD ( TC_CoreAFunc_DACR, TC_COREAFUNC_DACR ),
|
||||
TCD ( TC_CoreAFunc_SCTLR, TC_COREAFUNC_SCTLR ),
|
||||
TCD ( TC_CoreAFunc_ACTRL, TC_COREAFUNC_ACTRL ),
|
||||
TCD ( TC_CoreAFunc_MPIDR, TC_COREAFUNC_MPIDR ),
|
||||
TCD ( TC_CoreAFunc_VBAR, TC_COREAFUNC_VBAR ),
|
||||
TCD ( TC_CoreAFunc_MVBAR, TC_COREAFUNC_MVBAR ),
|
||||
TCD ( TC_CoreAFunc_FPU_Enable, TC_COREAFUNC_FPU_ENABLE ),
|
||||
#endif
|
||||
#endif /* RTE_CV_COREFUNC */
|
||||
|
||||
#if defined(RTE_CV_MPUFUNC) && RTE_CV_MPUFUNC
|
||||
TCD ( TC_MPU_SetClear, TC_MPU_SETCLEAR_EN ),
|
||||
TCD ( TC_MPU_Load, TC_MPU_LOAD_EN ),
|
||||
#endif /* RTE_CV_MPUFUNC */
|
||||
|
||||
#if defined(RTE_CV_GENTIMER) && RTE_CV_GENTIMER
|
||||
TCD ( TC_GenTimer_CNTFRQ, TC_GENTIMER_CNTFRQ ),
|
||||
TCD ( TC_GenTimer_CNTP_TVAL, TC_GENTIMER_CNTP_TVAL ),
|
||||
TCD ( TC_GenTimer_CNTP_CTL, TC_GENTIMER_CNTP_CTL ),
|
||||
TCD ( TC_GenTimer_CNTPCT, TC_GENTIMER_CNTPCT ),
|
||||
TCD ( TC_GenTimer_CNTP_CVAL, TC_GENTIMER_CNTP_CVAL ),
|
||||
#endif /* RTE_CV_GENTIMER */
|
||||
|
||||
#if defined(RTE_CV_L1CACHE) && RTE_CV_L1CACHE
|
||||
#if defined(__CORTEX_M)
|
||||
TCD ( TC_CML1Cache_EnDisableICache, TC_CML1CACHE_ENDISABLE_ICACHE ),
|
||||
TCD ( TC_CML1Cache_EnDisableDCache, TC_CML1CACHE_ENDISABLE_DCACHE ),
|
||||
TCD ( TC_CML1Cache_CleanDCacheByAddrWhileDisabled, TC_CML1CACHE_CLEANDCACHEBYADDRWHILEDISABLED),
|
||||
#elif defined(__CORTEX_A)
|
||||
TCD ( TC_CAL1Cache_EnDisable, TC_CAL1CACHE_ENDISABLE ),
|
||||
TCD ( TC_CAL1Cache_EnDisableBTAC, TC_CAL1CACHE_ENDISABLEBTAC ),
|
||||
TCD ( TC_CAL1Cache_log2_up, TC_CAL1CACHE_LOG2_UP ),
|
||||
TCD ( TC_CAL1Cache_InvalidateDCacheAll, TC_CAL1CACHE_INVALIDATEDCACHEALL ),
|
||||
TCD ( TC_CAL1Cache_CleanDCacheAll, TC_CAL1CACHE_CLEANDCACHEALL ),
|
||||
TCD ( TC_CAL1Cache_CleanInvalidateDCacheAll, TC_CAL1CACHE_CLEANINVALIDATEDCACHEALL ),
|
||||
#endif
|
||||
#endif /* RTE_CV_L1CACHE */
|
||||
};
|
||||
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang diagnostic push
|
||||
#pragma clang diagnostic ignored "-Wdate-time"
|
||||
#endif
|
||||
/*-----------------------------------------------------------------------------
|
||||
* Test suite description
|
||||
*----------------------------------------------------------------------------*/
|
||||
TEST_SUITE ts = {
|
||||
__FILE__, __DATE__, __TIME__,
|
||||
"CMSIS-CORE Test Suite",
|
||||
TS_Init,
|
||||
1,
|
||||
TC_LIST,
|
||||
ARRAY_SIZE (TC_LIST),
|
||||
};
|
||||
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#pragma clang diagnostic pop
|
||||
#endif
|
||||
Reference in New Issue
Block a user