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OneOfEleven
2023-09-09 08:03:56 +01:00
parent 92305117f1
commit 54441e27d9
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63
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/CMSIS/RTX_Config.c vendored Normal file
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/*
* Copyright (c) 2013-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.1.0
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration
*
* -----------------------------------------------------------------------------
*/
#include "cmsis_compiler.h"
#include "rtx_os.h"
// OS Idle Thread
__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
(void)argument;
for (;;) {}
}
// OS Error Callback function
__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
(void)object_id;
switch (code) {
case osRtxErrorStackUnderflow:
// Stack overflow detected for thread (thread_id=object_id)
break;
case osRtxErrorISRQueueOverflow:
// ISR Queue overflow detected when inserting object (object_id)
break;
case osRtxErrorTimerQueueOverflow:
// User Timer Callback Queue overflow detected for timer (timer_id=object_id)
break;
case osRtxErrorClibSpace:
// Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
break;
case osRtxErrorClibMutex:
// Standard C/C++ library mutex initialization failed
break;
default:
break;
}
for (;;) {}
//return 0U;
}

580
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/CMSIS/RTX_Config.h vendored Normal file
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/*
* Copyright (c) 2013-2020 Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* -----------------------------------------------------------------------------
*
* $Revision: V5.5.1
*
* Project: CMSIS-RTOS RTX
* Title: RTX Configuration definitions
*
* -----------------------------------------------------------------------------
*/
#ifndef RTX_CONFIG_H_
#define RTX_CONFIG_H_
#ifdef _RTE_
#include "RTE_Components.h"
#ifdef RTE_RTX_CONFIG_H
#include RTE_RTX_CONFIG_H
#endif
#endif
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>System Configuration
// =======================
// <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined global dynamic memory size.
// <i> Default: 32768
#ifndef OS_DYNAMIC_MEM_SIZE
#define OS_DYNAMIC_MEM_SIZE 4096
#endif
// <o>Kernel Tick Frequency [Hz] <1-1000000>
// <i> Defines base time unit for delays and timeouts.
// <i> Default: 1000 (1ms tick)
#ifndef OS_TICK_FREQ
#define OS_TICK_FREQ 1000
#endif
// <e>Round-Robin Thread switching
// <i> Enables Round-Robin Thread switching.
#ifndef OS_ROBIN_ENABLE
#define OS_ROBIN_ENABLE 1
#endif
// <o>Round-Robin Timeout <1-1000>
// <i> Defines how many ticks a thread will execute before a thread switch.
// <i> Default: 5
#ifndef OS_ROBIN_TIMEOUT
#define OS_ROBIN_TIMEOUT 5
#endif
// </e>
// <o>ISR FIFO Queue
// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries
// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries
// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries
// <i> RTOS Functions called from ISR store requests to this buffer.
// <i> Default: 16 entries
#ifndef OS_ISR_FIFO_QUEUE
#define OS_ISR_FIFO_QUEUE 32
#endif
// <q>Object Memory usage counters
// <i> Enables object memory usage counters (requires RTX source variant).
#ifndef OS_OBJ_MEM_USAGE
#define OS_OBJ_MEM_USAGE 0
#endif
// </h>
// <h>Thread Configuration
// =======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_THREAD_OBJ_MEM
#define OS_THREAD_OBJ_MEM 0
#endif
// <o>Number of user Threads <1-1000>
// <i> Defines maximum number of user threads that can be active at the same time.
// <i> Applies to user threads with system provided memory for control blocks.
#ifndef OS_THREAD_NUM
#define OS_THREAD_NUM 1
#endif
// <o>Number of user Threads with default Stack size <0-1000>
// <i> Defines maximum number of user threads with default stack size.
// <i> Applies to user threads with zero stack size specified.
#ifndef OS_THREAD_DEF_STACK_NUM
#define OS_THREAD_DEF_STACK_NUM 0
#endif
// <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
// <i> Defines the combined stack size for user threads with user-provided stack size.
// <i> Applies to user threads with user-provided stack size and system provided memory for stack.
// <i> Default: 0
#ifndef OS_THREAD_USER_STACK_SIZE
#define OS_THREAD_USER_STACK_SIZE 0
#endif
// </e>
// <o>Default Thread Stack size [bytes] <96-1073741824:8>
// <i> Defines stack size for threads with zero stack size specified.
// <i> Default: 3072
#ifndef OS_STACK_SIZE
#define OS_STACK_SIZE 1024
#endif
// <o>Idle Thread Stack size [bytes] <72-1073741824:8>
// <i> Defines stack size for Idle thread.
// <i> Default: 512
#ifndef OS_IDLE_THREAD_STACK_SIZE
#define OS_IDLE_THREAD_STACK_SIZE 512
#endif
// <o>Idle Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_IDLE_THREAD_TZ_MOD_ID
#define OS_IDLE_THREAD_TZ_MOD_ID 0
#endif
// <q>Stack overrun checking
// <i> Enables stack overrun check at thread switch.
// <i> Enabling this option increases slightly the execution time of a thread switch.
#ifndef OS_STACK_CHECK
#define OS_STACK_CHECK 1
#endif
// <q>Stack usage watermark
// <i> Initializes thread stack with watermark pattern for analyzing stack usage.
// <i> Enabling this option increases significantly the execution time of thread creation.
#ifndef OS_STACK_WATERMARK
#define OS_STACK_WATERMARK 0
#endif
// <o>Processor mode for Thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Privileged mode
#ifndef OS_PRIVILEGE_MODE
#define OS_PRIVILEGE_MODE 1
#endif
// </h>
// <h>Timer Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_TIMER_OBJ_MEM
#define OS_TIMER_OBJ_MEM 0
#endif
// <o>Number of Timer objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_TIMER_NUM
#define OS_TIMER_NUM 1
#endif
// </e>
// <o>Timer Thread Priority
// <8=> Low
// <16=> Below Normal <24=> Normal <32=> Above Normal
// <40=> High
// <48=> Realtime
// <i> Defines priority for timer thread
// <i> Default: High
#ifndef OS_TIMER_THREAD_PRIO
#define OS_TIMER_THREAD_PRIO 40
#endif
// <o>Timer Thread Stack size [bytes] <0-1073741824:8>
// <i> Defines stack size for Timer thread.
// <i> May be set to 0 when timers are not used.
// <i> Default: 512
#ifndef OS_TIMER_THREAD_STACK_SIZE
#define OS_TIMER_THREAD_STACK_SIZE 512
#endif
// <o>Timer Thread TrustZone Module Identifier
// <i> Defines TrustZone Thread Context Management Identifier.
// <i> Applies only to cores with TrustZone technology.
// <i> Default: 0 (not used)
#ifndef OS_TIMER_THREAD_TZ_MOD_ID
#define OS_TIMER_THREAD_TZ_MOD_ID 0
#endif
// <o>Timer Callback Queue entries <0-256>
// <i> Number of concurrent active timer callback functions.
// <i> May be set to 0 when timers are not used.
// <i> Default: 4
#ifndef OS_TIMER_CB_QUEUE
#define OS_TIMER_CB_QUEUE 4
#endif
// </h>
// <h>Event Flags Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_EVFLAGS_OBJ_MEM
#define OS_EVFLAGS_OBJ_MEM 0
#endif
// <o>Number of Event Flags objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_EVFLAGS_NUM
#define OS_EVFLAGS_NUM 1
#endif
// </e>
// </h>
// <h>Mutex Configuration
// ======================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MUTEX_OBJ_MEM
#define OS_MUTEX_OBJ_MEM 0
#endif
// <o>Number of Mutex objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MUTEX_NUM
#define OS_MUTEX_NUM 1
#endif
// </e>
// </h>
// <h>Semaphore Configuration
// ==========================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_SEMAPHORE_OBJ_MEM
#define OS_SEMAPHORE_OBJ_MEM 0
#endif
// <o>Number of Semaphore objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_SEMAPHORE_NUM
#define OS_SEMAPHORE_NUM 1
#endif
// </e>
// </h>
// <h>Memory Pool Configuration
// ============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MEMPOOL_OBJ_MEM
#define OS_MEMPOOL_OBJ_MEM 0
#endif
// <o>Number of Memory Pool objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MEMPOOL_NUM
#define OS_MEMPOOL_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MEMPOOL_DATA_SIZE
#define OS_MEMPOOL_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Message Queue Configuration
// ==============================
// <e>Object specific Memory allocation
// <i> Enables object specific memory allocation.
#ifndef OS_MSGQUEUE_OBJ_MEM
#define OS_MSGQUEUE_OBJ_MEM 0
#endif
// <o>Number of Message Queue objects <1-1000>
// <i> Defines maximum number of objects that can be active at the same time.
// <i> Applies to objects with system provided memory for control blocks.
#ifndef OS_MSGQUEUE_NUM
#define OS_MSGQUEUE_NUM 1
#endif
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
// <i> Defines the combined data storage memory size.
// <i> Applies to objects with system provided memory for data storage.
// <i> Default: 0
#ifndef OS_MSGQUEUE_DATA_SIZE
#define OS_MSGQUEUE_DATA_SIZE 0
#endif
// </e>
// </h>
// <h>Event Recorder Configuration
// ===============================
// <e>Global Initialization
// <i> Initialize Event Recorder during 'osKernelInitialize'.
#ifndef OS_EVR_INIT
#define OS_EVR_INIT 0
#endif
// <q>Start recording
// <i> Start event recording after initialization.
#ifndef OS_EVR_START
#define OS_EVR_START 1
#endif
// <h>Global Event Filter Setup
// <i> Initial recording level applied to all components.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_LEVEL
#define OS_EVR_LEVEL 0x00U
#endif
// <h>RTOS Event Filter Setup
// <i> Recording levels for RTX components.
// <i> Only applicable if events for the respective component are generated.
// <h>Memory Management
// <i> Recording level for Memory Management events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_MEMORY_LEVEL
#define OS_EVR_MEMORY_LEVEL 0x01U
#endif
// <h>Kernel
// <i> Recording level for Kernel events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_KERNEL_LEVEL
#define OS_EVR_KERNEL_LEVEL 0x01U
#endif
// <h>Thread
// <i> Recording level for Thread events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_THREAD_LEVEL
#define OS_EVR_THREAD_LEVEL 0x05U
#endif
// <h>Generic Wait
// <i> Recording level for Generic Wait events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_WAIT_LEVEL
#define OS_EVR_WAIT_LEVEL 0x01U
#endif
// <h>Thread Flags
// <i> Recording level for Thread Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_THFLAGS_LEVEL
#define OS_EVR_THFLAGS_LEVEL 0x01U
#endif
// <h>Event Flags
// <i> Recording level for Event Flags events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_EVFLAGS_LEVEL
#define OS_EVR_EVFLAGS_LEVEL 0x01U
#endif
// <h>Timer
// <i> Recording level for Timer events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_TIMER_LEVEL
#define OS_EVR_TIMER_LEVEL 0x01U
#endif
// <h>Mutex
// <i> Recording level for Mutex events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_MUTEX_LEVEL
#define OS_EVR_MUTEX_LEVEL 0x01U
#endif
// <h>Semaphore
// <i> Recording level for Semaphore events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_SEMAPHORE_LEVEL
#define OS_EVR_SEMAPHORE_LEVEL 0x01U
#endif
// <h>Memory Pool
// <i> Recording level for Memory Pool events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_MEMPOOL_LEVEL
#define OS_EVR_MEMPOOL_LEVEL 0x01U
#endif
// <h>Message Queue
// <i> Recording level for Message Queue events.
// <o.0>Error events
// <o.1>API function call events
// <o.2>Operation events
// <o.3>Detailed operation events
// </h>
#ifndef OS_EVR_MSGQUEUE_LEVEL
#define OS_EVR_MSGQUEUE_LEVEL 0x01U
#endif
// </h>
// </e>
// <h>RTOS Event Generation
// <i> Enables event generation for RTX components (requires RTX source variant).
// <q>Memory Management
// <i> Enables Memory Management event generation.
#ifndef OS_EVR_MEMORY
#define OS_EVR_MEMORY 1
#endif
// <q>Kernel
// <i> Enables Kernel event generation.
#ifndef OS_EVR_KERNEL
#define OS_EVR_KERNEL 1
#endif
// <q>Thread
// <i> Enables Thread event generation.
#ifndef OS_EVR_THREAD
#define OS_EVR_THREAD 1
#endif
// <q>Generic Wait
// <i> Enables Generic Wait event generation.
#ifndef OS_EVR_WAIT
#define OS_EVR_WAIT 1
#endif
// <q>Thread Flags
// <i> Enables Thread Flags event generation.
#ifndef OS_EVR_THFLAGS
#define OS_EVR_THFLAGS 1
#endif
// <q>Event Flags
// <i> Enables Event Flags event generation.
#ifndef OS_EVR_EVFLAGS
#define OS_EVR_EVFLAGS 1
#endif
// <q>Timer
// <i> Enables Timer event generation.
#ifndef OS_EVR_TIMER
#define OS_EVR_TIMER 1
#endif
// <q>Mutex
// <i> Enables Mutex event generation.
#ifndef OS_EVR_MUTEX
#define OS_EVR_MUTEX 1
#endif
// <q>Semaphore
// <i> Enables Semaphore event generation.
#ifndef OS_EVR_SEMAPHORE
#define OS_EVR_SEMAPHORE 1
#endif
// <q>Memory Pool
// <i> Enables Memory Pool event generation.
#ifndef OS_EVR_MEMPOOL
#define OS_EVR_MEMPOOL 1
#endif
// <q>Message Queue
// <i> Enables Message Queue event generation.
#ifndef OS_EVR_MSGQUEUE
#define OS_EVR_MSGQUEUE 1
#endif
// </h>
// </h>
// Number of Threads which use standard C/C++ library libspace
// (when thread specific memory allocation is not used).
#if (OS_THREAD_OBJ_MEM == 0)
#ifndef OS_THREAD_LIBSPACE_NUM
#define OS_THREAD_LIBSPACE_NUM 4
#endif
#else
#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM
#endif
//------------- <<< end of configuration section >>> ---------------------------
#endif // RTX_CONFIG_H_

2483
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4322_Cortex-M4/RTE_Device.h vendored Normal file
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333
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4322_Cortex-M4/startup_LPC43xx.s vendored Normal file
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;/**************************************************************************//**
; * @file LPC43xx.s
; * @brief CMSIS Cortex-M4 Core Device Startup File for
; * NXP LPC43xxDevice Series
; * @version V1.00
; * @date 03. September 2013
; *
; * @note
; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; * <<< Use Configuration Wizard in Context Menu >>>
; ******************************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
Sign_Value EQU 0x5A5A5A5A
__Vectors DCD __initial_sp ; 0 Top of Stack
DCD Reset_Handler ; 1 Reset Handler
DCD NMI_Handler ; 2 NMI Handler
DCD HardFault_Handler ; 3 Hard Fault Handler
DCD MemManage_Handler ; 4 MPU Fault Handler
DCD BusFault_Handler ; 5 Bus Fault Handler
DCD UsageFault_Handler ; 6 Usage Fault Handler
DCD Sign_Value ; 7 Reserved
DCD 0 ; 8 Reserved
DCD 0 ; 9 Reserved
DCD 0 ; 10 Reserved
DCD SVC_Handler ; 11 SVCall Handler
DCD DebugMon_Handler ; 12 Debug Monitor Handler
DCD 0 ; 13 Reserved
DCD PendSV_Handler ; 14 PendSV Handler
DCD SysTick_Handler ; 15 SysTick Handler
; External LPC43xx/M4 Interrupts
DCD DAC_IRQHandler ; 0 DAC interrupt
DCD M0APP_IRQHandler ; 1 Cortex-M0APP; Latched TXEV; for M4-M0APP communication
DCD DMA_IRQHandler ; 2 DMA interrupt
DCD 0 ; 3 Reserved
DCD FLASHEEPROM_IRQHandler ; 4 flash bank A, flash bank B, EEPROM ORed interrupt
DCD ETHERNET_IRQHandler ; 5 Ethernet interrupt
DCD SDIO_IRQHandler ; 6 SD/MMC interrupt
DCD LCD_IRQHandler ; 7 LCD interrupt
DCD USB0_IRQHandler ; 8 OTG interrupt
DCD USB1_IRQHandler ; 9 USB1 interrupt
DCD SCT_IRQHandler ; 10 SCT combined interrupt
DCD RITIMER_IRQHandler ; 11 RI Timer interrupt
DCD TIMER0_IRQHandler ; 12 Timer 0 interrupt
DCD TIMER1_IRQHandler ; 13 Timer 1 interrupt
DCD TIMER2_IRQHandler ; 14 Timer 2 interrupt
DCD TIMER3_IRQHandler ; 15 Timer 3 interrupt
DCD MCPWM_IRQHandler ; 16 Motor control PWM interrupt
DCD ADC0_IRQHandler ; 17 ADC0 interrupt
DCD I2C0_IRQHandler ; 18 I2C0 interrupt
DCD I2C1_IRQHandler ; 19 I2C1 interrupt
DCD SPI_IRQHandler ; 20 SPI interrupt
DCD ADC1_IRQHandler ; 21 ADC1 interrupt
DCD SSP0_IRQHandler ; 22 SSP0 interrupt
DCD SSP1_IRQHandler ; 23 SSP1 interrupt
DCD USART0_IRQHandler ; 24 USART0 interrupt
DCD UART1_IRQHandler ; 25 Combined UART1, Modem interrupt
DCD USART2_IRQHandler ; 26 USART2 interrupt
DCD USART3_IRQHandler ; 27 Combined USART3, IrDA interrupt
DCD I2S0_IRQHandler ; 28 I2S0 interrupt
DCD I2S1_IRQHandler ; 29 I2S1 interrupt
DCD SPIFI_IRQHandler ; 30 SPISI interrupt
DCD SGPIO_IRQHandler ; 31 SGPIO interrupt
DCD PIN_INT0_IRQHandler ; 32 GPIO pin interrupt 0
DCD PIN_INT1_IRQHandler ; 33 GPIO pin interrupt 1
DCD PIN_INT2_IRQHandler ; 34 GPIO pin interrupt 2
DCD PIN_INT3_IRQHandler ; 35 GPIO pin interrupt 3
DCD PIN_INT4_IRQHandler ; 36 GPIO pin interrupt 4
DCD PIN_INT5_IRQHandler ; 37 GPIO pin interrupt 5
DCD PIN_INT6_IRQHandler ; 38 GPIO pin interrupt 6
DCD PIN_INT7_IRQHandler ; 39 GPIO pin interrupt 7
DCD GINT0_IRQHandler ; 40 GPIO global interrupt 0
DCD GINT1_IRQHandler ; 41 GPIO global interrupt 1
DCD EVENTROUTER_IRQHandler ; 42 Event router interrupt
DCD C_CAN1_IRQHandler ; 43 C_CAN1 interrupt
DCD 0 ; 44 Reserved
DCD ADCHS_IRQHandler ; 45 ADCHS combined interrupt
DCD ATIMER_IRQHandler ; 46 Alarm timer interrupt
DCD RTC_IRQHandler ; 47 RTC interrupt
DCD 0 ; 48 Reserved
DCD WWDT_IRQHandler ; 49 WWDT interrupt
DCD M0SUB_IRQHandler ; 50 TXEV instruction from the M0 subsystem core interrupt
DCD C_CAN0_IRQHandler ; 51 C_CAN0 interrupt
DCD QEI_IRQHandler ; 52 QEI interrupt
;CRP address at offset 0x2FC relative to the BOOT Bank address
IF :LNOT::DEF:NO_CRP
SPACE (0x2FC - (. - __Vectors))
; EXPORT CRP_Key
CRP_Key DCD 0xFFFFFFFF
; 0xFFFFFFFF => CRP Disabled
; 0x12345678 => CRP Level 1
; 0x87654321 => CRP Level 2
; 0x43218765 => CRP Level 3 (ARE YOU SURE?)
; 0x4E697370 => NO ISP (ARE YOU SURE?)
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DAC_IRQHandler [WEAK]
EXPORT M0APP_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT FLASHEEPROM_IRQHandler [WEAK]
EXPORT ETHERNET_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT USB1_IRQHandler [WEAK]
EXPORT SCT_IRQHandler [WEAK]
EXPORT RITIMER_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT MCPWM_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT USART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT I2S0_IRQHandler [WEAK]
EXPORT I2S1_IRQHandler [WEAK]
EXPORT SPIFI_IRQHandler [WEAK]
EXPORT SGPIO_IRQHandler [WEAK]
EXPORT PIN_INT0_IRQHandler [WEAK]
EXPORT PIN_INT1_IRQHandler [WEAK]
EXPORT PIN_INT2_IRQHandler [WEAK]
EXPORT PIN_INT3_IRQHandler [WEAK]
EXPORT PIN_INT4_IRQHandler [WEAK]
EXPORT PIN_INT5_IRQHandler [WEAK]
EXPORT PIN_INT6_IRQHandler [WEAK]
EXPORT PIN_INT7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT EVENTROUTER_IRQHandler [WEAK]
EXPORT C_CAN1_IRQHandler [WEAK]
EXPORT ADCHS_IRQHandler [WEAK]
EXPORT ATIMER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT WWDT_IRQHandler [WEAK]
EXPORT M0SUB_IRQHandler [WEAK]
EXPORT C_CAN0_IRQHandler [WEAK]
EXPORT QEI_IRQHandler [WEAK]
DAC_IRQHandler
M0APP_IRQHandler
DMA_IRQHandler
FLASHEEPROM_IRQHandler
ETHERNET_IRQHandler
SDIO_IRQHandler
LCD_IRQHandler
USB0_IRQHandler
USB1_IRQHandler
SCT_IRQHandler
RITIMER_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
MCPWM_IRQHandler
ADC0_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI_IRQHandler
ADC1_IRQHandler
SSP0_IRQHandler
SSP1_IRQHandler
USART0_IRQHandler
UART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
I2S0_IRQHandler
I2S1_IRQHandler
SPIFI_IRQHandler
SGPIO_IRQHandler
PIN_INT0_IRQHandler
PIN_INT1_IRQHandler
PIN_INT2_IRQHandler
PIN_INT3_IRQHandler
PIN_INT4_IRQHandler
PIN_INT5_IRQHandler
PIN_INT6_IRQHandler
PIN_INT7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
EVENTROUTER_IRQHandler
C_CAN1_IRQHandler
ADCHS_IRQHandler
ATIMER_IRQHandler
RTC_IRQHandler
WWDT_IRQHandler
M0SUB_IRQHandler
C_CAN0_IRQHandler
QEI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

938
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4322_Cortex-M4/system_LPC43xx.c vendored Normal file
View File

@@ -0,0 +1,938 @@
/* -----------------------------------------------------------------------------
* Copyright (c) 2013 - 2017 ARM Ltd.
*
* This software is provided 'as-is', without any express or implied warranty.
* In no event will the authors be held liable for any damages arising from
* the use of this software. Permission is granted to anyone to use this
* software for any purpose, including commercial applications, and to alter
* it and redistribute it freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software in
* a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
*
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
*
* 3. This notice may not be removed or altered from any source distribution.
*
* $Date: 10. September 2018
* $Revision: V1.0.3
*
* Project: NXP LPC43xx System initialization
* -------------------------------------------------------------------------- */
#include "LPC43xx.h"
/*----------------------------------------------------------------------------
This file configures the clocks as follows:
-----------------------------------------------------------------------------
Clock Unit | Output clock | Source clock | Note
-----------------------------------------------------------------------------
PLL0USB | 480 MHz | XTAL | External crystal @ 12 MHz
-----------------------------------------------------------------------------
PLL1 | 180 MHz | XTAL | External crystal @ 12 MHz
-----------------------------------------------------------------------------
CPU | 180 MHz | PLL1 | CPU Clock == BASE_M4_CLK
-----------------------------------------------------------------------------
IDIV A | 60 MHz | PLL1 | To the USB1 peripheral
-----------------------------------------------------------------------------
IDIV B | 25 MHz | ENET_TX_CLK | ENET_TX_CLK @ 50MHz
-----------------------------------------------------------------------------
IDIV C | 12 MHz | IRC | Internal oscillator @ 12 MHz
-----------------------------------------------------------------------------
IDIV D | 12 MHz | IRC | Internal oscillator @ 12 MHz
-----------------------------------------------------------------------------
IDIV E | 5.3 MHz | PLL1 | To the LCD controller
-----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
Clock source selection definitions (do not change)
*----------------------------------------------------------------------------*/
#define CLK_SRC_32KHZ 0x00
#define CLK_SRC_IRC 0x01
#define CLK_SRC_ENET_RX 0x02
#define CLK_SRC_ENET_TX 0x03
#define CLK_SRC_GP_CLKIN 0x04
#define CLK_SRC_XTAL 0x06
#define CLK_SRC_PLL0U 0x07
#define CLK_SRC_PLL0A 0x08
#define CLK_SRC_PLL1 0x09
#define CLK_SRC_IDIVA 0x0C
#define CLK_SRC_IDIVB 0x0D
#define CLK_SRC_IDIVC 0x0E
#define CLK_SRC_IDIVD 0x0F
#define CLK_SRC_IDIVE 0x10
/*----------------------------------------------------------------------------
Define external input frequency values
*----------------------------------------------------------------------------*/
#define CLK_32KHZ 32768UL /* 32 kHz oscillator frequency */
#define CLK_IRC 12000000UL /* Internal oscillator frequency */
#define CLK_ENET_RX 50000000UL /* Ethernet Rx frequency */
#define CLK_ENET_TX 50000000UL /* Ethernet Tx frequency */
#define CLK_GP_CLKIN 12000000UL /* General purpose clock input freq. */
#define CLK_XTAL 12000000UL /* Crystal oscilator frequency */
/*----------------------------------------------------------------------------
Define clock sources
*----------------------------------------------------------------------------*/
#define PLL1_CLK_SEL CLK_SRC_XTAL /* PLL1 input clock: XTAL */
#define PLL0USB_CLK_SEL CLK_SRC_XTAL /* PLL0USB input clock: XTAL */
#define IDIVA_CLK_SEL CLK_SRC_PLL1 /* IDIVA input clock: PLL1 */
#define IDIVB_CLK_SEL CLK_SRC_ENET_TX /* IDIVB input clock: ENET TX */
#define IDIVC_CLK_SEL CLK_SRC_IRC /* IDIVC input clock: IRC */
#define IDIVD_CLK_SEL CLK_SRC_IRC /* IDIVD input clock: IRC */
#define IDIVE_CLK_SEL CLK_SRC_PLL1 /* IDIVD input clock: PLL1 */
/*----------------------------------------------------------------------------
Configure integer divider values
*----------------------------------------------------------------------------*/
#define IDIVA_IDIV 2 /* Divide input clock by 3 */
#define IDIVB_IDIV 1 /* Divide input clock by 2 */
#define IDIVC_IDIV 0 /* Divide input clock by 1 */
#define IDIVD_IDIV 0 /* Divide input clock by 1 */
#define IDIVE_IDIV 33 /* Divide input clock by 34 */
/*----------------------------------------------------------------------------
Define CPU clock input
*----------------------------------------------------------------------------*/
#define CPU_CLK_SEL CLK_SRC_PLL1 /* Default CPU clock source is PLL1 */
/*----------------------------------------------------------------------------
Configure external memory controller options
*----------------------------------------------------------------------------*/
#define USE_EXT_STAT_MEM_CS0 1 /* Use ext. static memory with CS0 */
#define USE_EXT_DYN_MEM_CS0 1 /* Use ext. dynamic memory with CS0 */
/*----------------------------------------------------------------------------
* Configure PLL1
*----------------------------------------------------------------------------
* Integer mode:
* - PLL1_DIRECT = 0 (Post divider enabled)
* - PLL1_FBSEL = 1 (Feedback divider runs from PLL output)
* - Output frequency:
* FCLKOUT = (FCLKIN / N) * M
* FCCO = FCLKOUT * 2 * P
*
* Non-integer:
* - PLL1_DIRECT = 0 (Post divider enabled)
* - PLL1_FBSEL = 0 (Feedback divider runs from CCO clock)
* - Output frequency:
* FCLKOUT = (FCLKIN / N) * M / (2 * P)
* FCCO = FCLKOUT * 2 * P
*
* Direct mode:
* - PLL1_DIRECT = 1 (Post divider disabled)
* - PLL1_FBSEL = dont care (Feedback divider runs from CCO clock)
* - Output frequency:
* FCLKOUT = (FCLKIN / N) * M
* FCCO = FCLKOUT
*
*----------------------------------------------------------------------------
* PLL1 requirements:
* | Frequency | Minimum | Maximum | Note |
* | FCLKIN | 1MHz | 25MHz | Clock source is external crystal |
* | FCLKIN | 1MHz | 50MHz | |
* | FCCO | 156MHz | 320MHz | |
* | FCLKOUT | 9.75MHz | 320MHz | |
*----------------------------------------------------------------------------
* Configuration examples:
* | Fclkout | Fcco | N | M | P | DIRECT | FBSEL | BYPASS |
* | 36MHz | 288MHz | 1 | 24 | 4 | 0 | 0 | 0 |
* | 72MHz | 288MHz | 1 | 24 | 2 | 0 | 0 | 0 |
* | 100MHz | 200MHz | 3 | 50 | 1 | 0 | 0 | 0 |
* | 120MHz | 240MHz | 1 | 20 | 1 | 0 | 0 | 0 |
* | 160MHz | 160MHz | 3 | 40 | x | 1 | 0 | 0 |
* | 180MHz | 180MHz | 1 | 15 | x | 1 | 0 | 0 |
* | 204MHz | 204MHz | 1 | 17 | x | 1 | 0 | 0 |
*----------------------------------------------------------------------------
* Relations beetwen PLL dividers and definitions:
* N = PLL1_NSEL + 1, M = PLL1_MSEL + 1, P = 2 ^ PLL1_PSEL
*----------------------------------------------------------------------------*/
/* PLL1 output clock: 180MHz, Fcco: 180MHz, N = 1, M = 15, P = x */
#define PLL1_NSEL 0 /* Range [0 - 3]: Pre-divider ratio N */
#define PLL1_MSEL 14 /* Range [0 - 255]: Feedback-divider ratio M */
#define PLL1_PSEL 0 /* Range [0 - 3]: Post-divider ratio P */
#define PLL1_BYPASS 0 /* 0: Use PLL, 1: PLL is bypassed */
#define PLL1_DIRECT 1 /* 0: Use PSEL, 1: Don't use PSEL */
#define PLL1_FBSEL 0 /* 0: FCCO is used as PLL feedback */
/* 1: FCLKOUT is used as PLL feedback */
/*----------------------------------------------------------------------------
* Configure Flash Accelerator
*----------------------------------------------------------------------------
* Flash acces time:
* | CPU clock | FLASHTIM |
* | up to 21MHz | 0 |
* | up to 43MHz | 1 |
* | up to 64MHz | 2 |
* | up to 86MHz | 3 |
* | up to 107MHz | 4 |
* | up to 129MHz | 5 |
* | up to 150MHz | 6 |
* | up to 172MHz | 7 |
* | up to 193MHz | 8 |
* | up to 204MHz | 9 |
*----------------------------------------------------------------------------*/
#define FLASHCFG_FLASHTIM 9
/*----------------------------------------------------------------------------
* Configure PLL0USB
*----------------------------------------------------------------------------
*
* Normal operating mode without post-divider and without pre-divider
* - PLL0USB_DIRECTI = 1
* - PLL0USB_DIRECTO = 1
* - PLL0USB_BYPASS = 0
* - Output frequency:
* FOUT = FIN * 2 * M
* FCCO = FOUT
*
* Normal operating mode with post-divider and without pre-divider
* - PLL0USB_DIRECTI = 1
* - PLL0USB_DIRECTO = 0
* - PLL0USB_BYPASS = 0
* - Output frequency:
* FOUT = FIN * (M / P)
* FCCO = FOUT * 2 * P
*
* Normal operating mode without post-divider and with pre-divider
* - PLL0USB_DIRECTI = 0
* - PLL0USB_DIRECTO = 1
* - PLL0USB_BYPASS = 0
* - Output frequency:
* FOUT = FIN * 2 * M / N
* FCCO = FOUT
*
* Normal operating mode with post-divider and with pre-divider
* - PLL0USB_DIRECTI = 0
* - PLL0USB_DIRECTO = 0
* - PLL0USB_BYPASS = 0
* - Output frequency:
* FOUT = FIN * M / (P * N)
* FCCO = FOUT * 2 * P
*----------------------------------------------------------------------------
* PLL0 requirements:
* | Frequency | Minimum | Maximum | Note |
* | FCLKIN | 14kHz | 25MHz | Clock source is external crystal |
* | FCLKIN | 14kHz | 150MHz | |
* | FCCO | 275MHz | 550MHz | |
* | FCLKOUT | 4.3MHz | 550MHz | |
*----------------------------------------------------------------------------
* Configuration examples:
* | Fclkout | Fcco | N | M | P | DIRECTI | DIRECTO | BYPASS |
* | 120MHz | 480MHz | x | 20 | 2 | 1 | 0 | 0 |
* | 480MHz | 480MHz | 1 | 20 | 1 | 1 | 1 | 0 |
*----------------------------------------------------------------------------*/
/* PLL0USB output clock: 480MHz, Fcco: 480MHz, N = 1, M = 20, P = 1 */
#define PLL0USB_N 1 /* Range [1 - 256]: Pre-divider */
#define PLL0USB_M 20 /* Range [1 - 2^15]: Feedback-divider */
#define PLL0USB_P 1 /* Range [1 - 32]: Post-divider */
#define PLL0USB_DIRECTI 1 /* 0: Use N_DIV, 1: Don't use N_DIV */
#define PLL0USB_DIRECTO 1 /* 0: Use P_DIV, 1: Don't use P_DIV */
#define PLL0USB_BYPASS 0 /* 0: Use PLL, 1: PLL is bypassed */
/*----------------------------------------------------------------------------
End of configuration
*----------------------------------------------------------------------------*/
/* PLL0 Setting Check */
#if (PLL0USB_BYPASS == 0)
#if (PLL0USB_CLK_SEL == CLK_SRC_XTAL)
#define PLL0USB_CLKIN CLK_XTAL
#else
#define PLL0USB_CLKIN CLK_IRC
#endif
#if ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 1)) /* Mode 1a */
#define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M)
#define PLL0USB_FCCO (PLL0USB_FOUT)
#elif ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 0)) /* Mode 1b */
#define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / PLL0USB_P)
#define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
#elif ((PLL0USB_DIRECTI == 0) && (PLL0USB_DIRECTO == 1)) /* Mode 1c */
#define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M / PLL0USB_N)
#define PLL0USB_FCCO (PLL0USB_FOUT)
#else /* Mode 1d */
#define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / (PLL0USB_P * PLL0USB_N))
#define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
#endif
#if (PLL0USB_FCCO < 275000000UL || PLL0USB_FCCO > 550000000UL)
#error "PLL0USB Fcco frequency out of range! (275MHz >= Fcco <= 550MHz)"
#endif
#if (PLL0USB_FOUT < 4300000UL || PLL0USB_FOUT > 550000000UL)
#error "PLL0USB output frequency out of range! (4.3MHz >= Fclkout <= 550MHz)"
#endif
#endif
/* PLL1 Setting Check */
#if (PLL1_BYPASS == 0)
#if (PLL1_CLK_SEL == CLK_SRC_XTAL)
#define PLL1_CLKIN CLK_XTAL
#else
#define PLL1_CLKIN CLK_IRC
#endif
#if (PLL1_DIRECT == 1) /* Direct Mode */
#define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
#define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
#elif (PLL1_FBSEL == 1) /* Integer Mode */
#define PLL1_FCCO ((2 * (1 << PLL1_PSEL)) * (PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
#define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
#else /* Noninteger Mode */
#define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
#define PLL1_FOUT (PLL1_FCCO / (2 * (1 << PLL1_PSEL)))
#endif
#if (PLL1_FCCO < 156000000UL || PLL1_FCCO > 320000000UL)
#error "PLL1 Fcco frequency out of range! (156MHz >= Fcco <= 320MHz)"
#endif
#if (PLL1_FOUT < 9750000UL || PLL1_FOUT > 204000000UL)
#error "PLL1 output frequency out of range! (9.75MHz >= Fclkout <= 204MHz)"
#endif
#endif
/*----------------------------------------------------------------------------
System Core Clock variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = 180000000U; /* System Clock Frequency (Core Clock) */
/******************************************************************************
* SetClock
******************************************************************************/
void SetClock (void) {
uint32_t x, i;
uint32_t selp, seli;
/* Set flash accelerator configuration for bank A and B to reset value */
LPC_CREG->FLASHCFGA |= (0xF << 12);
LPC_CREG->FLASHCFGB |= (0xF << 12);
/* Set flash wait states to maximum */
LPC_EMC->STATICWAITRD0 = 0x1F;
/* Switch BASE_M4_CLOCK to IRC */
LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */
(CLK_SRC_IRC << 24) ; /* Set clock source */
/* Configure input to crystal oscilator */
LPC_CGU->XTAL_OSC_CTRL = (0 << 0) | /* Enable oscillator-pad */
(0 << 1) | /* Operation with crystal connected */
(0 << 2) ; /* Low-frequency mode */
/* Wait ~250us @ 12MHz */
for (i = 1500; i; i--);
#if (USE_SPIFI)
/* configure SPIFI clk to IRC via IDIVA (later IDIVA is configured to PLL1/3) */
LPC_CGU->IDIVA_CTRL = (0 << 0) | /* Disable Power-down */
(0 << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(CLK_SRC_IRC << 24) ; /* Clock source */
LPC_CGU->BASE_SPIFI_CLK = (0 << 0) | /* Disable Power-down */
(0 << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(CLK_SRC_IDIVA << 24) ; /* Clock source */
#endif
/*----------------------------------------------------------------------------
PLL1 Setup
*----------------------------------------------------------------------------*/
/* Power down PLL */
LPC_CGU->PLL1_CTRL |= 1;
#if ((PLL1_FOUT > 110000000UL) && (CPU_CLK_SEL == CLK_SRC_PLL1))
/* To run at full speed, CPU must first run at an intermediate speed */
LPC_CGU->PLL1_CTRL = (0 << 0) | /* PLL1 Enabled */
(PLL1_BYPASS << 1) | /* CCO out sent to post-dividers */
(PLL1_FBSEL << 6) | /* PLL output used as feedback */
(0 << 7) | /* Direct on/off */
(PLL1_PSEL << 8) | /* PSEL */
(0 << 11)| /* Autoblock Disabled */
(PLL1_NSEL << 12)| /* NSEL */
(PLL1_MSEL << 16)| /* MSEL */
(PLL1_CLK_SEL << 24); /* Clock source */
/* Wait for lock */
while (!(LPC_CGU->PLL1_STAT & 1));
/* CPU base clock is in the mid frequency range before final clock set */
LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */
(0x09 << 24) ; /* Clock source: PLL1 */
/* Max. BASE_M4_CLK frequency here is 102MHz, wait at least 20us */
for (i = 1050; i; i--); /* Wait minimum 2100 cycles */
#endif
/* Configure PLL1 */
LPC_CGU->PLL1_CTRL = (0 << 0) | /* PLL1 Enabled */
(PLL1_BYPASS << 1) | /* CCO out sent to post-dividers */
(PLL1_FBSEL << 6) | /* PLL output used as feedback */
(PLL1_DIRECT << 7) | /* Direct on/off */
(PLL1_PSEL << 8) | /* PSEL */
(1 << 11)| /* Autoblock En */
(PLL1_NSEL << 12)| /* NSEL */
(PLL1_MSEL << 16)| /* MSEL */
(PLL1_CLK_SEL << 24); /* Clock source */
/* Wait for lock */
while (!(LPC_CGU->PLL1_STAT & 1));
/* Set CPU base clock source */
LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */
(CPU_CLK_SEL << 24) ; /* Set clock source */
/* Set flash accelerator configuration for internal flash bank A and B */
LPC_CREG->FLASHCFGA = (LPC_CREG->FLASHCFGA & (~0x0000F000)) | (FLASHCFG_FLASHTIM << 12);
LPC_CREG->FLASHCFGB = (LPC_CREG->FLASHCFGB & (~0x0000F000)) | (FLASHCFG_FLASHTIM << 12);
/*----------------------------------------------------------------------------
PLL0USB Setup
*----------------------------------------------------------------------------*/
/* Power down PLL0USB */
LPC_CGU->PLL0USB_CTRL |= 1;
/* M divider */
x = 0x00004000;
switch (PLL0USB_M) {
case 0: x = 0xFFFFFFFF;
break;
case 1: x = 0x00018003;
break;
case 2: x = 0x00010003;
break;
default:
for (i = PLL0USB_M; i <= 0x8000; i++) {
x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF);
}
}
if (PLL0USB_M < 60) selp = (PLL0USB_M >> 1) + 1;
else selp = 31;
if (PLL0USB_M > 16384) seli = 1;
else if (PLL0USB_M > 8192) seli = 2;
else if (PLL0USB_M > 2048) seli = 4;
else if (PLL0USB_M >= 501) seli = 8;
else if (PLL0USB_M >= 60) seli = 4 * (1024 / (PLL0USB_M + 9));
else seli = (PLL0USB_M & 0x3C) + 4;
LPC_CGU->PLL0USB_MDIV = (selp << 17) |
(seli << 22) |
(x << 0);
/* N divider */
x = 0x80;
switch (PLL0USB_N) {
case 0: x = 0xFFFFFFFF;
break;
case 1: x = 0x00000302;
break;
case 2: x = 0x00000202;
break;
default:
for (i = PLL0USB_N; i <= 0x0100; i++) {
x =(((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
}
}
LPC_CGU->PLL0USB_NP_DIV = (x << 12);
/* P divider */
x = 0x10;
switch (PLL0USB_P) {
case 0: x = 0xFFFFFFFF;
break;
case 1: x = 0x00000062;
break;
case 2: x = 0x00000042;
break;
default:
for (i = PLL0USB_P; i <= 0x200; i++) {
x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) &0x0F);
}
}
LPC_CGU->PLL0USB_NP_DIV |= x;
LPC_CGU->PLL0USB_CTRL = (PLL0USB_CLK_SEL << 24) | /* Clock source sel */
(1 << 11) | /* Autoblock En */
(1 << 4 ) | /* PLL0USB clock en */
(PLL0USB_DIRECTO << 3 ) | /* Direct output */
(PLL0USB_DIRECTI << 2 ) | /* Direct input */
(PLL0USB_BYPASS << 1 ) | /* PLL bypass */
(0 << 0 ) ; /* PLL0USB Enabled */
while (!(LPC_CGU->PLL0USB_STAT & 1));
/*----------------------------------------------------------------------------
Integer divider Setup
*----------------------------------------------------------------------------*/
/* Configure integer dividers */
LPC_CGU->IDIVA_CTRL = (0 << 0) | /* Disable Power-down */
(IDIVA_IDIV << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(IDIVA_CLK_SEL << 24) ; /* Clock source */
LPC_CGU->IDIVB_CTRL = (0 << 0) | /* Disable Power-down */
(IDIVB_IDIV << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(IDIVB_CLK_SEL << 24) ; /* Clock source */
LPC_CGU->IDIVC_CTRL = (0 << 0) | /* Disable Power-down */
(IDIVC_IDIV << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(IDIVC_CLK_SEL << 24) ; /* Clock source */
LPC_CGU->IDIVD_CTRL = (0 << 0) | /* Disable Power-down */
(IDIVD_IDIV << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(IDIVD_CLK_SEL << 24) ; /* Clock source */
LPC_CGU->IDIVE_CTRL = (0 << 0) | /* Disable Power-down */
(IDIVE_IDIV << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(IDIVE_CLK_SEL << 24) ; /* Clock source */
}
/*----------------------------------------------------------------------------
Approximate delay function (must be used after SystemCoreClockUpdate() call)
*----------------------------------------------------------------------------*/
#define CPU_NANOSEC(x) (((uint64_t)(x) * SystemCoreClock)/1000000000)
static void WaitUs (uint32_t us) {
uint32_t cyc = us * CPU_NANOSEC(1000)/4;
while(cyc--);
}
/*----------------------------------------------------------------------------
External Memory Controller Definitions
*----------------------------------------------------------------------------*/
#define SDRAM_ADDR_BASE 0x28000000 /* SDRAM base address */
/* Write Mode register macro */
#define WR_MODE(x) (*((volatile uint32_t *)(SDRAM_ADDR_BASE | (x))))
/* Pin Settings: Glith filter DIS, Input buffer EN, Fast Slew Rate, No Pullup */
#define EMC_PIN_SET ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4))
#define EMC_NANOSEC(ns, freq, div) (((uint64_t)(ns) * ((freq)/((div)+1)))/1000000000)
#define EMC_CLK_DLY_TIM_2 (0x7777) /* 3.5 ns delay for the EMC clock out */
#define EMC_CLK_DLY_TIM_0 (0x0000) /* No delay for the EMC clock out */
typedef void (*emcdivby2) (volatile uint32_t *creg6, volatile uint32_t *emcdiv, uint32_t cfg);
const uint16_t emcdivby2_opc[] = {
0x6803, /* LDR R3,[R0,#0] ; Load CREG6 */
0xF443,0x3380, /* ORR R3,R3,#0x10000 ; Set Divided by 2 */
0x6003, /* STR R3,[R0,#0] ; Store CREG6 */
0x600A, /* STR R2,[R1,#0] ; EMCDIV_CFG = cfg */
0x684B, /* loop LDR R3,[R1,#4] ; Load EMCDIV_STAT */
0x07DB, /* LSLS R3,R3,#31 ; Check EMCDIV_STAT.0 */
0xD0FC, /* BEQ loop ; Jump if 0 */
0x4770, /* BX LR ; Exit */
0,
};
#define emcdivby2_szw ((sizeof(emcdivby2_opc)+3)/4)
#define emcdivby2_ram 0x10000000
/*----------------------------------------------------------------------------
Initialize external memory controller
*----------------------------------------------------------------------------*/
void SystemInit_ExtMemCtl (void) {
uint32_t emcdivby2_buf[emcdivby2_szw];
uint32_t div, n;
/* Select and enable EMC branch clock */
LPC_CCU1->CLK_M4_EMC_CFG = (1 << 2) | (1 << 1) | 1;
while (!(LPC_CCU1->CLK_M4_EMC_STAT & 1));
/* Set EMC clock output delay */
if (SystemCoreClock < 80000000UL) {
LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_0; /* No EMC clock out delay */
}
else {
LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_2; /* 2.0 ns EMC clock out delay */
}
/* Configure EMC port pins */
LPC_SCU->SFSP1_0 = EMC_PIN_SET | 2; /* P1_0: A5 */
LPC_SCU->SFSP1_1 = EMC_PIN_SET | 2; /* P1_1: A6 */
LPC_SCU->SFSP1_2 = EMC_PIN_SET | 2; /* P1_2: A7 */
LPC_SCU->SFSP1_3 = EMC_PIN_SET | 3; /* P1_3: OE */
LPC_SCU->SFSP1_4 = EMC_PIN_SET | 3; /* P1_4: BLS0 */
LPC_SCU->SFSP1_5 = EMC_PIN_SET | 3; /* P1_5: CS0 */
LPC_SCU->SFSP1_6 = EMC_PIN_SET | 3; /* P1_6: WE */
LPC_SCU->SFSP1_7 = EMC_PIN_SET | 3; /* P1_7: D0 */
LPC_SCU->SFSP1_8 = EMC_PIN_SET | 3; /* P1_8: D1 */
LPC_SCU->SFSP1_9 = EMC_PIN_SET | 3; /* P1_9: D2 */
LPC_SCU->SFSP1_10 = EMC_PIN_SET | 3; /* P1_10: D3 */
LPC_SCU->SFSP1_11 = EMC_PIN_SET | 3; /* P1_11: D4 */
LPC_SCU->SFSP1_12 = EMC_PIN_SET | 3; /* P1_12: D5 */
LPC_SCU->SFSP1_13 = EMC_PIN_SET | 3; /* P1_13: D6 */
LPC_SCU->SFSP1_14 = EMC_PIN_SET | 3; /* P1_14: D7 */
LPC_SCU->SFSP2_0 = EMC_PIN_SET | 2; /* P2_0: A13 */
LPC_SCU->SFSP2_1 = EMC_PIN_SET | 2; /* P2_1: A12 */
LPC_SCU->SFSP2_2 = EMC_PIN_SET | 2; /* P2_2: A11 */
LPC_SCU->SFSP2_6 = EMC_PIN_SET | 2; /* P2_6: A10 */
LPC_SCU->SFSP2_7 = EMC_PIN_SET | 3; /* P2_7: A9 */
LPC_SCU->SFSP2_8 = EMC_PIN_SET | 3; /* P2_8: A8 */
LPC_SCU->SFSP2_9 = EMC_PIN_SET | 3; /* P2_9: A0 */
LPC_SCU->SFSP2_10 = EMC_PIN_SET | 3; /* P2_10: A1 */
LPC_SCU->SFSP2_11 = EMC_PIN_SET | 3; /* P2_11: A2 */
LPC_SCU->SFSP2_12 = EMC_PIN_SET | 3; /* P2_12: A3 */
LPC_SCU->SFSP2_13 = EMC_PIN_SET | 3; /* P2_13: A4 */
LPC_SCU->SFSP5_0 = EMC_PIN_SET | 2; /* P5_0: D12 */
LPC_SCU->SFSP5_1 = EMC_PIN_SET | 2; /* P5_1: D13 */
LPC_SCU->SFSP5_2 = EMC_PIN_SET | 2; /* P5_2: D14 */
LPC_SCU->SFSP5_3 = EMC_PIN_SET | 2; /* P5_3: D15 */
LPC_SCU->SFSP5_4 = EMC_PIN_SET | 2; /* P5_4: D8 */
LPC_SCU->SFSP5_5 = EMC_PIN_SET | 2; /* P5_5: D9 */
LPC_SCU->SFSP5_6 = EMC_PIN_SET | 2; /* P5_6: D10 */
LPC_SCU->SFSP5_7 = EMC_PIN_SET | 2; /* P5_7: D11 */
LPC_SCU->SFSP6_1 = EMC_PIN_SET | 1; /* P6_1: DYCS1 */
LPC_SCU->SFSP6_2 = EMC_PIN_SET | 1; /* P6_3: CKEOUT1 */
LPC_SCU->SFSP6_3 = EMC_PIN_SET | 3; /* P6_3: CS1 */
LPC_SCU->SFSP6_4 = EMC_PIN_SET | 3; /* P6_4: CAS */
LPC_SCU->SFSP6_5 = EMC_PIN_SET | 3; /* P6_5: RAS */
LPC_SCU->SFSP6_6 = EMC_PIN_SET | 1; /* P6_6: BLS1 */
LPC_SCU->SFSP6_7 = EMC_PIN_SET | 1; /* P6_7: A15 */
LPC_SCU->SFSP6_8 = EMC_PIN_SET | 1; /* P6_8: A14 */
LPC_SCU->SFSP6_9 = EMC_PIN_SET | 3; /* P6_9: DYCS0 */
LPC_SCU->SFSP6_10 = EMC_PIN_SET | 3; /* P6_10: DQMOUT1 */
LPC_SCU->SFSP6_11 = EMC_PIN_SET | 3; /* P6_11: CKEOUT0 */
LPC_SCU->SFSP6_12 = EMC_PIN_SET | 3; /* P6_12: DQMOUT0 */
LPC_SCU->SFSPA_4 = EMC_PIN_SET | 3; /* PA_4: A23 */
LPC_SCU->SFSPD_0 = EMC_PIN_SET | 2; /* PD_0: DQMOUT2 */
LPC_SCU->SFSPD_1 = EMC_PIN_SET | 2; /* PD_1: CKEOUT2 */
LPC_SCU->SFSPD_2 = EMC_PIN_SET | 2; /* PD_2: D16 */
LPC_SCU->SFSPD_3 = EMC_PIN_SET | 2; /* PD_3: D17 */
LPC_SCU->SFSPD_4 = EMC_PIN_SET | 2; /* PD_4: D18 */
LPC_SCU->SFSPD_5 = EMC_PIN_SET | 2; /* PD_5: D19 */
LPC_SCU->SFSPD_6 = EMC_PIN_SET | 2; /* PD_6: D20 */
LPC_SCU->SFSPD_7 = EMC_PIN_SET | 2; /* PD_7: D21 */
LPC_SCU->SFSPD_8 = EMC_PIN_SET | 2; /* PD_8: D22 */
LPC_SCU->SFSPD_9 = EMC_PIN_SET | 2; /* PD_9: D23 */
LPC_SCU->SFSPD_10 = EMC_PIN_SET | 2; /* PD_10: BLS3 */
LPC_SCU->SFSPD_11 = EMC_PIN_SET | 2; /* PD_11: CS3 */
LPC_SCU->SFSPD_12 = EMC_PIN_SET | 2; /* PD_12: CS2 */
LPC_SCU->SFSPD_13 = EMC_PIN_SET | 2; /* PD_13: BLS2 */
LPC_SCU->SFSPD_14 = EMC_PIN_SET | 2; /* PD_14: DYCS2 */
LPC_SCU->SFSPD_15 = EMC_PIN_SET | 2; /* PD_15: A17 */
LPC_SCU->SFSPD_16 = EMC_PIN_SET | 2; /* PD_16: A16 */
LPC_SCU->SFSPE_0 = EMC_PIN_SET | 3; /* PE_0: A18 */
LPC_SCU->SFSPE_1 = EMC_PIN_SET | 3; /* PE_1: A19 */
LPC_SCU->SFSPE_2 = EMC_PIN_SET | 3; /* PE_2: A20 */
LPC_SCU->SFSPE_3 = EMC_PIN_SET | 3; /* PE_3: A21 */
LPC_SCU->SFSPE_4 = EMC_PIN_SET | 3; /* PE_4: A22 */
LPC_SCU->SFSPE_5 = EMC_PIN_SET | 3; /* PE_5: D24 */
LPC_SCU->SFSPE_6 = EMC_PIN_SET | 3; /* PE_6: D25 */
LPC_SCU->SFSPE_7 = EMC_PIN_SET | 3; /* PE_7: D26 */
LPC_SCU->SFSPE_8 = EMC_PIN_SET | 3; /* PE_8: D27 */
LPC_SCU->SFSPE_9 = EMC_PIN_SET | 3; /* PE_9: D28 */
LPC_SCU->SFSPE_10 = EMC_PIN_SET | 3; /* PE_10: D29 */
LPC_SCU->SFSPE_11 = EMC_PIN_SET | 3; /* PE_11: D30 */
LPC_SCU->SFSPE_12 = EMC_PIN_SET | 3; /* PE_12: D31 */
LPC_SCU->SFSPE_13 = EMC_PIN_SET | 3; /* PE_13: DQMOUT3 */
LPC_SCU->SFSPE_14 = EMC_PIN_SET | 3; /* PE_14: DYCS3 */
LPC_SCU->SFSPE_15 = EMC_PIN_SET | 3; /* PE_15: CKEOUT3 */
LPC_EMC->CONTROL = 0x00000001; /* EMC Enable */
LPC_EMC->CONFIG = 0x00000000; /* Little-endian, Clock Ratio 1:1 */
div = 0;
if (SystemCoreClock > 120000000UL) {
/* Use EMC clock divider and EMC clock output delay */
div = 1;
/* Following code must be executed in RAM to ensure stable operation */
/* LPC_CCU1->CLK_M4_EMCDIV_CFG = (1 << 5) | (1 << 2) | (1 << 1) | 1; */
/* LPC_CREG->CREG6 |= (1 << 16); // EMC_CLK_DIV divided by 2 */
/* while (!(LPC_CCU1->CLK_M4_EMCDIV_STAT & 1)); */
/* This code configures EMC clock divider and is executed in RAM */
for (n = 0; n < emcdivby2_szw; n++) {
emcdivby2_buf[n] = *((uint32_t *)emcdivby2_ram + n);
*((uint32_t *)emcdivby2_ram + n) = *((uint32_t *)emcdivby2_opc + n);
}
__ISB();
((emcdivby2 )(emcdivby2_ram+1))(&LPC_CREG->CREG6, &LPC_CCU1->CLK_M4_EMCDIV_CFG, (1 << 5) | (1 << 2) | (1 << 1) | 1);
for (n = 0; n < emcdivby2_szw; n++) {
*((uint32_t *)emcdivby2_ram + n) = emcdivby2_buf[n];
}
}
/* Configure EMC clock-out pins */
LPC_SCU->SFSCLK_0 = EMC_PIN_SET | 0; /* CLK0 */
LPC_SCU->SFSCLK_1 = EMC_PIN_SET | 0; /* CLK1 */
LPC_SCU->SFSCLK_2 = EMC_PIN_SET | 0; /* CLK2 */
LPC_SCU->SFSCLK_3 = EMC_PIN_SET | 0; /* CLK3 */
/* Static memory configuration (chip select 0) */
#if (USE_EXT_STAT_MEM_CS0)
LPC_EMC->STATICCONFIG0 = (1 << 7) | /* Byte lane state: use WE signal */
(2 << 0) | /* Memory width 32-bit */
(1 << 3); /* Async page mode enable */
LPC_EMC->STATICWAITOEN0 = (0 << 0) ; /* Wait output enable: No delay */
LPC_EMC->STATICWAITPAGE0 = 2;
/* Set Static Memory Read Delay for 90ns External NOR Flash */
LPC_EMC->STATICWAITRD0 = 1 + EMC_NANOSEC(90, SystemCoreClock, div);
LPC_EMC->STATICCONFIG0 |= (1 << 19) ; /* Enable buffer */
#endif
/* Dynamic memory configuration (chip select 0) */
#if (USE_EXT_DYN_MEM_CS0)
/* Set Address mapping: 128Mb(4Mx32), 4 banks, row len = 12, column len = 8 */
LPC_EMC->DYNAMICCONFIG0 = (1 << 14) | /* AM[14] = 1 */
(0 << 12) | /* AM[12] = 0 */
(2 << 9) | /* AM[11:9] = 2 */
(2 << 7) ; /* AM[8:7] = 2 */
LPC_EMC->DYNAMICRASCAS0 = 0x00000303; /* Latency: RAS 3, CAS 3 CCLK cyc.*/
LPC_EMC->DYNAMICREADCONFIG = 0x00000001; /* Command delayed by 1/2 CCLK */
LPC_EMC->DYNAMICRP = EMC_NANOSEC (20, SystemCoreClock, div);
LPC_EMC->DYNAMICRAS = EMC_NANOSEC (42, SystemCoreClock, div);
LPC_EMC->DYNAMICSREX = EMC_NANOSEC (63, SystemCoreClock, div);
LPC_EMC->DYNAMICAPR = EMC_NANOSEC (70, SystemCoreClock, div);
LPC_EMC->DYNAMICDAL = EMC_NANOSEC (70, SystemCoreClock, div);
LPC_EMC->DYNAMICWR = EMC_NANOSEC (30, SystemCoreClock, div);
LPC_EMC->DYNAMICRC = EMC_NANOSEC (63, SystemCoreClock, div);
LPC_EMC->DYNAMICRFC = EMC_NANOSEC (63, SystemCoreClock, div);
LPC_EMC->DYNAMICXSR = EMC_NANOSEC (63, SystemCoreClock, div);
LPC_EMC->DYNAMICRRD = EMC_NANOSEC (14, SystemCoreClock, div);
LPC_EMC->DYNAMICMRD = EMC_NANOSEC (30, SystemCoreClock, div);
WaitUs (100);
LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */
WaitUs (10);
LPC_EMC->DYNAMICCONTROL = 0x00000103; /* Issue PALL command */
WaitUs (1);
LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */
WaitUs (1);
LPC_EMC->DYNAMICREFRESH = EMC_NANOSEC( 200, SystemCoreClock, div) / 16 + 1;
WaitUs (10);
LPC_EMC->DYNAMICREFRESH = EMC_NANOSEC(15625, SystemCoreClock, div) / 16 + 1;
WaitUs (10);
LPC_EMC->DYNAMICCONTROL = 0x00000083; /* Issue MODE command */
/* Mode register: Burst Length: 4, Burst Type: Sequential, CAS Latency: 3 */
WR_MODE(((3 << 4) | 2) << 12);
WaitUs (10);
LPC_EMC->DYNAMICCONTROL = 0x00000002; /* Issue NORMAL command */
LPC_EMC->DYNAMICCONFIG0 |= (1 << 19); /* Enable buffer */
#endif
}
/*----------------------------------------------------------------------------
Measure frequency using frequency monitor
*----------------------------------------------------------------------------*/
uint32_t MeasureFreq (uint32_t clk_sel) {
uint32_t fcnt, rcnt, fout;
/* Set register values */
LPC_CGU->FREQ_MON &= ~(1 << 23); /* Stop frequency counters */
LPC_CGU->FREQ_MON = (clk_sel << 24) | 511; /* RCNT == 511 */
LPC_CGU->FREQ_MON |= (1 << 23); /* Start RCNT and FCNT */
while (LPC_CGU->FREQ_MON & (1 << 23)) {
fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
rcnt = (LPC_CGU->FREQ_MON ) & 0x01FF;
if (fcnt == 0 && rcnt == 0) {
return (0); /* No input clock present */
}
}
fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
fout = fcnt * (12000000U/511U); /* FCNT * (IRC_CLK / RCNT) */
return (fout);
}
/*----------------------------------------------------------------------------
Get PLL1 (divider and multiplier) parameters
*----------------------------------------------------------------------------*/
static __inline uint32_t GetPLL1Param (void) {
uint32_t ctrl;
uint32_t p;
uint32_t div, mul;
ctrl = LPC_CGU->PLL1_CTRL;
div = ((ctrl >> 12) & 0x03) + 1;
mul = ((ctrl >> 16) & 0xFF) + 1;
p = 1 << ((ctrl >> 8) & 0x03);
if (ctrl & (1 << 1)) {
/* Bypass = 1, PLL1 input clock sent to post-dividers */
if (ctrl & (1 << 7)) {
div *= (2*p);
}
}
else {
/* Direct and integer mode */
if (((ctrl & (1 << 7)) == 0) && ((ctrl & (1 << 6)) == 0)) {
/* Non-integer mode */
div *= (2*p);
}
}
return ((div << 8) | (mul));
}
/*----------------------------------------------------------------------------
Get input clock source for specified clock generation block
*----------------------------------------------------------------------------*/
int32_t GetClkSel (uint32_t clk_src) {
uint32_t reg;
int32_t clk_sel = -1;
switch (clk_src) {
case CLK_SRC_IRC:
case CLK_SRC_ENET_RX:
case CLK_SRC_ENET_TX:
case CLK_SRC_GP_CLKIN:
return (clk_src);
case CLK_SRC_32KHZ:
return ((LPC_CREG->CREG0 & 0x0A) != 0x02) ? (-1) : (CLK_SRC_32KHZ);
case CLK_SRC_XTAL:
return (LPC_CGU->XTAL_OSC_CTRL & 1) ? (-1) : (CLK_SRC_XTAL);
case CLK_SRC_PLL0U: reg = LPC_CGU->PLL0USB_CTRL; break;
case CLK_SRC_PLL0A: reg = LPC_CGU->PLL0AUDIO_CTRL; break;
case CLK_SRC_PLL1: reg = (LPC_CGU->PLL1_STAT & 1) ? (LPC_CGU->PLL1_CTRL) : (0); break;
case CLK_SRC_IDIVA: reg = LPC_CGU->IDIVA_CTRL; break;
case CLK_SRC_IDIVB: reg = LPC_CGU->IDIVB_CTRL; break;
case CLK_SRC_IDIVC: reg = LPC_CGU->IDIVC_CTRL; break;
case CLK_SRC_IDIVD: reg = LPC_CGU->IDIVD_CTRL; break;
case CLK_SRC_IDIVE: reg = LPC_CGU->IDIVE_CTRL; break;
default:
return (clk_sel);
}
if (!(reg & 1)) {
clk_sel = (reg >> 24) & 0x1F;
}
return (clk_sel);
}
/*----------------------------------------------------------------------------
Get clock frequency for specified clock source
*----------------------------------------------------------------------------*/
uint32_t GetClockFreq (uint32_t clk_src) {
uint32_t tmp;
uint32_t mul = 1;
uint32_t div = 1;
uint32_t main_freq = 0;
int32_t clk_sel = clk_src;
do {
switch (clk_sel) {
case CLK_SRC_32KHZ: main_freq = CLK_32KHZ; break;
case CLK_SRC_IRC: main_freq = CLK_IRC; break;
case CLK_SRC_ENET_RX: main_freq = CLK_ENET_RX; break;
case CLK_SRC_ENET_TX: main_freq = CLK_ENET_TX; break;
case CLK_SRC_GP_CLKIN: main_freq = CLK_GP_CLKIN; break;
case CLK_SRC_XTAL: main_freq = CLK_XTAL; break;
case CLK_SRC_IDIVA: div *= ((LPC_CGU->IDIVA_CTRL >> 2) & 0x03) + 1; break;
case CLK_SRC_IDIVB: div *= ((LPC_CGU->IDIVB_CTRL >> 2) & 0x0F) + 1; break;
case CLK_SRC_IDIVC: div *= ((LPC_CGU->IDIVC_CTRL >> 2) & 0x0F) + 1; break;
case CLK_SRC_IDIVD: div *= ((LPC_CGU->IDIVD_CTRL >> 2) & 0x0F) + 1; break;
case CLK_SRC_IDIVE: div *= ((LPC_CGU->IDIVE_CTRL >> 2) & 0xFF) + 1; break;
case CLK_SRC_PLL0U: /* Not implemented */ break;
case CLK_SRC_PLL0A: /* Not implemented */ break;
case CLK_SRC_PLL1:
tmp = GetPLL1Param ();
mul *= (tmp ) & 0xFF; /* PLL input clock multiplier */
div *= (tmp >> 8) & 0xFF; /* PLL input clock divider */
break;
default:
return (0); /* Clock not running or not supported */
}
if (main_freq == 0) {
clk_sel = GetClkSel (clk_sel);
}
}
while (main_freq == 0);
return ((main_freq * mul) / div);
}
/*----------------------------------------------------------------------------
System Core Clock update
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) {
/* Check BASE_M4_CLK connection */
uint32_t base_src = (LPC_CGU->BASE_M4_CLK >> 24) & 0x1F;
/* Update core clock frequency */
SystemCoreClock = GetClockFreq (base_src);
}
extern uint32_t __Vectors; /* see startup_LPC43xx.s */
/*----------------------------------------------------------------------------
Initialize the system
*----------------------------------------------------------------------------*/
void SystemInit (void) {
#if (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */
#endif
/* Stop CM0 core */
LPC_RGU->RESET_CTRL1 = (1 << 24);
/* Disable SysTick timer */
SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk);
/* Set vector table pointer */
SCB->VTOR = ((uint32_t)(&__Vectors)) & 0xFFF00000UL;
/* Configure PLL0 and PLL1, connect CPU clock to selected clock source */
SetClock();
/* Update SystemCoreClock variable */
SystemCoreClockUpdate();
/* Configure External Memory Controller */
//SystemInit_ExtMemCtl ();
}

2483
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4370_Cortex-M4/RTE_Device.h vendored Normal file
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333
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4370_Cortex-M4/startup_LPC43xx.s vendored Normal file
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@@ -0,0 +1,333 @@
;/**************************************************************************//**
; * @file LPC43xx.s
; * @brief CMSIS Cortex-M4 Core Device Startup File for
; * NXP LPC43xxDevice Series
; * @version V1.00
; * @date 03. September 2013
; *
; * @note
; * Copyright (C) 2009-2013 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; * <<< Use Configuration Wizard in Context Menu >>>
; ******************************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
Sign_Value EQU 0x5A5A5A5A
__Vectors DCD __initial_sp ; 0 Top of Stack
DCD Reset_Handler ; 1 Reset Handler
DCD NMI_Handler ; 2 NMI Handler
DCD HardFault_Handler ; 3 Hard Fault Handler
DCD MemManage_Handler ; 4 MPU Fault Handler
DCD BusFault_Handler ; 5 Bus Fault Handler
DCD UsageFault_Handler ; 6 Usage Fault Handler
DCD Sign_Value ; 7 Reserved
DCD 0 ; 8 Reserved
DCD 0 ; 9 Reserved
DCD 0 ; 10 Reserved
DCD SVC_Handler ; 11 SVCall Handler
DCD DebugMon_Handler ; 12 Debug Monitor Handler
DCD 0 ; 13 Reserved
DCD PendSV_Handler ; 14 PendSV Handler
DCD SysTick_Handler ; 15 SysTick Handler
; External LPC43xx/M4 Interrupts
DCD DAC_IRQHandler ; 0 DAC interrupt
DCD M0APP_IRQHandler ; 1 Cortex-M0APP; Latched TXEV; for M4-M0APP communication
DCD DMA_IRQHandler ; 2 DMA interrupt
DCD 0 ; 3 Reserved
DCD FLASHEEPROM_IRQHandler ; 4 flash bank A, flash bank B, EEPROM ORed interrupt
DCD ETHERNET_IRQHandler ; 5 Ethernet interrupt
DCD SDIO_IRQHandler ; 6 SD/MMC interrupt
DCD LCD_IRQHandler ; 7 LCD interrupt
DCD USB0_IRQHandler ; 8 OTG interrupt
DCD USB1_IRQHandler ; 9 USB1 interrupt
DCD SCT_IRQHandler ; 10 SCT combined interrupt
DCD RITIMER_IRQHandler ; 11 RI Timer interrupt
DCD TIMER0_IRQHandler ; 12 Timer 0 interrupt
DCD TIMER1_IRQHandler ; 13 Timer 1 interrupt
DCD TIMER2_IRQHandler ; 14 Timer 2 interrupt
DCD TIMER3_IRQHandler ; 15 Timer 3 interrupt
DCD MCPWM_IRQHandler ; 16 Motor control PWM interrupt
DCD ADC0_IRQHandler ; 17 ADC0 interrupt
DCD I2C0_IRQHandler ; 18 I2C0 interrupt
DCD I2C1_IRQHandler ; 19 I2C1 interrupt
DCD SPI_IRQHandler ; 20 SPI interrupt
DCD ADC1_IRQHandler ; 21 ADC1 interrupt
DCD SSP0_IRQHandler ; 22 SSP0 interrupt
DCD SSP1_IRQHandler ; 23 SSP1 interrupt
DCD USART0_IRQHandler ; 24 USART0 interrupt
DCD UART1_IRQHandler ; 25 Combined UART1, Modem interrupt
DCD USART2_IRQHandler ; 26 USART2 interrupt
DCD USART3_IRQHandler ; 27 Combined USART3, IrDA interrupt
DCD I2S0_IRQHandler ; 28 I2S0 interrupt
DCD I2S1_IRQHandler ; 29 I2S1 interrupt
DCD SPIFI_IRQHandler ; 30 SPISI interrupt
DCD SGPIO_IRQHandler ; 31 SGPIO interrupt
DCD PIN_INT0_IRQHandler ; 32 GPIO pin interrupt 0
DCD PIN_INT1_IRQHandler ; 33 GPIO pin interrupt 1
DCD PIN_INT2_IRQHandler ; 34 GPIO pin interrupt 2
DCD PIN_INT3_IRQHandler ; 35 GPIO pin interrupt 3
DCD PIN_INT4_IRQHandler ; 36 GPIO pin interrupt 4
DCD PIN_INT5_IRQHandler ; 37 GPIO pin interrupt 5
DCD PIN_INT6_IRQHandler ; 38 GPIO pin interrupt 6
DCD PIN_INT7_IRQHandler ; 39 GPIO pin interrupt 7
DCD GINT0_IRQHandler ; 40 GPIO global interrupt 0
DCD GINT1_IRQHandler ; 41 GPIO global interrupt 1
DCD EVENTROUTER_IRQHandler ; 42 Event router interrupt
DCD C_CAN1_IRQHandler ; 43 C_CAN1 interrupt
DCD 0 ; 44 Reserved
DCD ADCHS_IRQHandler ; 45 ADCHS combined interrupt
DCD ATIMER_IRQHandler ; 46 Alarm timer interrupt
DCD RTC_IRQHandler ; 47 RTC interrupt
DCD 0 ; 48 Reserved
DCD WWDT_IRQHandler ; 49 WWDT interrupt
DCD M0SUB_IRQHandler ; 50 TXEV instruction from the M0 subsystem core interrupt
DCD C_CAN0_IRQHandler ; 51 C_CAN0 interrupt
DCD QEI_IRQHandler ; 52 QEI interrupt
;CRP address at offset 0x2FC relative to the BOOT Bank address
IF :LNOT::DEF:NO_CRP
SPACE (0x2FC - (. - __Vectors))
; EXPORT CRP_Key
CRP_Key DCD 0xFFFFFFFF
; 0xFFFFFFFF => CRP Disabled
; 0x12345678 => CRP Level 1
; 0x87654321 => CRP Level 2
; 0x43218765 => CRP Level 3 (ARE YOU SURE?)
; 0x4E697370 => NO ISP (ARE YOU SURE?)
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DAC_IRQHandler [WEAK]
EXPORT M0APP_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT FLASHEEPROM_IRQHandler [WEAK]
EXPORT ETHERNET_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT USB1_IRQHandler [WEAK]
EXPORT SCT_IRQHandler [WEAK]
EXPORT RITIMER_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT MCPWM_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT USART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT I2S0_IRQHandler [WEAK]
EXPORT I2S1_IRQHandler [WEAK]
EXPORT SPIFI_IRQHandler [WEAK]
EXPORT SGPIO_IRQHandler [WEAK]
EXPORT PIN_INT0_IRQHandler [WEAK]
EXPORT PIN_INT1_IRQHandler [WEAK]
EXPORT PIN_INT2_IRQHandler [WEAK]
EXPORT PIN_INT3_IRQHandler [WEAK]
EXPORT PIN_INT4_IRQHandler [WEAK]
EXPORT PIN_INT5_IRQHandler [WEAK]
EXPORT PIN_INT6_IRQHandler [WEAK]
EXPORT PIN_INT7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT EVENTROUTER_IRQHandler [WEAK]
EXPORT C_CAN1_IRQHandler [WEAK]
EXPORT ADCHS_IRQHandler [WEAK]
EXPORT ATIMER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT WWDT_IRQHandler [WEAK]
EXPORT M0SUB_IRQHandler [WEAK]
EXPORT C_CAN0_IRQHandler [WEAK]
EXPORT QEI_IRQHandler [WEAK]
DAC_IRQHandler
M0APP_IRQHandler
DMA_IRQHandler
FLASHEEPROM_IRQHandler
ETHERNET_IRQHandler
SDIO_IRQHandler
LCD_IRQHandler
USB0_IRQHandler
USB1_IRQHandler
SCT_IRQHandler
RITIMER_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
MCPWM_IRQHandler
ADC0_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI_IRQHandler
ADC1_IRQHandler
SSP0_IRQHandler
SSP1_IRQHandler
USART0_IRQHandler
UART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
I2S0_IRQHandler
I2S1_IRQHandler
SPIFI_IRQHandler
SGPIO_IRQHandler
PIN_INT0_IRQHandler
PIN_INT1_IRQHandler
PIN_INT2_IRQHandler
PIN_INT3_IRQHandler
PIN_INT4_IRQHandler
PIN_INT5_IRQHandler
PIN_INT6_IRQHandler
PIN_INT7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
EVENTROUTER_IRQHandler
C_CAN1_IRQHandler
ADCHS_IRQHandler
ATIMER_IRQHandler
RTC_IRQHandler
WWDT_IRQHandler
M0SUB_IRQHandler
C_CAN0_IRQHandler
QEI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

938
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/Device/LPC4370_Cortex-M4/system_LPC43xx.c vendored Normal file
View File

@@ -0,0 +1,938 @@
/* -----------------------------------------------------------------------------
* Copyright (c) 2013 - 2017 ARM Ltd.
*
* This software is provided 'as-is', without any express or implied warranty.
* In no event will the authors be held liable for any damages arising from
* the use of this software. Permission is granted to anyone to use this
* software for any purpose, including commercial applications, and to alter
* it and redistribute it freely, subject to the following restrictions:
*
* 1. The origin of this software must not be misrepresented; you must not
* claim that you wrote the original software. If you use this software in
* a product, an acknowledgment in the product documentation would be
* appreciated but is not required.
*
* 2. Altered source versions must be plainly marked as such, and must not be
* misrepresented as being the original software.
*
* 3. This notice may not be removed or altered from any source distribution.
*
* $Date: 10. September 2018
* $Revision: V1.0.3
*
* Project: NXP LPC43xx System initialization
* -------------------------------------------------------------------------- */
#include "LPC43xx.h"
/*----------------------------------------------------------------------------
This file configures the clocks as follows:
-----------------------------------------------------------------------------
Clock Unit | Output clock | Source clock | Note
-----------------------------------------------------------------------------
PLL0USB | 480 MHz | XTAL | External crystal @ 12 MHz
-----------------------------------------------------------------------------
PLL1 | 180 MHz | XTAL | External crystal @ 12 MHz
-----------------------------------------------------------------------------
CPU | 180 MHz | PLL1 | CPU Clock == BASE_M4_CLK
-----------------------------------------------------------------------------
IDIV A | 60 MHz | PLL1 | To the USB1 peripheral
-----------------------------------------------------------------------------
IDIV B | 25 MHz | ENET_TX_CLK | ENET_TX_CLK @ 50MHz
-----------------------------------------------------------------------------
IDIV C | 12 MHz | IRC | Internal oscillator @ 12 MHz
-----------------------------------------------------------------------------
IDIV D | 12 MHz | IRC | Internal oscillator @ 12 MHz
-----------------------------------------------------------------------------
IDIV E | 5.3 MHz | PLL1 | To the LCD controller
-----------------------------------------------------------------------------*/
/*----------------------------------------------------------------------------
Clock source selection definitions (do not change)
*----------------------------------------------------------------------------*/
#define CLK_SRC_32KHZ 0x00
#define CLK_SRC_IRC 0x01
#define CLK_SRC_ENET_RX 0x02
#define CLK_SRC_ENET_TX 0x03
#define CLK_SRC_GP_CLKIN 0x04
#define CLK_SRC_XTAL 0x06
#define CLK_SRC_PLL0U 0x07
#define CLK_SRC_PLL0A 0x08
#define CLK_SRC_PLL1 0x09
#define CLK_SRC_IDIVA 0x0C
#define CLK_SRC_IDIVB 0x0D
#define CLK_SRC_IDIVC 0x0E
#define CLK_SRC_IDIVD 0x0F
#define CLK_SRC_IDIVE 0x10
/*----------------------------------------------------------------------------
Define external input frequency values
*----------------------------------------------------------------------------*/
#define CLK_32KHZ 32768UL /* 32 kHz oscillator frequency */
#define CLK_IRC 12000000UL /* Internal oscillator frequency */
#define CLK_ENET_RX 50000000UL /* Ethernet Rx frequency */
#define CLK_ENET_TX 50000000UL /* Ethernet Tx frequency */
#define CLK_GP_CLKIN 12000000UL /* General purpose clock input freq. */
#define CLK_XTAL 12000000UL /* Crystal oscilator frequency */
/*----------------------------------------------------------------------------
Define clock sources
*----------------------------------------------------------------------------*/
#define PLL1_CLK_SEL CLK_SRC_XTAL /* PLL1 input clock: XTAL */
#define PLL0USB_CLK_SEL CLK_SRC_XTAL /* PLL0USB input clock: XTAL */
#define IDIVA_CLK_SEL CLK_SRC_PLL1 /* IDIVA input clock: PLL1 */
#define IDIVB_CLK_SEL CLK_SRC_ENET_TX /* IDIVB input clock: ENET TX */
#define IDIVC_CLK_SEL CLK_SRC_IRC /* IDIVC input clock: IRC */
#define IDIVD_CLK_SEL CLK_SRC_IRC /* IDIVD input clock: IRC */
#define IDIVE_CLK_SEL CLK_SRC_PLL1 /* IDIVD input clock: PLL1 */
/*----------------------------------------------------------------------------
Configure integer divider values
*----------------------------------------------------------------------------*/
#define IDIVA_IDIV 2 /* Divide input clock by 3 */
#define IDIVB_IDIV 1 /* Divide input clock by 2 */
#define IDIVC_IDIV 0 /* Divide input clock by 1 */
#define IDIVD_IDIV 0 /* Divide input clock by 1 */
#define IDIVE_IDIV 33 /* Divide input clock by 34 */
/*----------------------------------------------------------------------------
Define CPU clock input
*----------------------------------------------------------------------------*/
#define CPU_CLK_SEL CLK_SRC_PLL1 /* Default CPU clock source is PLL1 */
/*----------------------------------------------------------------------------
Configure external memory controller options
*----------------------------------------------------------------------------*/
#define USE_EXT_STAT_MEM_CS0 1 /* Use ext. static memory with CS0 */
#define USE_EXT_DYN_MEM_CS0 1 /* Use ext. dynamic memory with CS0 */
/*----------------------------------------------------------------------------
* Configure PLL1
*----------------------------------------------------------------------------
* Integer mode:
* - PLL1_DIRECT = 0 (Post divider enabled)
* - PLL1_FBSEL = 1 (Feedback divider runs from PLL output)
* - Output frequency:
* FCLKOUT = (FCLKIN / N) * M
* FCCO = FCLKOUT * 2 * P
*
* Non-integer:
* - PLL1_DIRECT = 0 (Post divider enabled)
* - PLL1_FBSEL = 0 (Feedback divider runs from CCO clock)
* - Output frequency:
* FCLKOUT = (FCLKIN / N) * M / (2 * P)
* FCCO = FCLKOUT * 2 * P
*
* Direct mode:
* - PLL1_DIRECT = 1 (Post divider disabled)
* - PLL1_FBSEL = dont care (Feedback divider runs from CCO clock)
* - Output frequency:
* FCLKOUT = (FCLKIN / N) * M
* FCCO = FCLKOUT
*
*----------------------------------------------------------------------------
* PLL1 requirements:
* | Frequency | Minimum | Maximum | Note |
* | FCLKIN | 1MHz | 25MHz | Clock source is external crystal |
* | FCLKIN | 1MHz | 50MHz | |
* | FCCO | 156MHz | 320MHz | |
* | FCLKOUT | 9.75MHz | 320MHz | |
*----------------------------------------------------------------------------
* Configuration examples:
* | Fclkout | Fcco | N | M | P | DIRECT | FBSEL | BYPASS |
* | 36MHz | 288MHz | 1 | 24 | 4 | 0 | 0 | 0 |
* | 72MHz | 288MHz | 1 | 24 | 2 | 0 | 0 | 0 |
* | 100MHz | 200MHz | 3 | 50 | 1 | 0 | 0 | 0 |
* | 120MHz | 240MHz | 1 | 20 | 1 | 0 | 0 | 0 |
* | 160MHz | 160MHz | 3 | 40 | x | 1 | 0 | 0 |
* | 180MHz | 180MHz | 1 | 15 | x | 1 | 0 | 0 |
* | 204MHz | 204MHz | 1 | 17 | x | 1 | 0 | 0 |
*----------------------------------------------------------------------------
* Relations beetwen PLL dividers and definitions:
* N = PLL1_NSEL + 1, M = PLL1_MSEL + 1, P = 2 ^ PLL1_PSEL
*----------------------------------------------------------------------------*/
/* PLL1 output clock: 180MHz, Fcco: 180MHz, N = 1, M = 15, P = x */
#define PLL1_NSEL 0 /* Range [0 - 3]: Pre-divider ratio N */
#define PLL1_MSEL 14 /* Range [0 - 255]: Feedback-divider ratio M */
#define PLL1_PSEL 0 /* Range [0 - 3]: Post-divider ratio P */
#define PLL1_BYPASS 0 /* 0: Use PLL, 1: PLL is bypassed */
#define PLL1_DIRECT 1 /* 0: Use PSEL, 1: Don't use PSEL */
#define PLL1_FBSEL 0 /* 0: FCCO is used as PLL feedback */
/* 1: FCLKOUT is used as PLL feedback */
/*----------------------------------------------------------------------------
* Configure Flash Accelerator
*----------------------------------------------------------------------------
* Flash acces time:
* | CPU clock | FLASHTIM |
* | up to 21MHz | 0 |
* | up to 43MHz | 1 |
* | up to 64MHz | 2 |
* | up to 86MHz | 3 |
* | up to 107MHz | 4 |
* | up to 129MHz | 5 |
* | up to 150MHz | 6 |
* | up to 172MHz | 7 |
* | up to 193MHz | 8 |
* | up to 204MHz | 9 |
*----------------------------------------------------------------------------*/
#define FLASHCFG_FLASHTIM 9
/*----------------------------------------------------------------------------
* Configure PLL0USB
*----------------------------------------------------------------------------
*
* Normal operating mode without post-divider and without pre-divider
* - PLL0USB_DIRECTI = 1
* - PLL0USB_DIRECTO = 1
* - PLL0USB_BYPASS = 0
* - Output frequency:
* FOUT = FIN * 2 * M
* FCCO = FOUT
*
* Normal operating mode with post-divider and without pre-divider
* - PLL0USB_DIRECTI = 1
* - PLL0USB_DIRECTO = 0
* - PLL0USB_BYPASS = 0
* - Output frequency:
* FOUT = FIN * (M / P)
* FCCO = FOUT * 2 * P
*
* Normal operating mode without post-divider and with pre-divider
* - PLL0USB_DIRECTI = 0
* - PLL0USB_DIRECTO = 1
* - PLL0USB_BYPASS = 0
* - Output frequency:
* FOUT = FIN * 2 * M / N
* FCCO = FOUT
*
* Normal operating mode with post-divider and with pre-divider
* - PLL0USB_DIRECTI = 0
* - PLL0USB_DIRECTO = 0
* - PLL0USB_BYPASS = 0
* - Output frequency:
* FOUT = FIN * M / (P * N)
* FCCO = FOUT * 2 * P
*----------------------------------------------------------------------------
* PLL0 requirements:
* | Frequency | Minimum | Maximum | Note |
* | FCLKIN | 14kHz | 25MHz | Clock source is external crystal |
* | FCLKIN | 14kHz | 150MHz | |
* | FCCO | 275MHz | 550MHz | |
* | FCLKOUT | 4.3MHz | 550MHz | |
*----------------------------------------------------------------------------
* Configuration examples:
* | Fclkout | Fcco | N | M | P | DIRECTI | DIRECTO | BYPASS |
* | 120MHz | 480MHz | x | 20 | 2 | 1 | 0 | 0 |
* | 480MHz | 480MHz | 1 | 20 | 1 | 1 | 1 | 0 |
*----------------------------------------------------------------------------*/
/* PLL0USB output clock: 480MHz, Fcco: 480MHz, N = 1, M = 20, P = 1 */
#define PLL0USB_N 1 /* Range [1 - 256]: Pre-divider */
#define PLL0USB_M 20 /* Range [1 - 2^15]: Feedback-divider */
#define PLL0USB_P 1 /* Range [1 - 32]: Post-divider */
#define PLL0USB_DIRECTI 1 /* 0: Use N_DIV, 1: Don't use N_DIV */
#define PLL0USB_DIRECTO 1 /* 0: Use P_DIV, 1: Don't use P_DIV */
#define PLL0USB_BYPASS 0 /* 0: Use PLL, 1: PLL is bypassed */
/*----------------------------------------------------------------------------
End of configuration
*----------------------------------------------------------------------------*/
/* PLL0 Setting Check */
#if (PLL0USB_BYPASS == 0)
#if (PLL0USB_CLK_SEL == CLK_SRC_XTAL)
#define PLL0USB_CLKIN CLK_XTAL
#else
#define PLL0USB_CLKIN CLK_IRC
#endif
#if ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 1)) /* Mode 1a */
#define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M)
#define PLL0USB_FCCO (PLL0USB_FOUT)
#elif ((PLL0USB_DIRECTI == 1) && (PLL0USB_DIRECTO == 0)) /* Mode 1b */
#define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / PLL0USB_P)
#define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
#elif ((PLL0USB_DIRECTI == 0) && (PLL0USB_DIRECTO == 1)) /* Mode 1c */
#define PLL0USB_FOUT (PLL0USB_CLKIN * 2 * PLL0USB_M / PLL0USB_N)
#define PLL0USB_FCCO (PLL0USB_FOUT)
#else /* Mode 1d */
#define PLL0USB_FOUT (PLL0USB_CLKIN * PLL0USB_M / (PLL0USB_P * PLL0USB_N))
#define PLL0USB_FCCO (PLL0USB_FOUT * 2 * PLL0USB_P)
#endif
#if (PLL0USB_FCCO < 275000000UL || PLL0USB_FCCO > 550000000UL)
#error "PLL0USB Fcco frequency out of range! (275MHz >= Fcco <= 550MHz)"
#endif
#if (PLL0USB_FOUT < 4300000UL || PLL0USB_FOUT > 550000000UL)
#error "PLL0USB output frequency out of range! (4.3MHz >= Fclkout <= 550MHz)"
#endif
#endif
/* PLL1 Setting Check */
#if (PLL1_BYPASS == 0)
#if (PLL1_CLK_SEL == CLK_SRC_XTAL)
#define PLL1_CLKIN CLK_XTAL
#else
#define PLL1_CLKIN CLK_IRC
#endif
#if (PLL1_DIRECT == 1) /* Direct Mode */
#define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
#define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
#elif (PLL1_FBSEL == 1) /* Integer Mode */
#define PLL1_FCCO ((2 * (1 << PLL1_PSEL)) * (PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
#define PLL1_FOUT ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
#else /* Noninteger Mode */
#define PLL1_FCCO ((PLL1_MSEL + 1) * (PLL1_CLKIN / (PLL1_NSEL + 1)))
#define PLL1_FOUT (PLL1_FCCO / (2 * (1 << PLL1_PSEL)))
#endif
#if (PLL1_FCCO < 156000000UL || PLL1_FCCO > 320000000UL)
#error "PLL1 Fcco frequency out of range! (156MHz >= Fcco <= 320MHz)"
#endif
#if (PLL1_FOUT < 9750000UL || PLL1_FOUT > 204000000UL)
#error "PLL1 output frequency out of range! (9.75MHz >= Fclkout <= 204MHz)"
#endif
#endif
/*----------------------------------------------------------------------------
System Core Clock variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = 180000000U; /* System Clock Frequency (Core Clock) */
/******************************************************************************
* SetClock
******************************************************************************/
void SetClock (void) {
uint32_t x, i;
uint32_t selp, seli;
/* Set flash accelerator configuration for bank A and B to reset value */
LPC_CREG->FLASHCFGA |= (0xF << 12);
LPC_CREG->FLASHCFGB |= (0xF << 12);
/* Set flash wait states to maximum */
LPC_EMC->STATICWAITRD0 = 0x1F;
/* Switch BASE_M4_CLOCK to IRC */
LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */
(CLK_SRC_IRC << 24) ; /* Set clock source */
/* Configure input to crystal oscilator */
LPC_CGU->XTAL_OSC_CTRL = (0 << 0) | /* Enable oscillator-pad */
(0 << 1) | /* Operation with crystal connected */
(0 << 2) ; /* Low-frequency mode */
/* Wait ~250us @ 12MHz */
for (i = 1500; i; i--);
#if (USE_SPIFI)
/* configure SPIFI clk to IRC via IDIVA (later IDIVA is configured to PLL1/3) */
LPC_CGU->IDIVA_CTRL = (0 << 0) | /* Disable Power-down */
(0 << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(CLK_SRC_IRC << 24) ; /* Clock source */
LPC_CGU->BASE_SPIFI_CLK = (0 << 0) | /* Disable Power-down */
(0 << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(CLK_SRC_IDIVA << 24) ; /* Clock source */
#endif
/*----------------------------------------------------------------------------
PLL1 Setup
*----------------------------------------------------------------------------*/
/* Power down PLL */
LPC_CGU->PLL1_CTRL |= 1;
#if ((PLL1_FOUT > 110000000UL) && (CPU_CLK_SEL == CLK_SRC_PLL1))
/* To run at full speed, CPU must first run at an intermediate speed */
LPC_CGU->PLL1_CTRL = (0 << 0) | /* PLL1 Enabled */
(PLL1_BYPASS << 1) | /* CCO out sent to post-dividers */
(PLL1_FBSEL << 6) | /* PLL output used as feedback */
(0 << 7) | /* Direct on/off */
(PLL1_PSEL << 8) | /* PSEL */
(0 << 11)| /* Autoblock Disabled */
(PLL1_NSEL << 12)| /* NSEL */
(PLL1_MSEL << 16)| /* MSEL */
(PLL1_CLK_SEL << 24); /* Clock source */
/* Wait for lock */
while (!(LPC_CGU->PLL1_STAT & 1));
/* CPU base clock is in the mid frequency range before final clock set */
LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */
(0x09 << 24) ; /* Clock source: PLL1 */
/* Max. BASE_M4_CLK frequency here is 102MHz, wait at least 20us */
for (i = 1050; i; i--); /* Wait minimum 2100 cycles */
#endif
/* Configure PLL1 */
LPC_CGU->PLL1_CTRL = (0 << 0) | /* PLL1 Enabled */
(PLL1_BYPASS << 1) | /* CCO out sent to post-dividers */
(PLL1_FBSEL << 6) | /* PLL output used as feedback */
(PLL1_DIRECT << 7) | /* Direct on/off */
(PLL1_PSEL << 8) | /* PSEL */
(1 << 11)| /* Autoblock En */
(PLL1_NSEL << 12)| /* NSEL */
(PLL1_MSEL << 16)| /* MSEL */
(PLL1_CLK_SEL << 24); /* Clock source */
/* Wait for lock */
while (!(LPC_CGU->PLL1_STAT & 1));
/* Set CPU base clock source */
LPC_CGU->BASE_M4_CLK = (0x01 << 11) | /* Autoblock En */
(CPU_CLK_SEL << 24) ; /* Set clock source */
/* Set flash accelerator configuration for internal flash bank A and B */
LPC_CREG->FLASHCFGA = (LPC_CREG->FLASHCFGA & (~0x0000F000)) | (FLASHCFG_FLASHTIM << 12);
LPC_CREG->FLASHCFGB = (LPC_CREG->FLASHCFGB & (~0x0000F000)) | (FLASHCFG_FLASHTIM << 12);
/*----------------------------------------------------------------------------
PLL0USB Setup
*----------------------------------------------------------------------------*/
/* Power down PLL0USB */
LPC_CGU->PLL0USB_CTRL |= 1;
/* M divider */
x = 0x00004000;
switch (PLL0USB_M) {
case 0: x = 0xFFFFFFFF;
break;
case 1: x = 0x00018003;
break;
case 2: x = 0x00010003;
break;
default:
for (i = PLL0USB_M; i <= 0x8000; i++) {
x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFF);
}
}
if (PLL0USB_M < 60) selp = (PLL0USB_M >> 1) + 1;
else selp = 31;
if (PLL0USB_M > 16384) seli = 1;
else if (PLL0USB_M > 8192) seli = 2;
else if (PLL0USB_M > 2048) seli = 4;
else if (PLL0USB_M >= 501) seli = 8;
else if (PLL0USB_M >= 60) seli = 4 * (1024 / (PLL0USB_M + 9));
else seli = (PLL0USB_M & 0x3C) + 4;
LPC_CGU->PLL0USB_MDIV = (selp << 17) |
(seli << 22) |
(x << 0);
/* N divider */
x = 0x80;
switch (PLL0USB_N) {
case 0: x = 0xFFFFFFFF;
break;
case 1: x = 0x00000302;
break;
case 2: x = 0x00000202;
break;
default:
for (i = PLL0USB_N; i <= 0x0100; i++) {
x =(((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
}
}
LPC_CGU->PLL0USB_NP_DIV = (x << 12);
/* P divider */
x = 0x10;
switch (PLL0USB_P) {
case 0: x = 0xFFFFFFFF;
break;
case 1: x = 0x00000062;
break;
case 2: x = 0x00000042;
break;
default:
for (i = PLL0USB_P; i <= 0x200; i++) {
x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) &0x0F);
}
}
LPC_CGU->PLL0USB_NP_DIV |= x;
LPC_CGU->PLL0USB_CTRL = (PLL0USB_CLK_SEL << 24) | /* Clock source sel */
(1 << 11) | /* Autoblock En */
(1 << 4 ) | /* PLL0USB clock en */
(PLL0USB_DIRECTO << 3 ) | /* Direct output */
(PLL0USB_DIRECTI << 2 ) | /* Direct input */
(PLL0USB_BYPASS << 1 ) | /* PLL bypass */
(0 << 0 ) ; /* PLL0USB Enabled */
while (!(LPC_CGU->PLL0USB_STAT & 1));
/*----------------------------------------------------------------------------
Integer divider Setup
*----------------------------------------------------------------------------*/
/* Configure integer dividers */
LPC_CGU->IDIVA_CTRL = (0 << 0) | /* Disable Power-down */
(IDIVA_IDIV << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(IDIVA_CLK_SEL << 24) ; /* Clock source */
LPC_CGU->IDIVB_CTRL = (0 << 0) | /* Disable Power-down */
(IDIVB_IDIV << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(IDIVB_CLK_SEL << 24) ; /* Clock source */
LPC_CGU->IDIVC_CTRL = (0 << 0) | /* Disable Power-down */
(IDIVC_IDIV << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(IDIVC_CLK_SEL << 24) ; /* Clock source */
LPC_CGU->IDIVD_CTRL = (0 << 0) | /* Disable Power-down */
(IDIVD_IDIV << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(IDIVD_CLK_SEL << 24) ; /* Clock source */
LPC_CGU->IDIVE_CTRL = (0 << 0) | /* Disable Power-down */
(IDIVE_IDIV << 2) | /* IDIV */
(1 << 11) | /* Autoblock En */
(IDIVE_CLK_SEL << 24) ; /* Clock source */
}
/*----------------------------------------------------------------------------
Approximate delay function (must be used after SystemCoreClockUpdate() call)
*----------------------------------------------------------------------------*/
#define CPU_NANOSEC(x) (((uint64_t)(x) * SystemCoreClock)/1000000000)
static void WaitUs (uint32_t us) {
uint32_t cyc = us * CPU_NANOSEC(1000)/4;
while(cyc--);
}
/*----------------------------------------------------------------------------
External Memory Controller Definitions
*----------------------------------------------------------------------------*/
#define SDRAM_ADDR_BASE 0x28000000 /* SDRAM base address */
/* Write Mode register macro */
#define WR_MODE(x) (*((volatile uint32_t *)(SDRAM_ADDR_BASE | (x))))
/* Pin Settings: Glith filter DIS, Input buffer EN, Fast Slew Rate, No Pullup */
#define EMC_PIN_SET ((1 << 7) | (1 << 6) | (1 << 5) | (1 << 4))
#define EMC_NANOSEC(ns, freq, div) (((uint64_t)(ns) * ((freq)/((div)+1)))/1000000000)
#define EMC_CLK_DLY_TIM_2 (0x7777) /* 3.5 ns delay for the EMC clock out */
#define EMC_CLK_DLY_TIM_0 (0x0000) /* No delay for the EMC clock out */
typedef void (*emcdivby2) (volatile uint32_t *creg6, volatile uint32_t *emcdiv, uint32_t cfg);
const uint16_t emcdivby2_opc[] = {
0x6803, /* LDR R3,[R0,#0] ; Load CREG6 */
0xF443,0x3380, /* ORR R3,R3,#0x10000 ; Set Divided by 2 */
0x6003, /* STR R3,[R0,#0] ; Store CREG6 */
0x600A, /* STR R2,[R1,#0] ; EMCDIV_CFG = cfg */
0x684B, /* loop LDR R3,[R1,#4] ; Load EMCDIV_STAT */
0x07DB, /* LSLS R3,R3,#31 ; Check EMCDIV_STAT.0 */
0xD0FC, /* BEQ loop ; Jump if 0 */
0x4770, /* BX LR ; Exit */
0,
};
#define emcdivby2_szw ((sizeof(emcdivby2_opc)+3)/4)
#define emcdivby2_ram 0x10000000
/*----------------------------------------------------------------------------
Initialize external memory controller
*----------------------------------------------------------------------------*/
void SystemInit_ExtMemCtl (void) {
uint32_t emcdivby2_buf[emcdivby2_szw];
uint32_t div, n;
/* Select and enable EMC branch clock */
LPC_CCU1->CLK_M4_EMC_CFG = (1 << 2) | (1 << 1) | 1;
while (!(LPC_CCU1->CLK_M4_EMC_STAT & 1));
/* Set EMC clock output delay */
if (SystemCoreClock < 80000000UL) {
LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_0; /* No EMC clock out delay */
}
else {
LPC_SCU->EMCDELAYCLK = EMC_CLK_DLY_TIM_2; /* 2.0 ns EMC clock out delay */
}
/* Configure EMC port pins */
LPC_SCU->SFSP1_0 = EMC_PIN_SET | 2; /* P1_0: A5 */
LPC_SCU->SFSP1_1 = EMC_PIN_SET | 2; /* P1_1: A6 */
LPC_SCU->SFSP1_2 = EMC_PIN_SET | 2; /* P1_2: A7 */
LPC_SCU->SFSP1_3 = EMC_PIN_SET | 3; /* P1_3: OE */
LPC_SCU->SFSP1_4 = EMC_PIN_SET | 3; /* P1_4: BLS0 */
LPC_SCU->SFSP1_5 = EMC_PIN_SET | 3; /* P1_5: CS0 */
LPC_SCU->SFSP1_6 = EMC_PIN_SET | 3; /* P1_6: WE */
LPC_SCU->SFSP1_7 = EMC_PIN_SET | 3; /* P1_7: D0 */
LPC_SCU->SFSP1_8 = EMC_PIN_SET | 3; /* P1_8: D1 */
LPC_SCU->SFSP1_9 = EMC_PIN_SET | 3; /* P1_9: D2 */
LPC_SCU->SFSP1_10 = EMC_PIN_SET | 3; /* P1_10: D3 */
LPC_SCU->SFSP1_11 = EMC_PIN_SET | 3; /* P1_11: D4 */
LPC_SCU->SFSP1_12 = EMC_PIN_SET | 3; /* P1_12: D5 */
LPC_SCU->SFSP1_13 = EMC_PIN_SET | 3; /* P1_13: D6 */
LPC_SCU->SFSP1_14 = EMC_PIN_SET | 3; /* P1_14: D7 */
LPC_SCU->SFSP2_0 = EMC_PIN_SET | 2; /* P2_0: A13 */
LPC_SCU->SFSP2_1 = EMC_PIN_SET | 2; /* P2_1: A12 */
LPC_SCU->SFSP2_2 = EMC_PIN_SET | 2; /* P2_2: A11 */
LPC_SCU->SFSP2_6 = EMC_PIN_SET | 2; /* P2_6: A10 */
LPC_SCU->SFSP2_7 = EMC_PIN_SET | 3; /* P2_7: A9 */
LPC_SCU->SFSP2_8 = EMC_PIN_SET | 3; /* P2_8: A8 */
LPC_SCU->SFSP2_9 = EMC_PIN_SET | 3; /* P2_9: A0 */
LPC_SCU->SFSP2_10 = EMC_PIN_SET | 3; /* P2_10: A1 */
LPC_SCU->SFSP2_11 = EMC_PIN_SET | 3; /* P2_11: A2 */
LPC_SCU->SFSP2_12 = EMC_PIN_SET | 3; /* P2_12: A3 */
LPC_SCU->SFSP2_13 = EMC_PIN_SET | 3; /* P2_13: A4 */
LPC_SCU->SFSP5_0 = EMC_PIN_SET | 2; /* P5_0: D12 */
LPC_SCU->SFSP5_1 = EMC_PIN_SET | 2; /* P5_1: D13 */
LPC_SCU->SFSP5_2 = EMC_PIN_SET | 2; /* P5_2: D14 */
LPC_SCU->SFSP5_3 = EMC_PIN_SET | 2; /* P5_3: D15 */
LPC_SCU->SFSP5_4 = EMC_PIN_SET | 2; /* P5_4: D8 */
LPC_SCU->SFSP5_5 = EMC_PIN_SET | 2; /* P5_5: D9 */
LPC_SCU->SFSP5_6 = EMC_PIN_SET | 2; /* P5_6: D10 */
LPC_SCU->SFSP5_7 = EMC_PIN_SET | 2; /* P5_7: D11 */
LPC_SCU->SFSP6_1 = EMC_PIN_SET | 1; /* P6_1: DYCS1 */
LPC_SCU->SFSP6_2 = EMC_PIN_SET | 1; /* P6_3: CKEOUT1 */
LPC_SCU->SFSP6_3 = EMC_PIN_SET | 3; /* P6_3: CS1 */
LPC_SCU->SFSP6_4 = EMC_PIN_SET | 3; /* P6_4: CAS */
LPC_SCU->SFSP6_5 = EMC_PIN_SET | 3; /* P6_5: RAS */
LPC_SCU->SFSP6_6 = EMC_PIN_SET | 1; /* P6_6: BLS1 */
LPC_SCU->SFSP6_7 = EMC_PIN_SET | 1; /* P6_7: A15 */
LPC_SCU->SFSP6_8 = EMC_PIN_SET | 1; /* P6_8: A14 */
LPC_SCU->SFSP6_9 = EMC_PIN_SET | 3; /* P6_9: DYCS0 */
LPC_SCU->SFSP6_10 = EMC_PIN_SET | 3; /* P6_10: DQMOUT1 */
LPC_SCU->SFSP6_11 = EMC_PIN_SET | 3; /* P6_11: CKEOUT0 */
LPC_SCU->SFSP6_12 = EMC_PIN_SET | 3; /* P6_12: DQMOUT0 */
LPC_SCU->SFSPA_4 = EMC_PIN_SET | 3; /* PA_4: A23 */
LPC_SCU->SFSPD_0 = EMC_PIN_SET | 2; /* PD_0: DQMOUT2 */
LPC_SCU->SFSPD_1 = EMC_PIN_SET | 2; /* PD_1: CKEOUT2 */
LPC_SCU->SFSPD_2 = EMC_PIN_SET | 2; /* PD_2: D16 */
LPC_SCU->SFSPD_3 = EMC_PIN_SET | 2; /* PD_3: D17 */
LPC_SCU->SFSPD_4 = EMC_PIN_SET | 2; /* PD_4: D18 */
LPC_SCU->SFSPD_5 = EMC_PIN_SET | 2; /* PD_5: D19 */
LPC_SCU->SFSPD_6 = EMC_PIN_SET | 2; /* PD_6: D20 */
LPC_SCU->SFSPD_7 = EMC_PIN_SET | 2; /* PD_7: D21 */
LPC_SCU->SFSPD_8 = EMC_PIN_SET | 2; /* PD_8: D22 */
LPC_SCU->SFSPD_9 = EMC_PIN_SET | 2; /* PD_9: D23 */
LPC_SCU->SFSPD_10 = EMC_PIN_SET | 2; /* PD_10: BLS3 */
LPC_SCU->SFSPD_11 = EMC_PIN_SET | 2; /* PD_11: CS3 */
LPC_SCU->SFSPD_12 = EMC_PIN_SET | 2; /* PD_12: CS2 */
LPC_SCU->SFSPD_13 = EMC_PIN_SET | 2; /* PD_13: BLS2 */
LPC_SCU->SFSPD_14 = EMC_PIN_SET | 2; /* PD_14: DYCS2 */
LPC_SCU->SFSPD_15 = EMC_PIN_SET | 2; /* PD_15: A17 */
LPC_SCU->SFSPD_16 = EMC_PIN_SET | 2; /* PD_16: A16 */
LPC_SCU->SFSPE_0 = EMC_PIN_SET | 3; /* PE_0: A18 */
LPC_SCU->SFSPE_1 = EMC_PIN_SET | 3; /* PE_1: A19 */
LPC_SCU->SFSPE_2 = EMC_PIN_SET | 3; /* PE_2: A20 */
LPC_SCU->SFSPE_3 = EMC_PIN_SET | 3; /* PE_3: A21 */
LPC_SCU->SFSPE_4 = EMC_PIN_SET | 3; /* PE_4: A22 */
LPC_SCU->SFSPE_5 = EMC_PIN_SET | 3; /* PE_5: D24 */
LPC_SCU->SFSPE_6 = EMC_PIN_SET | 3; /* PE_6: D25 */
LPC_SCU->SFSPE_7 = EMC_PIN_SET | 3; /* PE_7: D26 */
LPC_SCU->SFSPE_8 = EMC_PIN_SET | 3; /* PE_8: D27 */
LPC_SCU->SFSPE_9 = EMC_PIN_SET | 3; /* PE_9: D28 */
LPC_SCU->SFSPE_10 = EMC_PIN_SET | 3; /* PE_10: D29 */
LPC_SCU->SFSPE_11 = EMC_PIN_SET | 3; /* PE_11: D30 */
LPC_SCU->SFSPE_12 = EMC_PIN_SET | 3; /* PE_12: D31 */
LPC_SCU->SFSPE_13 = EMC_PIN_SET | 3; /* PE_13: DQMOUT3 */
LPC_SCU->SFSPE_14 = EMC_PIN_SET | 3; /* PE_14: DYCS3 */
LPC_SCU->SFSPE_15 = EMC_PIN_SET | 3; /* PE_15: CKEOUT3 */
LPC_EMC->CONTROL = 0x00000001; /* EMC Enable */
LPC_EMC->CONFIG = 0x00000000; /* Little-endian, Clock Ratio 1:1 */
div = 0;
if (SystemCoreClock > 120000000UL) {
/* Use EMC clock divider and EMC clock output delay */
div = 1;
/* Following code must be executed in RAM to ensure stable operation */
/* LPC_CCU1->CLK_M4_EMCDIV_CFG = (1 << 5) | (1 << 2) | (1 << 1) | 1; */
/* LPC_CREG->CREG6 |= (1 << 16); // EMC_CLK_DIV divided by 2 */
/* while (!(LPC_CCU1->CLK_M4_EMCDIV_STAT & 1)); */
/* This code configures EMC clock divider and is executed in RAM */
for (n = 0; n < emcdivby2_szw; n++) {
emcdivby2_buf[n] = *((uint32_t *)emcdivby2_ram + n);
*((uint32_t *)emcdivby2_ram + n) = *((uint32_t *)emcdivby2_opc + n);
}
__ISB();
((emcdivby2 )(emcdivby2_ram+1))(&LPC_CREG->CREG6, &LPC_CCU1->CLK_M4_EMCDIV_CFG, (1 << 5) | (1 << 2) | (1 << 1) | 1);
for (n = 0; n < emcdivby2_szw; n++) {
*((uint32_t *)emcdivby2_ram + n) = emcdivby2_buf[n];
}
}
/* Configure EMC clock-out pins */
LPC_SCU->SFSCLK_0 = EMC_PIN_SET | 0; /* CLK0 */
LPC_SCU->SFSCLK_1 = EMC_PIN_SET | 0; /* CLK1 */
LPC_SCU->SFSCLK_2 = EMC_PIN_SET | 0; /* CLK2 */
LPC_SCU->SFSCLK_3 = EMC_PIN_SET | 0; /* CLK3 */
/* Static memory configuration (chip select 0) */
#if (USE_EXT_STAT_MEM_CS0)
LPC_EMC->STATICCONFIG0 = (1 << 7) | /* Byte lane state: use WE signal */
(2 << 0) | /* Memory width 32-bit */
(1 << 3); /* Async page mode enable */
LPC_EMC->STATICWAITOEN0 = (0 << 0) ; /* Wait output enable: No delay */
LPC_EMC->STATICWAITPAGE0 = 2;
/* Set Static Memory Read Delay for 90ns External NOR Flash */
LPC_EMC->STATICWAITRD0 = 1 + EMC_NANOSEC(90, SystemCoreClock, div);
LPC_EMC->STATICCONFIG0 |= (1 << 19) ; /* Enable buffer */
#endif
/* Dynamic memory configuration (chip select 0) */
#if (USE_EXT_DYN_MEM_CS0)
/* Set Address mapping: 128Mb(4Mx32), 4 banks, row len = 12, column len = 8 */
LPC_EMC->DYNAMICCONFIG0 = (1 << 14) | /* AM[14] = 1 */
(0 << 12) | /* AM[12] = 0 */
(2 << 9) | /* AM[11:9] = 2 */
(2 << 7) ; /* AM[8:7] = 2 */
LPC_EMC->DYNAMICRASCAS0 = 0x00000303; /* Latency: RAS 3, CAS 3 CCLK cyc.*/
LPC_EMC->DYNAMICREADCONFIG = 0x00000001; /* Command delayed by 1/2 CCLK */
LPC_EMC->DYNAMICRP = EMC_NANOSEC (20, SystemCoreClock, div);
LPC_EMC->DYNAMICRAS = EMC_NANOSEC (42, SystemCoreClock, div);
LPC_EMC->DYNAMICSREX = EMC_NANOSEC (63, SystemCoreClock, div);
LPC_EMC->DYNAMICAPR = EMC_NANOSEC (70, SystemCoreClock, div);
LPC_EMC->DYNAMICDAL = EMC_NANOSEC (70, SystemCoreClock, div);
LPC_EMC->DYNAMICWR = EMC_NANOSEC (30, SystemCoreClock, div);
LPC_EMC->DYNAMICRC = EMC_NANOSEC (63, SystemCoreClock, div);
LPC_EMC->DYNAMICRFC = EMC_NANOSEC (63, SystemCoreClock, div);
LPC_EMC->DYNAMICXSR = EMC_NANOSEC (63, SystemCoreClock, div);
LPC_EMC->DYNAMICRRD = EMC_NANOSEC (14, SystemCoreClock, div);
LPC_EMC->DYNAMICMRD = EMC_NANOSEC (30, SystemCoreClock, div);
WaitUs (100);
LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */
WaitUs (10);
LPC_EMC->DYNAMICCONTROL = 0x00000103; /* Issue PALL command */
WaitUs (1);
LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */
WaitUs (1);
LPC_EMC->DYNAMICREFRESH = EMC_NANOSEC( 200, SystemCoreClock, div) / 16 + 1;
WaitUs (10);
LPC_EMC->DYNAMICREFRESH = EMC_NANOSEC(15625, SystemCoreClock, div) / 16 + 1;
WaitUs (10);
LPC_EMC->DYNAMICCONTROL = 0x00000083; /* Issue MODE command */
/* Mode register: Burst Length: 4, Burst Type: Sequential, CAS Latency: 3 */
WR_MODE(((3 << 4) | 2) << 12);
WaitUs (10);
LPC_EMC->DYNAMICCONTROL = 0x00000002; /* Issue NORMAL command */
LPC_EMC->DYNAMICCONFIG0 |= (1 << 19); /* Enable buffer */
#endif
}
/*----------------------------------------------------------------------------
Measure frequency using frequency monitor
*----------------------------------------------------------------------------*/
uint32_t MeasureFreq (uint32_t clk_sel) {
uint32_t fcnt, rcnt, fout;
/* Set register values */
LPC_CGU->FREQ_MON &= ~(1 << 23); /* Stop frequency counters */
LPC_CGU->FREQ_MON = (clk_sel << 24) | 511; /* RCNT == 511 */
LPC_CGU->FREQ_MON |= (1 << 23); /* Start RCNT and FCNT */
while (LPC_CGU->FREQ_MON & (1 << 23)) {
fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
rcnt = (LPC_CGU->FREQ_MON ) & 0x01FF;
if (fcnt == 0 && rcnt == 0) {
return (0); /* No input clock present */
}
}
fcnt = (LPC_CGU->FREQ_MON >> 9) & 0x3FFF;
fout = fcnt * (12000000U/511U); /* FCNT * (IRC_CLK / RCNT) */
return (fout);
}
/*----------------------------------------------------------------------------
Get PLL1 (divider and multiplier) parameters
*----------------------------------------------------------------------------*/
static __inline uint32_t GetPLL1Param (void) {
uint32_t ctrl;
uint32_t p;
uint32_t div, mul;
ctrl = LPC_CGU->PLL1_CTRL;
div = ((ctrl >> 12) & 0x03) + 1;
mul = ((ctrl >> 16) & 0xFF) + 1;
p = 1 << ((ctrl >> 8) & 0x03);
if (ctrl & (1 << 1)) {
/* Bypass = 1, PLL1 input clock sent to post-dividers */
if (ctrl & (1 << 7)) {
div *= (2*p);
}
}
else {
/* Direct and integer mode */
if (((ctrl & (1 << 7)) == 0) && ((ctrl & (1 << 6)) == 0)) {
/* Non-integer mode */
div *= (2*p);
}
}
return ((div << 8) | (mul));
}
/*----------------------------------------------------------------------------
Get input clock source for specified clock generation block
*----------------------------------------------------------------------------*/
int32_t GetClkSel (uint32_t clk_src) {
uint32_t reg;
int32_t clk_sel = -1;
switch (clk_src) {
case CLK_SRC_IRC:
case CLK_SRC_ENET_RX:
case CLK_SRC_ENET_TX:
case CLK_SRC_GP_CLKIN:
return (clk_src);
case CLK_SRC_32KHZ:
return ((LPC_CREG->CREG0 & 0x0A) != 0x02) ? (-1) : (CLK_SRC_32KHZ);
case CLK_SRC_XTAL:
return (LPC_CGU->XTAL_OSC_CTRL & 1) ? (-1) : (CLK_SRC_XTAL);
case CLK_SRC_PLL0U: reg = LPC_CGU->PLL0USB_CTRL; break;
case CLK_SRC_PLL0A: reg = LPC_CGU->PLL0AUDIO_CTRL; break;
case CLK_SRC_PLL1: reg = (LPC_CGU->PLL1_STAT & 1) ? (LPC_CGU->PLL1_CTRL) : (0); break;
case CLK_SRC_IDIVA: reg = LPC_CGU->IDIVA_CTRL; break;
case CLK_SRC_IDIVB: reg = LPC_CGU->IDIVB_CTRL; break;
case CLK_SRC_IDIVC: reg = LPC_CGU->IDIVC_CTRL; break;
case CLK_SRC_IDIVD: reg = LPC_CGU->IDIVD_CTRL; break;
case CLK_SRC_IDIVE: reg = LPC_CGU->IDIVE_CTRL; break;
default:
return (clk_sel);
}
if (!(reg & 1)) {
clk_sel = (reg >> 24) & 0x1F;
}
return (clk_sel);
}
/*----------------------------------------------------------------------------
Get clock frequency for specified clock source
*----------------------------------------------------------------------------*/
uint32_t GetClockFreq (uint32_t clk_src) {
uint32_t tmp;
uint32_t mul = 1;
uint32_t div = 1;
uint32_t main_freq = 0;
int32_t clk_sel = clk_src;
do {
switch (clk_sel) {
case CLK_SRC_32KHZ: main_freq = CLK_32KHZ; break;
case CLK_SRC_IRC: main_freq = CLK_IRC; break;
case CLK_SRC_ENET_RX: main_freq = CLK_ENET_RX; break;
case CLK_SRC_ENET_TX: main_freq = CLK_ENET_TX; break;
case CLK_SRC_GP_CLKIN: main_freq = CLK_GP_CLKIN; break;
case CLK_SRC_XTAL: main_freq = CLK_XTAL; break;
case CLK_SRC_IDIVA: div *= ((LPC_CGU->IDIVA_CTRL >> 2) & 0x03) + 1; break;
case CLK_SRC_IDIVB: div *= ((LPC_CGU->IDIVB_CTRL >> 2) & 0x0F) + 1; break;
case CLK_SRC_IDIVC: div *= ((LPC_CGU->IDIVC_CTRL >> 2) & 0x0F) + 1; break;
case CLK_SRC_IDIVD: div *= ((LPC_CGU->IDIVD_CTRL >> 2) & 0x0F) + 1; break;
case CLK_SRC_IDIVE: div *= ((LPC_CGU->IDIVE_CTRL >> 2) & 0xFF) + 1; break;
case CLK_SRC_PLL0U: /* Not implemented */ break;
case CLK_SRC_PLL0A: /* Not implemented */ break;
case CLK_SRC_PLL1:
tmp = GetPLL1Param ();
mul *= (tmp ) & 0xFF; /* PLL input clock multiplier */
div *= (tmp >> 8) & 0xFF; /* PLL input clock divider */
break;
default:
return (0); /* Clock not running or not supported */
}
if (main_freq == 0) {
clk_sel = GetClkSel (clk_sel);
}
}
while (main_freq == 0);
return ((main_freq * mul) / div);
}
/*----------------------------------------------------------------------------
System Core Clock update
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) {
/* Check BASE_M4_CLK connection */
uint32_t base_src = (LPC_CGU->BASE_M4_CLK >> 24) & 0x1F;
/* Update core clock frequency */
SystemCoreClock = GetClockFreq (base_src);
}
extern uint32_t __Vectors; /* see startup_LPC43xx.s */
/*----------------------------------------------------------------------------
Initialize the system
*----------------------------------------------------------------------------*/
void SystemInit (void) {
#if (__FPU_USED == 1)
SCB->CPACR |= ((3UL << 10*2) | /* set CP10 Full Access */
(3UL << 11*2) ); /* set CP11 Full Access */
#endif
/* Stop CM0 core */
LPC_RGU->RESET_CTRL1 = (1 << 24);
/* Disable SysTick timer */
SysTick->CTRL &= ~(SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk);
/* Set vector table pointer */
SCB->VTOR = ((uint32_t)(&__Vectors)) & 0xFFF00000UL;
/* Configure PLL0 and PLL1, connect CPU clock to selected clock source */
SetClock();
/* Update SystemCoreClock variable */
SystemCoreClockUpdate();
/* Configure External Memory Controller */
//SystemInit_ExtMemCtl ();
}

206
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/LPC-Link2/RTE/USB/USBD_Config_0.c vendored Normal file
View File

@@ -0,0 +1,206 @@
/*------------------------------------------------------------------------------
* MDK Middleware - Component ::USB:Device
* Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
*------------------------------------------------------------------------------
* Name: USBD_Config_0.c
* Purpose: USB Device Configuration
* Rev.: V5.2.0
*------------------------------------------------------------------------------
* Use the following configuration settings in the Device Class configuration
* files to assign a Device Class to this USB Device 0.
*
* Configuration Setting Value
* --------------------- -----
* Assign Device Class to USB Device # = 0
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>USB Device 0
// <o>Connect to hardware via Driver_USBD# <0-255>
// <i>Select driver control block for hardware interface.
#define USBD0_PORT 0
// <o.0>High-speed
// <i>Enable High-speed functionality (if device supports it).
#define USBD0_HS 1
// <h>Device Settings
// <i>These settings are used to create the Device Descriptor
// <o>Max Endpoint 0 Packet Size
// <i>Maximum packet size for Endpoint 0 (bMaxPacketSize0).
// <8=>8 Bytes <16=>16 Bytes <32=>32 Bytes <64=>64 Bytes
#define USBD0_MAX_PACKET0 64
// <o.0..15>Vendor ID <0x0000-0xFFFF>
// <i>Vendor ID assigned by USB-IF (idVendor).
#define USBD0_DEV_DESC_IDVENDOR 0xC251
// <o.0..15>Product ID <0x0000-0xFFFF>
// <i>Product ID assigned by manufacturer (idProduct).
#define USBD0_DEV_DESC_IDPRODUCT 0xF00A
// <o.0..15>Device Release Number <0x0000-0xFFFF>
// <i>Device Release Number in binary-coded decimal (bcdDevice)
#define USBD0_DEV_DESC_BCDDEVICE 0x0100
// </h>
// <h>Configuration Settings
// <i>These settings are used to create the Configuration Descriptor.
// <o.6>Power
// <i>Default Power Setting (D6: of bmAttributes).
// <0=>Bus-powered
// <1=>Self-powered
// <o.5>Remote Wakeup
// <i>Configuration support for Remote Wakeup (D5: of bmAttributes).
#define USBD0_CFG_DESC_BMATTRIBUTES 0x80
// <o.0..7>Maximum Power Consumption (in mA) <0-510><#/2>
// <i>Maximum Power Consumption of USB Device from bus in this
// <i>specific configuration when device is fully operational (bMaxPower).
#define USBD0_CFG_DESC_BMAXPOWER 250
// </h>
// <h>String Settings
// <i>These settings are used to create the String Descriptor.
// <o.0..15>Language ID <0x0000-0xFCFF>
// <i>English (United States) = 0x0409.
#define USBD0_STR_DESC_LANGID 0x0409
// <s.126>Manufacturer String
// <i>String Descriptor describing Manufacturer.
#define USBD0_STR_DESC_MAN L"KEIL - Tools By ARM"
// <s.126>Product String
// <i>String Descriptor describing Product.
#define USBD0_STR_DESC_PROD L"LPC-Link2"
// <e.0>Serial Number String
// <i>Enable Serial Number String.
// <i>If disabled Serial Number String will not be assigned to USB Device.
#define USBD0_STR_DESC_SER_EN 1
// <s.126>Default value
// <i>Default device's Serial Number String.
#define USBD0_STR_DESC_SER L"0001A0000000"
// <o.0..7>Maximum Length (in characters) <0-126>
// <i>Specifies the maximum number of Serial Number String characters that can be set at run-time.
// <i>Maximum value is 126. Use value 0 to disable RAM allocation for string.
#define USBD0_STR_DESC_SER_MAX_LEN 16
// </e>
// </h>
// <h>Microsoft OS Descriptors Settings
// <i>These settings are used to create the Microsoft OS Descriptors.
// <e.0>OS String
// <i>Enable creation of Microsoft OS String and Extended Compat ID OS Feature Descriptors.
#define USBD0_OS_DESC_EN 1
// <o.0..7>Vendor Code <0x01-0xFF>
// <i>Specifies Vendor Code used to retrieve OS Feature Descriptors.
#define USBD0_OS_DESC_VENDOR_CODE 0x01
// </e>
// </h>
// <o>Control Transfer Buffer Size <64-65536:64>
// <i>Specifies size of buffer used for Control Transfers.
// <i>It should be at least as big as maximum packet size for Endpoint 0.
#define USBD0_EP0_BUF_SIZE 128
// <h>OS Resources Settings
// <i>These settings are used to optimize usage of OS resources.
// <o>Core Thread Stack Size <64-65536>
#define USBD0_CORE_THREAD_STACK_SIZE 1024
// Core Thread Priority
#define USBD0_CORE_THREAD_PRIORITY osPriorityAboveNormal
// </h>
// </h>
#include "RTE_Components.h"
#ifdef RTE_USB_Device_CustomClass_0
#include "USBD_Config_CustomClass_0.h"
#endif
#ifdef RTE_USB_Device_CustomClass_1
#include "USBD_Config_CustomClass_1.h"
#endif
#ifdef RTE_USB_Device_CustomClass_2
#include "USBD_Config_CustomClass_2.h"
#endif
#ifdef RTE_USB_Device_CustomClass_3
#include "USBD_Config_CustomClass_3.h"
#endif
#ifdef RTE_USB_Device_HID_0
#include "USBD_Config_HID_0.h"
#endif
#ifdef RTE_USB_Device_HID_1
#include "USBD_Config_HID_1.h"
#endif
#ifdef RTE_USB_Device_HID_2
#include "USBD_Config_HID_2.h"
#endif
#ifdef RTE_USB_Device_HID_3
#include "USBD_Config_HID_3.h"
#endif
#ifdef RTE_USB_Device_MSC_0
#include "USBD_Config_MSC_0.h"
#endif
#ifdef RTE_USB_Device_MSC_1
#include "USBD_Config_MSC_1.h"
#endif
#ifdef RTE_USB_Device_MSC_2
#include "USBD_Config_MSC_2.h"
#endif
#ifdef RTE_USB_Device_MSC_3
#include "USBD_Config_MSC_3.h"
#endif
#ifdef RTE_USB_Device_CDC_0
#include "USBD_Config_CDC_0.h"
#endif
#ifdef RTE_USB_Device_CDC_1
#include "USBD_Config_CDC_1.h"
#endif
#ifdef RTE_USB_Device_CDC_2
#include "USBD_Config_CDC_2.h"
#endif
#ifdef RTE_USB_Device_CDC_3
#include "USBD_Config_CDC_3.h"
#endif
#ifdef RTE_USB_Device_CDC_4
#include "USBD_Config_CDC_4.h"
#endif
#ifdef RTE_USB_Device_CDC_5
#include "USBD_Config_CDC_5.h"
#endif
#ifdef RTE_USB_Device_CDC_6
#include "USBD_Config_CDC_6.h"
#endif
#ifdef RTE_USB_Device_CDC_7
#include "USBD_Config_CDC_7.h"
#endif
#ifdef RTE_USB_Device_ADC_0
#include "USBD_Config_ADC_0.h"
#endif
#ifdef RTE_USB_Device_ADC_1
#include "USBD_Config_ADC_1.h"
#endif
#ifdef RTE_USB_Device_ADC_2
#include "USBD_Config_ADC_2.h"
#endif
#ifdef RTE_USB_Device_ADC_3
#include "USBD_Config_ADC_3.h"
#endif
#include "usbd_config.h"

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::USB:Device
* Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
*------------------------------------------------------------------------------
* Name: USBD_Config_CDC_0.h
* Purpose: USB Device Communication Device Class (CDC) Configuration
* Rev.: V5.2.0
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>USB Device: Communication Device Class (CDC) 0
// <o>Assign Device Class to USB Device # <0-3>
// <i>Select USB Device that is used for this Device Class instance
#define USBD_CDC0_DEV 0
// <o>Communication Class Subclass
// <i>Specifies the model used by the CDC class.
// <2=>Abstract Control Model (ACM)
// <13=>Network Control Model (NCM)
#define USBD_CDC0_SUBCLASS 2
// <o>Communication Class Protocol
// <i>Specifies the protocol used by the CDC class.
// <0=>No protocol (Virtual COM)
// <255=>Vendor-specific (RNDIS)
#define USBD_CDC0_PROTOCOL 0
// <h>Interrupt Endpoint Settings
// <i>By default, the settings match the first USB Class instance in a USB Device.
// <i>Endpoint conflicts are flagged by compile-time error messages.
// <o.0..3>Interrupt IN Endpoint Number
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
#define USBD_CDC0_EP_INT_IN 3
// <h>Endpoint Settings
// <i>Parameters are used to create Endpoint Descriptors
// <i>and for memory allocation in the USB component.
// <h>Full/Low-speed (High-speed disabled)
// <i>Parameters apply when High-speed is disabled in USBD_Config_n.c
// <o.0..6>Maximum Endpoint Packet Size (in bytes) <0-64>
// <i>Specifies the physical packet size used for information exchange.
// <i>Maximum value is 64.
#define USBD_CDC0_WMAXPACKETSIZE 16
// <o.0..7>Endpoint polling Interval (in ms) <1-255>
// <i>Specifies the frequency of requests initiated by USB Host for
// <i>getting the notification.
#define USBD_CDC0_BINTERVAL 2
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in USBD_Config_n.c
//
// <o.0..10>Maximum Endpoint Packet Size (in bytes) <0-1024>
// <i>Specifies the physical packet size used for information exchange.
// <i>Maximum value is 1024.
// <o.11..12>Additional transactions per microframe
// <i>Additional transactions improve communication performance.
// <0=>None <1=>1 additional <2=>2 additional
#define USBD_CDC0_HS_WMAXPACKETSIZE 16
// <o.0..4>Endpoint polling Interval (in 125 us intervals)
// <i>Specifies the frequency of requests initiated by USB Host for
// <i>getting the notification.
// <1=> 1 <2=> 2 <3=> 4 <4=> 8
// <5=> 16 <6=> 32 <7=> 64 <8=> 128
// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048
// <13=>4096 <14=>8192 <15=>16384 <16=>32768
#define USBD_CDC0_HS_BINTERVAL 2
// </h>
// </h>
// </h>
// <h>Bulk Endpoint Settings
// <i>By default, the settings match the first USB Class instance in a USB Device.
// <i>Endpoint conflicts are flagged by compile-time error messages.
// <o.0..3>Bulk IN Endpoint Number
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
#define USBD_CDC0_EP_BULK_IN 4
// <o.0..3>Bulk OUT Endpoint Number
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
#define USBD_CDC0_EP_BULK_OUT 4
// <h>Endpoint Settings
// <i>Parameters are used to create USB Descriptors and for memory
// <i>allocation in the USB component.
//
// <h>Full/Low-speed (High-speed disabled)
// <i>Parameters apply when High-speed is disabled in USBD_Config_n.c
// <o.0..6>Maximum Endpoint Packet Size (in bytes) <8=>8 <16=>16 <32=>32 <64=>64
// <i>Specifies the physical packet size used for information exchange.
// <i>Maximum value is 64.
#define USBD_CDC0_WMAXPACKETSIZE1 64
// </h>
// <h>High-speed
// <i>Parameters apply when High-speed is enabled in USBD_Config_n.c
//
// <o.0..9>Maximum Endpoint Packet Size (in bytes) <512=>512
// <i>Specifies the physical packet size used for information exchange.
// <i>Only available value is 512.
#define USBD_CDC0_HS_WMAXPACKETSIZE1 512
// <o.0..7>Maximum NAK Rate <0-255>
// <i>Specifies the interval in which Bulk Endpoint can NAK.
// <i>Value of 0 indicates that Bulk Endpoint never NAKs.
#define USBD_CDC0_HS_BINTERVAL1 0
// </h>
// </h>
// </h>
// <h>Communication Device Class Settings
// <i>Parameters are used to create USB Descriptors and for memory allocation
// <i>in the USB component.
//
// <s.126>Communication Class Interface String
#define USBD_CDC0_CIF_STR_DESC L"USB_CDC0_0"
// <s.126>Data Class Interface String
#define USBD_CDC0_DIF_STR_DESC L"USB_CDC0_1"
// <h>Abstract Control Model Settings
// <h>Call Management Capabilities
// <i>Specifies which call management functionality is supported.
// <o.1>Call Management channel
// <0=>Communication Class Interface only
// <1=>Communication and Data Class Interface
// <o.0>Device Call Management handling
// <0=>None
// <1=>All
// </h>
#define USBD_CDC0_ACM_CM_BM_CAPABILITIES 0x03
// <h>Abstract Control Management Capabilities
// <i>Specifies which abstract control management functionality is supported.
// <o.3>D3 bit
// <i>Enabled = Supports the notification Network_Connection
// <o.2>D2 bit
// <i>Enabled = Supports the request Send_Break
// <o.1>D1 bit
// <i>Enabled = Supports the following requests: Set_Line_Coding, Get_Line_Coding,
// <i> Set_Control_Line_State, and notification Serial_State
// <o.0>D0 bit
// <i>Enabled = Supports the following requests: Set_Comm_Feature, Clear_Comm_Feature and Get_Comm_Feature
// </h>
#define USBD_CDC0_ACM_ACM_BM_CAPABILITIES 0x06
// <o>Maximum Communication Device Send Buffer Size
// <i>Specifies size of buffer used for sending of data to USB Host.
// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes
// <128=> 128 Bytes <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes
// <2048=>2048 Bytes <4096=>4096 Bytes <8192=>8192 Bytes <16384=>16384 Bytes
#define USBD_CDC0_ACM_SEND_BUF_SIZE 1024
// <o>Maximum Communication Device Receive Buffer Size
// <i>Specifies size of buffer used for receiving of data from USB Host.
// <i>Minimum size must be twice as large as Maximum Packet Size for Bulk OUT Endpoint.
// <i>Suggested size is three or more times larger then Maximum Packet Size for Bulk OUT Endpoint.
// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes
// <128=> 128 Bytes <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes
// <2048=>2048 Bytes <4096=>4096 Bytes <8192=>8192 Bytes <16384=>16384 Bytes
#define USBD_CDC0_ACM_RECEIVE_BUF_SIZE 2048
// </h>
// <h>Network Control Model Settings
// <s.12>MAC Address String
// <i>Specifies 48-bit Ethernet MAC address.
#define USBD_CDC0_NCM_MAC_ADDRESS L"1E306CA2455E"
// <h>Ethernet Statistics
// <i>Specifies Ethernet statistic functions supported.
// <o.0>XMIT_OK
// <i>Frames transmitted without errors
// <o.1>RVC_OK
// <i>Frames received without errors
// <o.2>XMIT_ERROR
// <i>Frames not transmitted, or transmitted with errors
// <o.3>RCV_ERROR
// <i>Frames received with errors that are not delivered to the USB host.
// <o.4>RCV_NO_BUFFER
// <i>Frame missed, no buffers
// <o.5>DIRECTED_BYTES_XMIT
// <i>Directed bytes transmitted without errors
// <o.6>DIRECTED_FRAMES_XMIT
// <i>Directed frames transmitted without errors
// <o.7>MULTICAST_BYTES_XMIT
// <i>Multicast bytes transmitted without errors
// <o.8>MULTICAST_FRAMES_XMIT
// <i>Multicast frames transmitted without errors
// <o.9>BROADCAST_BYTES_XMIT
// <i>Broadcast bytes transmitted without errors
// <o.10>BROADCAST_FRAMES_XMIT
// <i>Broadcast frames transmitted without errors
// <o.11>DIRECTED_BYTES_RCV
// <i>Directed bytes received without errors
// <o.12>DIRECTED_FRAMES_RCV
// <i>Directed frames received without errors
// <o.13>MULTICAST_BYTES_RCV
// <i>Multicast bytes received without errors
// <o.14>MULTICAST_FRAMES_RCV
// <i>Multicast frames received without errors
// <o.15>BROADCAST_BYTES_RCV
// <i>Broadcast bytes received without errors
// <o.16>BROADCAST_FRAMES_RCV
// <i>Broadcast frames received without errors
// <o.17>RCV_CRC_ERROR
// <i>Frames received with circular redundancy check (CRC) or frame check sequence (FCS) error
// <o.18>TRANSMIT_QUEUE_LENGTH
// <i>Length of transmit queue
// <o.19>RCV_ERROR_ALIGNMENT
// <i>Frames received with alignment error
// <o.20>XMIT_ONE_COLLISION
// <i>Frames transmitted with one collision
// <o.21>XMIT_MORE_COLLISIONS
// <i>Frames transmitted with more than one collision
// <o.22>XMIT_DEFERRED
// <i>Frames transmitted after deferral
// <o.23>XMIT_MAX_COLLISIONS
// <i>Frames not transmitted due to collisions
// <o.24>RCV_OVERRUN
// <i>Frames not received due to overrun
// <o.25>XMIT_UNDERRUN
// <i>Frames not transmitted due to underrun
// <o.26>XMIT_HEARTBEAT_FAILURE
// <i>Frames transmitted with heartbeat failure
// <o.27>XMIT_TIMES_CRS_LOST
// <i>Times carrier sense signal lost during transmission
// <o.28>XMIT_LATE_COLLISIONS
// <i>Late collisions detected
// </h>
#define USBD_CDC0_NCM_BM_ETHERNET_STATISTICS 0x00000003
// <o>Maximum Segment Size
// <i>Specifies maximum segment size that Ethernet device is capable of supporting.
// <i>Typically 1514 bytes.
#define USBD_CDC0_NCM_W_MAX_SEGMENT_SIZE 1514
// <o.15>Multicast Filtering <0=>Perfect (no hashing) <1=>Imperfect (hashing)
// <i>Specifies multicast filtering type.
// <o.0..14>Number of Multicast Filters
// <i>Specifies number of multicast filters that can be configured by the USB Host.
#define USBD_CDC0_NCM_W_NUMBER_MC_FILTERS 1
// <o.0..7>Number of Power Filters
// <i>Specifies number of pattern filters that are available for causing wake-up of the USB Host.
#define USBD_CDC0_NCM_B_NUMBER_POWER_FILTERS 0
// <h>Network Capabilities
// <i>Specifies which functions are supported.
// <o.4>SetCrcMode/GetCrcMode
// <o.3>SetMaxDatagramSize/GetMaxDatagramSize
// <o.1>SetNetAddress/GetNetAddress
// <o.0>SetEthernetPacketFilter
// </h>
#define USBD_CDC0_NCM_BM_NETWORK_CAPABILITIES 0x1B
// <h>NTB Parameters
// <i>Specifies NTB parameters reported by GetNtbParameters function.
// <h>NTB Formats Supported (bmNtbFormatsSupported)
// <i>Specifies NTB formats supported.
// <o.0>16-bit NTB (always supported)
// <o.1>32-bit NTB
// </h>
#define USBD_CDC0_NCM_BM_NTB_FORMATS_SUPPORTED 0x0001
// <h>IN Data Pipe
//
// <o>Maximum NTB Size (dwNtbInMaxSize)
// <i>Specifies maximum IN NTB size in bytes.
#define USBD_CDC0_NCM_DW_NTB_IN_MAX_SIZE 4096
// <o.0..15>NTB Datagram Payload Alignment Divisor (wNdpInDivisor)
// <i>Specifies divisor used for IN NTB Datagram payload alignment.
#define USBD_CDC0_NCM_W_NDP_IN_DIVISOR 4
// <o.0..15>NTB Datagram Payload Alignment Remainder (wNdpInPayloadRemainder)
// <i>Specifies remainder used to align input datagram payload within the NTB.
// <i>(Payload Offset) % (wNdpInDivisor) = wNdpInPayloadRemainder
#define USBD_CDC0_NCM_W_NDP_IN_PAYLOAD_REMINDER 0
// <o.0..15>NDP Alignment Modulus in NTB (wNdpInAlignment)
// <i>Specifies NDP alignment modulus for NTBs on the IN pipe.
// <i>Shall be power of 2, and shall be at least 4.
#define USBD_CDC0_NCM_W_NDP_IN_ALIGNMENT 4
// </h>
// <h>OUT Data Pipe
//
// <o>Maximum NTB Size (dwNtbOutMaxSize)
// <i>Specifies maximum OUT NTB size in bytes.
#define USBD_CDC0_NCM_DW_NTB_OUT_MAX_SIZE 4096
// <o.0..15>NTB Datagram Payload Alignment Divisor (wNdpOutDivisor)
// <i>Specifies divisor used for OUT NTB Datagram payload alignment.
#define USBD_CDC0_NCM_W_NDP_OUT_DIVISOR 4
// <o.0..15>NTB Datagram Payload Alignment Remainder (wNdpOutPayloadRemainder)
// <i>Specifies remainder used to align output datagram payload within the NTB.
// <i>(Payload Offset) % (wNdpOutDivisor) = wNdpOutPayloadRemainder
#define USBD_CDC0_NCM_W_NDP_OUT_PAYLOAD_REMINDER 0
// <o.0..15>NDP Alignment Modulus in NTB (wNdpOutAlignment)
// <i>Specifies NDP alignment modulus for NTBs on the IN pipe.
// <i>Shall be power of 2, and shall be at least 4.
#define USBD_CDC0_NCM_W_NDP_OUT_ALIGNMENT 4
// </h>
// </h>
// <o.0>Raw Data Access API
// <i>Enables or disables Raw Data Access API.
#define USBD_CDC0_NCM_RAW_ENABLE 0
// <o>IN NTB Data Buffering <1=>Single Buffer <2=>Double Buffer
// <i>Specifies buffering used for sending data to USB Host.
// <i>Not used when RAW Data Access API is enabled.
#define USBD_CDC0_NCM_NTB_IN_BUF_CNT 1
// <o>OUT NTB Data Buffering <1=>Single Buffer <2=>Double Buffer
// <i>Specifies buffering used for receiving data from USB Host.
// <i>Not used when RAW Data Access API is enabled.
#define USBD_CDC0_NCM_NTB_OUT_BUF_CNT 1
// </h>
// </h>
// <h>OS Resources Settings
// <i>These settings are used to optimize usage of OS resources.
// <o>Communication Device Class Interrupt Endpoint Thread Stack Size <64-65536>
#define USBD_CDC0_INT_THREAD_STACK_SIZE 512
// Communication Device Class Interrupt Endpoint Thread Priority
#define USBD_CDC0_INT_THREAD_PRIORITY osPriorityAboveNormal
// <o>Communication Device Class Bulk Endpoints Thread Stack Size <64-65536>
#define USBD_CDC0_BULK_THREAD_STACK_SIZE 512
// Communication Device Class Bulk Endpoints Thread Priority
#define USBD_CDC0_BULK_THREAD_PRIORITY osPriorityAboveNormal
// </h>
// </h>

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