Initial commit
This commit is contained in:
OneOfEleven
64
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/CMSIS/RTX_Config.c
vendored
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64
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/CMSIS/RTX_Config.c
vendored
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@@ -0,0 +1,64 @@
|
||||
/*
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* Copyright (c) 2013-2021 Arm Limited. All rights reserved.
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||||
*
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||||
* SPDX-License-Identifier: Apache-2.0
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||||
*
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||||
* Licensed under the Apache License, Version 2.0 (the License); you may
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||||
* not use this file except in compliance with the License.
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||||
* You may obtain a copy of the License at
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||||
*
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||||
* www.apache.org/licenses/LICENSE-2.0
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||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
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||||
* limitations under the License.
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||||
*
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* -----------------------------------------------------------------------------
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*
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* $Revision: V5.1.1
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*
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* Project: CMSIS-RTOS RTX
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* Title: RTX Configuration
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*
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* -----------------------------------------------------------------------------
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*/
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#include "cmsis_compiler.h"
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#include "rtx_os.h"
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// OS Idle Thread
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__WEAK __NO_RETURN void osRtxIdleThread (void *argument) {
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(void)argument;
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for (;;) {}
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}
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// OS Error Callback function
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__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) {
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(void)object_id;
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switch (code) {
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case osRtxErrorStackOverflow:
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// Stack overflow detected for thread (thread_id=object_id)
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break;
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case osRtxErrorISRQueueOverflow:
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// ISR Queue overflow detected when inserting object (object_id)
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break;
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case osRtxErrorTimerQueueOverflow:
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// User Timer Callback Queue overflow detected for timer (timer_id=object_id)
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break;
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case osRtxErrorClibSpace:
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// Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM
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break;
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case osRtxErrorClibMutex:
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// Standard C/C++ library mutex initialization failed
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break;
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default:
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// Reserved
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break;
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}
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for (;;) {}
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//return 0U;
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}
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580
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/CMSIS/RTX_Config.h
vendored
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580
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/CMSIS/RTX_Config.h
vendored
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@@ -0,0 +1,580 @@
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/*
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* Copyright (c) 2013-2021 Arm Limited. All rights reserved.
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*
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||||
* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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||||
* not use this file except in compliance with the License.
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||||
* You may obtain a copy of the License at
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||||
*
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||||
* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
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||||
* limitations under the License.
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||||
*
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||||
* -----------------------------------------------------------------------------
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*
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* $Revision: V5.5.2
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*
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* Project: CMSIS-RTOS RTX
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* Title: RTX Configuration definitions
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*
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* -----------------------------------------------------------------------------
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*/
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#ifndef RTX_CONFIG_H_
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#define RTX_CONFIG_H_
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#ifdef _RTE_
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#include "RTE_Components.h"
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#ifdef RTE_RTX_CONFIG_H
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#include RTE_RTX_CONFIG_H
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#endif
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#endif
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//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
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// <h>System Configuration
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// =======================
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// <o>Global Dynamic Memory size [bytes] <0-1073741824:8>
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// <i> Defines the combined global dynamic memory size.
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// <i> Default: 32768
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#ifndef OS_DYNAMIC_MEM_SIZE
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#define OS_DYNAMIC_MEM_SIZE 4096
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#endif
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// <o>Kernel Tick Frequency [Hz] <1-1000000>
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// <i> Defines base time unit for delays and timeouts.
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// <i> Default: 1000 (1ms tick)
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#ifndef OS_TICK_FREQ
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#define OS_TICK_FREQ 1000
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#endif
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// <e>Round-Robin Thread switching
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// <i> Enables Round-Robin Thread switching.
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#ifndef OS_ROBIN_ENABLE
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#define OS_ROBIN_ENABLE 1
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#endif
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// <o>Round-Robin Timeout <1-1000>
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// <i> Defines how many ticks a thread will execute before a thread switch.
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// <i> Default: 5
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#ifndef OS_ROBIN_TIMEOUT
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#define OS_ROBIN_TIMEOUT 5
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#endif
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// </e>
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// <o>ISR FIFO Queue
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// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries
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// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries
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// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries
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// <i> RTOS Functions called from ISR store requests to this buffer.
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// <i> Default: 16 entries
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#ifndef OS_ISR_FIFO_QUEUE
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#define OS_ISR_FIFO_QUEUE 32
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#endif
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// <q>Object Memory usage counters
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// <i> Enables object memory usage counters (requires RTX source variant).
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#ifndef OS_OBJ_MEM_USAGE
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#define OS_OBJ_MEM_USAGE 0
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#endif
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// </h>
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// <h>Thread Configuration
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// =======================
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// <e>Object specific Memory allocation
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// <i> Enables object specific memory allocation.
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#ifndef OS_THREAD_OBJ_MEM
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#define OS_THREAD_OBJ_MEM 0
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#endif
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// <o>Number of user Threads <1-1000>
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// <i> Defines maximum number of user threads that can be active at the same time.
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// <i> Applies to user threads with system provided memory for control blocks.
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#ifndef OS_THREAD_NUM
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#define OS_THREAD_NUM 1
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#endif
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// <o>Number of user Threads with default Stack size <0-1000>
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// <i> Defines maximum number of user threads with default stack size.
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// <i> Applies to user threads with zero stack size specified.
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#ifndef OS_THREAD_DEF_STACK_NUM
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#define OS_THREAD_DEF_STACK_NUM 0
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#endif
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// <o>Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8>
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// <i> Defines the combined stack size for user threads with user-provided stack size.
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// <i> Applies to user threads with user-provided stack size and system provided memory for stack.
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// <i> Default: 0
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#ifndef OS_THREAD_USER_STACK_SIZE
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#define OS_THREAD_USER_STACK_SIZE 0
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#endif
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// </e>
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// <o>Default Thread Stack size [bytes] <96-1073741824:8>
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// <i> Defines stack size for threads with zero stack size specified.
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// <i> Default: 3072
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#ifndef OS_STACK_SIZE
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#define OS_STACK_SIZE 1024
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#endif
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// <o>Idle Thread Stack size [bytes] <72-1073741824:8>
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// <i> Defines stack size for Idle thread.
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// <i> Default: 512
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#ifndef OS_IDLE_THREAD_STACK_SIZE
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#define OS_IDLE_THREAD_STACK_SIZE 512
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#endif
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// <o>Idle Thread TrustZone Module Identifier
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// <i> Defines TrustZone Thread Context Management Identifier.
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// <i> Applies only to cores with TrustZone technology.
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// <i> Default: 0 (not used)
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#ifndef OS_IDLE_THREAD_TZ_MOD_ID
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#define OS_IDLE_THREAD_TZ_MOD_ID 0
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#endif
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// <q>Stack overrun checking
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// <i> Enables stack overrun check at thread switch (requires RTX source variant).
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// <i> Enabling this option increases slightly the execution time of a thread switch.
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#ifndef OS_STACK_CHECK
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#define OS_STACK_CHECK 0
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#endif
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// <q>Stack usage watermark
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// <i> Initializes thread stack with watermark pattern for analyzing stack usage.
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// <i> Enabling this option increases significantly the execution time of thread creation.
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#ifndef OS_STACK_WATERMARK
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#define OS_STACK_WATERMARK 0
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#endif
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// <o>Processor mode for Thread execution
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// <0=> Unprivileged mode
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// <1=> Privileged mode
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// <i> Default: Privileged mode
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#ifndef OS_PRIVILEGE_MODE
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#define OS_PRIVILEGE_MODE 1
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#endif
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// </h>
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// <h>Timer Configuration
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// ======================
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// <e>Object specific Memory allocation
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// <i> Enables object specific memory allocation.
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#ifndef OS_TIMER_OBJ_MEM
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#define OS_TIMER_OBJ_MEM 0
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#endif
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// <o>Number of Timer objects <1-1000>
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// <i> Defines maximum number of objects that can be active at the same time.
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// <i> Applies to objects with system provided memory for control blocks.
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#ifndef OS_TIMER_NUM
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#define OS_TIMER_NUM 1
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#endif
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// </e>
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// <o>Timer Thread Priority
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// <8=> Low
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// <16=> Below Normal <24=> Normal <32=> Above Normal
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// <40=> High
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// <48=> Realtime
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||||
// <i> Defines priority for timer thread
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// <i> Default: High
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||||
#ifndef OS_TIMER_THREAD_PRIO
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#define OS_TIMER_THREAD_PRIO 40
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#endif
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||||
// <o>Timer Thread Stack size [bytes] <0-1073741824:8>
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||||
// <i> Defines stack size for Timer thread.
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||||
// <i> May be set to 0 when timers are not used.
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||||
// <i> Default: 512
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||||
#ifndef OS_TIMER_THREAD_STACK_SIZE
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#define OS_TIMER_THREAD_STACK_SIZE 512
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#endif
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||||
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||||
// <o>Timer Thread TrustZone Module Identifier
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||||
// <i> Defines TrustZone Thread Context Management Identifier.
|
||||
// <i> Applies only to cores with TrustZone technology.
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||||
// <i> Default: 0 (not used)
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||||
#ifndef OS_TIMER_THREAD_TZ_MOD_ID
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||||
#define OS_TIMER_THREAD_TZ_MOD_ID 0
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||||
#endif
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||||
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||||
// <o>Timer Callback Queue entries <0-256>
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||||
// <i> Number of concurrent active timer callback functions.
|
||||
// <i> May be set to 0 when timers are not used.
|
||||
// <i> Default: 4
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||||
#ifndef OS_TIMER_CB_QUEUE
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||||
#define OS_TIMER_CB_QUEUE 4
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||||
#endif
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||||
|
||||
// </h>
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||||
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||||
// <h>Event Flags Configuration
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||||
// ============================
|
||||
|
||||
// <e>Object specific Memory allocation
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||||
// <i> Enables object specific memory allocation.
|
||||
#ifndef OS_EVFLAGS_OBJ_MEM
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||||
#define OS_EVFLAGS_OBJ_MEM 0
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||||
#endif
|
||||
|
||||
// <o>Number of Event Flags objects <1-1000>
|
||||
// <i> Defines maximum number of objects that can be active at the same time.
|
||||
// <i> Applies to objects with system provided memory for control blocks.
|
||||
#ifndef OS_EVFLAGS_NUM
|
||||
#define OS_EVFLAGS_NUM 1
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Mutex Configuration
|
||||
// ======================
|
||||
|
||||
// <e>Object specific Memory allocation
|
||||
// <i> Enables object specific memory allocation.
|
||||
#ifndef OS_MUTEX_OBJ_MEM
|
||||
#define OS_MUTEX_OBJ_MEM 0
|
||||
#endif
|
||||
|
||||
// <o>Number of Mutex objects <1-1000>
|
||||
// <i> Defines maximum number of objects that can be active at the same time.
|
||||
// <i> Applies to objects with system provided memory for control blocks.
|
||||
#ifndef OS_MUTEX_NUM
|
||||
#define OS_MUTEX_NUM 1
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Semaphore Configuration
|
||||
// ==========================
|
||||
|
||||
// <e>Object specific Memory allocation
|
||||
// <i> Enables object specific memory allocation.
|
||||
#ifndef OS_SEMAPHORE_OBJ_MEM
|
||||
#define OS_SEMAPHORE_OBJ_MEM 0
|
||||
#endif
|
||||
|
||||
// <o>Number of Semaphore objects <1-1000>
|
||||
// <i> Defines maximum number of objects that can be active at the same time.
|
||||
// <i> Applies to objects with system provided memory for control blocks.
|
||||
#ifndef OS_SEMAPHORE_NUM
|
||||
#define OS_SEMAPHORE_NUM 1
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Memory Pool Configuration
|
||||
// ============================
|
||||
|
||||
// <e>Object specific Memory allocation
|
||||
// <i> Enables object specific memory allocation.
|
||||
#ifndef OS_MEMPOOL_OBJ_MEM
|
||||
#define OS_MEMPOOL_OBJ_MEM 0
|
||||
#endif
|
||||
|
||||
// <o>Number of Memory Pool objects <1-1000>
|
||||
// <i> Defines maximum number of objects that can be active at the same time.
|
||||
// <i> Applies to objects with system provided memory for control blocks.
|
||||
#ifndef OS_MEMPOOL_NUM
|
||||
#define OS_MEMPOOL_NUM 1
|
||||
#endif
|
||||
|
||||
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
|
||||
// <i> Defines the combined data storage memory size.
|
||||
// <i> Applies to objects with system provided memory for data storage.
|
||||
// <i> Default: 0
|
||||
#ifndef OS_MEMPOOL_DATA_SIZE
|
||||
#define OS_MEMPOOL_DATA_SIZE 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Message Queue Configuration
|
||||
// ==============================
|
||||
|
||||
// <e>Object specific Memory allocation
|
||||
// <i> Enables object specific memory allocation.
|
||||
#ifndef OS_MSGQUEUE_OBJ_MEM
|
||||
#define OS_MSGQUEUE_OBJ_MEM 0
|
||||
#endif
|
||||
|
||||
// <o>Number of Message Queue objects <1-1000>
|
||||
// <i> Defines maximum number of objects that can be active at the same time.
|
||||
// <i> Applies to objects with system provided memory for control blocks.
|
||||
#ifndef OS_MSGQUEUE_NUM
|
||||
#define OS_MSGQUEUE_NUM 1
|
||||
#endif
|
||||
|
||||
// <o>Data Storage Memory size [bytes] <0-1073741824:8>
|
||||
// <i> Defines the combined data storage memory size.
|
||||
// <i> Applies to objects with system provided memory for data storage.
|
||||
// <i> Default: 0
|
||||
#ifndef OS_MSGQUEUE_DATA_SIZE
|
||||
#define OS_MSGQUEUE_DATA_SIZE 0
|
||||
#endif
|
||||
|
||||
// </e>
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Event Recorder Configuration
|
||||
// ===============================
|
||||
|
||||
// <e>Global Initialization
|
||||
// <i> Initialize Event Recorder during 'osKernelInitialize'.
|
||||
#ifndef OS_EVR_INIT
|
||||
#define OS_EVR_INIT 0
|
||||
#endif
|
||||
|
||||
// <q>Start recording
|
||||
// <i> Start event recording after initialization.
|
||||
#ifndef OS_EVR_START
|
||||
#define OS_EVR_START 1
|
||||
#endif
|
||||
|
||||
// <h>Global Event Filter Setup
|
||||
// <i> Initial recording level applied to all components.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </h>
|
||||
#ifndef OS_EVR_LEVEL
|
||||
#define OS_EVR_LEVEL 0x00U
|
||||
#endif
|
||||
|
||||
// <h>RTOS Event Filter Setup
|
||||
// <i> Recording levels for RTX components.
|
||||
// <i> Only applicable if events for the respective component are generated.
|
||||
|
||||
// <e.7>Memory Management
|
||||
// <i> Recording level for Memory Management events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </e>
|
||||
#ifndef OS_EVR_MEMORY_LEVEL
|
||||
#define OS_EVR_MEMORY_LEVEL 0x81U
|
||||
#endif
|
||||
|
||||
// <e.7>Kernel
|
||||
// <i> Recording level for Kernel events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </e>
|
||||
#ifndef OS_EVR_KERNEL_LEVEL
|
||||
#define OS_EVR_KERNEL_LEVEL 0x81U
|
||||
#endif
|
||||
|
||||
// <e.7>Thread
|
||||
// <i> Recording level for Thread events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </e>
|
||||
#ifndef OS_EVR_THREAD_LEVEL
|
||||
#define OS_EVR_THREAD_LEVEL 0x85U
|
||||
#endif
|
||||
|
||||
// <e.7>Generic Wait
|
||||
// <i> Recording level for Generic Wait events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </e>
|
||||
#ifndef OS_EVR_WAIT_LEVEL
|
||||
#define OS_EVR_WAIT_LEVEL 0x81U
|
||||
#endif
|
||||
|
||||
// <e.7>Thread Flags
|
||||
// <i> Recording level for Thread Flags events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </e>
|
||||
#ifndef OS_EVR_THFLAGS_LEVEL
|
||||
#define OS_EVR_THFLAGS_LEVEL 0x81U
|
||||
#endif
|
||||
|
||||
// <e.7>Event Flags
|
||||
// <i> Recording level for Event Flags events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </e>
|
||||
#ifndef OS_EVR_EVFLAGS_LEVEL
|
||||
#define OS_EVR_EVFLAGS_LEVEL 0x81U
|
||||
#endif
|
||||
|
||||
// <e.7>Timer
|
||||
// <i> Recording level for Timer events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </e>
|
||||
#ifndef OS_EVR_TIMER_LEVEL
|
||||
#define OS_EVR_TIMER_LEVEL 0x81U
|
||||
#endif
|
||||
|
||||
// <e.7>Mutex
|
||||
// <i> Recording level for Mutex events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </e>
|
||||
#ifndef OS_EVR_MUTEX_LEVEL
|
||||
#define OS_EVR_MUTEX_LEVEL 0x81U
|
||||
#endif
|
||||
|
||||
// <e.7>Semaphore
|
||||
// <i> Recording level for Semaphore events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </e>
|
||||
#ifndef OS_EVR_SEMAPHORE_LEVEL
|
||||
#define OS_EVR_SEMAPHORE_LEVEL 0x81U
|
||||
#endif
|
||||
|
||||
// <e.7>Memory Pool
|
||||
// <i> Recording level for Memory Pool events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </e>
|
||||
#ifndef OS_EVR_MEMPOOL_LEVEL
|
||||
#define OS_EVR_MEMPOOL_LEVEL 0x81U
|
||||
#endif
|
||||
|
||||
// <e.7>Message Queue
|
||||
// <i> Recording level for Message Queue events.
|
||||
// <o.0>Error events
|
||||
// <o.1>API function call events
|
||||
// <o.2>Operation events
|
||||
// <o.3>Detailed operation events
|
||||
// </e>
|
||||
#ifndef OS_EVR_MSGQUEUE_LEVEL
|
||||
#define OS_EVR_MSGQUEUE_LEVEL 0x81U
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </e>
|
||||
|
||||
// <h>RTOS Event Generation
|
||||
// <i> Enables event generation for RTX components (requires RTX source variant).
|
||||
|
||||
// <q>Memory Management
|
||||
// <i> Enables Memory Management event generation.
|
||||
#ifndef OS_EVR_MEMORY
|
||||
#define OS_EVR_MEMORY 1
|
||||
#endif
|
||||
|
||||
// <q>Kernel
|
||||
// <i> Enables Kernel event generation.
|
||||
#ifndef OS_EVR_KERNEL
|
||||
#define OS_EVR_KERNEL 1
|
||||
#endif
|
||||
|
||||
// <q>Thread
|
||||
// <i> Enables Thread event generation.
|
||||
#ifndef OS_EVR_THREAD
|
||||
#define OS_EVR_THREAD 1
|
||||
#endif
|
||||
|
||||
// <q>Generic Wait
|
||||
// <i> Enables Generic Wait event generation.
|
||||
#ifndef OS_EVR_WAIT
|
||||
#define OS_EVR_WAIT 1
|
||||
#endif
|
||||
|
||||
// <q>Thread Flags
|
||||
// <i> Enables Thread Flags event generation.
|
||||
#ifndef OS_EVR_THFLAGS
|
||||
#define OS_EVR_THFLAGS 1
|
||||
#endif
|
||||
|
||||
// <q>Event Flags
|
||||
// <i> Enables Event Flags event generation.
|
||||
#ifndef OS_EVR_EVFLAGS
|
||||
#define OS_EVR_EVFLAGS 1
|
||||
#endif
|
||||
|
||||
// <q>Timer
|
||||
// <i> Enables Timer event generation.
|
||||
#ifndef OS_EVR_TIMER
|
||||
#define OS_EVR_TIMER 1
|
||||
#endif
|
||||
|
||||
// <q>Mutex
|
||||
// <i> Enables Mutex event generation.
|
||||
#ifndef OS_EVR_MUTEX
|
||||
#define OS_EVR_MUTEX 1
|
||||
#endif
|
||||
|
||||
// <q>Semaphore
|
||||
// <i> Enables Semaphore event generation.
|
||||
#ifndef OS_EVR_SEMAPHORE
|
||||
#define OS_EVR_SEMAPHORE 1
|
||||
#endif
|
||||
|
||||
// <q>Memory Pool
|
||||
// <i> Enables Memory Pool event generation.
|
||||
#ifndef OS_EVR_MEMPOOL
|
||||
#define OS_EVR_MEMPOOL 1
|
||||
#endif
|
||||
|
||||
// <q>Message Queue
|
||||
// <i> Enables Message Queue event generation.
|
||||
#ifndef OS_EVR_MSGQUEUE
|
||||
#define OS_EVR_MSGQUEUE 1
|
||||
#endif
|
||||
|
||||
// </h>
|
||||
|
||||
// </h>
|
||||
|
||||
// Number of Threads which use standard C/C++ library libspace
|
||||
// (when thread specific memory allocation is not used).
|
||||
#if (OS_THREAD_OBJ_MEM == 0)
|
||||
#ifndef OS_THREAD_LIBSPACE_NUM
|
||||
#define OS_THREAD_LIBSPACE_NUM 4
|
||||
#endif
|
||||
#else
|
||||
#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM
|
||||
#endif
|
||||
|
||||
//------------- <<< end of configuration section >>> ---------------------------
|
||||
|
||||
#endif // RTX_CONFIG_H_
|
||||
@@ -0,0 +1,105 @@
|
||||
#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: LPC55S69JBD100_cm33_core0
|
||||
** LPC55S69JBD64_cm33_core0
|
||||
** LPC55S69JEV98_cm33_core0
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
|
||||
** Version: rev. 1.1, 2019-05-16
|
||||
** Build: b200722
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2020 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
|
||||
/* USB BDT size */
|
||||
#define usb_bdt_size 0x0
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
#define m_interrupts_start 0x00000000
|
||||
#define m_interrupts_size 0x00000200
|
||||
|
||||
#define m_text_start 0x00000200
|
||||
#define m_text_size 0x00071E00
|
||||
|
||||
#define m_core1_image_start 0x00072000
|
||||
#define m_core1_image_size 0x00026000
|
||||
|
||||
#if (defined(__use_shmem__))
|
||||
#define m_data_start 0x20000000
|
||||
#define m_data_size 0x00031800
|
||||
#define m_rpmsg_sh_mem_start 0x20031800
|
||||
#define m_rpmsg_sh_mem_size 0x00001800
|
||||
#else
|
||||
#define m_data_start 0x20000000
|
||||
#define m_data_size 0x00033000
|
||||
#endif
|
||||
|
||||
#define m_usb_sram_start 0x40100000
|
||||
#define m_usb_sram_size 0x00004000
|
||||
|
||||
|
||||
LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region
|
||||
|
||||
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
#if (defined(__use_shmem__))
|
||||
RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
|
||||
* (rpmsg_sh_mem_section)
|
||||
}
|
||||
#endif
|
||||
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
|
||||
RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
|
||||
* (*m_usb_bdt)
|
||||
}
|
||||
|
||||
RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
|
||||
* (*m_usb_global)
|
||||
}
|
||||
}
|
||||
|
||||
LR_CORE1_IMAGE m_core1_image_start {
|
||||
CORE1_REGION m_core1_image_start m_core1_image_size {
|
||||
* (.core1_code)
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,107 @@
|
||||
#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: LPC55S69JBD100_cm33_core0
|
||||
** LPC55S69JBD64_cm33_core0
|
||||
** LPC55S69JEV98_cm33_core0
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
|
||||
** Version: rev. 1.1, 2019-05-16
|
||||
** Build: b190923
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2019 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
|
||||
/* USB BDT size */
|
||||
#define usb_bdt_size 0x0
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
/* The first 64kB of FLASH is used as secure memory. The rest of FLASH memory is non-secure memory. */
|
||||
#define m_interrupts_start 0x00010000
|
||||
#define m_interrupts_size 0x00000200
|
||||
|
||||
#define m_text_start 0x00010200
|
||||
#define m_text_size 0x00061E00
|
||||
|
||||
#define m_core1_image_start 0x00072000
|
||||
#define m_core1_image_size 0x00026000
|
||||
|
||||
/* The first 32kB of data RAM is used as secure memory. The rest of data RAM memory is non-secure memory. */
|
||||
#if (defined(__use_shmem__))
|
||||
#define m_data_start 0x20008000
|
||||
#define m_data_size 0x00029000
|
||||
#define m_rpmsg_sh_mem_start 0x20031800
|
||||
#define m_rpmsg_sh_mem_size 0x00001800
|
||||
#else
|
||||
#define m_data_start 0x20008000
|
||||
#define m_data_size 0x0002B000
|
||||
#endif
|
||||
|
||||
#define m_usb_sram_start 0x40100000
|
||||
#define m_usb_sram_size 0x00004000
|
||||
|
||||
|
||||
LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region
|
||||
|
||||
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
#if (defined(__use_shmem__))
|
||||
RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
|
||||
* (rpmsg_sh_mem_section)
|
||||
}
|
||||
#endif
|
||||
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
|
||||
RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
|
||||
* (*m_usb_bdt)
|
||||
}
|
||||
|
||||
RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
|
||||
* (*m_usb_global)
|
||||
}
|
||||
}
|
||||
|
||||
LR_CORE1_IMAGE m_core1_image_start {
|
||||
CORE1_REGION m_core1_image_start m_core1_image_size {
|
||||
* (.core1_code)
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,116 @@
|
||||
#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: LPC55S69JBD100_cm33_core0
|
||||
** LPC55S69JBD64_cm33_core0
|
||||
** LPC55S69JEV98_cm33_core0
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
|
||||
** Version: rev. 1.1, 2019-05-16
|
||||
** Build: b190923
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2019 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
|
||||
/* USB BDT size */
|
||||
#define usb_bdt_size 0x0
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
/* Only the first 64kB of flash is used as secure memory. */
|
||||
#define m_interrupts_start 0x10000000
|
||||
#define m_interrupts_size 0x00000200
|
||||
|
||||
#define m_text_start 0x10000200
|
||||
#define m_text_size 0x0000FC00
|
||||
|
||||
#define m_core1_image_start 0x10072000
|
||||
#define m_core1_image_size 0x00026000
|
||||
|
||||
/* Only first 32kB of data RAM is used as secure memory. */
|
||||
#if (defined(__use_shmem__))
|
||||
#define m_data_start 0x30000000
|
||||
#define m_data_size 0x00008000
|
||||
#define m_rpmsg_sh_mem_start 0x30031800
|
||||
#define m_rpmsg_sh_mem_size 0x00001800
|
||||
#else
|
||||
#define m_data_start 0x30000000
|
||||
#define m_data_size 0x00008000
|
||||
#endif
|
||||
|
||||
/* 512B - memory for veneer table (NSC - secure, non-secure callable memory) */
|
||||
#define m_veneer_table_start 0x1000FE00
|
||||
#define m_veneer_table_size 0x200
|
||||
|
||||
|
||||
#define m_usb_sram_start 0x50100000
|
||||
#define m_usb_sram_size 0x00004000
|
||||
|
||||
|
||||
LR_m_text m_interrupts_start m_interrupts_size+m_text_size+m_veneer_table_size { ; load region size_region
|
||||
|
||||
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
#if (defined(__use_shmem__))
|
||||
RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
|
||||
* (rpmsg_sh_mem_section)
|
||||
}
|
||||
#endif
|
||||
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
|
||||
ER_m_veneer_table m_veneer_table_start FIXED m_veneer_table_size {; veneer table
|
||||
*(Veneer$$CMSE)
|
||||
}
|
||||
|
||||
RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
|
||||
* (*m_usb_bdt)
|
||||
}
|
||||
|
||||
RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
|
||||
* (*m_usb_global)
|
||||
}
|
||||
}
|
||||
|
||||
LR_CORE1_IMAGE m_core1_image_start {
|
||||
CORE1_REGION m_core1_image_start m_core1_image_size {
|
||||
* (.core1_code)
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,105 @@
|
||||
#!armclang --target=arm-arm-none-eabi -march=armv8-m.main -E -x c
|
||||
/*
|
||||
** ###################################################################
|
||||
** Processors: LPC55S69JBD100_cm33_core0
|
||||
** LPC55S69JBD64_cm33_core0
|
||||
** LPC55S69JEV98_cm33_core0
|
||||
**
|
||||
** Compiler: Keil ARM C/C++ Compiler
|
||||
** Reference manual: LPC55S6x/LPC55S2x/LPC552x User manual(UM11126) Rev.1.3 16 May 2019
|
||||
** Version: rev. 1.1, 2019-05-16
|
||||
** Build: b200722
|
||||
**
|
||||
** Abstract:
|
||||
** Linker file for the Keil ARM C/C++ Compiler
|
||||
**
|
||||
** Copyright 2016 Freescale Semiconductor, Inc.
|
||||
** Copyright 2016-2020 NXP
|
||||
** All rights reserved.
|
||||
**
|
||||
** SPDX-License-Identifier: BSD-3-Clause
|
||||
**
|
||||
** http: www.nxp.com
|
||||
** mail: support@nxp.com
|
||||
**
|
||||
** ###################################################################
|
||||
*/
|
||||
|
||||
|
||||
/* USB BDT size */
|
||||
#define usb_bdt_size 0x0
|
||||
/* Sizes */
|
||||
#if (defined(__stack_size__))
|
||||
#define Stack_Size __stack_size__
|
||||
#else
|
||||
#define Stack_Size 0x0400
|
||||
#endif
|
||||
|
||||
#if (defined(__heap_size__))
|
||||
#define Heap_Size __heap_size__
|
||||
#else
|
||||
#define Heap_Size 0x0400
|
||||
#endif
|
||||
|
||||
#define m_interrupts_start 0x04000000
|
||||
#define m_interrupts_size 0x00000200
|
||||
|
||||
#define m_text_start 0x04000200
|
||||
#define m_text_size 0x00007E00
|
||||
|
||||
#define m_core1_image_start 0x20033000
|
||||
#define m_core1_image_size 0x0000C800
|
||||
|
||||
#if (defined(__use_shmem__))
|
||||
#define m_data_start 0x20000000
|
||||
#define m_data_size 0x00031800
|
||||
#define m_rpmsg_sh_mem_start 0x20031800
|
||||
#define m_rpmsg_sh_mem_size 0x00001800
|
||||
#else
|
||||
#define m_data_start 0x20000000
|
||||
#define m_data_size 0x00033000
|
||||
#endif
|
||||
|
||||
#define m_usb_sram_start 0x40100000
|
||||
#define m_usb_sram_size 0x00004000
|
||||
|
||||
|
||||
LR_m_text m_interrupts_start m_interrupts_size+m_text_size { ; load region size_region
|
||||
|
||||
VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
|
||||
* (.isr_vector,+FIRST)
|
||||
}
|
||||
|
||||
ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
|
||||
* (InRoot$$Sections)
|
||||
.ANY (+RO)
|
||||
}
|
||||
|
||||
#if (defined(__use_shmem__))
|
||||
RPMSG_SH_MEM m_rpmsg_sh_mem_start UNINIT m_rpmsg_sh_mem_size { ; Shared memory used by RPMSG
|
||||
* (rpmsg_sh_mem_section)
|
||||
}
|
||||
#endif
|
||||
|
||||
RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
|
||||
.ANY (+RW +ZI)
|
||||
}
|
||||
ARM_LIB_HEAP +0 EMPTY Heap_Size { ; Heap region growing up
|
||||
}
|
||||
ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
|
||||
}
|
||||
|
||||
RW_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
|
||||
* (*m_usb_bdt)
|
||||
}
|
||||
|
||||
RW_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
|
||||
* (*m_usb_global)
|
||||
}
|
||||
}
|
||||
|
||||
LR_CORE1_IMAGE m_core1_image_start {
|
||||
CORE1_REGION m_core1_image_start m_core1_image_size {
|
||||
* (.core1_code)
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,215 @@
|
||||
/*
|
||||
* Copyright (c) 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2020 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef _RTE_DEVICE_H
|
||||
#define _RTE_DEVICE_H
|
||||
|
||||
#include "pin_mux.h"
|
||||
|
||||
/* UART Select, UART0-UART7. */
|
||||
/* User needs to provide the implementation of USARTX_GetFreq/USARTX_InitPins/USARTX_DeinitPins for the enabled USART
|
||||
* instance. */
|
||||
#define RTE_USART0 1
|
||||
#define RTE_USART0_DMA_EN 1
|
||||
#define RTE_USART1 0
|
||||
#define RTE_USART1_DMA_EN 0
|
||||
#define RTE_USART2 0
|
||||
#define RTE_USART2_DMA_EN 0
|
||||
#define RTE_USART3 1
|
||||
#define RTE_USART3_DMA_EN 1
|
||||
#define RTE_USART4 0
|
||||
#define RTE_USART4_DMA_EN 0
|
||||
#define RTE_USART5 0
|
||||
#define RTE_USART5_DMA_EN 0
|
||||
#define RTE_USART6 0
|
||||
#define RTE_USART6_DMA_EN 0
|
||||
#define RTE_USART7 0
|
||||
#define RTE_USART7_DMA_EN 0
|
||||
|
||||
/* USART configuration. */
|
||||
#define USART_RX_BUFFER_LEN 64
|
||||
#define USART0_RX_BUFFER_ENABLE 1
|
||||
#define USART1_RX_BUFFER_ENABLE 0
|
||||
#define USART2_RX_BUFFER_ENABLE 0
|
||||
#define USART3_RX_BUFFER_ENABLE 1
|
||||
#define USART4_RX_BUFFER_ENABLE 0
|
||||
#define USART5_RX_BUFFER_ENABLE 0
|
||||
#define USART6_RX_BUFFER_ENABLE 0
|
||||
#define USART7_RX_BUFFER_ENABLE 0
|
||||
|
||||
#define RTE_USART0_DMA_TX_CH 5
|
||||
#define RTE_USART0_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_USART0_DMA_RX_CH 4
|
||||
#define RTE_USART0_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_USART1_DMA_TX_CH 7
|
||||
#define RTE_USART1_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_USART1_DMA_RX_CH 6
|
||||
#define RTE_USART1_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_USART2_DMA_TX_CH 8
|
||||
#define RTE_USART2_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_USART2_DMA_RX_CH 9
|
||||
#define RTE_USART2_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_USART3_DMA_TX_CH 9
|
||||
#define RTE_USART3_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_USART3_DMA_RX_CH 8
|
||||
#define RTE_USART3_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_USART4_DMA_TX_CH 13
|
||||
#define RTE_USART4_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_USART4_DMA_RX_CH 12
|
||||
#define RTE_USART4_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_USART5_DMA_TX_CH 15
|
||||
#define RTE_USART5_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_USART5_DMA_RX_CH 14
|
||||
#define RTE_USART5_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_USART6_DMA_TX_CH 17
|
||||
#define RTE_USART6_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_USART6_DMA_RX_CH 16
|
||||
#define RTE_USART6_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_USART7_DMA_TX_CH 19
|
||||
#define RTE_USART7_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_USART7_DMA_RX_CH 18
|
||||
#define RTE_USART7_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
/* I2C Select, I2C0 -I2C7*/
|
||||
/* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance.
|
||||
*/
|
||||
#define RTE_I2C0 0
|
||||
#define RTE_I2C0_DMA_EN 0
|
||||
#define RTE_I2C1 0
|
||||
#define RTE_I2C1_DMA_EN 0
|
||||
#define RTE_I2C2 0
|
||||
#define RTE_I2C2_DMA_EN 0
|
||||
#define RTE_I2C3 0
|
||||
#define RTE_I2C3_DMA_EN 0
|
||||
#define RTE_I2C4 0
|
||||
#define RTE_I2C4_DMA_EN 0
|
||||
#define RTE_I2C5 0
|
||||
#define RTE_I2C5_DMA_EN 0
|
||||
#define RTE_I2C6 0
|
||||
#define RTE_I2C6_DMA_EN 0
|
||||
#define RTE_I2C7 0
|
||||
#define RTE_I2C7_DMA_EN 0
|
||||
|
||||
/*I2C configuration*/
|
||||
#define RTE_I2C0_Master_DMA_BASE DMA0
|
||||
#define RTE_I2C0_Master_DMA_CH 1
|
||||
|
||||
#define RTE_I2C1_Master_DMA_BASE DMA0
|
||||
#define RTE_I2C1_Master_DMA_CH 3
|
||||
|
||||
#define RTE_I2C2_Master_DMA_BASE DMA0
|
||||
#define RTE_I2C2_Master_DMA_CH 5
|
||||
|
||||
#define RTE_I2C3_Master_DMA_BASE DMA0
|
||||
#define RTE_I2C3_Master_DMA_CH 7
|
||||
|
||||
#define RTE_I2C4_Master_DMA_BASE DMA0
|
||||
#define RTE_I2C4_Master_DMA_CH 9
|
||||
|
||||
#define RTE_I2C5_Master_DMA_BASE DMA0
|
||||
#define RTE_I2C5_Master_DMA_CH 11
|
||||
|
||||
#define RTE_I2C6_Master_DMA_BASE DMA0
|
||||
#define RTE_I2C6_Master_DMA_CH 13
|
||||
|
||||
#define RTE_I2C7_Master_DMA_BASE DMA0
|
||||
#define RTE_I2C7_Master_DMA_CH 15
|
||||
|
||||
/* SPI select, SPI0 - SPI7.*/
|
||||
/* User needs to provide the implementation of SPIX_GetFreq/SPIX_InitPins/SPIX_DeinitPins for the enabled SPI instance.
|
||||
*/
|
||||
#define RTE_SPI0 0
|
||||
#define RTE_SPI0_DMA_EN 0
|
||||
#define RTE_SPI1 0
|
||||
#define RTE_SPI1_DMA_EN 0
|
||||
#define RTE_SPI2 0
|
||||
#define RTE_SPI2_DMA_EN 0
|
||||
#define RTE_SPI3 0
|
||||
#define RTE_SPI3_DMA_EN 0
|
||||
#define RTE_SPI4 0
|
||||
#define RTE_SPI4_DMA_EN 0
|
||||
#define RTE_SPI5 0
|
||||
#define RTE_SPI5_DMA_EN 0
|
||||
#define RTE_SPI6 0
|
||||
#define RTE_SPI6_DMA_EN 0
|
||||
#define RTE_SPI7 0
|
||||
#define RTE_SPI7_DMA_EN 0
|
||||
|
||||
/* SPI configuration. */
|
||||
#define RTE_SPI0_SSEL_NUM kSPI_Ssel0
|
||||
#define RTE_SPI0_PIN_INIT SPI0_InitPins
|
||||
#define RTE_SPI0_PIN_DEINIT SPI0_DeinitPins
|
||||
#define RTE_SPI0_DMA_TX_CH 1
|
||||
#define RTE_SPI0_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_SPI0_DMA_RX_CH 0
|
||||
#define RTE_SPI0_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_SPI1_SSEL_NUM kSPI_Ssel0
|
||||
#define RTE_SPI1_PIN_INIT SPI1_InitPins
|
||||
#define RTE_SPI1_PIN_DEINIT SPI1_DeinitPins
|
||||
#define RTE_SPI1_DMA_TX_CH 3
|
||||
#define RTE_SPI1_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_SPI1_DMA_RX_CH 2
|
||||
#define RTE_SPI1_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_SPI2_SSEL_NUM kSPI_Ssel0
|
||||
#define RTE_SPI2_PIN_INIT SPI2_InitPins
|
||||
#define RTE_SPI2_PIN_DEINIT SPI2_DeinitPins
|
||||
#define RTE_SPI2_DMA_TX_CH 5
|
||||
#define RTE_SPI2_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_SPI2_DMA_RX_CH 4
|
||||
#define RTE_SPI2_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_SPI3_SSEL_NUM kSPI_Ssel0
|
||||
#define RTE_SPI3_PIN_INIT SPI3_InitPins
|
||||
#define RTE_SPI3_PIN_DEINIT SPI3_DeinitPins
|
||||
#define RTE_SPI3_DMA_TX_CH 7
|
||||
#define RTE_SPI3_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_SPI3_DMA_RX_CH 6
|
||||
#define RTE_SPI3_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_SPI4_SSEL_NUM kSPI_Ssel0
|
||||
#define RTE_SPI4_PIN_INIT SPI4_InitPins
|
||||
#define RTE_SPI4_PIN_DEINIT SPI4_DeinitPins
|
||||
#define RTE_SPI4_DMA_TX_CH 9
|
||||
#define RTE_SPI4_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_SPI4_DMA_RX_CH 8
|
||||
#define RTE_SPI4_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_SPI5_SSEL_NUM kSPI_Ssel0
|
||||
#define RTE_SPI5_PIN_INIT SPI5_InitPins
|
||||
#define RTE_SPI5_PIN_DEINIT SPI5_DeinitPins
|
||||
#define RTE_SPI5_DMA_TX_CH 11
|
||||
#define RTE_SPI5_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_SPI5_DMA_RX_CH 10
|
||||
#define RTE_SPI5_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_SPI6_SSEL_NUM kSPI_Ssel0
|
||||
#define RTE_SPI6_PIN_INIT SPI6_InitPins
|
||||
#define RTE_SPI6_PIN_DEINIT SPI6_DeinitPins
|
||||
#define RTE_SPI6_DMA_TX_CH 13
|
||||
#define RTE_SPI6_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_SPI6_DMA_RX_CH 12
|
||||
#define RTE_SPI6_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#define RTE_SPI7_SSEL_NUM kSPI_Ssel0
|
||||
#define RTE_SPI7_PIN_INIT SPI7_InitPins
|
||||
#define RTE_SPI7_PIN_DEINIT SPI7_DeinitPins
|
||||
#define RTE_SPI7_DMA_TX_CH 15
|
||||
#define RTE_SPI7_DMA_TX_DMA_BASE DMA0
|
||||
#define RTE_SPI7_DMA_RX_CH 14
|
||||
#define RTE_SPI7_DMA_RX_DMA_BASE DMA0
|
||||
|
||||
#endif /* _RTE_DEVICE_H */
|
||||
@@ -0,0 +1,801 @@
|
||||
/* ---------------------------------------------------------------------------------------
|
||||
* @file: startup_LPC55S69_cm33_core0.s
|
||||
* @purpose: CMSIS Cortex-M33 Core Device Startup File for the LPC55S69_cm33_core0
|
||||
* @version: 1.1
|
||||
* @date: 2019-5-16
|
||||
* ---------------------------------------------------------------------------------------*/
|
||||
/*
|
||||
* Copyright 1997-2016 Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2021 NXP
|
||||
* All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
/*****************************************************************************/
|
||||
/* Version: GCC for ARM Embedded Processors */
|
||||
/*****************************************************************************/
|
||||
|
||||
.syntax unified
|
||||
.arch armv8-m.main
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1 /*8-byte alignment */
|
||||
|
||||
.section .isr_vector, "a"
|
||||
.align 2
|
||||
.globl __Vectors
|
||||
|
||||
__Vectors:
|
||||
.long Image$$ARM_LIB_STACK$$ZI$$Limit /* Top of Stack */
|
||||
.long Reset_Handler /* Reset Handler */
|
||||
.long NMI_Handler /* NMI Handler*/
|
||||
.long HardFault_Handler /* Hard Fault Handler*/
|
||||
.long MemManage_Handler /* MPU Fault Handler*/
|
||||
.long BusFault_Handler /* Bus Fault Handler*/
|
||||
.long UsageFault_Handler /* Usage Fault Handler*/
|
||||
.long SecureFault_Handler /* Secure Fault Handler*/
|
||||
.long 0 /* Reserved*/
|
||||
.long 0 /* Reserved*/
|
||||
.long 0 /* Reserved*/
|
||||
.long SVC_Handler /* SVCall Handler*/
|
||||
.long DebugMon_Handler /* Debug Monitor Handler*/
|
||||
.long 0 /* Reserved*/
|
||||
.long PendSV_Handler /* PendSV Handler*/
|
||||
.long SysTick_Handler /* SysTick Handler*/
|
||||
|
||||
/* External Interrupts*/
|
||||
.long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */
|
||||
.long DMA0_IRQHandler /* DMA0 controller */
|
||||
.long GINT0_IRQHandler /* GPIO group 0 */
|
||||
.long GINT1_IRQHandler /* GPIO group 1 */
|
||||
.long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */
|
||||
.long PIN_INT1_IRQHandler /* Pin interrupt 1or pattern match engine slice 1 */
|
||||
.long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */
|
||||
.long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */
|
||||
.long UTICK0_IRQHandler /* Micro-tick Timer */
|
||||
.long MRT0_IRQHandler /* Multi-rate timer */
|
||||
.long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */
|
||||
.long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */
|
||||
.long SCT0_IRQHandler /* SCTimer/PWM */
|
||||
.long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */
|
||||
.long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */
|
||||
.long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */
|
||||
.long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */
|
||||
.long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */
|
||||
.long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */
|
||||
.long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */
|
||||
.long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */
|
||||
.long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */
|
||||
.long ADC0_IRQHandler /* ADC0 */
|
||||
.long Reserved39_IRQHandler /* Reserved interrupt */
|
||||
.long ACMP_IRQHandler /* ACMP interrupts */
|
||||
.long Reserved41_IRQHandler /* Reserved interrupt */
|
||||
.long Reserved42_IRQHandler /* Reserved interrupt */
|
||||
.long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */
|
||||
.long USB0_IRQHandler /* USB device */
|
||||
.long RTC_IRQHandler /* RTC alarm and wake-up interrupts */
|
||||
.long Reserved46_IRQHandler /* Reserved interrupt */
|
||||
.long MAILBOX_IRQHandler /* WAKEUP,Mailbox interrupt (present on selected devices) */
|
||||
.long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */
|
||||
.long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */
|
||||
.long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */
|
||||
.long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */
|
||||
.long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */
|
||||
.long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */
|
||||
.long OS_EVENT_IRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */
|
||||
.long Reserved55_IRQHandler /* Reserved interrupt */
|
||||
.long Reserved56_IRQHandler /* Reserved interrupt */
|
||||
.long Reserved57_IRQHandler /* Reserved interrupt */
|
||||
.long SDIO_IRQHandler /* SD/MMC */
|
||||
.long Reserved59_IRQHandler /* Reserved interrupt */
|
||||
.long Reserved60_IRQHandler /* Reserved interrupt */
|
||||
.long Reserved61_IRQHandler /* Reserved interrupt */
|
||||
.long USB1_PHY_IRQHandler /* USB1_PHY */
|
||||
.long USB1_IRQHandler /* USB1 interrupt */
|
||||
.long USB1_NEEDCLK_IRQHandler /* USB1 activity */
|
||||
.long SEC_HYPERVISOR_CALL_IRQHandler /* SEC_HYPERVISOR_CALL interrupt */
|
||||
.long SEC_GPIO_INT0_IRQ0_IRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */
|
||||
.long SEC_GPIO_INT0_IRQ1_IRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */
|
||||
.long PLU_IRQHandler /* PLU interrupt */
|
||||
.long SEC_VIO_IRQHandler /* SEC_VIO interrupt */
|
||||
.long HASHCRYPT_IRQHandler /* HASHCRYPT interrupt */
|
||||
.long CASER_IRQHandler /* CASPER interrupt */
|
||||
.long PUF_IRQHandler /* PUF interrupt */
|
||||
.long PQ_IRQHandler /* PQ interrupt */
|
||||
.long DMA1_IRQHandler /* DMA1 interrupt */
|
||||
.long FLEXCOMM8_IRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */
|
||||
.size __Vectors, . - __Vectors
|
||||
|
||||
.text
|
||||
.thumb
|
||||
|
||||
/* Reset Handler */
|
||||
.thumb_func
|
||||
.align 2
|
||||
.weak Reset_Handler
|
||||
.type Reset_Handler, %function
|
||||
|
||||
Reset_Handler:
|
||||
cpsid i /* Mask interrupts */
|
||||
.equ VTOR, 0xE000ED08
|
||||
ldr r0, =VTOR
|
||||
ldr r1, =__Vectors
|
||||
str r1, [r0]
|
||||
ldr r2, [r1]
|
||||
msr msp, r2
|
||||
ldr R0, =Image$$ARM_LIB_STACK$$ZI$$Base
|
||||
msr msplim, R0
|
||||
ldr r0,=SystemInit
|
||||
blx r0
|
||||
cpsie i /* Unmask interrupts */
|
||||
ldr r0,=__main
|
||||
bx r0
|
||||
|
||||
.pool
|
||||
.size Reset_Handler, . - Reset_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak DefaultISR
|
||||
.type DefaultISR, %function
|
||||
DefaultISR:
|
||||
b DefaultISR
|
||||
.size DefaultISR, . - DefaultISR
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak NMI_Handler
|
||||
.type NMI_Handler, %function
|
||||
NMI_Handler:
|
||||
ldr r0,=NMI_Handler
|
||||
bx r0
|
||||
.size NMI_Handler, . - NMI_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak HardFault_Handler
|
||||
.type HardFault_Handler, %function
|
||||
HardFault_Handler:
|
||||
ldr r0,=HardFault_Handler
|
||||
bx r0
|
||||
.size HardFault_Handler, . - HardFault_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak SVC_Handler
|
||||
.type SVC_Handler, %function
|
||||
SVC_Handler:
|
||||
ldr r0,=SVC_Handler
|
||||
bx r0
|
||||
.size SVC_Handler, . - SVC_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak PendSV_Handler
|
||||
.type PendSV_Handler, %function
|
||||
PendSV_Handler:
|
||||
ldr r0,=PendSV_Handler
|
||||
bx r0
|
||||
.size PendSV_Handler, . - PendSV_Handler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak SysTick_Handler
|
||||
.type SysTick_Handler, %function
|
||||
SysTick_Handler:
|
||||
ldr r0,=SysTick_Handler
|
||||
bx r0
|
||||
.size SysTick_Handler, . - SysTick_Handler
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak WDT_BOD_IRQHandler
|
||||
.type WDT_BOD_IRQHandler, %function
|
||||
WDT_BOD_IRQHandler:
|
||||
ldr r0,=WDT_BOD_DriverIRQHandler
|
||||
bx r0
|
||||
.size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak DMA0_IRQHandler
|
||||
.type DMA0_IRQHandler, %function
|
||||
DMA0_IRQHandler:
|
||||
ldr r0,=DMA0_DriverIRQHandler
|
||||
bx r0
|
||||
.size DMA0_IRQHandler, . - DMA0_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak GINT0_IRQHandler
|
||||
.type GINT0_IRQHandler, %function
|
||||
GINT0_IRQHandler:
|
||||
ldr r0,=GINT0_DriverIRQHandler
|
||||
bx r0
|
||||
.size GINT0_IRQHandler, . - GINT0_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak GINT1_IRQHandler
|
||||
.type GINT1_IRQHandler, %function
|
||||
GINT1_IRQHandler:
|
||||
ldr r0,=GINT1_DriverIRQHandler
|
||||
bx r0
|
||||
.size GINT1_IRQHandler, . - GINT1_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak PIN_INT0_IRQHandler
|
||||
.type PIN_INT0_IRQHandler, %function
|
||||
PIN_INT0_IRQHandler:
|
||||
ldr r0,=PIN_INT0_DriverIRQHandler
|
||||
bx r0
|
||||
.size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak PIN_INT1_IRQHandler
|
||||
.type PIN_INT1_IRQHandler, %function
|
||||
PIN_INT1_IRQHandler:
|
||||
ldr r0,=PIN_INT1_DriverIRQHandler
|
||||
bx r0
|
||||
.size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak PIN_INT2_IRQHandler
|
||||
.type PIN_INT2_IRQHandler, %function
|
||||
PIN_INT2_IRQHandler:
|
||||
ldr r0,=PIN_INT2_DriverIRQHandler
|
||||
bx r0
|
||||
.size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak PIN_INT3_IRQHandler
|
||||
.type PIN_INT3_IRQHandler, %function
|
||||
PIN_INT3_IRQHandler:
|
||||
ldr r0,=PIN_INT3_DriverIRQHandler
|
||||
bx r0
|
||||
.size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak UTICK0_IRQHandler
|
||||
.type UTICK0_IRQHandler, %function
|
||||
UTICK0_IRQHandler:
|
||||
ldr r0,=UTICK0_DriverIRQHandler
|
||||
bx r0
|
||||
.size UTICK0_IRQHandler, . - UTICK0_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak MRT0_IRQHandler
|
||||
.type MRT0_IRQHandler, %function
|
||||
MRT0_IRQHandler:
|
||||
ldr r0,=MRT0_DriverIRQHandler
|
||||
bx r0
|
||||
.size MRT0_IRQHandler, . - MRT0_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak CTIMER0_IRQHandler
|
||||
.type CTIMER0_IRQHandler, %function
|
||||
CTIMER0_IRQHandler:
|
||||
ldr r0,=CTIMER0_DriverIRQHandler
|
||||
bx r0
|
||||
.size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak CTIMER1_IRQHandler
|
||||
.type CTIMER1_IRQHandler, %function
|
||||
CTIMER1_IRQHandler:
|
||||
ldr r0,=CTIMER1_DriverIRQHandler
|
||||
bx r0
|
||||
.size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak SCT0_IRQHandler
|
||||
.type SCT0_IRQHandler, %function
|
||||
SCT0_IRQHandler:
|
||||
ldr r0,=SCT0_DriverIRQHandler
|
||||
bx r0
|
||||
.size SCT0_IRQHandler, . - SCT0_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak CTIMER3_IRQHandler
|
||||
.type CTIMER3_IRQHandler, %function
|
||||
CTIMER3_IRQHandler:
|
||||
ldr r0,=CTIMER3_DriverIRQHandler
|
||||
bx r0
|
||||
.size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak FLEXCOMM0_IRQHandler
|
||||
.type FLEXCOMM0_IRQHandler, %function
|
||||
FLEXCOMM0_IRQHandler:
|
||||
ldr r0,=FLEXCOMM0_DriverIRQHandler
|
||||
bx r0
|
||||
.size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak FLEXCOMM1_IRQHandler
|
||||
.type FLEXCOMM1_IRQHandler, %function
|
||||
FLEXCOMM1_IRQHandler:
|
||||
ldr r0,=FLEXCOMM1_DriverIRQHandler
|
||||
bx r0
|
||||
.size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak FLEXCOMM2_IRQHandler
|
||||
.type FLEXCOMM2_IRQHandler, %function
|
||||
FLEXCOMM2_IRQHandler:
|
||||
ldr r0,=FLEXCOMM2_DriverIRQHandler
|
||||
bx r0
|
||||
.size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak FLEXCOMM3_IRQHandler
|
||||
.type FLEXCOMM3_IRQHandler, %function
|
||||
FLEXCOMM3_IRQHandler:
|
||||
ldr r0,=FLEXCOMM3_DriverIRQHandler
|
||||
bx r0
|
||||
.size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak FLEXCOMM4_IRQHandler
|
||||
.type FLEXCOMM4_IRQHandler, %function
|
||||
FLEXCOMM4_IRQHandler:
|
||||
ldr r0,=FLEXCOMM4_DriverIRQHandler
|
||||
bx r0
|
||||
.size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak FLEXCOMM5_IRQHandler
|
||||
.type FLEXCOMM5_IRQHandler, %function
|
||||
FLEXCOMM5_IRQHandler:
|
||||
ldr r0,=FLEXCOMM5_DriverIRQHandler
|
||||
bx r0
|
||||
.size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak FLEXCOMM6_IRQHandler
|
||||
.type FLEXCOMM6_IRQHandler, %function
|
||||
FLEXCOMM6_IRQHandler:
|
||||
ldr r0,=FLEXCOMM6_DriverIRQHandler
|
||||
bx r0
|
||||
.size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak FLEXCOMM7_IRQHandler
|
||||
.type FLEXCOMM7_IRQHandler, %function
|
||||
FLEXCOMM7_IRQHandler:
|
||||
ldr r0,=FLEXCOMM7_DriverIRQHandler
|
||||
bx r0
|
||||
.size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak ADC0_IRQHandler
|
||||
.type ADC0_IRQHandler, %function
|
||||
ADC0_IRQHandler:
|
||||
ldr r0,=ADC0_DriverIRQHandler
|
||||
bx r0
|
||||
.size ADC0_IRQHandler, . - ADC0_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak Reserved39_IRQHandler
|
||||
.type Reserved39_IRQHandler, %function
|
||||
Reserved39_IRQHandler:
|
||||
ldr r0,=Reserved39_DriverIRQHandler
|
||||
bx r0
|
||||
.size Reserved39_IRQHandler, . - Reserved39_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak ACMP_IRQHandler
|
||||
.type ACMP_IRQHandler, %function
|
||||
ACMP_IRQHandler:
|
||||
ldr r0,=ACMP_DriverIRQHandler
|
||||
bx r0
|
||||
.size ACMP_IRQHandler, . - ACMP_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak Reserved41_IRQHandler
|
||||
.type Reserved41_IRQHandler, %function
|
||||
Reserved41_IRQHandler:
|
||||
ldr r0,=Reserved41_DriverIRQHandler
|
||||
bx r0
|
||||
.size Reserved41_IRQHandler, . - Reserved41_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak Reserved42_IRQHandler
|
||||
.type Reserved42_IRQHandler, %function
|
||||
Reserved42_IRQHandler:
|
||||
ldr r0,=Reserved42_DriverIRQHandler
|
||||
bx r0
|
||||
.size Reserved42_IRQHandler, . - Reserved42_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak USB0_NEEDCLK_IRQHandler
|
||||
.type USB0_NEEDCLK_IRQHandler, %function
|
||||
USB0_NEEDCLK_IRQHandler:
|
||||
ldr r0,=USB0_NEEDCLK_DriverIRQHandler
|
||||
bx r0
|
||||
.size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak USB0_IRQHandler
|
||||
.type USB0_IRQHandler, %function
|
||||
USB0_IRQHandler:
|
||||
ldr r0,=USB0_DriverIRQHandler
|
||||
bx r0
|
||||
.size USB0_IRQHandler, . - USB0_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak RTC_IRQHandler
|
||||
.type RTC_IRQHandler, %function
|
||||
RTC_IRQHandler:
|
||||
ldr r0,=RTC_DriverIRQHandler
|
||||
bx r0
|
||||
.size RTC_IRQHandler, . - RTC_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak Reserved46_IRQHandler
|
||||
.type Reserved46_IRQHandler, %function
|
||||
Reserved46_IRQHandler:
|
||||
ldr r0,=Reserved46_DriverIRQHandler
|
||||
bx r0
|
||||
.size Reserved46_IRQHandler, . - Reserved46_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak MAILBOX_IRQHandler
|
||||
.type MAILBOX_IRQHandler, %function
|
||||
MAILBOX_IRQHandler:
|
||||
ldr r0,=MAILBOX_DriverIRQHandler
|
||||
bx r0
|
||||
.size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak PIN_INT4_IRQHandler
|
||||
.type PIN_INT4_IRQHandler, %function
|
||||
PIN_INT4_IRQHandler:
|
||||
ldr r0,=PIN_INT4_DriverIRQHandler
|
||||
bx r0
|
||||
.size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak PIN_INT5_IRQHandler
|
||||
.type PIN_INT5_IRQHandler, %function
|
||||
PIN_INT5_IRQHandler:
|
||||
ldr r0,=PIN_INT5_DriverIRQHandler
|
||||
bx r0
|
||||
.size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak PIN_INT6_IRQHandler
|
||||
.type PIN_INT6_IRQHandler, %function
|
||||
PIN_INT6_IRQHandler:
|
||||
ldr r0,=PIN_INT6_DriverIRQHandler
|
||||
bx r0
|
||||
.size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak PIN_INT7_IRQHandler
|
||||
.type PIN_INT7_IRQHandler, %function
|
||||
PIN_INT7_IRQHandler:
|
||||
ldr r0,=PIN_INT7_DriverIRQHandler
|
||||
bx r0
|
||||
.size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak CTIMER2_IRQHandler
|
||||
.type CTIMER2_IRQHandler, %function
|
||||
CTIMER2_IRQHandler:
|
||||
ldr r0,=CTIMER2_DriverIRQHandler
|
||||
bx r0
|
||||
.size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak CTIMER4_IRQHandler
|
||||
.type CTIMER4_IRQHandler, %function
|
||||
CTIMER4_IRQHandler:
|
||||
ldr r0,=CTIMER4_DriverIRQHandler
|
||||
bx r0
|
||||
.size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak OS_EVENT_IRQHandler
|
||||
.type OS_EVENT_IRQHandler, %function
|
||||
OS_EVENT_IRQHandler:
|
||||
ldr r0,=OS_EVENT_DriverIRQHandler
|
||||
bx r0
|
||||
.size OS_EVENT_IRQHandler, . - OS_EVENT_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak Reserved55_IRQHandler
|
||||
.type Reserved55_IRQHandler, %function
|
||||
Reserved55_IRQHandler:
|
||||
ldr r0,=Reserved55_DriverIRQHandler
|
||||
bx r0
|
||||
.size Reserved55_IRQHandler, . - Reserved55_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak Reserved56_IRQHandler
|
||||
.type Reserved56_IRQHandler, %function
|
||||
Reserved56_IRQHandler:
|
||||
ldr r0,=Reserved56_DriverIRQHandler
|
||||
bx r0
|
||||
.size Reserved56_IRQHandler, . - Reserved56_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak Reserved57_IRQHandler
|
||||
.type Reserved57_IRQHandler, %function
|
||||
Reserved57_IRQHandler:
|
||||
ldr r0,=Reserved57_DriverIRQHandler
|
||||
bx r0
|
||||
.size Reserved57_IRQHandler, . - Reserved57_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak SDIO_IRQHandler
|
||||
.type SDIO_IRQHandler, %function
|
||||
SDIO_IRQHandler:
|
||||
ldr r0,=SDIO_DriverIRQHandler
|
||||
bx r0
|
||||
.size SDIO_IRQHandler, . - SDIO_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak Reserved59_IRQHandler
|
||||
.type Reserved59_IRQHandler, %function
|
||||
Reserved59_IRQHandler:
|
||||
ldr r0,=Reserved59_DriverIRQHandler
|
||||
bx r0
|
||||
.size Reserved59_IRQHandler, . - Reserved59_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak Reserved60_IRQHandler
|
||||
.type Reserved60_IRQHandler, %function
|
||||
Reserved60_IRQHandler:
|
||||
ldr r0,=Reserved60_DriverIRQHandler
|
||||
bx r0
|
||||
.size Reserved60_IRQHandler, . - Reserved60_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak Reserved61_IRQHandler
|
||||
.type Reserved61_IRQHandler, %function
|
||||
Reserved61_IRQHandler:
|
||||
ldr r0,=Reserved61_DriverIRQHandler
|
||||
bx r0
|
||||
.size Reserved61_IRQHandler, . - Reserved61_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak USB1_PHY_IRQHandler
|
||||
.type USB1_PHY_IRQHandler, %function
|
||||
USB1_PHY_IRQHandler:
|
||||
ldr r0,=USB1_PHY_DriverIRQHandler
|
||||
bx r0
|
||||
.size USB1_PHY_IRQHandler, . - USB1_PHY_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak USB1_IRQHandler
|
||||
.type USB1_IRQHandler, %function
|
||||
USB1_IRQHandler:
|
||||
ldr r0,=USB1_DriverIRQHandler
|
||||
bx r0
|
||||
.size USB1_IRQHandler, . - USB1_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak USB1_NEEDCLK_IRQHandler
|
||||
.type USB1_NEEDCLK_IRQHandler, %function
|
||||
USB1_NEEDCLK_IRQHandler:
|
||||
ldr r0,=USB1_NEEDCLK_DriverIRQHandler
|
||||
bx r0
|
||||
.size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak SEC_HYPERVISOR_CALL_IRQHandler
|
||||
.type SEC_HYPERVISOR_CALL_IRQHandler, %function
|
||||
SEC_HYPERVISOR_CALL_IRQHandler:
|
||||
ldr r0,=SEC_HYPERVISOR_CALL_DriverIRQHandler
|
||||
bx r0
|
||||
.size SEC_HYPERVISOR_CALL_IRQHandler, . - SEC_HYPERVISOR_CALL_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak SEC_GPIO_INT0_IRQ0_IRQHandler
|
||||
.type SEC_GPIO_INT0_IRQ0_IRQHandler, %function
|
||||
SEC_GPIO_INT0_IRQ0_IRQHandler:
|
||||
ldr r0,=SEC_GPIO_INT0_IRQ0_DriverIRQHandler
|
||||
bx r0
|
||||
.size SEC_GPIO_INT0_IRQ0_IRQHandler, . - SEC_GPIO_INT0_IRQ0_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak SEC_GPIO_INT0_IRQ1_IRQHandler
|
||||
.type SEC_GPIO_INT0_IRQ1_IRQHandler, %function
|
||||
SEC_GPIO_INT0_IRQ1_IRQHandler:
|
||||
ldr r0,=SEC_GPIO_INT0_IRQ1_DriverIRQHandler
|
||||
bx r0
|
||||
.size SEC_GPIO_INT0_IRQ1_IRQHandler, . - SEC_GPIO_INT0_IRQ1_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak PLU_IRQHandler
|
||||
.type PLU_IRQHandler, %function
|
||||
PLU_IRQHandler:
|
||||
ldr r0,=PLU_DriverIRQHandler
|
||||
bx r0
|
||||
.size PLU_IRQHandler, . - PLU_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak SEC_VIO_IRQHandler
|
||||
.type SEC_VIO_IRQHandler, %function
|
||||
SEC_VIO_IRQHandler:
|
||||
ldr r0,=SEC_VIO_DriverIRQHandler
|
||||
bx r0
|
||||
.size SEC_VIO_IRQHandler, . - SEC_VIO_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak HASHCRYPT_IRQHandler
|
||||
.type HASHCRYPT_IRQHandler, %function
|
||||
HASHCRYPT_IRQHandler:
|
||||
ldr r0,=HASHCRYPT_DriverIRQHandler
|
||||
bx r0
|
||||
.size HASHCRYPT_IRQHandler, . - HASHCRYPT_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak CASER_IRQHandler
|
||||
.type CASER_IRQHandler, %function
|
||||
CASER_IRQHandler:
|
||||
ldr r0,=CASER_DriverIRQHandler
|
||||
bx r0
|
||||
.size CASER_IRQHandler, . - CASER_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak PUF_IRQHandler
|
||||
.type PUF_IRQHandler, %function
|
||||
PUF_IRQHandler:
|
||||
ldr r0,=PUF_DriverIRQHandler
|
||||
bx r0
|
||||
.size PUF_IRQHandler, . - PUF_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak PQ_IRQHandler
|
||||
.type PQ_IRQHandler, %function
|
||||
PQ_IRQHandler:
|
||||
ldr r0,=PQ_DriverIRQHandler
|
||||
bx r0
|
||||
.size PQ_IRQHandler, . - PQ_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak DMA1_IRQHandler
|
||||
.type DMA1_IRQHandler, %function
|
||||
DMA1_IRQHandler:
|
||||
ldr r0,=DMA1_DriverIRQHandler
|
||||
bx r0
|
||||
.size DMA1_IRQHandler, . - DMA1_IRQHandler
|
||||
|
||||
.align 1
|
||||
.thumb_func
|
||||
.weak FLEXCOMM8_IRQHandler
|
||||
.type FLEXCOMM8_IRQHandler, %function
|
||||
FLEXCOMM8_IRQHandler:
|
||||
ldr r0,=FLEXCOMM8_DriverIRQHandler
|
||||
bx r0
|
||||
.size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler
|
||||
|
||||
/* Macro to define default handlers. Default handler
|
||||
* will be weak symbol and just dead loops. They can be
|
||||
* overwritten by other handlers */
|
||||
.macro def_irq_handler handler_name
|
||||
.weak \handler_name
|
||||
.set \handler_name, DefaultISR
|
||||
.endm
|
||||
/* Exception Handlers */
|
||||
def_irq_handler MemManage_Handler
|
||||
def_irq_handler BusFault_Handler
|
||||
def_irq_handler UsageFault_Handler
|
||||
def_irq_handler SecureFault_Handler
|
||||
def_irq_handler DebugMon_Handler
|
||||
def_irq_handler WDT_BOD_DriverIRQHandler /* Windowed watchdog timer, Brownout detect, Flash interrupt */
|
||||
def_irq_handler DMA0_DriverIRQHandler /* DMA0 controller */
|
||||
def_irq_handler GINT0_DriverIRQHandler /* GPIO group 0 */
|
||||
def_irq_handler GINT1_DriverIRQHandler /* GPIO group 1 */
|
||||
def_irq_handler PIN_INT0_DriverIRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */
|
||||
def_irq_handler PIN_INT1_DriverIRQHandler /* Pin interrupt 1or pattern match engine slice 1 */
|
||||
def_irq_handler PIN_INT2_DriverIRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */
|
||||
def_irq_handler PIN_INT3_DriverIRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */
|
||||
def_irq_handler UTICK0_DriverIRQHandler /* Micro-tick Timer */
|
||||
def_irq_handler MRT0_DriverIRQHandler /* Multi-rate timer */
|
||||
def_irq_handler CTIMER0_DriverIRQHandler /* Standard counter/timer CTIMER0 */
|
||||
def_irq_handler CTIMER1_DriverIRQHandler /* Standard counter/timer CTIMER1 */
|
||||
def_irq_handler SCT0_DriverIRQHandler /* SCTimer/PWM */
|
||||
def_irq_handler CTIMER3_DriverIRQHandler /* Standard counter/timer CTIMER3 */
|
||||
def_irq_handler FLEXCOMM0_DriverIRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, I2S, FLEXCOMM) */
|
||||
def_irq_handler FLEXCOMM1_DriverIRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, I2S, FLEXCOMM) */
|
||||
def_irq_handler FLEXCOMM2_DriverIRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, I2S, FLEXCOMM) */
|
||||
def_irq_handler FLEXCOMM3_DriverIRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, I2S, FLEXCOMM) */
|
||||
def_irq_handler FLEXCOMM4_DriverIRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, I2S, FLEXCOMM) */
|
||||
def_irq_handler FLEXCOMM5_DriverIRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C, I2S, FLEXCOMM) */
|
||||
def_irq_handler FLEXCOMM6_DriverIRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S, FLEXCOMM) */
|
||||
def_irq_handler FLEXCOMM7_DriverIRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S, FLEXCOMM) */
|
||||
def_irq_handler ADC0_DriverIRQHandler /* ADC0 */
|
||||
def_irq_handler Reserved39_DriverIRQHandler /* Reserved interrupt */
|
||||
def_irq_handler ACMP_DriverIRQHandler /* ACMP interrupts */
|
||||
def_irq_handler Reserved41_DriverIRQHandler /* Reserved interrupt */
|
||||
def_irq_handler Reserved42_DriverIRQHandler /* Reserved interrupt */
|
||||
def_irq_handler USB0_NEEDCLK_DriverIRQHandler /* USB Activity Wake-up Interrupt */
|
||||
def_irq_handler USB0_DriverIRQHandler /* USB device */
|
||||
def_irq_handler RTC_DriverIRQHandler /* RTC alarm and wake-up interrupts */
|
||||
def_irq_handler Reserved46_DriverIRQHandler /* Reserved interrupt */
|
||||
def_irq_handler MAILBOX_DriverIRQHandler /* WAKEUP,Mailbox interrupt (present on selected devices) */
|
||||
def_irq_handler PIN_INT4_DriverIRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */
|
||||
def_irq_handler PIN_INT5_DriverIRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */
|
||||
def_irq_handler PIN_INT6_DriverIRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */
|
||||
def_irq_handler PIN_INT7_DriverIRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */
|
||||
def_irq_handler CTIMER2_DriverIRQHandler /* Standard counter/timer CTIMER2 */
|
||||
def_irq_handler CTIMER4_DriverIRQHandler /* Standard counter/timer CTIMER4 */
|
||||
def_irq_handler OS_EVENT_DriverIRQHandler /* OSEVTIMER0 and OSEVTIMER0_WAKEUP interrupts */
|
||||
def_irq_handler Reserved55_DriverIRQHandler /* Reserved interrupt */
|
||||
def_irq_handler Reserved56_DriverIRQHandler /* Reserved interrupt */
|
||||
def_irq_handler Reserved57_DriverIRQHandler /* Reserved interrupt */
|
||||
def_irq_handler SDIO_DriverIRQHandler /* SD/MMC */
|
||||
def_irq_handler Reserved59_DriverIRQHandler /* Reserved interrupt */
|
||||
def_irq_handler Reserved60_DriverIRQHandler /* Reserved interrupt */
|
||||
def_irq_handler Reserved61_DriverIRQHandler /* Reserved interrupt */
|
||||
def_irq_handler USB1_PHY_DriverIRQHandler /* USB1_PHY */
|
||||
def_irq_handler USB1_DriverIRQHandler /* USB1 interrupt */
|
||||
def_irq_handler USB1_NEEDCLK_DriverIRQHandler /* USB1 activity */
|
||||
def_irq_handler SEC_HYPERVISOR_CALL_DriverIRQHandler /* SEC_HYPERVISOR_CALL interrupt */
|
||||
def_irq_handler SEC_GPIO_INT0_IRQ0_DriverIRQHandler /* SEC_GPIO_INT0_IRQ0 interrupt */
|
||||
def_irq_handler SEC_GPIO_INT0_IRQ1_DriverIRQHandler /* SEC_GPIO_INT0_IRQ1 interrupt */
|
||||
def_irq_handler PLU_DriverIRQHandler /* PLU interrupt */
|
||||
def_irq_handler SEC_VIO_DriverIRQHandler /* SEC_VIO interrupt */
|
||||
def_irq_handler HASHCRYPT_DriverIRQHandler /* HASHCRYPT interrupt */
|
||||
def_irq_handler CASER_DriverIRQHandler /* CASPER interrupt */
|
||||
def_irq_handler PUF_DriverIRQHandler /* PUF interrupt */
|
||||
def_irq_handler PQ_DriverIRQHandler /* PQ interrupt */
|
||||
def_irq_handler DMA1_DriverIRQHandler /* DMA1 interrupt */
|
||||
def_irq_handler FLEXCOMM8_DriverIRQHandler /* Flexcomm Interface 8 (SPI, , FLEXCOMM) */
|
||||
|
||||
.end
|
||||
206
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/USB/USBD_Config_0.c
vendored
Normal file
206
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/USB/USBD_Config_0.c
vendored
Normal file
@@ -0,0 +1,206 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
* MDK Middleware - Component ::USB:Device
|
||||
* Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
|
||||
*------------------------------------------------------------------------------
|
||||
* Name: USBD_Config_0.c
|
||||
* Purpose: USB Device Configuration
|
||||
* Rev.: V5.2.0
|
||||
*------------------------------------------------------------------------------
|
||||
* Use the following configuration settings in the Device Class configuration
|
||||
* files to assign a Device Class to this USB Device 0.
|
||||
*
|
||||
* Configuration Setting Value
|
||||
* --------------------- -----
|
||||
* Assign Device Class to USB Device # = 0
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <h>USB Device 0
|
||||
// <o>Connect to hardware via Driver_USBD# <0-255>
|
||||
// <i>Select driver control block for hardware interface.
|
||||
#define USBD0_PORT 1
|
||||
|
||||
// <o.0>High-speed
|
||||
// <i>Enable High-speed functionality (if device supports it).
|
||||
#define USBD0_HS 1
|
||||
|
||||
// <h>Device Settings
|
||||
// <i>These settings are used to create the Device Descriptor
|
||||
// <o>Max Endpoint 0 Packet Size
|
||||
// <i>Maximum packet size for Endpoint 0 (bMaxPacketSize0).
|
||||
// <8=>8 Bytes <16=>16 Bytes <32=>32 Bytes <64=>64 Bytes
|
||||
#define USBD0_MAX_PACKET0 64
|
||||
|
||||
// <o.0..15>Vendor ID <0x0000-0xFFFF>
|
||||
// <i>Vendor ID assigned by USB-IF (idVendor).
|
||||
#define USBD0_DEV_DESC_IDVENDOR 0xC251
|
||||
|
||||
// <o.0..15>Product ID <0x0000-0xFFFF>
|
||||
// <i>Product ID assigned by manufacturer (idProduct).
|
||||
#define USBD0_DEV_DESC_IDPRODUCT 0xF00B
|
||||
|
||||
// <o.0..15>Device Release Number <0x0000-0xFFFF>
|
||||
// <i>Device Release Number in binary-coded decimal (bcdDevice)
|
||||
#define USBD0_DEV_DESC_BCDDEVICE 0x0100
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Configuration Settings
|
||||
// <i>These settings are used to create the Configuration Descriptor.
|
||||
// <o.6>Power
|
||||
// <i>Default Power Setting (D6: of bmAttributes).
|
||||
// <0=>Bus-powered
|
||||
// <1=>Self-powered
|
||||
// <o.5>Remote Wakeup
|
||||
// <i>Configuration support for Remote Wakeup (D5: of bmAttributes).
|
||||
#define USBD0_CFG_DESC_BMATTRIBUTES 0x80
|
||||
|
||||
// <o.0..7>Maximum Power Consumption (in mA) <0-510><#/2>
|
||||
// <i>Maximum Power Consumption of USB Device from bus in this
|
||||
// <i>specific configuration when device is fully operational (bMaxPower).
|
||||
#define USBD0_CFG_DESC_BMAXPOWER 250
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>String Settings
|
||||
// <i>These settings are used to create the String Descriptor.
|
||||
// <o.0..15>Language ID <0x0000-0xFCFF>
|
||||
// <i>English (United States) = 0x0409.
|
||||
#define USBD0_STR_DESC_LANGID 0x0409
|
||||
|
||||
// <s.126>Manufacturer String
|
||||
// <i>String Descriptor describing Manufacturer.
|
||||
#define USBD0_STR_DESC_MAN L"KEIL - Tools By ARM"
|
||||
|
||||
// <s.126>Product String
|
||||
// <i>String Descriptor describing Product.
|
||||
#define USBD0_STR_DESC_PROD L"MCU-LINK"
|
||||
|
||||
// <e.0>Serial Number String
|
||||
// <i>Enable Serial Number String.
|
||||
// <i>If disabled Serial Number String will not be assigned to USB Device.
|
||||
#define USBD0_STR_DESC_SER_EN 1
|
||||
|
||||
// <s.126>Default value
|
||||
// <i>Default device's Serial Number String.
|
||||
#define USBD0_STR_DESC_SER L"0001A0000000"
|
||||
|
||||
// <o.0..7>Maximum Length (in characters) <0-126>
|
||||
// <i>Specifies the maximum number of Serial Number String characters that can be set at run-time.
|
||||
// <i>Maximum value is 126. Use value 0 to disable RAM allocation for string.
|
||||
#define USBD0_STR_DESC_SER_MAX_LEN 16
|
||||
|
||||
// </e>
|
||||
// </h>
|
||||
|
||||
// <h>Microsoft OS Descriptors Settings
|
||||
// <i>These settings are used to create the Microsoft OS Descriptors.
|
||||
// <e.0>OS String
|
||||
// <i>Enable creation of Microsoft OS String and Extended Compat ID OS Feature Descriptors.
|
||||
#define USBD0_OS_DESC_EN 1
|
||||
|
||||
// <o.0..7>Vendor Code <0x01-0xFF>
|
||||
// <i>Specifies Vendor Code used to retrieve OS Feature Descriptors.
|
||||
#define USBD0_OS_DESC_VENDOR_CODE 0x01
|
||||
|
||||
// </e>
|
||||
// </h>
|
||||
|
||||
// <o>Control Transfer Buffer Size <64-65536:64>
|
||||
// <i>Specifies size of buffer used for Control Transfers.
|
||||
// <i>It should be at least as big as maximum packet size for Endpoint 0.
|
||||
#define USBD0_EP0_BUF_SIZE 128
|
||||
|
||||
// <h>OS Resources Settings
|
||||
// <i>These settings are used to optimize usage of OS resources.
|
||||
// <o>Core Thread Stack Size <64-65536>
|
||||
#define USBD0_CORE_THREAD_STACK_SIZE 1024
|
||||
|
||||
// Core Thread Priority
|
||||
#define USBD0_CORE_THREAD_PRIORITY osPriorityAboveNormal
|
||||
|
||||
// </h>
|
||||
// </h>
|
||||
|
||||
|
||||
#include "RTE_Components.h"
|
||||
|
||||
#ifdef RTE_USB_Device_CustomClass_0
|
||||
#include "USBD_Config_CustomClass_0.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CustomClass_1
|
||||
#include "USBD_Config_CustomClass_1.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CustomClass_2
|
||||
#include "USBD_Config_CustomClass_2.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CustomClass_3
|
||||
#include "USBD_Config_CustomClass_3.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_USB_Device_HID_0
|
||||
#include "USBD_Config_HID_0.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_HID_1
|
||||
#include "USBD_Config_HID_1.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_HID_2
|
||||
#include "USBD_Config_HID_2.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_HID_3
|
||||
#include "USBD_Config_HID_3.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_USB_Device_MSC_0
|
||||
#include "USBD_Config_MSC_0.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_MSC_1
|
||||
#include "USBD_Config_MSC_1.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_MSC_2
|
||||
#include "USBD_Config_MSC_2.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_MSC_3
|
||||
#include "USBD_Config_MSC_3.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_USB_Device_CDC_0
|
||||
#include "USBD_Config_CDC_0.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CDC_1
|
||||
#include "USBD_Config_CDC_1.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CDC_2
|
||||
#include "USBD_Config_CDC_2.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CDC_3
|
||||
#include "USBD_Config_CDC_3.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CDC_4
|
||||
#include "USBD_Config_CDC_4.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CDC_5
|
||||
#include "USBD_Config_CDC_5.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CDC_6
|
||||
#include "USBD_Config_CDC_6.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_CDC_7
|
||||
#include "USBD_Config_CDC_7.h"
|
||||
#endif
|
||||
|
||||
#ifdef RTE_USB_Device_ADC_0
|
||||
#include "USBD_Config_ADC_0.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_ADC_1
|
||||
#include "USBD_Config_ADC_1.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_ADC_2
|
||||
#include "USBD_Config_ADC_2.h"
|
||||
#endif
|
||||
#ifdef RTE_USB_Device_ADC_3
|
||||
#include "USBD_Config_ADC_3.h"
|
||||
#endif
|
||||
|
||||
#include "usbd_config.h"
|
||||
364
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/USB/USBD_Config_CDC_0.h
vendored
Normal file
364
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/USB/USBD_Config_CDC_0.h
vendored
Normal file
@@ -0,0 +1,364 @@
|
||||
/*------------------------------------------------------------------------------
|
||||
* MDK Middleware - Component ::USB:Device
|
||||
* Copyright (c) 2004-2019 Arm Limited (or its affiliates). All rights reserved.
|
||||
*------------------------------------------------------------------------------
|
||||
* Name: USBD_Config_CDC_0.h
|
||||
* Purpose: USB Device Communication Device Class (CDC) Configuration
|
||||
* Rev.: V5.2.0
|
||||
*----------------------------------------------------------------------------*/
|
||||
|
||||
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
|
||||
|
||||
// <h>USB Device: Communication Device Class (CDC) 0
|
||||
// <o>Assign Device Class to USB Device # <0-3>
|
||||
// <i>Select USB Device that is used for this Device Class instance
|
||||
#define USBD_CDC0_DEV 0
|
||||
|
||||
// <o>Communication Class Subclass
|
||||
// <i>Specifies the model used by the CDC class.
|
||||
// <2=>Abstract Control Model (ACM)
|
||||
// <13=>Network Control Model (NCM)
|
||||
#define USBD_CDC0_SUBCLASS 2
|
||||
|
||||
// <o>Communication Class Protocol
|
||||
// <i>Specifies the protocol used by the CDC class.
|
||||
// <0=>No protocol (Virtual COM)
|
||||
// <255=>Vendor-specific (RNDIS)
|
||||
#define USBD_CDC0_PROTOCOL 0
|
||||
|
||||
// <h>Interrupt Endpoint Settings
|
||||
// <i>By default, the settings match the first USB Class instance in a USB Device.
|
||||
// <i>Endpoint conflicts are flagged by compile-time error messages.
|
||||
|
||||
// <o.0..3>Interrupt IN Endpoint Number
|
||||
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
|
||||
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
|
||||
#define USBD_CDC0_EP_INT_IN 3
|
||||
|
||||
|
||||
// <h>Endpoint Settings
|
||||
// <i>Parameters are used to create Endpoint Descriptors
|
||||
// <i>and for memory allocation in the USB component.
|
||||
|
||||
// <h>Full/Low-speed (High-speed disabled)
|
||||
// <i>Parameters apply when High-speed is disabled in USBD_Config_n.c
|
||||
// <o.0..6>Maximum Endpoint Packet Size (in bytes) <0-64>
|
||||
// <i>Specifies the physical packet size used for information exchange.
|
||||
// <i>Maximum value is 64.
|
||||
#define USBD_CDC0_WMAXPACKETSIZE 16
|
||||
|
||||
// <o.0..7>Endpoint polling Interval (in ms) <1-255>
|
||||
// <i>Specifies the frequency of requests initiated by USB Host for
|
||||
// <i>getting the notification.
|
||||
#define USBD_CDC0_BINTERVAL 2
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>High-speed
|
||||
// <i>Parameters apply when High-speed is enabled in USBD_Config_n.c
|
||||
//
|
||||
// <o.0..10>Maximum Endpoint Packet Size (in bytes) <0-1024>
|
||||
// <i>Specifies the physical packet size used for information exchange.
|
||||
// <i>Maximum value is 1024.
|
||||
// <o.11..12>Additional transactions per microframe
|
||||
// <i>Additional transactions improve communication performance.
|
||||
// <0=>None <1=>1 additional <2=>2 additional
|
||||
#define USBD_CDC0_HS_WMAXPACKETSIZE 16
|
||||
|
||||
// <o.0..4>Endpoint polling Interval (in 125 us intervals)
|
||||
// <i>Specifies the frequency of requests initiated by USB Host for
|
||||
// <i>getting the notification.
|
||||
// <1=> 1 <2=> 2 <3=> 4 <4=> 8
|
||||
// <5=> 16 <6=> 32 <7=> 64 <8=> 128
|
||||
// <9=> 256 <10=> 512 <11=> 1024 <12=> 2048
|
||||
// <13=>4096 <14=>8192 <15=>16384 <16=>32768
|
||||
#define USBD_CDC0_HS_BINTERVAL 2
|
||||
|
||||
// </h>
|
||||
// </h>
|
||||
// </h>
|
||||
|
||||
|
||||
// <h>Bulk Endpoint Settings
|
||||
// <i>By default, the settings match the first USB Class instance in a USB Device.
|
||||
// <i>Endpoint conflicts are flagged by compile-time error messages.
|
||||
|
||||
// <o.0..3>Bulk IN Endpoint Number
|
||||
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
|
||||
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
|
||||
#define USBD_CDC0_EP_BULK_IN 4
|
||||
|
||||
// <o.0..3>Bulk OUT Endpoint Number
|
||||
// <1=>1 <2=>2 <3=>3 <4=>4 <5=>5 <6=>6 <7=>7
|
||||
// <8=>8 <9=>9 <10=>10 <11=>11 <12=>12 <13=>13 <14=>14 <15=>15
|
||||
#define USBD_CDC0_EP_BULK_OUT 4
|
||||
|
||||
|
||||
// <h>Endpoint Settings
|
||||
// <i>Parameters are used to create USB Descriptors and for memory
|
||||
// <i>allocation in the USB component.
|
||||
//
|
||||
// <h>Full/Low-speed (High-speed disabled)
|
||||
// <i>Parameters apply when High-speed is disabled in USBD_Config_n.c
|
||||
// <o.0..6>Maximum Endpoint Packet Size (in bytes) <8=>8 <16=>16 <32=>32 <64=>64
|
||||
// <i>Specifies the physical packet size used for information exchange.
|
||||
// <i>Maximum value is 64.
|
||||
#define USBD_CDC0_WMAXPACKETSIZE1 64
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>High-speed
|
||||
// <i>Parameters apply when High-speed is enabled in USBD_Config_n.c
|
||||
//
|
||||
// <o.0..9>Maximum Endpoint Packet Size (in bytes) <512=>512
|
||||
// <i>Specifies the physical packet size used for information exchange.
|
||||
// <i>Only available value is 512.
|
||||
#define USBD_CDC0_HS_WMAXPACKETSIZE1 512
|
||||
|
||||
// <o.0..7>Maximum NAK Rate <0-255>
|
||||
// <i>Specifies the interval in which Bulk Endpoint can NAK.
|
||||
// <i>Value of 0 indicates that Bulk Endpoint never NAKs.
|
||||
#define USBD_CDC0_HS_BINTERVAL1 0
|
||||
|
||||
// </h>
|
||||
// </h>
|
||||
// </h>
|
||||
|
||||
// <h>Communication Device Class Settings
|
||||
// <i>Parameters are used to create USB Descriptors and for memory allocation
|
||||
// <i>in the USB component.
|
||||
//
|
||||
// <s.126>Communication Class Interface String
|
||||
#define USBD_CDC0_CIF_STR_DESC L"USB_CDC0_0"
|
||||
|
||||
// <s.126>Data Class Interface String
|
||||
#define USBD_CDC0_DIF_STR_DESC L"USB_CDC0_1"
|
||||
|
||||
// <h>Abstract Control Model Settings
|
||||
|
||||
// <h>Call Management Capabilities
|
||||
// <i>Specifies which call management functionality is supported.
|
||||
// <o.1>Call Management channel
|
||||
// <0=>Communication Class Interface only
|
||||
// <1=>Communication and Data Class Interface
|
||||
// <o.0>Device Call Management handling
|
||||
// <0=>None
|
||||
// <1=>All
|
||||
// </h>
|
||||
#define USBD_CDC0_ACM_CM_BM_CAPABILITIES 0x03
|
||||
|
||||
// <h>Abstract Control Management Capabilities
|
||||
// <i>Specifies which abstract control management functionality is supported.
|
||||
// <o.3>D3 bit
|
||||
// <i>Enabled = Supports the notification Network_Connection
|
||||
// <o.2>D2 bit
|
||||
// <i>Enabled = Supports the request Send_Break
|
||||
// <o.1>D1 bit
|
||||
// <i>Enabled = Supports the following requests: Set_Line_Coding, Get_Line_Coding,
|
||||
// <i> Set_Control_Line_State, and notification Serial_State
|
||||
// <o.0>D0 bit
|
||||
// <i>Enabled = Supports the following requests: Set_Comm_Feature, Clear_Comm_Feature and Get_Comm_Feature
|
||||
// </h>
|
||||
#define USBD_CDC0_ACM_ACM_BM_CAPABILITIES 0x06
|
||||
|
||||
// <o>Maximum Communication Device Send Buffer Size
|
||||
// <i>Specifies size of buffer used for sending of data to USB Host.
|
||||
// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes
|
||||
// <128=> 128 Bytes <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes
|
||||
// <2048=>2048 Bytes <4096=>4096 Bytes <8192=>8192 Bytes <16384=>16384 Bytes
|
||||
#define USBD_CDC0_ACM_SEND_BUF_SIZE 1024
|
||||
|
||||
// <o>Maximum Communication Device Receive Buffer Size
|
||||
// <i>Specifies size of buffer used for receiving of data from USB Host.
|
||||
// <i>Minimum size must be twice as large as Maximum Packet Size for Bulk OUT Endpoint.
|
||||
// <i>Suggested size is three or more times larger then Maximum Packet Size for Bulk OUT Endpoint.
|
||||
// <8=> 8 Bytes <16=> 16 Bytes <32=> 32 Bytes <64=> 64 Bytes
|
||||
// <128=> 128 Bytes <256=> 256 Bytes <512=> 512 Bytes <1024=> 1024 Bytes
|
||||
// <2048=>2048 Bytes <4096=>4096 Bytes <8192=>8192 Bytes <16384=>16384 Bytes
|
||||
#define USBD_CDC0_ACM_RECEIVE_BUF_SIZE 2048
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>Network Control Model Settings
|
||||
|
||||
// <s.12>MAC Address String
|
||||
// <i>Specifies 48-bit Ethernet MAC address.
|
||||
#define USBD_CDC0_NCM_MAC_ADDRESS L"1E306CA2455E"
|
||||
|
||||
// <h>Ethernet Statistics
|
||||
// <i>Specifies Ethernet statistic functions supported.
|
||||
// <o.0>XMIT_OK
|
||||
// <i>Frames transmitted without errors
|
||||
// <o.1>RVC_OK
|
||||
// <i>Frames received without errors
|
||||
// <o.2>XMIT_ERROR
|
||||
// <i>Frames not transmitted, or transmitted with errors
|
||||
// <o.3>RCV_ERROR
|
||||
// <i>Frames received with errors that are not delivered to the USB host.
|
||||
// <o.4>RCV_NO_BUFFER
|
||||
// <i>Frame missed, no buffers
|
||||
// <o.5>DIRECTED_BYTES_XMIT
|
||||
// <i>Directed bytes transmitted without errors
|
||||
// <o.6>DIRECTED_FRAMES_XMIT
|
||||
// <i>Directed frames transmitted without errors
|
||||
// <o.7>MULTICAST_BYTES_XMIT
|
||||
// <i>Multicast bytes transmitted without errors
|
||||
// <o.8>MULTICAST_FRAMES_XMIT
|
||||
// <i>Multicast frames transmitted without errors
|
||||
// <o.9>BROADCAST_BYTES_XMIT
|
||||
// <i>Broadcast bytes transmitted without errors
|
||||
// <o.10>BROADCAST_FRAMES_XMIT
|
||||
// <i>Broadcast frames transmitted without errors
|
||||
// <o.11>DIRECTED_BYTES_RCV
|
||||
// <i>Directed bytes received without errors
|
||||
// <o.12>DIRECTED_FRAMES_RCV
|
||||
// <i>Directed frames received without errors
|
||||
// <o.13>MULTICAST_BYTES_RCV
|
||||
// <i>Multicast bytes received without errors
|
||||
// <o.14>MULTICAST_FRAMES_RCV
|
||||
// <i>Multicast frames received without errors
|
||||
// <o.15>BROADCAST_BYTES_RCV
|
||||
// <i>Broadcast bytes received without errors
|
||||
// <o.16>BROADCAST_FRAMES_RCV
|
||||
// <i>Broadcast frames received without errors
|
||||
// <o.17>RCV_CRC_ERROR
|
||||
// <i>Frames received with circular redundancy check (CRC) or frame check sequence (FCS) error
|
||||
// <o.18>TRANSMIT_QUEUE_LENGTH
|
||||
// <i>Length of transmit queue
|
||||
// <o.19>RCV_ERROR_ALIGNMENT
|
||||
// <i>Frames received with alignment error
|
||||
// <o.20>XMIT_ONE_COLLISION
|
||||
// <i>Frames transmitted with one collision
|
||||
// <o.21>XMIT_MORE_COLLISIONS
|
||||
// <i>Frames transmitted with more than one collision
|
||||
// <o.22>XMIT_DEFERRED
|
||||
// <i>Frames transmitted after deferral
|
||||
// <o.23>XMIT_MAX_COLLISIONS
|
||||
// <i>Frames not transmitted due to collisions
|
||||
// <o.24>RCV_OVERRUN
|
||||
// <i>Frames not received due to overrun
|
||||
// <o.25>XMIT_UNDERRUN
|
||||
// <i>Frames not transmitted due to underrun
|
||||
// <o.26>XMIT_HEARTBEAT_FAILURE
|
||||
// <i>Frames transmitted with heartbeat failure
|
||||
// <o.27>XMIT_TIMES_CRS_LOST
|
||||
// <i>Times carrier sense signal lost during transmission
|
||||
// <o.28>XMIT_LATE_COLLISIONS
|
||||
// <i>Late collisions detected
|
||||
// </h>
|
||||
#define USBD_CDC0_NCM_BM_ETHERNET_STATISTICS 0x00000003
|
||||
|
||||
// <o>Maximum Segment Size
|
||||
// <i>Specifies maximum segment size that Ethernet device is capable of supporting.
|
||||
// <i>Typically 1514 bytes.
|
||||
#define USBD_CDC0_NCM_W_MAX_SEGMENT_SIZE 1514
|
||||
|
||||
// <o.15>Multicast Filtering <0=>Perfect (no hashing) <1=>Imperfect (hashing)
|
||||
// <i>Specifies multicast filtering type.
|
||||
// <o.0..14>Number of Multicast Filters
|
||||
// <i>Specifies number of multicast filters that can be configured by the USB Host.
|
||||
#define USBD_CDC0_NCM_W_NUMBER_MC_FILTERS 1
|
||||
|
||||
// <o.0..7>Number of Power Filters
|
||||
// <i>Specifies number of pattern filters that are available for causing wake-up of the USB Host.
|
||||
#define USBD_CDC0_NCM_B_NUMBER_POWER_FILTERS 0
|
||||
|
||||
// <h>Network Capabilities
|
||||
// <i>Specifies which functions are supported.
|
||||
// <o.4>SetCrcMode/GetCrcMode
|
||||
// <o.3>SetMaxDatagramSize/GetMaxDatagramSize
|
||||
// <o.1>SetNetAddress/GetNetAddress
|
||||
// <o.0>SetEthernetPacketFilter
|
||||
// </h>
|
||||
#define USBD_CDC0_NCM_BM_NETWORK_CAPABILITIES 0x1B
|
||||
|
||||
// <h>NTB Parameters
|
||||
// <i>Specifies NTB parameters reported by GetNtbParameters function.
|
||||
|
||||
// <h>NTB Formats Supported (bmNtbFormatsSupported)
|
||||
// <i>Specifies NTB formats supported.
|
||||
// <o.0>16-bit NTB (always supported)
|
||||
// <o.1>32-bit NTB
|
||||
// </h>
|
||||
#define USBD_CDC0_NCM_BM_NTB_FORMATS_SUPPORTED 0x0001
|
||||
|
||||
// <h>IN Data Pipe
|
||||
//
|
||||
// <o>Maximum NTB Size (dwNtbInMaxSize)
|
||||
// <i>Specifies maximum IN NTB size in bytes.
|
||||
#define USBD_CDC0_NCM_DW_NTB_IN_MAX_SIZE 4096
|
||||
|
||||
// <o.0..15>NTB Datagram Payload Alignment Divisor (wNdpInDivisor)
|
||||
// <i>Specifies divisor used for IN NTB Datagram payload alignment.
|
||||
#define USBD_CDC0_NCM_W_NDP_IN_DIVISOR 4
|
||||
|
||||
// <o.0..15>NTB Datagram Payload Alignment Remainder (wNdpInPayloadRemainder)
|
||||
// <i>Specifies remainder used to align input datagram payload within the NTB.
|
||||
// <i>(Payload Offset) % (wNdpInDivisor) = wNdpInPayloadRemainder
|
||||
#define USBD_CDC0_NCM_W_NDP_IN_PAYLOAD_REMINDER 0
|
||||
|
||||
// <o.0..15>NDP Alignment Modulus in NTB (wNdpInAlignment)
|
||||
// <i>Specifies NDP alignment modulus for NTBs on the IN pipe.
|
||||
// <i>Shall be power of 2, and shall be at least 4.
|
||||
#define USBD_CDC0_NCM_W_NDP_IN_ALIGNMENT 4
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>OUT Data Pipe
|
||||
//
|
||||
// <o>Maximum NTB Size (dwNtbOutMaxSize)
|
||||
// <i>Specifies maximum OUT NTB size in bytes.
|
||||
#define USBD_CDC0_NCM_DW_NTB_OUT_MAX_SIZE 4096
|
||||
|
||||
// <o.0..15>NTB Datagram Payload Alignment Divisor (wNdpOutDivisor)
|
||||
// <i>Specifies divisor used for OUT NTB Datagram payload alignment.
|
||||
#define USBD_CDC0_NCM_W_NDP_OUT_DIVISOR 4
|
||||
|
||||
// <o.0..15>NTB Datagram Payload Alignment Remainder (wNdpOutPayloadRemainder)
|
||||
// <i>Specifies remainder used to align output datagram payload within the NTB.
|
||||
// <i>(Payload Offset) % (wNdpOutDivisor) = wNdpOutPayloadRemainder
|
||||
#define USBD_CDC0_NCM_W_NDP_OUT_PAYLOAD_REMINDER 0
|
||||
|
||||
// <o.0..15>NDP Alignment Modulus in NTB (wNdpOutAlignment)
|
||||
// <i>Specifies NDP alignment modulus for NTBs on the IN pipe.
|
||||
// <i>Shall be power of 2, and shall be at least 4.
|
||||
#define USBD_CDC0_NCM_W_NDP_OUT_ALIGNMENT 4
|
||||
|
||||
// </h>
|
||||
|
||||
// </h>
|
||||
|
||||
// <o.0>Raw Data Access API
|
||||
// <i>Enables or disables Raw Data Access API.
|
||||
#define USBD_CDC0_NCM_RAW_ENABLE 0
|
||||
|
||||
// <o>IN NTB Data Buffering <1=>Single Buffer <2=>Double Buffer
|
||||
// <i>Specifies buffering used for sending data to USB Host.
|
||||
// <i>Not used when RAW Data Access API is enabled.
|
||||
#define USBD_CDC0_NCM_NTB_IN_BUF_CNT 1
|
||||
|
||||
// <o>OUT NTB Data Buffering <1=>Single Buffer <2=>Double Buffer
|
||||
// <i>Specifies buffering used for receiving data from USB Host.
|
||||
// <i>Not used when RAW Data Access API is enabled.
|
||||
#define USBD_CDC0_NCM_NTB_OUT_BUF_CNT 1
|
||||
|
||||
// </h>
|
||||
|
||||
// </h>
|
||||
|
||||
// <h>OS Resources Settings
|
||||
// <i>These settings are used to optimize usage of OS resources.
|
||||
// <o>Communication Device Class Interrupt Endpoint Thread Stack Size <64-65536>
|
||||
#define USBD_CDC0_INT_THREAD_STACK_SIZE 512
|
||||
|
||||
// Communication Device Class Interrupt Endpoint Thread Priority
|
||||
#define USBD_CDC0_INT_THREAD_PRIORITY osPriorityAboveNormal
|
||||
|
||||
// <o>Communication Device Class Bulk Endpoints Thread Stack Size <64-65536>
|
||||
#define USBD_CDC0_BULK_THREAD_STACK_SIZE 512
|
||||
|
||||
// Communication Device Class Bulk Endpoints Thread Priority
|
||||
#define USBD_CDC0_BULK_THREAD_PRIORITY osPriorityAboveNormal
|
||||
|
||||
// </h>
|
||||
// </h>
|
||||
3771
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/USB/USBD_Config_CustomClass_0.h
vendored
Normal file
3771
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/RTE/USB/USBD_Config_CustomClass_0.h
vendored
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user