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OneOfEleven
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external/CMSIS_5/CMSIS/DoxyGen/Core/core.dxy
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external/CMSIS_5/CMSIS/DoxyGen/Core/core.dxy
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external/CMSIS_5/CMSIS/DoxyGen/Core/core_CM0-7.dxy
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external/CMSIS_5/CMSIS/DoxyGen/Core/src/MISRA.txt
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external/CMSIS_5/CMSIS/DoxyGen/Core/src/MISRA.txt
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/** \page coreMISRA_Exceptions_pg MISRA-C Deviations
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CMSIS-Core (Cortex-M) uses the common coding rules for CMSIS components that are documented under
|
||||
\ifnot FuSaRTS <a href="../../General/html/index.html"><b>Introduction</b></a> \endif \if FuSaRTS <a href="../../Safety/html/index.html#CodingRules"><b>Coding Rules</b></a> \endif.
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||||
*/
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|
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/* MISRA-C:2004 no longer included in build
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CMSIS-Core (Cortex-M) violates the following MISRA-C:2004 rules:
|
||||
|
||||
- Required Rule 8.5, object/function definition in header file.<br>
|
||||
Violated since function definitions in header files are used for function inlining'.
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||||
|
||||
- Advisory Rule 12.4, Side effects on right hand side of logical operator.<br>
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||||
Violated because volatile is used for core register definitions.
|
||||
|
||||
- Advisory Rule 14.7, Return statement before end of function.<br>
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||||
Violated to simplify code logic.
|
||||
|
||||
- Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Violated since unions are used for effective representation of core registers.
|
||||
|
||||
- Advisory Rule 19.4, Disallowed definition for macro.<br>
|
||||
Violated since macros are used for assembler keywords.
|
||||
|
||||
- Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Violated since function-like macros are used to generate more efficient code.
|
||||
|
||||
- Advisory Rule 19.16, all preprocessing directives must be valid.<br>
|
||||
Violated to set default settings for macros.
|
||||
*/
|
||||
|
||||
/**
|
||||
CMSIS-Core (Cortex-M) violates the following MISRA-C:2012 rules:
|
||||
|
||||
- Directive 4.9, function-like macro defined.<br>
|
||||
Violated since function-like macros are used to generate more efficient code.
|
||||
|
||||
- Rule 1.3, multiple use of '#/##' operators in macro definition.<br>
|
||||
Violated since function-like macros are used to generate more efficient code.
|
||||
|
||||
- Rule 11.4, conversion between a pointer and integer type.<br>
|
||||
Violated because of core register access.
|
||||
|
||||
- Rule 11.6, cast from unsigned long to pointer.<br>
|
||||
Violated because of core register access.
|
||||
|
||||
- Rule 13.5, side effects on right hand side of logical operator.<br>
|
||||
Violated because of shift operand is used in macros and functions.
|
||||
|
||||
- Rule 14.4, conditional expression should have essentially Boolean type.<br>
|
||||
Violated since macros with several instructions are used.
|
||||
|
||||
- Rule 15.5, return statement before end of function.<br>
|
||||
Violated to simplify code logic.
|
||||
|
||||
- Rule 20.10, '#/##' operators used.<br>
|
||||
Violated since function-like macros are used to generate more efficient code.
|
||||
|
||||
- Rule 21.1, reserved to the compiler.<br>
|
||||
Violated since macros with leading underscores are used.
|
||||
|
||||
|
||||
|
||||
<device>.h files generated by <b>SVDConv.exe</b> violate the following MISRA-C:2004 rules:
|
||||
|
||||
- Advisory Rule 20.2, Re-use of C90 identifier pattern.<br>
|
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Violated since CMSIS macros begin with '__'. Since CMSIS is developed and verified with various compilers this approach is acceptable and avoids conflicts with user symbols.
|
||||
|
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- Advisory Rule 19.1, Declaration before \#include.<br>
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Violated since Interrupt Number Definition Type (IRQn_Type) must be defined before including the core header file.
|
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*/
|
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|
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external/CMSIS_5/CMSIS/DoxyGen/Core/src/Overview.txt
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external/CMSIS_5/CMSIS/DoxyGen/Core/src/Overview.txt
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/** \mainpage Overview
|
||||
|
||||
CMSIS-Core (Cortex-M) implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals.
|
||||
In detail it defines:
|
||||
- <b>Hardware Abstraction Layer (HAL)</b> for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.
|
||||
- <b>System exception names</b> to interface to system exceptions without having compatibility issues.
|
||||
- <b>Methods to organize header files</b> that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
|
||||
- <b>Methods for system initialization</b> to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
|
||||
- <b>Intrinsic functions</b> used to generate CPU instructions that are not supported by standard C functions.
|
||||
- A variable to determine the <b>system clock frequency</b> which simplifies the setup the SysTick timer.
|
||||
|
||||
|
||||
The following sections provide details about the CMSIS-Core (Cortex-M):
|
||||
- \ref using_pg describes the project setup and shows a simple program example.
|
||||
\if ARMv8M
|
||||
- \ref using_TrustZone_pg "Using TrustZone® for Armv8-M" describes how to use the security extensions available in the Armv8-M architecture.
|
||||
\endif
|
||||
- \ref templates_pg describes the files of the CMSIS-Core (Cortex-M) in detail and explains how to adapt template files provided by Arm to silicon vendor devices.
|
||||
- \ref coreMISRA_Exceptions_pg describes the violations to the MISRA standard.
|
||||
- <a href="modules.html">\b Reference </a> describe the features and functions of the \ref device_h_pg in detail.
|
||||
- <a href="annotated.html">\b Data \b Structures </a> describe the data structures of the \ref device_h_pg in detail.
|
||||
|
||||
<hr>
|
||||
|
||||
CMSIS-Core (Cortex-M) in ARM::CMSIS Pack
|
||||
-----------------------------
|
||||
|
||||
Files relevant to CMSIS-Core (Cortex-M) are present in the following <b>ARM::CMSIS</b> directories:
|
||||
|File/Folder |Content |
|
||||
|------------------------------|------------------------------------------------------------------------|
|
||||
|\b CMSIS\\Documentation\\Core | This documentation |
|
||||
|\b CMSIS\\Core\\Include | CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.) |
|
||||
|\b Device | \ref using_ARM_pg "Arm reference implementations" of Cortex-M devices |
|
||||
|\b Device\\\_Template_Vendor | \ref templates_pg for extension by silicon vendors |
|
||||
|
||||
<hr>
|
||||
|
||||
\section ref_v6-v8M Processor Support
|
||||
|
||||
CMSIS supports the complete range of <a href="https://developer.arm.com/products/processors/cortex-m" target="_blank"><b>Cortex-M processors</b></a> and
|
||||
the <a href="https://developer.arm.com/architectures/cpu-architecture/m-profile" target="_blank"><b>Armv8-M/v8.1-M architecture</b></a> including security extensions.
|
||||
|
||||
\subsection ref_man_sec Cortex-M Generic User Guides
|
||||
|
||||
The Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:
|
||||
|
||||
- <a href="https://developer.arm.com/documentation/dui0497/latest/" target="_blank"><b>Cortex-M0 Devices Generic User Guide</b></a> (Armv6-M architecture)
|
||||
- <a href="https://developer.arm.com/documentation/dui0662/latest/" target="_blank"><b>Cortex-M0+ Devices Generic User Guide</b></a> (Armv6-M architecture)
|
||||
- <a href="https://developer.arm.com/documentation/dui0552/latest/" target="_blank"><b>Cortex-M3 Devices Generic User Guide</b></a> (Armv7-M architecture)
|
||||
- <a href="https://developer.arm.com/documentation/dui0553/latest/" target="_blank"><b>Cortex-M4 Devices Generic User Guide</b></a> (Armv7-M architecture)
|
||||
- <a href="https://developer.arm.com/documentation/dui0646/latest/" target="_blank"><b>Cortex-M7 Devices Generic User Guide</b></a> (Armv7-M architecture)
|
||||
- <a href="https://developer.arm.com/documentation/dui1095/latest/" target="_blank"><b>Cortex-M23 Devices Generic User Guide</b></a> (Armv8-M architecture)
|
||||
- <a href="https://developer.arm.com/documentation/100235/latest/" target="_blank"><b>Cortex-M33 Devices Generic User Guide</b></a> (Armv8-M architecture)
|
||||
- <a href="https://developer.arm.com/documentation/101273/latest/" target="_blank"><b>Cortex-M55 Devices Generic User Guide</b></a> (Armv8.1-M architecture)
|
||||
- <a href="https://developer.arm.com/documentation/101928/latest" target="_blank"><b>Cortex-M85 Devices Generic User Guide</b></a> (Armv8.1-M architecture)
|
||||
|
||||
CMSIS also supports the following Cortex-M processor variants:
|
||||
- <a href="https://developer.arm.com/products/processors/cortex-m/cortex-m1" target="_blank"><b>Cortex-M1</b></a> is a processor designed specifically for implementation in FPGAs (Armv6-M architecture).
|
||||
- <a href="https://developer.arm.com/products/processors/cortex-m/sc000-processor" target="_blank"><b>SecurCore SC000</b></a> is designed specifically for smartcard and security applications (Armv6-M architecture).
|
||||
- <a href="https://developer.arm.com/products/processors/cortex-m/sc300-processor" target="_blank"><b>SecurCore SC300</b></a> is designed specifically for smartcard and security applications (Armv7-M architecture).
|
||||
- <a href="https://developer.arm.com/products/processors/cortex-m/cortex-m35p" target="_blank"><b>Cortex-M35P</b></a> is a tamper resistant Cortex-M processor with optional software isolation using TrustZone for Armv8-M.
|
||||
- <a href="https://www.armchina.com/mountain?infoId=160" target="_blank"><b>STAR-MC1</b></a> is a variant of Armv8-M with TrustZone designed by Arm China.
|
||||
|
||||
|
||||
\subsection ARMv8M Armv8-M and Armv8.1-M Architecture
|
||||
|
||||
Armv8-M introduces two profiles \b baseline (for power and area constrained applications) and \b mainline (full-featured with optional SIMD, floating-point, and co-processor extensions).
|
||||
Both Armv8-M profiles and Armv8.1-M are supported by CMSIS.
|
||||
|
||||
The Armv8-M architecture is described in the <a href="https://developer.arm.com/documentation/ddi0553/latest/" target="_blank"><b>Armv8-M Architecture Reference Manual</b></a>.
|
||||
|
||||
The Armv8.1-M architecture further extends Armv8-M with Helium (the so called M-Profile Vector Extension (MVE)), as well as further instruction set and debug extensions.
|
||||
More information about Armv8.1-M architecture is available under <a href="https://developer.arm.com/technologies/helium" target="_blank"><b>Arm Helium technology</b></a>.
|
||||
|
||||
<hr>
|
||||
|
||||
\section tested_tools_sec Tested and Verified Toolchains
|
||||
|
||||
The \ref templates_pg supplied by Arm have been tested and verified with the following toolchains:
|
||||
- Arm: Arm Compiler 5.06 update 7 (not for Cortex-M23/33/35P/55/85, Armv8-M, Armv8.1-M)
|
||||
- Arm: Arm Compiler 6.16
|
||||
- Arm: Arm Compiler 6.6.4 (not for Cortex-M0/23/33/35P/55/85, Armv8-M, Armv8.1-M)
|
||||
- GNU: GNU Arm Embedded Toolchain 10-2020-q4-major (10.2.1 20201103)
|
||||
- IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183
|
||||
*/
|
||||
/*=======0=========1=========2=========3=========4=========5=========6=========7=========8=========9=========0=========1====*/
|
||||
/**
|
||||
|
||||
\page core_revisionHistory Revision History of CMSIS-Core (Cortex-M)
|
||||
|
||||
<table class="cmtable" summary="Revision History">
|
||||
<tr>
|
||||
<th>Version</th>
|
||||
<th>Description</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V5.7.0</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Added: Added new compiler macros __ALIAS and __NO_INIT</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V5.6.0</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Added: Arm Cortex-M85 cpu support</li>
|
||||
<li>Added: Arm China Star-MC1 cpu support</li>
|
||||
<li>Updated: system_ARMCM55.c</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V5.5.0</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Updated GCC LinkerDescription, GCC Assembler startup</li>
|
||||
<li>Added ARMv8-M Stack Sealing (to linker, startup) for toolchain ARM, GCC</li>
|
||||
<li>Changed C-Startup to default Startup.</li>
|
||||
</li>
|
||||
Updated Armv8-M Assembler startup to use GAS syntax<br>
|
||||
Note: Updating existing projects may need manual user interaction!
|
||||
</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V5.4.0</td>
|
||||
<td>
|
||||
<ul>
|
||||
\if ARMv8M
|
||||
<li>Added: Cortex-M55 cpu support</li>
|
||||
<li>Enhanced: MVE support for Armv8.1-MML</li>
|
||||
\endif
|
||||
<li>Fixed: Device config define checks</li>
|
||||
<li>Added: L1 Cache functions for Armv7-M and later</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V5.3.0</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Added: Provisions for compiler-independent C startup code.</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V5.2.1</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Fixed: Compilation issue in cmsis_armclang_ltm.h introduced in 5.2.0</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V5.2.0</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Added: Cortex-M35P support.</li>
|
||||
<li>Added: Cortex-M1 support.
|
||||
<li>Added: Armv8.1 architecture support.
|
||||
<li>Added: \ref __RESTRICT and \ref __STATIC_FORCEINLINE compiler control macros.
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V5.1.2</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Removed using get/set built-ins FPSCR in GCC >= 7.2 due to shortcomings.</li>
|
||||
<li>Added __NO_RETURN to __NVIC_SystemReset() to silence compiler warnings.</li>
|
||||
<li>Added support for Cortex-M1 (beta).</li>
|
||||
<li>Removed usage of register keyword.</li>
|
||||
<li>Added defines for EXC_RETURN, FNC_RETURN and integrity signature values.</li>
|
||||
<li>Enhanced MPUv7 API with defines for memory access attributes.</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V5.1.1</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Aligned MSPLIM and PSPLIM access functions along supported compilers.</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V5.1.0</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Added MPU Functions for ARMv8-M for Cortex-M23/M33.</li>
|
||||
<li>Moved __SSAT and __USAT intrinsics to CMSIS-Core.</li>
|
||||
<li>Aligned __REV, __REV16 and __REVSH intrinsics along supported compilers.</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V5.0.2</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Added macros \ref \__UNALIGNED_UINT16_READ, \ref \__UNALIGNED_UINT16_WRITE.</li>
|
||||
<li>Added macros \ref \__UNALIGNED_UINT32_READ, \ref \__UNALIGNED_UINT32_WRITE.</li>
|
||||
<li>Deprecated macro \ref \__UNALIGNED_UINT32.</li>
|
||||
<li>Changed \ref version_control_gr macros to be core agnostic.</li>
|
||||
<li>Added \ref mpu_functions for Cortex-M0+/M3/M4/M7.</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V5.0.1</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Added: macro \ref \__PACKED_STRUCT.</li>
|
||||
<li>Added: uVisor support.</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V5.00</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Added: Cortex-M23, Cortex-M33 support.</li>
|
||||
<li>Added: macro __SAU_PRESENT with __SAU_REGION_PRESENT.</li>
|
||||
<li>Replaced: macro __SAU_PRESENT with __SAU_REGION_PRESENT.</li>
|
||||
<li>Reworked: SAU register and functions.</li>
|
||||
<li>Added: macro \ref \__ALIGNED.</li>
|
||||
<li>Updated: function \ref SCB_EnableICache.</li>
|
||||
<li>Added: cmsis_compiler.h with compiler specific CMSIS macros, functions, instructions.</li>
|
||||
<li>Added: macro \ref \__PACKED.</li>
|
||||
<li>Updated: compiler specific include files.</li>
|
||||
<li>Updated: core dependant include files.</li>
|
||||
<li>Removed: deprecated files core_cmfunc.h, core_cminstr.h, core_cmsimd.h.</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V5.00<br>Beta 6</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Added: SCB_CFSR register bit definitions.</li>
|
||||
<li>Added: function \ref NVIC_GetEnableIRQ.</li>
|
||||
<li>Updated: core instruction macros \ref \__NOP, \ref \__WFI, \ref \__WFE, \ref \__SEV for toolchain GCC.</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V5.00<br>Beta 5</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Moved: DSP libraries from CMSIS/DSP/Lib to CMSIS/Lib.</li>
|
||||
<li>Added: DSP libraries build projects to CMSIS pack.</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V5.00<br>Beta 4</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Updated: ARMv8M device files.</li>
|
||||
<li>Corrected: ARMv8MBL interrupts.</li>
|
||||
<li>Reworked: NVIC functions.</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V5.00<br>Beta 2</td>
|
||||
<td>
|
||||
<ul>
|
||||
\if ARMv8M
|
||||
<li>Changed: ARMv8M SAU regions to 8.</li>
|
||||
<li>Changed: moved function \ref TZ_SAU_Setup to file partition_<device>.h.</li>
|
||||
\endif
|
||||
<li>Changed: license under Apache-2.0.</li>
|
||||
<li>Added: check if macro is defined before use.</li>
|
||||
<li>Corrected: function \ref SCB_DisableDCache.</li>
|
||||
<li>Corrected: macros \ref \_VAL2FLD, \ref \_FLD2VAL.</li>
|
||||
<li>Added: NVIC function virtualization with macros \ref CMSIS_NVIC_VIRTUAL and \ref CMSIS_VECTAB_VIRTUAL.</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V5.00<br>Beta 1</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Renamed: cmsis_armcc_V6.h to cmsis_armclang.h.</li>
|
||||
<li>Renamed: core\_*.h to lower case.</li>
|
||||
<li>Added: function \ref SCB_GetFPUType to all CMSIS cores.</li>
|
||||
<li>Added: ARMv8-M support.</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V4.30</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Corrected: DoxyGen function parameter comments.</li>
|
||||
<li>Corrected: IAR toolchain: removed for \ref NVIC_SystemReset the attribute(noreturn).</li>
|
||||
<li>Corrected: GCC toolchain: suppressed irrelevant compiler warnings.</li>
|
||||
<li>Added: Support files for Arm Compiler v6 (cmsis_armcc_v6.h).</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V4.20</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Corrected: MISRA-C:2004 violations.</li>
|
||||
<li>Corrected: predefined macro for TI CCS Compiler.</li>
|
||||
<li>Corrected: function \ref __SHADD16 in arm_math.h.</li>
|
||||
<li>Updated: cache functions for Cortex-M7.</li>
|
||||
<li>Added: macros \ref _VAL2FLD, \ref _FLD2VAL to core\_*.h.</li>
|
||||
<li>Updated: functions \ref __QASX, \ref __QSAX, \ref __SHASX, \ref __SHSAX.</li>
|
||||
<li>Corrected: potential bug in function \ref __SHADD16.</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V4.10</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Corrected: MISRA-C:2004 violations.</li>
|
||||
<li>Corrected: intrinsic functions \ref __DSB, \ref __DMB, \ref __ISB.</li>
|
||||
<li>Corrected: register definitions for ITCMCR register.</li>
|
||||
<li>Corrected: register definitions for \ref CONTROL_Type register.</li>
|
||||
<li>Added: functions \ref SCB_GetFPUType, \ref SCB_InvalidateDCache_by_Addr to core_cm7.h.</li>
|
||||
<li>Added: register definitions for \ref APSR_Type, \ref IPSR_Type, \ref xPSR_Type register.</li>
|
||||
<li>Added: \ref __set_BASEPRI_MAX function to core_cmFunc.h.</li>
|
||||
<li>Added: intrinsic functions \ref __RBIT, \ref __CLZ for Cortex-M0/CortexM0+.</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V4.00</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Added: Cortex-M7 support.</li>
|
||||
<li>Added: intrinsic functions for \ref __RRX, \ref __LDRBT, \ref __LDRHT, \ref __LDRT, \ref __STRBT, \ref __STRHT, and \ref __STRT</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V3.40</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Corrected: C++ include guard settings.</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V3.30</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Added: COSMIC tool chain support.</li>
|
||||
<li>Corrected: GCC __SMLALDX instruction intrinsic for Cortex-M4.</li>
|
||||
<li>Corrected: GCC __SMLALD instruction intrinsic for Cortex-M4.</li>
|
||||
<li>Corrected: GCC/CLang warnings.</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V3.20</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Added: \ref __BKPT instruction intrinsic.</li>
|
||||
<li>Added: \ref __SMMLA instruction intrinsic for Cortex-M4.</li>
|
||||
<li>Corrected: \ref ITM_SendChar.</li>
|
||||
<li>Corrected: \ref __enable_irq, \ref __disable_irq and inline assembly for GCC Compiler.</li>
|
||||
<li>Corrected: \ref NVIC_GetPriority and VTOR_TBLOFF for Cortex-M0/M0+, SC000.</li>
|
||||
<li>Corrected: rework of in-line assembly functions to remove potential compiler warnings.</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V3.01</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Added support for Cortex-M0+ processor.</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V3.00</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Added support for GNU GCC ARM Embedded Compiler.</li>
|
||||
<li>Added function \ref __ROR.</li>
|
||||
<li>Added \ref regMap_pg for TPIU, DWT.</li>
|
||||
<li>Added support for \ref core_config_sect "SC000 and SC300 processors".</li>
|
||||
<li>Corrected \ref ITM_SendChar function.</li>
|
||||
<li>Corrected the functions \ref __STREXB, \ref __STREXH, \ref __STREXW for the GNU GCC compiler section.</li>
|
||||
<li>Documentation restructured.</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V2.10</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Updated documentation.</li>
|
||||
<li>Updated CMSIS core include files.</li>
|
||||
<li>Changed CMSIS/Device folder structure.</li>
|
||||
<li>Added support for Cortex-M0, Cortex-M4 w/o FPU to CMSIS DSP library.</li>
|
||||
<li>Reworked CMSIS DSP library examples.</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V2.00</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Added support for Cortex-M4 processor.</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V1.30</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Reworked Startup Concept.</li>
|
||||
<li>Added additional Debug Functionality.</li>
|
||||
<li>Changed folder structure.</li>
|
||||
<li>Added doxygen comments.</li>
|
||||
<li>Added definitions for bit.</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V1.01</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Added support for Cortex-M0 processor.</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V1.01</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Added intrinsic functions for \ref __LDREXB, \ref __LDREXH, \ref __LDREXW, \ref __STREXB, \ref __STREXH, \ref __STREXW, and \ref __CLREX</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>V1.00</td>
|
||||
<td>
|
||||
<ul>
|
||||
<li>Initial Release for Cortex-M3 processor.</li>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
|
||||
*/
|
||||
|
||||
|
||||
546
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_CompilerControl.txt
vendored
Normal file
546
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_CompilerControl.txt
vendored
Normal file
@@ -0,0 +1,546 @@
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\defgroup compiler_conntrol_gr Compiler Control
|
||||
\brief Compiler agnostic \#define symbols for generic C/C++ source code
|
||||
\details
|
||||
The CMSIS-Core provides the header file <b>cmsis_compiler.h</b> with consistent \#define symbols for generate C or C++ source files that should be compiler agnostic.
|
||||
Each CMSIS compliant compiler should support the functionality described in this section.
|
||||
|
||||
The header file <b>cmsis_compiler.h</b> is also included by each \ref device_h_pg so that these definitions are available.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\def __ARM_ARCH_6M__
|
||||
\brief Set to 1 when generating code for Armv6-M (Cortex-M0, Cortex-M1)
|
||||
\details
|
||||
The <b>\#define __ARM_ARCH_6M__</b> is set to 1 when generating code for the Armv6-M architecture. This architecture is for example used by the Cortex-M0, Cortex-M0+, and Cortex-M1 processor.
|
||||
*/
|
||||
#define __ARM_ARCH_6M__
|
||||
|
||||
/**
|
||||
\def __ARM_ARCH_7M__
|
||||
\brief Set to 1 when generating code for Armv7-M (Cortex-M3)
|
||||
\details
|
||||
The <b>\#define __ARM_ARCH_7M__</b> is set to 1 when generating code for the Armv7-M architecture. This architecture is for example used by the Cortex-M3 processor.
|
||||
*/
|
||||
#define __ARM_ARCH_7M__
|
||||
|
||||
/**
|
||||
\def __ARM_ARCH_7EM__
|
||||
\brief Set to 1 when generating code for Armv7-M (Cortex-M4) with FPU
|
||||
\details
|
||||
The <b>\#define __ARM_ARCH_7EM__</b> is set to 1 when generating code for the Armv7-M architecture with floating point extension. This architecture is for example used by the Cortex-M4 processor with FPU
|
||||
*/
|
||||
#define __ARM_ARCH_7EM__
|
||||
|
||||
/**
|
||||
\cond (ARMv8M)
|
||||
*/
|
||||
|
||||
/**
|
||||
\def __ARM_ARCH_8M_BASE__
|
||||
\brief Set to 1 when generating code for Armv8-M Baseline
|
||||
\details
|
||||
The <b>\#define __ARM_ARCH_8M_BASE__</b> is set to 1 when generating code for the Armv8-M architecture baseline variant.
|
||||
*/
|
||||
#define __ARM_ARCH_8M_BASE__
|
||||
|
||||
/**
|
||||
\def __ARM_ARCH_8M_MAIN__
|
||||
\brief Set to 1 when generating code for Armv8-M Mainline
|
||||
\details
|
||||
The <b>\#define __ARM_ARCH_8M_MAIN__</b> is set to 1 when generating code for the Armv8-M architecture mainline variant.
|
||||
*/
|
||||
#define __ARM_ARCH_8M_MAIN__
|
||||
|
||||
/**
|
||||
\endcond
|
||||
*/
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\def __ASM
|
||||
\brief Pass information from the compiler to the assembler.
|
||||
\details
|
||||
The \b __ASM keyword can declare or define an embedded assembly function or incorporate inline assembly into a function
|
||||
(shown in the code example below).
|
||||
|
||||
<b>Code Example:</b>
|
||||
\code
|
||||
// Reverse bit order of value
|
||||
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
\endcode
|
||||
|
||||
*/
|
||||
#define __ASM
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\def __INLINE
|
||||
\brief Recommend that function should be inlined by the compiler.
|
||||
\details
|
||||
Inline functions offer a trade-off between code size and performance. By default, the compiler decides during optimization whether to
|
||||
inline code or not. The \b __INLINE attribute gives the compiler an hint to inline this function. Still, the compiler may decide not to inline
|
||||
the function. As the function is global an callable function is also generated.
|
||||
|
||||
<b>Code Example:</b>
|
||||
\code
|
||||
const uint32_t led_mask[] = {1U << 4, 1U << 5, 1U << 6, 1U << 7};
|
||||
|
||||
/*------------------------------------------------------------------------------
|
||||
Switch on LEDs
|
||||
*------------------------------------------------------------------------------*/
|
||||
__INLINE static void LED_On (uint32_t led) {
|
||||
|
||||
PTD->PCOR = led_mask[led];
|
||||
}
|
||||
\endcode
|
||||
|
||||
*/
|
||||
#define __INLINE
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\def __STATIC_INLINE
|
||||
\brief Define a static function that may be inlined by the compiler.
|
||||
\details
|
||||
Defines a static function that may be inlined by the compiler. If the compiler generates inline code for
|
||||
all calls to this functions, no additional function implementation is generated which may further optimize space.
|
||||
|
||||
<b>Code Example:</b>
|
||||
\code
|
||||
\\ Get Interrupt Vector
|
||||
__STATIC_INLINE uint32_t NVIC_GetVector(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||
}
|
||||
\endcode
|
||||
|
||||
*/
|
||||
#define __STATIC_INLINE
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\def __STATIC_FORCEINLINE
|
||||
\brief Define a static function that should be always inlined by the compiler.
|
||||
\details
|
||||
Defines a static function that should be always inlined by the compiler.
|
||||
|
||||
\note
|
||||
For compilers that do not allow to force function inlining, the macro maps to \ref __STATIC_INLINE.
|
||||
|
||||
<b>Code Example:</b>
|
||||
\code
|
||||
\\ Get Interrupt Vector
|
||||
__STATIC_FORCEINLINE uint32_t NVIC_GetVector(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||
}
|
||||
\endcode
|
||||
|
||||
*/
|
||||
#define __STATIC_FORCEINLINE
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\def __NO_RETURN
|
||||
\brief Inform the compiler that a function does not return.
|
||||
\details
|
||||
Informs the compiler that the function does not return. The compiler can then perform optimizations by
|
||||
removing code that is never reached.
|
||||
|
||||
<b>Code Example:</b>
|
||||
\code
|
||||
// OS idle demon (running when no other thread is ready to run).
|
||||
|
||||
__NO_RETURN void os_idle_demon (void);
|
||||
\endcode
|
||||
|
||||
*/
|
||||
#define __NO_RETURN
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\def __RESTRICT
|
||||
\brief restrict pointer qualifier to enable additional optimizations.
|
||||
\details
|
||||
The __RESTRICT keyword corresponds to the \b restrict pointer qualifier that has been introduced in C99.
|
||||
__RESTRICT is a hint to the compiler that enables additional optimizations. It specifies that for the lifetime
|
||||
of the pointer, only the pointer itself or a value directly derived from it (such as pointer + 1) is used to access
|
||||
the object. The compiler may therefore ignore potential pointer aliasing effects and perform additional optimizations.
|
||||
|
||||
\note
|
||||
For compilers that do not support the restrict keyword, __RESTRICT is defined as an empty macro and a warning is issued.
|
||||
|
||||
<b>Code Example:</b>
|
||||
\code
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy (volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i]; // Since src is restrict, the compiler can assume that dst and src are not overlapping may load multiple values at a time
|
||||
}
|
||||
}
|
||||
\endcode
|
||||
|
||||
*/
|
||||
#define __RESTRICT
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\def __USED
|
||||
\brief Inform that a variable shall be retained in executable image.
|
||||
\details
|
||||
Definitions tagged with \b __USED in the source code should be not removed by the linker when detected as unused.
|
||||
|
||||
<b>Code Example:</b>
|
||||
\code
|
||||
/* Export following variables for debugging */
|
||||
__USED uint32_t const CMSIS_RTOS_API_Version = osCMSIS;
|
||||
__USED uint32_t const CMSIS_RTOS_RTX_Version = osCMSIS_RTX;
|
||||
__USED uint32_t const os_clockrate = OS_TICK;
|
||||
__USED uint32_t const os_timernum = 0;
|
||||
\endcode
|
||||
|
||||
*/
|
||||
#define __USED
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\def __WEAK
|
||||
\brief Export a function or variable weakly to allow overwrites.
|
||||
\details
|
||||
Functions defined with \b __WEAK export their symbols weakly. A weakly defined function behaves like a normally defined
|
||||
function unless a non-weakly defined function of the same name is linked into the same image. If both a non-weakly defined
|
||||
function and a weakly defined function exist in the same image then all calls to the function resolve to call the non-weak
|
||||
function.
|
||||
|
||||
Functions declared with \b __WEAK and then defined without \b __WEAK behave as non-weak functions.
|
||||
|
||||
<b>Code Example:</b>
|
||||
\code
|
||||
__WEAK void SystemInit(void)
|
||||
{
|
||||
SystemCoreSetup();
|
||||
SystemCoreClockSetup();
|
||||
}
|
||||
\endcode
|
||||
|
||||
*/
|
||||
#define __WEAK
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\def __PACKED
|
||||
\brief Request smallest possible alignment.
|
||||
\details
|
||||
Specifies that a type must have the smallest possible alignment.
|
||||
|
||||
<b>Code Example:</b>
|
||||
\code
|
||||
struct foo {
|
||||
uint8_t u8;
|
||||
uint32_t u32[2] __PACKED;
|
||||
};
|
||||
\endcode
|
||||
|
||||
*/
|
||||
#define __PACKED
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\def __PACKED_STRUCT
|
||||
\brief Request smallest possible alignment for a structure.
|
||||
\details
|
||||
Specifies that a structure must have the smallest possible alignment.
|
||||
|
||||
<b>Code Example:</b>
|
||||
\code
|
||||
__PACKED_STRUCT foo {
|
||||
uint8_t u8;
|
||||
uint32_t u32;
|
||||
uint16_t u16;
|
||||
};
|
||||
\endcode
|
||||
|
||||
*/
|
||||
#define __PACKED_STRUCT
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\def __UNALIGNED_UINT32
|
||||
\brief Pointer for unaligned access of a uint32_t variable.
|
||||
\deprecated
|
||||
Do not use this macro.
|
||||
It has been superseded by \ref __UNALIGNED_UINT32_READ, \ref __UNALIGNED_UINT32_WRITE and will be removed in the future.
|
||||
\details
|
||||
Defines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in read/write
|
||||
operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm
|
||||
processor core and compiler settings.
|
||||
|
||||
<b>Code Example:</b>
|
||||
\code
|
||||
uint32_t val32;
|
||||
|
||||
void test (uint8_t *ptr) {
|
||||
__UNALIGNED_UINT32(ptr) = val32;
|
||||
}
|
||||
\endcode
|
||||
|
||||
*/
|
||||
#define __UNALIGNED_UINT32
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\def __UNALIGNED_UINT16_READ
|
||||
\brief Pointer for unaligned read of a uint16_t variable.
|
||||
\details
|
||||
Defines a pointer to a uint16_t from an address that does not need to be aligned. This can then be used in read
|
||||
operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm
|
||||
processor core and compiler settings.
|
||||
|
||||
<b>Code Example:</b>
|
||||
\code
|
||||
uint16_t val16;
|
||||
|
||||
void test (uint8_t *ptr) {
|
||||
val16 = __UNALIGNED_UINT16_READ(ptr);
|
||||
}
|
||||
\endcode
|
||||
|
||||
*/
|
||||
#define __UNALIGNED_UINT16_READ
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\def __UNALIGNED_UINT16_WRITE
|
||||
\brief Pointer for unaligned write of a uint16_t variable.
|
||||
\details
|
||||
Defines a pointer to a uint16_t from an address that does not need to be aligned. This can then be used in write
|
||||
operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm
|
||||
processor core and compiler settings.
|
||||
|
||||
<b>Code Example:</b>
|
||||
\code
|
||||
uint16_t val16 = 0U;
|
||||
|
||||
void test (uint8_t *ptr) {
|
||||
__UNALIGNED_UINT16_WRITE(ptr, val16);
|
||||
}
|
||||
\endcode
|
||||
|
||||
*/
|
||||
#define __UNALIGNED_UINT16_WRITE
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\def __UNALIGNED_UINT32_READ
|
||||
\brief Pointer for unaligned read of a uint32_t variable.
|
||||
\details
|
||||
Defines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in read
|
||||
operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm
|
||||
processor core and compiler settings.
|
||||
|
||||
<b>Code Example:</b>
|
||||
\code
|
||||
uint32_t val32;
|
||||
|
||||
void test (uint8_t *ptr) {
|
||||
val32 = __UNALIGNED_UINT32_READ(ptr);
|
||||
}
|
||||
\endcode
|
||||
|
||||
*/
|
||||
#define __UNALIGNED_UINT32_READ
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\def __UNALIGNED_UINT32_WRITE
|
||||
\brief Pointer for unaligned write of a uint32_t variable.
|
||||
\details
|
||||
Defines a pointer to a uint32_t from an address that does not need to be aligned. This can then be used in write
|
||||
operations. The compiler will generate the appropriate access (aligned or non-aligned) depending on the underlying Arm
|
||||
processor core and compiler settings.
|
||||
|
||||
<b>Code Example:</b>
|
||||
\code
|
||||
uint32_t val32 = 0U;
|
||||
|
||||
void test (uint8_t *ptr) {
|
||||
__UNALIGNED_UINT32_WRITE(ptr, val32);
|
||||
}
|
||||
\endcode
|
||||
|
||||
*/
|
||||
#define __UNALIGNED_UINT32_WRITE
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\def __ALIGNED
|
||||
\brief Minimum alignment for a variable.
|
||||
\details
|
||||
Specifies a minimum alignment for a variable or structure field, measured in bytes.
|
||||
|
||||
<b>Code Example:</b>
|
||||
\code
|
||||
uint32_t stack_space[0x100] __ALIGNED(8); // 8-byte alignment required
|
||||
\endcode
|
||||
|
||||
*/
|
||||
#define __ALIGNED
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\def __COMPILER_BARRIER
|
||||
\brief Barrier to prevent compiler from reordering instructions.
|
||||
\details
|
||||
This barrier limits the compilers reordering optimizations. It prevents the compiler from swapping
|
||||
instructions resulting from code before and after the barrier.
|
||||
|
||||
<b>Code Example:</b>
|
||||
The assignments in the example are independent. Hence the compiler could choose a different order of
|
||||
execution, e.g. for a better pipeline utilization. Using the barrier in between prevents this type
|
||||
of reordering.
|
||||
|
||||
\code
|
||||
void test (uint8_t *ptr) {
|
||||
var1 = 1;
|
||||
__COMPILE_BARRIER();
|
||||
var2 = var3 + 1;
|
||||
}
|
||||
\endcode
|
||||
|
||||
*/
|
||||
#define __COMPILER_BARRIER
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\def __NO_INIT
|
||||
\brief Force symbol into uninitialized memory section
|
||||
\details
|
||||
This puts a symbol (such as a variable) into an uninitialized memory section (e.g, .bss.noinit).
|
||||
|
||||
<b>Code Example:</b>
|
||||
The EventBuffer in the example does not need to be copy- or zero-initialized. By adding
|
||||
__NO_INIT this variable is allocated into an uninitialized memory section.
|
||||
|
||||
\code
|
||||
static EventRecord_t EventBuffer[EVENT_RECORD_COUNT] __NO_INIT __ALIGNED(16);
|
||||
\endcode
|
||||
|
||||
*/
|
||||
#define __NO_INIT
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\def __ALIAS
|
||||
\brief Creates a symbol as alias to another symbol.
|
||||
|
||||
<b>Code Example:</b>
|
||||
The example declares the function Interrupt0_Handler. By default it is just an alias
|
||||
pointing to Default_Handler. In combination with __WEAK modifier this allows giving
|
||||
the function definition at a later point if required.
|
||||
|
||||
\code
|
||||
void Interrupt0_Handler (void) __WEAK __ALIAS("Default_Handler");
|
||||
\endcode
|
||||
|
||||
*/
|
||||
#define __ALIAS
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\def __PROGRAM_START
|
||||
\brief Entry function into the user application or library startup.
|
||||
\details
|
||||
Gives the function to be jumped into right after low level initialization, i.e. SystemInit. This
|
||||
is compiler and library specific. CMSIS specifies common default for supported compilers.
|
||||
|
||||
\note This define is only intended to be used by the \ref startup_c_pg.
|
||||
|
||||
<b>Code Example:</b>
|
||||
\code
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
SystemInit(); /* CMSIS System Initialization */
|
||||
__PROGRAM_START(); /* Enter PreMain (C library entry point) */
|
||||
}
|
||||
\endcode
|
||||
*/
|
||||
#define __PROGRAM_START
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\def __INITIAL_SP
|
||||
\brief Compiler/linker symbol specifying the location of the main stack (MSP).
|
||||
\details
|
||||
The address of the specified symbol is used to initialize the main stack pointer (MSP) during low
|
||||
level init. This is compiler/linker specific. CMSIS specifies common default for supported compilers.
|
||||
|
||||
\note This define is only intended to be used by the \ref startup_c_pg.
|
||||
*/
|
||||
#define __INITIAL_SP
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\def __STACK_LIMIT
|
||||
\brief Compiler/linker symbol specifying the limit of the main stack (MSP).
|
||||
\details
|
||||
The address of the specified symbol is used to initialize the main stack pointer limit (MSPLIM on Armv8-M)
|
||||
during low level init. This is compiler/linker specific. CMSIS specifies common default for supported
|
||||
compilers.
|
||||
|
||||
\note This define is only intended to be used by the \ref startup_c_pg.
|
||||
|
||||
<b>Code Example:</b>
|
||||
\code
|
||||
void Reset_Handler(void)
|
||||
{
|
||||
__set_MSPLIM((uint32_t)(&__STACK_LIMIT));
|
||||
// :
|
||||
// :
|
||||
}
|
||||
\endcode
|
||||
*/
|
||||
#define __STACK_LIMIT
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\def __VECTOR_TABLE
|
||||
\brief Symbol name used for the (static) interrupt vector table.
|
||||
\details
|
||||
The given name is used for defining the static (compiler time) interrupt vector table. The name
|
||||
must comply with any compiler/linker conventions, e.g. if used for vector table relocation or debugger
|
||||
awareness. CMSIS specifies common default for supported compilers.
|
||||
|
||||
\note This define is only intended to be used by the \ref startup_c_pg.
|
||||
*/
|
||||
#define __VECTOR_TABLE
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\def __VECTOR_TABLE_ATTRIBUTE
|
||||
\brief Additional decl specs to be used when defining the (static) interrupt vector table.
|
||||
\details
|
||||
The given decl specs are used for defining the static (compiler time) interrupt vector table, e.g.
|
||||
to mark the table as used and force it into a specific linker section. CMSIS specifies common default
|
||||
for supported compilers.
|
||||
|
||||
\note This define is only intended to be used by the \ref startup_c_pg.
|
||||
*/
|
||||
#define __VECTOR_TABLE_ATTRIBUTE
|
||||
|
||||
/** @} */ /** end of compiler_conntrol_gr **/
|
||||
741
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_CoreReg.txt
vendored
Normal file
741
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_CoreReg.txt
vendored
Normal file
@@ -0,0 +1,741 @@
|
||||
/**************************************************************************************************/
|
||||
/** \defgroup Core_Register_gr Core Register Access
|
||||
\brief Functions to access the Cortex-M core registers.
|
||||
\details
|
||||
The following functions provide access to Cortex-M core registers.
|
||||
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Read the CONTROL register
|
||||
\details
|
||||
The function reads the CONTROL register value using the instruction \b MRS.
|
||||
\n\n
|
||||
The CONTROL register controls the stack used and the privilege level for software execution
|
||||
when the processor is in thread mode and, if implemented, indicates whether the FPU state is
|
||||
active. This register uses the following bits:
|
||||
\n
|
||||
- \b CONTROL[2] [only Cortex-M4 and Cortex-M7]
|
||||
- =0 FPU not active
|
||||
- =1 FPU active
|
||||
\n\n
|
||||
- \b CONTROL[1]
|
||||
- =0 In handler mode - MSP is selected. No alternate stack possible for handler mode.
|
||||
- =0 In thread mode - Default stack pointer MSP is used.
|
||||
- =1 In thread mode - Alternate stack pointer PSP is used.
|
||||
\n\n
|
||||
- \b CONTROL[0] [not Cortex-M0]
|
||||
- =0 In thread mode and privileged state.
|
||||
- =1 In thread mode and user state.
|
||||
|
||||
\returns CONTROL register value
|
||||
|
||||
\remarks
|
||||
- The processor can be in user state or privileged state when running in thread mode.
|
||||
- Exception handlers always run in privileged state.
|
||||
- On reset, the processor is in thread mode with privileged access rights.
|
||||
|
||||
\sa
|
||||
- \ref __set_CONTROL; CONTROL_Type
|
||||
- \ref ref_man_sec
|
||||
*/
|
||||
uint32_t __get_CONTROL(void);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Set the CONTROL Register
|
||||
\details
|
||||
The function sets the CONTROL register value using the instruction \b MSR.
|
||||
\n\n
|
||||
The CONTROL register controls the stack used and the privilege level for software execution
|
||||
when the processor is in thread mode and, if implemented, indicates whether the FPU state is
|
||||
active. This register uses the following bits:
|
||||
\n
|
||||
- \b CONTROL[2] [only Cortex-M4 and Cortex-M7]
|
||||
- =0 FPU not active
|
||||
- =1 FPU active
|
||||
\n\n
|
||||
- \b CONTROL[1]
|
||||
- Writeable only when the processor is in thread mode and privileged state (CONTROL[0]=0).
|
||||
- =0 In handler mode - MSP is selected. No alternate stack pointer possible for handler mode.
|
||||
- =0 In thread mode - Default stack pointer MSP is used.
|
||||
- =1 In thread mode - Alternate stack pointer PSP is used.
|
||||
\n\n
|
||||
- \b CONTROL[0] [not writeable for Cortex-M0]
|
||||
- Writeable only when the processor is in privileged state.
|
||||
- Can be used to switch the processor to user state (thread mode).
|
||||
- Once in user state, trigger an interrupt and change the state to privileged in the
|
||||
exception handler (the only way).
|
||||
- =0 In thread mode and privileged state.
|
||||
- =1 In thread mode and user state.
|
||||
|
||||
|
||||
\param [in] control CONTROL register value to set
|
||||
|
||||
\remarks
|
||||
- The processor can be in user state or privileged state when running in thread mode.
|
||||
- Exception handlers always run in privileged state.
|
||||
- On reset, the processor is in thread mode with privileged access rights.
|
||||
|
||||
\sa
|
||||
- \ref __get_CONTROL; __set_PSP; __set_MSP; CONTROL_Type
|
||||
- \ref ref_man_sec
|
||||
*/
|
||||
void __set_CONTROL(uint32_t control);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Read the IPSR register
|
||||
\details
|
||||
The function reads the Interrupt Program Status Register (IPSR) using the instruction \b MRS.
|
||||
\n\n
|
||||
The ISPR contains the exception type number of the current Interrupt Service Routine (ISR).
|
||||
Each exception has an associated unique IRQn number. The following bits are used:
|
||||
|
||||
- \b ISR_NUMBER (IPSR[8:0])
|
||||
- = 0 Thread mode
|
||||
- = 1 Reserved
|
||||
- = 2 NMI
|
||||
- = 3 HardFault
|
||||
- = 4 MemManage
|
||||
- = 5 BusFault
|
||||
- = 6 UsageFault
|
||||
- = 7 SecureFault
|
||||
- = 8-10 Reserved
|
||||
- = 11 SVC
|
||||
- = 12 Reserved for Debug
|
||||
- = 13 Reserved
|
||||
- = 14 PendSV
|
||||
- = 15 SysTick
|
||||
- = 16 IRQ0
|
||||
- ...
|
||||
- = n+15 IRQ(n-1)
|
||||
|
||||
\returns ISPR register value
|
||||
|
||||
\remarks
|
||||
- This register is read-only.
|
||||
|
||||
\sa
|
||||
- \ref __get_xPSR; IPSR_Type
|
||||
- \ref NVIC_gr
|
||||
- \ref ref_man_sec
|
||||
*/
|
||||
uint32_t __get_IPSR(void);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Read the APSR register
|
||||
\details
|
||||
The function reads the Application Program Status Register (APSR) using the instruction \b MRS.
|
||||
\n\n
|
||||
The APSR contains the current state of the condition flags from instructions executed previously.
|
||||
The APSR is essential for controlling conditional branches. The following flags are used:
|
||||
|
||||
- \b N (APSR[31]) (Negative flag)
|
||||
- =1 The instruction result has a negative value (when interpreted as signed integer).
|
||||
- =0 The instruction result has a positive value or equal zero.
|
||||
\n\n
|
||||
- \b Z (APSR[30]) (Zero flag)
|
||||
- =1 The instruction result is zero. Or, after a compare instruction, when the two values
|
||||
are the same.
|
||||
\n\n
|
||||
- \b C (APSR[29]) (Carry or borrow flag)
|
||||
- =1 For unsigned additions, if an unsigned overflow occurred.
|
||||
- =<i>inverse of borrow output status</i> For unsigned subtract operations.
|
||||
\n\n
|
||||
- \b V (APSR[28]) (Overflow flag)
|
||||
- =1 A signed overflow occurred (for signed additions or subtractions).
|
||||
\n\n
|
||||
- \b Q (APSR[27]) (DSP overflow or saturation flag) [not Cortex-M0]
|
||||
- This flag is a \em sticky flag. Saturating and certain multiplying instructions can set the
|
||||
flag, but cannot clear it.
|
||||
- =1 When saturation or an overflow occurred.
|
||||
\n\n
|
||||
- \b GE (APSR[19:16]) (Greater than or Equal flags) [not Cortex-M0]
|
||||
- Can be set by the parallel add and subtract instructions.
|
||||
- Are used by the <kbd>SEL</kbd> instruction to perform byte-based selection from two registers.
|
||||
|
||||
|
||||
\returns APSR register value
|
||||
|
||||
\remarks
|
||||
- Some instructions update all flags; some instructions update a subset of the flags.
|
||||
- If a flag is not updated, the original value is preserved.
|
||||
- Conditional instructions that are not executed have no effect on the flags.
|
||||
- The CMSIS does not provide a function to update this register.
|
||||
|
||||
\sa
|
||||
- \ref __get_xPSR; APSR_Type
|
||||
- \ref ref_man_sec
|
||||
|
||||
*/
|
||||
uint32_t __get_APSR(void);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Read the xPSR register
|
||||
\details
|
||||
The function reads the combined Program Status Register (xPSR) using the instruction \b MRS.
|
||||
\n\n
|
||||
xPSR provides information about program execution and the APSR flags. It consists of the
|
||||
following PSRs:
|
||||
\li Application Program Status Register (APSR)
|
||||
\li Interrupt Program Status Register (IPSR)
|
||||
\li Execution Program Status Register (EPSR)
|
||||
|
||||
In addition to the flags described in \ref __get_APSR and \ref __get_IPSR, the register provides
|
||||
the following flags:
|
||||
- \b IT (xPSR[26:25]) (If-Then condition instruction)
|
||||
- Contains up to four instructions following an IT instruction.
|
||||
- Each instruction in the block is conditional.
|
||||
- The conditions for the instructions are either all the same, or some can be the inverse
|
||||
of others.
|
||||
\n\n
|
||||
- \b T (xPSR[24]) (Thumb bit)
|
||||
- =1 Indicates that that the processor is in Thumb state.
|
||||
- =0 Attempting to execute instructions when the T bit is 0 results in a fault or lockup.
|
||||
- The conditions for the instructions are either all the same, or some can be the inverse
|
||||
of others.
|
||||
|
||||
\returns xPSR register value
|
||||
|
||||
\remarks
|
||||
- The CMSIS does not provide functions that access EPSR.
|
||||
|
||||
\sa
|
||||
- \ref __get_APSR; __get_IPSR; xPSR_Type
|
||||
- \ref ref_man_sec
|
||||
|
||||
*/
|
||||
uint32_t __get_xPSR(void);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Read the PSP register
|
||||
\details
|
||||
The function reads the Process Stack Pointer (PSP) value using the instruction \b MRS.
|
||||
\n\n
|
||||
Physically two different stack pointers (SP) exist:
|
||||
- The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when
|
||||
running exception handlers (handler mode).
|
||||
- The Process Stack Pointer (PSP), which can be used only in thread mode.
|
||||
|
||||
Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:
|
||||
- =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded
|
||||
from the first 32-bit word of the vector table from the program memory.
|
||||
- =1 PSP is the current stack pointer. The initial value is undefined.
|
||||
|
||||
\returns PSP register value
|
||||
|
||||
\remarks
|
||||
- Only one of the two SPs is visible at a time.
|
||||
- For many applications, the system can completely rely on the MSP.
|
||||
- The PSP is normally used in designs with an OS where the stack memory for OS Kernel must
|
||||
be separated from the application code.
|
||||
|
||||
\sa
|
||||
- \ref __set_PSP; __get_MSP; __get_CONTROL
|
||||
- \ref ref_man_sec
|
||||
|
||||
|
||||
*/
|
||||
uint32_t __get_PSP(void);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Set the PSP register
|
||||
\details
|
||||
The function sets the Process Stack Pointer (PSP) value using the instruction \b MSR.
|
||||
\n\n
|
||||
Physically two different stack pointers (SP) exist:
|
||||
- The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when
|
||||
running exception handlers (handler mode).
|
||||
- The Process Stack Pointer (PSP), which can be used only in thread mode.
|
||||
|
||||
Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:
|
||||
- =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded
|
||||
from the first 32-bit word of the vector table from the program memory.
|
||||
- =1 PSP is the current stack pointer. The initial value is undefined.
|
||||
|
||||
\param [in] topOfProcStack PSP value to set
|
||||
|
||||
\remarks
|
||||
- Only one of the two SPs is visible at a time.
|
||||
- For many applications, the system can completely rely on the MSP.
|
||||
- The PSP is normally used in designs with an OS where the stack memory for OS Kernel must
|
||||
be separated from the application code.
|
||||
|
||||
\sa
|
||||
- \ref __get_PSP; __set_MSP; __set_CONTROL
|
||||
- \ref ref_man_sec
|
||||
*/
|
||||
void __set_PSP(uint32_t topOfProcStack);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Read the MSP register
|
||||
\details
|
||||
The function reads the Main Stack Pointer (MSP) value using the instruction \b MRS.
|
||||
\n\n
|
||||
Physically two different stack pointers (SP) exist:
|
||||
- The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when
|
||||
running exception handlers (handler mode).
|
||||
- The Process Stack Pointer (PSP), which can be used only in thread mode.
|
||||
|
||||
Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:
|
||||
- =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded
|
||||
from the first 32-bit word of the vector table from the program memory.
|
||||
- =1 PSP is the current stack pointer. The initial value is undefined.
|
||||
|
||||
\returns MSP Register value
|
||||
|
||||
\remarks
|
||||
- Only one of the two SPs is visible at a time.
|
||||
- For many applications, the system can completely rely on the MSP.
|
||||
- The PSP is normally used in designs with an OS where the stack memory for OS Kernel must
|
||||
be separated from the application code.
|
||||
|
||||
\sa
|
||||
- \ref __set_MSP; __get_PSP; __get_CONTROL
|
||||
- \ref ref_man_sec
|
||||
|
||||
*/
|
||||
uint32_t __get_MSP(void);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Set the MSP register
|
||||
\details
|
||||
The function sets the Main Stack Pointer (MSP) value using the instruction \b MSR.
|
||||
\n\n
|
||||
Physically two different stack pointers (SP) exist:
|
||||
- The Main Stack Pointer (MSP) is the default stack pointer after reset. It is also used when
|
||||
running exception handlers (handler mode).
|
||||
- The Process Stack Pointer (PSP), which can be used only in thread mode.
|
||||
|
||||
Register R13 banks the SP. The SP selection is determined by the bit[1] of the CONTROL register:
|
||||
- =0 MSP is the current stack pointer. This is also the default SP. The initial value is loaded
|
||||
from the first 32-bit word of the vector table from the program memory.
|
||||
- =1 PSP is the current stack pointer. The initial value is undefined.
|
||||
|
||||
\param [in] topOfMainStack MSP value to set
|
||||
|
||||
\remarks
|
||||
- Only one of the two SPs is visible at a time.
|
||||
- For many applications, the system can completely rely on the MSP.
|
||||
- The PSP is normally used in designs with an OS where the stack memory for OS Kernel must
|
||||
be separated from the application code.
|
||||
|
||||
\sa
|
||||
- \ref __get_MSP; __set_PSP; __set_CONTROL
|
||||
- \ref ref_man_sec
|
||||
|
||||
*/
|
||||
void __set_MSP(uint32_t topOfMainStack);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Read the PRIMASK register bit
|
||||
\details
|
||||
The function reads the Priority Mask register (PRIMASK) value using the instruction \b MRS.
|
||||
\n\n
|
||||
PRIMASK is a 1-bit-wide interrupt mask register. When set,
|
||||
it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception.
|
||||
The PRIMASK prevents activation of all exceptions with configurable priority.
|
||||
|
||||
\returns PRIMASK register value
|
||||
- =0 no effect
|
||||
- =1 prevents the activation of all exceptions with configurable priority
|
||||
|
||||
\sa
|
||||
- \ref __set_PRIMASK; __get_BASEPRI; __get_FAULTMASK
|
||||
- \ref ref_man_sec
|
||||
|
||||
*/
|
||||
uint32_t __get_PRIMASK(void);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Set the Priority Mask bit
|
||||
\details
|
||||
The function sets the Priority Mask register (PRIMASK) value using the instruction \b MSR.
|
||||
\n\n
|
||||
PRIMASK is a 1-bit-wide interrupt mask register. When set,
|
||||
it blocks all interrupts apart from the non-maskable interrupt (NMI) and the hard fault exception.
|
||||
The PRIMASK prevents activation of all exceptions with configurable priority.
|
||||
|
||||
\param [in] priMask Priority Mask
|
||||
- =0 no effect
|
||||
- =1 prevents the activation of all exceptions with configurable priority
|
||||
|
||||
\remarks
|
||||
- When set, PRIMASK effectively changes the current priority level to 0.
|
||||
This is the highest programmable level.
|
||||
- When set and a fault occurs, the hard fault handler will be executed.
|
||||
- Useful for temporarily disabling all interrupts for timing critical tasks.
|
||||
- Does not have the ability to mask BusFault or bypass MPU.
|
||||
|
||||
\sa
|
||||
- \ref __get_PRIMASK; __set_BASEPRI; __set_FAULTMASK
|
||||
- \ref ref_man_sec
|
||||
|
||||
*/
|
||||
void __set_PRIMASK(uint32_t priMask);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Read the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]
|
||||
\details
|
||||
The function returns the Base Priority Mask register (BASEPRI) using the instruction \b MRS.
|
||||
\n\n
|
||||
BASEPRI defines the minimum priority for exception processing. When BASEPRI is set to a non-zero
|
||||
value, it prevents the activation of all exceptions with the same or lower priority level as
|
||||
the BASEPRI value.
|
||||
|
||||
\returns BASEPRI register value
|
||||
|
||||
\remarks
|
||||
- Not for Cortex-M0, Cortex-M0+, or SC000.
|
||||
|
||||
\sa
|
||||
- \ref __set_BASEPRI; __set_BASEPRI_MAX; __get_FAULTMASK; __get_PRIMASK
|
||||
- \ref ref_man_sec
|
||||
|
||||
*/
|
||||
uint32_t __get_BASEPRI(void);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Set the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]
|
||||
\details
|
||||
The function sets the Base Priority Mask register (BASEPRI) value using the instruction \b MSR.
|
||||
\n\n
|
||||
BASEPRI defines the minimum priority for exception processing.
|
||||
When BASEPRI is set to a non-zero value, it prevents the activation of all exceptions with the
|
||||
same or lower priority level as the BASEPRI value.
|
||||
|
||||
\param [in] basePri BASEPRI value to set
|
||||
|
||||
\remarks
|
||||
- Not for Cortex-M0, Cortex-M0+, or SC000.
|
||||
- Cannot be set in user state.
|
||||
- Useful for changing the masking level or disabling the masking.
|
||||
|
||||
\sa
|
||||
- \ref __get_BASEPRI; __set_BASEPRI_MAX; __set_FAULTMASK; __set_PRIMASK
|
||||
- \ref ref_man_sec
|
||||
|
||||
*/
|
||||
void __set_BASEPRI(uint32_t basePri);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Increase the BASEPRI register [not for Cortex-M0, Cortex-M0+, or SC000]
|
||||
\details
|
||||
The function only increases the Base Priority Mask register (BASEPRI) value using the instruction \b MSR.
|
||||
The value is set only if BASEPRI masking is disabled, or the new value increases the BASEPRI priority level.
|
||||
\n\n
|
||||
BASEPRI defines the minimum priority for exception processing.
|
||||
|
||||
\param [in] basePri BASEPRI value to set
|
||||
|
||||
\remarks
|
||||
- Not for Cortex-M0, Cortex-M0+, or SC000.
|
||||
- Cannot be set in user state.
|
||||
- Useful for increasing the masking level.
|
||||
- Has no effect when \em basePri is lower than the current value of BASEPRI.
|
||||
- Use \ref __set_BASEPRI to lower the Base Priority Mask register.
|
||||
|
||||
\sa
|
||||
- \ref __set_BASEPRI; __get_BASEPRI; __set_FAULTMASK; __set_PRIMASK
|
||||
- \ref ref_man_sec
|
||||
|
||||
*/
|
||||
void __set_BASEPRI_MAX(uint32_t basePri);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Read the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000]
|
||||
\details
|
||||
The function reads the Fault Mask register (FAULTMASK) value using the instruction \b MRS.
|
||||
\n\n
|
||||
FAULTMASK prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI).
|
||||
|
||||
\returns FAULTMASK register value
|
||||
|
||||
\remarks
|
||||
- not for Cortex-M0, Cortex-M0+, or SC000.
|
||||
- Is cleared automatically upon exiting the exception handler, except when returning
|
||||
from the NMI handler.
|
||||
|
||||
\sa
|
||||
- \ref __set_FAULTMASK; __get_BASEPRI; __get_PRIMASK
|
||||
- \ref ref_man_sec
|
||||
*/
|
||||
uint32_t __get_FAULTMASK(void);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Set the FAULTMASK register [not for Cortex-M0, Cortex-M0+, or SC000]
|
||||
\details
|
||||
The function sets the Fault Mask register (FAULTMASK) value using the instruction \b MSR.
|
||||
\n\n
|
||||
FAULTMASK prevents activation of all exceptions except for Non-Maskable Interrupt (NMI).
|
||||
FAULTMASK can be used to escalate a configurable fault handler (BusFault, usage fault, or
|
||||
memory management fault) to hard fault level without invoking a hard fault. This allows the
|
||||
fault handler to pretend to be the hard fault handler, with the ability to:
|
||||
-# <b>Mask BusFault</b> by setting the BFHFNMIGN in the Configuration Control register.
|
||||
It can be used to test the bus system without causing a lockup.
|
||||
-# <b>Bypass the MPU</b>, allowing accessing the MPU protected memory location without
|
||||
reprogramming the MPU to just carry out a few transfers for fixing faults.
|
||||
|
||||
\param [in] faultMask FAULTMASK register value to set
|
||||
|
||||
\remarks
|
||||
- not for Cortex-M0, Cortex-M0+, or SC000.
|
||||
- Is cleared automatically upon exiting the exception handler, except when returning
|
||||
from the NMI handler.
|
||||
- When set, it changes the effective current priority level to -1, so that even the hard
|
||||
fault handler is blocked.
|
||||
- Can be used by fault handlers to change their priority to -1 to have access to some
|
||||
features for hard fault exceptions (see above).
|
||||
- When set, lockups can still be caused by incorrect or undefined instructions, or by using
|
||||
SVC in the wrong priority level.
|
||||
|
||||
\sa
|
||||
- \ref __get_FAULTMASK; __set_BASEPRI; __set_PRIMASK
|
||||
- \ref ref_man_sec
|
||||
*/
|
||||
void __set_FAULTMASK(uint32_t faultMask);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Read the FPSCR register [only Cortex-M4 and Cortex-M7]
|
||||
\details
|
||||
The function reads the Floating-Point Status Control Register (FPSCR) value.
|
||||
\n\n
|
||||
FPSCR provides all necessary User level controls of the floating-point system.
|
||||
|
||||
\returns
|
||||
- FPSCR register value, when __FPU_PRESENT=1
|
||||
- =0, when __FPU_PRESENT=0
|
||||
|
||||
\remarks
|
||||
- Only for Cortex-M4 and Cortex-M7.
|
||||
|
||||
\sa
|
||||
- \ref __set_FPSCR
|
||||
- \ref ref_man_sec
|
||||
|
||||
*/
|
||||
uint32_t __get_FPSCR(void);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Set the FPSC register [only for Cortex-M4 and Cortex-M7]
|
||||
\details
|
||||
The function sets the Floating-Point Status Control Register (FPSCR) value.
|
||||
\n\n
|
||||
FPSCR provides all necessary User level control of the floating-point system.
|
||||
\n
|
||||
- \b N (FPSC[31]) (Negative flag)
|
||||
- =1 The instruction result has a negative value (when interpreted as signed integer).
|
||||
- =0 The instruction result has a positive value or equal zero.
|
||||
\n\n
|
||||
- \b Z (FPSC[30]) (Zero flag)
|
||||
- =1 The instruction result is zero. Or, after a compare instruction, when the two values
|
||||
are the same.
|
||||
\n\n
|
||||
- \b C (FPSC[29]) (Carry or borrow flag)
|
||||
- =1 For unsigned additions, if an unsigned overflow occurred.
|
||||
- =<i>inverse of borrow output status</i> For unsigned subtract operations.
|
||||
\n\n
|
||||
- \b V (FPSC[28]) (Overflow flag)
|
||||
- =1 A signed overflow occurred (for signed additions or subtractions).
|
||||
\n\n
|
||||
- \b AHP (FPSC[26]) (Alternative half-precision flag)
|
||||
- =1 Alternative half-precision format selected.
|
||||
- =0 IEEE half-precision format selected.
|
||||
\n\n
|
||||
- \b DN (FPSC[25]) (Default NaN mode control flag)
|
||||
- =1 Any operation involving one or more NaNs returns the Default NaN.
|
||||
- =0 NaN operands propagate through to the output of a floating-point operation.
|
||||
\n\n
|
||||
- \b FZ (FPSC[24]) (Flush-to-zero mode control flag)
|
||||
- =1 Flush-to-zero mode enabled.
|
||||
- =0 Flush-to-zero mode disabled. Behavior of the floating-point system is fully
|
||||
compliant with the IEEE 754 standard.
|
||||
\n\n
|
||||
- \b RMode (FPSC[23:22]) (Rounding Mode control flags)
|
||||
- =0b00 Round to Nearest (RN) mode.
|
||||
- =0b01 Round towards Plus Infinity (RP) mode.
|
||||
- =0b10 Round towards Minus Infinity (RM) mode.
|
||||
- =0b11 Round towards Zero (RZ) mode.
|
||||
- The specified rounding mode is used by almost all floating-point instructions.
|
||||
\n\n
|
||||
- \b IDC (FPSC[7]) (Input Denormal cumulative exception flags)
|
||||
- See Cumulative exception bits (FPSC[4:0]).
|
||||
\n\n
|
||||
- \b IXC (FPSC[4]) (Inexact cumulative exception flag)
|
||||
- =1 Exception occurred.
|
||||
- =0 Value has to be set explicitly.
|
||||
- Flag is not cleared automatically.
|
||||
\n\n
|
||||
- \b UFC (FPSC[3]) (Underflow cumulative exception flag)
|
||||
- =1 Exception occurred.
|
||||
- =0 Value has to be set explicitly.
|
||||
- Flag is not cleared automatically.
|
||||
\n\n
|
||||
- \b OFC (FPSC[2]) (Overflow cumulative exception flag)
|
||||
- =1 Exception occurred.
|
||||
- =0 Value has to be set explicitly.
|
||||
- Flag is not cleared automatically.
|
||||
\n\n
|
||||
- \b DZC (FPSC[1]) (Division by Zero cumulative exception flag)
|
||||
- =1 Exception occurred.
|
||||
- =0 Value has to be set explicitly.
|
||||
- Flag is not cleared automatically.
|
||||
\n\n
|
||||
- \b IOC (FPSC[0]) (Invalid Operation cumulative exception flag)
|
||||
- =1 Exception occurred.
|
||||
- =0 Value has to be set explicitly.
|
||||
- Flag is not cleared automatically.
|
||||
|
||||
\param [in] fpscr FPSCR value to set
|
||||
|
||||
\remarks
|
||||
- Only for Cortex-M4 and Cortex-M7.
|
||||
- The variable \b __FPU_PRESENT has to be set to 1.
|
||||
|
||||
\sa
|
||||
- \ref __get_FPSCR
|
||||
- \ref ref_man_sec
|
||||
*/
|
||||
void __set_FPSCR(uint32_t fpscr);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Globally enables interrupts and configurable fault handlers
|
||||
\details
|
||||
The function enables interrupts and all configurable fault handlers by clearing PRIMASK.
|
||||
The function uses the instruction <b>CPSIE i</b>.
|
||||
|
||||
\remarks
|
||||
- Can be executed in privileged mode only.
|
||||
|
||||
\sa
|
||||
- \ref __disable_irq; __set_BASEPRI; __set_CONTROL; __set_PRIMASK
|
||||
*/
|
||||
void __enable_irq(void);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Globally disables interrupts and configurable fault handlers
|
||||
\details
|
||||
The function disables interrupts and all configurable fault handlers by setting PRIMASK.
|
||||
The function uses the instruction <b>CPSID i</b>.
|
||||
|
||||
\remarks
|
||||
- Can be executed in privileged mode only.
|
||||
- An interrupt can enter pending state even if it is disabled. Disabling an interrupt
|
||||
only prevents the processor from taking that interrupt.
|
||||
|
||||
\sa
|
||||
- \ref __enable_irq; __set_BASEPRI; __set_CONTROL; __set_PRIMASK
|
||||
*/
|
||||
void __disable_irq(void);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Enables interrupts and all fault handlers [not for Cortex-M0, Cortex-M0+, or SC000]
|
||||
\details
|
||||
The function enables interrupts and all fault handlers by clearing FAULTMASK.
|
||||
The function uses the instruction <b>CPSIE f</b>.
|
||||
|
||||
\remarks
|
||||
- not for Cortex-M0, Cortex-M0+, or SC000.
|
||||
- Can be executed in privileged mode only.
|
||||
|
||||
\sa
|
||||
- \ref __disable_fault_irq; __set_BASEPRI; __set_CONTROL; __set_FAULTMASK
|
||||
*/
|
||||
void __enable_fault_irq(void);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Disables interrupts and all fault handlers [not for Cortex-M0, Cortex-M0+, or SC000]
|
||||
\details
|
||||
The function disables interrupts and all fault handlers by setting FAULTMASK.
|
||||
The function uses the instruction <b>CPSID f</b>.
|
||||
|
||||
\remarks
|
||||
- not for Cortex-M0, Cortex-M0+, or SC000.
|
||||
- Can be executed in privileged mode only.
|
||||
- An interrupt can enter pending state even if it is disabled. Disabling an interrupt
|
||||
only prevents the processor from taking that interrupt.
|
||||
|
||||
\sa
|
||||
- \ref __enable_fault_irq; __set_BASEPRI; __set_CONTROL; __set_FAULTMASK
|
||||
*/
|
||||
void __disable_fault_irq(void);
|
||||
|
||||
/**
|
||||
\cond (ARMv8M)
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Get Process Stack Pointer Limit
|
||||
Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||||
Stack Pointer Limit register hence zero is returned always in non-secure
|
||||
mode.
|
||||
|
||||
\details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
|
||||
\return PSPLIM Register value
|
||||
\note Only available for Armv8-M Architecture.
|
||||
*/
|
||||
uint32_t __get_PSPLIM(void);
|
||||
|
||||
/**
|
||||
\brief Set Process Stack Pointer Limit
|
||||
Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||||
Stack Pointer Limit register hence the write is silently ignored in non-secure
|
||||
mode.
|
||||
|
||||
\details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
|
||||
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
|
||||
\note Only available for Armv8-M Architecture.
|
||||
*/
|
||||
void __set_PSPLIM(uint32_t ProcStackPtrLimit);
|
||||
|
||||
/**
|
||||
\brief Get Main Stack Pointer Limit
|
||||
Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||||
Stack Pointer Limit register hence zero is returned always in non-secure
|
||||
mode.
|
||||
|
||||
\details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
|
||||
\return MSPLIM Register value
|
||||
\note Only available for Armv8-M Architecture.
|
||||
*/
|
||||
uint32_t __get_MSPLIM(void);
|
||||
|
||||
/**
|
||||
\brief Set Main Stack Pointer Limit
|
||||
Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||||
Stack Pointer Limit register hence the write is silently ignored in non-secure
|
||||
mode.
|
||||
|
||||
\details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
|
||||
\param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
|
||||
\note Only available for Armv8-M Architecture.
|
||||
*/
|
||||
__set_MSPLIM(uint32_t MainStackPtrLimit);
|
||||
|
||||
/**
|
||||
\endcond
|
||||
*/
|
||||
|
||||
/** @} */ /** end of Core_Register_gr **/
|
||||
319
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_DataStructs.txt
vendored
Normal file
319
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_DataStructs.txt
vendored
Normal file
@@ -0,0 +1,319 @@
|
||||
/**************************** Data Structures ***********************************************/
|
||||
/** \brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
#if (__CORTEX_M != 0x04)
|
||||
uint32_t _reserved0:27; ///< bit: 0..26 Reserved
|
||||
#else
|
||||
uint32_t _reserved0:16; ///< bit: 0..15 Reserved
|
||||
uint32_t GE:4; ///< bit: 16..19 Greater than or Equal flags
|
||||
uint32_t _reserved1:7; ///< bit: 20..26 Reserved
|
||||
#endif
|
||||
uint32_t Q:1; ///< bit: 27 Saturation condition flag
|
||||
uint32_t V:1; ///< bit: 28 Overflow condition code flag
|
||||
uint32_t C:1; ///< bit: 29 Carry condition code flag
|
||||
uint32_t Z:1; ///< bit: 30 Zero condition code flag
|
||||
uint32_t N:1; ///< bit: 31 Negative condition code flag
|
||||
} b; ///< Structure used for bit access
|
||||
uint32_t w; ///< Type used for word access
|
||||
} APSR_Type;
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; ///< bit: 0.. 8 Exception number
|
||||
uint32_t _reserved0:23; ///< bit: 9..31 Reserved
|
||||
} b; ///< Structure used for bit access
|
||||
uint32_t w; ///< Type used for word access
|
||||
} IPSR_Type;
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; ///< bit: 0.. 8 Exception number
|
||||
#if (__CORTEX_M != 0x04)
|
||||
uint32_t _reserved0:15; ///< bit: 9..23 Reserved
|
||||
#else
|
||||
uint32_t _reserved0:7; ///< bit: 9..15 Reserved
|
||||
uint32_t GE:4; ///< bit: 16..19 Greater than or Equal flags
|
||||
uint32_t _reserved1:4; ///< bit: 20..23 Reserved
|
||||
#endif
|
||||
uint32_t T:1; ///< bit: 24 Thumb bit (read 0)
|
||||
uint32_t IT:2; ///< bit: 25..26 saved IT state (read 0)
|
||||
uint32_t Q:1; ///< bit: 27 Saturation condition flag
|
||||
uint32_t V:1; ///< bit: 28 Overflow condition code flag
|
||||
uint32_t C:1; ///< bit: 29 Carry condition code flag
|
||||
uint32_t Z:1; ///< bit: 30 Zero condition code flag
|
||||
uint32_t N:1; ///< bit: 31 Negative condition code flag
|
||||
} b; ///< Structure used for bit access
|
||||
uint32_t w; ///< Type used for word access
|
||||
} xPSR_Type;
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t nPRIV:1; ///< bit: 0 Execution privilege in Thread mode
|
||||
uint32_t SPSEL:1; ///< bit: 1 Stack to be used
|
||||
uint32_t FPCA:1; ///< bit: 2 FP extension active flag
|
||||
uint32_t _reserved0:29; ///< bit: 3..31 Reserved
|
||||
} b; ///< Structure used for bit access
|
||||
uint32_t w; ///< Type used for word access
|
||||
} CONTROL_Type;
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[8]; ///< Offset: 0x000 (R/W) Interrupt Set Enable Register
|
||||
uint32_t RESERVED0[24]; ///< Reserved
|
||||
__IOM uint32_t ICER[8]; ///< Offset: 0x080 (R/W) Interrupt Clear Enable Register
|
||||
uint32_t RSERVED1[24]; ///< Reserved
|
||||
__IOM uint32_t ISPR[8]; ///< Offset: 0x100 (R/W) Interrupt Set Pending Register
|
||||
uint32_t RESERVED2[24]; ///< Reserved
|
||||
__IOM uint32_t ICPR[8]; ///< Offset: 0x180 (R/W) Interrupt Clear Pending Register
|
||||
uint32_t RESERVED3[24]; ///< Reserved
|
||||
__IOM uint32_t IABR[8]; ///< Offset: 0x200 (R/W) Interrupt Active bit Register
|
||||
uint32_t RESERVED4[56]; ///< Reserved
|
||||
__IOM uint8_t IP[240]; ///< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide)
|
||||
uint32_t RESERVED5[644]; ///< Reserved
|
||||
__OM uint32_t STIR; ///< Offset: 0xE00 ( /W) Software Trigger Interrupt Register
|
||||
} NVIC_Type;
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; ///< Offset: 0x000 (R/ ) CPUID Base Register
|
||||
__IOM uint32_t ICSR; ///< Offset: 0x004 (R/W) Interrupt Control and State Register
|
||||
__IOM uint32_t VTOR; ///< Offset: 0x008 (R/W) Vector Table Offset Register
|
||||
__IOM uint32_t AIRCR; ///< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register
|
||||
__IOM uint32_t SCR; ///< Offset: 0x010 (R/W) System Control Register
|
||||
__IOM uint32_t CCR; ///< Offset: 0x014 (R/W) Configuration Control Register
|
||||
__IOM uint8_t SHP[12]; ///< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15)
|
||||
__IOM uint32_t SHCSR; ///< Offset: 0x024 (R/W) System Handler Control and State Register
|
||||
__IOM uint32_t CFSR; ///< Offset: 0x028 (R/W) Configurable Fault Status Register
|
||||
__IOM uint32_t HFSR; ///< Offset: 0x02C (R/W) HardFault Status Register
|
||||
__IOM uint32_t DFSR; ///< Offset: 0x030 (R/W) Debug Fault Status Register
|
||||
__IOM uint32_t MMFAR; ///< Offset: 0x034 (R/W) MemManage Fault Address Register
|
||||
__IOM uint32_t BFAR; ///< Offset: 0x038 (R/W) BusFault Address Register
|
||||
__IOM uint32_t AFSR; ///< Offset: 0x03C (R/W) Auxiliary Fault Status Register
|
||||
__IM uint32_t PFR[2]; ///< Offset: 0x040 (R/ ) Processor Feature Register
|
||||
__IM uint32_t DFR; ///< Offset: 0x048 (R/ ) Debug Feature Register
|
||||
__IM uint32_t ADR; ///< Offset: 0x04C (R/ ) Auxiliary Feature Register
|
||||
__IM uint32_t MMFR[4]; ///< Offset: 0x050 (R/ ) Memory Model Feature Register
|
||||
__IM uint32_t ISAR[5]; ///< Offset: 0x060 (R/ ) Instruction Set Attributes Register
|
||||
uint32_t RESERVED0[5]; ///< Reserved
|
||||
__IOM uint32_t CPACR; ///< Offset: 0x088 (R/W) Coprocessor Access Control Register
|
||||
} SCB_Type;
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Structure type to access the System Control and ID Register not in the SCB.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RESERVED0[1]; /*!< Reserved */
|
||||
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register
|
||||
\note available for Cortex-M3, Cortex-M4, Cortex-M7, Cortex-M33, Cortex-M33P, SecureCore SC300 */
|
||||
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register
|
||||
\note available for Cortex-M1, Cortex-M3 , Cortex-M4, Cortex-M7, Cortex-M33, Cortex-M33P, SecureCore SC000, SecureCore SC300 */
|
||||
__IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register
|
||||
\note available for Cortex-M33, Cortex-M33P */
|
||||
} SCnSCB_Type;
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Structure type to access the Implementation Control Block Register (ICB).
|
||||
\note replaces SCnSCB_Type (only on Cortex-M55/M85)
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RESERVED0[1U];
|
||||
__IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
|
||||
__IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
||||
__IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */
|
||||
} ICB_Type;
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; ///< Offset: 0x000 (R/W) SysTick Control and Status Register
|
||||
__IOM uint32_t LOAD; ///< Offset: 0x004 (R/W) SysTick Reload Value Register
|
||||
__IOM uint32_t VAL; ///< Offset: 0x008 (R/W) SysTick Current Value Register
|
||||
__IM uint32_t CALIB; ///< Offset: 0x00C (R/ ) SysTick Calibration Register
|
||||
} SysTick_Type;
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__OM union
|
||||
{
|
||||
__OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
|
||||
__OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
|
||||
__OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
|
||||
} PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
|
||||
// uint32_t RESERVED0[864U];
|
||||
__IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
|
||||
// uint32_t RESERVED1[15U];
|
||||
__IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
|
||||
// uint32_t RESERVED2[15U];
|
||||
__IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
|
||||
// uint32_t RESERVED3[29U];
|
||||
__OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
|
||||
__IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
|
||||
__IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
|
||||
// uint32_t RESERVED4[43U];
|
||||
__OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
|
||||
__IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
|
||||
// uint32_t RESERVED5[1U];
|
||||
__IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register (Cortex-M33 only) */
|
||||
// uint32_t RESERVED6[4U];
|
||||
__IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
|
||||
__IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
|
||||
__IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
|
||||
__IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
|
||||
__IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
|
||||
__IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
|
||||
__IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
|
||||
__IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
|
||||
__IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
|
||||
__IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
|
||||
__IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
|
||||
__IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
|
||||
} ITM_Type;
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Structure type to access the Memory Protection Unit (MPU).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t TYPE; ///< Offset: 0x000 (R/ ) MPU Type Register
|
||||
__IOM uint32_t CTRL; ///< Offset: 0x004 (R/W) MPU Control Register
|
||||
__IOM uint32_t RNR; ///< Offset: 0x008 (R/W) MPU Region RNRber Register
|
||||
__IOM uint32_t RBAR; ///< Offset: 0x00C (R/W) MPU Region Base Address Register
|
||||
__IOM uint32_t RASR; ///< Offset: 0x010 (R/W) MPU Region Attribute and Size Register
|
||||
__IOM uint32_t RBAR_A1; ///< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register
|
||||
__IOM uint32_t RASR_A1; ///< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register
|
||||
__IOM uint32_t RBAR_A2; ///< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register
|
||||
__IOM uint32_t RASR_A2; ///< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register
|
||||
__IOM uint32_t RBAR_A3; ///< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register
|
||||
__IOM uint32_t RASR_A3; ///< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register
|
||||
} MPU_Type;
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Structure type to access the Floating Point Unit (FPU).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RESERVED0[1]; ///< Reserved
|
||||
__IOM uint32_t FPCCR; ///< Offset: 0x004 (R/W) Floating-Point Context Control Register
|
||||
__IOM uint32_t FPCAR; ///< Offset: 0x008 (R/W) Floating-Point Context Address Register
|
||||
__IOM uint32_t FPDSCR; ///< Offset: 0x00C (R/W) Floating-Point Default Status Control Register
|
||||
__IM uint32_t MVFR0; ///< Offset: 0x010 (R/ ) Media and FP Feature Register 0
|
||||
__IM uint32_t MVFR1; ///< Offset: 0x014 (R/ ) Media and FP Feature Register 1
|
||||
} FPU_Type;
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Structure type to access the Core Debug Register (CoreDebug).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t DHCSR; ///< Offset: 0x000 (R/W) Debug Halting Control and Status Register
|
||||
__OM uint32_t DCRSR; ///< Offset: 0x004 ( /W) Debug Core Register Selector Register
|
||||
__IOM uint32_t DCRDR; ///< Offset: 0x008 (R/W) Debug Core Register Data Register
|
||||
__IOM uint32_t DEMCR; ///< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register
|
||||
} CoreDebug_Type;
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; ///< Offset: 0x000 (R/W) Control Register
|
||||
__IOM uint32_t CYCCNT; ///< Offset: 0x004 (R/W) Cycle Count Register
|
||||
__IOM uint32_t CPICNT; ///< Offset: 0x008 (R/W) CPI Count Register
|
||||
__IOM uint32_t EXCCNT; ///< Offset: 0x00C (R/W) Exception Overhead Count Register
|
||||
__IOM uint32_t SLEEPCNT; ///< Offset: 0x010 (R/W) Sleep Count Register
|
||||
__IOM uint32_t LSUCNT; ///< Offset: 0x014 (R/W) LSU Count Register
|
||||
__IOM uint32_t FOLDCNT; ///< Offset: 0x018 (R/W) Folded-instruction Count Register
|
||||
__IM uint32_t PCSR; ///< Offset: 0x01C (R/ ) Program Counter Sample Register
|
||||
__IOM uint32_t COMP0; ///< Offset: 0x020 (R/W) Comparator Register 0
|
||||
__IOM uint32_t MASK0; ///< Offset: 0x024 (R/W) Mask Register 0
|
||||
__IOM uint32_t FUNCTION0; ///< Offset: 0x028 (R/W) Function Register 0
|
||||
uint32_t RESERVED0[1]; ///< Reserved
|
||||
__IOM uint32_t COMP1; ///< Offset: 0x030 (R/W) Comparator Register 1
|
||||
__IOM uint32_t MASK1; ///< Offset: 0x034 (R/W) Mask Register 1
|
||||
__IOM uint32_t FUNCTION1; ///< Offset: 0x038 (R/W) Function Register 1
|
||||
uint32_t RESERVED1[1]; ///< Reserved
|
||||
__IOM uint32_t COMP2; ///< Offset: 0x040 (R/W) Comparator Register 2
|
||||
__IOM uint32_t MASK2; ///< Offset: 0x044 (R/W) Mask Register 2
|
||||
__IOM uint32_t FUNCTION2; ///< Offset: 0x048 (R/W) Function Register 2
|
||||
uint32_t RESERVED2[1]; ///< Reserved
|
||||
__IOM uint32_t COMP3; ///< Offset: 0x050 (R/W) Comparator Register 3
|
||||
__IOM uint32_t MASK3; ///< Offset: 0x054 (R/W) Mask Register 3
|
||||
__IOM uint32_t FUNCTION3; ///< Offset: 0x058 (R/W) Function Register 3
|
||||
} DWT_Type;
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Structure type to access the Trace Port Interface Register (TPI).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t SSPSR; ///< Offset: 0x000 (R/ ) Supported Parallel Port Size Register
|
||||
__IOM uint32_t CSPSR; ///< Offset: 0x004 (R/W) Current Parallel Port Size Register
|
||||
uint32_t RESERVED0[2]; ///< Reserved
|
||||
__IOM uint32_t ACPR; ///< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register
|
||||
uint32_t RESERVED1[55]; ///< Reserved
|
||||
__IOM uint32_t SPPR; ///< Offset: 0x0F0 (R/W) Selected Pin Protocol Register
|
||||
uint32_t RESERVED2[131]; ///< Reserved
|
||||
__IM uint32_t FFSR; ///< Offset: 0x300 (R/ ) Formatter and Flush Status Register
|
||||
__IOM uint32_t FFCR; ///< Offset: 0x304 (R/W) Formatter and Flush Control Register
|
||||
__IM uint32_t FSCR; ///< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register
|
||||
uint32_t RESERVED3[759]; ///< Reserved
|
||||
__IM uint32_t TRIGGER; ///< Offset: 0xEE8 (R/ ) TRIGGER
|
||||
__IM uint32_t FIFO0; ///< Offset: 0xEEC (R/ ) Integration ETM Data
|
||||
__IM uint32_t ITATBCTR2; ///< Offset: 0xEF0 (R/ ) ITATBCTR2
|
||||
uint32_t RESERVED4[1]; ///< Reserved
|
||||
__IM uint32_t ITATBCTR0; ///< Offset: 0xEF8 (R/ ) ITATBCTR0
|
||||
__IM uint32_t FIFO1; ///< Offset: 0xEFC (R/ ) Integration ITM Data
|
||||
__IOM uint32_t ITCTRL; ///< Offset: 0xF00 (R/W) Integration Mode Control
|
||||
uint32_t RESERVED5[39]; ///< Reserved
|
||||
__IOM uint32_t CLAIMSET; ///< Offset: 0xFA0 (R/W) Claim tag set
|
||||
__IOM uint32_t CLAIMCLR; ///< Offset: 0xFA4 (R/W) Claim tag clear
|
||||
uint32_t RESERVED7[8]; ///< Reserved
|
||||
__IM uint32_t DEVID; ///< Offset: 0xFC8 (R/ ) TPIU_DEVID
|
||||
__IM uint32_t DEVTYPE; ///< Offset: 0xFCC (R/ ) TPIU_DEVTYPE
|
||||
} TPI_Type;
|
||||
116
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_Debug.txt
vendored
Normal file
116
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_Debug.txt
vendored
Normal file
@@ -0,0 +1,116 @@
|
||||
/* ##################################### Debug In/Output function ############################### */
|
||||
/**
|
||||
\defgroup ITM_Debug_gr Debug Access
|
||||
\brief Debug Access to the Instrumented Trace Macrocell (ITM)
|
||||
\details
|
||||
CMSIS provides additional debug functions to enlarge the Debug Access.
|
||||
Data can be transmitted via a certain global buffer variable towards the target system.
|
||||
|
||||
The Cortex-M3 / Cortex-M4 / Cortex-M7 incorporates the <b>Instrumented Trace Macrocell (ITM)</b> that
|
||||
provides together with the <b>Serial Wire Output (SWO)</b> trace capabilities for the
|
||||
microcontroller system. The ITM has 32 communication channels; two ITM
|
||||
communication channels are used by CMSIS to output the following information:
|
||||
|
||||
- <b>ITM Channel 0</b>: implements the \ref ITM_SendChar function
|
||||
which can be used for printf-style output via the debug interface.
|
||||
|
||||
- <b>ITM Channel 31</b>: is reserved for the RTOS kernel and can be used for kernel awareness debugging.
|
||||
|
||||
\remarks
|
||||
- ITM channels have 4 groups with 8 channels each, whereby each group can be configured for
|
||||
access rights in the Unprivileged level.
|
||||
- The ITM channel 0 can be enabled for the user task.
|
||||
- ITM channel 31 can be accessed only in Privileged mode
|
||||
from the RTOS kernel itself. The ITM channel 31 has been selected for the RTOS kernel because some
|
||||
kernels may use the Privileged level for program execution.
|
||||
|
||||
<hr>
|
||||
\section ITM_debug_uv ITM Debugger Support
|
||||
|
||||
A debugger may support a <b>Debug (printf) Viewer</b> window to display data.
|
||||
|
||||
<b>Direction: Microcontroller --> Debugger:</b>
|
||||
- Characters received via ITM communication channel 0 are written in a printf-style to the
|
||||
<b>Debug (printf) Viewer</b> window.
|
||||
|
||||
<b>Direction: Debugger --> Microcontroller:</b>
|
||||
- Check if \ref ITM_RxBuffer variable is available (only performed once).
|
||||
- Read the character from the <b>Debug (printf) Viewer</b> window.
|
||||
- If \ref ITM_RxBuffer is empty, write character to \ref ITM_RxBuffer.
|
||||
|
||||
\note
|
||||
The current solution does not use a buffer mechanism for transmitting the characters.
|
||||
|
||||
|
||||
<hr>
|
||||
\section itm_debug_ex Example:
|
||||
Example for the usage of the ITM Channel 31 for RTOS Kernels:
|
||||
|
||||
\code
|
||||
// check if debugger connected and ITM channel enabled for tracing
|
||||
if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
|
||||
(ITM->TCR & ITM_TCR_ITMENA) &&
|
||||
(ITM->TER & (1UL >> 31))) {
|
||||
|
||||
// transmit trace data
|
||||
while (ITM->PORT31_U32 == 0);
|
||||
ITM->PORT[31].u8 = task_id; // id of next task
|
||||
while (ITM->PORT[31].u32 == 0);
|
||||
ITM->PORT[31].u32 = task_status; // status information
|
||||
}
|
||||
\endcode
|
||||
|
||||
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
volatile int32_t ITM_RxBuffer; ///< external variable to receive characters
|
||||
|
||||
/********
|
||||
#define ITM_RxBuffer_EMPTY 0x5AA55AA5 ///< value identifying whether \ref ITM_RxBuffer is ready for the next character
|
||||
********/
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Transmits a character via channel 0.
|
||||
|
||||
This function transmits a character via the ITM channel 0.
|
||||
It returns when no debugger is connected that has booked the output.
|
||||
It is blocking when a debugger is connected, but the previously sent character has not been
|
||||
transmitted.
|
||||
|
||||
\param [in] ch Character to transmit
|
||||
|
||||
\returns Character to transmit
|
||||
*/
|
||||
uint32_t ITM_SendChar (uint32_t ch);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief ITM Receive Character
|
||||
|
||||
This function inputs a character via the external variable \ref ITM_RxBuffer.
|
||||
It returns when no debugger is connected that has booked the output.
|
||||
It is blocking when a debugger is connected, but the previously sent character has not been transmitted.
|
||||
|
||||
\returns
|
||||
- Received character
|
||||
- =1 - No character received
|
||||
*/
|
||||
int32_t ITM_ReceiveChar (void);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief ITM Check Character
|
||||
|
||||
This function reads the external variable \ref ITM_RxBuffer and checks whether a character
|
||||
is available or not.
|
||||
|
||||
\returns
|
||||
- =0 - No character available
|
||||
- =1 - Character available
|
||||
*/
|
||||
int32_t ITM_CheckChar (void);
|
||||
|
||||
/** @} */
|
||||
28
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_FPU.txt
vendored
Normal file
28
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_FPU.txt
vendored
Normal file
@@ -0,0 +1,28 @@
|
||||
/**
|
||||
\defgroup fpu_functions FPU Functions
|
||||
\brief Functions that relate to the Floating-Point Arithmetic Unit.
|
||||
\details
|
||||
Some Cortex-M processors include optional floating-point arithmetic functionality, with support
|
||||
for single and double-precision arithmetic.
|
||||
The Cortex-M processor with FPU is an implementation of the single-precision and
|
||||
double-precision variant of the Armv7-M Architecture with Floating-Point Extension (FPv5).
|
||||
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Get the FPU type.
|
||||
\returns
|
||||
- \b 0: No FPU
|
||||
- \b 1: Single precision FPU
|
||||
- \b 2: Double + Single precision FPU
|
||||
|
||||
The function returns the implemented FPU type.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SCB_GetFPUType(void);
|
||||
|
||||
/**
|
||||
@}
|
||||
*/
|
||||
|
||||
|
||||
373
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_MPU.txt
vendored
Normal file
373
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_MPU.txt
vendored
Normal file
@@ -0,0 +1,373 @@
|
||||
/**
|
||||
\defgroup mpu_functions MPU Functions for Armv6-M/v7-M
|
||||
\brief Functions that relate to the Memory Protection Unit.
|
||||
\details
|
||||
The following functions support the optional Memory Protection Unit (MPU) that is available on the Cortex-M0+, M3, M4 and M7 processor.
|
||||
|
||||
The MPU is used to prevent from illegal memory accesses that are typically caused by errors in an application software.
|
||||
|
||||
<b>Example:</b>
|
||||
\code
|
||||
int main()
|
||||
{
|
||||
// Set Region 0
|
||||
ARM_MPU_SetRegionEx(0UL, 0x08000000UL, ARM_MPU_RASR(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB));
|
||||
|
||||
ARM_MPU_Enable(0);
|
||||
|
||||
// Execute application code that is access protected by the MPU
|
||||
|
||||
ARM_MPU_Disable();
|
||||
}
|
||||
\endcode
|
||||
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
*/
|
||||
typedef struct {} MPU_Type;
|
||||
|
||||
|
||||
/** \def ARM_MPU_RBAR
|
||||
* \brief MPU Region Base Address Register Value
|
||||
*
|
||||
* This preprocessor function can be used to construct a valid \ref MPU_Type::RBAR "RBAR" value.
|
||||
* The VALID bit is implicitly set to 1.
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress)
|
||||
|
||||
/**
|
||||
* \def ARM_MPU_RASR
|
||||
* \brief MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* This macro is used to construct a valid \ref MPU_Type::RASR "RASR" value.
|
||||
* The ENABLE bit of the RASR value is implicitly set to 1.
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit. 1 = disable instruction fetches.
|
||||
* \param AccessPermission Data access permission configures read/write access for User and Privileged mode. Possible values see \ref ARM_MPU_AP_xxx.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable 1 = region is shareable between multiple bus masters.
|
||||
* \param IsCacheable 1 = region is cacheable (values may be kept in cache).
|
||||
* \param IsBufferable 1 = region is bufferable (when using write-back caching). Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field (8 bits).
|
||||
* \param Size Region size with values defined under \ref ARM_MPU_REGION_SIZE_xxx.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size)
|
||||
|
||||
|
||||
/**
|
||||
* \def ARM_MPU_RASR_EX
|
||||
* \brief MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* This macro is used to construct a valid \ref MPU_Type::RASR "RASR" value.
|
||||
* The ENABLE bit of the RASR value is implicitly set to 1.
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permission configures read/write access for User and Privileged mode. Possible values see \ref ARM_MPU_AP_xxx.
|
||||
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_xxx.
|
||||
* \param SubRegionDisable Sub-region disable field (8 bits).
|
||||
* \param Size Region size with values defined under \ref ARM_MPU_REGION_SIZE_xxx.
|
||||
*/
|
||||
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)
|
||||
|
||||
/**
|
||||
* \brief Setup information of a single MPU Region
|
||||
* \details The typedef \ref ARM_MPU_Region_t allows to define a MPU table (array of MPU regions) with pre-compiled register values.
|
||||
* Such tables enable efficient MPU setup using the function \ref ARM_MPU_Load.
|
||||
*
|
||||
* <b>Example:</b> See \ref ARM_MPU_Load
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; //!< The region base address register value (\ref MPU_Type::RBAR "RBAR")
|
||||
uint32_t RASR; //!< The region attribute and size register value (\ref MPU_Type::RASR "RASR"), see \ref ARM_MPU_RASR.
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/**
|
||||
\brief Enable the memory protection unit (MPU) and
|
||||
\param MPU_CTRL Additional control settings that configure MPU behaviour
|
||||
\details
|
||||
The function \ref ARM_MPU_Enable writes to the register \ref MPU_Type::CTRL "MPU->CTRL" and sets bit ENABLE. The parameter \em MPU_CTRL provides additional bit values
|
||||
(see table below) that configure the MPU behaviour. For processors that implement an <b>MPU Fault Handler</b> the \ref NVIC_gr "MemoryManagement_IRQn" exception is enabled by setting the bit MEMFAULTACT in register SBC->SHCSR.
|
||||
|
||||
The following table contains possible values for the parameter \em MPU_CTRL that set specific bits in register MPU->CTRL.
|
||||
| Bit | MPU_CTRL value | When applied | When not applied
|
||||
|:----|:-------------------------|:------------------------------------------------------------------------|:---------------------------------------
|
||||
| 1 | MPU_CTRL_HFNMIENA_Msk | Enable MPU during hard fault, NMI, and FAULTMASK handlers execution | Disable MPU during hard fault, NMI, and FAULTMASK handler execution
|
||||
| 2 | MPU_CTRL_PRIVDEFENA_Msk | Enable default memory map as a background region for privileged access | Use only MPU region settings
|
||||
|
||||
<b>Example:</b>
|
||||
|
||||
\code
|
||||
// enable MPU with all region definitions. Exceptions are not protected by MPU.
|
||||
MPU_Enable (0);
|
||||
|
||||
// enable MPU with all region definitions and background regions for privileged access. Exceptions are protected by MPU.
|
||||
MPU_Enable (MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_HFNMIENA_Msk);
|
||||
\endcode
|
||||
|
||||
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_CTRL);
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable();
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr);
|
||||
|
||||
/** Configure an MPU region.
|
||||
*
|
||||
* The region number should be contained in the rbar value.
|
||||
*
|
||||
* \param rbar Value for \ref MPU_Type::RBAR "RBAR" register.
|
||||
* \param rasr Value for \ref MPU_Type::RASR "RASR" register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr);
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for \ref MPU_Type::RBAR "RBAR" register.
|
||||
* \param rasr Value for \ref MPU_Type::RASR "RASR" register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr);
|
||||
|
||||
/** Memcpy with strictly ordered memory access, e.g. used by code in \ref ARM_MPU_Load.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len);
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Number of regions to be configured.
|
||||
*
|
||||
* \note only up to 16 regions can be handled as the function \ref ARM_MPU_Load uses the REGION field in \ref MPU_Type::RBAR "MPU->RBAR".
|
||||
*
|
||||
* <b>Example:</b>
|
||||
* \code
|
||||
* const ARM_MPU_Region_t mpuTable[3][4] = {
|
||||
* {
|
||||
* { .RBAR = ARM_MPU_RBAR(0UL, 0x08000000UL), .RASR = ARM_MPU_RASR(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB) },
|
||||
* { .RBAR = ARM_MPU_RBAR(1UL, 0x20000000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_32KB) },
|
||||
* { .RBAR = ARM_MPU_RBAR(2UL, 0x40020000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0x00UL, ARM_MPU_REGION_SIZE_8KB) },
|
||||
* { .RBAR = ARM_MPU_RBAR(3UL, 0x40022000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0xC0UL, ARM_MPU_REGION_SIZE_4KB) }
|
||||
* },
|
||||
* {
|
||||
* { .RBAR = ARM_MPU_RBAR(4UL, 0x08000000UL), .RASR = ARM_MPU_RASR(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB) },
|
||||
* { .RBAR = ARM_MPU_RBAR(5UL, 0x20000000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_32KB) },
|
||||
* { .RBAR = ARM_MPU_RBAR(6UL, 0x40020000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0x00UL, ARM_MPU_REGION_SIZE_8KB) },
|
||||
* { .RBAR = ARM_MPU_RBAR(7UL, 0x40022000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0xC0UL, ARM_MPU_REGION_SIZE_4KB) }
|
||||
* },
|
||||
* {
|
||||
* { .RBAR = ARM_MPU_RBAR(4UL, 0x18000000UL), .RASR = ARM_MPU_RASR(0UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_1MB) },
|
||||
* { .RBAR = ARM_MPU_RBAR(5UL, 0x30000000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 0UL, 0UL, 1UL, 1UL, 0x00UL, ARM_MPU_REGION_SIZE_32KB) },
|
||||
* { .RBAR = ARM_MPU_RBAR(6UL, 0x50020000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0x00UL, ARM_MPU_REGION_SIZE_8KB) },
|
||||
* { .RBAR = ARM_MPU_RBAR(7UL, 0x50022000UL), .RASR = ARM_MPU_RASR(1UL, ARM_MPU_AP_FULL, 2UL, 0UL, 0UL, 0UL, 0xC0UL, ARM_MPU_REGION_SIZE_4KB) }
|
||||
* }
|
||||
* };
|
||||
*
|
||||
* void UpdateMpu(uint32_t idx)
|
||||
* {
|
||||
* ARM_MPU_Load(mpuTable[idx], 4);
|
||||
* }
|
||||
* \endcode
|
||||
*
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(MPU_Region_t const* table, uint32_t cnt);
|
||||
|
||||
|
||||
/**
|
||||
@}
|
||||
|
||||
\defgroup mpu_defines Define values
|
||||
\ingroup mpu_functions
|
||||
\brief Define values for MPU region setup.
|
||||
\details
|
||||
The following define values are used with \ref ARM_MPU_RASR to setup the \ref MPU_Type::RASR "RASR" value field in the MPU region.
|
||||
|
||||
\see
|
||||
ARM_MPU_Region_t, ARM_MPU_SetRegion, ARM_MPU_SetRegionEx.
|
||||
@{
|
||||
*/
|
||||
|
||||
/** \def ARM_MPU_REGION_SIZE_xxx
|
||||
\brief Size values of a MPU region (in RASR field)
|
||||
\details
|
||||
The following define values are used to compose the size information for an MPU region:
|
||||
|
||||
|\#define | Value | Description |
|
||||
|:-------------------------|:-----------------|:---------------------------------------------------------|
|
||||
|ARM_MPU_REGION_SIZE_32B | 0x04U | Region size 32 Bytes
|
||||
|ARM_MPU_REGION_SIZE_64B | 0x05U | Region size 64 Bytes
|
||||
|ARM_MPU_REGION_SIZE_128B | 0x06U | Region size 128 Bytes
|
||||
|ARM_MPU_REGION_SIZE_256B | 0x07U | Region size 256 Bytes
|
||||
|ARM_MPU_REGION_SIZE_512B | 0x08U | Region size 512 Bytes
|
||||
|ARM_MPU_REGION_SIZE_1KB | 0x09U | Region size 1 KByte
|
||||
|ARM_MPU_REGION_SIZE_2KB | 0x0AU | Region size 2 KBytes
|
||||
|ARM_MPU_REGION_SIZE_4KB | 0x0BU | Region size 4 KBytes
|
||||
|ARM_MPU_REGION_SIZE_8KB | 0x0CU | Region size 8 KBytes
|
||||
|ARM_MPU_REGION_SIZE_16KB | 0x0DU | Region size 16 KBytes
|
||||
|ARM_MPU_REGION_SIZE_32KB | 0x0EU | Region size 32 KBytes
|
||||
|ARM_MPU_REGION_SIZE_64KB | 0x0FU | Region size 64 KBytes
|
||||
|ARM_MPU_REGION_SIZE_128KB | 0x10U | Region size 128 KBytes
|
||||
|ARM_MPU_REGION_SIZE_256KB | 0x11U | Region size 256 KBytes
|
||||
|ARM_MPU_REGION_SIZE_512KB | 0x12U | Region size 512 KBytes
|
||||
|ARM_MPU_REGION_SIZE_1MB | 0x13U | Region size 1 MByte
|
||||
|ARM_MPU_REGION_SIZE_2MB | 0x14U | Region size 2 MBytes
|
||||
|ARM_MPU_REGION_SIZE_4MB | 0x15U | Region size 4 MBytes
|
||||
|ARM_MPU_REGION_SIZE_8MB | 0x16U | Region size 8 MBytes
|
||||
|ARM_MPU_REGION_SIZE_16MB | 0x17U | Region size 16 MBytes
|
||||
|ARM_MPU_REGION_SIZE_32MB | 0x18U | Region size 32 MBytes
|
||||
|ARM_MPU_REGION_SIZE_64MB | 0x19U | Region size 64 MBytes
|
||||
|ARM_MPU_REGION_SIZE_128MB | 0x1AU | Region size 128 MBytes
|
||||
|ARM_MPU_REGION_SIZE_256MB | 0x1BU | Region size 256 MBytes
|
||||
|ARM_MPU_REGION_SIZE_512MB | 0x1CU | Region size 512 MBytes
|
||||
|ARM_MPU_REGION_SIZE_1GB | 0x1DU | Region size 1 GByte
|
||||
|ARM_MPU_REGION_SIZE_2GB | 0x1EU | Region size 2 GBytes
|
||||
|ARM_MPU_REGION_SIZE_4GB | 0x1FU | Region size 4 GBytes
|
||||
*/
|
||||
#define ARM_MPU_REGION_SIZE_xxx
|
||||
|
||||
/** \def ARM_MPU_AP_xxx
|
||||
\brief Values for MPU region access permissions (in RASR field)
|
||||
\details
|
||||
The following define values are used to compose the access permission for an MPU region:
|
||||
|\#define | Value | Access permissions |
|
||||
|:-------------------------|:-----------------|:---------------------------------------------------------|
|
||||
|ARM_MPU_AP_NONE | 0x0U | None: any access generates a permission fault.
|
||||
|ARM_MPU_AP_PRIV | 0x1U | Privileged Read/Write: privileged access only; any unprivileged access generates a permission fault.
|
||||
|ARM_MPU_AP_URO | 0x2U | Privileged Read/Write; Unprivileged Read-only: any unprivileged write generates a permission fault.
|
||||
|ARM_MPU_AP_FULL | 0x3U | Privileged Read/Write. Unprivileged Read/Write: full access, permission faults are never generated.
|
||||
|ARM_MPU_AP_PRO | 0x5U | Privileged Read-only: any unprivileged access or privileged write generates a permission fault.
|
||||
|ARM_MPU_AP_RO | 0x6U | Privileged and Unprivileged Read-only: any write generates a permission fault.
|
||||
*/
|
||||
#define ARM_MPU_AP_xxx
|
||||
|
||||
/** \def ARM_MPU_ACCESS_xxx
|
||||
\brief Values for MPU region access attributes (in RASR field)
|
||||
\details
|
||||
The following define values are used to compose the access attributes for an MPU region:
|
||||
|\#define | TEX | Shareable | Cacheable | Bufferable | Description |
|
||||
|:-----------------------------|:-----|:----------|:----------|:-----------|:------------------------|
|
||||
| ARM_MPU_ACCESS_ORDERED | 000b | 1 | 0 | 0 | Strongly ordered memory |
|
||||
| ARM_MPU_ACCESS_DEVICE(S) | 0s0b | S | 0 | S | Memory mapped peripheral device, shared (S=1) or non-shared (S=0) |
|
||||
| ARM_MPU_ACCESS_NORMAL(O,I,S) | 1BBb | S | A | A | Normal memory, with outer/inner cache policy (O/I=\ref ARM_MPU_CACHEP_xxx, shared (S=1) or non-share (S=0) |
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_xxx
|
||||
|
||||
/** \def ARM_MPU_CACHEP_xxx
|
||||
\brief Cache policy values for MPU region access attributes (in RASR field)
|
||||
\details
|
||||
The following define values are used to compose the cacheability flags within the
|
||||
access attributes for an MPU region:
|
||||
|\#define | Value | Cacheability policy |
|
||||
|:-----------------------------|:------|:------------------------|
|
||||
| ARM_MPU_CACHEP_NOCACHE | 00b | Non-cacheable |
|
||||
| ARM_MPU_CACHEP_WB_WRA | 01b | Write-back, write and read allocate |
|
||||
| ARM_MPU_CACHEP_WT_NWA | 10b | Write-through, no write allocate |
|
||||
| ARM_MPU_CACHEP_WB_NWA | 11b | Write-back, no write allocate |
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_xxx
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
|
||||
\var ARM_MPU_Region_t::RBAR
|
||||
This value specifies the start address of the MPU protected memory region. The address must be a multiple of the region size (size aligned).
|
||||
|
||||
See \ref MPU_Type::RBAR for details about field bit format.
|
||||
|
||||
\var ARM_MPU_Region_t::RASR
|
||||
This value specifies region attributes and size. Use the \ref ARM_MPU_RASR macro to compose this value.
|
||||
|
||||
\var MPU_Type::TYPE
|
||||
The MPU Type Register indicates how many regions the MPU support. Software can use it
|
||||
to determine if the processor implements an MPU.
|
||||
|
||||
| Bits | Name | Function |
|
||||
| :------ | :------------ | :------------------------------------------------------------ |
|
||||
| [31:24] | - | Reserved. |
|
||||
| [23:16] | IREGION | Instruction region. RAZ. Armv7-M only supports a unified MPU. |
|
||||
| [15:8] | DREGION | Number of regions supported by the MPU. If this field reads-as-zero the processor does not implement an MPU. |
|
||||
| [7:1] | - | Reserved. |
|
||||
| [0] | SEPARATE | Indicates support for separate instruction and data address maps. RAZ. Armv7-M only supports a unified MPU. |
|
||||
|
||||
\var MPU_Type::CTRL
|
||||
Enables the MPU, and when the MPU is enabled, controls whether the default memory map
|
||||
is enabled as a background region for privileged accesses, and whether the MPU is enabled
|
||||
for HardFaults, NMIs, and exception handlers when FAULTMASK is set to 1.
|
||||
|
||||
| Bits | Name | Function |
|
||||
| :------ | :------------ | :------------------------------------------------------------ |
|
||||
| [31:3] | - | Reserved. |
|
||||
| [2] | PRIVDEFENA | 0 - Disables the default memory map. 1 - Enables the default memory map as a background region for privileged access. |
|
||||
| [1] | HFNMIENA | 0 - Disables the MPU for exception handlers. 1 - Use the MPU for memory accesses by exception handlers. |
|
||||
| [0] | ENABLE | 0 - The MPU is disabled. 1 - The MPU is enabled. |
|
||||
|
||||
\var MPU_Type::RNR
|
||||
Selects the region currently accessed by \ref MPU_Type::RBAR and \ref MPU_Type::RASR.
|
||||
|
||||
| Bits | Name | Function |
|
||||
| :------ | :------------ | :------------------------------------------------------------ |
|
||||
| [31:8] | - | Reserved. |
|
||||
| [7:0] | REGION | Indicates the memory region accessed. |
|
||||
|
||||
\var MPU_Type::RBAR
|
||||
Holds the base address of the region identified by MPU_RNR. On a write, can also be used
|
||||
to update the base address of a specified region, in the range 0 to 15, updating MPU_RNR
|
||||
with the new region number.
|
||||
|
||||
| Bits | Name | Function |
|
||||
| :------ | :------------ | :------------------------------------------------------------ |
|
||||
| [31:5] | ADDR | Base address of the region. |
|
||||
| [4] | VALID | 1 - Update \ref MPU_Type::RNR to the value obtained by zero extending the REGION value specified in this write, and apply the base address update to this region. |
|
||||
| [3:0] | REGION | On writes, can specify the number of the region to update, see VALID field description. |
|
||||
|
||||
\var MPU_Type::RASR
|
||||
Defines the size and access behavior of the region identified by MPU_RNR, and enables
|
||||
that region.
|
||||
|
||||
| Bits | Name | Function |
|
||||
| :------ | :------------ | :------------------------------------------------------------ |
|
||||
| [31:29] | - | Reserved. |
|
||||
| [28] | XN | Execute Never. |
|
||||
| [27] | - | Reserved. |
|
||||
| [26:24] | AP | Access Permissions, see \ref ARM_MPU_AP_xxx. |
|
||||
| [23:22] | - | Reserved. |
|
||||
| [21:19] | TEX | Type Extension. |
|
||||
| [18] | S | Shareable. |
|
||||
| [17] | C | Cacheable. |
|
||||
| [16] | B | Bufferable. |
|
||||
| [15:8] | SRD | Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled (0) or disabled (1).
|
||||
| [7:6] | - | Reserved. |
|
||||
| [5:1] | SIZE | Indicates the region size. The region size, in bytes, is 2(SIZE+1). SIZE field values less than 4 are reserved, because the smallest supported region size is 32 bytes. |
|
||||
| [0] | ENABLE | 0 - This region is disabled. 1 - This region is enabled. |
|
||||
|
||||
\var MPU_Type::RBAR_A1
|
||||
Alias for \ref MPU_Type::RBAR.
|
||||
|
||||
\var MPU_Type::RASR_A1
|
||||
Alias for \ref MPU_Type::RASR.
|
||||
|
||||
\var MPU_Type::RBAR_A2
|
||||
Alias for \ref MPU_Type::RBAR.
|
||||
|
||||
\var MPU_Type::RASR_A2
|
||||
Alias for \ref MPU_Type::RASR.
|
||||
|
||||
\var MPU_Type::RBAR_A3
|
||||
Alias for \ref MPU_Type::RBAR.
|
||||
|
||||
\var MPU_Type::RASR_A3
|
||||
Alias for \ref MPU_Type::RASR.
|
||||
|
||||
*/
|
||||
300
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_MPU8.txt
vendored
Normal file
300
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_MPU8.txt
vendored
Normal file
@@ -0,0 +1,300 @@
|
||||
/**
|
||||
\defgroup mpu8_functions MPU Functions for Armv8-M
|
||||
\brief Functions that relate to the Memory Protection Unit.
|
||||
\details
|
||||
The following functions support the optional Memory Protection Unit (MPU) that is available on the Cortex-M23, M33, M35P processor.
|
||||
|
||||
The MPU is used to prevent from illegal memory accesses that are typically caused by errors in an application software.
|
||||
|
||||
<b>Example:</b>
|
||||
\code
|
||||
int main()
|
||||
{
|
||||
// Set Region 0 using Attr 0
|
||||
ARM_MPU_SetMemAttr(0UL, ARM_MPU_ATTR( /* Normal memory */
|
||||
MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA, /* Outer Write-Back transient with read and write allocate */
|
||||
MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA /* Inner Write-Through transient with read and write allocate */
|
||||
));
|
||||
|
||||
ARM_MPU_SetRegion(0UL,
|
||||
ARM_MPU_RBAR(0x08000000UL, ARM_MPU_SH_NON, ARM_MPU_AP_RW, ARM_MPU_AP_NP, ARM_MPU_XN), /* Non-shareable, read/write, non-privileged, execute-never */
|
||||
ARM_MPU_RLAR(0x080FFFFFUL, MAIR_ATTR(0)) /* 1MB memory block using Attr 0 */
|
||||
);
|
||||
|
||||
ARM_MPU_Enable(0);
|
||||
|
||||
// Execute application code that is access protected by the MPU
|
||||
|
||||
ARM_MPU_Disable();
|
||||
}
|
||||
\endcode
|
||||
|
||||
@{
|
||||
*/
|
||||
|
||||
/** \brief Attribute for device memory (outer only) */
|
||||
#define ARM_MPU_ATTR_DEVICE ( 0U )
|
||||
|
||||
/** \brief Attribute for non-cacheable, normal memory */
|
||||
#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U )
|
||||
|
||||
/** \brief Attribute for Normal memory, Outer and Inner cacheability.
|
||||
* \param NT Non-Transient: Set to 1 for Non-transient data. Set to 0 for Transient data.
|
||||
* \param WB Write-Back: Set to 1 to use a Write-Back policy. Set to 0 to use a Write-Through policy.
|
||||
* \param RA Read Allocation: Set to 1 to enable cache allocation on read miss. Set to 0 to disable cache allocation on read miss.
|
||||
* \param WA Write Allocation: Set to 1 to enable cache allocation on write miss. Set to 0 to disable cache allocation on write miss.
|
||||
*/
|
||||
#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA)
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRnE
|
||||
|
||||
/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGnRE
|
||||
|
||||
/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_nGRE
|
||||
|
||||
/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
|
||||
#define ARM_MPU_ATTR_DEVICE_GRE
|
||||
|
||||
/** \brief Normal memory outer-cacheable and inner-cacheable attributes
|
||||
* WT = Write Through, WB = Write Back, TR = Transient, RA = Read-Allocate, WA = Write Allocate
|
||||
*/
|
||||
#define MPU_ATTR_NORMAL_OUTER_NON_CACHEABLE
|
||||
#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA
|
||||
#define MPU_ATTR_NORMAL_OUTER_WT_TR_WA
|
||||
#define MPU_ATTR_NORMAL_OUTER_WT_TR_RA_WA
|
||||
#define MPU_ATTR_NORMAL_OUTER_WT_RA
|
||||
#define MPU_ATTR_NORMAL_OUTER_WT_WA
|
||||
#define MPU_ATTR_NORMAL_OUTER_WT_RA_WA
|
||||
#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA
|
||||
#define MPU_ATTR_NORMAL_OUTER_WB_TR_WA
|
||||
#define MPU_ATTR_NORMAL_OUTER_WB_TR_RA_WA
|
||||
#define MPU_ATTR_NORMAL_OUTER_WB_RA
|
||||
#define MPU_ATTR_NORMAL_OUTER_WB_WA
|
||||
#define MPU_ATTR_NORMAL_OUTER_WB_RA_WA
|
||||
#define MPU_ATTR_NORMAL_INNER_NON_CACHEABLE
|
||||
#define MPU_ATTR_NORMAL_INNER_WT_TR_RA
|
||||
#define MPU_ATTR_NORMAL_INNER_WT_TR_WA
|
||||
#define MPU_ATTR_NORMAL_INNER_WT_TR_RA_WA
|
||||
#define MPU_ATTR_NORMAL_INNER_WT_RA
|
||||
#define MPU_ATTR_NORMAL_INNER_WT_WA
|
||||
#define MPU_ATTR_NORMAL_INNER_WT_RA_WA
|
||||
#define MPU_ATTR_NORMAL_INNER_WB_TR_RA
|
||||
#define MPU_ATTR_NORMAL_INNER_WB_TR_WA
|
||||
#define MPU_ATTR_NORMAL_INNER_WB_TR_RA_WA
|
||||
#define MPU_ATTR_NORMAL_INNER_WB_RA
|
||||
#define MPU_ATTR_NORMAL_INNER_WB_WA
|
||||
#define MPU_ATTR_NORMAL_INNER_WB_RA_WA
|
||||
|
||||
/** \brief Memory Attribute
|
||||
* \param O Outer memory attributes
|
||||
* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
|
||||
*/
|
||||
#define ARM_MPU_ATTR(O, I)
|
||||
|
||||
/**
|
||||
* Shareability
|
||||
*/
|
||||
/** \brief Normal memory non-shareable */
|
||||
#define ARM_MPU_SH_NON
|
||||
|
||||
/** \brief Normal memory outer shareable */
|
||||
#define ARM_MPU_SH_OUTER
|
||||
|
||||
/** \brief Normal memory inner shareable */
|
||||
#define ARM_MPU_SH_INNER
|
||||
|
||||
/**
|
||||
* Access permissions
|
||||
* AP = Access permission, RO = Read-only, RW = Read/Write, NP = Any privilege, PO = Privileged code only
|
||||
*/
|
||||
/** \brief Normal memory, read/write */
|
||||
#define ARM_MPU_AP_RW
|
||||
|
||||
/** \brief Normal memory, read-only */
|
||||
#define ARM_MPU_AP_RO
|
||||
|
||||
/** \brief Normal memory, any privilege level */
|
||||
#define ARM_MPU_AP_NP
|
||||
|
||||
/** \brief Normal memory, privileged access only */
|
||||
#define ARM_MPU_AP_PO
|
||||
|
||||
/*
|
||||
* Execute-never
|
||||
* XN = Execute-never, EX = Executable
|
||||
*/
|
||||
/** \brief Normal memory, Execution only permitted if read permitted */
|
||||
#define ARM_MPU_XN
|
||||
|
||||
/** \brief Normal memory, Execution only permitted if read permitted */
|
||||
#define ARM_MPU_EX
|
||||
|
||||
/** \brief Memory access permissions
|
||||
* \param RO Read-Only: Set to 1 for read-only memory.
|
||||
* \param NP Non-Privileged: Set to 1 for non-privileged memory.
|
||||
*/
|
||||
#define ARM_MPU_AP_(RO, NP)
|
||||
|
||||
/** \brief Region Base Address Register value
|
||||
* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
|
||||
* \param SH Defines the Shareability domain for this memory region.
|
||||
* \param RO Read-Only: Set to 1 for a read-only memory region. Set to 0 for a read/write memory region.
|
||||
* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. Set to 0 for privileged memory region.
|
||||
* \param XN eXecute Never: Set to 1 for a non-executable memory region. Set to 0 for an executable memory region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN)
|
||||
|
||||
/** \brief Region Limit Address Register value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR(LIMIT, IDX)
|
||||
|
||||
/** \brief Region Limit Address Register with PXN value
|
||||
* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
|
||||
* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
|
||||
* \param IDX The attribute index to be associated with this memory region.
|
||||
*/
|
||||
#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX)
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; /*!< Region Base Address Register value */
|
||||
uint32_t RLAR; /*!< Region Limit Address Register value */
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/**
|
||||
\brief Read MPU Type Register
|
||||
\return Number of MPU regions
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_MPU_TYPE()
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control);
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void);
|
||||
|
||||
/** Enable the Non-secure MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE ARM_MPU_Enable_NS(uint32_t MPU_Control);
|
||||
|
||||
/** Disable the Non-secure MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable_NS(void);
|
||||
|
||||
/** Set the memory attribute encoding to the given MPU.
|
||||
* \param mpu Pointer to the MPU to be configured.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr);
|
||||
|
||||
/** Set the memory attribute encoding.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr);
|
||||
|
||||
/** Set the memory attribute encoding to the Non-secure MPU.
|
||||
* \param idx The attribute index to be set [0-7]
|
||||
* \param attr The attribute value to be set.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr);
|
||||
|
||||
/** Clear and disable the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr);
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr);
|
||||
|
||||
/** Clear and disable the given Non-secure MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr);
|
||||
|
||||
/** Configure the given MPU region of the given MPU.
|
||||
* \param mpu Pointer to MPU to be used.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar);
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar);
|
||||
|
||||
/** Configure the given Non-secure MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rlar Value for RLAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar);
|
||||
|
||||
/** Memcpy with strictly ordered memory access, e.g. used by code in \ref ARM_MPU_LoadEx.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len);
|
||||
|
||||
/** Load the given number of MPU regions from a table to the given MPU.
|
||||
* \param mpu Pointer to the MPU registers to be used.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt);
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*
|
||||
* <b>Example:</b>
|
||||
* \code
|
||||
* const ARM_MPU_Region_t mpuTable[1][4] = {
|
||||
* {
|
||||
* // BASE SH RO NP XN LIMIT ATTR
|
||||
* { .RBAR = ARM_MPU_RBAR(0x08000000UL, ARM_MPU_SH_NON, ARM_MPU_AP_RO, ARM_MPU_AP_NP, ARM_MPU_XN), .RLAR = ARM_MPU_RLAR(0x080FFFFFUL, MAIR_ATTR(0)) },
|
||||
* { .RBAR = ARM_MPU_RBAR(0x20000000UL, ARM_MPU_SH_NON, ARM_MPU_AP_RO, ARM_MPU_AP_NP, ARM_MPU_XN), .RLAR = ARM_MPU_RLAR(0x20007FFFUL, MAIR_ATTR(0)) },
|
||||
* { .RBAR = ARM_MPU_RBAR(0x40020000UL, ARM_MPU_SH_NON, ARM_MPU_AP_RO, ARM_MPU_AP_NP, ARM_MPU_XN), .RLAR = ARM_MPU_RLAR(0x40021FFFUL, MAIR_ATTR(1)) },
|
||||
* { .RBAR = ARM_MPU_RBAR(0x40022000UL, ARM_MPU_SH_NON, ARM_MPU_AP_RO, ARM_MPU_AP_NP, ARM_MPU_XN), .RLAR = ARM_MPU_RLAR(0x40022FFFUL, MAIR_ATTR(1)) }
|
||||
* }
|
||||
* };
|
||||
*
|
||||
* void UpdateMpu(uint32_t idx)
|
||||
* {
|
||||
* ARM_MPU_Load(0, mpuTable[idx], 4);
|
||||
* }
|
||||
* \endcode
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt);
|
||||
|
||||
/** Load the given number of MPU regions from a table to the Non-secure MPU.
|
||||
* \param rnr First region number to be configured.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt);
|
||||
|
||||
/** @} */
|
||||
|
||||
24
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_MVE.txt
vendored
Normal file
24
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_MVE.txt
vendored
Normal file
@@ -0,0 +1,24 @@
|
||||
/**
|
||||
\defgroup mve_functions MVE Functions
|
||||
\brief Functions that relate to the MVE (Cortex-M Vector Extensions) Unit.
|
||||
\details
|
||||
Some Cortex-M processors include an optional MVE unit.
|
||||
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Get the MVE type.
|
||||
\details Returns the MVE type.
|
||||
\returns
|
||||
- \b 0: No Vector Extension (MVE)
|
||||
- \b 1: Integer Vector Extension (MVE-I)
|
||||
- \b 2: Floating-point Vector Extension (MVE-F)
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SCB_GetMVEType(void);
|
||||
|
||||
/**
|
||||
@}
|
||||
*/
|
||||
|
||||
|
||||
836
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_NVIC.txt
vendored
Normal file
836
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_NVIC.txt
vendored
Normal file
@@ -0,0 +1,836 @@
|
||||
/**
|
||||
\defgroup NVIC_gr Interrupts and Exceptions (NVIC)
|
||||
@{
|
||||
\brief Functions to access the Nested Vector Interrupt Controller (NVIC).
|
||||
\details
|
||||
This section explains how to use interrupts and exceptions and access functions for the Nested Vector Interrupt Controller (NVIC).
|
||||
|
||||
Arm provides a template file <strong>startup_<em>device</em></strong> for each supported
|
||||
compiler. The file must be adapted by the silicon vendor to include interrupt vectors for all device-specific
|
||||
interrupt handlers. Each interrupt handler is defined as a <strong><em>weak</em></strong> function
|
||||
to an dummy handler. These interrupt handlers can be used directly in application software
|
||||
without being adapted by the programmer.
|
||||
|
||||
The table below lists the core exception vectors of the various Cortex-M processors.
|
||||
|
||||
<table class="cmtable" summary="Core Exception Name">
|
||||
<tr>
|
||||
<th>Exception Vector</th>
|
||||
<th>Handler Function</th>
|
||||
<th>IRQn<br/>Value</th>
|
||||
<th title="Cortex-M0/M0+
|
||||
\if ARMSC
|
||||
and SC000
|
||||
\endif
|
||||
">Armv6-M</th>
|
||||
<th title="Cortex-M3/M4/M7
|
||||
\if ARMSC
|
||||
and SC300
|
||||
\endif
|
||||
">Armv7-M</th>
|
||||
\if ARMv8M
|
||||
<th title="Cortex-M23">Armv8-M<br/>Baseline</th>
|
||||
<th title="Cortex-M33/M35P">Armv8-M<br/>Mainline</th>
|
||||
<th>Armv8.1-M<br/>Mainline</th>
|
||||
\endif
|
||||
<th>Description</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><b>NonMaskableInt_IRQn</b></td>
|
||||
<td>NMI_Handler</td>
|
||||
<td>-14</td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
\if ARMv8M
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
\endif
|
||||
<td>Non Maskable Interrupt</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><b>HardFault_IRQn</b></td>
|
||||
<td>HardFault_Handler</td>
|
||||
<td>-13</td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
\if ARMv8M
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
\endif
|
||||
<td>Hard Fault Interrupt</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><b>MemoryManagement_IRQn</b></td>
|
||||
<td>MemManage_Handler</td>
|
||||
<td>-12</td>
|
||||
<td> </td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
\if ARMv8M
|
||||
<td> </td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
\endif
|
||||
<td>Memory Management Interrupt</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><b>BusFault_IRQn</b></td>
|
||||
<td>BusFault_Handler</td>
|
||||
<td>-11</td>
|
||||
<td> </td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
\if ARMv8M
|
||||
<td> </td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
\endif
|
||||
<td>Bus Fault Interrupt</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><b>UsageFault_IRQn</b></td>
|
||||
<td>UsageFault_Handler</td>
|
||||
<td>-10</td>
|
||||
<td> </td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
\if ARMv8M
|
||||
<td> </td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
\endif
|
||||
<td>Usage Fault Interrupt</td>
|
||||
</tr>
|
||||
\if ARMv8M
|
||||
<tr>
|
||||
<td><b>SecureFault_IRQn</b></td>
|
||||
<td>SecureFault_Handler</td>
|
||||
<td>-9</td>
|
||||
<td> </td>
|
||||
<td> </td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
<td>Secure Fault Interrupt</td>
|
||||
</tr>
|
||||
\endif
|
||||
<tr>
|
||||
<td><b>SVCall_IRQn</b></td>
|
||||
<td>SVC_Handler</td>
|
||||
<td>-5</td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
\if ARMv8M
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
\endif
|
||||
<td>SVC Interrupt </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><b>DebugMonitor_IRQn</b></td>
|
||||
<td>DebugMon_Handler</td>
|
||||
<td>-4</td>
|
||||
<td> </td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
\if ARMv8M
|
||||
<td> </td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
\endif
|
||||
<td>Debug Monitor Interrupt</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><b>PendSV_IRQn</b></td>
|
||||
<td>PendSV_Handler</td>
|
||||
<td>-2</td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
\if ARMv8M
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
\endif
|
||||
<td>Pend SV Interrupt</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><b>SysTick_IRQn</b></td>
|
||||
<td>SysTick_Handler</td>
|
||||
<td>-1</td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
\if ARMv8M
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
<td><img src="check.png" alt="available"></td>
|
||||
\endif
|
||||
<td>System Tick Interrupt</td>
|
||||
</tr>
|
||||
</table>
|
||||
|
||||
|
||||
Vector Table
|
||||
============
|
||||
The Vector Table defines the entry addresses of the processor exceptions and the
|
||||
device specific interrupts. It is typically located at the beginning of the
|
||||
program memory, however \ref using_VTOR_pg it can be relocated to RAM. The symbol
|
||||
<b>__Vectors</b> is the address of the vector table in the startup code and the
|
||||
register <b>SCB->VTOR</b> holds the start address of the vector table.
|
||||
|
||||
\if ARMv8M
|
||||
An Armv8-M implementation with TrustZone provides two vector tables:
|
||||
- vector table for Secure handlers
|
||||
- vector table for Non-Secure handlers
|
||||
|
||||
Refer to \ref Model_TrustZone for more information.
|
||||
\endif
|
||||
|
||||
Processor Exceptions
|
||||
--------------------
|
||||
At the beginning of the vector table, the initial stack value and the
|
||||
exception vectors of the processor are defined. The vector table below
|
||||
shows the exception vectors of a Armv8-M Mainline processor. Other processor
|
||||
variants may have fewer vectors.
|
||||
|
||||
\code
|
||||
__Vectors DCD __initial_sp ; Top of Stack initialization
|
||||
DCD Reset_Handler ; Reset Handler
|
||||
DCD NMI_Handler ; NMI Handler
|
||||
DCD HardFault_Handler ; Hard Fault Handler
|
||||
DCD MemManage_Handler ; MPU Fault Handler
|
||||
DCD BusFault_Handler ; Bus Fault Handler
|
||||
DCD UsageFault_Handler ; Usage Fault Handler
|
||||
DCD SecureFault_Handler ; Secure Fault Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD 0 ; Reserved
|
||||
DCD SVC_Handler ; SVC Handler
|
||||
DCD DebugMon_Handler ; Debug Monitor Handler
|
||||
DCD 0 ; Reserved
|
||||
DCD PendSV_Handler ; PendSV Handler
|
||||
DCD SysTick_Handler ; SysTick Handler
|
||||
\endcode
|
||||
|
||||
|
||||
Device Specific Vectors
|
||||
-----------------------
|
||||
Following the processor exception vectors, the vector table contains also the
|
||||
device specific interrupt vectors.
|
||||
|
||||
\code
|
||||
; device specific interrupts
|
||||
DCD WWDG_IRQHandler ; Window Watchdog
|
||||
DCD PVD_IRQHandler ; PVD through EXTI Line detect
|
||||
DCD TAMPER_IRQHandler ; Tamper
|
||||
\endcode
|
||||
|
||||
All device specific interrupts should have a default interrupt handler function that can
|
||||
be overwritten in user code. Below is an example for this default handler function.
|
||||
|
||||
\code
|
||||
Default_Handler PROC
|
||||
EXPORT WWDG_IRQHandler [WEAK]
|
||||
EXPORT PVD_IRQHandler [WEAK]
|
||||
EXPORT TAMPER_IRQHandler [WEAK]
|
||||
:
|
||||
:
|
||||
WWDG_IRQHandler
|
||||
PVD_IRQHandler
|
||||
TAMPER_IRQHandler
|
||||
:
|
||||
:
|
||||
B .
|
||||
ENDP
|
||||
\endcode
|
||||
|
||||
|
||||
The user application may simply define an interrupt handler function by using the handler name
|
||||
as shown below.
|
||||
|
||||
\code
|
||||
void WWDG_IRQHandler(void)
|
||||
{
|
||||
...
|
||||
}
|
||||
\endcode
|
||||
|
||||
NVIC Function Usage
|
||||
===================
|
||||
The code below shows the usage of various CMSIS NVIC functions with an LPC1700 device.
|
||||
|
||||
Code Example 1
|
||||
--------------
|
||||
\code
|
||||
#include "LPC17xx.h"
|
||||
|
||||
uint32_t priorityGroup; /* Variables to store priority group and priority */
|
||||
uint32_t priority;
|
||||
uint32_t preemptPriority;
|
||||
uint32_t subPriority;
|
||||
|
||||
int main (void) {
|
||||
NVIC_SetPriorityGrouping(5); /* Set priority group to 5:
|
||||
Bit[7..6] preempt priority Bits,
|
||||
Bit[5..3] subpriority Bits
|
||||
(valid for five priority bits) */
|
||||
|
||||
priorityGroup = NVIC_GetPriorityGrouping(); /* Get used priority grouping */
|
||||
|
||||
priority = NVIC_EncodePriority(priorityGroup, 1, 6); /* Encode priority with 6 for subpriority and 1 for preempt priority
|
||||
Note: priority depends on the used priority grouping */
|
||||
NVIC_SetPriority(UART0_IRQn, priority); /* Set new priority */
|
||||
|
||||
priority = NVIC_GetPriority(UART0_IRQn); /* Retrieve priority again */
|
||||
NVIC_DecodePriority(priority, priorityGroup, &preemptPriority, &subPriority);
|
||||
|
||||
while(1);
|
||||
}
|
||||
\endcode
|
||||
|
||||
|
||||
Code Example 2
|
||||
--------------
|
||||
\code
|
||||
#include "LPC17xx.h"
|
||||
|
||||
uint32_t active; /* Variable to store interrupt active state */
|
||||
|
||||
void TIMER0_IRQHandler(void) { /* Timer 0 interrupt handler */
|
||||
|
||||
if (LPC_TIM0->IR & (1 << 0)) { /* Check if interrupt for match channel 0 occurred */
|
||||
LPC_TIM0->IR |= (1 << 0); /* Acknowledge interrupt for match channel 0 occurred */
|
||||
}
|
||||
active = NVIC_GetActive(TIMER0_IRQn); /* Get interrupt active state of timer 0 */
|
||||
}
|
||||
|
||||
int main (void) {
|
||||
/* Set match channel register MR0 to 1 millisecond */
|
||||
LPC_TIM0->MR0 = (((SystemCoreClock / 1000) / 4) - 1); /* 1 ms? */
|
||||
|
||||
LPC_TIM0->MCR = (3 << 0); /* Enable interrupt and reset for match channel MR0 */
|
||||
NVIC_EnableIRQ(TIMER0_IRQn); /* Enable NVIC interrupt for timer 0 */
|
||||
LPC_TIM0->TCR = (1 << 0); /* Enable timer 0 */
|
||||
|
||||
while(1);
|
||||
}
|
||||
\endcode
|
||||
|
||||
|
||||
NVIC API Virtualization
|
||||
=======================
|
||||
The CMSIS-Core has provisions for overriding NVIC APIs as required for implementing
|
||||
secure systems that control access to peripherals and related interrupts.
|
||||
These overrides allow an operating system to control the access privileges of
|
||||
application code to critical interrupts.
|
||||
|
||||
The NVIC function virtualization is enabled with the following \#define symbols:
|
||||
- \ref CMSIS_NVIC_VIRTUAL enables overriding the CMSIS-Core (Cortex-M) NVIC functions.
|
||||
- \ref CMSIS_VECTAB_VIRTUAL enables overriding the CMSIS-Core (Cortex-M) interrupt vector table access functions.
|
||||
|
||||
*/
|
||||
|
||||
#define CMSIS_NVIC_VIRTUAL ///< Virtualization of the NVIC API
|
||||
/**
|
||||
\def CMSIS_NVIC_VIRTUAL
|
||||
When \ref CMSIS_NVIC_VIRTUAL is defined, the NVIC access functions in the table below must be implemented
|
||||
for virtualizing NVIC access. These functions should be implemented
|
||||
in a separate source module.
|
||||
The original CMSIS-Core __NVIC functions are always available independent of \ref CMSIS_NVIC_VIRTUAL.
|
||||
|
||||
NVIC Access Functions | CMSIS-Core Functions
|
||||
--------------------------|---------------------------------------------
|
||||
NVIC_EnableIRQ | __NVIC_EnableIRQ
|
||||
NVIC_GetEnableIRQ | __NVIC_GetEnableIRQ
|
||||
NVIC_DisableIRQ | __NVIC_DisableIRQ
|
||||
NVIC_GetPendingIRQ | __NVIC_GetPendingIRQ
|
||||
NVIC_SetPendingIRQ | __NVIC_SetPendingIRQ
|
||||
NVIC_ClearPendingIRQ | __NVIC_ClearPendingIRQ
|
||||
NVIC_GetActive | __NVIC_GetActive
|
||||
NVIC_SetPriority | __NVIC_SetPriority
|
||||
NVIC_GetPriority | __NVIC_GetPriority
|
||||
NVIC_SetPriorityGrouping | __NVIC_SetPriorityGrouping
|
||||
NVIC_GetPriorityGrouping | __NVIC_GetPriorityGrouping
|
||||
*/
|
||||
|
||||
#define CMSIS_VECTAB_VIRTUAL ///< Virtualization of interrupt vector table access functions
|
||||
/**
|
||||
|
||||
\def CMSIS_VECTAB_VIRTUAL
|
||||
When \ref CMSIS_NVIC_VIRTUAL is defined, the functions in the table below must be replaced
|
||||
to virtualize the API access functions to the interrupt vector table. The NVIC vector table API should be implemented
|
||||
in a separate source module. This allows, for example, alternate implementations to relocate the vector table from flash to RAM on the first vector table update.
|
||||
|
||||
The original CMSIS-Core functions are always available, but prefixed with __NVIC.
|
||||
|
||||
Interrupt Vector Table Access | CMSIS-Core Functions
|
||||
-------------------------------|---------------------------------------------
|
||||
NVIC_GetVector | __NVIC_GetVector
|
||||
NVIC_SetVector | __NVIC_SetVector
|
||||
|
||||
*/
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Definition of IRQn numbers
|
||||
|
||||
|
||||
The core exception enumeration names for IRQn values are defined in the \ref device_h_pg.
|
||||
|
||||
- Negative IRQn values represent processor core exceptions (internal interrupts).
|
||||
- Positive IRQn values represent device-specific exceptions (external interrupts).
|
||||
- The first device-specific interrupt has the IRQn value 0.
|
||||
|
||||
The table below describes the core exception names and their availability in various Cortex-M cores.
|
||||
*/
|
||||
typedef enum IRQn
|
||||
{
|
||||
/****** Cortex-M3 Processor Exceptions/Interrupt Numbers **************************/
|
||||
NonMaskableInt_IRQn = -14, ///< Exception 2: Non Maskable Interrupt
|
||||
HardFault_IRQn = -13, ///< Exception 3: Hard Fault Interrupt
|
||||
MemoryManagement_IRQn = -12, ///< Exception 4: Memory Management Interrupt [not on Cortex-M0 variants]
|
||||
BusFault_IRQn = -11, ///< Exception 5: Bus Fault Interrupt [not on Cortex-M0 variants]
|
||||
UsageFault_IRQn = -10, ///< Exception 6: Usage Fault Interrupt [not on Cortex-M0 variants]
|
||||
\if ARMv8M
|
||||
SecureFault_IRQn = -9, ///< Exception 7: Secure Fault Interrupt [only on Armv8-M]
|
||||
\endif
|
||||
SVCall_IRQn = -5, ///< Exception 11: SVC Interrupt
|
||||
DebugMonitor_IRQn = -4, ///< Exception 12: Debug Monitor Interrupt [not on Cortex-M0 variants]
|
||||
PendSV_IRQn = -2, ///< Exception 14: Pend SV Interrupt [not on Cortex-M0 variants]
|
||||
SysTick_IRQn = -1, ///< Exception 15: System Tick Interrupt
|
||||
/****** Device-specific Interrupt Numbers *****************************************/
|
||||
WWDG_STM_IRQn = 0, ///< Device Interrupt 0: Window WatchDog Interrupt
|
||||
PVD_STM_IRQn = 1, ///< Device Interrupt 1: PVD through EXTI Line detection Interrupt
|
||||
} IRQn_Type;
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Set priority grouping [not for Cortex-M0, Cortex-M0+, or SC000]
|
||||
|
||||
The function sets the priority grouping \em PriorityGroup using the required unlock sequence.
|
||||
\em PriorityGroup is assigned to the field PRIGROUP (register AIRCR[10:8]). This field
|
||||
determines the split of group priority from subpriority.
|
||||
Only values from 0..7 are used.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||
|
||||
\param [in] PriorityGroup Priority group
|
||||
|
||||
\remarks
|
||||
- not for Cortex-M0, Cortex-M0+, or SC000.
|
||||
- By default, priority group setting is zero.
|
||||
|
||||
\sa
|
||||
- \ref NVIC_GetPriorityGrouping; NVIC_SetPriority; SCB_Type
|
||||
- \ref ref_man_sec
|
||||
*/
|
||||
void NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\brief Read the priority grouping [not for Cortex-M0, Cortex-M0+, or SC000]
|
||||
|
||||
This function returns the priority grouping (flag PRIGROUP in AIRCR[10:8]).
|
||||
|
||||
\return Priority grouping field
|
||||
|
||||
\remarks
|
||||
- not for Cortex-M0, Cortex-M0+, or SC000.
|
||||
- By default, priority group setting is zero.
|
||||
|
||||
\sa
|
||||
- \ref NVIC_SetPriorityGrouping; NVIC_GetPriority; SCB_Type
|
||||
- \ref ref_man_sec
|
||||
|
||||
*/
|
||||
uint32_t NVIC_GetPriorityGrouping(void);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\brief Enable a device specific interrupt
|
||||
|
||||
This function enables the specified device specific interrupt \em IRQn.
|
||||
\em IRQn cannot be a negative value.
|
||||
|
||||
\param [in] IRQn Interrupt number
|
||||
|
||||
\remarks
|
||||
- IRQn must not be negative.
|
||||
- The registers that control the enabling and disabling of interrupts are called
|
||||
SETENA and CLRENA.
|
||||
- The number of supported interrupts depends on the implementation of the chip designer
|
||||
and can be read form the Interrupt Controller Type Register (ICTR) in granularities of 32:
|
||||
\n ICTR[4:0]
|
||||
- 0 - 32 interrupts supported
|
||||
- 1 - 64 interrupts supported
|
||||
- ...
|
||||
|
||||
\sa
|
||||
- \ref NVIC_DisableIRQ; SCnSCB_Type;
|
||||
- \ref ref_man_sec
|
||||
*/
|
||||
void NVIC_EnableIRQ(IRQn_Type IRQn);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\brief Get a device specific interrupt enable status
|
||||
|
||||
This function returns the interrupt enable status for the specified device specific interrupt \em IRQn.
|
||||
\em IRQn cannot be a negative value.
|
||||
|
||||
\param [in] IRQn Interrupt number
|
||||
|
||||
\returns
|
||||
- 0 Interrupt is not enabled
|
||||
- 1 Interrupt is enabled
|
||||
|
||||
\remarks
|
||||
- IRQn must not be negative.
|
||||
- The registers that control the enabling and disabling of interrupts are called SETENA and CLRENA.
|
||||
|
||||
\sa
|
||||
- \ref NVIC_EnableIRQ; NVIC_DisableIRQ;
|
||||
- \ref ref_man_sec
|
||||
*/
|
||||
uint32_t NVIC_GetEnableIRQ(IRQn_Type IRQn);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\brief Disable a device specific interrupt
|
||||
|
||||
This function disables the specified device specific interrupt \em IRQn.
|
||||
\em IRQn cannot be a negative value.
|
||||
|
||||
\param [in] IRQn Number of the external interrupt to disable
|
||||
|
||||
\remarks
|
||||
- IRQn must not be negative.
|
||||
- The registers that control the enabling and disabling of interrupts are called
|
||||
SETENA and CLRENA.
|
||||
|
||||
\sa
|
||||
- \ref NVIC_EnableIRQ
|
||||
- \ref ref_man_sec
|
||||
*/
|
||||
void NVIC_DisableIRQ(IRQn_Type IRQn);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\brief Get the pending device specific interrupt
|
||||
|
||||
This function returns the pending status of the specified device specific interrupt \em IRQn.
|
||||
|
||||
\param [in] IRQn Interrupt number
|
||||
|
||||
\returns
|
||||
- 0 Interrupt is not pending
|
||||
- 1 Interrupt is pending
|
||||
|
||||
\remarks
|
||||
- IRQn must not be negative.
|
||||
- The registers that control the status of interrupts are called SETPEND and CLRPEND.
|
||||
|
||||
\sa
|
||||
- \ref NVIC_SetPendingIRQ; NVIC_ClearPendingIRQ
|
||||
- \ref ref_man_sec
|
||||
*/
|
||||
uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\brief Set a device specific interrupt to pending
|
||||
|
||||
This function sets the pending bit for the specified device specific interrupt \em IRQn.
|
||||
\em IRQn cannot be a negative value.
|
||||
|
||||
\param [in] IRQn Interrupt number
|
||||
|
||||
\remarks
|
||||
- IRQn must not be negative.
|
||||
- The registers that control the status of interrupts are called SETPEND and CLRPEND.
|
||||
|
||||
\sa
|
||||
- \ref NVIC_GetPendingIRQ; NVIC_ClearPendingIRQ
|
||||
- \ref ref_man_sec
|
||||
*/
|
||||
void NVIC_SetPendingIRQ(IRQn_Type IRQn);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\brief Clear a device specific interrupt from pending
|
||||
|
||||
This function removes the pending state of the specified device specific interrupt \em IRQn.
|
||||
\em IRQn cannot be a negative number.
|
||||
|
||||
\param [in] IRQn Interrupt number
|
||||
|
||||
\remarks
|
||||
- IRQn must not be negative.
|
||||
- The registers that control the status of interrupts are called SETPEND and CLRPEND.
|
||||
- An interrupt can have the status pending though it is not active.
|
||||
|
||||
\sa
|
||||
- \ref NVIC_SetPendingIRQ; NVIC_GetPendingIRQ
|
||||
- \ref ref_man_sec
|
||||
*/
|
||||
void NVIC_ClearPendingIRQ(IRQn_Type IRQn);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\brief Get the device specific interrupt active status [not for Cortex-M0, Cortex-M0+, or SC000]
|
||||
|
||||
This function reads the Interrupt Active Register (NVIC_IABR0-NVIC_IABR7) in NVIC and
|
||||
returns the active bit of the interrupt \em IRQn.
|
||||
|
||||
\param [in] IRQn Interrupt number
|
||||
|
||||
\returns
|
||||
- 0 Interrupt is not active
|
||||
- 1 Interrupt is active, or active and pending
|
||||
|
||||
\remarks
|
||||
- not for Cortex-M0, Cortex-M0+, or SC000.
|
||||
- IRQn must not be negative.
|
||||
- Each external interrupt has an active status bit. When the processor starts the interrupt
|
||||
handler the bit is set to 1 and cleared when the interrupt return is executed.
|
||||
- When an ISR is preempted and the processor executes another interrupt handler, the
|
||||
previous interrupt is still defined as active.
|
||||
|
||||
\sa
|
||||
- \ref ref_man_sec
|
||||
|
||||
*/
|
||||
uint32_t NVIC_GetActive(IRQn_Type IRQn);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\brief Set the priority for an interrupt
|
||||
|
||||
Sets the priority for the interrupt specified by \em IRQn.\em IRQn can can specify any
|
||||
device specific interrupt, or processor exception. The \em priority specifies
|
||||
the interrupt priority value, whereby lower values indicate a higher priority. The default
|
||||
priority is 0 for every interrupt. This is the highest possible priority.
|
||||
|
||||
The priority cannot be set for every core interrupt. HardFault and NMI have a fixed (negative)
|
||||
priority that is higher than any configurable exception or interrupt.
|
||||
|
||||
\param [in] IRQn Interrupt Number
|
||||
\param [in] priority Priority to set
|
||||
|
||||
\remarks
|
||||
- The number of priority levels is configurable and depends on the implementation of the
|
||||
chip designer. To determine the number of bits implemented for interrupt priority-level
|
||||
registers, write \em 0xFF to one of the priority-level register, then read back the value. For
|
||||
example, if the minimum number of 3 bits have been implemented, the read-back value is \em 0xE0.
|
||||
- Writes to unimplemented bits are ignored.
|
||||
- <b>For Cortex-M0</b>:
|
||||
- Dynamic switching of interrupt priority levels is not supported. The priority level of
|
||||
an interrupt should not be changed after it has been enabled.
|
||||
- Supports 0 to 192 priority levels.
|
||||
- Priority-level registers are 2 bit wide, occupying the two MSBs.
|
||||
Each Interrupt Priority Level Register is 1-byte wide.
|
||||
- <b>For Cortex-M3, Cortex-M4, and Cortex-M7</b>:
|
||||
- Dynamic switching of interrupt priority levels is supported.
|
||||
- Supports 0 to 255 priority levels.
|
||||
- Priority-level registers have a maximum width of 8 bits and a minimum of 3 bits.
|
||||
Each register can be further divided into preempt priority level and subpriority level.
|
||||
|
||||
\sa
|
||||
- \ref NVIC_GetPriority; NVIC_SetPriorityGrouping; __set_BASEPRI;
|
||||
- \ref ref_man_sec
|
||||
*/
|
||||
void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\brief Get the priority of an interrupt
|
||||
|
||||
This function reads the priority for the specified interrupt \em IRQn. \em IRQn can can specify
|
||||
any device specific interrupt, or processor exception.
|
||||
|
||||
The returned priority value is automatically aligned to the implemented
|
||||
priority bits of the microcontroller.
|
||||
|
||||
\param [in] IRQn Interrupt number
|
||||
|
||||
\returns Interrupt priority
|
||||
|
||||
\remarks
|
||||
- Each external interrupt has an associated priority-level register.
|
||||
- Unimplemented bits are read as zero.
|
||||
|
||||
\sa
|
||||
- \ref NVIC_SetPriority; NVIC_GetPriorityGrouping; __get_BASEPRI;
|
||||
- \ref ref_man_sec
|
||||
*/
|
||||
uint32_t NVIC_GetPriority(IRQn_Type IRQn);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\brief Encodes Priority [not for Cortex-M0, Cortex-M0+, or SC000]
|
||||
|
||||
This function encodes the priority for an interrupt with the priority group \em PriorityGroup,
|
||||
preemptive priority value \em PreemptPriority, and subpriority value \em SubPriority.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||
|
||||
\param [in] PriorityGroup Priority group
|
||||
\param [in] PreemptPriority Preemptive priority value (starting from 0)
|
||||
\param [in] SubPriority Subpriority value (starting from 0)
|
||||
|
||||
\returns Encoded priority for the interrupt
|
||||
|
||||
|
||||
\remarks
|
||||
- not for Cortex-M0, Cortex-M0+, or SC000.
|
||||
|
||||
\sa
|
||||
- \ref NVIC_DecodePriority; NVIC_SetPriority;
|
||||
- \ref ref_man_sec
|
||||
*/
|
||||
uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\brief Decode the interrupt priority [not for Cortex-M0, Cortex-M0+, or SC000]
|
||||
|
||||
This function decodes an interrupt priority value with the priority group \em PriorityGroup to
|
||||
preemptive priority value \em pPreemptPriority and subpriority value \em pSubPriority.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||
|
||||
\param [in] Priority Priority
|
||||
\param [in] PriorityGroup Priority group
|
||||
\param [out] *pPreemptPriority Preemptive priority value (starting from 0)
|
||||
\param [out] *pSubPriority Subpriority value (starting from 0)
|
||||
|
||||
|
||||
\remarks
|
||||
- not for Cortex-M0, Cortex-M0+, or SC000.
|
||||
|
||||
\sa
|
||||
- \ref NVIC_EncodePriority; NVIC_GetPriority; NVIC_GetPriorityGrouping;
|
||||
- \ref ref_man_sec
|
||||
*/
|
||||
void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\brief Read Interrupt Vector [not for Cortex-M0, SC000]
|
||||
|
||||
This function allows to read the address of an interrupt handler function.
|
||||
|
||||
\param [in] IRQn Interrupt number
|
||||
|
||||
\returns Address of interrupt handler function
|
||||
|
||||
\remarks
|
||||
- For using this function with Cortex-M0+ processor based devices, the SBC->VTOR register must be implemented.
|
||||
|
||||
\sa
|
||||
- \ref NVIC_SetVector
|
||||
- \ref ref_man_sec
|
||||
*/
|
||||
uint32_t NVIC_GetVector(IRQn_Type IRQn);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\brief Modify Interrupt Vector [not for Cortex-M0, SC000]
|
||||
|
||||
This function allows to change the address of an interrupt handler function.
|
||||
|
||||
\param [in] IRQn Interrupt number
|
||||
\param [in] vector Address of new interrupt handler function
|
||||
|
||||
\remarks
|
||||
- Usage of this function requires vector relocation to RAM. Refer to \ref using_VTOR_pg for more information.
|
||||
- For using this function with Cortex-M0+ processor based devices, the SBC->VTOR register must be implemented.
|
||||
|
||||
\sa
|
||||
- \ref NVIC_GetVector
|
||||
- \ref ref_man_sec
|
||||
*/
|
||||
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\brief Reset the system
|
||||
|
||||
This function requests a system reset by setting the SYSRESETREQ flag in the AIRCR register.
|
||||
|
||||
\remarks
|
||||
- In most microcontroller designs, setting the SYSRESETREQ flag resets the processor and
|
||||
most parts of the system, but should not affect the debug system.
|
||||
|
||||
\sa
|
||||
- \ref ref_man_sec
|
||||
*/
|
||||
void NVIC_SystemReset (void);
|
||||
|
||||
/**
|
||||
\cond (ARMv8M)
|
||||
*/
|
||||
/**
|
||||
\brief Get Interrupt Target State
|
||||
\details Reads the interrupt target field from the non-secure NVIC when in secure state.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
\returns
|
||||
- 0 if interrupt is assigned to Secure
|
||||
- 1 if interrupt is assigned to Non Secure
|
||||
\remarks
|
||||
- Only available for Armv8-M in secure state.
|
||||
|
||||
\sa
|
||||
- \ref NVIC_ClearTargetState; NVIC_SetTargetState;
|
||||
*/
|
||||
uint32_t NVIC_GetTargetState(IRQn_Type IRQn);
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Target State
|
||||
\details Sets the interrupt target field in the non-secure NVIC when in secure state.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
\returns
|
||||
- 0 if interrupt is assigned to Secure
|
||||
- 1 if interrupt is assigned to Non Secure
|
||||
\remarks
|
||||
- Only available for Armv8-M in secure state.
|
||||
|
||||
\sa
|
||||
- \ref NVIC_ClearTargetState; NVIC_GetTargetState;
|
||||
*/
|
||||
uint32_t NVIC_SetTargetState(IRQn_Type IRQn);
|
||||
|
||||
/**
|
||||
\brief Clear Interrupt Target State
|
||||
\details Clears the interrupt target field in the non-secure NVIC when in secure state.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
\returns
|
||||
- 0 if interrupt is assigned to Secure
|
||||
- 1 if interrupt is assigned to Non Secure
|
||||
\remarks
|
||||
- Only available for Armv8-M in secure state.
|
||||
|
||||
\sa
|
||||
- \ref NVIC_GetTargetState; NVIC_SetTargetState;
|
||||
*/
|
||||
uint32_t NVIC_ClearTargetState(IRQn_Type IRQn);
|
||||
|
||||
/**
|
||||
\endcond
|
||||
*/
|
||||
|
||||
/*@} end of NVIC_gr */
|
||||
|
||||
|
||||
428
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_PMU8.txt
vendored
Normal file
428
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_PMU8.txt
vendored
Normal file
@@ -0,0 +1,428 @@
|
||||
/**
|
||||
\defgroup pmu8_functions PMU Functions for Armv8.1-M
|
||||
\brief Functions that relate to the Performance Monitoring Unit.
|
||||
\details
|
||||
The following functions support the Performance Monitoring Unit (PMU) that is available on the Cortex-M55/M85 processors.
|
||||
|
||||
The PMU is used to monitor events that occur during run-time of an application.
|
||||
|
||||
<b>Example:</b>
|
||||
\code
|
||||
// Initialize counter variables
|
||||
|
||||
unsigned int cycle_count = 0;
|
||||
unsigned int l1_dcache_miss_count = 0;
|
||||
unsigned int instructions_retired_count = 0;
|
||||
|
||||
// Enable the PMU
|
||||
// Note: Before using the PMU, software needs to ensure
|
||||
// that trace is enabled via the Debug Exception Monitor Control Register, DEMCR:
|
||||
// CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
|
||||
|
||||
ARM_PMU_Enable();
|
||||
|
||||
// Configure Event Counter Register 0 to count instructions retired
|
||||
// Configure Event Counter Register 1 to count L1 D-Cache misses
|
||||
|
||||
ARM_PMU_Set_EVTYPER(0, ARM_PMU_INST_RETIRED);
|
||||
ARM_PMU_Set_EVTYPER(1, ARM_PMU_L1D_CACHE_MISS_RD);
|
||||
|
||||
// Reset Event Counters and Cycle Counter
|
||||
|
||||
ARM_PMU_EVCNTR_ALL_Reset();
|
||||
ARM_PMU_CYCCNT_Reset();
|
||||
|
||||
// Start incrementing Cycle Count Register and Event Counter Registers 0 & 1
|
||||
|
||||
ARM_PMU_CNTR_Enable(PMU_CNTENSET_CCNTR_ENABLE_Msk|PMU_CNTENSET_CNT0_ENABLE_Msk|PMU_CNTENSET_CNT1_ENABLE_Msk);
|
||||
|
||||
// Code you want to measure here
|
||||
|
||||
// Stop incrementing Cycle Count Register and Event Counter Registers 0 & 1
|
||||
|
||||
ARM_PMU_CNTR_Disable(PMU_CNTENCLR_CCNTR_ENABLE_Msk|PMU_CNTENCLR_CNT0_ENABLE_Msk|PMU_CNTENCLR_CNT1_ENABLE_Msk);
|
||||
|
||||
// Get cycle count, number of instructions retired and number of L1 D-Cache misses (on read)
|
||||
|
||||
cycle_count = cycle_count + ARM_PMU_Get_CCNTR();
|
||||
instructions_retired_count = instructions_retired_count + ARM_PMU_Get_EVCNTR(0);
|
||||
l1_dcache_miss_count = l1_dcache_miss_count + ARM_PMU_Get_EVCNTR(1); // Note: D-Cache must be enabled using
|
||||
// SCB_EnableDCache() for meaningful result.
|
||||
\endcode
|
||||
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\defgroup pmu8_events_armv81 PMU Events for Armv8.1-M
|
||||
\ingroup pmu8_functions
|
||||
\brief IDs for Armv8.1-M architecture defined events.
|
||||
\details
|
||||
These events are available on all Armv8.1-M devices including a PMU.
|
||||
@{
|
||||
*/
|
||||
|
||||
#define ARM_PMU_SW_INCR 0x0000 /*!< \brief Software update to the PMU_SWINC register, architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< \brief L1 I-Cache refill */
|
||||
#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< \brief L1 D-Cache refill */
|
||||
#define ARM_PMU_L1D_CACHE 0x0004 /*!< \brief L1 D-Cache access */
|
||||
#define ARM_PMU_LD_RETIRED 0x0006 /*!< \brief Memory-reading instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_ST_RETIRED 0x0007 /*!< \brief Memory-writing instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_INST_RETIRED 0x0008 /*!< \brief Instruction architecturally executed */
|
||||
#define ARM_PMU_EXC_TAKEN 0x0009 /*!< \brief Exception entry */
|
||||
#define ARM_PMU_EXC_RETURN 0x000A /*!< \brief Exception return instruction architecturally executed and the condition code check pass */
|
||||
#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< \brief Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< \brief Immediate branch architecturally executed */
|
||||
#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< \brief Function return instruction architecturally executed and the condition code check pass */
|
||||
#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< \brief Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< \brief Mispredicted or not predicted branch speculatively executed */
|
||||
#define ARM_PMU_CPU_CYCLES 0x0011 /*!< \brief Cycle */
|
||||
#define ARM_PMU_BR_PRED 0x0012 /*!< \brief Predictable branch speculatively executed */
|
||||
#define ARM_PMU_MEM_ACCESS 0x0013 /*!< \brief Data memory access */
|
||||
#define ARM_PMU_L1I_CACHE 0x0014 /*!< \brief Level 1 instruction cache access */
|
||||
#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< \brief Level 1 data cache write-back */
|
||||
#define ARM_PMU_L2D_CACHE 0x0016 /*!< \brief Level 2 data cache access */
|
||||
#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< \brief Level 2 data cache refill */
|
||||
#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< \brief Level 2 data cache write-back */
|
||||
#define ARM_PMU_BUS_ACCESS 0x0019 /*!< \brief Bus access */
|
||||
#define ARM_PMU_MEMORY_ERROR 0x001A /*!< \brief Local memory error */
|
||||
#define ARM_PMU_INST_SPEC 0x001B /*!< \brief Instruction speculatively executed */
|
||||
#define ARM_PMU_BUS_CYCLES 0x001D /*!< \brief Bus cycles */
|
||||
#define ARM_PMU_CHAIN 0x001E /*!< \brief For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */
|
||||
#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< \brief Level 1 data cache allocation without refill */
|
||||
#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< \brief Level 2 data cache allocation without refill */
|
||||
#define ARM_PMU_BR_RETIRED 0x0021 /*!< \brief Branch instruction architecturally executed */
|
||||
#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< \brief Mispredicted branch instruction architecturally executed */
|
||||
#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< \brief No operation issued because of the frontend */
|
||||
#define ARM_PMU_STALL_BACKEND 0x0024 /*!< \brief No operation issued because of the backend */
|
||||
#define ARM_PMU_L2I_CACHE 0x0027 /*!< \brief Level 2 instruction cache access */
|
||||
#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< \brief Level 2 instruction cache refill */
|
||||
#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< \brief Level 3 data cache allocation without refill */
|
||||
#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< \brief Level 3 data cache refill */
|
||||
#define ARM_PMU_L3D_CACHE 0x002B /*!< \brief Level 3 data cache access */
|
||||
#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< \brief Level 3 data cache write-back */
|
||||
#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< \brief Last level data cache read */
|
||||
#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< \brief Last level data cache read miss */
|
||||
#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< \brief Level 1 data cache read miss */
|
||||
#define ARM_PMU_OP_COMPLETE 0x003A /*!< \brief Operation retired */
|
||||
#define ARM_PMU_OP_SPEC 0x003B /*!< \brief Operation speculatively executed */
|
||||
#define ARM_PMU_STALL 0x003C /*!< \brief Stall cycle for instruction or operation not sent for execution */
|
||||
#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< \brief Stall cycle for instruction or operation not sent for execution due to pipeline backend */
|
||||
#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< \brief Stall cycle for instruction or operation not sent for execution due to pipeline frontend */
|
||||
#define ARM_PMU_STALL_OP 0x003F /*!< \brief Instruction or operation slots not occupied each cycle */
|
||||
#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< \brief Level 1 data cache read */
|
||||
#define ARM_PMU_LE_RETIRED 0x0100 /*!< \brief Loop end instruction executed */
|
||||
#define ARM_PMU_LE_SPEC 0x0101 /*!< \brief Loop end instruction speculatively executed */
|
||||
#define ARM_PMU_BF_RETIRED 0x0104 /*!< \brief Branch future instruction architecturally executed and condition code check pass */
|
||||
#define ARM_PMU_BF_SPEC 0x0105 /*!< \brief Branch future instruction speculatively executed and condition code check pass */
|
||||
#define ARM_PMU_LE_CANCEL 0x0108 /*!< \brief Loop end instruction not taken */
|
||||
#define ARM_PMU_BF_CANCEL 0x0109 /*!< \brief Branch future instruction not taken */
|
||||
#define ARM_PMU_SE_CALL_S 0x0114 /*!< \brief Call to secure function, resulting in Security state change */
|
||||
#define ARM_PMU_SE_CALL_NS 0x0115 /*!< \brief Call to non-secure function, resulting in Security state change */
|
||||
#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< \brief DWT comparator 0 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< \brief DWT comparator 1 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< \brief DWT comparator 2 match */
|
||||
#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< \brief DWT comparator 3 match */
|
||||
#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< \brief MVE instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< \brief MVE instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< \brief MVE floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< \brief MVE floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< \brief MVE half-precision floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< \brief MVE half-precision floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< \brief MVE single-precision floating-point instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< \brief MVE single-precision floating-point instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< \brief MVE floating-point multiply or multiply-accumulate instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< \brief MVE floating-point multiply or multiply-accumulate instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< \brief MVE integer instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< \brief MVE integer instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< \brief MVE multiply or multiply-accumulate instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< \brief MVE multiply or multiply-accumulate instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< \brief MVE load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< \brief MVE load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< \brief MVE load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< \brief MVE load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< \brief MVE store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< \brief MVE store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< \brief MVE contiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< \brief MVE contiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< \brief MVE contiguous load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< \brief MVE contiguous load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< \brief MVE contiguous store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< \brief MVE contiguous store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< \brief MVE non-contiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< \brief MVE non-contiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< \brief MVE non-contiguous load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< \brief MVE non-contiguous load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< \brief MVE non-contiguous store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< \brief MVE non-contiguous store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< \brief MVE memory instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< \brief MVE memory instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< \brief MVE memory load instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< \brief MVE memory load instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< \brief MVE memory store instruction targeting multiple registers architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< \brief MVE memory store instruction targeting multiple registers speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< \brief MVE unaligned memory load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< \brief MVE unaligned memory load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< \brief MVE unaligned load instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< \brief MVE unaligned load instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< \brief MVE unaligned store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< \brief MVE unaligned store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< \brief MVE unaligned noncontiguous load or store instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< \brief MVE unaligned noncontiguous load or store instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< \brief MVE vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< \brief MVE vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< \brief MVE floating-point vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< \brief MVE floating-point vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< \brief MVE integer vector reduction instruction architecturally executed */
|
||||
#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< \brief MVE integer vector reduction instruction speculatively executed */
|
||||
#define ARM_PMU_MVE_PRED 0x02B8 /*!< \brief Cycles where one or more predicated beats architecturally executed */
|
||||
#define ARM_PMU_MVE_STALL 0x02CC /*!< \brief Stall cycles caused by an MVE instruction */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< \brief Stall cycles caused by an MVE instruction because of resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< \brief Stall cycles caused by an MVE instruction because of memory resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< \brief Stall cycles caused by an MVE instruction because of floating-point resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< \brief Stall cycles caused by an MVE instruction because of integer resource conflicts */
|
||||
#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< \brief Stall cycles caused by an MVE chain break */
|
||||
#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< \brief Stall cycles caused by MVE register dependency */
|
||||
#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< \brief Instruction TCM access */
|
||||
#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< \brief Data TCM access */
|
||||
#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< \brief ETM external output 0 */
|
||||
#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< \brief ETM external output 1 */
|
||||
#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< \brief ETM external output 2 */
|
||||
#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< \brief ETM external output 3 */
|
||||
#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< \brief Cross-trigger Interface output trigger 4 */
|
||||
#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< \brief Cross-trigger Interface output trigger 5 */
|
||||
#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< \brief Cross-trigger Interface output trigger 6 */
|
||||
#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< \brief Cross-trigger Interface output trigger 7 */
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
\defgroup pmu8_events_armcm55 PMU Events for Cortex-M55
|
||||
\ingroup pmu8_functions
|
||||
\brief IDs for additional events defined for Cortex-M55.
|
||||
\details
|
||||
These events are available on a Cortex-M55 device including a PMU.
|
||||
@{
|
||||
*/
|
||||
|
||||
#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< \brief Any ECC error */
|
||||
#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< \brief Any fatal ECC error */
|
||||
#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< \brief Any ECC error in the data cache */
|
||||
#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< \brief Any ECC error in the instruction cache */
|
||||
#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< \brief Any fatal ECC error in the data cache */
|
||||
#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< \brief Any fatal ECC error in the instruction cache*/
|
||||
#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< \brief Any ECC error in the DTCM */
|
||||
#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< \brief Any ECC error in the ITCM */
|
||||
#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< \brief Any fatal ECC error in the DTCM */
|
||||
#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< \brief Any fatal ECC error in the ITCM */
|
||||
#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< \brief A prefetcher starts a line-fill */
|
||||
#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< \brief A prefetcher stops prefetching */
|
||||
#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< \brief A linefill triggered by a prefetcher has been dropped because of lack of buffering */
|
||||
#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< \brief No write-allocate mode entry */
|
||||
#define ARMCM55_PMU_NWAMODE 0xC201 /*!< \brief Write-allocate store is not allocated into the data cache due to no-write-allocate mode */
|
||||
#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< \brief Read or write access on the S-AHB interface to the TCM */
|
||||
#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< \brief Read or write access on the S-AHB interface to the TCM */
|
||||
#define ARMCM55_PMU_PAHB_ACCESS 0xC301 /*!< \brief Read or write access on the P-AHB interface */
|
||||
#define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302 /*!< \brief Any beat access to M-AXI write interface */
|
||||
#define ARMCM55_PMU_AXI_READ_ACCESS 0xC303 /*!< \brief Any beat access to M-AXI read interface */
|
||||
#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< \brief Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */
|
||||
#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< \brief Denial of Service timeout has fired three times and blocked the LSU to force forward progress */
|
||||
|
||||
/** @} */
|
||||
|
||||
/**
|
||||
\defgroup pmu8_events_armcm85 PMU Events for Cortex-M85
|
||||
\ingroup pmu8_functions
|
||||
\brief IDs for additional events defined for Cortex-M85.
|
||||
\details
|
||||
These events are available on a Cortex-M85 device including a PMU.
|
||||
@{
|
||||
*/
|
||||
|
||||
#define ARMCM85_PMU_ECC_ERR 0xC000 /*!< \brief Any ECC error */
|
||||
#define ARMCM85_PMU_ECC_ERR_MBIT 0xC001 /*!< \brief Any multi-bit ECC error */
|
||||
#define ARMCM85_PMU_ECC_ERR_DCACHE 0xC010 /*!< \brief Any ECC error in the data cache */
|
||||
#define ARMCM85_PMU_ECC_ERR_ICACHE 0xC011 /*!< \brief Any ECC error in the instruction cache */
|
||||
#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< \brief Any multi-bit ECC error in the data cache */
|
||||
#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< \brief Any multi-biy ECC error in the instruction cache*/
|
||||
#define ARMCM85_PMU_ECC_ERR_DTCM 0xC020 /*!< \brief Any ECC error in the DTCM */
|
||||
#define ARMCM85_PMU_ECC_ERR_ITCM 0xC021 /*!< \brief Any ECC error in the ITCM */
|
||||
#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< \brief Any multi-bit ECC error in the DTCM */
|
||||
#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< \brief Any multi-bit ECC error in the ITCM */
|
||||
#define ARMCM85_PMU_PF_LINEFILL 0xC100 /*!< \brief A prefetcher starts a line-fill */
|
||||
#define ARMCM85_PMU_PF_CANCEL 0xC101 /*!< \brief A prefetcher stops prefetching */
|
||||
#define ARMCM85_PMU_PF_DROP_LINEFILL 0xC102 /*!< \brief A linefill triggered by a prefetcher has been dropped because of lack of buffering */
|
||||
#define ARMCM85_PMU_NWAMODE_ENTER 0xC200 /*!< \brief No write-allocate mode entry */
|
||||
#define ARMCM85_PMU_NWAMODE 0xC201 /*!< \brief Write-allocate store is not allocated into the data cache due to no-write-allocate mode */
|
||||
#define ARMCM85_PMU_SAHB_ACCESS 0xC300 /*!< \brief Read or write access on the S-AHB interface to the TCM */
|
||||
#define ARMCM85_PMU_PAHB_ACCESS 0xC301 /*!< \brief Read or write access on the P-AHB interface */
|
||||
#define ARMCM85_PMU_AXI_WRITE_ACCESS 0xC302 /*!< \brief Any beat access to M-AXI write interface */
|
||||
#define ARMCM85_PMU_AXI_READ_ACCESS 0xC303 /*!< \brief Any beat access to M-AXI read interface */
|
||||
#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< \brief Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */
|
||||
#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< \brief Denial of Service timeout has fired three times and blocked the LSU to force forward progress */
|
||||
|
||||
/** @} */
|
||||
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Performance Monitoring Unit (PMU).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) \brief PMU Event Counter Registers \details Two up to 31 event counters, see device specific \ref __PMU_NUM_EVENTCNT */
|
||||
// uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT];
|
||||
__IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) \brief PMU Cycle Counter Register */
|
||||
// uint32_t RESERVED1[224];
|
||||
__IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) \brief PMU Event Type and Filter Registers \details Two up to 31 event counters, see device specific \ref __PMU_NUM_EVENTCNT */
|
||||
// uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT];
|
||||
__IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) \brief PMU Cycle Counter Filter Register */
|
||||
// uint32_t RESERVED3[480];
|
||||
__IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) \brief PMU Count Enable Set Register */
|
||||
// uint32_t RESERVED4[7];
|
||||
__IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) \brief PMU Count Enable Clear Register */
|
||||
// uint32_t RESERVED5[7];
|
||||
__IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) \brief PMU Interrupt Enable Set Register */
|
||||
// uint32_t RESERVED6[7];
|
||||
__IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) \brief PMU Interrupt Enable Clear Register */
|
||||
// uint32_t RESERVED7[7];
|
||||
__IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) \brief PMU Overflow Flag Status Clear Register */
|
||||
// uint32_t RESERVED8[7];
|
||||
__IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) \brief PMU Software Increment Register */
|
||||
// uint32_t RESERVED9[7];
|
||||
__IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) \brief PMU Overflow Flag Status Set Register */
|
||||
// uint32_t RESERVED10[79];
|
||||
__IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) \brief PMU Type Register */
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) \brief PMU Control Register */
|
||||
// uint32_t RESERVED11[108];
|
||||
__IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) \brief PMU Authentication Status Register */
|
||||
__IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) \brief PMU Device Architecture Register */
|
||||
// uint32_t RESERVED12[4];
|
||||
__IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) \brief PMU Device Type Register */
|
||||
__IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) \brief PMU Peripheral Identification Register 4 */
|
||||
// uint32_t RESERVED13[3];
|
||||
__IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) \brief PMU Peripheral Identification Register 0 */
|
||||
__IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) \brief PMU Peripheral Identification Register 1 */
|
||||
__IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) \brief PMU Peripheral Identification Register 2 */
|
||||
__IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) \brief PMU Peripheral Identification Register 3 */
|
||||
// uint32_t RESERVED14[3];
|
||||
__IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) \brief PMU Component Identification Register 0 */
|
||||
__IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) \brief PMU Component Identification Register 1 */
|
||||
__IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) \brief PMU Component Identification Register 2 */
|
||||
__IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) \brief PMU Component Identification Register 3 */
|
||||
} PMU_Type;
|
||||
|
||||
/**
|
||||
\brief PMU configuration struct
|
||||
\details
|
||||
This macro can be used to access the PMU registers, directly. For the common tasks
|
||||
one should prefer using the control functions.
|
||||
|
||||
Example:
|
||||
<b>Example:</b>
|
||||
\code
|
||||
PMU->CTRL |= PMU_CTRL_ENABLE_Msk; // Enable PMU
|
||||
\endcode
|
||||
*/
|
||||
#define PMU
|
||||
|
||||
/**
|
||||
\brief Enable the PMU
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Enable(void);
|
||||
|
||||
/**
|
||||
\brief Disable the PMU
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Disable(void);
|
||||
|
||||
/**
|
||||
\brief Set event to count for PMU event counter
|
||||
\param [in] num Event counter (0-30) to configure
|
||||
\param [in] type Event to count
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type);
|
||||
|
||||
/**
|
||||
\brief Reset cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void);
|
||||
|
||||
/**
|
||||
\brief Reset all event counters
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void);
|
||||
|
||||
/**
|
||||
\brief Enable counters
|
||||
\param [in] mask Counters to enable
|
||||
\note Enables one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask);
|
||||
|
||||
/**
|
||||
\brief Disable counters
|
||||
\param [in] mask Counters to enable
|
||||
\note Disables one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask);
|
||||
|
||||
/**
|
||||
\brief Read cycle counter
|
||||
\return Cycle count
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void);
|
||||
|
||||
/**
|
||||
\brief Read event counter
|
||||
\param [in] num Event counter (0-30) to read
|
||||
\return Event count
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num);
|
||||
|
||||
/**
|
||||
\brief Read counter overflow status
|
||||
\return Counter overflow status bits for the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void);
|
||||
|
||||
/**
|
||||
\brief Clear counter overflow status
|
||||
\param [in] mask Counter overflow status bits to clear
|
||||
\note Clears overflow status bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask);
|
||||
|
||||
/**
|
||||
\brief Enable counter overflow interrupt request
|
||||
\param [in] mask Counter overflow interrupt request bits to set
|
||||
\note Sets overflow interrupt request bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask);
|
||||
|
||||
/**
|
||||
\brief Disable counter overflow interrupt request
|
||||
\param [in] mask Counter overflow interrupt request bits to clear
|
||||
\note Clears overflow interrupt request bits for one or more of the following:
|
||||
- event counters (0-30)
|
||||
- cycle counter
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask);
|
||||
|
||||
/**
|
||||
\brief Software increment event counter
|
||||
\param [in] mask Counters to increment
|
||||
\note Software increment bits for one or more event counters (0-30)
|
||||
*/
|
||||
__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask);
|
||||
|
||||
/** @} */
|
||||
231
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_Peripheral.txt
vendored
Normal file
231
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_Peripheral.txt
vendored
Normal file
@@ -0,0 +1,231 @@
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\defgroup peripheral_gr Peripheral Access
|
||||
\brief Naming conventions and optional features for accessing peripherals.
|
||||
\details
|
||||
|
||||
The section below describes the naming conventions, requirements, and optional features for accessing device specific peripherals.
|
||||
Most of the rules also apply to the core peripherals. The \ref device_h_pg contains typically these definition and also includes
|
||||
the core specific header files.
|
||||
|
||||
\ifnot FuSaRTS
|
||||
The definitions for \ref peripheral_gr can be generated using the <a href="../../SVD/html/index.html"><b>CMSIS-SVD</b></a> System View Description for Peripherals.
|
||||
Refer to <a href="../../SVD/html/svd_SVDConv_pg.html"><b>SVDConv.exe</b></a> for more information.
|
||||
\endif
|
||||
|
||||
Each peripheral provides a data type definition with a name that is composed of:
|
||||
- an optional prefix <b><<i>device abbreviation></i>_</b>
|
||||
- <b><<i>peripheral name</i>></b>
|
||||
- postfix \b _Type or \b _TypeDef to identify a type definition.
|
||||
|
||||
Examples:
|
||||
- \b UART_TypeDef for the peripheral \b UART.
|
||||
- \b LPC_UART_TypeDef for the device family \b LPC and the peripheral \b UART.
|
||||
|
||||
The data type definition uses standard C data types defined by the ANSI C header file <stdint.h>.
|
||||
|
||||
- IO Type Qualifiers are used to specify the access to peripheral variables.
|
||||
IO Type Qualifier | Type | Description
|
||||
:------------------|:----------------|:------------
|
||||
\b __IM | Struct member | Defines 'read only' permissions
|
||||
\b __OM | Struct member | Defines 'write only' permissions
|
||||
\b __IOM | Struct member | Defines 'read / write' permissions
|
||||
\b __I | Scalar variable | Defines 'read only' permissions
|
||||
\b __O | Scalar variable | Defines 'write only' permissions
|
||||
\b __IO | Scalar variable | Defines 'read / write' permissions
|
||||
|
||||
\note
|
||||
\b __IM, \b __OM, \b __IOM are added in CMSIS-Core V4.20 to enhance support for C++. Prior version used \b __I, \b __O, \b __IO also for struct member definitions.
|
||||
|
||||
The typedef <b>\<<i>device abbreviation</i>\>_UART_TypeDef</b> shown below defines the generic register layout for all UART channels in a device.
|
||||
|
||||
\code
|
||||
typedef struct
|
||||
{
|
||||
union {
|
||||
__IM uint8_t RBR; /* Offset: 0x000 (R/ ) Receiver Buffer Register */
|
||||
__OM uint8_t THR; /* Offset: 0x000 ( /W) Transmit Holding Register */
|
||||
__IOM uint8_t DLL; /* Offset: 0x000 (R/W) Divisor Latch LSB */
|
||||
uint32_t RESERVED0;
|
||||
};
|
||||
union {
|
||||
__IOM uint8_t DLM; /* Offset: 0x004 (R/W) Divisor Latch MSB */
|
||||
__IOM uint32_t IER; /* Offset: 0x004 (R/W) Interrupt Enable Register */
|
||||
};
|
||||
union {
|
||||
__IM uint32_t IIR; /* Offset: 0x008 (R/ ) Interrupt ID Register */
|
||||
__OM uint8_t FCR; /* Offset: 0x008 ( /W) FIFO Control Register */
|
||||
};
|
||||
__IOM uint8_t LCR; /* Offset: 0x00C (R/W) Line Control Register */
|
||||
uint8_t RESERVED1[7];
|
||||
__IM uint8_t LSR; /* Offset: 0x014 (R/ ) Line Status Register */
|
||||
uint8_t RESERVED2[7];
|
||||
__IOM uint8_t SCR; /* Offset: 0x01C (R/W) Scratch Pad Register */
|
||||
uint8_t RESERVED3[3];
|
||||
__IOM uint32_t ACR; /* Offset: 0x020 (R/W) Autobaud Control Register */
|
||||
__IOM uint8_t ICR; /* Offset: 0x024 (R/W) IrDA Control Register */
|
||||
uint8_t RESERVED4[3];
|
||||
__IOM uint8_t FDR; /* Offset: 0x028 (R/W) Fractional Divider Register */
|
||||
uint8_t RESERVED5[7];
|
||||
__IOM uint8_t TER; /* Offset: 0x030 (R/W) Transmit Enable Register */
|
||||
uint8_t RESERVED6[39];
|
||||
__IM uint8_t FIFOLVL; /* Offset: 0x058 (R/ ) FIFO Level Register */
|
||||
} LPC_UART_TypeDef;
|
||||
\endcode
|
||||
|
||||
To access the registers of the UART defined above, pointers to this register structure are defined.
|
||||
If more instances of a peripheral exist, the variables have a postfix (digit or letter) that identifies the peripheral.
|
||||
|
||||
\b Example:
|
||||
In this example \b LPC_UART2 and \b LPC_UART3 are two pointers to UARTs defined with above register structure.
|
||||
\n
|
||||
\code
|
||||
#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
|
||||
#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
|
||||
\endcode
|
||||
|
||||
\note
|
||||
- The prefix <b>LPC</b> is optional.
|
||||
|
||||
The registers in the various UARTs can now be referred in the user code as shown below:\n
|
||||
\code
|
||||
val = LPC_UART2->DR // is the data register of UART1.
|
||||
\endcode
|
||||
|
||||
<hr>
|
||||
|
||||
\section core_cmsis_pal_min_reqs Minimal Requirements
|
||||
\details
|
||||
To access the peripheral registers and related function in a device, the files <b><i>device.h</i></b> and <b>core_cm<i>#</i>.h</b> define as a minimum:
|
||||
\n\n
|
||||
- The <b>Register Layout Typedef</b> for each peripheral that defines all register names.
|
||||
RESERVED is used to introduce space into the structure for adjusting the addresses of
|
||||
the peripheral registers.
|
||||
\n\n
|
||||
<b>Example:</b>
|
||||
\code
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /* Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /* Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /* Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /* Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
\endcode
|
||||
|
||||
|
||||
- <b>Base Address</b> for each peripheral (in case of multiple peripherals
|
||||
that use the same <b>register layout typedef</b> multiple base addresses are defined).
|
||||
\n\n
|
||||
<b>Example:</b>
|
||||
\code
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010) /* SysTick Base Address */
|
||||
\endcode
|
||||
|
||||
|
||||
- <b>Access Definitions</b> for each peripheral. In case of multiple peripherals that are using the same
|
||||
<b>register layout typdef</b>, multiple access definitions exist (LPC_UART0, LPC_UART2).
|
||||
\n\n
|
||||
<b>Example:</b>
|
||||
\code
|
||||
#define SysTick ((SysTick_Type *) Systick_BASE) /* SysTick access definition */
|
||||
\endcode
|
||||
|
||||
|
||||
These definitions allow accessing peripheral registers with simple assignments.
|
||||
|
||||
- <b>Example:</b>
|
||||
\n
|
||||
\code
|
||||
SysTick->CTRL = 0;
|
||||
\endcode
|
||||
|
||||
<hr>
|
||||
|
||||
\section core_cmsis_pal_opts Optional Features
|
||||
\details
|
||||
Optionally, the file <b><i>device</i>.h</b> may define:
|
||||
|
||||
- \ref core_cmsis_pal_bitfields and \#define constants that simplify access to peripheral registers.
|
||||
These constants may define bit-positions or other specific patterns that are required for
|
||||
programming peripheral registers. The identifiers should start with
|
||||
<b><<i>device abbreviation</i>>_</b> and <b><<i>peripheral name</i>>_</b>.
|
||||
It is recommended to use CAPITAL letters for \#define constants.
|
||||
|
||||
- More complex functions (i.e. status query before
|
||||
a sending register is accessed). Again, these functions start with
|
||||
<b><<i>device abbreviation</i>>_</b> and <b><<i>peripheral name</i>>_</b>.
|
||||
|
||||
<hr>
|
||||
|
||||
\section core_cmsis_pal_bitfields Register Bit Fields
|
||||
\details
|
||||
|
||||
For Core Register, macros define the position and the mask value for a bit field. It is recommended to create such definitions also
|
||||
for other peripheral registers.
|
||||
|
||||
<b>Example:</b>
|
||||
|
||||
Bit field definitions for register CPUID in SCB (System Control Block).
|
||||
|
||||
|
||||
\code
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
\endcode
|
||||
|
||||
The macros <b>_VAL2FLD(field, value)</b> and <b>_FLD2VAL(field, value)</b> enable access to bit fields.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\def _VAL2FLD(field, value)
|
||||
\param field name of bit field.
|
||||
\param value value for the bit field. This parameter is interpreted as an uint32_t type.
|
||||
\brief Mask and shift a bit field value for assigning the result to a peripheral register.
|
||||
\details
|
||||
The macro \ref _VAL2FLD uses the \#define's <i>_Pos</i> and <i>_Msk</i> of the related bit field to shift bit-field values for
|
||||
assigning to a register.
|
||||
|
||||
<b>Example:</b>
|
||||
\code
|
||||
SCB->CPUID = _VAL2FLD(SCB_CPUID_REVISION, 0x3) | _VAL2FLD(SCB_CPUID_VARIANT, 0x3);
|
||||
\endcode
|
||||
|
||||
*/
|
||||
#define _VAL2FLD(field, value)
|
||||
|
||||
/**
|
||||
|
||||
\def _FLD2VAL(field, value)
|
||||
\param field name of bit field.
|
||||
\param value value of the register. This parameter is interpreted as an uint32_t type.
|
||||
\brief Extract from a peripheral register value the a bit field value.
|
||||
\details
|
||||
The macro \ref _FLD2VAL uses the \#define's <i>_Pos</i> and <i>_Msk</i> of the related bit field to extract the value of a bit field from a register.
|
||||
|
||||
<b>Example:</b>
|
||||
\code
|
||||
id = _FLD2VAL(SCB_CPUID_REVISION, SCB->CPUID);
|
||||
\endcode
|
||||
|
||||
*/
|
||||
#define _FLD2VAL(field, value)
|
||||
|
||||
/**
|
||||
@}
|
||||
|
||||
*/
|
||||
95
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_SystemAndClock.txt
vendored
Normal file
95
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_SystemAndClock.txt
vendored
Normal file
@@ -0,0 +1,95 @@
|
||||
/* ################################ System and Clock Configuration ########################### */
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\defgroup system_init_gr System and Clock Configuration
|
||||
\brief Functions for system and clock setup available in system_<i>device</i>.c.
|
||||
\details
|
||||
Arm provides a template file <b>system_<i>device</i>.c</b> that must be adapted by
|
||||
the silicon vendor to match their actual device. As a <b>minimum requirement</b>,
|
||||
this file must provide:
|
||||
- A device-specific system configuration function, \ref SystemInit().
|
||||
- A global variable that contains the system frequency, \ref SystemCoreClock.
|
||||
|
||||
The file configures the device and, typically, initializes the oscillator (PLL) that is part
|
||||
of the microcontroller device. This file might export other functions or variables that provide
|
||||
a more flexible configuration of the microcontroller system.
|
||||
|
||||
\note Please pay special attention to the static variable \c SystemCoreClock. This variable might be
|
||||
used throughout the whole system initialization and runtime to calculate frequency/time related values.
|
||||
Thus one must assure that the variable always reflects the actual system clock speed. Be aware that
|
||||
a value stored to \c SystemCoreClock during low level initialization (i.e. \c SystemInit()) might get
|
||||
overwritten by C library startup code and/or .bss section initialization.
|
||||
Thus its highly recommended to call \ref SystemCoreClockUpdate at the beginning of the user \c main() routine.
|
||||
|
||||
|
||||
\section system_init_code_ex_sec Code Example
|
||||
The code below shows the usage of the variable \ref SystemCoreClock and the functions
|
||||
SystemInit() and SystemCoreClockUpdate() with an LPC1700.
|
||||
|
||||
\code
|
||||
#include "LPC17xx.h"
|
||||
|
||||
uint32_t coreClock_1 = 0; /* Variables to store core clock values */
|
||||
uint32_t coreClock_2 = 0;
|
||||
|
||||
|
||||
int main (void) {
|
||||
|
||||
coreClock_1 = SystemCoreClock; /* Store value of predefined SystemCoreClock */
|
||||
|
||||
SystemCoreClockUpdate(); /* Update SystemCoreClock according to register settings */
|
||||
|
||||
coreClock_2 = SystemCoreClock; /* Store value of calculated SystemCoreClock */
|
||||
|
||||
if (coreClock_2 != coreClock_1) { /* Without changing the clock setting both core clock values should be the same */
|
||||
// Error Handling
|
||||
}
|
||||
|
||||
while(1);
|
||||
}
|
||||
\endcode
|
||||
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\brief Variable to hold the system core clock value
|
||||
\details
|
||||
Holds the system core clock, which is the system clock frequency supplied to the SysTick
|
||||
timer and the processor core clock. This variable can be used by debuggers to query the
|
||||
frequency of the debug timer or to configure the trace clock speed.
|
||||
|
||||
\attention Compilers must be configured to avoid removing this variable in case the application
|
||||
program is not using it. Debugging systems require the variable to be physically
|
||||
present in memory so that it can be examined to configure the debugger.
|
||||
*/
|
||||
uint32_t SystemCoreClock;
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\brief Function to Initialize the system.
|
||||
\details
|
||||
Initializes the microcontroller system. Typically, this function configures the
|
||||
oscillator (PLL) that is part of the microcontroller device. For systems
|
||||
with a variable clock speed, it updates the variable \ref SystemCoreClock.
|
||||
SystemInit is called from the file <b>startup<i>_device</i></b>.
|
||||
*/
|
||||
void SystemInit (void);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\brief Function to update the variable \ref SystemCoreClock
|
||||
\details
|
||||
Updates the variable \ref SystemCoreClock and must be called whenever the core clock is changed
|
||||
during program execution. The function evaluates the clock register settings and calculates
|
||||
the current core clock.
|
||||
*/
|
||||
void SystemCoreClockUpdate (void);
|
||||
|
||||
|
||||
/** @} */ /* end group system_init_gr */
|
||||
|
||||
60
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_Systick.txt
vendored
Normal file
60
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_Systick.txt
vendored
Normal file
@@ -0,0 +1,60 @@
|
||||
/* ################################## SysTick function ###################################### */
|
||||
/**
|
||||
\defgroup SysTick_gr Systick Timer (SYSTICK)
|
||||
\brief Initialize and start the SysTick timer.
|
||||
\details
|
||||
The System Tick Time (SysTick) generates interrupt requests on a regular basis.
|
||||
This allows an OS to carry out context switching to support multiple tasking. For applications
|
||||
that do not require an OS, the SysTick can be used for time keeping, time measurement, or as an
|
||||
interrupt source for tasks that need to be executed regularly.
|
||||
|
||||
|
||||
\section SysTick_code_ex_sec Code Example
|
||||
The code below shows the usage of the function SysTick_Config() with an LPC1700.
|
||||
|
||||
\code
|
||||
#include "LPC17xx.h"
|
||||
|
||||
volatile uint32_t msTicks = 0; /* Variable to store millisecond ticks */
|
||||
|
||||
void SysTick_Handler(void) { /* SysTick interrupt Handler. */
|
||||
msTicks++; /* See startup file startup_LPC17xx.s for SysTick vector */
|
||||
}
|
||||
|
||||
int main (void) {
|
||||
uint32_t returnCode;
|
||||
|
||||
returnCode = SysTick_Config(SystemCoreClock / 1000); /* Configure SysTick to generate an interrupt every millisecond */
|
||||
|
||||
if (returnCode != 0) { /* Check return code for errors */
|
||||
// Error Handling
|
||||
}
|
||||
|
||||
while(1);
|
||||
}
|
||||
\endcode
|
||||
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief System Tick Timer Configuration
|
||||
\details
|
||||
Initialises and starts the System Tick Timer and its interrupt.
|
||||
After this call, the SysTick timer creates interrupts with the specified time interval.
|
||||
Counter is in free running mode to generate periodical interrupts.
|
||||
|
||||
\param [in] ticks Number of ticks between two interrupts
|
||||
|
||||
\returns 0 - success
|
||||
\returns 1 - failure
|
||||
|
||||
\note
|
||||
When \ref __Vendor_SysTickConfig is defined to 1, the standard function <b>SysTick_Config</b>
|
||||
is excluded. In this case, the \ref device_h_pg must contain a vendor specific implementation
|
||||
of this function.
|
||||
*/
|
||||
uint32_t SysTick_Config(uint32_t ticks);
|
||||
|
||||
/** @} */
|
||||
493
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_Trustzone.txt
vendored
Normal file
493
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_Trustzone.txt
vendored
Normal file
@@ -0,0 +1,493 @@
|
||||
/**
|
||||
\cond (ARMv8M)
|
||||
*/
|
||||
|
||||
/**
|
||||
\defgroup trustzone_functions TrustZone for Armv8-M/v8.1-M
|
||||
\brief Functions that related to optional Armv8-M and Armv8.1-M security extension
|
||||
@{
|
||||
\details
|
||||
The Armv8-M architecture has optional Armv8-M security extension based on Arm TrustZone technology.
|
||||
To access Arm TrustZone extensions for Armv8-M additional CMSIS functions are provided:
|
||||
- \ref coreregister_trustzone_functions
|
||||
- \ref nvic_trustzone_functions
|
||||
- \ref systick_trustzone_functions
|
||||
- \ref sau_trustzone_functions
|
||||
- \ref stacksealing_support_trustzone_functions
|
||||
- \ref context_trustzone_functions
|
||||
*/
|
||||
|
||||
/**
|
||||
\defgroup coreregister_trustzone_functions Core Register Access Functions
|
||||
\brief Core register Access functions related to TrustZone for Armv8-M.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Get Control register (non-secure)
|
||||
\details Returns the content of the non-secure Control register when in secure mode.
|
||||
\return non-secure Control register value
|
||||
\sa
|
||||
- \ref __get_CONTROL; CONTROL_Type
|
||||
*/
|
||||
uint32_t __TZ_get_CONTROL_NS(void);
|
||||
|
||||
/**
|
||||
\brief Set Control register (non-secure)
|
||||
\details Writes the given value to the non-secure Control register when in secure state.
|
||||
\param [in] control Control register value to set
|
||||
\sa
|
||||
- \ref __set_CONTROL; CONTROL_Type
|
||||
*/
|
||||
void __TZ_set_CONTROL_NS(uint32_t control);
|
||||
|
||||
/**
|
||||
\brief Get Process Stack Pointer (non-secure)
|
||||
\details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
|
||||
\return PSP register value
|
||||
\sa
|
||||
- \ref __get_PSP
|
||||
*/
|
||||
uint32_t __TZ_get_PSP_NS(void);
|
||||
|
||||
/**
|
||||
\brief Set Process Stack Pointer (non-secure)
|
||||
\details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
\sa
|
||||
- \ref __set_PSP
|
||||
*/
|
||||
void __TZ_set_PSP_NS(uint32_t topOfProcStack);
|
||||
|
||||
/**
|
||||
\brief Get Main Stack Pointer (non-secure)
|
||||
\details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
|
||||
\return MSP register value
|
||||
\sa
|
||||
- \ref __get_MSP
|
||||
*/
|
||||
uint32_t __TZ_get_MSP_NS(void);
|
||||
|
||||
/**
|
||||
\brief Set Main Stack Pointer (non-secure)
|
||||
\details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
\sa
|
||||
- \ref __set_MSP
|
||||
*/
|
||||
void __TZ_set_MSP_NS(uint32_t topOfMainStack);
|
||||
|
||||
/**
|
||||
\brief Get Stack Pointer (non-secure)
|
||||
\details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
|
||||
\return SP register value
|
||||
*/
|
||||
uint32_t __TZ_get_SP_NS(void);
|
||||
|
||||
/**
|
||||
\brief Set Stack Pointer (non-secure)
|
||||
\details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
|
||||
\param [in] topOfStack Stack Pointer value to set
|
||||
*/
|
||||
void __TZ_set_SP_NS(uint32_t topOfStack);
|
||||
|
||||
/**
|
||||
\brief Get Priority Mask (non-secure)
|
||||
\details Returns the current state of the non-secure priority mask bit from the Priority Mask register when in secure state.
|
||||
\return Priority Mask value
|
||||
\sa
|
||||
- \ref __get_PRIMASK
|
||||
*/
|
||||
uint32_t __TZ_get_PRIMASK_NS(void);
|
||||
|
||||
/**
|
||||
\brief Set Priority Mask (non-secure)
|
||||
\details Assigns the given value to the non-secure Priority Mask register when in secure state.
|
||||
\param [in] priMask Priority Mask
|
||||
\sa
|
||||
- \ref __set_PRIMASK
|
||||
*/
|
||||
void __TZ_set_PRIMASK_NS(uint32_t priMask);
|
||||
|
||||
/**
|
||||
\brief Get Base Priority (non-secure)
|
||||
\details Returns the current value of the non-secure Base Priority register when in secure state.
|
||||
\return Base Priority register value
|
||||
\sa
|
||||
- \ref __get_BASEPRI
|
||||
*/
|
||||
uint32_t __TZ_get_BASEPRI_NS(void);
|
||||
|
||||
/**
|
||||
\brief Set Base Priority (non-secure)
|
||||
\details Assigns the given value to the non-secure Base Priority register when in secure state.
|
||||
\param [in] basePri Base Priority value to set
|
||||
\sa
|
||||
- \ref __set_BASEPRI
|
||||
*/
|
||||
void __TZ_set_BASEPRI_NS(uint32_t basePri);
|
||||
|
||||
/**
|
||||
\brief Get Fault Mask (non-secure)
|
||||
\details Returns the current value of the non-secure Fault Mask register when in secure state.
|
||||
\return Fault Mask register value
|
||||
\sa
|
||||
- \ref __get_FAULTMASK
|
||||
*/
|
||||
uint32_t __TZ_get_FAULTMASK_NS(void);
|
||||
|
||||
/**
|
||||
\brief Set Fault Mask (non-secure)
|
||||
\details Assigns the given value to the non-secure Fault Mask register when in secure state.
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
\sa
|
||||
- \ref __set_FAULTMASK
|
||||
*/
|
||||
void __TZ_set_FAULTMASK_NS(uint32_t faultMask);
|
||||
|
||||
/**
|
||||
\brief Get Process Stack Pointer Limit (non-secure)
|
||||
Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||||
Stack Pointer Limit register hence zero is returned always.
|
||||
|
||||
\details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
|
||||
\return PSPLIM register value
|
||||
*/
|
||||
uint32_t __TZ_get_PSPLIM_NS(void);
|
||||
|
||||
/**
|
||||
\brief Set Process Stack Pointer (non-secure)
|
||||
Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||||
Stack Pointer Limit register hence zero is returned always.
|
||||
|
||||
\details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
|
||||
\param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
|
||||
*/
|
||||
void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit);
|
||||
|
||||
/**
|
||||
\brief Get Main Stack Pointer Limit (non-secure)
|
||||
Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||||
Stack Pointer Limit register hence zero is returned always.
|
||||
|
||||
\details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
|
||||
\return MSPLIM register value
|
||||
*/
|
||||
uint32_t __TZ_get_MSPLIM_NS(void);
|
||||
|
||||
/**
|
||||
\brief Set Main Stack Pointer Limit (non-secure)
|
||||
Devices without Armv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure
|
||||
Stack Pointer Limit register hence zero is returned always.
|
||||
|
||||
\details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
|
||||
\param [in] MainStackPtrLimit Main Stack Pointer value to set
|
||||
*/
|
||||
void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit);
|
||||
|
||||
/** close coreregister_trustzone_functions
|
||||
@}
|
||||
*/
|
||||
|
||||
/**
|
||||
\defgroup nvic_trustzone_functions NVIC Functions
|
||||
\brief Nested Vector Interrupt Controller (NVIC) functions related to TrustZone for Armv8-M
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Set Priority Grouping (non-secure)
|
||||
\details Sets the non-secure priority grouping field when in secure state using the required unlock sequence.
|
||||
The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
|
||||
Only values from 0..7 are used.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||
\param [in] PriorityGroup Priority grouping field.
|
||||
\note Only available for Armv8-M Mainline.
|
||||
\sa
|
||||
- \ref NVIC_SetPriorityGrouping
|
||||
*/
|
||||
void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup);
|
||||
|
||||
/**
|
||||
\brief Get Priority Grouping (non-secure)
|
||||
\details Reads the priority grouping field from the non-secure NVIC when in secure state.
|
||||
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
||||
\note Only available for Armv8-M Mainline.
|
||||
\sa
|
||||
- \ref NVIC_GetPriorityGrouping
|
||||
*/
|
||||
uint32_t TZ_NVIC_GetPriorityGrouping_NS(void);
|
||||
|
||||
/**
|
||||
\brief Enable External Interrupt (non-secure)
|
||||
\details Enables a device-specific interrupt in the non-secure NVIC when in secure state.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
\sa
|
||||
- \ref NVIC_EnableIRQ
|
||||
*/
|
||||
void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn);
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Enable status (non-secure)
|
||||
\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return 0 Interrupt is not enabled.
|
||||
\return 1 Interrupt is enabled.
|
||||
\sa
|
||||
- \ref NVIC_EnableIRQ; NVIC_DisableIRQ;
|
||||
*/
|
||||
uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn);
|
||||
|
||||
/**
|
||||
\brief Disable External Interrupt (non-secure)
|
||||
\details Disables a device-specific interrupt in the non-secure NVIC when in secure state.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
\sa
|
||||
- \ref NVIC_DisableIRQ
|
||||
*/
|
||||
void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn);
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt (non-secure)
|
||||
\details Reads the pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
\sa
|
||||
- \ref NVIC_GetPendingIRQ
|
||||
*/
|
||||
uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn);
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt (non-secure)
|
||||
\details Sets the pending bit of an non-secure external interrupt when in secure state.
|
||||
\param [in] IRQn Interrupt number. Value cannot be negative.
|
||||
\sa
|
||||
- \ref NVIC_SetPendingIRQ
|
||||
*/
|
||||
void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn);
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt (non-secure)
|
||||
\details Clears the pending bit of an non-secure external interrupt when in secure state.
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
\sa
|
||||
- \ref NVIC_ClearPendingIRQ
|
||||
*/
|
||||
void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn);
|
||||
|
||||
/**
|
||||
\brief Get Active Interrupt (non-secure)
|
||||
\details Reads the active register in non-secure NVIC when in secure state and returns the active bit.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return 0 Interrupt status is not active.
|
||||
\return 1 Interrupt status is active.
|
||||
\sa
|
||||
- \ref NVIC_GetActive
|
||||
*/
|
||||
uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn);
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority (non-secure)
|
||||
\details Sets the priority of an non-secure interrupt when in secure state.
|
||||
\note The priority cannot be set for every core interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
\sa
|
||||
- \ref NVIC_SetPriority
|
||||
*/
|
||||
void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority);
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority (non-secure)
|
||||
\details Reads the priority of an non-secure interrupt when in secure state.
|
||||
The interrupt number can be positive to specify an external (device specific) interrupt,
|
||||
or negative to specify an internal (core) interrupt.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
\sa
|
||||
- \ref NVIC_GetPriority
|
||||
*/
|
||||
uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn);
|
||||
|
||||
/** close nvic_trustzone_functions
|
||||
@}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
\defgroup systick_trustzone_functions SysTick Functions
|
||||
\brief SysTick functions related to TrustZone for Armv8-M.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration (non-secure)
|
||||
\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
\sa
|
||||
- \ref SysTick_Config
|
||||
*/
|
||||
uint32_t TZ_SysTick_Config_NS(uint32_t ticks);
|
||||
|
||||
/** close systick_trustzone_functions
|
||||
@}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
\defgroup sau_trustzone_functions SAU Functions
|
||||
\brief Secure Attribution Unit (SAU) functions related to TrustZone for Armv8-M.
|
||||
@{
|
||||
\details
|
||||
The Secure Attribution Unit (SAU) functions SAU
|
||||
|
||||
\note
|
||||
A SAU is always present if the security extension is available.
|
||||
The functionality differs if the SAU contains SAU regions.
|
||||
If SAU regions are available is configured with the macro __SAUREGION_PRESENT (see \ref core_config_sect).
|
||||
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Setup Secure Attribute Unit (SAU) and non-secure interrupts
|
||||
\details
|
||||
The function \ref TZ_SAU_Setup uses the settings in the \ref partition_h_pg to initialize
|
||||
the Secure Attribute Unit (SAU) and define non-secure interrupts. It is called from
|
||||
the function \ref SystemInit.
|
||||
*/
|
||||
void TZ_SAU_Setup (void);
|
||||
|
||||
/**
|
||||
\brief Enable Security Attribution Unit (SAU)
|
||||
\details Enables the Security Attribution Unit (SAU).
|
||||
*/
|
||||
void TZ_SAU_Enable(void);
|
||||
|
||||
/**
|
||||
\brief Disable Security Attribution Unit (SAU)
|
||||
\details Disables the Security Attribution Unit (SAU).
|
||||
*/
|
||||
void TZ_SAU_Disable(void);
|
||||
|
||||
/** close sau_trustzone_functions
|
||||
@}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
\defgroup stacksealing_support_trustzone_functions Stack Sealing Support Functions
|
||||
\brief Stack sealing macros and helper functions.
|
||||
@{
|
||||
\details
|
||||
See \ref RTOS_TrustZone_stacksealing for details on stack sealing technique.
|
||||
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Set stack seal at given address (secure)
|
||||
\details Writes the stack seal values (2 x 0xFEF5EDA5U) to the given address when in secure state.
|
||||
\param [in] stackTop address to write stackseal
|
||||
*/
|
||||
void __TZ_set_STACKSEAL_S (uint32_t *stackTop);
|
||||
|
||||
/**
|
||||
\def __STACK_SEAL
|
||||
\brief Compiler/linker symbol specifying the location of the stack seal.
|
||||
\details
|
||||
The address of the specified symbol is used to set the stack seal during low level init.
|
||||
This is compiler/linker specific. CMSIS specifies common default for supported compilers.
|
||||
|
||||
\note This define is only intended to be used by the \ref startup_c_pg.
|
||||
*/
|
||||
#define __STACK_SEAL
|
||||
|
||||
/** close stacksealing_support_trustzone_functions
|
||||
@}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
\defgroup context_trustzone_functions RTOS Context Management
|
||||
\brief RTOS Thread Context Management for Armv8-M TrustZone.
|
||||
@{
|
||||
\details The CMSIS-Core provides the file <b>tz_context.h</b> which defines an API to standardize the context memory system for real-time operating systems. For more information refer to \ref RTOS_TrustZone.
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Initialize secure context memory system
|
||||
\details Initializes the memory allocation management for the secure memory regions. As a minimum the secure thread mode stack will be provided.
|
||||
\return execution status (1: success, 0: error)
|
||||
*/
|
||||
uint32_t TZ_InitContextSystem_S (void);
|
||||
|
||||
/**
|
||||
\brief Allocate context memory for calling secure software modules in TrustZone
|
||||
\details
|
||||
Allocates the secure memory regions for thread execution. The parameter \em module describes
|
||||
the set of secure functions that are called by the non-secure thread.
|
||||
Set \em module to zero if no secure calls are used/allowed. This leads to no secure memory to be assigned
|
||||
which results in zero being returned as memory id as well.
|
||||
This function should be called by an RTOS kernel at the start of a thread.
|
||||
\param[in] module A non-zero value identifies software modules called from non-secure mode. zero is used if no secure calls are used/allowed.
|
||||
\return value != 0 id TrustZone memory slot identify
|
||||
\return value 0 no memory available or internal error
|
||||
*/
|
||||
TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module);
|
||||
|
||||
/**
|
||||
\brief Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S
|
||||
\details
|
||||
De-allocates the secure memory regions.
|
||||
The parameter \em id refers to a TrustZone memory slot that has been obtained with \ref TZ_AllocModuleContext_S.
|
||||
This function should be called by an RTOS kernel at the termination of a thread.
|
||||
\param[in] id TrustZone memory slot identifier
|
||||
\return execution status (1: success, 0: error)
|
||||
*/
|
||||
uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/**
|
||||
\brief Load secure context (called on RTOS thread context switch)
|
||||
\details
|
||||
Prepare the secure context for execution so that a thread in the non-secure state can
|
||||
call secure library modules. The parameter \em id refers to a TrustZone memory slot that has been
|
||||
obtained with \ref TZ_AllocModuleContext_S which might be zero if not used.
|
||||
This function should be called by an RTOS kernel at thread context switch before running a thread.
|
||||
\param[in] id TrustZone memory slot identifier
|
||||
\return execution status (1: success, 0: error)
|
||||
*/
|
||||
uint32_t TZ_LoadContext_S (TZ_MemoryId_t id);
|
||||
|
||||
/**
|
||||
\brief Store secure context (called on RTOS thread context switch)
|
||||
\details
|
||||
Free the secure context that has been previously loaded with \ref TZ_LoadContext_S. The parameter
|
||||
\em id refers to a TrustZone memory slot that has been obtained with \ref TZ_AllocModuleContext_S
|
||||
which might be zero if not used.
|
||||
This function should be called by an RTOS kernel at thread context switch after running a thread.
|
||||
\param[in] id TrustZone memory slot identifier
|
||||
\return execution status (1: success, 0: error)
|
||||
*/
|
||||
uint32_t TZ_StoreContext_S (TZ_MemoryId_t id);
|
||||
|
||||
|
||||
/** close context_trustzone_functions
|
||||
@}
|
||||
*/
|
||||
|
||||
|
||||
/** close trustzone_functions
|
||||
@}
|
||||
*/
|
||||
|
||||
/**
|
||||
\endcond
|
||||
*/
|
||||
131
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_VersionControl.txt
vendored
Normal file
131
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_VersionControl.txt
vendored
Normal file
@@ -0,0 +1,131 @@
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\defgroup version_control_gr Version Control
|
||||
\brief Version \#define symbols for CMSIS release specific C/C++ source code
|
||||
\details
|
||||
The header file <b>cmsis_version.h</b> is included by each core header so that these definitions are available.
|
||||
|
||||
<b>Code Example:</b>
|
||||
\code
|
||||
#if defined(__CM_CMSIS_VERSION) && \
|
||||
(__CM_CMSIS_VERSION >= 0x00050001)
|
||||
#error Yes, we have CMSIS 5.1 or later
|
||||
#else
|
||||
#error We need CMSIS 5.1 or later!
|
||||
#endif
|
||||
\endcode
|
||||
|
||||
<b>Deprecated</b>
|
||||
|
||||
The following macros are deprecated:
|
||||
- \b __XXX_CMSIS_VERSION_MAIN which is replaced by \ref __CM_CMSIS_VERSION_MAIN.
|
||||
- \b __XXX_CMSIS_VERSION_SUB which is replaced by \ref __CM_CMSIS_VERSION_SUB.
|
||||
- \b __XXX_CMSIS_VERSION which is replaced by \ref __CM_CMSIS_VERSION.
|
||||
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Contains the CMSIS major version
|
||||
\details The CMSIS major version can be used to differentiate between CMSIS major releases.
|
||||
*/
|
||||
#define __CM_CMSIS_VERSION_MAIN
|
||||
|
||||
/**
|
||||
\brief Contains the CMSIS minor version
|
||||
\details The CMSIS minor version can be used to query a CMSIS release update level.
|
||||
*/
|
||||
#define __CM_CMSIS_VERSION_SUB
|
||||
|
||||
/**
|
||||
\brief Contains the CMSIS version
|
||||
\details The CMSIS version is a combination of the \ref __CM_CMSIS_VERSION_MAIN (bits 31..15) and \ref __CM_CMSIS_VERSION_SUB (bits 14..0).
|
||||
*/
|
||||
#define __CM_CMSIS_VERSION
|
||||
|
||||
/**
|
||||
\brief Contains the core version for a Cortex-M class controller.
|
||||
\details This define can be used to differentiate between the various available Cortex-M controllers.
|
||||
Possible values are:
|
||||
- 0 for a Cortex-M0 or Cortex-M0+
|
||||
- 1 for a Cortex-M1
|
||||
- 3 for a Cortex-M3
|
||||
- 4 for a Cortex-M4
|
||||
- 7 for a Cortex-M7
|
||||
\if ARMv8M
|
||||
- 23 for a Cortex-M23
|
||||
- 33 for a Cortex-M33
|
||||
- 35 for a Cortex-M35P
|
||||
- 55 for a Cortex-M55
|
||||
- 85 for a Cortex-M85
|
||||
- 2 for a Armv8-M Base Line device
|
||||
- 80 for a Armv8-M Main Line device
|
||||
- 81 for a Armv8.1-M Main Line device
|
||||
\endif
|
||||
|
||||
This define is only available for Cortex-M class controllers.
|
||||
<b>Code Example:</b>
|
||||
\code
|
||||
#if defined(__CORTEX_M) && (__CORTEX_M == 4)
|
||||
#error Yes, we have an Cortex-M4 controller.
|
||||
#else
|
||||
#error We need a Cortex-M4 controller!
|
||||
#endif
|
||||
\endcode
|
||||
*/
|
||||
#define __CORTEX_M
|
||||
|
||||
|
||||
/**
|
||||
\cond (ARMSC)
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Contains the core version for a Cortex Secure Core controller.
|
||||
\details This define can be used to differentiate between the various available Cortex Secure Core controllers.
|
||||
Possible values are:
|
||||
- 000 for a Cortex-SC000
|
||||
- 300 for a Cortex-SC300
|
||||
|
||||
This define is only available for Cortex Secure Core controllers.
|
||||
<b>Code Example:</b>
|
||||
\code
|
||||
#if defined(__CORTEX_SC) && (__CORTEX_SC == 300U)
|
||||
#error Yes, we have an Cortex SC300 controller.
|
||||
#else
|
||||
#error We need a Cortex SC300 controller!
|
||||
#endif
|
||||
\endcode
|
||||
*/
|
||||
#define __CORTEX_SC
|
||||
/**
|
||||
\endcond
|
||||
*/
|
||||
|
||||
/**
|
||||
\cond (STAR)
|
||||
*/
|
||||
/**
|
||||
\brief Contains the core version for a STAR-MC controller.
|
||||
\details This define can be used to differentiate between the various available STAR-MC controllers.
|
||||
Possible values are:
|
||||
- 1 for a STAR-MC1
|
||||
|
||||
This define is only available for STAR-MC controllers.
|
||||
<b>Code Example:</b>
|
||||
\code
|
||||
#if defined(__STAR_MC) && (__STAR_MC == 1U)
|
||||
#error Yes, we have a STAR-MC1 controller.
|
||||
#else
|
||||
#error We need a STAR-MC1 controller!
|
||||
#endif
|
||||
\endcode
|
||||
*/
|
||||
#define __STAR_MC
|
||||
/**
|
||||
\endcond
|
||||
*/
|
||||
|
||||
/**
|
||||
@}
|
||||
*/
|
||||
1960
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_cm4_simd.txt
vendored
Normal file
1960
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_cm4_simd.txt
vendored
Normal file
File diff suppressed because it is too large
Load Diff
485
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_cmInstr.txt
vendored
Normal file
485
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Ref_cmInstr.txt
vendored
Normal file
@@ -0,0 +1,485 @@
|
||||
/**
|
||||
\defgroup intrinsic_CPU_gr Intrinsic Functions for CPU Instructions
|
||||
@{
|
||||
\brief Functions that generate specific Cortex-M CPU Instructions.
|
||||
\details
|
||||
The following functions generate specific Cortex-M instructions that cannot be directly accessed by the C/C++ Compiler.
|
||||
Refer to the \ref ref_man_sec for detailed information about these Cortex-M instructions.
|
||||
|
||||
\note
|
||||
When using the <b>Arm Compiler Version 5 Toolchain</b> the following \ref intrinsic_CPU_gr are implemented using the Embedded Assembler.
|
||||
As the Embedded Assembler may cause side effects (Refer to <b>Arm Compiler v5.xx User Guide - Using the Inline and Embedded Assemblers of the Arm Compiler</b> for more information)
|
||||
it is possible to disable the following intrinsic functions and therefore the usage of the Embedded Assembler with the <b><i>define __NO_EMBEDDED_ASM</i></b>:
|
||||
- \ref __REV16
|
||||
- \ref __REVSH
|
||||
- \ref __RRX
|
||||
|
||||
|
||||
*/
|
||||
/**************************************************************************************************/
|
||||
/** \brief No Operation
|
||||
|
||||
This function does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
void __NOP(void);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
WFI is a hint instruction that suspends execution until one of the following events occurs:
|
||||
- A non-masked interrupt occurs and is taken.
|
||||
- An interrupt masked by PRIMASK becomes pending.
|
||||
- A Debug Entry request.
|
||||
*/
|
||||
void __WFI(void);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until an events occurs:
|
||||
\li If the <b>event register is 0</b>, then WFE suspends execution until one of the following events occurs:
|
||||
- An exception, unless masked by the exception mask registers or the current priority level.
|
||||
- An exception enters the Pending state, if SEVONPEND in the System Control Register is set.
|
||||
- A Debug Entry request, if Debug is enabled.
|
||||
- An event signaled by a peripheral or another processor in a multiprocessor system using
|
||||
the SEV instruction.
|
||||
|
||||
\li If the <b>event register is 1</b>, then WFE clears it to 0 and returns immediately.
|
||||
|
||||
*/
|
||||
void __WFE(void);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
void __SEV(void);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Set Breakpoint
|
||||
|
||||
This function causes the processor to enter Debug state.
|
||||
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
|
||||
|
||||
\param [in] value is ignored by the processor. If required, a debugger can use it to obtain additional information about the breakpoint.
|
||||
*/
|
||||
void __BKPT(uint8_t value);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
void __ISB(void);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
\details
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
void __DSB(void);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
\details
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
void __DMB(void);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\brief Reverse byte order (32 bit)
|
||||
\details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
uint32_t __REV(uint32_t value);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
uint32_t __REV16(uint32_t value);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\brief Reverse byte order (16 bit)
|
||||
\details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
int16_t __REVSH(int16_t value);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/**
|
||||
\brief Reverse bit order of value
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
uint32_t __RBIT(uint32_t value);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Rotate a value right by a number of bits
|
||||
|
||||
This function rotates a value right by a specified number of bits.
|
||||
|
||||
\param [in] value Value to be shifted right
|
||||
\param [in] shift Number of bits in the range [1..31]
|
||||
\return Rotated value
|
||||
|
||||
*/
|
||||
uint32_t __ROR(uint32_t value, uint32_t shift);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief LDR Exclusive (8 bit) [not for Cortex-M0, Cortex-M0+, or SC000]
|
||||
|
||||
This function executed an exclusive LDR command for 8 bit value [not for Cortex-M0, Cortex-M0+, or SC000].
|
||||
|
||||
\param [in] *addr Pointer to data
|
||||
\return value of type uint8_t at (*addr)
|
||||
*/
|
||||
uint8_t __LDREXB(volatile uint8_t *addr);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief LDR Exclusive (16 bit) [not for Cortex-M0, Cortex-M0+, or SC000]
|
||||
|
||||
This function executed an exclusive LDR command for 16 bit values [not for Cortex-M0, Cortex-M0+, or SC000].
|
||||
|
||||
\param [in] *addr Pointer to data
|
||||
\return value of type uint16_t at (*addr)
|
||||
*/
|
||||
uint16_t __LDREXH(volatile uint16_t *addr);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief LDR Exclusive (32 bit) [not for Cortex-M0, Cortex-M0+, or SC000]
|
||||
|
||||
This function executed an exclusive LDR command for 32 bit values [not for Cortex-M0, Cortex-M0+, or SC000].
|
||||
|
||||
\param [in] *addr Pointer to data
|
||||
\return value of type uint32_t at (*addr)
|
||||
*/
|
||||
uint32_t __LDREXW(volatile uint32_t *addr);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief STR Exclusive (8 bit) [not for Cortex-M0, Cortex-M0+, or SC000]
|
||||
|
||||
This function executed an exclusive STR command for 8 bit values [not for Cortex-M0, Cortex-M0+, or SC000].
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] *addr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
uint32_t __STREXB(uint8_t value, volatile uint8_t *addr);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief STR Exclusive (16 bit) [not for Cortex-M0, Cortex-M0+, or SC000]
|
||||
|
||||
This function executed an exclusive STR command for 16 bit values [not for Cortex-M0, Cortex-M0+, or SC000].
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] *addr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
uint32_t __STREXH(uint16_t value, volatile uint16_t *addr);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief STR Exclusive (32 bit) [not for Cortex-M0, Cortex-M0+, or SC000]
|
||||
|
||||
This function executed an exclusive STR command for 32 bit values [not for Cortex-M0, Cortex-M0+, or SC000].
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] *addr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
uint32_t __STREXW(uint32_t value, volatile uint32_t *addr);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Remove the exclusive lock [not for Cortex-M0, Cortex-M0+, or SC000]
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX [not for Cortex-M0, Cortex-M0+, or SC000].
|
||||
|
||||
*/
|
||||
void __CLREX(void);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
The Q bit is set if saturation occurs [not for Cortex-M0, Cortex-M0+, or SC000].
|
||||
|
||||
On Armv6-M (Cortex-M0, Cortex-M0+, and SC000) this function is not available as a core instruction
|
||||
instruction and thus __SSAT is implemented in software.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to [1..32]
|
||||
\return Saturated value
|
||||
*/
|
||||
int32_t __SSAT(int32_t value, uint32_t sat);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
The Q bit is set if saturation occurs [not for Cortex-M0, Cortex-M0+, or SC000].
|
||||
|
||||
On Armv6-M (Cortex-M0, Cortex-M0+, and SC000) this function is not available as a core instruction
|
||||
instruction and thus __USAT is implemented in software.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to [0..31]
|
||||
\return Saturated value
|
||||
*/
|
||||
uint32_t __USAT(int32_t value, uint32_t sat);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
On Armv6-M (Cortex-M0, Cortex-M0+, and SC000) this function is not available as a core instruction
|
||||
instruction and thus __CLZ is implemented in software.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
uint8_t __CLZ(uint32_t value);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief Rotate Right with Extend (32 bit)
|
||||
|
||||
This function moves each bit of a bitstring right by one bit. The carry input is shifted in at the left end of the bitstring.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
uint32_t __RRX(uint32_t value);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief LDRT Unprivileged (8 bit)
|
||||
|
||||
This function executed an Unprivileged LDRT command for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
uint8_t __LDRBT(uint8_t ptr);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief LDRT Unprivileged (16 bit)
|
||||
|
||||
This function executed an Unprivileged LDRT command for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
uint16_t __LDRHT(uint16_t ptr);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief LDRT Unprivileged (32 bit)
|
||||
|
||||
This function executed an Unprivileged LDRT command for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
uint32_t __LDRT(uint32_t ptr);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief STRT Unprivileged (8 bit)
|
||||
|
||||
This function executed an Unprivileged STRT command for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
void __STRBT(uint8_t value, uint8_t ptr);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief STRT Unprivileged (16 bit)
|
||||
|
||||
This function executed an Unprivileged STRT command for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
void __STRHT(uint16_t value, uint16_t ptr);
|
||||
|
||||
|
||||
/**************************************************************************************************/
|
||||
/** \brief STRT Unprivileged (32 bit)
|
||||
|
||||
This function executed an Unprivileged STRT command for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
*/
|
||||
void __STRT(uint32_t value, uint32_t ptr);
|
||||
|
||||
|
||||
/**
|
||||
\cond (ARMv8M)
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Load-Acquire (8 bit)
|
||||
\details Executes a LDAB instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
\note Only available for Armv8-M Architecture.
|
||||
*/
|
||||
uint8_t __LDAB(volatile uint8_t *ptr);
|
||||
|
||||
/**
|
||||
\brief Load-Acquire (16 bit)
|
||||
\details Executes a LDAH instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
\note Only available for Armv8-M Architecture.
|
||||
*/
|
||||
uint16_t __LDAH(volatile uint16_t *ptr);
|
||||
|
||||
/**
|
||||
\brief Load-Acquire (32 bit)
|
||||
\details Executes a LDA instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
\note Only available for Armv8-M Architecture.
|
||||
*/
|
||||
uint32_t __LDA(volatile uint32_t *ptr);
|
||||
|
||||
/**
|
||||
\brief Store-Release (8 bit)
|
||||
\details Executes a STLB instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\note Only available for Armv8-M Architecture.
|
||||
*/
|
||||
void __STLB(uint8_t value, volatile uint8_t *ptr);
|
||||
|
||||
/**
|
||||
\brief Store-Release (16 bit)
|
||||
\details Executes a STLH instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\note Only available for Armv8-M Architecture.
|
||||
*/
|
||||
void __STLH(uint16_t value, volatile uint16_t *ptr);
|
||||
|
||||
/**
|
||||
\brief Store-Release (32 bit)
|
||||
\details Executes a STL instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\note Only available for Armv8-M Architecture.
|
||||
*/
|
||||
void __STL(uint32_t value, volatile uint32_t *ptr);
|
||||
|
||||
/**
|
||||
\brief Load-Acquire Exclusive (8 bit)
|
||||
\details Executes a LDAB exclusive instruction for 8 bit value.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
\note Only available for Armv8-M Architecture.
|
||||
*/
|
||||
uint8_t __LDAEXB(volatile uint32_t *ptr);
|
||||
|
||||
/**
|
||||
\brief Load-Acquire Exclusive (16 bit)
|
||||
\details Executes a LDAH exclusive instruction for 16 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
\note Only available for Armv8-M Architecture.
|
||||
*/
|
||||
uint16_t __LDAEXH(volatile uint32_t *ptr);
|
||||
|
||||
/**
|
||||
\brief Load-Acquire Exclusive (32 bit)
|
||||
\details Executes a LDA exclusive instruction for 32 bit values.
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
\note Only available for Armv8-M Architecture.
|
||||
*/
|
||||
uint32_t __LDAEX(volatile uint32_t *ptr);
|
||||
|
||||
/**
|
||||
\brief Store-Release Exclusive (8 bit)
|
||||
\details Executes a STLB exclusive instruction for 8 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
\note Only available for Armv8-M Architecture.
|
||||
*/
|
||||
uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr);
|
||||
|
||||
/**
|
||||
\brief Store-Release Exclusive (16 bit)
|
||||
\details Executes a STLH exclusive instruction for 16 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
\note Only available for Armv8-M Architecture.
|
||||
*/
|
||||
uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr);
|
||||
|
||||
/**
|
||||
\brief Store-Release Exclusive (32 bit)
|
||||
\details Executes a STL exclusive instruction for 32 bit values.
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
\note Only available for Armv8-M Architecture.
|
||||
*/
|
||||
uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr);
|
||||
|
||||
/**
|
||||
\endcond
|
||||
*/
|
||||
|
||||
/*@}*/ /* end of group Intrisic_CPU */
|
||||
|
||||
|
||||
500
external/CMSIS_5/CMSIS/DoxyGen/Core/src/RegMap_CMSIS2ARM_Doc.txt
vendored
Normal file
500
external/CMSIS_5/CMSIS/DoxyGen/Core/src/RegMap_CMSIS2ARM_Doc.txt
vendored
Normal file
@@ -0,0 +1,500 @@
|
||||
/**
|
||||
\page regMap_pg Register Mapping
|
||||
|
||||
\details
|
||||
|
||||
The table below associates some common register names used in CMSIS to the register names
|
||||
used in Technical Reference Manuals.
|
||||
|
||||
<table class="cmtable" summary="Register Mapping">
|
||||
<tr>
|
||||
<th>CMSIS Register Name</th>
|
||||
<th>Cortex-M3, Cortex-M4, and Cortex-M7</th>
|
||||
<th>Cortex-M0 and Cortex-M0+</th>
|
||||
<th>Register Name</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<th colspan="4">Nested Vectored Interrupt Controller (NVIC) Register Access</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>NVIC->ISER[]</td>
|
||||
<td>NVIC_ISER0..7</td>
|
||||
<td>ISER</td>
|
||||
<td>Interrupt Set-Enable Registers</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>NVIC->ICER[]</td>
|
||||
<td>NVIC_ICER0..7</td>
|
||||
<td>ICER</td>
|
||||
<td>Interrupt Clear-Enable Registers</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>NVIC->ISPR[]</td>
|
||||
<td>NVIC_ISPR0..7</td>
|
||||
<td>ISPR</td>
|
||||
<td>Interrupt Set-Pending Registers</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>NVIC->ICPR[]</td>
|
||||
<td>NVIC_ICPR0..7</td>
|
||||
<td>ICPR</td>
|
||||
<td>Interrupt Clear-Pending Registers</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>NVIC->IABR[]</td>
|
||||
<td>NVIC_IABR0..7</td>
|
||||
<td>-</td>
|
||||
<td>Interrupt Active Bit Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>NVIC->IP[]</td>
|
||||
<td>NVIC_IPR0..59</td>
|
||||
<td>IPR0..7</td>
|
||||
<td>Interrupt Priority Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>NVIC->STIR</td>
|
||||
<td>STIR</td>
|
||||
<td>-</td>
|
||||
<td>Software Triggered Interrupt Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<th colspan="4">System Control Block (SCB) Register Access</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SCB->CPUID</td>
|
||||
<td>CPUID</td>
|
||||
<td>CPUID</td>
|
||||
<td>CPUID Base Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SCB->ICSR</td>
|
||||
<td>ICSR</td>
|
||||
<td>ICSR</td>
|
||||
<td>Interrupt Control and State Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SCB->VTOR</td>
|
||||
<td>VTOR</td>
|
||||
<td>-</td>
|
||||
<td>Vector Table Offset Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SCB->AIRCR</td>
|
||||
<td>AIRCR</td>
|
||||
<td>AIRCR</td>
|
||||
<td>Application Interrupt and Reset Control Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SCB->SCR</td>
|
||||
<td>SCR</td>
|
||||
<td>SCR</td>
|
||||
<td>System Control Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SCB->CCR</td>
|
||||
<td>CCR</td>
|
||||
<td>CCR</td>
|
||||
<td>Configuration and Control Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SCB->SHP[]</td>
|
||||
<td>SHPR1..3</td>
|
||||
<td>SHPR2..3</td>
|
||||
<td>System Handler Priority Registers</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SCB->SHCSR</td>
|
||||
<td>SHCSR</td>
|
||||
<td>SHCSR</td>
|
||||
<td>System Handler Control and State Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SCB->CFSR</td>
|
||||
<td>CFSR</td>
|
||||
<td>-</td>
|
||||
<td>Configurable Fault Status Registers</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SCB->HFSR</td>
|
||||
<td>HFSR</td>
|
||||
<td>-</td>
|
||||
<td>HardFault Status Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SCB->DFSR</td>
|
||||
<td>DFSR</td>
|
||||
<td>-</td>
|
||||
<td>Debug Fault Status Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SCB->MMFAR</td>
|
||||
<td>MMFAR</td>
|
||||
<td>-</td>
|
||||
<td>MemManage Fault Address Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SCB->BFAR</td>
|
||||
<td>BFAR</td>
|
||||
<td>-</td>
|
||||
<td>BusFault Address Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SCB->AFSR</td>
|
||||
<td>AFSR</td>
|
||||
<td>-</td>
|
||||
<td>Auxiliary Fault Status Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SCB->PFR[]</td>
|
||||
<td>ID_PFR0..1</td>
|
||||
<td>-</td>
|
||||
<td>Processor Feature Registers</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SCB->DFR</td>
|
||||
<td>ID_DFR0</td>
|
||||
<td>-</td>
|
||||
<td>Debug Feature Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SCB->ADR</td>
|
||||
<td>ID_AFR0</td>
|
||||
<td>-</td>
|
||||
<td>Auxiliary Feature Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SCB->MMFR[]</td>
|
||||
<td>ID_MMFR0..3</td>
|
||||
<td>-</td>
|
||||
<td>Memory Model Feature Registers</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SCB->ISAR[]</td>
|
||||
<td>ID_ISAR0..4</td>
|
||||
<td>-</td>
|
||||
<td>Instruction Set Attributes Registers</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SCB->CPACR</td>
|
||||
<td>CPACR</td>
|
||||
<td>-</td>
|
||||
<td>Coprocessor Access Control Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<th colspan="4">System Control and ID Registers not in the SCB (SCnSCB) Register Access</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SCnSCB->ICTR</td>
|
||||
<td>ICTR</td>
|
||||
<td>-</td>
|
||||
<td>Interrupt Controller Type Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SCnSCB->ACTLR</td>
|
||||
<td>ACTLR</td>
|
||||
<td>-</td>
|
||||
<td>Auxiliary Control Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<th colspan="4">System Timer (SysTick) Control and Status Register Access</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SysTick->CTRL</td>
|
||||
<td>STCSR</td>
|
||||
<td>SYST_CSR</td>
|
||||
<td>SysTick Control and Status Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SysTick->LOAD</td>
|
||||
<td>STRVR</td>
|
||||
<td>SYST_RVR</td>
|
||||
<td>SysTick Reload Value Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SysTick->VAL</td>
|
||||
<td>STCVR</td>
|
||||
<td>SYST_CVR</td>
|
||||
<td>SysTick Current Value Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>SysTick->CALIB</td>
|
||||
<td>STCR</td>
|
||||
<td>SYST_CALIB</td>
|
||||
<td>SysTick Calibaration Value Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<th colspan="4">Data Watchpoint and Trace (DWT) Register Access</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>DWT->CTRL</td>
|
||||
<td>DWT_CTRL</td>
|
||||
<td>-</td>
|
||||
<td>Control Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>DWT->CYCCNT</td>
|
||||
<td>DWT_CYCCNT</td>
|
||||
<td>-</td>
|
||||
<td>Cycle Count Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>DWT->CPICNT</td>
|
||||
<td>DWT_CPICNT</td>
|
||||
<td>-</td>
|
||||
<td>CPI Count Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>DWT->EXCCNT</td>
|
||||
<td>DWT_EXCCNT</td>
|
||||
<td>-</td>
|
||||
<td>Exception Overhead Count Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>DWT->SLEEPCNT</td>
|
||||
<td>DWT_SLEEPCNT</td>
|
||||
<td>-</td>
|
||||
<td>Sleep Count Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>DWT->LSUCNT</td>
|
||||
<td>DWT_LSUCNT</td>
|
||||
<td>-</td>
|
||||
<td>LSU Count Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>DWT->FOLDCNT</td>
|
||||
<td>DWT_FOLDCNT</td>
|
||||
<td>-</td>
|
||||
<td>Folded-instruction Count Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>DWT->PCSR</td>
|
||||
<td>DWT_PCSR</td>
|
||||
<td>-</td>
|
||||
<td>Program Counter Sample Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>DWT->COMP0..3</td>
|
||||
<td>DWT_COMP0..3</td>
|
||||
<td>-</td>
|
||||
<td>Comparator Register 0..3</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>DWT->MASK0..3</td>
|
||||
<td>DWT_MASK0..3</td>
|
||||
<td>-</td>
|
||||
<td>Mask Register 0..3</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>DWT->FUNCTION0..3</td>
|
||||
<td>DWT_FUNCTION0..3</td>
|
||||
<td>-</td>
|
||||
<td>Function Register 0..3</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<th colspan="4">Instrumentation Trace Macrocell (ITM) Register Access</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>ITM->PORT[]</td>
|
||||
<td>ITM_STIM0..31</td>
|
||||
<td>-</td>
|
||||
<td>Stimulus Port Registers</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>ITM->TER</td>
|
||||
<td>ITM_TER</td>
|
||||
<td>-</td>
|
||||
<td>Trace Enable Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>ITM->TPR</td>
|
||||
<td>ITM_TPR</td>
|
||||
<td>-</td>
|
||||
<td>ITM Trace Privilege Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>ITM->TCR</td>
|
||||
<td>ITM_TCR</td>
|
||||
<td>-</td>
|
||||
<td>Trace Control Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<th colspan="4">Trace Port Interface (TPIU) Register Access</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>TPI->SSPSR</td>
|
||||
<td>TPIU_SSPR</td>
|
||||
<td>-</td>
|
||||
<td>Supported Parallel Port Size Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>TPI->CSPSR</td>
|
||||
<td>TPIU_CSPSR</td>
|
||||
<td>-</td>
|
||||
<td>Current Parallel Port Size Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>TPI->ACPR</td>
|
||||
<td>TPIU_ACPR</td>
|
||||
<td>-</td>
|
||||
<td>Asynchronous Clock Prescaler Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>TPI->SPPR</td>
|
||||
<td>TPIU_SPPR</td>
|
||||
<td>-</td>
|
||||
<td>Selected Pin Protocol Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>TPI->FFSR</td>
|
||||
<td>TPIU_FFSR</td>
|
||||
<td>-</td>
|
||||
<td>Formatter and Flush Status Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>TPI->FFCR</td>
|
||||
<td>TPIU_FFCR</td>
|
||||
<td>-</td>
|
||||
<td>Formatter and Flush Control Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>TPI->FSCR</td>
|
||||
<td>TPIU_FSCR</td>
|
||||
<td>-</td>
|
||||
<td>Formatter Synchronization Counter Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>TPI->TRIGGER</td>
|
||||
<td>TRIGGER</td>
|
||||
<td>-</td>
|
||||
<td>TRIGGER</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>TPI->FIFO0</td>
|
||||
<td>FIFO data 0</td>
|
||||
<td>-</td>
|
||||
<td>Integration ETM Data</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>TPI->ITATBCTR2</td>
|
||||
<td>ITATBCTR2</td>
|
||||
<td>-</td>
|
||||
<td>ITATBCTR2</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>TPI->ITATBCTR0</td>
|
||||
<td>ITATBCTR0</td>
|
||||
<td>-</td>
|
||||
<td>ITATBCTR0</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>TPI->FIFO1</td>
|
||||
<td>FIFO data 1</td>
|
||||
<td>-</td>
|
||||
<td>Integration ITM Data</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>TPI->ITCTRL</td>
|
||||
<td>TPIU_ITCTRL</td>
|
||||
<td>-</td>
|
||||
<td>Integration Mode Control</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>TPI->CLAIMSET</td>
|
||||
<td>CLAIMSET</td>
|
||||
<td>-</td>
|
||||
<td>Claim tag set</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>TPI->CLAIMCLR</td>
|
||||
<td>CLAIMCLR</td>
|
||||
<td>-</td>
|
||||
<td>Claim tag clear</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>TPI->DEVID</td>
|
||||
<td>TPIU_DEVID</td>
|
||||
<td>-</td>
|
||||
<td>TPIU_DEVID</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>TPI->DEVTYPE</td>
|
||||
<td>TPIU_DEVTYPE</td>
|
||||
<td>-</td>
|
||||
<td>TPIU_DEVTYPE</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<th colspan="4">Memory Protection Unit (MPU) Register Access</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>MPU->TYPE</td>
|
||||
<td>MPU_TYPE</td>
|
||||
<td>-</td>
|
||||
<td>MPU Type Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>MPU->CTRL</td>
|
||||
<td>MPU_CTRL</td>
|
||||
<td>-</td>
|
||||
<td>MPU Control Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>MPU->RNR</td>
|
||||
<td>MPU_RNR</td>
|
||||
<td>-</td>
|
||||
<td>MPU Region Number Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>MPU->RBAR</td>
|
||||
<td>MPU_RBAR</td>
|
||||
<td>-</td>
|
||||
<td>MPU Region Base Address Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>MPU->RASR</td>
|
||||
<td>MPU_RASR</td>
|
||||
<td>-</td>
|
||||
<td>MPU Region Attribute and Size Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>MPU->RBAR_A1..3</td>
|
||||
<td>MPU_RBAR_A1..3</td>
|
||||
<td>-</td>
|
||||
<td>MPU alias Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>MPU->RASR_A1..3</td>
|
||||
<td>MPU_RASR_A1..3</td>
|
||||
<td>-</td>
|
||||
<td>MPU alias Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<th colspan="4">Floating Point Unit (FPU) Register Access [only Cortex-M4 and Cortex-M7 both with FPU]</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>FPU->FPCCR</td>
|
||||
<td>FPCCR</td>
|
||||
<td>-</td>
|
||||
<td>FP Context Control Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>FPU->FPCAR</td>
|
||||
<td>FPCAR</td>
|
||||
<td>-</td>
|
||||
<td>FP Context Address Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>FPU->FPDSCR</td>
|
||||
<td>FPDSCR</td>
|
||||
<td>-</td>
|
||||
<td>FP Default Status Control Register</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>FPU->MVFR0..1</td>
|
||||
<td>MVFR0..1</td>
|
||||
<td>-</td>
|
||||
<td>Media and VFP Feature Registers</td>
|
||||
</tr>
|
||||
</table>
|
||||
*/
|
||||
1719
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Template.txt
vendored
Normal file
1719
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Template.txt
vendored
Normal file
File diff suppressed because it is too large
Load Diff
347
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Using.txt
vendored
Normal file
347
external/CMSIS_5/CMSIS/DoxyGen/Core/src/Using.txt
vendored
Normal file
@@ -0,0 +1,347 @@
|
||||
/**
|
||||
\page using_pg Using CMSIS in Embedded Applications
|
||||
|
||||
\details
|
||||
|
||||
To use the CMSIS-Core (Cortex-M) the following files are added to the embedded application:
|
||||
- \ref startup_c_pg (formerly \ref startup_s_pg) with reset handler and exception vectors.
|
||||
- \ref system_c_pg with general device configuration (i.e. for clock and BUS setup).
|
||||
- \ref device_h_pg gives access to processor core and all peripherals.
|
||||
|
||||
\note The files \ref startup_c_pg (or \ref startup_s_pg) and \ref system_c_pg may require application specific adaptations and therefore should be copied
|
||||
into the application project folder prior configuration. The \ref device_h_pg is included in all source files that need device access
|
||||
and can be stored on a central include folder that is generic for all projects.
|
||||
|
||||
The \ref startup_c_pg (or \ref startup_s_pg) is executed after reset and calls \ref SystemInit. After the system initialization control is transferred to the C/C++ run-time
|
||||
library which performs initialization and calls the \b main function in the user code. In addition the \ref startup_c_pg (or \ref startup_s_pg) contains all exception and
|
||||
interrupt vectors and implements a default function for every interrupt. It may also contain stack and heap configurations for the user application.
|
||||
|
||||
The \ref system_c_pg performs the setup for the processor clock. The variable \ref SystemCoreClock indicates the CPU clock speed.
|
||||
\ref system_init_gr describes the minimum feature set. In addition the file may contain functions for the memory BUS setup and clock re-configuration.
|
||||
|
||||
The \ref device_h_pg is the central include file that the application programmer is using in the C source code. It provides the following features:
|
||||
- \ref peripheral_gr provides a standardized register layout for all peripherals. Optionally functions for device-specific peripherals may be available.
|
||||
- \ref NVIC_gr can be accessed with standardized symbols and functions for the Nested Interrupt Vector Controller (NVIC) are provided.
|
||||
- \ref intrinsic_CPU_gr allow to access special instructions, for example for activating sleep mode or the NOP instruction.
|
||||
- \ref intrinsic_SIMD_gr provide access to the DSP-oriented instructions.
|
||||
- \ref SysTick_gr function to configure and start a periodic timer interrupt.
|
||||
- \ref ITM_Debug_gr are functions that allow printf-style I/O via the CoreSight Debug Unit and ITM communication.
|
||||
|
||||
CMSIS-Pack provides the <b>\#define CMSIS_header_file</b> in <a href="../../Pack/html/pdsc_components_pg.html#RTE_Components_h"><b>RTE_Components.h</b></a> which gives you access to this <b><i>device</i>.h</b> file.
|
||||
|
||||
\image html "CMSIS_CORE_Files_USER.png" "CMSIS-Core (Cortex-M) User Files"
|
||||
|
||||
The CMSIS-Core (Cortex-M) system files are device specific. In addition, the deprecated \ref startup_s_pg is also compiler vendor specific.
|
||||
The versions provided by CMSIS are only generic templates. The adopted versions for a concrete device are typically provided by the device
|
||||
vendor through the according device family pack (DFP).
|
||||
|
||||
For example, the following files are provided by the STM32F10x device family pack:
|
||||
|
||||
<table class="cmtable">
|
||||
<tr>
|
||||
<th>File</th>
|
||||
<th>Description</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>".\Device\Source\ARM\startup_stm32f10x_cl.s"</td>
|
||||
<td>\ref startup_s_pg for the STM32F10x Connectivity Line device variants.</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>".\Device\Source\system_stmf10x.c"</td>
|
||||
<td>\ref system_c_pg for the STM32F10x device families.</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>".\Device\Include\stm32f10x.h"</td>
|
||||
<td>\ref device_h_pg for the STM32F10x device families.</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>".\Device\Include\system_stm32f10x.h"</td>
|
||||
<td>\ref system_Device_h_sec for the STM32F10x device families.</td>
|
||||
</tr>
|
||||
</table>
|
||||
|
||||
|
||||
\note The silicon vendors create these device-specific CMSIS-Core (Cortex-M) files based on \ref templates_pg provide by Arm.
|
||||
|
||||
Thereafter, the functions described under <a href="modules.html">\b Reference </a> can be used in the application.
|
||||
|
||||
\b Examples
|
||||
- \subpage using_CMSIS is a simple example that shows the usage of the CMSIS layer.
|
||||
- \subpage using_VTOR_pg shows how to remap the interrupt vector table.
|
||||
- \subpage using_ARM_pg explains how to use CMSIS-Core (Cortex-M) for Arm processors.
|
||||
|
||||
|
||||
\page using_CMSIS Basic CMSIS Example
|
||||
|
||||
A typical example for using the CMSIS layer is provided below. The example is based on a STM32F10x Device.
|
||||
|
||||
\code
|
||||
#include <stm32f10x.h> // File name depends on device used
|
||||
|
||||
uint32_t volatile msTicks; // Counter for millisecond Interval
|
||||
|
||||
void SysTick_Handler (void) { // SysTick Interrupt Handler
|
||||
msTicks++; // Increment Counter
|
||||
}
|
||||
|
||||
void WaitForTick (void) {
|
||||
uint32_t curTicks;
|
||||
|
||||
curTicks = msTicks; // Save Current SysTick Value
|
||||
while (msTicks == curTicks) { // Wait for next SysTick Interrupt
|
||||
__WFE (); // Power-Down until next Event/Interrupt
|
||||
}
|
||||
}
|
||||
|
||||
void TIM1_UP_IRQHandler (void) { // Timer Interrupt Handler
|
||||
; // Add user code here
|
||||
}
|
||||
|
||||
void timer1_init(int frequency) { // Set up Timer (device specific)
|
||||
NVIC_SetPriority (TIM1_UP_IRQn, 1); // Set Timer priority
|
||||
NVIC_EnableIRQ (TIM1_UP_IRQn); // Enable Timer Interrupt
|
||||
}
|
||||
|
||||
|
||||
void Device_Initialization (void) { // Configure & Initialize MCU
|
||||
if (SysTick_Config (SystemCoreClock / 1000)) { // SysTick 1mSec
|
||||
: // Handle Error
|
||||
}
|
||||
timer1_init (); // setup device-specific timer
|
||||
}
|
||||
|
||||
|
||||
// The processor clock is initialized by CMSIS startup + system file
|
||||
void main (void) { // user application starts here
|
||||
Device_Initialization (); // Configure & Initialize MCU
|
||||
while (1) { // Endless Loop (the Super-Loop)
|
||||
__disable_irq (); // Disable all interrupts
|
||||
Get_InputValues (); // Read Values
|
||||
__enable_irq (); // Enable all interrupts
|
||||
Calculation_Response (); // Calculate Results
|
||||
Output_Response (); // Output Results
|
||||
WaitForTick (); // Synchronize to SysTick Timer
|
||||
}
|
||||
}
|
||||
\endcode
|
||||
|
||||
CMSIS-Pack provides the <b>\#define CMSIS_header_file</b> in <a href="../../Pack/html/pdsc_components_pg.html#RTE_Components_h"><b>RTE_Components.h</b></a> which gives you access to the <b><i>device</i>.h</b> file
|
||||
of a project. This allows you to generate generic software components that use the device selected in a project.
|
||||
|
||||
\code
|
||||
#include "RTE_Components.h" // include information about project configuration
|
||||
#include CMSIS_device_header // include <device>.h file
|
||||
\endcode
|
||||
|
||||
\page using_VTOR_pg Using Interrupt Vector Remap
|
||||
|
||||
Most Cortex-M processors provide VTOR register for remapping interrupt vectors. The following example shows
|
||||
a typical use case where the interrupt vectors are copied to RAM and the SysTick_Handler is replaced.
|
||||
|
||||
\code
|
||||
#include "ARMCM3.h" // Device header
|
||||
|
||||
#define VECTORTABLE_SIZE (240) /* size of the used vector tables */
|
||||
/* see startup file startup_ARMCM3.c */
|
||||
#define VECTORTABLE_ALIGNMENT (0x100U) /* 16 Cortex + 32 ARMCM3 = 48 words */
|
||||
/* next power of 2 = 256 */
|
||||
|
||||
/* externals from startup_ARMCM3.c */
|
||||
extern uint32_t __VECTOR_TABLE[VECTORTABLE_SIZE]; /* vector table ROM */
|
||||
|
||||
/* new vector table in RAM, same size as vector table in ROM */
|
||||
uint32_t vectorTable_RAM[VECTORTABLE_SIZE] __attribute__(( aligned (VECTORTABLE_ALIGNMENT) ));
|
||||
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
SysTick_Handler
|
||||
*----------------------------------------------------------------------------*/
|
||||
volatile uint32_t msTicks = 0; /* counts 1ms timeTicks */
|
||||
void SysTick_Handler(void) {
|
||||
msTicks++; /* increment counter */
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
SysTick_Handler (RAM)
|
||||
*----------------------------------------------------------------------------*/
|
||||
volatile uint32_t msTicks_RAM = 0; /* counts 1ms timeTicks */
|
||||
void SysTick_Handler_RAM(void) {
|
||||
msTicks_RAM++; /* increment counter */
|
||||
}
|
||||
|
||||
/*----------------------------------------------------------------------------
|
||||
MAIN function
|
||||
*----------------------------------------------------------------------------*/
|
||||
int main (void) {
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < VECTORTABLE_SIZE; i++) {
|
||||
vectorTable_RAM[i] = __VECTOR_TABLE[i]; /* copy vector table to RAM */
|
||||
}
|
||||
/* replace SysTick Handler */
|
||||
vectorTable_RAM[SysTick_IRQn + 16] = (uint32_t)SysTick_Handler_RAM;
|
||||
|
||||
/* relocate vector table */
|
||||
__disable_irq();
|
||||
SCB->VTOR = (uint32_t)&vectorTable_RAM;
|
||||
__DSB();
|
||||
__enable_irq();
|
||||
|
||||
SystemCoreClockUpdate(); /* Get Core Clock Frequency */
|
||||
SysTick_Config(SystemCoreClock / 1000ul); /* Setup SysTick Timer for 1 msec */
|
||||
|
||||
while(1);
|
||||
}
|
||||
\endcode
|
||||
|
||||
|
||||
\page using_ARM_pg Using CMSIS with generic Arm Processors
|
||||
|
||||
Arm provides CMSIS-Core (Cortex-M) files for the supported Arm Processors and for various compiler vendors.
|
||||
These files can be used when standard Arm processors should be used in a project.
|
||||
The table below lists the folder and device names of the Arm processors.
|
||||
|
||||
<table class="cmtable">
|
||||
<tr>
|
||||
<th>Folder</th>
|
||||
<th>Processor</th>
|
||||
<th>Description</th>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>".\Device\ARM\ARMCM0"</td>
|
||||
<td>Cortex-M0</td>
|
||||
<td>Contains \b Include and \b Source template files configured for the Cortex-M0 processor.
|
||||
The device name is ARMCM0 and the name of the \ref device_h_pg is <ARMCM0.h>.
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>".\Device\ARM\ARMCM0plus"</td>
|
||||
<td>Cortex-M0+</td>
|
||||
<td>Contains \b Include and \b Source template files configured for the Cortex-M0+ processor.
|
||||
The device name is ARMCM0plus and the name of the \ref device_h_pg is <ARMCM0plus.h>.
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>".\Device\ARM\ARMCM3"</td>
|
||||
<td>Cortex-M3</td>
|
||||
<td>Contains \b Include and \b Source template files configured for the Cortex-M3 processor.
|
||||
The device name is ARMCM3 and the name of the \ref device_h_pg is <ARMCM3.h>.
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>".\Device\ARM\ARMCM4"</td>
|
||||
<td>Cortex-M4</td>
|
||||
<td>Contains \b Include and \b Source template files configured for the Cortex-M4 processor.
|
||||
The device name is ARMCM4 and the name of the \ref device_h_pg is <ARMCM4.h>.
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>".\Device\ARM\ARMCM7"</td>
|
||||
<td>Cortex-M7</td>
|
||||
<td>Contains \b Include and \b Source template files configured for the Cortex-M7 processor.
|
||||
The device name is ARMCM7 and the name of the \ref device_h_pg is <ARMCM7.h>.
|
||||
</td>
|
||||
</tr>
|
||||
\if ARMv8M
|
||||
</tr>
|
||||
<tr>
|
||||
<td>".\Device\ARM\ARMCM23"</td>
|
||||
<td>Cortex-M23</td>
|
||||
<td>Contains \b Include and \b Source template files configured for the Cortex-M23 processor.
|
||||
The device name is ARMCM23 and the name of the \ref device_h_pg is <ARMCM23.h>.
|
||||
This device is available with and without TrustZone.
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>".\Device\ARM\ARMCM33"</td>
|
||||
<td>Cortex-M33</td>
|
||||
<td>Contains \b Include and \b Source template files configured for the Cortex-M33 processor.
|
||||
The device name is ARMCM33 and the name of the \ref device_h_pg is <ARMCM33.h>.
|
||||
This device is available with and without TrustZone.
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>".\Device\ARM\ARMCM35P"</td>
|
||||
<td>Cortex-M35P</td>
|
||||
<td>Contains \b Include and \b Source template files configured for the Cortex-M35P processor.
|
||||
The device name is ARMCM35P and the name of the \ref device_h_pg is <ARMCM35P.h>.
|
||||
This device is available with and without TrustZone.
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>".\Device\ARM\ARMCM55"</td>
|
||||
<td>Cortex-M55</td>
|
||||
<td>Contains \b Include and \b Source template files configured for the Cortex-M55 processor.
|
||||
The device name is ARMCM55 and the name of the \ref device_h_pg is <ARMCM55.h>.
|
||||
This device is only available with TrustZone.
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>".\Device\ARM\ARMCM85"</td>
|
||||
<td>Cortex-M85</td>
|
||||
<td>Contains \b Include and \b Source template files configured for the Cortex-M85 processor.
|
||||
The device name is ARMCM85 and the name of the \ref device_h_pg is <ARMCM85.h>.
|
||||
This device is only available with TrustZone.
|
||||
</td>
|
||||
</tr>
|
||||
\endif
|
||||
\if ARMSC
|
||||
<tr>
|
||||
<td>".\Device\ARM\ARMSC000"</td>
|
||||
<td>SecurCore SC000</td>
|
||||
<td>Contains \b Include and \b Source template files configured for the SecurCore SC000 processor.
|
||||
The device name is ARMSC000 and the name of the \ref device_h_pg is <ARMSC000.h>.
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>".\Device\ARM\ARMSC300"</td>
|
||||
<td>SecurCore SC300</td>
|
||||
<td>Contains \b Include and \b Source template files configured for the SecurCore SC300 processor.
|
||||
The device name is ARMSC300 and the name of the \ref device_h_pg is <ARMSC300.h>.
|
||||
</td>
|
||||
</tr>
|
||||
\endif
|
||||
</table>
|
||||
|
||||
\note
|
||||
CMSIS-Pack provides the <b>\#define CMSIS_header_file</b> in <a href="../../Pack/html/pdsc_components_pg.html#RTE_Components_h"><b>RTE_Components.h</b></a> which gives you access to the <b><i>device</i>.h</b> file
|
||||
of a project. This allows you to generate generic software components that adjust to the device settings.
|
||||
|
||||
|
||||
\section using_ARM_Lib_sec Create generic Libraries with CMSIS
|
||||
|
||||
The CMSIS Processor and Core Peripheral files allow also to create generic libraries.
|
||||
The <a href="../../DSP/html/index.html">\b CMSIS-DSP </a> Libraries are an example for such a generic library.
|
||||
|
||||
To build a generic Library set the define \b __CMSIS_GENERIC and include the relevant <b>core_<cpu>.h</b> CMSIS CPU & Core Access header file for the processor.
|
||||
The define <b>__CMSIS_GENERIC</b> disables device-dependent features such as the <b>SysTick</b> timer and the <b>Interrupt System</b>.
|
||||
Refer to \ref core_config_sect for a list of the available <b>core_<cpu>.h</b> header files.
|
||||
|
||||
\b Example:
|
||||
|
||||
The following code section shows the usage of the <b>core_<cpu>.h</b> header files to build a generic library for Cortex-M0, Cortex-M3, Cortex-M4, or Cortex-M7. To
|
||||
select the processor, the source code uses the define \b CORTEX_M7, \b CORTEX_M4, \b CORTEX_M3, \b CORTEX_M0, or \b CORTEX_M0PLUS. One of these defines needs to be provided
|
||||
on the compiler command line. By using this header file, the source code can access the functions for \ref Core_Register_gr, \ref intrinsic_CPU_gr, \ref intrinsic_SIMD_gr,
|
||||
and \ref ITM_Debug_gr.
|
||||
|
||||
\code
|
||||
#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
|
||||
|
||||
#if defined (CORTEX_M7)
|
||||
#include "core_cm7.h"
|
||||
#elif defined (CORTEX_M4)
|
||||
#include "core_cm4.h"
|
||||
#elif defined (CORTEX_M3)
|
||||
#include "core_cm3.h"
|
||||
#elif defined (CORTEX_M0)
|
||||
#include "core_cm0.h"
|
||||
#elif defined (CORTEX_M0PLUS)
|
||||
#include "core_cm0plus.h"
|
||||
#else
|
||||
#error "Processor not specified or unsupported."
|
||||
#endif
|
||||
|
||||
\endcode
|
||||
|
||||
|
||||
*/
|
||||
165
external/CMSIS_5/CMSIS/DoxyGen/Core/src/UsingTrustZone.txt
vendored
Normal file
165
external/CMSIS_5/CMSIS/DoxyGen/Core/src/UsingTrustZone.txt
vendored
Normal file
@@ -0,0 +1,165 @@
|
||||
/**
|
||||
\cond (ARMv8M)
|
||||
*/
|
||||
|
||||
/**
|
||||
\page using_TrustZone_pg Using TrustZone for Armv8-M
|
||||
|
||||
|
||||
\details
|
||||
The optional Armv8-M Security Extension is similar to Arm TrustZone technology used in Cortex-A processors, but is
|
||||
optimized for ultra-low power embedded applications. TrustZone for Armv8-M enables of multiple software security
|
||||
domains that restrict access to secure memory and I/O only for trusted software.
|
||||
|
||||
TrustZone for Armv8-M:
|
||||
- preserves low interrupt latencies for both Secure and Non-secure domains.
|
||||
- does not impose code overhead, cycle overhead or the complexity of a virtualization based solution.
|
||||
- introduces the Secure Gateway (SG) processor instruction for calls to the secure domain.
|
||||
|
||||
\b Notations
|
||||
|
||||
This manual uses the following notations to identify functions and hardware resources that are related to TrustZone for Armv8-M:
|
||||
|
||||
- prefix \b TZ or \b __TZ indicates a function that is available only in Armv8-M TrustZone enabled devices.
|
||||
- postfix \b _NS indicates a hardware resource that belongs to the Non-secure state.
|
||||
- postfix \b _S indicates a hardware resource that belongs to the Secure state.
|
||||
|
||||
|
||||
\section useCase_TrustZone Simplified Use Case with TrustZone
|
||||
|
||||
An Armv8-M TrustZone enabled device has restricted access for data, code, and I/O access to trusted
|
||||
software that runs in the Secure state. Typical applications are secure IoT nodes, firmware IP protection,
|
||||
or multi-party embedded software deployments.
|
||||
|
||||
The figure <b>Simplified Use Case</b> shows and embedded application that is split into a <b>User Project</b>
|
||||
(executed in Non-secure state) and a <b>Firmware Project</b> (executed in Secure state).
|
||||
|
||||
- <b>System Start:</b> after power on or reset, an Armv8-M system starts code execution in the <b>Secure state</b>. The access rights for the <b>Non-secure state</b> is configured.
|
||||
|
||||
- <b>User Application:</b> control can be transferred to <b>Non-secure state</b> to execute user code. This code can only call functions in the <b>secure state</b> that are marked for execution with the <b>SG</b> (secure gate) instruction and memory attributes. Any attempt to access memory or peripherals that are assigned to the <b>Secure state</b> triggers a security exception.
|
||||
|
||||
- <b>Firmware callbacks:</b> code running in the <b>Secure state</b> can execute code in the <b>Non-secure state</b> using call-back function pointers. For example, a communication stack (protected firmware) could use an I/O driver that is configured in user space.
|
||||
|
||||
\anchor SimpleUseCase
|
||||
\image html "SimpleUseCase.png" "Simplified Use Case"
|
||||
|
||||
Program execution in the <b>Secure state</b> is further protected by TrustZone hardware from software failures.
|
||||
For example, an Armv8-M system may implement two independent SYSTICK timers which allows to stop code execution
|
||||
in <b>Non-secure state</b> in case of timing violations. Also function pointer callbacks from <b>Secure state</b>
|
||||
to <b>Non-secure state</b> protected by a special CPU instruction and the address bit 0 which prevents anciently
|
||||
executing code in <b>Non-secure state</b>.
|
||||
|
||||
\subsection Example_TrustZone Program Examples
|
||||
|
||||
This CMSIS software pack contains the following program examples that show the usage of TrustZone for Armv8-M on Cortex-M33 devices:
|
||||
|
||||
Example | Description
|
||||
:-------------------------------------------|:----------------
|
||||
TrustZone for Armv8-M No RTOS | bare-metal secure/non-secure programming without RTOS (shows the Simplified Use Case).
|
||||
TrustZone for Armv8-M RTOS | secure/non-secure RTOS example with thread context management
|
||||
TrustZone for Armv8-M RTOS Security Tests | secure/non-secure RTOS example with security test cases and system recovery
|
||||
|
||||
Other sample application that reflects this <a href="#SimpleUseCase"><b>Simplified Use Case</b></a> is the <b>Armv8MBL Secure/Non-Secure example</b> that is available in
|
||||
the Software Pack <b>Keil - Arm V2M-MPS2 Board Support PACK for Cortex-M System Design Kit Devices</b>
|
||||
(Keil:V2M-MPS2_CMx_BSP.1.2.0.pack or higher).
|
||||
|
||||
\section Model_TrustZone Programmers Model with TrustZone
|
||||
|
||||
The figure <a href="#MemoryMap_S"><b>Secure Memory Map</b></a> shows the memory view for the <b>Secure state</b>. In the Secure state all
|
||||
memory and peripherals can be accessed. The <b>System Control and Debug</b> area provides access to secure peripherals
|
||||
and non-secure peripherals that are mirrored at a memory alias.
|
||||
|
||||
The secure peripherals are only accessible during program execution in <b>Secure state</b>. The Secure Attribute Unit (SAU)
|
||||
configures the non-secure memory, peripheral, and interrupt access. Also available are a secure MPU (memory protection
|
||||
unit), secure SCB (system control block), and secure SysTick timer.
|
||||
|
||||
The system supports two separate interrupt vector tables for secure and non-secure code execution.
|
||||
This interrupt assignment is controlled during <b>Secure state</b> code execution via the NVIC
|
||||
(nested vector interrupt controller).
|
||||
|
||||
\anchor MemoryMap_S
|
||||
\image html "MemoryMap_S.png" "Secure Memory Map"
|
||||
|
||||
The figure <a href="#MemoryMap_NS"><b>Non-Secure Memory Map</b></a> shows the memory view for the Non-secure state. This memory view is identical
|
||||
to the traditional Cortex-M memory map. Access to any secure memory or peripheral space triggers the secure exception
|
||||
that executes a handler in <b>Secure state</b>.
|
||||
|
||||
The \ref partition_h_pg defines the initial setup of the <a href="#MemoryMap_NS"><b>Non-Secure Memory Map</b></a> during system start in the Secure state
|
||||
(refer to functions \ref SystemInit and \ref TZ_SAU_Setup).
|
||||
|
||||
<!-- <img id="MemoryMap_NS" src="MemoryMap_NS.png"><CENTER><b>Non-Secure Memory Map</b></CENTER> -->
|
||||
|
||||
\anchor MemoryMap_NS
|
||||
\image html "MemoryMap_NS.png" "Non-Secure Memory Map"
|
||||
|
||||
The figure <b>Registers</b> shows the register view of the Armv8-M system with TrustZone. As the general purpose registers
|
||||
are can be accessed from any state (secure or non-secure), function calls between the states use these registers for parameter
|
||||
and return values.
|
||||
|
||||
The register R13 is the stack pointer alias, and the actual stack pointer (PSP_NS, MSP_NS, PSP_S, MSP_S)
|
||||
accessed depends on state (Secure or Non-secure) and mode (handler=exception/interrupt execution or
|
||||
thread=normal code execution).
|
||||
|
||||
In Armv8-M Mainline, each stack pointer has a limit register (PSPLIM_NS, MSPLIM_NS, PSPLIM_S, MSPLIM_S)
|
||||
that traps stack overflows with the \b UsageFault exception (register UFSR bit STKOF=1).
|
||||
|
||||
An Armv8-M system with TrustZone has an independent \b CONTROL register for each state (Secure or Non-secure).
|
||||
The interrupt/exception control registers (PRIMASK, FAULTMASK, BASEPRI) are banked between the states (Secure or Non-secure),
|
||||
however the interrupt priority for the Non-Secure state can be lowered (SCB_AIRCR register bit PRIS) so that
|
||||
secure interrupts have always higher priority.
|
||||
|
||||
The core registers of the current state (Secure or Non-secure) are accessed using the standard \ref Core_Register_gr
|
||||
functions. In Secure state all non-secure registers are accessible using the \ref coreregister_trustzone_functions
|
||||
related to TrustZone for Armv8-M.
|
||||
|
||||
\image html "Registers.png" "Registers"
|
||||
|
||||
\subsection RTOS_TrustZone_stacksealing Stack Sealing
|
||||
|
||||
CMSIS-Core \ref stacksealing_support_trustzone_functions provide standard interface for implementing the <a href="https://developer.arm.com/support/arm-security-updates/armv8-m-stack-sealing" target="_blank"><b>Secure Stack Sealing technique</b></a> recommended for mitigating some security vulnerabilities on Armv8-M systems with TrustZone.
|
||||
|
||||
\ref startup_c_sec_v8 demonstrates how this functionality can be used in a device startup file.
|
||||
|
||||
Stack Sealing also requires an application project to have a linker script that explicitly reserves 8 bytes for the stack seal on top of the secure main stack. Linker files provided with \ref device_examples for Armv8-M cores demonstrate how this can be implemented. For example see .\\Device\\ARM\\ARMCM33\\Source\\ARM\\ARMCM33_ac6.sct.
|
||||
|
||||
To learn more about the stack sealing implementation in CMSIS projects for Armv8-M devices, refer to
|
||||
<a href="https://www.keil.com/appnotes/docs/apnt_335.asp" target="_blank"><b>Application Note 335</b></a>.
|
||||
|
||||
\section CMSIS_Files_TrustZone CMSIS Files for TrustZone
|
||||
|
||||
The CMSIS-Core files are extended by the header files \ref partition_h_pg and \ref partition_gen_h_pg :
|
||||
|
||||
- The file \ref partition_h_pg "partition_<device>.h" defines the initial system configuration and during SystemInit in Secure state.
|
||||
- The file \ref partition_gen_h_pg "partition_gen.h" is optional and contains SAU region and interrupt target assignments. This file may be generated using CMSIS-Zone.
|
||||
|
||||
\note
|
||||
Refer to \ref using_pg for a general description of the CMSIS-Core (Cortex-M) files.
|
||||
|
||||
\image html "CMSIS_TZ_files.png" "CMSIS with extensions for TrustZone"
|
||||
|
||||
|
||||
|
||||
\subsection RTOS_TrustZone RTOS Thread Context Management
|
||||
|
||||
To provide a consistent RTOS thread context management for Armv8-M TrustZone across the various real-time operating systems (RTOS), the CMSIS-Core (Cortex-M) includes header file <b>TZ_context.h</b> with API definitions.
|
||||
An <i>non-secure application</i> which uses an RTOS and calls <i>secure</i> library modules requires the management of the <i>secure</i> stack space. Since <i>secure state</i> registers cannot be accessed
|
||||
by the RTOS that runs in <i>non-secure state</i> secure functions implement the thread context switch.
|
||||
|
||||
As the <i>non-secure state</i> and <i>secure state</i> parts of an application are separated, the API for managing the <i>secure</i> stack space should be standardized. Otherwise the <i>secure</i> library modules
|
||||
would force the <i>non-secure state</i> application to use a matching RTOS implementation.
|
||||
|
||||
\image html "TZ_context.png" "RTOS Thread Context Management for Armv8-M TrustZone"
|
||||
|
||||
To allocate the context memory for threads, an RTOS kernel that runs in <i>non-secure state</i> calls the interface functions defined by the header file <b>TZ_context.h</b>. The <b>TZ_context</b> functions itself are
|
||||
part of the <i>secure state</i> application. An minimum implementation is provided as part of RTOS2 and should handle the secure stack for the thread execution. However it is also possible to implement the context memory
|
||||
management system with additional features such as access control to <i>secure state</i> memory regions using an MPU.
|
||||
|
||||
The API functions of <b>TZ_context</b> are described in the chapter <a href="modules.html">\b Reference </a> under \ref trustzone_functions - \ref context_trustzone_functions.
|
||||
|
||||
Refer to \ref Example_TrustZone for RTOS examples that provide a template implementation for <b>TZ_context.c</b>.
|
||||
|
||||
*/
|
||||
|
||||
/**
|
||||
\endcond
|
||||
*/
|
||||
176
external/CMSIS_5/CMSIS/DoxyGen/Core/src/core_cm7.txt
vendored
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176
external/CMSIS_5/CMSIS/DoxyGen/Core/src/core_cm7.txt
vendored
Normal file
@@ -0,0 +1,176 @@
|
||||
/**
|
||||
\defgroup cache_functions_m7 Cache Functions (Level-1)
|
||||
\brief Functions for level-1 instruction and data cache.
|
||||
\details
|
||||
Enhanced Cortex processors (like M7 and M55) include a memory system, which includes an optional
|
||||
Harvard level-1 data and instruction cache with ECC. The optional CPU cache has an instruction
|
||||
and data cache with sizes of \token{[0;4;8;16;32;64]KB}.
|
||||
Both instruction and data cache RAM can be configured at implementation time to have Error
|
||||
Correcting Code (ECC) to protect the data stored in the memory from errors.
|
||||
|
||||
All cache maintenance operations are executed by writing to registers in the memory mapped
|
||||
System Control Space (SCS) region of the internal PPB memory space.
|
||||
|
||||
\note
|
||||
After reset, you must invalidate each cache before enabling it.
|
||||
|
||||
The functions are grouped for:
|
||||
- \ref Icache_functions_m7
|
||||
- \ref Dcache_functions_m7
|
||||
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\defgroup Icache_functions_m7 I-Cache Functions
|
||||
\brief Functions for the level-1 instruction cache.
|
||||
@{
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Enable I-Cache.
|
||||
|
||||
The function turns on the instruction cache.
|
||||
\note
|
||||
Before enabling the instruction cache, you must invalidate (\ref SCB_InvalidateICache) the entire instruction cache if
|
||||
external memory might have changed since the cache was disabled.
|
||||
\note
|
||||
After reset, you must invalidate (\ref SCB_InvalidateICache) each cache before enabling it.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_EnableICache (void);
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable I-Cache.
|
||||
|
||||
The function turns off the instruction cache.
|
||||
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_DisableICache (void);
|
||||
|
||||
|
||||
/**
|
||||
\brief Invalidate I-Cache.
|
||||
|
||||
The function invalidates the instruction cache.
|
||||
The instruction cache is never dirty so cache RAM errors are always recoverable by invalidating the cache and retrying the instruction.
|
||||
\note
|
||||
After reset, you must invalidate each cache before enabling (\ref SCB_EnableICache) it.
|
||||
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateICache (void);
|
||||
|
||||
|
||||
/**
|
||||
\brief I-Cache Invalidate by address
|
||||
\details Invalidates I-Cache for the given address.
|
||||
I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||
I-Cache memory blocks which are part of given address + given size are invalidated.
|
||||
\param[in] addr address
|
||||
\param[in] isize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize);
|
||||
|
||||
/**
|
||||
@} // close ICache functions
|
||||
*/
|
||||
|
||||
/**
|
||||
\defgroup Dcache_functions_m7 D-Cache Functions
|
||||
\brief Functions for the level-1 data cache.
|
||||
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Enable D-Cache.
|
||||
|
||||
The function turns on the entire data cache.
|
||||
\note
|
||||
Before enabling the data cache, you must invalidate the entire data cache (\ref SCB_InvalidateDCache), because external
|
||||
memory might have changed from when the cache was disabled.
|
||||
|
||||
\note
|
||||
After reset, you must invalidate (\ref SCB_InvalidateDCache) each cache before enabling it.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_EnableDCache (void);
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable D-Cache.
|
||||
|
||||
The function turns off the entire data cache.
|
||||
|
||||
\note
|
||||
When disabling the data cache, you must clean (\ref SCB_CleanDCache) the entire cache to ensure that any dirty data is
|
||||
flushed to external memory.
|
||||
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_DisableDCache (void);
|
||||
|
||||
|
||||
/**
|
||||
\brief Invalidate D-Cache.
|
||||
|
||||
The function invalidates the entire data cache.
|
||||
|
||||
\note
|
||||
After reset, you must invalidate each cache before enabling (\ref SCB_EnableDCache) it.
|
||||
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateDCache (void);
|
||||
|
||||
|
||||
/**
|
||||
\brief Clean D-Cache.
|
||||
|
||||
The function cleans the entire data cache.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanDCache (void);
|
||||
|
||||
|
||||
/**
|
||||
\brief Clean & Invalidate D-Cache.
|
||||
|
||||
The function cleans and invalidates the entire data cache.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void);
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Invalidate by address
|
||||
\param[in] addr address (aligned to 32-byte boundary)
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
|
||||
The function invalidates a memory block of size \em dsize [bytes] starting at address \em address. The address is aligned to 32-byte boundary.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize);
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Clean by address
|
||||
\param[in] addr address (aligned to 32-byte boundary)
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
|
||||
The function cleans a memory block of size \em dsize [bytes] starting at address \em address. The address is aligned to 32-byte boundary.
|
||||
|
||||
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize);
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Clean and Invalidate by address
|
||||
\param[in] addr address (aligned to 32-byte boundary)
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
|
||||
The function invalidates and cleans a memory block of size \em dsize [bytes] starting at address \em address. The address is aligned to 32-byte boundary.
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize);
|
||||
|
||||
/**
|
||||
@} // close D-Cache Functions
|
||||
@}
|
||||
*/
|
||||
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external/CMSIS_5/CMSIS/DoxyGen/Core/src/images/ARMv8-M_images.pptx
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|
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|
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external/CMSIS_5/CMSIS/DoxyGen/Core/src/images/Registers.png
vendored
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|
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external/CMSIS_5/CMSIS/DoxyGen/Core/src/images/SimpleUseCase.png
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|
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BIN
external/CMSIS_5/CMSIS/DoxyGen/Core/src/images/TZ_context.png
vendored
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external/CMSIS_5/CMSIS/DoxyGen/Core/src/images/TZ_context.png
vendored
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|
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Reference in New Issue
Block a user