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external/CMSIS_5/Device/ARM/ARMCA7/Source/mmu_ARMCA7.c
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external/CMSIS_5/Device/ARM/ARMCA7/Source/mmu_ARMCA7.c
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/**************************************************************************//**
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* @file mmu_ARMCA7.c
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* @brief MMU Configuration for Arm Cortex-A7 Device Series
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* @version V1.2.0
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* @date 15. May 2019
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*
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* @note
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*
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******************************************************************************/
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/*
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* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/* Memory map description from: DUI0447G_v2m_p1_trm.pdf 4.2.2 Arm Cortex-A Series memory map
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Memory Type
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0xffffffff |--------------------------| ------------
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| FLAG SYNC | Device Memory
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0xfffff000 |--------------------------| ------------
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| Fault | Fault
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0xfff00000 |--------------------------| ------------
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| | Normal
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| |
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| Daughterboard |
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| memory |
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| |
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0x80505000 |--------------------------| ------------
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|TTB (L2 Sync Flags ) 4k | Normal
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0x80504C00 |--------------------------| ------------
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|TTB (L2 Peripherals-B) 16k| Normal
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0x80504800 |--------------------------| ------------
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|TTB (L2 Peripherals-A) 16k| Normal
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0x80504400 |--------------------------| ------------
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|TTB (L2 Priv Periphs) 4k | Normal
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0x80504000 |--------------------------| ------------
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| TTB (L1 Descriptors) | Normal
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0x80500000 |--------------------------| ------------
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| Stack | Normal
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|--------------------------| ------------
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| Heap | Normal
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0x80400000 |--------------------------| ------------
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| ZI Data | Normal
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0x80300000 |--------------------------| ------------
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| RW Data | Normal
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0x80200000 |--------------------------| ------------
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| RO Data | Normal
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|--------------------------| ------------
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| RO Code | USH Normal
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0x80000000 |--------------------------| ------------
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| Daughterboard | Fault
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| HSB AXI buses |
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0x40000000 |--------------------------| ------------
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| Daughterboard | Fault
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| test chips peripherals |
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0x2c002000 |--------------------------| ------------
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| Private Address | Device Memory
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0x2c000000 |--------------------------| ------------
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| Daughterboard | Fault
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| test chips peripherals |
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0x20000000 |--------------------------| ------------
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| Peripherals | Device Memory RW/RO
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| | & Fault
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0x00000000 |--------------------------|
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*/
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// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
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// Write-Through support *not* available
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// Write-Back support available.
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// Read allocation support available.
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// Write allocation support available.
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//Note: You should use the Shareable attribute carefully.
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//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
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//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
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//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
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//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
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//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
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//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
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//Following MMU configuration is expected
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//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
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//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
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//Domain 0 is always the Client domain
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//Descriptors should place all memory in domain 0
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#include "ARMCA7.h"
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#include "mem_ARMCA7.h"
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// TTB base address
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#define TTB_BASE ((uint32_t*)__TTB_BASE)
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// L2 table pointers
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//----------------------------------------
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#define TTB_L1_SIZE (0x00004000) // The L1 translation table divides the full 4GB address space of a 32-bit core
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// into 4096 equally sized sections, each of which describes 1MB of virtual memory space.
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// The L1 translation table therefore contains 4096 32-bit (word-sized) entries.
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#define PRIVATE_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE) // Map 4k Private Address space
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#define PERIPHERAL_A_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x400) // Map 64k Peripheral #1 0x1C000000 - 0x1C00FFFFF
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#define PERIPHERAL_B_TABLE_L2_BASE_64k (__TTB_BASE + TTB_L1_SIZE + 0x800) // Map 64k Peripheral #2 0x1C100000 - 0x1C1FFFFFF
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#define SYNC_FLAGS_TABLE_L2_BASE_4k (__TTB_BASE + TTB_L1_SIZE + 0xC00) // Map 4k Flag synchronization
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//--------------------- PERIPHERALS -------------------
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#define PERIPHERAL_A_FAULT (0x00000000 + 0x1c000000) //0x1C000000-0x1C00FFFF (1M)
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#define PERIPHERAL_B_FAULT (0x00100000 + 0x1c000000) //0x1C100000-0x1C10FFFF (1M)
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//--------------------- SYNC FLAGS --------------------
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#define FLAG_SYNC 0xFFFFF000
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#define F_SYNC_BASE 0xFFF00000 //1M aligned
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static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
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static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
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static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
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static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
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static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
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static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
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/* Define global descriptors */
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static uint32_t Page_L1_4k = 0x0; //generic
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static uint32_t Page_L1_64k = 0x0; //generic
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static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
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static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
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void MMU_CreateTranslationTable(void)
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{
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mmu_region_attributes_Type region;
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//Create 4GB of faulting entries
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MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT);
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/*
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* Generate descriptors. Refer to core_ca.h to get information about attributes
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*
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*/
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//Create descriptors for Vectors, RO, RW, ZI sections
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section_normal(Sect_Normal, region);
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section_normal_cod(Sect_Normal_Cod, region);
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section_normal_ro(Sect_Normal_RO, region);
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section_normal_rw(Sect_Normal_RW, region);
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//Create descriptors for peripherals
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section_device_ro(Sect_Device_RO, region);
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section_device_rw(Sect_Device_RW, region);
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//Create descriptors for 64k pages
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page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
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//Create descriptors for 4k pages
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page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
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/*
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* Define MMU flat-map regions and attributes
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*
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*/
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//Define Image
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MMU_TTSection (TTB_BASE, __ROM_BASE, __ROM_SIZE/0x100000, Sect_Normal_Cod); // multiple of 1MB sections
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MMU_TTSection (TTB_BASE, __RAM_BASE, __RAM_SIZE/0x100000, Sect_Normal_RW); // multiple of 1MB sections
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//--------------------- PERIPHERALS -------------------
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MMU_TTSection (TTB_BASE, VE_A7_MP_FLASH_BASE0 , 64, Sect_Device_RO); // 64MB NOR
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MMU_TTSection (TTB_BASE, VE_A7_MP_FLASH_BASE1 , 64, Sect_Device_RO); // 64MB NOR
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MMU_TTSection (TTB_BASE, VE_A7_MP_SRAM_BASE , 32, Sect_Device_RW); // 32MB RAM
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MMU_TTSection (TTB_BASE, VE_A7_MP_VRAM_BASE , 32, Sect_Device_RW); // 32MB RAM
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MMU_TTSection (TTB_BASE, VE_A7_MP_ETHERNET_BASE , 16, Sect_Device_RW);
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MMU_TTSection (TTB_BASE, VE_A7_MP_USB_BASE , 16, Sect_Device_RW);
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// Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C000000-0x1C00FFFF
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MMU_TTPage64k(TTB_BASE, PERIPHERAL_A_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
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// Define peripheral range 0x1C000000-0x1C00FFFF
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MMU_TTPage64k(TTB_BASE, VE_A7_MP_DAP_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
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MMU_TTPage64k(TTB_BASE, VE_A7_MP_SYSTEM_REG_BASE, 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
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MMU_TTPage64k(TTB_BASE, VE_A7_MP_SERIAL_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
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MMU_TTPage64k(TTB_BASE, VE_A7_MP_AACI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
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MMU_TTPage64k(TTB_BASE, VE_A7_MP_MMCI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
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MMU_TTPage64k(TTB_BASE, VE_A7_MP_KMI0_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
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MMU_TTPage64k(TTB_BASE, VE_A7_MP_UART_BASE , 4, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
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MMU_TTPage64k(TTB_BASE, VE_A7_MP_WDT_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_A_TABLE_L2_BASE_64k, Page_64k_Device_RW);
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// Create (16 * 64k)=1MB faulting entries to cover peripheral range 0x1C100000-0x1C10FFFF
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MMU_TTPage64k(TTB_BASE, PERIPHERAL_B_FAULT , 16, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, DESCRIPTOR_FAULT);
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// Define peripheral range 0x1C100000-0x1C10FFFF
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MMU_TTPage64k(TTB_BASE, VE_A7_MP_TIMER_BASE , 2, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
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MMU_TTPage64k(TTB_BASE, VE_A7_MP_DVI_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
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MMU_TTPage64k(TTB_BASE, VE_A7_MP_RTC_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
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MMU_TTPage64k(TTB_BASE, VE_A7_MP_UART4_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
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MMU_TTPage64k(TTB_BASE, VE_A7_MP_CLCD_BASE , 1, Page_L1_64k, (uint32_t *)PERIPHERAL_B_TABLE_L2_BASE_64k, Page_64k_Device_RW);
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// Create (256 * 4k)=1MB faulting entries to cover private address space. Needs to be marked as Device memory
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MMU_TTPage4k (TTB_BASE, __get_CBAR() ,256, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
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// Define private address space entry.
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MMU_TTPage4k (TTB_BASE, __get_CBAR() , 3, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
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// Define L2CC entry. Uncomment if PL310 is present
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// MMU_TTPage4k (TTB_BASE, VE_A5_MP_PL310_BASE , 1, Page_L1_4k, (uint32_t *)PRIVATE_TABLE_L2_BASE_4k, Page_4k_Device_RW);
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// Create (256 * 4k)=1MB faulting entries to synchronization space (Useful if some non-cacheable DMA agent is present in the SoC)
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MMU_TTPage4k (TTB_BASE, F_SYNC_BASE , 256, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, DESCRIPTOR_FAULT);
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// Define synchronization space entry.
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MMU_TTPage4k (TTB_BASE, FLAG_SYNC , 1, Page_L1_4k, (uint32_t *)SYNC_FLAGS_TABLE_L2_BASE_4k, Page_4k_Device_RW);
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/* Set location of level 1 page table
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; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
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; 13:7 - 0x0
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; 6 - IRGN[0] 0x1 (Inner WB WA)
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; 5 - NOS 0x0 (Non-shared)
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; 4:3 - RGN 0x01 (Outer WB WA)
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; 2 - IMP 0x0 (Implementation Defined)
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; 1 - S 0x0 (Non-shared)
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; 0 - IRGN[1] 0x0 (Inner WB WA) */
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__set_TTBR0(__TTB_BASE | 0x48);
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__ISB();
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/* Set up domain access control register
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; We set domain 0 to Client and all other domains to No Access.
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; All translation table entries specify domain 0 */
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__set_DACR(1);
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__ISB();
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}
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