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This commit is contained in:
Armel FAUVEAU
2024-08-16 00:11:09 +02:00
parent 7c53df8d2b
commit 74862d1ac2
95 changed files with 15257 additions and 15258 deletions
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178
driver/adc.c
View File

@@ -22,40 +22,40 @@
uint8_t ADC_GetChannelNumber(ADC_CH_MASK Mask)
{
if (Mask & ADC_CH15) return 15U;
if (Mask & ADC_CH14) return 14U;
if (Mask & ADC_CH13) return 13U;
if (Mask & ADC_CH12) return 12U;
if (Mask & ADC_CH11) return 11U;
if (Mask & ADC_CH10) return 10U;
if (Mask & ADC_CH9) return 9U;
if (Mask & ADC_CH8) return 8U;
if (Mask & ADC_CH7) return 7U;
if (Mask & ADC_CH6) return 6U;
if (Mask & ADC_CH5) return 5U;
if (Mask & ADC_CH4) return 4U;
if (Mask & ADC_CH3) return 3U;
if (Mask & ADC_CH2) return 2U;
if (Mask & ADC_CH1) return 1U;
if (Mask & ADC_CH0) return 0U;
if (Mask & ADC_CH15) return 15U;
if (Mask & ADC_CH14) return 14U;
if (Mask & ADC_CH13) return 13U;
if (Mask & ADC_CH12) return 12U;
if (Mask & ADC_CH11) return 11U;
if (Mask & ADC_CH10) return 10U;
if (Mask & ADC_CH9) return 9U;
if (Mask & ADC_CH8) return 8U;
if (Mask & ADC_CH7) return 7U;
if (Mask & ADC_CH6) return 6U;
if (Mask & ADC_CH5) return 5U;
if (Mask & ADC_CH4) return 4U;
if (Mask & ADC_CH3) return 3U;
if (Mask & ADC_CH2) return 2U;
if (Mask & ADC_CH1) return 1U;
if (Mask & ADC_CH0) return 0U;
return 0U;
return 0U;
}
void ADC_Disable(void)
{
SARADC_CFG = (SARADC_CFG & ~SARADC_CFG_ADC_EN_MASK) | SARADC_CFG_ADC_EN_BITS_DISABLE;
SARADC_CFG = (SARADC_CFG & ~SARADC_CFG_ADC_EN_MASK) | SARADC_CFG_ADC_EN_BITS_DISABLE;
}
void ADC_Enable(void)
{
SARADC_CFG = (SARADC_CFG & ~SARADC_CFG_ADC_EN_MASK) | SARADC_CFG_ADC_EN_BITS_ENABLE;
SARADC_CFG = (SARADC_CFG & ~SARADC_CFG_ADC_EN_MASK) | SARADC_CFG_ADC_EN_BITS_ENABLE;
}
void ADC_SoftReset(void)
{
SARADC_START = (SARADC_START & ~SARADC_START_SOFT_RESET_MASK) | SARADC_START_SOFT_RESET_BITS_ASSERT;
SARADC_START = (SARADC_START & ~SARADC_START_SOFT_RESET_MASK) | SARADC_START_SOFT_RESET_BITS_DEASSERT;
SARADC_START = (SARADC_START & ~SARADC_START_SOFT_RESET_MASK) | SARADC_START_SOFT_RESET_BITS_ASSERT;
SARADC_START = (SARADC_START & ~SARADC_START_SOFT_RESET_MASK) | SARADC_START_SOFT_RESET_BITS_DEASSERT;
}
// The firmware thinks W_SARADC_SMPL_CLK_SEL is at [8:7] but the TRM says it's at [10:9]
@@ -64,102 +64,102 @@ void ADC_SoftReset(void)
uint32_t ADC_GetClockConfig(void)
{
uint32_t Value;
uint32_t Value;
Value = SYSCON_CLK_SEL;
Value = SYSCON_CLK_SEL;
Value = 0
| (Value & ~(SYSCON_CLK_SEL_R_PLL_MASK | FW_R_SARADC_SMPL_MASK))
| (((Value & SYSCON_CLK_SEL_R_PLL_MASK) >> SYSCON_CLK_SEL_R_PLL_SHIFT) << SYSCON_CLK_SEL_W_PLL_SHIFT)
| (((Value & FW_R_SARADC_SMPL_MASK) >> FW_R_SARADC_SMPL_SHIFT) << SYSCON_CLK_SEL_W_SARADC_SMPL_SHIFT)
;
Value = 0
| (Value & ~(SYSCON_CLK_SEL_R_PLL_MASK | FW_R_SARADC_SMPL_MASK))
| (((Value & SYSCON_CLK_SEL_R_PLL_MASK) >> SYSCON_CLK_SEL_R_PLL_SHIFT) << SYSCON_CLK_SEL_W_PLL_SHIFT)
| (((Value & FW_R_SARADC_SMPL_MASK) >> FW_R_SARADC_SMPL_SHIFT) << SYSCON_CLK_SEL_W_SARADC_SMPL_SHIFT)
;
return Value;
return Value;
}
void ADC_Configure(ADC_Config_t *pAdc)
{
SYSCON_DEV_CLK_GATE = (SYSCON_DEV_CLK_GATE & ~SYSCON_DEV_CLK_GATE_SARADC_MASK) | SYSCON_DEV_CLK_GATE_SARADC_BITS_ENABLE;
SYSCON_DEV_CLK_GATE = (SYSCON_DEV_CLK_GATE & ~SYSCON_DEV_CLK_GATE_SARADC_MASK) | SYSCON_DEV_CLK_GATE_SARADC_BITS_ENABLE;
ADC_Disable();
ADC_Disable();
SYSCON_CLK_SEL = (ADC_GetClockConfig() & ~SYSCON_CLK_SEL_W_SARADC_SMPL_MASK) | ((pAdc->CLK_SEL << SYSCON_CLK_SEL_W_SARADC_SMPL_SHIFT) & SYSCON_CLK_SEL_W_SARADC_SMPL_MASK);
SYSCON_CLK_SEL = (ADC_GetClockConfig() & ~SYSCON_CLK_SEL_W_SARADC_SMPL_MASK) | ((pAdc->CLK_SEL << SYSCON_CLK_SEL_W_SARADC_SMPL_SHIFT) & SYSCON_CLK_SEL_W_SARADC_SMPL_MASK);
SARADC_CFG = 0
| (SARADC_CFG & ~(0
| SARADC_CFG_CH_SEL_MASK
| SARADC_CFG_AVG_MASK
| SARADC_CFG_CONT_MASK
| SARADC_CFG_SMPL_SETUP_MASK
| SARADC_CFG_MEM_MODE_MASK
| SARADC_CFG_SMPL_CLK_MASK
| SARADC_CFG_SMPL_WIN_MASK
| SARADC_CFG_ADC_TRIG_MASK
| SARADC_CFG_DMA_EN_MASK
))
| ((pAdc->CH_SEL << SARADC_CFG_CH_SEL_SHIFT) & SARADC_CFG_CH_SEL_MASK)
| ((pAdc->AVG << SARADC_CFG_AVG_SHIFT) & SARADC_CFG_AVG_MASK)
| ((pAdc->CONT << SARADC_CFG_CONT_SHIFT) & SARADC_CFG_CONT_MASK)
| ((pAdc->SMPL_SETUP << SARADC_CFG_SMPL_SETUP_SHIFT) & SARADC_CFG_SMPL_SETUP_MASK)
| ((pAdc->MEM_MODE << SARADC_CFG_MEM_MODE_SHIFT) & SARADC_CFG_MEM_MODE_MASK)
| ((pAdc->SMPL_CLK << SARADC_CFG_SMPL_CLK_SHIFT) & SARADC_CFG_SMPL_CLK_MASK)
| ((pAdc->SMPL_WIN << SARADC_CFG_SMPL_WIN_SHIFT) & SARADC_CFG_SMPL_WIN_MASK)
| ((pAdc->ADC_TRIG << SARADC_CFG_ADC_TRIG_SHIFT) & SARADC_CFG_ADC_TRIG_MASK)
| ((pAdc->DMA_EN << SARADC_CFG_DMA_EN_SHIFT) & SARADC_CFG_DMA_EN_MASK)
;
SARADC_CFG = 0
| (SARADC_CFG & ~(0
| SARADC_CFG_CH_SEL_MASK
| SARADC_CFG_AVG_MASK
| SARADC_CFG_CONT_MASK
| SARADC_CFG_SMPL_SETUP_MASK
| SARADC_CFG_MEM_MODE_MASK
| SARADC_CFG_SMPL_CLK_MASK
| SARADC_CFG_SMPL_WIN_MASK
| SARADC_CFG_ADC_TRIG_MASK
| SARADC_CFG_DMA_EN_MASK
))
| ((pAdc->CH_SEL << SARADC_CFG_CH_SEL_SHIFT) & SARADC_CFG_CH_SEL_MASK)
| ((pAdc->AVG << SARADC_CFG_AVG_SHIFT) & SARADC_CFG_AVG_MASK)
| ((pAdc->CONT << SARADC_CFG_CONT_SHIFT) & SARADC_CFG_CONT_MASK)
| ((pAdc->SMPL_SETUP << SARADC_CFG_SMPL_SETUP_SHIFT) & SARADC_CFG_SMPL_SETUP_MASK)
| ((pAdc->MEM_MODE << SARADC_CFG_MEM_MODE_SHIFT) & SARADC_CFG_MEM_MODE_MASK)
| ((pAdc->SMPL_CLK << SARADC_CFG_SMPL_CLK_SHIFT) & SARADC_CFG_SMPL_CLK_MASK)
| ((pAdc->SMPL_WIN << SARADC_CFG_SMPL_WIN_SHIFT) & SARADC_CFG_SMPL_WIN_MASK)
| ((pAdc->ADC_TRIG << SARADC_CFG_ADC_TRIG_SHIFT) & SARADC_CFG_ADC_TRIG_MASK)
| ((pAdc->DMA_EN << SARADC_CFG_DMA_EN_SHIFT) & SARADC_CFG_DMA_EN_MASK)
;
SARADC_EXTTRIG_SEL = pAdc->EXTTRIG_SEL;
SARADC_EXTTRIG_SEL = pAdc->EXTTRIG_SEL;
if (pAdc->CALIB_OFFSET_VALID) {
SARADC_CALIB_OFFSET = (SARADC_CALIB_OFFSET & ~SARADC_CALIB_OFFSET_VALID_MASK) | SARADC_CALIB_OFFSET_VALID_BITS_YES;
} else {
SARADC_CALIB_OFFSET = (SARADC_CALIB_OFFSET & ~SARADC_CALIB_OFFSET_VALID_MASK) | SARADC_CALIB_OFFSET_VALID_BITS_NO;
}
if (pAdc->CALIB_KD_VALID) {
SARADC_CALIB_KD = (SARADC_CALIB_KD & ~SARADC_CALIB_KD_VALID_MASK) | SARADC_CALIB_KD_VALID_BITS_YES;
} else {
SARADC_CALIB_KD = (SARADC_CALIB_KD & ~SARADC_CALIB_KD_VALID_MASK) | SARADC_CALIB_KD_VALID_BITS_NO;
}
if (pAdc->CALIB_OFFSET_VALID) {
SARADC_CALIB_OFFSET = (SARADC_CALIB_OFFSET & ~SARADC_CALIB_OFFSET_VALID_MASK) | SARADC_CALIB_OFFSET_VALID_BITS_YES;
} else {
SARADC_CALIB_OFFSET = (SARADC_CALIB_OFFSET & ~SARADC_CALIB_OFFSET_VALID_MASK) | SARADC_CALIB_OFFSET_VALID_BITS_NO;
}
if (pAdc->CALIB_KD_VALID) {
SARADC_CALIB_KD = (SARADC_CALIB_KD & ~SARADC_CALIB_KD_VALID_MASK) | SARADC_CALIB_KD_VALID_BITS_YES;
} else {
SARADC_CALIB_KD = (SARADC_CALIB_KD & ~SARADC_CALIB_KD_VALID_MASK) | SARADC_CALIB_KD_VALID_BITS_NO;
}
SARADC_IF = 0xFFFFFFFF;
SARADC_IE = 0
| (SARADC_IE & ~(0
| SARADC_IE_CHx_EOC_MASK
| SARADC_IE_FIFO_FULL_MASK
| SARADC_IE_FIFO_HFULL_MASK
))
| ((pAdc->IE_CHx_EOC << SARADC_IE_CHx_EOC_SHIFT) & SARADC_IE_CHx_EOC_MASK)
| ((pAdc->IE_FIFO_FULL << SARADC_IE_FIFO_FULL_SHIFT) & SARADC_IE_FIFO_FULL_MASK)
| ((pAdc->IE_FIFO_HFULL << SARADC_IE_FIFO_HFULL_SHIFT) & SARADC_IE_FIFO_HFULL_MASK)
;
SARADC_IF = 0xFFFFFFFF;
SARADC_IE = 0
| (SARADC_IE & ~(0
| SARADC_IE_CHx_EOC_MASK
| SARADC_IE_FIFO_FULL_MASK
| SARADC_IE_FIFO_HFULL_MASK
))
| ((pAdc->IE_CHx_EOC << SARADC_IE_CHx_EOC_SHIFT) & SARADC_IE_CHx_EOC_MASK)
| ((pAdc->IE_FIFO_FULL << SARADC_IE_FIFO_FULL_SHIFT) & SARADC_IE_FIFO_FULL_MASK)
| ((pAdc->IE_FIFO_HFULL << SARADC_IE_FIFO_HFULL_SHIFT) & SARADC_IE_FIFO_HFULL_MASK)
;
if (SARADC_IE == 0) {
NVIC_DisableIRQ((IRQn_Type)DP32_SARADC_IRQn);
} else {
NVIC_EnableIRQ((IRQn_Type)DP32_SARADC_IRQn);
}
if (SARADC_IE == 0) {
NVIC_DisableIRQ((IRQn_Type)DP32_SARADC_IRQn);
} else {
NVIC_EnableIRQ((IRQn_Type)DP32_SARADC_IRQn);
}
}
void ADC_Start(void)
{
SARADC_START = (SARADC_START & ~SARADC_START_START_MASK) | SARADC_START_START_BITS_ENABLE;
SARADC_START = (SARADC_START & ~SARADC_START_START_MASK) | SARADC_START_START_BITS_ENABLE;
}
bool ADC_CheckEndOfConversion(ADC_CH_MASK Mask)
{
volatile ADC_Channel_t *pChannels = (volatile ADC_Channel_t *)&SARADC_CH0;
uint8_t Channel = ADC_GetChannelNumber(Mask);
volatile ADC_Channel_t *pChannels = (volatile ADC_Channel_t *)&SARADC_CH0;
uint8_t Channel = ADC_GetChannelNumber(Mask);
return (pChannels[Channel].STAT & ADC_CHx_STAT_EOC_MASK) >> ADC_CHx_STAT_EOC_SHIFT;
return (pChannels[Channel].STAT & ADC_CHx_STAT_EOC_MASK) >> ADC_CHx_STAT_EOC_SHIFT;
}
uint16_t ADC_GetValue(ADC_CH_MASK Mask)
{
volatile ADC_Channel_t *pChannels = (volatile ADC_Channel_t *)&SARADC_CH0;
uint8_t Channel = ADC_GetChannelNumber(Mask);
volatile ADC_Channel_t *pChannels = (volatile ADC_Channel_t *)&SARADC_CH0;
uint8_t Channel = ADC_GetChannelNumber(Mask);
SARADC_IF = 1 << Channel; // TODO: Or just use 'Mask'
SARADC_IF = 1 << Channel; // TODO: Or just use 'Mask'
return (pChannels[Channel].DATA & ADC_CHx_DATA_DATA_MASK) >> ADC_CHx_DATA_DATA_SHIFT;
return (pChannels[Channel].DATA & ADC_CHx_DATA_DATA_MASK) >> ADC_CHx_DATA_DATA_SHIFT;
}

66
driver/adc.h
View File

@@ -21,44 +21,44 @@
#include <stdint.h>
enum ADC_CH_MASK {
ADC_CH0 = 0x0001U,
ADC_CH1 = 0x0002U,
ADC_CH2 = 0x0004U,
ADC_CH3 = 0x0008U,
ADC_CH4 = 0x0010U,
ADC_CH5 = 0x0020U,
ADC_CH6 = 0x0040U,
ADC_CH7 = 0x0080U,
ADC_CH8 = 0x0100U,
ADC_CH9 = 0x0200U,
ADC_CH10 = 0x0400U,
ADC_CH11 = 0x0800U,
ADC_CH12 = 0x1000U,
ADC_CH13 = 0x2000U,
ADC_CH14 = 0x4000U,
ADC_CH15 = 0x8000U,
ADC_CH0 = 0x0001U,
ADC_CH1 = 0x0002U,
ADC_CH2 = 0x0004U,
ADC_CH3 = 0x0008U,
ADC_CH4 = 0x0010U,
ADC_CH5 = 0x0020U,
ADC_CH6 = 0x0040U,
ADC_CH7 = 0x0080U,
ADC_CH8 = 0x0100U,
ADC_CH9 = 0x0200U,
ADC_CH10 = 0x0400U,
ADC_CH11 = 0x0800U,
ADC_CH12 = 0x1000U,
ADC_CH13 = 0x2000U,
ADC_CH14 = 0x4000U,
ADC_CH15 = 0x8000U,
};
typedef enum ADC_CH_MASK ADC_CH_MASK;
typedef struct {
uint16_t EXTTRIG_SEL;
uint16_t IE_CHx_EOC;
ADC_CH_MASK CH_SEL;
uint8_t CLK_SEL;
uint8_t AVG;
uint8_t CONT;
uint8_t MEM_MODE;
uint8_t SMPL_CLK;
uint8_t SMPL_SETUP;
uint8_t SMPL_WIN;
uint8_t ADC_TRIG;
uint8_t DMA_EN;
uint8_t IE_FIFO_HFULL;
uint8_t IE_FIFO_FULL;
bool CALIB_OFFSET_VALID;
bool CALIB_KD_VALID;
uint8_t _pad[1];
uint16_t EXTTRIG_SEL;
uint16_t IE_CHx_EOC;
ADC_CH_MASK CH_SEL;
uint8_t CLK_SEL;
uint8_t AVG;
uint8_t CONT;
uint8_t MEM_MODE;
uint8_t SMPL_CLK;
uint8_t SMPL_SETUP;
uint8_t SMPL_WIN;
uint8_t ADC_TRIG;
uint8_t DMA_EN;
uint8_t IE_FIFO_HFULL;
uint8_t IE_FIFO_FULL;
bool CALIB_OFFSET_VALID;
bool CALIB_KD_VALID;
uint8_t _pad[1];
} ADC_Config_t;
uint8_t ADC_GetChannelNumber(ADC_CH_MASK Mask);

70
driver/aes.c
View File

@@ -21,54 +21,54 @@
static void AES_Setup_ENC_CBC(bool IsDecrypt, const void *pKey, const void *pIv)
{
const uint32_t *pK = (const uint32_t *)pKey;
const uint32_t *pI = (const uint32_t *)pIv;
const uint32_t *pK = (const uint32_t *)pKey;
const uint32_t *pI = (const uint32_t *)pIv;
(void)IsDecrypt; // unused
AES_CR = (AES_CR & ~AES_CR_EN_MASK) | AES_CR_EN_BITS_DISABLE;
AES_CR = AES_CR_CHMOD_BITS_CBC;
AES_KEYR3 = pK[0];
AES_KEYR2 = pK[1];
AES_KEYR1 = pK[2];
AES_KEYR0 = pK[3];
AES_IVR3 = pI[0];
AES_IVR2 = pI[1];
AES_IVR1 = pI[2];
AES_IVR0 = pI[3];
AES_CR = (AES_CR & ~AES_CR_EN_MASK) | AES_CR_EN_BITS_ENABLE;
(void)IsDecrypt; // unused
AES_CR = (AES_CR & ~AES_CR_EN_MASK) | AES_CR_EN_BITS_DISABLE;
AES_CR = AES_CR_CHMOD_BITS_CBC;
AES_KEYR3 = pK[0];
AES_KEYR2 = pK[1];
AES_KEYR1 = pK[2];
AES_KEYR0 = pK[3];
AES_IVR3 = pI[0];
AES_IVR2 = pI[1];
AES_IVR1 = pI[2];
AES_IVR0 = pI[3];
AES_CR = (AES_CR & ~AES_CR_EN_MASK) | AES_CR_EN_BITS_ENABLE;
}
static void AES_Transform(const void *pIn, void *pOut)
{
const uint32_t *pI = (const uint32_t *)pIn;
uint32_t *pO = (uint32_t *)pOut;
const uint32_t *pI = (const uint32_t *)pIn;
uint32_t *pO = (uint32_t *)pOut;
AES_DINR = pI[0];
AES_DINR = pI[1];
AES_DINR = pI[2];
AES_DINR = pI[3];
AES_DINR = pI[0];
AES_DINR = pI[1];
AES_DINR = pI[2];
AES_DINR = pI[3];
while ((AES_SR & AES_SR_CCF_MASK) == AES_SR_CCF_BITS_NOT_COMPLETE) {
}
while ((AES_SR & AES_SR_CCF_MASK) == AES_SR_CCF_BITS_NOT_COMPLETE) {
}
pO[0] = AES_DOUTR;
pO[1] = AES_DOUTR;
pO[2] = AES_DOUTR;
pO[3] = AES_DOUTR;
pO[0] = AES_DOUTR;
pO[1] = AES_DOUTR;
pO[2] = AES_DOUTR;
pO[3] = AES_DOUTR;
AES_CR |= AES_CR_CCFC_BITS_SET;
AES_CR |= AES_CR_CCFC_BITS_SET;
}
void AES_Encrypt(const void *pKey, const void *pIv, const void *pIn, void *pOut, uint8_t NumBlocks)
{
const uint8_t *pI = (const uint8_t *)pIn;
uint8_t *pO = (uint8_t *)pOut;
uint8_t i;
const uint8_t *pI = (const uint8_t *)pIn;
uint8_t *pO = (uint8_t *)pOut;
uint8_t i;
AES_Setup_ENC_CBC(0, pKey, pIv);
for (i = 0; i < NumBlocks; i++) {
AES_Transform(pI + (i * 16), pO + (i * 16));
}
AES_Setup_ENC_CBC(0, pKey, pIv);
for (i = 0; i < NumBlocks; i++) {
AES_Transform(pI + (i * 16), pO + (i * 16));
}
}

166
driver/backlight.c
View File

@@ -22,9 +22,9 @@
#include "settings.h"
#ifdef ENABLE_FEAT_F4HWN
#include "driver/system.h"
#include "audio.h"
#include "misc.h"
#include "driver/system.h"
#include "audio.h"
#include "misc.h"
#endif
// this is decremented once every 500ms
@@ -33,128 +33,128 @@ bool backlightOn;
void BACKLIGHT_InitHardware()
{
// 48MHz / 94 / 1024 ~ 500Hz
const uint32_t PWM_FREQUENCY_HZ = 25000;
PWM_PLUS0_CLKSRC |= ((48000000 / 1024 / PWM_FREQUENCY_HZ) << 16);
PWM_PLUS0_PERIOD = 1023;
// 48MHz / 94 / 1024 ~ 500Hz
const uint32_t PWM_FREQUENCY_HZ = 25000;
PWM_PLUS0_CLKSRC |= ((48000000 / 1024 / PWM_FREQUENCY_HZ) << 16);
PWM_PLUS0_PERIOD = 1023;
PORTCON_PORTB_SEL0 &= ~(0
// Back light
| PORTCON_PORTB_SEL0_B6_MASK
);
PORTCON_PORTB_SEL0 |= 0
// Back light PWM
| PORTCON_PORTB_SEL0_B6_BITS_PWMP0_CH0
;
PORTCON_PORTB_SEL0 &= ~(0
// Back light
| PORTCON_PORTB_SEL0_B6_MASK
);
PORTCON_PORTB_SEL0 |= 0
// Back light PWM
| PORTCON_PORTB_SEL0_B6_BITS_PWMP0_CH0
;
PWM_PLUS0_GEN =
PWMPLUS_GEN_CH0_OE_BITS_ENABLE |
PWMPLUS_GEN_CH0_OUTINV_BITS_ENABLE |
0;
PWM_PLUS0_GEN =
PWMPLUS_GEN_CH0_OE_BITS_ENABLE |
PWMPLUS_GEN_CH0_OUTINV_BITS_ENABLE |
0;
PWM_PLUS0_CFG =
PWMPLUS_CFG_CNT_REP_BITS_ENABLE |
PWMPLUS_CFG_COUNTER_EN_BITS_ENABLE |
0;
PWM_PLUS0_CFG =
PWMPLUS_CFG_CNT_REP_BITS_ENABLE |
PWMPLUS_CFG_COUNTER_EN_BITS_ENABLE |
0;
}
static void BACKLIGHT_Sound(void)
{
if (gEeprom.POWER_ON_DISPLAY_MODE == POWER_ON_DISPLAY_MODE_SOUND || gEeprom.POWER_ON_DISPLAY_MODE == POWER_ON_DISPLAY_MODE_ALL)
{
AUDIO_PlayBeep(BEEP_880HZ_60MS_DOUBLE_BEEP);
AUDIO_PlayBeep(BEEP_880HZ_60MS_DOUBLE_BEEP);
gK5startup = false;
}
else
gK5startup = false;
if (gEeprom.POWER_ON_DISPLAY_MODE == POWER_ON_DISPLAY_MODE_SOUND || gEeprom.POWER_ON_DISPLAY_MODE == POWER_ON_DISPLAY_MODE_ALL)
{
AUDIO_PlayBeep(BEEP_880HZ_60MS_DOUBLE_BEEP);
AUDIO_PlayBeep(BEEP_880HZ_60MS_DOUBLE_BEEP);
gK5startup = false;
}
else
gK5startup = false;
}
void BACKLIGHT_TurnOn(void)
{
#ifdef ENABLE_FEAT_F4HWN
gBacklightBrightnessOld = BACKLIGHT_GetBrightness();
#endif
#ifdef ENABLE_FEAT_F4HWN
gBacklightBrightnessOld = BACKLIGHT_GetBrightness();
#endif
if (gEeprom.BACKLIGHT_TIME == 0) {
BACKLIGHT_TurnOff();
#ifdef ENABLE_FEAT_F4HWN
if(gK5startup == true)
{
BACKLIGHT_Sound();
}
#endif
return;
}
if (gEeprom.BACKLIGHT_TIME == 0) {
BACKLIGHT_TurnOff();
#ifdef ENABLE_FEAT_F4HWN
if(gK5startup == true)
{
BACKLIGHT_Sound();
}
#endif
return;
}
backlightOn = true;
backlightOn = true;
#ifdef ENABLE_FEAT_F4HWN
if(gK5startup == true) {
for(uint8_t i = 0; i <= gEeprom.BACKLIGHT_MAX; i++)
{
BACKLIGHT_SetBrightness(i);
SYSTEM_DelayMs(50);
}
if(gK5startup == true) {
for(uint8_t i = 0; i <= gEeprom.BACKLIGHT_MAX; i++)
{
BACKLIGHT_SetBrightness(i);
SYSTEM_DelayMs(50);
}
BACKLIGHT_Sound();
}
else
{
BACKLIGHT_SetBrightness(gEeprom.BACKLIGHT_MAX);
}
BACKLIGHT_Sound();
}
else
{
BACKLIGHT_SetBrightness(gEeprom.BACKLIGHT_MAX);
}
#else
BACKLIGHT_SetBrightness(gEeprom.BACKLIGHT_MAX);
BACKLIGHT_SetBrightness(gEeprom.BACKLIGHT_MAX);
#endif
switch (gEeprom.BACKLIGHT_TIME) {
default:
case 1 ... 60: // 5 sec * value
gBacklightCountdown_500ms = 1 + (gEeprom.BACKLIGHT_TIME * 5) * 2;
break;
case 61: // always on
gBacklightCountdown_500ms = 0;
break;
}
switch (gEeprom.BACKLIGHT_TIME) {
default:
case 1 ... 60: // 5 sec * value
gBacklightCountdown_500ms = 1 + (gEeprom.BACKLIGHT_TIME * 5) * 2;
break;
case 61: // always on
gBacklightCountdown_500ms = 0;
break;
}
}
void BACKLIGHT_TurnOff()
{
#ifdef ENABLE_BLMIN_TMP_OFF
register uint8_t tmp;
register uint8_t tmp;
if (gEeprom.BACKLIGHT_MIN_STAT == BLMIN_STAT_ON)
tmp = gEeprom.BACKLIGHT_MIN;
else
tmp = 0;
if (gEeprom.BACKLIGHT_MIN_STAT == BLMIN_STAT_ON)
tmp = gEeprom.BACKLIGHT_MIN;
else
tmp = 0;
BACKLIGHT_SetBrightness(tmp);
BACKLIGHT_SetBrightness(tmp);
#else
BACKLIGHT_SetBrightness(gEeprom.BACKLIGHT_MIN);
BACKLIGHT_SetBrightness(gEeprom.BACKLIGHT_MIN);
#endif
gBacklightCountdown_500ms = 0;
backlightOn = false;
gBacklightCountdown_500ms = 0;
backlightOn = false;
}
bool BACKLIGHT_IsOn()
{
return backlightOn;
return backlightOn;
}
static uint8_t currentBrightness;
void BACKLIGHT_SetBrightness(uint8_t brigtness)
{
const uint8_t value[] = {0, 3, 6, 9, 15, 24, 38, 62, 100, 159, 255};
const uint8_t value[] = {0, 3, 6, 9, 15, 24, 38, 62, 100, 159, 255};
currentBrightness = brigtness;
PWM_PLUS0_CH0_COMP = value[brigtness] * 4;
//PWM_PLUS0_CH0_COMP = (1 << brigtness) - 1;
//PWM_PLUS0_SWLOAD = 1;
currentBrightness = brigtness;
PWM_PLUS0_CH0_COMP = value[brigtness] * 4;
//PWM_PLUS0_CH0_COMP = (1 << brigtness) - 1;
//PWM_PLUS0_SWLOAD = 1;
}
uint8_t BACKLIGHT_GetBrightness(void)
{
return currentBrightness;
return currentBrightness;
}

40
driver/bk1080-regs.h
View File

@@ -18,40 +18,40 @@
#define BK1080_REGS_H
enum BK1080_Register_t {
BK1080_REG_00 = 0x00U,
BK1080_REG_02_POWER_CONFIGURATION = 0x02U,
BK1080_REG_03_CHANNEL = 0x03U,
BK1080_REG_05_SYSTEM_CONFIGURATION2 = 0x05U,
BK1080_REG_07 = 0x07U,
BK1080_REG_10 = 0x0AU,
BK1080_REG_25_INTERNAL = 0x19U,
BK1080_REG_00 = 0x00U,
BK1080_REG_02_POWER_CONFIGURATION = 0x02U,
BK1080_REG_03_CHANNEL = 0x03U,
BK1080_REG_05_SYSTEM_CONFIGURATION2 = 0x05U,
BK1080_REG_07 = 0x07U,
BK1080_REG_10 = 0x0AU,
BK1080_REG_25_INTERNAL = 0x19U,
};
typedef enum BK1080_Register_t BK1080_Register_t;
// REG 07
#define BK1080_REG_07_SHIFT_FREQD 4
#define BK1080_REG_07_SHIFT_SNR 0
#define BK1080_REG_07_SHIFT_FREQD 4
#define BK1080_REG_07_SHIFT_SNR 0
#define BK1080_REG_07_MASK_FREQD (0xFFFU << BK1080_REG_07_SHIFT_FREQD)
#define BK1080_REG_07_MASK_SNR (0x00FU << BK1080_REG_07_SHIFT_SNR)
#define BK1080_REG_07_MASK_FREQD (0xFFFU << BK1080_REG_07_SHIFT_FREQD)
#define BK1080_REG_07_MASK_SNR (0x00FU << BK1080_REG_07_SHIFT_SNR)
#define BK1080_REG_07_GET_FREQD(x) (((x) & BK1080_REG_07_MASK_FREQD) >> BK1080_REG_07_SHIFT_FREQD)
#define BK1080_REG_07_GET_SNR(x) (((x) & BK1080_REG_07_MASK_SNR) >> BK1080_REG_07_SHIFT_SNR)
#define BK1080_REG_07_GET_FREQD(x) (((x) & BK1080_REG_07_MASK_FREQD) >> BK1080_REG_07_SHIFT_FREQD)
#define BK1080_REG_07_GET_SNR(x) (((x) & BK1080_REG_07_MASK_SNR) >> BK1080_REG_07_SHIFT_SNR)
// REG 10
#define BK1080_REG_10_SHIFT_AFCRL 12
#define BK1080_REG_10_SHIFT_RSSI 0
#define BK1080_REG_10_SHIFT_AFCRL 12
#define BK1080_REG_10_SHIFT_RSSI 0
#define BK1080_REG_10_MASK_AFCRL (0x01U << BK1080_REG_10_SHIFT_AFCRL)
#define BK1080_REG_10_MASK_RSSI (0xFFU << BK1080_REG_10_SHIFT_RSSI)
#define BK1080_REG_10_MASK_AFCRL (0x01U << BK1080_REG_10_SHIFT_AFCRL)
#define BK1080_REG_10_MASK_RSSI (0xFFU << BK1080_REG_10_SHIFT_RSSI)
#define BK1080_REG_10_AFCRL_NOT_RAILED (0U << BK1080_REG_10_SHIFT_AFCRL)
#define BK1080_REG_10_AFCRL_RAILED (1U << BK1080_REG_10_SHIFT_AFCRL)
#define BK1080_REG_10_AFCRL_NOT_RAILED (0U << BK1080_REG_10_SHIFT_AFCRL)
#define BK1080_REG_10_AFCRL_RAILED (1U << BK1080_REG_10_SHIFT_AFCRL)
#define BK1080_REG_10_GET_RSSI(x) (((x) & BK1080_REG_10_MASK_RSSI) >> BK1080_REG_10_SHIFT_RSSI)
#define BK1080_REG_10_GET_RSSI(x) (((x) & BK1080_REG_10_MASK_RSSI) >> BK1080_REG_10_SHIFT_RSSI)
#endif

120
driver/bk1080.c
View File

@@ -22,16 +22,16 @@
#include "misc.h"
#ifndef ARRAY_SIZE
#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
#endif
static const uint16_t BK1080_RegisterTable[] =
{
0x0008, 0x1080, 0x0201, 0x0000, 0x40C0, 0x0A1F, 0x002E, 0x02FF,
0x5B11, 0x0000, 0x411E, 0x0000, 0xCE00, 0x0000, 0x0000, 0x1000,
0x3197, 0x0000, 0x13FF, 0x9852, 0x0000, 0x0000, 0x0008, 0x0000,
0x51E1, 0xA8BC, 0x2645, 0x00E4, 0x1CD8, 0x3A50, 0xEAE0, 0x3000,
0x0200, 0x0000,
0x0008, 0x1080, 0x0201, 0x0000, 0x40C0, 0x0A1F, 0x002E, 0x02FF,
0x5B11, 0x0000, 0x411E, 0x0000, 0xCE00, 0x0000, 0x0000, 0x1000,
0x3197, 0x0000, 0x13FF, 0x9852, 0x0000, 0x0000, 0x0008, 0x0000,
0x51E1, 0xA8BC, 0x2645, 0x00E4, 0x1CD8, 0x3A50, 0xEAE0, 0x3000,
0x0200, 0x0000,
};
static bool gIsInitBK1080;
@@ -41,104 +41,104 @@ uint16_t BK1080_FrequencyDeviation;
void BK1080_Init0(void)
{
BK1080_Init(0,0/*,0*/);
BK1080_Init(0,0/*,0*/);
}
void BK1080_Init(uint16_t freq, uint8_t band/*, uint8_t space*/)
{
unsigned int i;
unsigned int i;
if (freq) {
GPIO_ClearBit(&GPIOB->DATA, GPIOB_PIN_BK1080);
if (freq) {
GPIO_ClearBit(&GPIOB->DATA, GPIOB_PIN_BK1080);
if (!gIsInitBK1080) {
for (i = 0; i < ARRAY_SIZE(BK1080_RegisterTable); i++)
BK1080_WriteRegister(i, BK1080_RegisterTable[i]);
if (!gIsInitBK1080) {
for (i = 0; i < ARRAY_SIZE(BK1080_RegisterTable); i++)
BK1080_WriteRegister(i, BK1080_RegisterTable[i]);
SYSTEM_DelayMs(250);
SYSTEM_DelayMs(250);
BK1080_WriteRegister(BK1080_REG_25_INTERNAL, 0xA83C);
BK1080_WriteRegister(BK1080_REG_25_INTERNAL, 0xA8BC);
BK1080_WriteRegister(BK1080_REG_25_INTERNAL, 0xA83C);
BK1080_WriteRegister(BK1080_REG_25_INTERNAL, 0xA8BC);
SYSTEM_DelayMs(60);
SYSTEM_DelayMs(60);
gIsInitBK1080 = true;
}
else {
BK1080_WriteRegister(BK1080_REG_02_POWER_CONFIGURATION, 0x0201);
}
gIsInitBK1080 = true;
}
else {
BK1080_WriteRegister(BK1080_REG_02_POWER_CONFIGURATION, 0x0201);
}
BK1080_WriteRegister(BK1080_REG_05_SYSTEM_CONFIGURATION2, 0x0A1F);
BK1080_SetFrequency(freq, band/*, space*/);
}
else {
BK1080_WriteRegister(BK1080_REG_02_POWER_CONFIGURATION, 0x0241);
GPIO_SetBit(&GPIOB->DATA, GPIOB_PIN_BK1080);
}
BK1080_WriteRegister(BK1080_REG_05_SYSTEM_CONFIGURATION2, 0x0A1F);
BK1080_SetFrequency(freq, band/*, space*/);
}
else {
BK1080_WriteRegister(BK1080_REG_02_POWER_CONFIGURATION, 0x0241);
GPIO_SetBit(&GPIOB->DATA, GPIOB_PIN_BK1080);
}
}
uint16_t BK1080_ReadRegister(BK1080_Register_t Register)
{
uint8_t Value[2];
uint8_t Value[2];
I2C_Start();
I2C_Write(0x80);
I2C_Write((Register << 1) | I2C_READ);
I2C_ReadBuffer(Value, sizeof(Value));
I2C_Stop();
I2C_Start();
I2C_Write(0x80);
I2C_Write((Register << 1) | I2C_READ);
I2C_ReadBuffer(Value, sizeof(Value));
I2C_Stop();
return (Value[0] << 8) | Value[1];
return (Value[0] << 8) | Value[1];
}
void BK1080_WriteRegister(BK1080_Register_t Register, uint16_t Value)
{
I2C_Start();
I2C_Write(0x80);
I2C_Write((Register << 1) | I2C_WRITE);
Value = ((Value >> 8) & 0xFF) | ((Value & 0xFF) << 8);
I2C_WriteBuffer(&Value, sizeof(Value));
I2C_Stop();
I2C_Start();
I2C_Write(0x80);
I2C_Write((Register << 1) | I2C_WRITE);
Value = ((Value >> 8) & 0xFF) | ((Value & 0xFF) << 8);
I2C_WriteBuffer(&Value, sizeof(Value));
I2C_Stop();
}
void BK1080_Mute(bool Mute)
{
BK1080_WriteRegister(BK1080_REG_02_POWER_CONFIGURATION, Mute ? 0x4201 : 0x0201);
BK1080_WriteRegister(BK1080_REG_02_POWER_CONFIGURATION, Mute ? 0x4201 : 0x0201);
}
void BK1080_SetFrequency(uint16_t frequency, uint8_t band/*, uint8_t space*/)
{
//uint8_t spacings[] = {20,10,5};
//space %= 3;
//uint8_t spacings[] = {20,10,5};
//space %= 3;
uint16_t channel = (frequency - BK1080_GetFreqLoLimit(band))/* * 10 / spacings[space]*/;
uint16_t channel = (frequency - BK1080_GetFreqLoLimit(band))/* * 10 / spacings[space]*/;
uint16_t regval = BK1080_ReadRegister(BK1080_REG_05_SYSTEM_CONFIGURATION2);
regval = (regval & ~(0b11 << 6)) | ((band & 0b11) << 6);
//regval = (regval & ~(0b11 << 4)) | ((space & 0b11) << 4);
uint16_t regval = BK1080_ReadRegister(BK1080_REG_05_SYSTEM_CONFIGURATION2);
regval = (regval & ~(0b11 << 6)) | ((band & 0b11) << 6);
//regval = (regval & ~(0b11 << 4)) | ((space & 0b11) << 4);
BK1080_WriteRegister(BK1080_REG_05_SYSTEM_CONFIGURATION2, regval);
BK1080_WriteRegister(BK1080_REG_05_SYSTEM_CONFIGURATION2, regval);
BK1080_WriteRegister(BK1080_REG_03_CHANNEL, channel);
SYSTEM_DelayMs(10);
BK1080_WriteRegister(BK1080_REG_03_CHANNEL, channel | 0x8000);
BK1080_WriteRegister(BK1080_REG_03_CHANNEL, channel);
SYSTEM_DelayMs(10);
BK1080_WriteRegister(BK1080_REG_03_CHANNEL, channel | 0x8000);
}
void BK1080_GetFrequencyDeviation(uint16_t Frequency)
{
BK1080_BaseFrequency = Frequency;
BK1080_FrequencyDeviation = BK1080_ReadRegister(BK1080_REG_07) / 16;
BK1080_BaseFrequency = Frequency;
BK1080_FrequencyDeviation = BK1080_ReadRegister(BK1080_REG_07) / 16;
}
uint16_t BK1080_GetFreqLoLimit(uint8_t band)
{
uint16_t lim[] = {875, 760, 760, 640};
return lim[band % 4];
uint16_t lim[] = {875, 760, 760, 640};
return lim[band % 4];
}
uint16_t BK1080_GetFreqHiLimit(uint8_t band)
{
band %= 4;
uint16_t lim[] = {1080, 1080, 900, 760};
return lim[band % 4];
band %= 4;
uint16_t lim[] = {1080, 1080, 900, 760};
return lim[band % 4];
}

532
driver/bk4819-regs.h
View File

@@ -32,179 +32,179 @@ static const RegisterSpec afOutRegSpec = {"AF Output Select", 0x47, 8, 0xF, 1};
static const RegisterSpec afDacGainRegSpec = {"AF DAC Gain", 0x48, 0, 0xF, 1};
enum BK4819_REGISTER_t {
BK4819_REG_00 = 0x00U,
BK4819_REG_02 = 0x02U,
BK4819_REG_06 = 0x06U,
BK4819_REG_07 = 0x07U,
BK4819_REG_08 = 0x08U,
BK4819_REG_09 = 0x09U,
BK4819_REG_0B = 0x0BU,
BK4819_REG_0C = 0x0CU,
BK4819_REG_0D = 0x0DU,
BK4819_REG_0E = 0x0EU,
// RX AGC Gain Table[0]
BK4819_REG_10 = 0x10U,
// RX AGC Gain Table[1]
BK4819_REG_11 = 0x11U,
// RX AGC Gain Table[2]
BK4819_REG_12 = 0x12U,
// RX AGC Gain Table[3]
BK4819_REG_13 = 0x13U,
// RX AGC Gain Table[-1]
BK4819_REG_14 = 0x14U,
BK4819_REG_19 = 0x19U,
BK4819_REG_1F = 0x1FU,
BK4819_REG_20 = 0x20U,
BK4819_REG_21 = 0x21U,
BK4819_REG_24 = 0x24U,
BK4819_REG_28 = 0x28U,
BK4819_REG_29 = 0x29U,
BK4819_REG_2B = 0x2BU,
BK4819_REG_30 = 0x30U,
BK4819_REG_31 = 0x31U,
BK4819_REG_32 = 0x32U,
BK4819_REG_33 = 0x33U,
BK4819_REG_36 = 0x36U,
BK4819_REG_37 = 0x37U,
BK4819_REG_38 = 0x38U,
BK4819_REG_39 = 0x39U,
BK4819_REG_3A = 0x3AU,
BK4819_REG_3B = 0x3BU,
BK4819_REG_3C = 0x3CU,
BK4819_REG_3D = 0x3DU,
BK4819_REG_3E = 0x3EU,
BK4819_REG_3F = 0x3FU,
BK4819_REG_43 = 0x43U,
BK4819_REG_46 = 0x46U,
BK4819_REG_47 = 0x47U,
BK4819_REG_48 = 0x48U,
// REG_49<15:14> 0b00; High/Low Lo selection:
// 0X: Auto High/Low Lo
// 10: Low Lo
// 11: High Lo
// REG_49<13:7> 0x50; RF AGC high threshold, 1 dB/LSB
// REG_49<6:0> 0x30; RF AGC low threshold, 1 dB/LSB
BK4819_REG_49 = 0x49U,
BK4819_REG_4D = 0x4DU,
BK4819_REG_4E = 0x4EU,
BK4819_REG_4F = 0x4FU,
BK4819_REG_50 = 0x50U,
BK4819_REG_51 = 0x51U,
BK4819_REG_52 = 0x52U,
BK4819_REG_58 = 0x58U,
BK4819_REG_59 = 0x59U,
BK4819_REG_5A = 0x5AU,
BK4819_REG_5B = 0x5BU,
BK4819_REG_5C = 0x5CU,
BK4819_REG_5D = 0x5DU,
BK4819_REG_5F = 0x5FU,
BK4819_REG_63 = 0x63U,
BK4819_REG_64 = 0x64U,
BK4819_REG_65 = 0x65U,
BK4819_REG_67 = 0x67U,
BK4819_REG_68 = 0x68U,
BK4819_REG_69 = 0x69U,
BK4819_REG_6A = 0x6AU,
BK4819_REG_6F = 0x6FU,
BK4819_REG_70 = 0x70U,
BK4819_REG_71 = 0x71U,
BK4819_REG_72 = 0x72U,
BK4819_REG_78 = 0x78U,
BK4819_REG_79 = 0x79U,
BK4819_REG_7A = 0x7AU,
// REG_7B<15:0> 0xae34 RSSI table
BK4819_REG_7B = 0x7BU,
// REG_7C<15:0> 0x8000 RSSI table
BK4819_REG_7C = 0x7CU,
BK4819_REG_7D = 0x7DU,
// REG_7E<15> 0; AGC fix mode:
// 1: Fix
// 0: Auto
// REG_7E<14:12> 0b011; AGC fix index:
// 011: Max.
// …
// 100: Min.
// REG_7E<5:3> 0b101; DC filter bandwidth for TX (MIC in):
// 000: Bypass DC filter
// REG_7E<2:0> 0b110; DC filter bandwidth for RX (IF in):
// 000: Bypass DC filter
BK4819_REG_7E = 0x7EU,
BK4819_REG_00 = 0x00U,
BK4819_REG_02 = 0x02U,
BK4819_REG_06 = 0x06U,
BK4819_REG_07 = 0x07U,
BK4819_REG_08 = 0x08U,
BK4819_REG_09 = 0x09U,
BK4819_REG_0B = 0x0BU,
BK4819_REG_0C = 0x0CU,
BK4819_REG_0D = 0x0DU,
BK4819_REG_0E = 0x0EU,
// RX AGC Gain Table[0]
BK4819_REG_10 = 0x10U,
// RX AGC Gain Table[1]
BK4819_REG_11 = 0x11U,
// RX AGC Gain Table[2]
BK4819_REG_12 = 0x12U,
// RX AGC Gain Table[3]
BK4819_REG_13 = 0x13U,
// RX AGC Gain Table[-1]
BK4819_REG_14 = 0x14U,
BK4819_REG_19 = 0x19U,
BK4819_REG_1F = 0x1FU,
BK4819_REG_20 = 0x20U,
BK4819_REG_21 = 0x21U,
BK4819_REG_24 = 0x24U,
BK4819_REG_28 = 0x28U,
BK4819_REG_29 = 0x29U,
BK4819_REG_2B = 0x2BU,
BK4819_REG_30 = 0x30U,
BK4819_REG_31 = 0x31U,
BK4819_REG_32 = 0x32U,
BK4819_REG_33 = 0x33U,
BK4819_REG_36 = 0x36U,
BK4819_REG_37 = 0x37U,
BK4819_REG_38 = 0x38U,
BK4819_REG_39 = 0x39U,
BK4819_REG_3A = 0x3AU,
BK4819_REG_3B = 0x3BU,
BK4819_REG_3C = 0x3CU,
BK4819_REG_3D = 0x3DU,
BK4819_REG_3E = 0x3EU,
BK4819_REG_3F = 0x3FU,
BK4819_REG_43 = 0x43U,
BK4819_REG_46 = 0x46U,
BK4819_REG_47 = 0x47U,
BK4819_REG_48 = 0x48U,
// REG_49<15:14> 0b00; High/Low Lo selection:
// 0X: Auto High/Low Lo
// 10: Low Lo
// 11: High Lo
// REG_49<13:7> 0x50; RF AGC high threshold, 1 dB/LSB
// REG_49<6:0> 0x30; RF AGC low threshold, 1 dB/LSB
BK4819_REG_49 = 0x49U,
BK4819_REG_4D = 0x4DU,
BK4819_REG_4E = 0x4EU,
BK4819_REG_4F = 0x4FU,
BK4819_REG_50 = 0x50U,
BK4819_REG_51 = 0x51U,
BK4819_REG_52 = 0x52U,
BK4819_REG_58 = 0x58U,
BK4819_REG_59 = 0x59U,
BK4819_REG_5A = 0x5AU,
BK4819_REG_5B = 0x5BU,
BK4819_REG_5C = 0x5CU,
BK4819_REG_5D = 0x5DU,
BK4819_REG_5F = 0x5FU,
BK4819_REG_63 = 0x63U,
BK4819_REG_64 = 0x64U,
BK4819_REG_65 = 0x65U,
BK4819_REG_67 = 0x67U,
BK4819_REG_68 = 0x68U,
BK4819_REG_69 = 0x69U,
BK4819_REG_6A = 0x6AU,
BK4819_REG_6F = 0x6FU,
BK4819_REG_70 = 0x70U,
BK4819_REG_71 = 0x71U,
BK4819_REG_72 = 0x72U,
BK4819_REG_78 = 0x78U,
BK4819_REG_79 = 0x79U,
BK4819_REG_7A = 0x7AU,
// REG_7B<15:0> 0xae34 RSSI table
BK4819_REG_7B = 0x7BU,
// REG_7C<15:0> 0x8000 RSSI table
BK4819_REG_7C = 0x7CU,
BK4819_REG_7D = 0x7DU,
// REG_7E<15> 0; AGC fix mode:
// 1: Fix
// 0: Auto
// REG_7E<14:12> 0b011; AGC fix index:
// 011: Max.
// …
// 100: Min.
// REG_7E<5:3> 0b101; DC filter bandwidth for TX (MIC in):
// 000: Bypass DC filter
// REG_7E<2:0> 0b110; DC filter bandwidth for RX (IF in):
// 000: Bypass DC filter
BK4819_REG_7E = 0x7EU,
};
typedef enum BK4819_REGISTER_t BK4819_REGISTER_t;
enum BK4819_GPIO_PIN_t {
BK4819_GPIO0_PIN28_RX_ENABLE = 0,
BK4819_GPIO1_PIN29_PA_ENABLE = 1,
BK4819_GPIO3_PIN31_UHF_LNA = 3,
BK4819_GPIO4_PIN32_VHF_LNA = 4,
BK4819_GPIO5_PIN1_RED = 5,
BK4819_GPIO6_PIN2_GREEN = 6,
BK4819_GPIO0_PIN28_RX_ENABLE = 0,
BK4819_GPIO1_PIN29_PA_ENABLE = 1,
BK4819_GPIO3_PIN31_UHF_LNA = 3,
BK4819_GPIO4_PIN32_VHF_LNA = 4,
BK4819_GPIO5_PIN1_RED = 5,
BK4819_GPIO6_PIN2_GREEN = 6,
};
typedef enum BK4819_GPIO_PIN_t BK4819_GPIO_PIN_t;
// REG 02
#define BK4819_REG_02_SHIFT_FSK_TX_FINISHED 15
#define BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_EMPTY 14
#define BK4819_REG_02_SHIFT_FSK_RX_FINISHED 13
#define BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_FULL 12
#define BK4819_REG_02_SHIFT_DTMF_5TONE_FOUND 11
#define BK4819_REG_02_SHIFT_CxCSS_TAIL 10
#define BK4819_REG_02_SHIFT_CDCSS_FOUND 9
#define BK4819_REG_02_SHIFT_CDCSS_LOST 8
#define BK4819_REG_02_SHIFT_CTCSS_FOUND 7
#define BK4819_REG_02_SHIFT_CTCSS_LOST 6
#define BK4819_REG_02_SHIFT_VOX_FOUND 5
#define BK4819_REG_02_SHIFT_VOX_LOST 4
#define BK4819_REG_02_SHIFT_SQUELCH_FOUND 3
#define BK4819_REG_02_SHIFT_SQUELCH_LOST 2
#define BK4819_REG_02_SHIFT_FSK_RX_SYNC 1
#define BK4819_REG_02_SHIFT_FSK_TX_FINISHED 15
#define BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_EMPTY 14
#define BK4819_REG_02_SHIFT_FSK_RX_FINISHED 13
#define BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_FULL 12
#define BK4819_REG_02_SHIFT_DTMF_5TONE_FOUND 11
#define BK4819_REG_02_SHIFT_CxCSS_TAIL 10
#define BK4819_REG_02_SHIFT_CDCSS_FOUND 9
#define BK4819_REG_02_SHIFT_CDCSS_LOST 8
#define BK4819_REG_02_SHIFT_CTCSS_FOUND 7
#define BK4819_REG_02_SHIFT_CTCSS_LOST 6
#define BK4819_REG_02_SHIFT_VOX_FOUND 5
#define BK4819_REG_02_SHIFT_VOX_LOST 4
#define BK4819_REG_02_SHIFT_SQUELCH_FOUND 3
#define BK4819_REG_02_SHIFT_SQUELCH_LOST 2
#define BK4819_REG_02_SHIFT_FSK_RX_SYNC 1
#define BK4819_REG_02_MASK_FSK_TX_FINISHED (1U << BK4819_REG_02_SHIFT_FSK_TX)
#define BK4819_REG_02_MASK_FSK_FIFO_ALMOST_EMPTY (1U << BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_EMPTY)
#define BK4819_REG_02_MASK_FSK_RX_FINISHED (1U << BK4819_REG_02_SHIFT_FSK_RX_FINISHED)
#define BK4819_REG_02_MASK_FSK_FIFO_ALMOST_FULL (1U << BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_FULL)
#define BK4819_REG_02_MASK_DTMF_5TONE_FOUND (1U << BK4819_REG_02_SHIFT_DTMF_5TONE_FOUND)
#define BK4819_REG_02_MASK_CxCSS_TAIL (1U << BK4819_REG_02_SHIFT_CxCSS_TAIL)
#define BK4819_REG_02_MASK_CDCSS_FOUND (1U << BK4819_REG_02_SHIFT_CDCSS_FOUND)
#define BK4819_REG_02_MASK_CDCSS_LOST (1U << BK4819_REG_02_SHIFT_CDCSS_LOST)
#define BK4819_REG_02_MASK_CTCSS_FOUND (1U << BK4819_REG_02_SHIFT_CTCSS_FOUND)
#define BK4819_REG_02_MASK_CTCSS_LOST (1U << BK4819_REG_02_SHIFT_CTCSS_LOST)
#define BK4819_REG_02_MASK_VOX_FOUND (1U << BK4819_REG_02_SHIFT_VOX_FOUND)
#define BK4819_REG_02_MASK_VOX_LOST (1U << BK4819_REG_02_SHIFT_VOX_LOST)
#define BK4819_REG_02_MASK_SQUELCH_FOUND (1U << BK4819_REG_02_SHIFT_SQUELCH_FOUND)
#define BK4819_REG_02_MASK_SQUELCH_LOST (1U << BK4819_REG_02_SHIFT_SQUELCH_LOST)
#define BK4819_REG_02_MASK_FSK_RX_SYNC (1U << BK4819_REG_02_SHIFT_FSK_RX_SYNC)
#define BK4819_REG_02_MASK_FSK_TX_FINISHED (1U << BK4819_REG_02_SHIFT_FSK_TX)
#define BK4819_REG_02_MASK_FSK_FIFO_ALMOST_EMPTY (1U << BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_EMPTY)
#define BK4819_REG_02_MASK_FSK_RX_FINISHED (1U << BK4819_REG_02_SHIFT_FSK_RX_FINISHED)
#define BK4819_REG_02_MASK_FSK_FIFO_ALMOST_FULL (1U << BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_FULL)
#define BK4819_REG_02_MASK_DTMF_5TONE_FOUND (1U << BK4819_REG_02_SHIFT_DTMF_5TONE_FOUND)
#define BK4819_REG_02_MASK_CxCSS_TAIL (1U << BK4819_REG_02_SHIFT_CxCSS_TAIL)
#define BK4819_REG_02_MASK_CDCSS_FOUND (1U << BK4819_REG_02_SHIFT_CDCSS_FOUND)
#define BK4819_REG_02_MASK_CDCSS_LOST (1U << BK4819_REG_02_SHIFT_CDCSS_LOST)
#define BK4819_REG_02_MASK_CTCSS_FOUND (1U << BK4819_REG_02_SHIFT_CTCSS_FOUND)
#define BK4819_REG_02_MASK_CTCSS_LOST (1U << BK4819_REG_02_SHIFT_CTCSS_LOST)
#define BK4819_REG_02_MASK_VOX_FOUND (1U << BK4819_REG_02_SHIFT_VOX_FOUND)
#define BK4819_REG_02_MASK_VOX_LOST (1U << BK4819_REG_02_SHIFT_VOX_LOST)
#define BK4819_REG_02_MASK_SQUELCH_FOUND (1U << BK4819_REG_02_SHIFT_SQUELCH_FOUND)
#define BK4819_REG_02_MASK_SQUELCH_LOST (1U << BK4819_REG_02_SHIFT_SQUELCH_LOST)
#define BK4819_REG_02_MASK_FSK_RX_SYNC (1U << BK4819_REG_02_SHIFT_FSK_RX_SYNC)
#define BK4819_REG_02_FSK_TX_FINISHED (1U << BK4819_REG_02_SHIFT_FSK_TX_FINISHED)
#define BK4819_REG_02_FSK_FIFO_ALMOST_EMPTY (1U << BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_EMPTY)
#define BK4819_REG_02_FSK_RX_FINISHED (1U << BK4819_REG_02_SHIFT_FSK_RX_FINISHED)
#define BK4819_REG_02_FSK_FIFO_ALMOST_FULL (1U << BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_FULL)
#define BK4819_REG_02_DTMF_5TONE_FOUND (1U << BK4819_REG_02_SHIFT_DTMF_5TONE_FOUND)
#define BK4819_REG_02_CxCSS_TAIL (1U << BK4819_REG_02_SHIFT_CxCSS_TAIL)
#define BK4819_REG_02_CDCSS_FOUND (1U << BK4819_REG_02_SHIFT_CDCSS_FOUND)
#define BK4819_REG_02_CDCSS_LOST (1U << BK4819_REG_02_SHIFT_CDCSS_LOST)
#define BK4819_REG_02_CTCSS_FOUND (1U << BK4819_REG_02_SHIFT_CTCSS_FOUND)
#define BK4819_REG_02_CTCSS_LOST (1U << BK4819_REG_02_SHIFT_CTCSS_LOST)
#define BK4819_REG_02_VOX_FOUND (1U << BK4819_REG_02_SHIFT_VOX_FOUND)
#define BK4819_REG_02_VOX_LOST (1U << BK4819_REG_02_SHIFT_VOX_LOST)
#define BK4819_REG_02_SQUELCH_FOUND (1U << BK4819_REG_02_SHIFT_SQUELCH_FOUND)
#define BK4819_REG_02_SQUELCH_LOST (1U << BK4819_REG_02_SHIFT_SQUELCH_LOST)
#define BK4819_REG_02_FSK_RX_SYNC (1U << BK4819_REG_02_SHIFT_FSK_RX_SYNC)
#define BK4819_REG_02_FSK_TX_FINISHED (1U << BK4819_REG_02_SHIFT_FSK_TX_FINISHED)
#define BK4819_REG_02_FSK_FIFO_ALMOST_EMPTY (1U << BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_EMPTY)
#define BK4819_REG_02_FSK_RX_FINISHED (1U << BK4819_REG_02_SHIFT_FSK_RX_FINISHED)
#define BK4819_REG_02_FSK_FIFO_ALMOST_FULL (1U << BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_FULL)
#define BK4819_REG_02_DTMF_5TONE_FOUND (1U << BK4819_REG_02_SHIFT_DTMF_5TONE_FOUND)
#define BK4819_REG_02_CxCSS_TAIL (1U << BK4819_REG_02_SHIFT_CxCSS_TAIL)
#define BK4819_REG_02_CDCSS_FOUND (1U << BK4819_REG_02_SHIFT_CDCSS_FOUND)
#define BK4819_REG_02_CDCSS_LOST (1U << BK4819_REG_02_SHIFT_CDCSS_LOST)
#define BK4819_REG_02_CTCSS_FOUND (1U << BK4819_REG_02_SHIFT_CTCSS_FOUND)
#define BK4819_REG_02_CTCSS_LOST (1U << BK4819_REG_02_SHIFT_CTCSS_LOST)
#define BK4819_REG_02_VOX_FOUND (1U << BK4819_REG_02_SHIFT_VOX_FOUND)
#define BK4819_REG_02_VOX_LOST (1U << BK4819_REG_02_SHIFT_VOX_LOST)
#define BK4819_REG_02_SQUELCH_FOUND (1U << BK4819_REG_02_SHIFT_SQUELCH_FOUND)
#define BK4819_REG_02_SQUELCH_LOST (1U << BK4819_REG_02_SHIFT_SQUELCH_LOST)
#define BK4819_REG_02_FSK_RX_SYNC (1U << BK4819_REG_02_SHIFT_FSK_RX_SYNC)
// REG 07
#define BK4819_REG_07_SHIFT_FREQUENCY_MODE 13
#define BK4819_REG_07_SHIFT_FREQUENCY 0
#define BK4819_REG_07_SHIFT_FREQUENCY_MODE 13
#define BK4819_REG_07_SHIFT_FREQUENCY 0
#define BK4819_REG_07_MASK_FREQUENCY_MODE (0x0007U << BK4819_REG_07_SHIFT_FREQUENCY_MODE)
#define BK4819_REG_07_MASK_FREQUENCY (0x1FFFU << BK4819_REG_07_SHIFT_FREQUENCY)
#define BK4819_REG_07_MASK_FREQUENCY_MODE (0x0007U << BK4819_REG_07_SHIFT_FREQUENCY_MODE)
#define BK4819_REG_07_MASK_FREQUENCY (0x1FFFU << BK4819_REG_07_SHIFT_FREQUENCY)
#define BK4819_REG_07_MODE_CTC1 (0U << BK4819_REG_07_SHIFT_FREQUENCY_MODE)
#define BK4819_REG_07_MODE_CTC2 (1U << BK4819_REG_07_SHIFT_FREQUENCY_MODE)
#define BK4819_REG_07_MODE_CDCSS (2U << BK4819_REG_07_SHIFT_FREQUENCY_MODE)
#define BK4819_REG_07_MODE_CTC1 (0U << BK4819_REG_07_SHIFT_FREQUENCY_MODE)
#define BK4819_REG_07_MODE_CTC2 (1U << BK4819_REG_07_SHIFT_FREQUENCY_MODE)
#define BK4819_REG_07_MODE_CDCSS (2U << BK4819_REG_07_SHIFT_FREQUENCY_MODE)
// REG 24
@@ -227,100 +227,100 @@ typedef enum BK4819_GPIO_PIN_t BK4819_GPIO_PIN_t;
// REG 30
#define BK4819_REG_30_SHIFT_ENABLE_VCO_CALIB 15
#define BK4819_REG_30_SHIFT_ENABLE_UNKNOWN 14
#define BK4819_REG_30_SHIFT_ENABLE_RX_LINK 10
#define BK4819_REG_30_SHIFT_ENABLE_AF_DAC 9
#define BK4819_REG_30_SHIFT_ENABLE_DISC_MODE 8
#define BK4819_REG_30_SHIFT_ENABLE_PLL_VCO 4
#define BK4819_REG_30_SHIFT_ENABLE_PA_GAIN 3
#define BK4819_REG_30_SHIFT_ENABLE_MIC_ADC 2
#define BK4819_REG_30_SHIFT_ENABLE_TX_DSP 1
#define BK4819_REG_30_SHIFT_ENABLE_RX_DSP 0
#define BK4819_REG_30_SHIFT_ENABLE_VCO_CALIB 15
#define BK4819_REG_30_SHIFT_ENABLE_UNKNOWN 14
#define BK4819_REG_30_SHIFT_ENABLE_RX_LINK 10
#define BK4819_REG_30_SHIFT_ENABLE_AF_DAC 9
#define BK4819_REG_30_SHIFT_ENABLE_DISC_MODE 8
#define BK4819_REG_30_SHIFT_ENABLE_PLL_VCO 4
#define BK4819_REG_30_SHIFT_ENABLE_PA_GAIN 3
#define BK4819_REG_30_SHIFT_ENABLE_MIC_ADC 2
#define BK4819_REG_30_SHIFT_ENABLE_TX_DSP 1
#define BK4819_REG_30_SHIFT_ENABLE_RX_DSP 0
#define BK4819_REG_30_MASK_ENABLE_VCO_CALIB (0x1U << BK4819_REG_30_SHIFT_ENABLE_VCO_CALIB)
#define BK4819_REG_30_MASK_ENABLE_UNKNOWN (0x1U << BK4819_REG_30_SHIFT_ENABLE_UNKNOWN)
#define BK4819_REG_30_MASK_ENABLE_RX_LINK (0xFU << BK4819_REG_30_SHIFT_ENABLE_RX_LINK)
#define BK4819_REG_30_MASK_ENABLE_AF_DAC (0x1U << BK4819_REG_30_SHIFT_ENABLE_AF_DAC)
#define BK4819_REG_30_MASK_ENABLE_DISC_MODE (0x1U << BK4819_REG_30_SHIFT_ENABLE_DISC_MODE)
#define BK4819_REG_30_MASK_ENABLE_PLL_VCO (0xFU << BK4819_REG_30_SHIFT_ENABLE_PLL_VCO)
#define BK4819_REG_30_MASK_ENABLE_PA_GAIN (0x1U << BK4819_REG_30_SHIFT_ENABLE_PA_GAIN)
#define BK4819_REG_30_MASK_ENABLE_MIC_ADC (0x1U << BK4819_REG_30_SHIFT_ENABLE_MIC_ADC)
#define BK4819_REG_30_MASK_ENABLE_TX_DSP (0x1U << BK4819_REG_30_SHIFT_ENABLE_TX_DSP)
#define BK4819_REG_30_MASK_ENABLE_RX_DSP (0x1U << BK4819_REG_30_SHIFT_ENABLE_RX_DSP)
#define BK4819_REG_30_MASK_ENABLE_VCO_CALIB (0x1U << BK4819_REG_30_SHIFT_ENABLE_VCO_CALIB)
#define BK4819_REG_30_MASK_ENABLE_UNKNOWN (0x1U << BK4819_REG_30_SHIFT_ENABLE_UNKNOWN)
#define BK4819_REG_30_MASK_ENABLE_RX_LINK (0xFU << BK4819_REG_30_SHIFT_ENABLE_RX_LINK)
#define BK4819_REG_30_MASK_ENABLE_AF_DAC (0x1U << BK4819_REG_30_SHIFT_ENABLE_AF_DAC)
#define BK4819_REG_30_MASK_ENABLE_DISC_MODE (0x1U << BK4819_REG_30_SHIFT_ENABLE_DISC_MODE)
#define BK4819_REG_30_MASK_ENABLE_PLL_VCO (0xFU << BK4819_REG_30_SHIFT_ENABLE_PLL_VCO)
#define BK4819_REG_30_MASK_ENABLE_PA_GAIN (0x1U << BK4819_REG_30_SHIFT_ENABLE_PA_GAIN)
#define BK4819_REG_30_MASK_ENABLE_MIC_ADC (0x1U << BK4819_REG_30_SHIFT_ENABLE_MIC_ADC)
#define BK4819_REG_30_MASK_ENABLE_TX_DSP (0x1U << BK4819_REG_30_SHIFT_ENABLE_TX_DSP)
#define BK4819_REG_30_MASK_ENABLE_RX_DSP (0x1U << BK4819_REG_30_SHIFT_ENABLE_RX_DSP)
enum {
BK4819_REG_30_ENABLE_VCO_CALIB = (0x1U << BK4819_REG_30_SHIFT_ENABLE_VCO_CALIB),
BK4819_REG_30_DISABLE_VCO_CALIB = (0x0U << BK4819_REG_30_SHIFT_ENABLE_VCO_CALIB),
BK4819_REG_30_ENABLE_UNKNOWN = (0x1U << BK4819_REG_30_SHIFT_ENABLE_UNKNOWN),
BK4819_REG_30_DISABLE_UNKNOWN = (0x0U << BK4819_REG_30_SHIFT_ENABLE_UNKNOWN),
BK4819_REG_30_ENABLE_RX_LINK = (0xFU << BK4819_REG_30_SHIFT_ENABLE_RX_LINK),
BK4819_REG_30_DISABLE_RX_LINK = (0x0U << BK4819_REG_30_SHIFT_ENABLE_RX_LINK),
BK4819_REG_30_ENABLE_AF_DAC = (0x1U << BK4819_REG_30_SHIFT_ENABLE_AF_DAC),
BK4819_REG_30_DISABLE_AF_DAC = (0x0U << BK4819_REG_30_SHIFT_ENABLE_AF_DAC),
BK4819_REG_30_ENABLE_DISC_MODE = (0x1U << BK4819_REG_30_SHIFT_ENABLE_DISC_MODE),
BK4819_REG_30_DISABLE_DISC_MODE = (0x0U << BK4819_REG_30_SHIFT_ENABLE_DISC_MODE),
BK4819_REG_30_ENABLE_PLL_VCO = (0xFU << BK4819_REG_30_SHIFT_ENABLE_PLL_VCO),
BK4819_REG_30_DISABLE_PLL_VCO = (0x0U << BK4819_REG_30_SHIFT_ENABLE_PLL_VCO),
BK4819_REG_30_ENABLE_PA_GAIN = (0x1U << BK4819_REG_30_SHIFT_ENABLE_PA_GAIN),
BK4819_REG_30_DISABLE_PA_GAIN = (0x0U << BK4819_REG_30_SHIFT_ENABLE_PA_GAIN),
BK4819_REG_30_ENABLE_MIC_ADC = (0x1U << BK4819_REG_30_SHIFT_ENABLE_MIC_ADC),
BK4819_REG_30_DISABLE_MIC_ADC = (0x0U << BK4819_REG_30_SHIFT_ENABLE_MIC_ADC),
BK4819_REG_30_ENABLE_TX_DSP = (0x1U << BK4819_REG_30_SHIFT_ENABLE_TX_DSP),
BK4819_REG_30_DISABLE_TX_DSP = (0x0U << BK4819_REG_30_SHIFT_ENABLE_TX_DSP),
BK4819_REG_30_ENABLE_RX_DSP = (0x1U << BK4819_REG_30_SHIFT_ENABLE_RX_DSP),
BK4819_REG_30_DISABLE_RX_DSP = (0x0U << BK4819_REG_30_SHIFT_ENABLE_RX_DSP),
BK4819_REG_30_ENABLE_VCO_CALIB = (0x1U << BK4819_REG_30_SHIFT_ENABLE_VCO_CALIB),
BK4819_REG_30_DISABLE_VCO_CALIB = (0x0U << BK4819_REG_30_SHIFT_ENABLE_VCO_CALIB),
BK4819_REG_30_ENABLE_UNKNOWN = (0x1U << BK4819_REG_30_SHIFT_ENABLE_UNKNOWN),
BK4819_REG_30_DISABLE_UNKNOWN = (0x0U << BK4819_REG_30_SHIFT_ENABLE_UNKNOWN),
BK4819_REG_30_ENABLE_RX_LINK = (0xFU << BK4819_REG_30_SHIFT_ENABLE_RX_LINK),
BK4819_REG_30_DISABLE_RX_LINK = (0x0U << BK4819_REG_30_SHIFT_ENABLE_RX_LINK),
BK4819_REG_30_ENABLE_AF_DAC = (0x1U << BK4819_REG_30_SHIFT_ENABLE_AF_DAC),
BK4819_REG_30_DISABLE_AF_DAC = (0x0U << BK4819_REG_30_SHIFT_ENABLE_AF_DAC),
BK4819_REG_30_ENABLE_DISC_MODE = (0x1U << BK4819_REG_30_SHIFT_ENABLE_DISC_MODE),
BK4819_REG_30_DISABLE_DISC_MODE = (0x0U << BK4819_REG_30_SHIFT_ENABLE_DISC_MODE),
BK4819_REG_30_ENABLE_PLL_VCO = (0xFU << BK4819_REG_30_SHIFT_ENABLE_PLL_VCO),
BK4819_REG_30_DISABLE_PLL_VCO = (0x0U << BK4819_REG_30_SHIFT_ENABLE_PLL_VCO),
BK4819_REG_30_ENABLE_PA_GAIN = (0x1U << BK4819_REG_30_SHIFT_ENABLE_PA_GAIN),
BK4819_REG_30_DISABLE_PA_GAIN = (0x0U << BK4819_REG_30_SHIFT_ENABLE_PA_GAIN),
BK4819_REG_30_ENABLE_MIC_ADC = (0x1U << BK4819_REG_30_SHIFT_ENABLE_MIC_ADC),
BK4819_REG_30_DISABLE_MIC_ADC = (0x0U << BK4819_REG_30_SHIFT_ENABLE_MIC_ADC),
BK4819_REG_30_ENABLE_TX_DSP = (0x1U << BK4819_REG_30_SHIFT_ENABLE_TX_DSP),
BK4819_REG_30_DISABLE_TX_DSP = (0x0U << BK4819_REG_30_SHIFT_ENABLE_TX_DSP),
BK4819_REG_30_ENABLE_RX_DSP = (0x1U << BK4819_REG_30_SHIFT_ENABLE_RX_DSP),
BK4819_REG_30_DISABLE_RX_DSP = (0x0U << BK4819_REG_30_SHIFT_ENABLE_RX_DSP),
};
// REG 3F
#define BK4819_REG_3F_SHIFT_FSK_TX_FINISHED 15
#define BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_EMPTY 14
#define BK4819_REG_3F_SHIFT_FSK_RX_FINISHED 13
#define BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_FULL 12
#define BK4819_REG_3F_SHIFT_DTMF_5TONE_FOUND 11
#define BK4819_REG_3F_SHIFT_CxCSS_TAIL 10
#define BK4819_REG_3F_SHIFT_CDCSS_FOUND 9
#define BK4819_REG_3F_SHIFT_CDCSS_LOST 8
#define BK4819_REG_3F_SHIFT_CTCSS_FOUND 7
#define BK4819_REG_3F_SHIFT_CTCSS_LOST 6
#define BK4819_REG_3F_SHIFT_VOX_FOUND 5
#define BK4819_REG_3F_SHIFT_VOX_LOST 4
#define BK4819_REG_3F_SHIFT_SQUELCH_FOUND 3
#define BK4819_REG_3F_SHIFT_SQUELCH_LOST 2
#define BK4819_REG_3F_SHIFT_FSK_RX_SYNC 1
#define BK4819_REG_3F_SHIFT_FSK_TX_FINISHED 15
#define BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_EMPTY 14
#define BK4819_REG_3F_SHIFT_FSK_RX_FINISHED 13
#define BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_FULL 12
#define BK4819_REG_3F_SHIFT_DTMF_5TONE_FOUND 11
#define BK4819_REG_3F_SHIFT_CxCSS_TAIL 10
#define BK4819_REG_3F_SHIFT_CDCSS_FOUND 9
#define BK4819_REG_3F_SHIFT_CDCSS_LOST 8
#define BK4819_REG_3F_SHIFT_CTCSS_FOUND 7
#define BK4819_REG_3F_SHIFT_CTCSS_LOST 6
#define BK4819_REG_3F_SHIFT_VOX_FOUND 5
#define BK4819_REG_3F_SHIFT_VOX_LOST 4
#define BK4819_REG_3F_SHIFT_SQUELCH_FOUND 3
#define BK4819_REG_3F_SHIFT_SQUELCH_LOST 2
#define BK4819_REG_3F_SHIFT_FSK_RX_SYNC 1
#define BK4819_REG_3F_MASK_FSK_TX_FINISHED (1U << BK4819_REG_3F_SHIFT_FSK_TX)
#define BK4819_REG_3F_MASK_FSK_FIFO_ALMOST_EMPTY (1U << BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_EMPTY)
#define BK4819_REG_3F_MASK_FSK_RX_FINISHED (1U << BK4819_REG_3F_SHIFT_FSK_RX_FINISHED)
#define BK4819_REG_3F_MASK_FSK_FIFO_ALMOST_FULL (1U << BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_FULL)
#define BK4819_REG_3F_MASK_DTMF_5TONE_FOUND (1U << BK4819_REG_3F_SHIFT_DTMF_5TONE_FOUND)
#define BK4819_REG_3F_MASK_CxCSS_TAIL (1U << BK4819_REG_3F_SHIFT_CxCSS_TAIL)
#define BK4819_REG_3F_MASK_CDCSS_FOUND (1U << BK4819_REG_3F_SHIFT_CDCSS_FOUND)
#define BK4819_REG_3F_MASK_CDCSS_LOST (1U << BK4819_REG_3F_SHIFT_CDCSS_LOST)
#define BK4819_REG_3F_MASK_CTCSS_FOUND (1U << BK4819_REG_3F_SHIFT_CTCSS_FOUND)
#define BK4819_REG_3F_MASK_CTCSS_LOST (1U << BK4819_REG_3F_SHIFT_CTCSS_LOST)
#define BK4819_REG_3F_MASK_VOX_FOUND (1U << BK4819_REG_3F_SHIFT_VOX_FOUND)
#define BK4819_REG_3F_MASK_VOX_LOST (1U << BK4819_REG_3F_SHIFT_VOX_LOST)
#define BK4819_REG_3F_MASK_SQUELCH_FOUND (1U << BK4819_REG_3F_SHIFT_SQUELCH_FOUND)
#define BK4819_REG_3F_MASK_SQUELCH_LOST (1U << BK4819_REG_3F_SHIFT_SQUELCH_LOST)
#define BK4819_REG_3F_MASK_FSK_RX_SYNC (1U << BK4819_REG_3F_SHIFT_FSK_RX_SYNC)
#define BK4819_REG_3F_MASK_FSK_TX_FINISHED (1U << BK4819_REG_3F_SHIFT_FSK_TX)
#define BK4819_REG_3F_MASK_FSK_FIFO_ALMOST_EMPTY (1U << BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_EMPTY)
#define BK4819_REG_3F_MASK_FSK_RX_FINISHED (1U << BK4819_REG_3F_SHIFT_FSK_RX_FINISHED)
#define BK4819_REG_3F_MASK_FSK_FIFO_ALMOST_FULL (1U << BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_FULL)
#define BK4819_REG_3F_MASK_DTMF_5TONE_FOUND (1U << BK4819_REG_3F_SHIFT_DTMF_5TONE_FOUND)
#define BK4819_REG_3F_MASK_CxCSS_TAIL (1U << BK4819_REG_3F_SHIFT_CxCSS_TAIL)
#define BK4819_REG_3F_MASK_CDCSS_FOUND (1U << BK4819_REG_3F_SHIFT_CDCSS_FOUND)
#define BK4819_REG_3F_MASK_CDCSS_LOST (1U << BK4819_REG_3F_SHIFT_CDCSS_LOST)
#define BK4819_REG_3F_MASK_CTCSS_FOUND (1U << BK4819_REG_3F_SHIFT_CTCSS_FOUND)
#define BK4819_REG_3F_MASK_CTCSS_LOST (1U << BK4819_REG_3F_SHIFT_CTCSS_LOST)
#define BK4819_REG_3F_MASK_VOX_FOUND (1U << BK4819_REG_3F_SHIFT_VOX_FOUND)
#define BK4819_REG_3F_MASK_VOX_LOST (1U << BK4819_REG_3F_SHIFT_VOX_LOST)
#define BK4819_REG_3F_MASK_SQUELCH_FOUND (1U << BK4819_REG_3F_SHIFT_SQUELCH_FOUND)
#define BK4819_REG_3F_MASK_SQUELCH_LOST (1U << BK4819_REG_3F_SHIFT_SQUELCH_LOST)
#define BK4819_REG_3F_MASK_FSK_RX_SYNC (1U << BK4819_REG_3F_SHIFT_FSK_RX_SYNC)
#define BK4819_REG_3F_FSK_TX_FINISHED (1U << BK4819_REG_3F_SHIFT_FSK_TX_FINISHED)
#define BK4819_REG_3F_FSK_FIFO_ALMOST_EMPTY (1U << BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_EMPTY)
#define BK4819_REG_3F_FSK_RX_FINISHED (1U << BK4819_REG_3F_SHIFT_FSK_RX_FINISHED)
#define BK4819_REG_3F_FSK_FIFO_ALMOST_FULL (1U << BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_FULL)
#define BK4819_REG_3F_DTMF_5TONE_FOUND (1U << BK4819_REG_3F_SHIFT_DTMF_5TONE_FOUND)
#define BK4819_REG_3F_CxCSS_TAIL (1U << BK4819_REG_3F_SHIFT_CxCSS_TAIL)
#define BK4819_REG_3F_CDCSS_FOUND (1U << BK4819_REG_3F_SHIFT_CDCSS_FOUND)
#define BK4819_REG_3F_CDCSS_LOST (1U << BK4819_REG_3F_SHIFT_CDCSS_LOST)
#define BK4819_REG_3F_CTCSS_FOUND (1U << BK4819_REG_3F_SHIFT_CTCSS_FOUND)
#define BK4819_REG_3F_CTCSS_LOST (1U << BK4819_REG_3F_SHIFT_CTCSS_LOST)
#define BK4819_REG_3F_VOX_FOUND (1U << BK4819_REG_3F_SHIFT_VOX_FOUND)
#define BK4819_REG_3F_VOX_LOST (1U << BK4819_REG_3F_SHIFT_VOX_LOST)
#define BK4819_REG_3F_SQUELCH_FOUND (1U << BK4819_REG_3F_SHIFT_SQUELCH_FOUND)
#define BK4819_REG_3F_SQUELCH_LOST (1U << BK4819_REG_3F_SHIFT_SQUELCH_LOST)
#define BK4819_REG_3F_FSK_RX_SYNC (1U << BK4819_REG_3F_SHIFT_FSK_RX_SYNC)
#define BK4819_REG_3F_FSK_TX_FINISHED (1U << BK4819_REG_3F_SHIFT_FSK_TX_FINISHED)
#define BK4819_REG_3F_FSK_FIFO_ALMOST_EMPTY (1U << BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_EMPTY)
#define BK4819_REG_3F_FSK_RX_FINISHED (1U << BK4819_REG_3F_SHIFT_FSK_RX_FINISHED)
#define BK4819_REG_3F_FSK_FIFO_ALMOST_FULL (1U << BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_FULL)
#define BK4819_REG_3F_DTMF_5TONE_FOUND (1U << BK4819_REG_3F_SHIFT_DTMF_5TONE_FOUND)
#define BK4819_REG_3F_CxCSS_TAIL (1U << BK4819_REG_3F_SHIFT_CxCSS_TAIL)
#define BK4819_REG_3F_CDCSS_FOUND (1U << BK4819_REG_3F_SHIFT_CDCSS_FOUND)
#define BK4819_REG_3F_CDCSS_LOST (1U << BK4819_REG_3F_SHIFT_CDCSS_LOST)
#define BK4819_REG_3F_CTCSS_FOUND (1U << BK4819_REG_3F_SHIFT_CTCSS_FOUND)
#define BK4819_REG_3F_CTCSS_LOST (1U << BK4819_REG_3F_SHIFT_CTCSS_LOST)
#define BK4819_REG_3F_VOX_FOUND (1U << BK4819_REG_3F_SHIFT_VOX_FOUND)
#define BK4819_REG_3F_VOX_LOST (1U << BK4819_REG_3F_SHIFT_VOX_LOST)
#define BK4819_REG_3F_SQUELCH_FOUND (1U << BK4819_REG_3F_SHIFT_SQUELCH_FOUND)
#define BK4819_REG_3F_SQUELCH_LOST (1U << BK4819_REG_3F_SHIFT_SQUELCH_LOST)
#define BK4819_REG_3F_FSK_RX_SYNC (1U << BK4819_REG_3F_SHIFT_FSK_RX_SYNC)
// REG 51
@@ -345,46 +345,46 @@ enum {
#define BK4819_REG_51_MASK_CxCSS_TX_GAIN1 (0x7FU << BK4819_REG_51_SHIFT_CxCSS_TX_GAIN1)
enum {
BK4819_REG_51_ENABLE_CxCSS = (1U << BK4819_REG_51_SHIFT_ENABLE_CxCSS),
BK4819_REG_51_DISABLE_CxCSS = (0U << BK4819_REG_51_SHIFT_ENABLE_CxCSS),
BK4819_REG_51_ENABLE_CxCSS = (1U << BK4819_REG_51_SHIFT_ENABLE_CxCSS),
BK4819_REG_51_DISABLE_CxCSS = (0U << BK4819_REG_51_SHIFT_ENABLE_CxCSS),
BK4819_REG_51_GPIO6_PIN2_INPUT = (1U << BK4819_REG_51_SHIFT_GPIO6_PIN2_INPUT),
BK4819_REG_51_GPIO6_PIN2_NORMAL = (0U << BK4819_REG_51_SHIFT_GPIO6_PIN2_INPUT),
BK4819_REG_51_GPIO6_PIN2_INPUT = (1U << BK4819_REG_51_SHIFT_GPIO6_PIN2_INPUT),
BK4819_REG_51_GPIO6_PIN2_NORMAL = (0U << BK4819_REG_51_SHIFT_GPIO6_PIN2_INPUT),
BK4819_REG_51_TX_CDCSS_NEGATIVE = (1U << BK4819_REG_51_SHIFT_TX_CDCSS_POLARITY),
BK4819_REG_51_TX_CDCSS_POSITIVE = (0U << BK4819_REG_51_SHIFT_TX_CDCSS_POLARITY),
BK4819_REG_51_TX_CDCSS_NEGATIVE = (1U << BK4819_REG_51_SHIFT_TX_CDCSS_POLARITY),
BK4819_REG_51_TX_CDCSS_POSITIVE = (0U << BK4819_REG_51_SHIFT_TX_CDCSS_POLARITY),
BK4819_REG_51_MODE_CTCSS = (1U << BK4819_REG_51_SHIFT_CxCSS_MODE),
BK4819_REG_51_MODE_CDCSS = (0U << BK4819_REG_51_SHIFT_CxCSS_MODE),
BK4819_REG_51_MODE_CTCSS = (1U << BK4819_REG_51_SHIFT_CxCSS_MODE),
BK4819_REG_51_MODE_CDCSS = (0U << BK4819_REG_51_SHIFT_CxCSS_MODE),
BK4819_REG_51_CDCSS_24_BIT = (1U << BK4819_REG_51_SHIFT_CDCSS_BIT_WIDTH),
BK4819_REG_51_CDCSS_23_BIT = (0U << BK4819_REG_51_SHIFT_CDCSS_BIT_WIDTH),
BK4819_REG_51_CDCSS_24_BIT = (1U << BK4819_REG_51_SHIFT_CDCSS_BIT_WIDTH),
BK4819_REG_51_CDCSS_23_BIT = (0U << BK4819_REG_51_SHIFT_CDCSS_BIT_WIDTH),
BK4819_REG_51_1050HZ_DETECTION = (1U << BK4819_REG_51_SHIFT_1050HZ_DETECTION),
BK4819_REG_51_1050HZ_NO_DETECTION = (0U << BK4819_REG_51_SHIFT_1050HZ_DETECTION),
BK4819_REG_51_1050HZ_DETECTION = (1U << BK4819_REG_51_SHIFT_1050HZ_DETECTION),
BK4819_REG_51_1050HZ_NO_DETECTION = (0U << BK4819_REG_51_SHIFT_1050HZ_DETECTION),
BK4819_REG_51_AUTO_CDCSS_BW_DISABLE = (1U << BK4819_REG_51_SHIFT_AUTO_CDCSS_BW),
BK4819_REG_51_AUTO_CDCSS_BW_ENABLE = (0U << BK4819_REG_51_SHIFT_AUTO_CDCSS_BW),
BK4819_REG_51_AUTO_CDCSS_BW_DISABLE = (1U << BK4819_REG_51_SHIFT_AUTO_CDCSS_BW),
BK4819_REG_51_AUTO_CDCSS_BW_ENABLE = (0U << BK4819_REG_51_SHIFT_AUTO_CDCSS_BW),
BK4819_REG_51_AUTO_CTCSS_BW_DISABLE = (1U << BK4819_REG_51_SHIFT_AUTO_CTCSS_BW),
BK4819_REG_51_AUTO_CTCSS_BW_ENABLE = (0U << BK4819_REG_51_SHIFT_AUTO_CTCSS_BW),
BK4819_REG_51_AUTO_CTCSS_BW_DISABLE = (1U << BK4819_REG_51_SHIFT_AUTO_CTCSS_BW),
BK4819_REG_51_AUTO_CTCSS_BW_ENABLE = (0U << BK4819_REG_51_SHIFT_AUTO_CTCSS_BW),
};
// REG 70
#define BK4819_REG_70_SHIFT_ENABLE_TONE1 15
#define BK4819_REG_70_SHIFT_TONE1_TUNING_GAIN 8
#define BK4819_REG_70_SHIFT_ENABLE_TONE2 7
#define BK4819_REG_70_SHIFT_TONE2_TUNING_GAIN 0
#define BK4819_REG_70_SHIFT_ENABLE_TONE1 15
#define BK4819_REG_70_SHIFT_TONE1_TUNING_GAIN 8
#define BK4819_REG_70_SHIFT_ENABLE_TONE2 7
#define BK4819_REG_70_SHIFT_TONE2_TUNING_GAIN 0
#define BK4819_REG_70_MASK_ENABLE_TONE1 (0x01U << BK4819_REG_70_SHIFT_ENABLE_TONE1)
#define BK4819_REG_70_MASK_TONE1_TUNING_GAIN (0x7FU << BK4819_REG_70_SHIFT_TONE1_TUNING_GAIN)
#define BK4819_REG_70_MASK_ENABLE_TONE2 (0x01U << BK4819_REG_70_SHIFT_ENABLE_TONE2)
#define BK4819_REG_70_MASK_TONE2_TUNING_GAIN (0x7FU << BK4819_REG_70_SHIFT_TONE2_TUNING_GAIN)
#define BK4819_REG_70_MASK_ENABLE_TONE1 (0x01U << BK4819_REG_70_SHIFT_ENABLE_TONE1)
#define BK4819_REG_70_MASK_TONE1_TUNING_GAIN (0x7FU << BK4819_REG_70_SHIFT_TONE1_TUNING_GAIN)
#define BK4819_REG_70_MASK_ENABLE_TONE2 (0x01U << BK4819_REG_70_SHIFT_ENABLE_TONE2)
#define BK4819_REG_70_MASK_TONE2_TUNING_GAIN (0x7FU << BK4819_REG_70_SHIFT_TONE2_TUNING_GAIN)
enum {
BK4819_REG_70_ENABLE_TONE1 = (1U << BK4819_REG_70_SHIFT_ENABLE_TONE1),
BK4819_REG_70_ENABLE_TONE2 = (1U << BK4819_REG_70_SHIFT_ENABLE_TONE2),
BK4819_REG_70_ENABLE_TONE1 = (1U << BK4819_REG_70_SHIFT_ENABLE_TONE1),
BK4819_REG_70_ENABLE_TONE2 = (1U << BK4819_REG_70_SHIFT_ENABLE_TONE2),
};
#endif

2586
driver/bk4819.c
View File

File diff suppressed because it is too large Load Diff

58
driver/bk4819.h
View File

@@ -24,40 +24,40 @@
enum BK4819_AF_Type_t
{
BK4819_AF_MUTE = 0u, //
BK4819_AF_FM = 1u, // FM
BK4819_AF_ALAM = 2u, //
BK4819_AF_BEEP = 3u, //
BK4819_AF_BASEBAND1 = 4u, // RAW
BK4819_AF_BASEBAND2 = 5u, // USB
BK4819_AF_CTCO = 6u, // strange LF audio .. maybe the CTCSS LF line ?
BK4819_AF_AM = 7u, // AM
BK4819_AF_FSKO = 8u, // nothing
BK4819_AF_UNKNOWN3 = 9u, // BYP
BK4819_AF_UNKNOWN4 = 10u, // nothing at all
BK4819_AF_UNKNOWN5 = 11u, // distorted
BK4819_AF_UNKNOWN6 = 12u, // distorted
BK4819_AF_UNKNOWN7 = 13u, // interesting
BK4819_AF_UNKNOWN8 = 14u, // interesting
BK4819_AF_UNKNOWN9 = 15u // not a lot
BK4819_AF_MUTE = 0u, //
BK4819_AF_FM = 1u, // FM
BK4819_AF_ALAM = 2u, //
BK4819_AF_BEEP = 3u, //
BK4819_AF_BASEBAND1 = 4u, // RAW
BK4819_AF_BASEBAND2 = 5u, // USB
BK4819_AF_CTCO = 6u, // strange LF audio .. maybe the CTCSS LF line ?
BK4819_AF_AM = 7u, // AM
BK4819_AF_FSKO = 8u, // nothing
BK4819_AF_UNKNOWN3 = 9u, // BYP
BK4819_AF_UNKNOWN4 = 10u, // nothing at all
BK4819_AF_UNKNOWN5 = 11u, // distorted
BK4819_AF_UNKNOWN6 = 12u, // distorted
BK4819_AF_UNKNOWN7 = 13u, // interesting
BK4819_AF_UNKNOWN8 = 14u, // interesting
BK4819_AF_UNKNOWN9 = 15u // not a lot
};
typedef enum BK4819_AF_Type_t BK4819_AF_Type_t;
enum BK4819_FilterBandwidth_t
{
BK4819_FILTER_BW_WIDE = 0,
BK4819_FILTER_BW_NARROW,
BK4819_FILTER_BW_NARROWER
BK4819_FILTER_BW_WIDE = 0,
BK4819_FILTER_BW_NARROW,
BK4819_FILTER_BW_NARROWER
};
typedef enum BK4819_FilterBandwidth_t BK4819_FilterBandwidth_t;
enum BK4819_CssScanResult_t
{
BK4819_CSS_RESULT_NOT_FOUND = 0,
BK4819_CSS_RESULT_CTCSS,
BK4819_CSS_RESULT_CDCSS
BK4819_CSS_RESULT_NOT_FOUND = 0,
BK4819_CSS_RESULT_CTCSS,
BK4819_CSS_RESULT_CDCSS
};
typedef enum BK4819_CssScanResult_t BK4819_CssScanResult_t;
@@ -85,12 +85,12 @@ void BK4819_SetFilterBandwidth(const BK4819_FilterBandwidth_t Bandwidth, con
void BK4819_SetupPowerAmplifier(const uint8_t bias, const uint32_t frequency);
void BK4819_SetFrequency(uint32_t Frequency);
void BK4819_SetupSquelch(
uint8_t SquelchOpenRSSIThresh,
uint8_t SquelchCloseRSSIThresh,
uint8_t SquelchOpenNoiseThresh,
uint8_t SquelchCloseNoiseThresh,
uint8_t SquelchCloseGlitchThresh,
uint8_t SquelchOpenGlitchThresh);
uint8_t SquelchOpenRSSIThresh,
uint8_t SquelchCloseRSSIThresh,
uint8_t SquelchOpenNoiseThresh,
uint8_t SquelchCloseNoiseThresh,
uint8_t SquelchCloseGlitchThresh,
uint8_t SquelchOpenGlitchThresh);
void BK4819_SetAF(BK4819_AF_Type_t AF);
void BK4819_RX_TurnOn(void);
@@ -111,7 +111,7 @@ void BK4819_ExitTxMute(void);
void BK4819_Sleep(void);
void BK4819_TurnsOffTones_TurnsOnRX(void);
#ifdef ENABLE_AIRCOPY
void BK4819_SetupAircopy(void);
void BK4819_SetupAircopy(void);
#endif
void BK4819_ResetFSK(void);
void BK4819_Idle(void);

38
driver/crc.c
View File

@@ -19,31 +19,31 @@
void CRC_Init(void)
{
CRC_CR = 0
| CRC_CR_CRC_EN_BITS_DISABLE
| CRC_CR_INPUT_REV_BITS_NORMAL
| CRC_CR_INPUT_INV_BITS_NORMAL
| CRC_CR_OUTPUT_REV_BITS_NORMAL
| CRC_CR_OUTPUT_INV_BITS_NORMAL
| CRC_CR_DATA_WIDTH_BITS_8
| CRC_CR_CRC_SEL_BITS_CRC_16_CCITT
;
CRC_IV = 0;
CRC_CR = 0
| CRC_CR_CRC_EN_BITS_DISABLE
| CRC_CR_INPUT_REV_BITS_NORMAL
| CRC_CR_INPUT_INV_BITS_NORMAL
| CRC_CR_OUTPUT_REV_BITS_NORMAL
| CRC_CR_OUTPUT_INV_BITS_NORMAL
| CRC_CR_DATA_WIDTH_BITS_8
| CRC_CR_CRC_SEL_BITS_CRC_16_CCITT
;
CRC_IV = 0;
}
uint16_t CRC_Calculate(const void *pBuffer, uint16_t Size)
{
const uint8_t *pData = (const uint8_t *)pBuffer;
uint16_t i, Crc;
const uint8_t *pData = (const uint8_t *)pBuffer;
uint16_t i, Crc;
CRC_CR = (CRC_CR & ~CRC_CR_CRC_EN_MASK) | CRC_CR_CRC_EN_BITS_ENABLE;
CRC_CR = (CRC_CR & ~CRC_CR_CRC_EN_MASK) | CRC_CR_CRC_EN_BITS_ENABLE;
for (i = 0; i < Size; i++) {
CRC_DATAIN = pData[i];
}
Crc = (uint16_t)CRC_DATAOUT;
for (i = 0; i < Size; i++) {
CRC_DATAIN = pData[i];
}
Crc = (uint16_t)CRC_DATAOUT;
CRC_CR = (CRC_CR & ~CRC_CR_CRC_EN_MASK) | CRC_CR_CRC_EN_BITS_DISABLE;
CRC_CR = (CRC_CR & ~CRC_CR_CRC_EN_MASK) | CRC_CR_CRC_EN_BITS_DISABLE;
return Crc;
return Crc;
}

46
driver/eeprom.c
View File

@@ -23,41 +23,41 @@
void EEPROM_ReadBuffer(uint16_t Address, void *pBuffer, uint8_t Size)
{
I2C_Start();
I2C_Start();
I2C_Write(0xA0);
I2C_Write(0xA0);
I2C_Write((Address >> 8) & 0xFF);
I2C_Write((Address >> 0) & 0xFF);
I2C_Write((Address >> 8) & 0xFF);
I2C_Write((Address >> 0) & 0xFF);
I2C_Start();
I2C_Start();
I2C_Write(0xA1);
I2C_Write(0xA1);
I2C_ReadBuffer(pBuffer, Size);
I2C_ReadBuffer(pBuffer, Size);
I2C_Stop();
I2C_Stop();
}
void EEPROM_WriteBuffer(uint16_t Address, const void *pBuffer)
{
if (pBuffer == NULL || Address >= 0x2000)
return;
if (pBuffer == NULL || Address >= 0x2000)
return;
uint8_t buffer[8];
EEPROM_ReadBuffer(Address, buffer, 8);
if (memcmp(pBuffer, buffer, 8) == 0) {
return;
}
uint8_t buffer[8];
EEPROM_ReadBuffer(Address, buffer, 8);
if (memcmp(pBuffer, buffer, 8) == 0) {
return;
}
I2C_Start();
I2C_Write(0xA0);
I2C_Write((Address >> 8) & 0xFF);
I2C_Write((Address >> 0) & 0xFF);
I2C_WriteBuffer(pBuffer, 8);
I2C_Stop();
I2C_Start();
I2C_Write(0xA0);
I2C_Write((Address >> 8) & 0xFF);
I2C_Write((Address >> 0) & 0xFF);
I2C_WriteBuffer(pBuffer, 8);
I2C_Stop();
// give the EEPROM time to burn the data in (apparently takes 5ms)
SYSTEM_DelayMs(8);
// give the EEPROM time to burn the data in (apparently takes 5ms)
SYSTEM_DelayMs(8);
}

6
driver/flash.c
View File

@@ -19,15 +19,15 @@
void FLASH_Init(FLASH_READ_MODE ReadMode)
{
overlay_FLASH_Init(ReadMode);
overlay_FLASH_Init(ReadMode);
}
void FLASH_ConfigureTrimValues(void)
{
overlay_FLASH_ConfigureTrimValues();
overlay_FLASH_ConfigureTrimValues();
}
uint32_t FLASH_ReadNvrWord(uint32_t Address)
{
return overlay_FLASH_ReadNvrWord(Address);
return overlay_FLASH_ReadNvrWord(Address);
}

24
driver/flash.h
View File

@@ -20,33 +20,33 @@
#include "bsp/dp32g030/flash.h"
enum FLASH_READ_MODE {
FLASH_READ_MODE_1_CYCLE = FLASH_CFG_READ_MD_VALUE_1_CYCLE,
FLASH_READ_MODE_2_CYCLE = FLASH_CFG_READ_MD_VALUE_2_CYCLE,
FLASH_READ_MODE_1_CYCLE = FLASH_CFG_READ_MD_VALUE_1_CYCLE,
FLASH_READ_MODE_2_CYCLE = FLASH_CFG_READ_MD_VALUE_2_CYCLE,
};
typedef enum FLASH_READ_MODE FLASH_READ_MODE;
enum FLASH_MASK_SELECTION {
FLASH_MASK_SELECTION_NONE = FLASH_MASK_SEL_VALUE_NONE,
FLASH_MASK_SELECTION_2KB = FLASH_MASK_SEL_VALUE_2KB,
FLASH_MASK_SELECTION_4KB = FLASH_MASK_SEL_VALUE_4KB,
FLASH_MASK_SELECTION_8KB = FLASH_MASK_SEL_VALUE_8KB,
FLASH_MASK_SELECTION_NONE = FLASH_MASK_SEL_VALUE_NONE,
FLASH_MASK_SELECTION_2KB = FLASH_MASK_SEL_VALUE_2KB,
FLASH_MASK_SELECTION_4KB = FLASH_MASK_SEL_VALUE_4KB,
FLASH_MASK_SELECTION_8KB = FLASH_MASK_SEL_VALUE_8KB,
};
typedef enum FLASH_MASK_SELECTION FLASH_MASK_SELECTION;
enum FLASH_MODE {
FLASH_MODE_READ_AHB = FLASH_CFG_MODE_VALUE_READ_AHB,
FLASH_MODE_PROGRAM = FLASH_CFG_MODE_VALUE_PROGRAM,
FLASH_MODE_ERASE = FLASH_CFG_MODE_VALUE_ERASE,
FLASH_MODE_READ_APB = FLASH_CFG_MODE_VALUE_READ_APB,
FLASH_MODE_READ_AHB = FLASH_CFG_MODE_VALUE_READ_AHB,
FLASH_MODE_PROGRAM = FLASH_CFG_MODE_VALUE_PROGRAM,
FLASH_MODE_ERASE = FLASH_CFG_MODE_VALUE_ERASE,
FLASH_MODE_READ_APB = FLASH_CFG_MODE_VALUE_READ_APB,
};
typedef enum FLASH_MODE FLASH_MODE;
enum FLASH_AREA {
FLASH_AREA_MAIN = FLASH_CFG_NVR_SEL_VALUE_MAIN,
FLASH_AREA_NVR = FLASH_CFG_NVR_SEL_VALUE_NVR,
FLASH_AREA_MAIN = FLASH_CFG_NVR_SEL_VALUE_MAIN,
FLASH_AREA_NVR = FLASH_CFG_NVR_SEL_VALUE_NVR,
};
typedef enum FLASH_AREA FLASH_AREA;

56
driver/gpio.h
View File

@@ -20,58 +20,58 @@
#include <stdint.h>
enum GPIOA_PINS {
GPIOA_PIN_KEYBOARD_0 = 3,
GPIOA_PIN_KEYBOARD_1 = 4,
GPIOA_PIN_KEYBOARD_2 = 5,
GPIOA_PIN_KEYBOARD_3 = 6,
GPIOA_PIN_KEYBOARD_4 = 10, // Shared with I2C!
GPIOA_PIN_KEYBOARD_5 = 11, // Shared with I2C!
GPIOA_PIN_KEYBOARD_6 = 12, // Shared with voice chip!
GPIOA_PIN_KEYBOARD_7 = 13, // Shared with voice chip!
GPIOA_PIN_KEYBOARD_0 = 3,
GPIOA_PIN_KEYBOARD_1 = 4,
GPIOA_PIN_KEYBOARD_2 = 5,
GPIOA_PIN_KEYBOARD_3 = 6,
GPIOA_PIN_KEYBOARD_4 = 10, // Shared with I2C!
GPIOA_PIN_KEYBOARD_5 = 11, // Shared with I2C!
GPIOA_PIN_KEYBOARD_6 = 12, // Shared with voice chip!
GPIOA_PIN_KEYBOARD_7 = 13, // Shared with voice chip!
GPIOA_PIN_I2C_SCL = 10, // Shared with keyboard!
GPIOA_PIN_I2C_SDA = 11, // Shared with keyboard!
GPIOA_PIN_I2C_SCL = 10, // Shared with keyboard!
GPIOA_PIN_I2C_SDA = 11, // Shared with keyboard!
GPIOA_PIN_VOICE_0 = 12, // Shared with keyboard!
GPIOA_PIN_VOICE_1 = 13 // Shared with keyboard!
GPIOA_PIN_VOICE_0 = 12, // Shared with keyboard!
GPIOA_PIN_VOICE_1 = 13 // Shared with keyboard!
};
enum GPIOB_PINS {
GPIOB_PIN_BACKLIGHT = 6,
GPIOB_PIN_BACKLIGHT = 6,
GPIOB_PIN_ST7565_A0 = 9,
GPIOB_PIN_ST7565_RES = 11, // Shared with SWD!
GPIOB_PIN_ST7565_A0 = 9,
GPIOB_PIN_ST7565_RES = 11, // Shared with SWD!
GPIOB_PIN_SWD_IO = 11, // Shared with ST7565!
GPIOB_PIN_SWD_CLK = 14,
GPIOB_PIN_SWD_IO = 11, // Shared with ST7565!
GPIOB_PIN_SWD_CLK = 14,
GPIOB_PIN_BK1080 = 15
GPIOB_PIN_BK1080 = 15
};
enum GPIOC_PINS {
GPIOC_PIN_BK4819_SCN = 0,
GPIOC_PIN_BK4819_SCL = 1,
GPIOC_PIN_BK4819_SDA = 2,
GPIOC_PIN_BK4819_SCN = 0,
GPIOC_PIN_BK4819_SCL = 1,
GPIOC_PIN_BK4819_SDA = 2,
GPIOC_PIN_FLASHLIGHT = 3,
GPIOC_PIN_AUDIO_PATH = 4,
GPIOC_PIN_PTT = 5
GPIOC_PIN_FLASHLIGHT = 3,
GPIOC_PIN_AUDIO_PATH = 4,
GPIOC_PIN_PTT = 5
};
static inline void GPIO_ClearBit(volatile uint32_t *pReg, uint8_t Bit) {
*pReg &= ~(1U << Bit);
*pReg &= ~(1U << Bit);
}
static inline uint8_t GPIO_CheckBit(volatile uint32_t *pReg, uint8_t Bit) {
return (*pReg >> Bit) & 1U;
return (*pReg >> Bit) & 1U;
}
static inline void GPIO_FlipBit(volatile uint32_t *pReg, uint8_t Bit) {
*pReg ^= 1U << Bit;
*pReg ^= 1U << Bit;
}
static inline void GPIO_SetBit(volatile uint32_t *pReg, uint8_t Bit) {
*pReg |= 1U << Bit;
*pReg |= 1U << Bit;
}
#endif

208
driver/i2c.c
View File

@@ -22,143 +22,143 @@
void I2C_Start(void)
{
GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);
SYSTICK_DelayUs(1);
GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);
SYSTICK_DelayUs(1);
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);
SYSTICK_DelayUs(1);
GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);
SYSTICK_DelayUs(1);
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
}
void I2C_Stop(void)
{
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);
SYSTICK_DelayUs(1);
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);
SYSTICK_DelayUs(1);
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);
SYSTICK_DelayUs(1);
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);
SYSTICK_DelayUs(1);
}
uint8_t I2C_Read(bool bFinal)
{
uint8_t i, Data;
uint8_t i, Data;
PORTCON_PORTA_IE |= PORTCON_PORTA_IE_A11_BITS_ENABLE;
PORTCON_PORTA_OD &= ~PORTCON_PORTA_OD_A11_MASK;
GPIOA->DIR &= ~GPIO_DIR_11_MASK;
PORTCON_PORTA_IE |= PORTCON_PORTA_IE_A11_BITS_ENABLE;
PORTCON_PORTA_OD &= ~PORTCON_PORTA_OD_A11_MASK;
GPIOA->DIR &= ~GPIO_DIR_11_MASK;
Data = 0;
for (i = 0; i < 8; i++) {
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
Data <<= 1;
SYSTICK_DelayUs(1);
if (GPIO_CheckBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA)) {
Data |= 1U;
}
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
}
Data = 0;
for (i = 0; i < 8; i++) {
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
Data <<= 1;
SYSTICK_DelayUs(1);
if (GPIO_CheckBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA)) {
Data |= 1U;
}
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
}
PORTCON_PORTA_IE &= ~PORTCON_PORTA_IE_A11_MASK;
PORTCON_PORTA_OD |= PORTCON_PORTA_OD_A11_BITS_ENABLE;
GPIOA->DIR |= GPIO_DIR_11_BITS_OUTPUT;
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
if (bFinal) {
GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);
} else {
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);
}
SYSTICK_DelayUs(1);
GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
PORTCON_PORTA_IE &= ~PORTCON_PORTA_IE_A11_MASK;
PORTCON_PORTA_OD |= PORTCON_PORTA_OD_A11_BITS_ENABLE;
GPIOA->DIR |= GPIO_DIR_11_BITS_OUTPUT;
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
if (bFinal) {
GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);
} else {
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);
}
SYSTICK_DelayUs(1);
GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
return Data;
return Data;
}
int I2C_Write(uint8_t Data)
{
uint8_t i;
int ret = -1;
uint8_t i;
int ret = -1;
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
for (i = 0; i < 8; i++) {
if ((Data & 0x80) == 0) {
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);
} else {
GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);
}
Data <<= 1;
SYSTICK_DelayUs(1);
GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
}
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
for (i = 0; i < 8; i++) {
if ((Data & 0x80) == 0) {
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);
} else {
GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);
}
Data <<= 1;
SYSTICK_DelayUs(1);
GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
}
PORTCON_PORTA_IE |= PORTCON_PORTA_IE_A11_BITS_ENABLE;
PORTCON_PORTA_OD &= ~PORTCON_PORTA_OD_A11_MASK;
GPIOA->DIR &= ~GPIO_DIR_11_MASK;
GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);
SYSTICK_DelayUs(1);
GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
PORTCON_PORTA_IE |= PORTCON_PORTA_IE_A11_BITS_ENABLE;
PORTCON_PORTA_OD &= ~PORTCON_PORTA_OD_A11_MASK;
GPIOA->DIR &= ~GPIO_DIR_11_MASK;
GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);
SYSTICK_DelayUs(1);
GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
for (i = 0; i < 255; i++) {
if (GPIO_CheckBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA) == 0) {
ret = 0;
break;
}
}
for (i = 0; i < 255; i++) {
if (GPIO_CheckBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA) == 0) {
ret = 0;
break;
}
}
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
PORTCON_PORTA_IE &= ~PORTCON_PORTA_IE_A11_MASK;
PORTCON_PORTA_OD |= PORTCON_PORTA_OD_A11_BITS_ENABLE;
GPIOA->DIR |= GPIO_DIR_11_BITS_OUTPUT;
GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_I2C_SCL);
SYSTICK_DelayUs(1);
PORTCON_PORTA_IE &= ~PORTCON_PORTA_IE_A11_MASK;
PORTCON_PORTA_OD |= PORTCON_PORTA_OD_A11_BITS_ENABLE;
GPIOA->DIR |= GPIO_DIR_11_BITS_OUTPUT;
GPIO_SetBit(&GPIOA->DATA, GPIOA_PIN_I2C_SDA);
return ret;
return ret;
}
int I2C_ReadBuffer(void *pBuffer, uint8_t Size)
{
uint8_t *pData = (uint8_t *)pBuffer;
uint8_t i;
uint8_t *pData = (uint8_t *)pBuffer;
uint8_t i;
for (i = 0; i < Size - 1; i++) {
SYSTICK_DelayUs(1);
pData[i] = I2C_Read(false);
}
for (i = 0; i < Size - 1; i++) {
SYSTICK_DelayUs(1);
pData[i] = I2C_Read(false);
}
SYSTICK_DelayUs(1);
pData[i] = I2C_Read(true);
SYSTICK_DelayUs(1);
pData[i] = I2C_Read(true);
return Size;
return Size;
}
int I2C_WriteBuffer(const void *pBuffer, uint8_t Size)
{
const uint8_t *pData = (const uint8_t *)pBuffer;
uint8_t i;
const uint8_t *pData = (const uint8_t *)pBuffer;
uint8_t i;
for (i = 0; i < Size; i++) {
if (I2C_Write(*pData++) < 0) {
return -1;
}
}
for (i = 0; i < Size; i++) {
if (I2C_Write(*pData++) < 0) {
return -1;
}
}
return 0;
return 0;
}

4
driver/i2c.h
View File

@@ -21,8 +21,8 @@
#include <stdint.h>
enum {
I2C_WRITE = 0U,
I2C_READ = 1U,
I2C_WRITE = 0U,
I2C_READ = 1U,
};
void I2C_Start(void);

200
driver/keyboard.c
View File

@@ -29,125 +29,125 @@ bool gWasFKeyPressed = false;
static const struct {
// Using a 16 bit pre-calculated shift and invert is cheaper
// than using 8 bit and doing shift and invert in code.
uint16_t set_to_zero_mask;
// Using a 16 bit pre-calculated shift and invert is cheaper
// than using 8 bit and doing shift and invert in code.
uint16_t set_to_zero_mask;
// We are very fortunate.
// The key and pin defines fit together in a single u8, making this very efficient
struct {
KEY_Code_t key : 5;
uint8_t pin : 3; // Pin 6 is highest
} pins[4];
// We are very fortunate.
// The key and pin defines fit together in a single u8, making this very efficient
struct {
KEY_Code_t key : 5;
uint8_t pin : 3; // Pin 6 is highest
} pins[4];
} keyboard[] = {
{ // Zero row
// Set to zero to handle special case of nothing pulled down
.set_to_zero_mask = 0xffff,
.pins = {
{ .key = KEY_SIDE1, .pin = GPIOA_PIN_KEYBOARD_0},
{ .key = KEY_SIDE2, .pin = GPIOA_PIN_KEYBOARD_1},
{ // Zero row
// Set to zero to handle special case of nothing pulled down
.set_to_zero_mask = 0xffff,
.pins = {
{ .key = KEY_SIDE1, .pin = GPIOA_PIN_KEYBOARD_0},
{ .key = KEY_SIDE2, .pin = GPIOA_PIN_KEYBOARD_1},
// Duplicate to fill the array with valid values
{ .key = KEY_INVALID, .pin = GPIOA_PIN_KEYBOARD_1},
{ .key = KEY_INVALID, .pin = GPIOA_PIN_KEYBOARD_1}
}
},
{ // First row
.set_to_zero_mask = ~(1u << GPIOA_PIN_KEYBOARD_4) & 0xffff,
.pins = {
{ .key = KEY_MENU, .pin = GPIOA_PIN_KEYBOARD_0},
{ .key = KEY_1, .pin = GPIOA_PIN_KEYBOARD_1},
{ .key = KEY_4, .pin = GPIOA_PIN_KEYBOARD_2},
{ .key = KEY_7, .pin = GPIOA_PIN_KEYBOARD_3}
}
},
{ // Second row
.set_to_zero_mask = ~(1u << GPIOA_PIN_KEYBOARD_5) & 0xffff,
.pins = {
{ .key = KEY_UP, .pin = GPIOA_PIN_KEYBOARD_0},
{ .key = KEY_2 , .pin = GPIOA_PIN_KEYBOARD_1},
{ .key = KEY_5 , .pin = GPIOA_PIN_KEYBOARD_2},
{ .key = KEY_8 , .pin = GPIOA_PIN_KEYBOARD_3}
}
},
{ // Third row
.set_to_zero_mask = ~(1u << GPIOA_PIN_KEYBOARD_6) & 0xffff,
.pins = {
{ .key = KEY_DOWN, .pin = GPIOA_PIN_KEYBOARD_0},
{ .key = KEY_3 , .pin = GPIOA_PIN_KEYBOARD_1},
{ .key = KEY_6 , .pin = GPIOA_PIN_KEYBOARD_2},
{ .key = KEY_9 , .pin = GPIOA_PIN_KEYBOARD_3}
}
},
{ // Fourth row
.set_to_zero_mask = ~(1u << GPIOA_PIN_KEYBOARD_7) & 0xffff,
.pins = {
{ .key = KEY_EXIT, .pin = GPIOA_PIN_KEYBOARD_0},
{ .key = KEY_STAR, .pin = GPIOA_PIN_KEYBOARD_1},
{ .key = KEY_0 , .pin = GPIOA_PIN_KEYBOARD_2},
{ .key = KEY_F , .pin = GPIOA_PIN_KEYBOARD_3}
}
}
// Duplicate to fill the array with valid values
{ .key = KEY_INVALID, .pin = GPIOA_PIN_KEYBOARD_1},
{ .key = KEY_INVALID, .pin = GPIOA_PIN_KEYBOARD_1}
}
},
{ // First row
.set_to_zero_mask = ~(1u << GPIOA_PIN_KEYBOARD_4) & 0xffff,
.pins = {
{ .key = KEY_MENU, .pin = GPIOA_PIN_KEYBOARD_0},
{ .key = KEY_1, .pin = GPIOA_PIN_KEYBOARD_1},
{ .key = KEY_4, .pin = GPIOA_PIN_KEYBOARD_2},
{ .key = KEY_7, .pin = GPIOA_PIN_KEYBOARD_3}
}
},
{ // Second row
.set_to_zero_mask = ~(1u << GPIOA_PIN_KEYBOARD_5) & 0xffff,
.pins = {
{ .key = KEY_UP, .pin = GPIOA_PIN_KEYBOARD_0},
{ .key = KEY_2 , .pin = GPIOA_PIN_KEYBOARD_1},
{ .key = KEY_5 , .pin = GPIOA_PIN_KEYBOARD_2},
{ .key = KEY_8 , .pin = GPIOA_PIN_KEYBOARD_3}
}
},
{ // Third row
.set_to_zero_mask = ~(1u << GPIOA_PIN_KEYBOARD_6) & 0xffff,
.pins = {
{ .key = KEY_DOWN, .pin = GPIOA_PIN_KEYBOARD_0},
{ .key = KEY_3 , .pin = GPIOA_PIN_KEYBOARD_1},
{ .key = KEY_6 , .pin = GPIOA_PIN_KEYBOARD_2},
{ .key = KEY_9 , .pin = GPIOA_PIN_KEYBOARD_3}
}
},
{ // Fourth row
.set_to_zero_mask = ~(1u << GPIOA_PIN_KEYBOARD_7) & 0xffff,
.pins = {
{ .key = KEY_EXIT, .pin = GPIOA_PIN_KEYBOARD_0},
{ .key = KEY_STAR, .pin = GPIOA_PIN_KEYBOARD_1},
{ .key = KEY_0 , .pin = GPIOA_PIN_KEYBOARD_2},
{ .key = KEY_F , .pin = GPIOA_PIN_KEYBOARD_3}
}
}
};
KEY_Code_t KEYBOARD_Poll(void)
{
KEY_Code_t Key = KEY_INVALID;
KEY_Code_t Key = KEY_INVALID;
// if (!GPIO_CheckBit(&GPIOC->DATA, GPIOC_PIN_PTT))
// return KEY_PTT;
// if (!GPIO_CheckBit(&GPIOC->DATA, GPIOC_PIN_PTT))
// return KEY_PTT;
// *****************
// *****************
for (unsigned int j = 0; j < ARRAY_SIZE(keyboard); j++)
{
uint16_t reg;
unsigned int i;
unsigned int k;
for (unsigned int j = 0; j < ARRAY_SIZE(keyboard); j++)
{
uint16_t reg;
unsigned int i;
unsigned int k;
// Set all high
GPIOA->DATA |= 1u << GPIOA_PIN_KEYBOARD_4 |
1u << GPIOA_PIN_KEYBOARD_5 |
1u << GPIOA_PIN_KEYBOARD_6 |
1u << GPIOA_PIN_KEYBOARD_7;
// Set all high
GPIOA->DATA |= 1u << GPIOA_PIN_KEYBOARD_4 |
1u << GPIOA_PIN_KEYBOARD_5 |
1u << GPIOA_PIN_KEYBOARD_6 |
1u << GPIOA_PIN_KEYBOARD_7;
// Clear the pin we are selecting
GPIOA->DATA &= keyboard[j].set_to_zero_mask;
// Clear the pin we are selecting
GPIOA->DATA &= keyboard[j].set_to_zero_mask;
// Read all 4 GPIO pins at once .. with de-noise, max of 8 sample loops
for (i = 0, k = 0, reg = 0; i < 3 && k < 8; i++, k++) {
SYSTICK_DelayUs(1);
uint16_t reg2 = GPIOA->DATA;
i *= reg == reg2;
reg = reg2;
}
// Read all 4 GPIO pins at once .. with de-noise, max of 8 sample loops
for (i = 0, k = 0, reg = 0; i < 3 && k < 8; i++, k++) {
SYSTICK_DelayUs(1);
uint16_t reg2 = GPIOA->DATA;
i *= reg == reg2;
reg = reg2;
}
if (i < 3)
break; // noise is too bad
if (i < 3)
break; // noise is too bad
for (unsigned int i = 0; i < ARRAY_SIZE(keyboard[j].pins); i++)
{
const uint16_t mask = 1u << keyboard[j].pins[i].pin;
if (!(reg & mask))
{
Key = keyboard[j].pins[i].key;
break;
}
}
for (unsigned int i = 0; i < ARRAY_SIZE(keyboard[j].pins); i++)
{
const uint16_t mask = 1u << keyboard[j].pins[i].pin;
if (!(reg & mask))
{
Key = keyboard[j].pins[i].key;
break;
}
}
if (Key != KEY_INVALID)
break;
}
if (Key != KEY_INVALID)
break;
}
// Create I2C stop condition since we might have toggled I2C pins
// This leaves GPIOA_PIN_KEYBOARD_4 and GPIOA_PIN_KEYBOARD_5 high
I2C_Stop();
// Create I2C stop condition since we might have toggled I2C pins
// This leaves GPIOA_PIN_KEYBOARD_4 and GPIOA_PIN_KEYBOARD_5 high
I2C_Stop();
// Reset VOICE pins
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_KEYBOARD_6);
GPIO_SetBit( &GPIOA->DATA, GPIOA_PIN_KEYBOARD_7);
// Reset VOICE pins
GPIO_ClearBit(&GPIOA->DATA, GPIOA_PIN_KEYBOARD_6);
GPIO_SetBit( &GPIOA->DATA, GPIOA_PIN_KEYBOARD_7);
return Key;
return Key;
}

40
driver/keyboard.h
View File

@@ -22,26 +22,26 @@
#include <stdint.h>
enum KEY_Code_e {
KEY_0 = 0, // 0
KEY_1, // 1
KEY_2, // 2
KEY_3, // 3
KEY_4, // 4
KEY_5, // 5
KEY_6, // 6
KEY_7, // 7
KEY_8, // 8
KEY_9, // 9
KEY_MENU, // A
KEY_UP, // B
KEY_DOWN, // C
KEY_EXIT, // D
KEY_STAR, // *
KEY_F, // #
KEY_PTT, //
KEY_SIDE2, //
KEY_SIDE1, //
KEY_INVALID //
KEY_0 = 0, // 0
KEY_1, // 1
KEY_2, // 2
KEY_3, // 3
KEY_4, // 4
KEY_5, // 5
KEY_6, // 6
KEY_7, // 7
KEY_8, // 8
KEY_9, // 9
KEY_MENU, // A
KEY_UP, // B
KEY_DOWN, // C
KEY_EXIT, // D
KEY_STAR, // *
KEY_F, // #
KEY_PTT, //
KEY_SIDE2, //
KEY_SIDE1, //
KEY_INVALID //
};
typedef enum KEY_Code_e KEY_Code_t;

124
driver/spi.c
View File

@@ -22,95 +22,95 @@
void SPI0_Init(void)
{
SPI_Config_t Config;
SPI_Config_t Config;
SPI_Disable(&SPI0->CR);
SPI_Disable(&SPI0->CR);
Config.TXFIFO_EMPTY = 0;
Config.RXFIFO_HFULL = 0;
Config.RXFIFO_FULL = 0;
Config.RXFIFO_OVF = 0;
Config.MSTR = 1;
Config.SPR = 2;
Config.CPHA = 1;
Config.CPOL = 1;
Config.LSB = 0;
Config.TF_CLR = 0;
Config.RF_CLR = 0;
Config.TXFIFO_HFULL = 0;
SPI_Configure(SPI0, &Config);
Config.TXFIFO_EMPTY = 0;
Config.RXFIFO_HFULL = 0;
Config.RXFIFO_FULL = 0;
Config.RXFIFO_OVF = 0;
Config.MSTR = 1;
Config.SPR = 2;
Config.CPHA = 1;
Config.CPOL = 1;
Config.LSB = 0;
Config.TF_CLR = 0;
Config.RF_CLR = 0;
Config.TXFIFO_HFULL = 0;
SPI_Configure(SPI0, &Config);
SPI_Enable(&SPI0->CR);
SPI_Enable(&SPI0->CR);
}
void SPI_WaitForUndocumentedTxFifoStatusBit(void)
{
uint32_t Timeout;
uint32_t Timeout;
Timeout = 0;
do {
// Undocumented bit!
if ((SPI0->IF & 0x20) == 0) {
break;
}
Timeout++;
} while (Timeout <= 100000);
Timeout = 0;
do {
// Undocumented bit!
if ((SPI0->IF & 0x20) == 0) {
break;
}
Timeout++;
} while (Timeout <= 100000);
}
void SPI_Disable(volatile uint32_t *pCR)
{
*pCR = (*pCR & ~SPI_CR_SPE_MASK) | SPI_CR_SPE_BITS_DISABLE;
*pCR = (*pCR & ~SPI_CR_SPE_MASK) | SPI_CR_SPE_BITS_DISABLE;
}
void SPI_Configure(volatile SPI_Port_t *pPort, SPI_Config_t *pConfig)
{
if (pPort == SPI0) {
SYSCON_DEV_CLK_GATE = (SYSCON_DEV_CLK_GATE & ~SYSCON_DEV_CLK_GATE_SPI0_MASK) | SYSCON_DEV_CLK_GATE_SPI0_BITS_ENABLE;
} else if (pPort == SPI1) {
SYSCON_DEV_CLK_GATE = (SYSCON_DEV_CLK_GATE & ~SYSCON_DEV_CLK_GATE_SPI1_MASK) | SYSCON_DEV_CLK_GATE_SPI1_BITS_ENABLE;
}
if (pPort == SPI0) {
SYSCON_DEV_CLK_GATE = (SYSCON_DEV_CLK_GATE & ~SYSCON_DEV_CLK_GATE_SPI0_MASK) | SYSCON_DEV_CLK_GATE_SPI0_BITS_ENABLE;
} else if (pPort == SPI1) {
SYSCON_DEV_CLK_GATE = (SYSCON_DEV_CLK_GATE & ~SYSCON_DEV_CLK_GATE_SPI1_MASK) | SYSCON_DEV_CLK_GATE_SPI1_BITS_ENABLE;
}
SPI_Disable(&pPort->CR);
SPI_Disable(&pPort->CR);
pPort->CR = 0
| (pPort->CR & ~(SPI_CR_SPR_MASK | SPI_CR_CPHA_MASK | SPI_CR_CPOL_MASK | SPI_CR_MSTR_MASK | SPI_CR_LSB_MASK | SPI_CR_RF_CLR_MASK))
| ((pConfig->SPR << SPI_CR_SPR_SHIFT) & SPI_CR_SPR_MASK)
| ((pConfig->CPHA << SPI_CR_CPHA_SHIFT) & SPI_CR_CPHA_MASK)
| ((pConfig->CPOL << SPI_CR_CPOL_SHIFT) & SPI_CR_CPOL_MASK)
| ((pConfig->MSTR << SPI_CR_MSTR_SHIFT) & SPI_CR_MSTR_MASK)
| ((pConfig->LSB << SPI_CR_LSB_SHIFT) & SPI_CR_LSB_MASK)
| ((pConfig->RF_CLR << SPI_CR_RF_CLR_SHIFT) & SPI_CR_RF_CLR_MASK)
| ((pConfig->TF_CLR << SPI_CR_TF_CLR_SHIFT) & SPI_CR_TF_CLR_MASK)
;
pPort->CR = 0
| (pPort->CR & ~(SPI_CR_SPR_MASK | SPI_CR_CPHA_MASK | SPI_CR_CPOL_MASK | SPI_CR_MSTR_MASK | SPI_CR_LSB_MASK | SPI_CR_RF_CLR_MASK))
| ((pConfig->SPR << SPI_CR_SPR_SHIFT) & SPI_CR_SPR_MASK)
| ((pConfig->CPHA << SPI_CR_CPHA_SHIFT) & SPI_CR_CPHA_MASK)
| ((pConfig->CPOL << SPI_CR_CPOL_SHIFT) & SPI_CR_CPOL_MASK)
| ((pConfig->MSTR << SPI_CR_MSTR_SHIFT) & SPI_CR_MSTR_MASK)
| ((pConfig->LSB << SPI_CR_LSB_SHIFT) & SPI_CR_LSB_MASK)
| ((pConfig->RF_CLR << SPI_CR_RF_CLR_SHIFT) & SPI_CR_RF_CLR_MASK)
| ((pConfig->TF_CLR << SPI_CR_TF_CLR_SHIFT) & SPI_CR_TF_CLR_MASK)
;
pPort->IE = 0
| ((pConfig->RXFIFO_OVF << SPI_IE_RXFIFO_OVF_SHIFT) & SPI_IE_RXFIFO_OVF_MASK)
| ((pConfig->RXFIFO_FULL << SPI_IE_RXFIFO_FULL_SHIFT) & SPI_IE_RXFIFO_FULL_MASK)
| ((pConfig->RXFIFO_HFULL << SPI_IE_RXFIFO_HFULL_SHIFT) & SPI_IE_RXFIFO_HFULL_MASK)
| ((pConfig->TXFIFO_EMPTY << SPI_IE_TXFIFO_EMPTY_SHIFT) & SPI_IE_TXFIFO_EMPTY_MASK)
| ((pConfig->TXFIFO_HFULL << SPI_IE_TXFIFO_HFULL_SHIFT) & SPI_IE_TXFIFO_HFULL_MASK)
;
pPort->IE = 0
| ((pConfig->RXFIFO_OVF << SPI_IE_RXFIFO_OVF_SHIFT) & SPI_IE_RXFIFO_OVF_MASK)
| ((pConfig->RXFIFO_FULL << SPI_IE_RXFIFO_FULL_SHIFT) & SPI_IE_RXFIFO_FULL_MASK)
| ((pConfig->RXFIFO_HFULL << SPI_IE_RXFIFO_HFULL_SHIFT) & SPI_IE_RXFIFO_HFULL_MASK)
| ((pConfig->TXFIFO_EMPTY << SPI_IE_TXFIFO_EMPTY_SHIFT) & SPI_IE_TXFIFO_EMPTY_MASK)
| ((pConfig->TXFIFO_HFULL << SPI_IE_TXFIFO_HFULL_SHIFT) & SPI_IE_TXFIFO_HFULL_MASK)
;
if (pPort->IE) {
if (pPort == SPI0) {
NVIC_EnableIRQ((IRQn_Type)DP32_SPI0_IRQn);
} else if (pPort == SPI1) {
NVIC_EnableIRQ((IRQn_Type)DP32_SPI1_IRQn);
}
}
if (pPort->IE) {
if (pPort == SPI0) {
NVIC_EnableIRQ((IRQn_Type)DP32_SPI0_IRQn);
} else if (pPort == SPI1) {
NVIC_EnableIRQ((IRQn_Type)DP32_SPI1_IRQn);
}
}
}
void SPI_ToggleMasterMode(volatile uint32_t *pCR, bool bIsMaster)
{
if (bIsMaster) {
*pCR = (*pCR & ~SPI_CR_MSR_SSN_MASK) | SPI_CR_MSR_SSN_BITS_ENABLE;
} else {
*pCR = (*pCR & ~SPI_CR_MSR_SSN_MASK) | SPI_CR_MSR_SSN_BITS_DISABLE;
}
if (bIsMaster) {
*pCR = (*pCR & ~SPI_CR_MSR_SSN_MASK) | SPI_CR_MSR_SSN_BITS_ENABLE;
} else {
*pCR = (*pCR & ~SPI_CR_MSR_SSN_MASK) | SPI_CR_MSR_SSN_BITS_DISABLE;
}
}
void SPI_Enable(volatile uint32_t *pCR)
{
*pCR = (*pCR & ~SPI_CR_SPE_MASK) | SPI_CR_SPE_BITS_ENABLE;
*pCR = (*pCR & ~SPI_CR_SPE_MASK) | SPI_CR_SPE_BITS_ENABLE;
}

24
driver/spi.h
View File

@@ -21,18 +21,18 @@
#include <stdint.h>
typedef struct {
uint8_t MSTR;
uint8_t SPR;
uint8_t CPHA;
uint8_t CPOL;
uint8_t LSB;
uint8_t TF_CLR;
uint8_t RF_CLR;
uint8_t TXFIFO_HFULL;
uint8_t TXFIFO_EMPTY;
uint8_t RXFIFO_HFULL;
uint8_t RXFIFO_FULL;
uint8_t RXFIFO_OVF;
uint8_t MSTR;
uint8_t SPR;
uint8_t CPHA;
uint8_t CPOL;
uint8_t LSB;
uint8_t TF_CLR;
uint8_t RF_CLR;
uint8_t TXFIFO_HFULL;
uint8_t TXFIFO_EMPTY;
uint8_t RXFIFO_HFULL;
uint8_t RXFIFO_FULL;
uint8_t RXFIFO_OVF;
} SPI_Config_t;
void SPI0_Init(void);

314
driver/st7565.c
View File

@@ -29,104 +29,104 @@ uint8_t gStatusLine[LCD_WIDTH];
uint8_t gFrameBuffer[FRAME_LINES][LCD_WIDTH];
static void DrawLine(uint8_t column, uint8_t line, const uint8_t * lineBuffer, unsigned size_defVal)
{
ST7565_SelectColumnAndLine(column + 4, line);
GPIO_SetBit(&GPIOB->DATA, GPIOB_PIN_ST7565_A0);
for (unsigned i = 0; i < size_defVal; i++) {
while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) {}
SPI0->WDR = lineBuffer ? lineBuffer[i] : size_defVal;
}
SPI_WaitForUndocumentedTxFifoStatusBit();
{
ST7565_SelectColumnAndLine(column + 4, line);
GPIO_SetBit(&GPIOB->DATA, GPIOB_PIN_ST7565_A0);
for (unsigned i = 0; i < size_defVal; i++) {
while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) {}
SPI0->WDR = lineBuffer ? lineBuffer[i] : size_defVal;
}
SPI_WaitForUndocumentedTxFifoStatusBit();
}
void ST7565_DrawLine(const unsigned int Column, const unsigned int Line, const uint8_t *pBitmap, const unsigned int Size)
{
SPI_ToggleMasterMode(&SPI0->CR, false);
DrawLine(Column, Line, pBitmap, Size);
SPI_ToggleMasterMode(&SPI0->CR, true);
SPI_ToggleMasterMode(&SPI0->CR, false);
DrawLine(Column, Line, pBitmap, Size);
SPI_ToggleMasterMode(&SPI0->CR, true);
}
#ifdef ENABLE_FEAT_F4HWN
// Optimization
//
// ST7565_BlitScreen(0) = ST7565_BlitStatusLine()
// ST7565_BlitScreen(1..7) = ST7565_BlitLine()
// ST7565_BlitScreen(8) = ST7565_BlitFullScreen()
//
// Optimization
//
// ST7565_BlitScreen(0) = ST7565_BlitStatusLine()
// ST7565_BlitScreen(1..7) = ST7565_BlitLine()
// ST7565_BlitScreen(8) = ST7565_BlitFullScreen()
//
static void ST7565_BlitScreen(uint8_t line)
{
SPI_ToggleMasterMode(&SPI0->CR, false);
ST7565_WriteByte(0x40);
static void ST7565_BlitScreen(uint8_t line)
{
SPI_ToggleMasterMode(&SPI0->CR, false);
ST7565_WriteByte(0x40);
if(line == 0)
{
DrawLine(0, 0, gStatusLine, LCD_WIDTH);
}
else if(line <= FRAME_LINES)
{
DrawLine(0, line, gFrameBuffer[line - 1], LCD_WIDTH);
}
else
{
for (line = 1; line <= FRAME_LINES; line++) {
DrawLine(0, line, gFrameBuffer[line - 1], LCD_WIDTH);
}
}
if(line == 0)
{
DrawLine(0, 0, gStatusLine, LCD_WIDTH);
}
else if(line <= FRAME_LINES)
{
DrawLine(0, line, gFrameBuffer[line - 1], LCD_WIDTH);
}
else
{
for (line = 1; line <= FRAME_LINES; line++) {
DrawLine(0, line, gFrameBuffer[line - 1], LCD_WIDTH);
}
}
SPI_ToggleMasterMode(&SPI0->CR, true);
}
SPI_ToggleMasterMode(&SPI0->CR, true);
}
void ST7565_BlitFullScreen(void)
{
ST7565_BlitScreen(8);
}
void ST7565_BlitFullScreen(void)
{
ST7565_BlitScreen(8);
}
void ST7565_BlitLine(unsigned line)
{
ST7565_BlitScreen(line + 1);
}
void ST7565_BlitLine(unsigned line)
{
ST7565_BlitScreen(line + 1);
}
void ST7565_BlitStatusLine(void)
{
ST7565_BlitScreen(0);
}
void ST7565_BlitStatusLine(void)
{
ST7565_BlitScreen(0);
}
#else
void ST7565_BlitFullScreen(void)
{
SPI_ToggleMasterMode(&SPI0->CR, false);
ST7565_WriteByte(0x40);
for (unsigned line = 0; line < FRAME_LINES; line++) {
DrawLine(0, line+1, gFrameBuffer[line], LCD_WIDTH);
}
SPI_ToggleMasterMode(&SPI0->CR, true);
}
void ST7565_BlitFullScreen(void)
{
SPI_ToggleMasterMode(&SPI0->CR, false);
ST7565_WriteByte(0x40);
for (unsigned line = 0; line < FRAME_LINES; line++) {
DrawLine(0, line+1, gFrameBuffer[line], LCD_WIDTH);
}
SPI_ToggleMasterMode(&SPI0->CR, true);
}
void ST7565_BlitLine(unsigned line)
{
SPI_ToggleMasterMode(&SPI0->CR, false);
ST7565_WriteByte(0x40); // start line ?
DrawLine(0, line+1, gFrameBuffer[line], LCD_WIDTH);
SPI_ToggleMasterMode(&SPI0->CR, true);
}
void ST7565_BlitLine(unsigned line)
{
SPI_ToggleMasterMode(&SPI0->CR, false);
ST7565_WriteByte(0x40); // start line ?
DrawLine(0, line+1, gFrameBuffer[line], LCD_WIDTH);
SPI_ToggleMasterMode(&SPI0->CR, true);
}
void ST7565_BlitStatusLine(void)
{ // the top small text line on the display
SPI_ToggleMasterMode(&SPI0->CR, false);
ST7565_WriteByte(0x40); // start line ?
DrawLine(0, 0, gStatusLine, LCD_WIDTH);
SPI_ToggleMasterMode(&SPI0->CR, true);
}
void ST7565_BlitStatusLine(void)
{ // the top small text line on the display
SPI_ToggleMasterMode(&SPI0->CR, false);
ST7565_WriteByte(0x40); // start line ?
DrawLine(0, 0, gStatusLine, LCD_WIDTH);
SPI_ToggleMasterMode(&SPI0->CR, true);
}
#endif
void ST7565_FillScreen(uint8_t value)
{
SPI_ToggleMasterMode(&SPI0->CR, false);
for (unsigned i = 0; i < 8; i++) {
DrawLine(0, i, NULL, value);
}
SPI_ToggleMasterMode(&SPI0->CR, true);
SPI_ToggleMasterMode(&SPI0->CR, false);
for (unsigned i = 0; i < 8; i++) {
DrawLine(0, i, NULL, value);
}
SPI_ToggleMasterMode(&SPI0->CR, true);
}
// Software reset
@@ -179,121 +179,121 @@ const uint8_t ST7565_CMD_SET_START_LINE = 0x40;
const uint8_t ST7565_CMD_DISPLAY_ON_OFF = 0xAE;
uint8_t cmds[] = {
ST7565_CMD_BIAS_SELECT | 0, // Select bias setting: 1/9
ST7565_CMD_COM_DIRECTION | (0 << 3), // Set output direction of COM: normal
ST7565_CMD_SEG_DIRECTION | 1, // Set scan direction of SEG: reverse
ST7565_CMD_INVERSE_DISPLAY | 0, // Inverse Display: false
ST7565_CMD_ALL_PIXEL_ON | 0, // All Pixel ON: false - normal display
ST7565_CMD_REGULATION_RATIO | (4 << 0), // Regulation Ratio 5.0
ST7565_CMD_BIAS_SELECT | 0, // Select bias setting: 1/9
ST7565_CMD_COM_DIRECTION | (0 << 3), // Set output direction of COM: normal
ST7565_CMD_SEG_DIRECTION | 1, // Set scan direction of SEG: reverse
ST7565_CMD_INVERSE_DISPLAY | 0, // Inverse Display: false
ST7565_CMD_ALL_PIXEL_ON | 0, // All Pixel ON: false - normal display
ST7565_CMD_REGULATION_RATIO | (4 << 0), // Regulation Ratio 5.0
ST7565_CMD_SET_EV, // Set contrast
31,
ST7565_CMD_SET_EV, // Set contrast
31,
ST7565_CMD_POWER_CIRCUIT | 0b111, // Built-in power circuit ON/OFF: VB=1 VR=1 VF=1
ST7565_CMD_SET_START_LINE | 0, // Set Start Line: 0
ST7565_CMD_DISPLAY_ON_OFF | 1, // Display ON/OFF: ON
ST7565_CMD_POWER_CIRCUIT | 0b111, // Built-in power circuit ON/OFF: VB=1 VR=1 VF=1
ST7565_CMD_SET_START_LINE | 0, // Set Start Line: 0
ST7565_CMD_DISPLAY_ON_OFF | 1, // Display ON/OFF: ON
};
#ifdef ENABLE_FEAT_F4HWN
static void ST7565_Cmd(uint8_t i)
{
switch(i) {
case 3:
ST7565_WriteByte(ST7565_CMD_INVERSE_DISPLAY | gSetting_set_inv);
break;
case 7:
ST7565_WriteByte(21 + gSetting_set_ctr);
break;
default:
ST7565_WriteByte(cmds[i]);
}
}
static void ST7565_Cmd(uint8_t i)
{
switch(i) {
case 3:
ST7565_WriteByte(ST7565_CMD_INVERSE_DISPLAY | gSetting_set_inv);
break;
case 7:
ST7565_WriteByte(21 + gSetting_set_ctr);
break;
default:
ST7565_WriteByte(cmds[i]);
}
}
void ST7565_ContrastAndInv(void)
{
SPI_ToggleMasterMode(&SPI0->CR, false);
ST7565_WriteByte(ST7565_CMD_SOFTWARE_RESET); // software reset
void ST7565_ContrastAndInv(void)
{
SPI_ToggleMasterMode(&SPI0->CR, false);
ST7565_WriteByte(ST7565_CMD_SOFTWARE_RESET); // software reset
for(uint8_t i = 0; i < 8; i++)
{
ST7565_Cmd(i);
}
}
for(uint8_t i = 0; i < 8; i++)
{
ST7565_Cmd(i);
}
}
#endif
void ST7565_Init(void)
{
SPI0_Init();
ST7565_HardwareReset();
SPI_ToggleMasterMode(&SPI0->CR, false);
ST7565_WriteByte(ST7565_CMD_SOFTWARE_RESET); // software reset
SYSTEM_DelayMs(120);
SPI0_Init();
ST7565_HardwareReset();
SPI_ToggleMasterMode(&SPI0->CR, false);
ST7565_WriteByte(ST7565_CMD_SOFTWARE_RESET); // software reset
SYSTEM_DelayMs(120);
for(uint8_t i = 0; i < 8; i++)
{
for(uint8_t i = 0; i < 8; i++)
{
#ifdef ENABLE_FEAT_F4HWN
ST7565_Cmd(i);
ST7565_Cmd(i);
#else
ST7565_WriteByte(cmds[i]);
ST7565_WriteByte(cmds[i]);
#endif
}
}
ST7565_WriteByte(ST7565_CMD_POWER_CIRCUIT | 0b011); // VB=0 VR=1 VF=1
SYSTEM_DelayMs(1);
ST7565_WriteByte(ST7565_CMD_POWER_CIRCUIT | 0b110); // VB=1 VR=1 VF=0
SYSTEM_DelayMs(1);
ST7565_WriteByte(ST7565_CMD_POWER_CIRCUIT | 0b011); // VB=0 VR=1 VF=1
SYSTEM_DelayMs(1);
ST7565_WriteByte(ST7565_CMD_POWER_CIRCUIT | 0b110); // VB=1 VR=1 VF=0
SYSTEM_DelayMs(1);
for(uint8_t i = 0; i < 4; i++) // why 4 times?
ST7565_WriteByte(ST7565_CMD_POWER_CIRCUIT | 0b111); // VB=1 VR=1 VF=1
for(uint8_t i = 0; i < 4; i++) // why 4 times?
ST7565_WriteByte(ST7565_CMD_POWER_CIRCUIT | 0b111); // VB=1 VR=1 VF=1
SYSTEM_DelayMs(40);
ST7565_WriteByte(ST7565_CMD_SET_START_LINE | 0); // line 0
ST7565_WriteByte(ST7565_CMD_DISPLAY_ON_OFF | 1); // D=1
SPI_WaitForUndocumentedTxFifoStatusBit();
SPI_ToggleMasterMode(&SPI0->CR, true);
SYSTEM_DelayMs(40);
ST7565_WriteByte(ST7565_CMD_SET_START_LINE | 0); // line 0
ST7565_WriteByte(ST7565_CMD_DISPLAY_ON_OFF | 1); // D=1
SPI_WaitForUndocumentedTxFifoStatusBit();
SPI_ToggleMasterMode(&SPI0->CR, true);
ST7565_FillScreen(0x00);
ST7565_FillScreen(0x00);
}
void ST7565_FixInterfGlitch(void)
{
SPI_ToggleMasterMode(&SPI0->CR, false);
for(uint8_t i = 0; i < ARRAY_SIZE(cmds); i++)
SPI_ToggleMasterMode(&SPI0->CR, false);
for(uint8_t i = 0; i < ARRAY_SIZE(cmds); i++)
#ifdef ENABLE_FEAT_F4HWN
ST7565_Cmd(i);
ST7565_Cmd(i);
#else
ST7565_WriteByte(cmds[i]);
ST7565_WriteByte(cmds[i]);
#endif
SPI_WaitForUndocumentedTxFifoStatusBit();
SPI_ToggleMasterMode(&SPI0->CR, true);
SPI_WaitForUndocumentedTxFifoStatusBit();
SPI_ToggleMasterMode(&SPI0->CR, true);
}
void ST7565_HardwareReset(void)
{
GPIO_SetBit(&GPIOB->DATA, GPIOB_PIN_ST7565_RES);
SYSTEM_DelayMs(1);
GPIO_ClearBit(&GPIOB->DATA, GPIOB_PIN_ST7565_RES);
SYSTEM_DelayMs(20);
GPIO_SetBit(&GPIOB->DATA, GPIOB_PIN_ST7565_RES);
SYSTEM_DelayMs(120);
GPIO_SetBit(&GPIOB->DATA, GPIOB_PIN_ST7565_RES);
SYSTEM_DelayMs(1);
GPIO_ClearBit(&GPIOB->DATA, GPIOB_PIN_ST7565_RES);
SYSTEM_DelayMs(20);
GPIO_SetBit(&GPIOB->DATA, GPIOB_PIN_ST7565_RES);
SYSTEM_DelayMs(120);
}
void ST7565_SelectColumnAndLine(uint8_t Column, uint8_t Line)
{
GPIO_ClearBit(&GPIOB->DATA, GPIOB_PIN_ST7565_A0);
while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) {}
SPI0->WDR = Line + 176;
while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) {}
SPI0->WDR = ((Column >> 4) & 0x0F) | 0x10;
while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) {}
SPI0->WDR = ((Column >> 0) & 0x0F);
SPI_WaitForUndocumentedTxFifoStatusBit();
GPIO_ClearBit(&GPIOB->DATA, GPIOB_PIN_ST7565_A0);
while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) {}
SPI0->WDR = Line + 176;
while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) {}
SPI0->WDR = ((Column >> 4) & 0x0F) | 0x10;
while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) {}
SPI0->WDR = ((Column >> 0) & 0x0F);
SPI_WaitForUndocumentedTxFifoStatusBit();
}
void ST7565_WriteByte(uint8_t Value)
{
GPIO_ClearBit(&GPIOB->DATA, GPIOB_PIN_ST7565_A0);
while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) {}
SPI0->WDR = Value;
GPIO_ClearBit(&GPIOB->DATA, GPIOB_PIN_ST7565_A0);
while ((SPI0->FIFOST & SPI_FIFOST_TFF_MASK) != SPI_FIFOST_TFF_BITS_NOT_FULL) {}
SPI0->WDR = Value;
}

2
driver/st7565.h
View File

@@ -39,7 +39,7 @@ void ST7565_SelectColumnAndLine(uint8_t Column, uint8_t Line);
void ST7565_WriteByte(uint8_t Value);
#ifdef ENABLE_FEAT_F4HWN
void ST7565_ContrastAndInv(void);
void ST7565_ContrastAndInv(void);
#endif
#endif

14
driver/system.c
View File

@@ -21,17 +21,17 @@
void SYSTEM_DelayMs(uint32_t Delay)
{
SYSTICK_DelayUs(Delay * 1000);
SYSTICK_DelayUs(Delay * 1000);
}
void SYSTEM_ConfigureClocks(void)
{
// Set source clock from external crystal
PMU_SRC_CFG = (PMU_SRC_CFG & ~(PMU_SRC_CFG_RCHF_SEL_MASK | PMU_SRC_CFG_RCHF_EN_MASK)) | PMU_SRC_CFG_RCHF_SEL_BITS_48MHZ | PMU_SRC_CFG_RCHF_EN_BITS_ENABLE;
// Set source clock from external crystal
PMU_SRC_CFG = (PMU_SRC_CFG & ~(PMU_SRC_CFG_RCHF_SEL_MASK | PMU_SRC_CFG_RCHF_EN_MASK)) | PMU_SRC_CFG_RCHF_SEL_BITS_48MHZ | PMU_SRC_CFG_RCHF_EN_BITS_ENABLE;
// Divide by 2
SYSCON_CLK_SEL = SYSCON_CLK_SEL_DIV_BITS_2;
// Divide by 2
SYSCON_CLK_SEL = SYSCON_CLK_SEL_DIV_BITS_2;
// Disable division clock gate
SYSCON_DIV_CLK_GATE = (SYSCON_DIV_CLK_GATE & ~SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_MASK) | SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_BITS_DISABLE;
// Disable division clock gate
SYSCON_DIV_CLK_GATE = (SYSCON_DIV_CLK_GATE & ~SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_MASK) | SYSCON_DIV_CLK_GATE_DIV_CLK_GATE_BITS_DISABLE;
}

30
driver/systick.c
View File

@@ -23,27 +23,27 @@ static uint32_t gTickMultiplier;
void SYSTICK_Init(void)
{
SysTick_Config(480000);
gTickMultiplier = 48;
SysTick_Config(480000);
gTickMultiplier = 48;
}
void SYSTICK_DelayUs(uint32_t Delay)
{
const uint32_t ticks = Delay * gTickMultiplier;
uint32_t elapsed_ticks = 0;
uint32_t Start = SysTick->LOAD;
uint32_t Previous = SysTick->VAL;
do {
uint32_t Current;
const uint32_t ticks = Delay * gTickMultiplier;
uint32_t elapsed_ticks = 0;
uint32_t Start = SysTick->LOAD;
uint32_t Previous = SysTick->VAL;
do {
uint32_t Current;
do {
Current = SysTick->VAL;
} while (Current == Previous);
do {
Current = SysTick->VAL;
} while (Current == Previous);
uint32_t Delta = ((Current < Previous) ? - Current : Start - Current);
uint32_t Delta = ((Current < Previous) ? - Current : Start - Current);
elapsed_ticks += Delta + Previous;
elapsed_ticks += Delta + Previous;
Previous = Current;
} while (elapsed_ticks < ticks);
Previous = Current;
} while (elapsed_ticks < ticks);
}

122
driver/uart.c
View File

@@ -25,80 +25,80 @@ uint8_t UART_DMA_Buffer[256];
void UART_Init(void)
{
uint32_t Delta;
uint32_t Positive;
uint32_t Frequency;
uint32_t Delta;
uint32_t Positive;
uint32_t Frequency;
UART1->CTRL = (UART1->CTRL & ~UART_CTRL_UARTEN_MASK) | UART_CTRL_UARTEN_BITS_DISABLE;
Delta = SYSCON_RC_FREQ_DELTA;
Positive = (Delta & SYSCON_RC_FREQ_DELTA_RCHF_SIG_MASK) >> SYSCON_RC_FREQ_DELTA_RCHF_SIG_SHIFT;
Frequency = (Delta & SYSCON_RC_FREQ_DELTA_RCHF_DELTA_MASK) >> SYSCON_RC_FREQ_DELTA_RCHF_DELTA_SHIFT;
if (Positive) {
Frequency += 48000000U;
} else {
Frequency = 48000000U - Frequency;
}
UART1->CTRL = (UART1->CTRL & ~UART_CTRL_UARTEN_MASK) | UART_CTRL_UARTEN_BITS_DISABLE;
Delta = SYSCON_RC_FREQ_DELTA;
Positive = (Delta & SYSCON_RC_FREQ_DELTA_RCHF_SIG_MASK) >> SYSCON_RC_FREQ_DELTA_RCHF_SIG_SHIFT;
Frequency = (Delta & SYSCON_RC_FREQ_DELTA_RCHF_DELTA_MASK) >> SYSCON_RC_FREQ_DELTA_RCHF_DELTA_SHIFT;
if (Positive) {
Frequency += 48000000U;
} else {
Frequency = 48000000U - Frequency;
}
UART1->BAUD = Frequency / 39053U;
UART1->CTRL = UART_CTRL_RXEN_BITS_ENABLE | UART_CTRL_TXEN_BITS_ENABLE | UART_CTRL_RXDMAEN_BITS_ENABLE;
UART1->RXTO = 4;
UART1->FC = 0;
UART1->FIFO = UART_FIFO_RF_LEVEL_BITS_8_BYTE | UART_FIFO_RF_CLR_BITS_ENABLE | UART_FIFO_TF_CLR_BITS_ENABLE;
UART1->IE = 0;
UART1->BAUD = Frequency / 39053U;
UART1->CTRL = UART_CTRL_RXEN_BITS_ENABLE | UART_CTRL_TXEN_BITS_ENABLE | UART_CTRL_RXDMAEN_BITS_ENABLE;
UART1->RXTO = 4;
UART1->FC = 0;
UART1->FIFO = UART_FIFO_RF_LEVEL_BITS_8_BYTE | UART_FIFO_RF_CLR_BITS_ENABLE | UART_FIFO_TF_CLR_BITS_ENABLE;
UART1->IE = 0;
DMA_CTR = (DMA_CTR & ~DMA_CTR_DMAEN_MASK) | DMA_CTR_DMAEN_BITS_DISABLE;
DMA_CTR = (DMA_CTR & ~DMA_CTR_DMAEN_MASK) | DMA_CTR_DMAEN_BITS_DISABLE;
DMA_CH0->MSADDR = (uint32_t)(uintptr_t)&UART1->RDR;
DMA_CH0->MDADDR = (uint32_t)(uintptr_t)UART_DMA_Buffer;
DMA_CH0->MOD = 0
// Source
| DMA_CH_MOD_MS_ADDMOD_BITS_NONE
| DMA_CH_MOD_MS_SIZE_BITS_8BIT
| DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS1
// Destination
| DMA_CH_MOD_MD_ADDMOD_BITS_INCREMENT
| DMA_CH_MOD_MD_SIZE_BITS_8BIT
| DMA_CH_MOD_MD_SEL_BITS_SRAM
;
DMA_INTEN = 0;
DMA_INTST = 0
| DMA_INTST_CH0_TC_INTST_BITS_SET
| DMA_INTST_CH1_TC_INTST_BITS_SET
| DMA_INTST_CH2_TC_INTST_BITS_SET
| DMA_INTST_CH3_TC_INTST_BITS_SET
| DMA_INTST_CH0_THC_INTST_BITS_SET
| DMA_INTST_CH1_THC_INTST_BITS_SET
| DMA_INTST_CH2_THC_INTST_BITS_SET
| DMA_INTST_CH3_THC_INTST_BITS_SET
;
DMA_CH0->CTR = 0
| DMA_CH_CTR_CH_EN_BITS_ENABLE
| ((0xFF << DMA_CH_CTR_LENGTH_SHIFT) & DMA_CH_CTR_LENGTH_MASK)
| DMA_CH_CTR_LOOP_BITS_ENABLE
| DMA_CH_CTR_PRI_BITS_MEDIUM
;
UART1->IF = UART_IF_RXTO_BITS_SET;
DMA_CH0->MSADDR = (uint32_t)(uintptr_t)&UART1->RDR;
DMA_CH0->MDADDR = (uint32_t)(uintptr_t)UART_DMA_Buffer;
DMA_CH0->MOD = 0
// Source
| DMA_CH_MOD_MS_ADDMOD_BITS_NONE
| DMA_CH_MOD_MS_SIZE_BITS_8BIT
| DMA_CH_MOD_MS_SEL_BITS_HSREQ_MS1
// Destination
| DMA_CH_MOD_MD_ADDMOD_BITS_INCREMENT
| DMA_CH_MOD_MD_SIZE_BITS_8BIT
| DMA_CH_MOD_MD_SEL_BITS_SRAM
;
DMA_INTEN = 0;
DMA_INTST = 0
| DMA_INTST_CH0_TC_INTST_BITS_SET
| DMA_INTST_CH1_TC_INTST_BITS_SET
| DMA_INTST_CH2_TC_INTST_BITS_SET
| DMA_INTST_CH3_TC_INTST_BITS_SET
| DMA_INTST_CH0_THC_INTST_BITS_SET
| DMA_INTST_CH1_THC_INTST_BITS_SET
| DMA_INTST_CH2_THC_INTST_BITS_SET
| DMA_INTST_CH3_THC_INTST_BITS_SET
;
DMA_CH0->CTR = 0
| DMA_CH_CTR_CH_EN_BITS_ENABLE
| ((0xFF << DMA_CH_CTR_LENGTH_SHIFT) & DMA_CH_CTR_LENGTH_MASK)
| DMA_CH_CTR_LOOP_BITS_ENABLE
| DMA_CH_CTR_PRI_BITS_MEDIUM
;
UART1->IF = UART_IF_RXTO_BITS_SET;
DMA_CTR = (DMA_CTR & ~DMA_CTR_DMAEN_MASK) | DMA_CTR_DMAEN_BITS_ENABLE;
DMA_CTR = (DMA_CTR & ~DMA_CTR_DMAEN_MASK) | DMA_CTR_DMAEN_BITS_ENABLE;
UART1->CTRL |= UART_CTRL_UARTEN_BITS_ENABLE;
UART1->CTRL |= UART_CTRL_UARTEN_BITS_ENABLE;
}
void UART_Send(const void *pBuffer, uint32_t Size)
{
const uint8_t *pData = (const uint8_t *)pBuffer;
uint32_t i;
const uint8_t *pData = (const uint8_t *)pBuffer;
uint32_t i;
for (i = 0; i < Size; i++) {
UART1->TDR = pData[i];
while ((UART1->IF & UART_IF_TXFIFO_FULL_MASK) != UART_IF_TXFIFO_FULL_BITS_NOT_SET) {
}
}
for (i = 0; i < Size; i++) {
UART1->TDR = pData[i];
while ((UART1->IF & UART_IF_TXFIFO_FULL_MASK) != UART_IF_TXFIFO_FULL_BITS_NOT_SET) {
}
}
}
void UART_LogSend(const void *pBuffer, uint32_t Size)
{
if (UART_IsLogEnabled) {
UART_Send(pBuffer, Size);
}
if (UART_IsLogEnabled) {
UART_Send(pBuffer, Size);
}
}