BRNSystems/brnQuanFW
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases 3 Wiki Activity

Test
Some checks failed
Build Firmware / build (push) Has been cancelled
Details

Browse Source
This commit is contained in:
Bruno Rybársky
2025-11-04 19:49:24 +01:00
parent 1ec2e15de8
commit b54e5ef8a5
5 changed files with 57 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files

81
app/fskmodem.c
View File

@@ -30,7 +30,7 @@ typedef enum {
RXState rxState = Ready;
uint8_t SMSResponseCounterTarget = 6;
uint8_t SMSResponseCounterTarget = 6;
void FSKModem_TimeSlice500ms(void) {
if (SMSResponseCounter && FUNCTION_IsRx() && SMSResponseCounter++ > SMSResponseCounterTarget) {
@@ -65,54 +65,73 @@ void FSKModem_TimeSlice500ms(void) {
void MSG_ConfigureFSK(bool rx) {
BK4819_WriteRegister(BK4819_REG_70, TONE2_ENABLE_BIT | (96U << 0));
// Compute tone frequency control word (for 26 MHz XTAL)
#define BK4819_FREQ_WORD(freq_hz) ((uint16_t)((freq_hz) * 10.32444f))
// Tone word macro for 26MHz XTAL (app note: freq * 10.32444)
#undef BK4819_FREQ_WORD
#define BK4819_FREQ_WORD(freq_hz) ((uint16_t)((freq_hz) * 10.32444f))
switch (gEeprom.FSKMode) {
case MOD_AFSK_2400:
TONE2_FREQ = 24779U; // Estimated
TONE2_FREQ = BK4819_FREQ_WORD(2400.0f);
break;
case MOD_AFSK_1200:
TONE2_FREQ = 12389U;
TONE2_FREQ = BK4819_FREQ_WORD(1200.0f);
break;
case MOD_FSK_700:
TONE2_FREQ = 7227U;
TONE2_FREQ = BK4819_FREQ_WORD(700.0f);
break;
case MOD_FSK_450:
TONE2_FREQ = 4646U;
TONE2_FREQ = BK4819_FREQ_WORD(450.0f);
break;
case MOD_FSK_1200_2400:
TONE2_FREQ = 12389U; // Default to 1200Hz, dynamic switching may be required
TONE2_FREQ = BK4819_FREQ_WORD(1200.0f);
break;
case MOD_NOAA_SAME:
TONE2_FREQ = 2083U; // NOAA SAME uses 2083.3 Hz for mark and 1562.5 Hz for space
TONE2_FREQ = BK4819_FREQ_WORD(2083.3f);
break;
default:
TONE2_FREQ = BK4819_FREQ_WORD(1200.0f);
break;
}
BK4819_WriteRegister(BK4819_REG_72, TONE2_FREQ);
// uint16_t fskConfig = FSK_ENABLE_BIT | FSK_RX_BW_1_2K | FSK_RX_GAIN_DEFAULT | FSK_PREAMBLE_TYPE_AA;
// if (gEeprom.FSKMode == MOD_AFSK_1200) {
// fskConfig = FSK_ENABLE_BIT | FSK_TX_MODE_FSK_1_2K_2_4K | FSK_RX_MODE_FSK_1_2K_2_4K_NOAA;
// }
// Base config (enable + preamble type AA)
uint16_t fskConfig = FSK_ENABLE_BIT | FSK_PREAMBLE_TYPE_AA;
// Compose the correct fields into REG_58:
// - TX mode bits are at <15:13> (use your FSK_TX_MODE_* macros which are <<13)
// - RX mode bits are at <12:10> (use your FSK_RX_MODE_* macros which are <<10)
// - RX BW bits are at <3:1> (use your FSK_RX_BW_* macros which are <<1)
switch (gEeprom.FSKMode) {
case MOD_AFSK_1200:
fskConfig |= FSK_TX_MODE_FFSK_1200_1800 /*<<13 in macro*/
| FSK_RX_MODE_FFSK_1200_1800 /*<<10 in macro*/
| FSK_RX_BW_FFSK_1200_1800; /*<<1 in macro*/
break;
case MOD_AFSK_2400:
fskConfig |= FSK_TX_MODE_FFSK_1200_2400
| FSK_RX_MODE_FFSK_1200_2400
| FSK_RX_BW_2_4K_FFSK_1200_2400;
break;
case MOD_NOAA_SAME:
fskConfig |= FSK_TX_MODE_NOAA_SAME
| FSK_RX_MODE_FSK_1_2K_2_4K_NOAA
| FSK_RX_BW_NOAA_SAME;
break;
case MOD_FSK_700:
case MOD_FSK_450:
case MOD_FSK_1200_2400:
fskConfig |= FSK_TX_MODE_FSK_1_2K_2_4K | FSK_RX_MODE_FSK_1_2K_2_4K_NOAA | FSK_RX_BW_1_2K;
break;
case MOD_AFSK_1200:
fskConfig |= FSK_TX_MODE_FFSK_1200_1800 | FSK_RX_MODE_FFSK_1200_1800 | FSK_RX_BW_FFSK_1200_1800;
break;
case MOD_AFSK_2400:
fskConfig |= FSK_TX_MODE_FFSK_1200_2400 | FSK_RX_MODE_FFSK_1200_2400 | FSK_RX_BW_2_4K_FFSK_1200_2400;
break;
case MOD_NOAA_SAME:
fskConfig |= FSK_TX_MODE_NOAA_SAME | FSK_RX_MODE_FSK_1_2K_2_4K_NOAA | FSK_RX_BW_NOAA_SAME;
break;
default:
// Unsupported mode; keep previous setting
// binary FSK 1.2k/2.4k - use default FSK TX/RX modes and 1.2k BW
fskConfig |= FSK_TX_MODE_FSK_1_2K_2_4K
| FSK_RX_MODE_FSK_1_2K_2_4K_NOAA
| FSK_RX_BW_1_2K;
break;
}
@@ -127,19 +146,19 @@ void MSG_ConfigureFSK(bool rx) {
BK4819_WriteRegister(BK4819_REG_5E, (64U << 3) | (1U << 0));
}
// Data length (REG_5D<15:8>)
size_t size = sizeof(dataPacket);
if (rx) {
size = (((size + 1) / 2) * 2) + 2;
}
if (rx) size = (((size + 1) / 2) * 2) + 2;
BK4819_WriteRegister(BK4819_REG_5D, (size << 8));
BK4819_FskClearFifo();
// REG_59: clear flags, preamble len, sync len etc.
uint16_t fskParams = FSK_SYNC_LEN_BIT | ((rx ? 0U : 15U) << 4);
if (gCurrentVfo->SCRAMBLING_TYPE > 0) {
fskParams |= FSK_SCRAMBLE_ENABLE;
}
if (gCurrentVfo->SCRAMBLING_TYPE > 0) fskParams |= FSK_SCRAMBLE_ENABLE;
BK4819_WriteRegister(BK4819_REG_59, fskParams);
// Clear interrupt flags
BK4819_WriteRegister(BK4819_REG_02, 0);
}