Bruno Rybársky
72558f93f3
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86 lines
3.0 KiB
C
86 lines
3.0 KiB
C
/* Copyright 2023 Dual Tachyon
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* https://github.com/DualTachyon
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef BK1080_REGS_H
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#define BK1080_REGS_H
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enum BK1080_Register_t {
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BK1080_REG_00 = 0x00U,
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BK1080_REG_01_CHIP_ID = 0x01U,
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BK1080_REG_02_POWER_CONFIGURATION = 0x02U,
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BK1080_REG_03_CHANNEL = 0x03U,
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BK1080_REG_04_SYSTEM_CONFIGURATION1 = 0x04U,
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BK1080_REG_05_SYSTEM_CONFIGURATION2 = 0x05U,
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BK1080_REG_06_SYSTEM_CONFIGURATION3 = 0x06U,
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BK1080_REG_07_TEST1 = 0x07U,
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BK1080_REG_08_TEST2 = 0x08U,
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BK1080_REG_09_BOOT_CONFIGURATION = 0x09U,
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BK1080_REG_10_RSSI_STATUS = 0x0AU,
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BK1080_REG_11_RSSI_THRESHOLD = 0x0BU,
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BK1080_REG_12_INTERNAL = 0x0CU,
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BK1080_REG_13_INTERNAL = 0x0DU,
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BK1080_REG_14_INTERNAL = 0x0EU,
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BK1080_REG_15_INTERNAL = 0x0FU,
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BK1080_REG_16_INTERNAL = 0x10U,
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BK1080_REG_17_INTERNAL = 0x11U,
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BK1080_REG_18_INTERNAL = 0x12U,
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BK1080_REG_19_INTERNAL = 0x13U,
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BK1080_REG_20_INTERNAL = 0x14U,
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BK1080_REG_21_INTERNAL = 0x15U,
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BK1080_REG_22_INTERNAL = 0x16U,
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BK1080_REG_23_INTERNAL = 0x17U,
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BK1080_REG_24_INTERNAL = 0x18U,
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BK1080_REG_25_INTERNAL = 0x19U,
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BK1080_REG_26_INTERNAL = 0x1AU,
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BK1080_REG_27_INTERNAL = 0x1BU,
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BK1080_REG_28_INTERNAL = 0x1CU,
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BK1080_REG_29_INTERNAL = 0x1DU,
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BK1080_REG_30_INTERNAL = 0x1EU,
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BK1080_REG_31_INTERNAL = 0x1FU,
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BK1080_REG_32_INTERNAL = 0x20U,
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BK1080_REG_33_INTERNAL = 0x21U,
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};
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typedef enum BK1080_Register_t BK1080_Register_t;
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// REG 07
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#define BK1080_REG_07_SHIFT_FREQD 4
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#define BK1080_REG_07_SHIFT_SNR 0
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#define BK1080_REG_07_MASK_FREQD (0xFFFU << BK1080_REG_07_SHIFT_FREQD)
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#define BK1080_REG_07_MASK_SNR (0x00FU << BK1080_REG_07_SHIFT_SNR)
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#define BK1080_REG_07_GET_FREQD(x) (((x) & BK1080_REG_07_MASK_FREQD) >> BK1080_REG_07_SHIFT_FREQD)
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#define BK1080_REG_07_GET_SNR(x) (((x) & BK1080_REG_07_MASK_SNR) >> BK1080_REG_07_SHIFT_SNR)
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// REG 10
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#define BK1080_REG_10_SHIFT_AFCRL 12
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#define BK1080_REG_10_SHIFT_RSSI 0
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#define BK1080_REG_10_MASK_AFCRL (0x01U << BK1080_REG_10_SHIFT_AFCRL)
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#define BK1080_REG_10_MASK_RSSI (0xFFU << BK1080_REG_10_SHIFT_RSSI)
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#define BK1080_REG_10_AFCRL_NOT_RAILED (0U << BK1080_REG_10_SHIFT_AFCRL)
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#define BK1080_REG_10_AFCRL_RAILED (1U << BK1080_REG_10_SHIFT_AFCRL)
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#define BK1080_REG_10_GET_RSSI(x) (((x) & BK1080_REG_10_MASK_RSSI) >> BK1080_REG_10_SHIFT_RSSI)
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#endif
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