456 lines
19 KiB
C
456 lines
19 KiB
C
/***********************************************************************//**
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* @file system_LPC177x_8x.c
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Source File
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* for the NXP LPC177x_8x Device Series
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* @version V1.11
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* @date 10. November. 2010
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* @author NXP MCU SW Application Team
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**************************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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**********************************************************************/
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#include <stdint.h>
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#include "LPC177x_8x.h"
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#include "system_LPC177x_8x.h"
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/*
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//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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*/
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/*--------------------- Clock Configuration ----------------------------------
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//
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// <e> Clock Configuration
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// <h> System Controls and Status Register (SCS)
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// <o1.0> EMC_SHIFT: EMC Shift enable
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// <0=> Static CS addresses match bus width; AD[1] = 0 for 32 bit, AD[0] = 0 for 16+32 bit
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// <1=> Static CS addresses start at LSB 0 regardless of memory width
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// <o1.1> EMC_RESET: EMC Reset disable
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// <0=> EMC will be reset by any chip reset
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// <1=> Portions of EMC will only be reset by POR or BOR
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// <o1.2> EMC_BURST: EMC Burst disable
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// <o1.3> MCIPWR_LEVEL: SD card interface signal SD_PWR Active Level selection
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// <0=> SD_PWR is active low
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// <1=> SD_PWR is active high
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// <o1.4> OSCRANGE: Main Oscillator Range Select
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// <0=> 1 MHz to 20 MHz
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// <1=> 15 MHz to 25 MHz
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// <o1.5> OSCEN: Main Oscillator enable
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// </h>
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//
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// <h> Clock Source Select Register (CLKSRCSEL)
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// <o2.0> CLKSRC: sysclk and PLL0 clock source selection
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// <0=> Internal RC oscillator
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// <1=> Main oscillator
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// </h>
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//
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// <e3> PLL0 Configuration (Main PLL)
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// <h> PLL0 Configuration Register (PLL0CFG)
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// <i> PLL out clock = (F_cco / (2 * P))
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// <i> F_cco = (F_in * M * 2 * P)
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// <i> F_in must be in the range of 1 MHz to 25 MHz
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// <i> F_cco must be in the range of 9.75 MHz to 160 MHz
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// <o4.0..4> MSEL: PLL Multiplier Selection
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// <i> M Value
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// <1-32><#-1>
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// <o4.5..6> PSEL: PLL Divider Selection
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// <i> P Value
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// <0=> 1
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// <1=> 2
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// <2=> 4
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// <3=> 8
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// </h>
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// </e>
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//
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// <e5> PLL1 Configuration (Alt PLL)
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// <h> PLL1 Configuration Register (PLL1CFG)
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// <i> PLL out clock = (F_cco / (2 * P))
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// <i> F_cco = (F_in * M * 2 * P)
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// <i> F_in must be in the range of 1 MHz to 25 MHz
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// <i> F_cco must be in the range of 9.75 MHz to 160 MHz
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// <o6.0..4> MSEL: PLL Multiplier Selection
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// <i> M Value
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// <1-32><#-1>
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// <o6.5..6> PSEL: PLL Divider Selection
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// <i> P Value
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// <0=> 1
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// <1=> 2
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// <2=> 4
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// <3=> 8
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// </h>
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// </e>
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//
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// <h> CPU Clock Selection Register (CCLKSEL)
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// <o7.0..4> CCLKDIV: CPU clock (CCLK) divider
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// <i> 0: The divider is turned off. No clock will be provided to the CPU
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// <i> n: The input clock is divided by n to produce the CPU clock
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// <0-31>
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// <o7.8> CCLKSEL: CPU clock divider input clock selection
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// <0=> sysclk clock
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// <1=> PLL0 clock
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// </h>
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//
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// <h> USB Clock Selection Register (USBCLKSEL)
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// <o8.0..4> USBDIV: USB clock (source PLL0) divider selection
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// <0=> USB clock off
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// <4=> PLL0 / 4 (PLL0 must be 192Mhz)
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// <6=> PLL0 / 6 (PLL0 must be 288Mhz)
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// <o8.8..9> USBSEL: USB clock divider input clock selection
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// <i> When CPU clock is selected, the USB can be accessed
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// <i> by software but cannot perform USB functions
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// <0=> CPU clock
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// <1=> PLL0 clock
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// <2=> PLL1 clock
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// </h>
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//
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// <h> EMC Clock Selection Register (EMCCLKSEL)
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// <o9.0> EMCDIV: EMC clock selection
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// <0=> CPU clock
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// <1=> CPU clock / 2
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// </h>
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//
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// <h> Peripheral Clock Selection Register (PCLKSEL)
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// <o10.0..4> PCLKDIV: APB Peripheral clock divider
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// <i> 0: The divider is turned off. No clock will be provided to APB peripherals
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// <i> n: The input clock is divided by n to produce the APB peripheral clock
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// <0-31>
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// </h>
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//
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// <h> Power Control for Peripherals Register (PCONP)
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// <o11.0> PCLCD: LCD controller power/clock enable
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// <o11.1> PCTIM0: Timer/Counter 0 power/clock enable
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// <o11.2> PCTIM1: Timer/Counter 1 power/clock enable
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// <o11.3> PCUART0: UART 0 power/clock enable
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// <o11.4> PCUART1: UART 1 power/clock enable
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// <o11.5> PCPWM0: PWM0 power/clock enable
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// <o11.6> PCPWM1: PWM1 power/clock enable
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// <o11.7> PCI2C0: I2C 0 interface power/clock enable
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// <o11.8> PCUART4: UART 4 power/clock enable
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// <o11.9> PCRTC: RTC and Event Recorder power/clock enable
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// <o11.10> PCSSP1: SSP 1 interface power/clock enable
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// <o11.11> PCEMC: External Memory Controller power/clock enable
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// <o11.12> PCADC: A/D converter power/clock enable
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// <o11.13> PCCAN1: CAN controller 1 power/clock enable
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// <o11.14> PCCAN2: CAN controller 2 power/clock enable
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// <o11.15> PCGPIO: IOCON, GPIO, and GPIO interrupts power/clock enable
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// <o11.17> PCMCPWM: Motor Control PWM power/clock enable
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// <o11.18> PCQEI: Quadrature encoder interface power/clock enable
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// <o11.19> PCI2C1: I2C 1 interface power/clock enable
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// <o11.20> PCSSP2: SSP 2 interface power/clock enable
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// <o11.21> PCSSP0: SSP 0 interface power/clock enable
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// <o11.22> PCTIM2: Timer 2 power/clock enable
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// <o11.23> PCTIM3: Timer 3 power/clock enable
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// <o11.24> PCUART2: UART 2 power/clock enable
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// <o11.25> PCUART3: UART 3 power/clock enable
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// <o11.26> PCI2C2: I2C 2 interface power/clock enable
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// <o11.27> PCI2S: I2S interface power/clock enable
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// <o11.28> PCSDC: SD Card interface power/clock enable
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// <o11.29> PCGPDMA: GPDMA function power/clock enable
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// <o11.30> PCENET: Ethernet block power/clock enable
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// <o11.31> PCUSB: USB interface power/clock enable
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// </h>
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//
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// <h> Clock Output Configuration Register (CLKOUTCFG)
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// <o12.0..3> CLKOUTSEL: Clock Source for CLKOUT Selection
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// <0=> CPU clock
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// <1=> Main Oscillator
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// <2=> Internal RC Oscillator
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// <3=> USB clock
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// <4=> RTC Oscillator
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// <5=> unused
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// <6=> Watchdog Oscillator
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// <o12.4..7> CLKOUTDIV: Output Clock Divider
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// <1-16><#-1>
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// <o12.8> CLKOUT_EN: CLKOUT enable
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// </h>
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//
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// </e>
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*/
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#define CLOCK_SETUP 1
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#define SCS_Val 0x00000021
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#define CLKSRCSEL_Val 0x00000001
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#define PLL0_SETUP 1
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#define PLL0CFG_Val 0x00000009
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#define PLL1_SETUP 1
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#define PLL1CFG_Val 0x00000023
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#define CCLKSEL_Val (0x00000001|(1<<8))
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#define USBCLK_SETUP 1
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#define USBCLKSEL_Val (0x00000001|(0x02<<8))
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#define EMCCLKSEL_Val 0x00000001
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#define PCLKSEL_Val 0x00000002
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#define PCONP_Val 0x042887DE
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#define CLKOUTCFG_Val 0x00000100
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/*--------------------- Flash Accelerator Configuration ----------------------
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//
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// <e> Flash Accelerator Configuration
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// <o1.12..15> FLASHTIM: Flash Access Time
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// <0=> 1 CPU clock (for CPU clock up to 20 MHz)
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// <1=> 2 CPU clocks (for CPU clock up to 40 MHz)
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// <2=> 3 CPU clocks (for CPU clock up to 60 MHz)
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// <3=> 4 CPU clocks (for CPU clock up to 80 MHz)
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// <4=> 5 CPU clocks (for CPU clock up to 100 MHz)
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// <5=> 6 CPU clocks (for any CPU clock)
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// </e>
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*/
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#define FLASH_SETUP 1
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#define FLASHCFG_Val 0x00005000
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/*----------------------------------------------------------------------------
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Check the register settings
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*----------------------------------------------------------------------------*/
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#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
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#define CHECK_RSVD(val, mask) (val & mask)
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/* Clock Configuration -------------------------------------------------------*/
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#if (CHECK_RSVD((SCS_Val), ~0x0000003F))
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#error "SCS: Invalid values of reserved bits!"
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#endif
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#if (CHECK_RANGE((CLKSRCSEL_Val), 0, 1))
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#error "CLKSRCSEL: Value out of range!"
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#endif
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#if (CHECK_RSVD((PLL0CFG_Val), ~0x0000007F))
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#error "PLL0CFG: Invalid values of reserved bits!"
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#endif
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#if (CHECK_RSVD((PLL1CFG_Val), ~0x0000007F))
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#error "PLL1CFG: Invalid values of reserved bits!"
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#endif
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#if (CHECK_RSVD((CCLKSEL_Val), ~0x0000011F))
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#error "CCLKSEL: Invalid values of reserved bits!"
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#endif
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#if (CHECK_RSVD((USBCLKSEL_Val), ~0x0000031F))
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#error "USBCLKSEL: Invalid values of reserved bits!"
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#endif
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#if (CHECK_RSVD((EMCCLKSEL_Val), ~0x00000001))
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#error "EMCCLKSEL: Invalid values of reserved bits!"
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#endif
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#if (CHECK_RSVD((PCLKSEL_Val), ~0x0000001F))
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#error "PCLKSEL: Invalid values of reserved bits!"
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#endif
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#if (CHECK_RSVD((PCONP_Val), ~0xFFFEFFFF))
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#error "PCONP: Invalid values of reserved bits!"
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#endif
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#if (CHECK_RSVD((CLKOUTCFG_Val), ~0x000001FF))
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#error "CLKOUTCFG: Invalid values of reserved bits!"
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#endif
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/* Flash Accelerator Configuration -------------------------------------------*/
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#if (CHECK_RSVD((FLASHCFG_Val), ~0x0000F000))
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#warning "FLASHCFG: Invalid values of reserved bits!"
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#endif
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/*----------------------------------------------------------------------------
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DEFINES
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*----------------------------------------------------------------------------*/
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/* pll_out_clk = F_cco / (2 × P)
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F_cco = pll_in_clk × M × 2 × P */
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#define __M ((PLL0CFG_Val & 0x1F) + 1)
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#define __PLL0_CLK(__F_IN) (__F_IN * __M)
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#define __CCLK_DIV (CCLKSEL_Val & 0x1F)
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#define __PCLK_DIV (PCLKSEL_Val & 0x1F)
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#define __ECLK_DIV ((EMCCLKSEL_Val & 0x01) + 1)
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/* Determine core clock frequency according to settings */
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#if (CLOCK_SETUP) /* Clock Setup */
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#if ((CLKSRCSEL_Val & 0x01) == 1) && ((SCS_Val & 0x20)== 0)
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#error "Main Oscillator is selected as clock source but is not enabled!"
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#endif
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#if ((CCLKSEL_Val & 0x100) == 0x100) && (PLL0_SETUP == 0)
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#error "Main PLL is selected as clock source but is not enabled!"
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#endif
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#if ((CCLKSEL_Val & 0x100) == 0) /* cclk = sysclk */
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#if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */
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#define __CORE_CLK (IRC_OSC / __CCLK_DIV)
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#define __PER_CLK (IRC_OSC/ __PCLK_DIV)
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#define __EMC_CLK (IRC_OSC/ __ECLK_DIV)
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#else /* sysclk = osc_clk */
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#define __CORE_CLK (OSC_CLK / __CCLK_DIV)
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#define __PER_CLK (OSC_CLK/ __PCLK_DIV)
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#define __EMC_CLK (OSC_CLK/ __ECLK_DIV)
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#endif
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#else /* cclk = pll_clk */
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#if ((CLKSRCSEL_Val & 0x01) == 0) /* sysclk = irc_clk */
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#define __CORE_CLK (__PLL0_CLK(IRC_OSC) / __CCLK_DIV)
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#define __PER_CLK (__PLL0_CLK(IRC_OSC) / __PCLK_DIV)
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#define __EMC_CLK (__PLL0_CLK(IRC_OSC) / __ECLK_DIV)
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#else /* sysclk = osc_clk */
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#define __CORE_CLK (__PLL0_CLK(OSC_CLK) / __CCLK_DIV)
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#define __PER_CLK (__PLL0_CLK(OSC_CLK) / __PCLK_DIV)
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#define __EMC_CLK (__PLL0_CLK(OSC_CLK) / __ECLK_DIV)
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#endif
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#endif
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#else
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#define __CORE_CLK (IRC_OSC)
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#define __PER_CLK (IRC_OSC)
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#define __EMC_CLK (IRC_OSC)
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#endif
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/*----------------------------------------------------------------------------
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Clock Variable definitions
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*----------------------------------------------------------------------------*/
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uint32_t SystemCoreClock = __CORE_CLK;/*!< System Clock Frequency (Core Clock)*/
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uint32_t PeripheralClock = __PER_CLK; /*!< Peripheral Clock Frequency (Pclk) */
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uint32_t EMCClock = __EMC_CLK; /*!< EMC Clock Frequency */
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uint32_t USBClock = (48000000UL); /*!< USB Clock Frequency - this value will
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be updated after call SystemCoreClockUpdate, should be 48MHz*/
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/*----------------------------------------------------------------------------
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Clock functions
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*----------------------------------------------------------------------------*/
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void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
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{
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/* Determine clock frequency according to clock register values */
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if ((LPC_SC->CCLKSEL &0x100) == 0) { /* cclk = sysclk */
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if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */
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SystemCoreClock = (IRC_OSC / (LPC_SC->CCLKSEL & 0x1F));
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PeripheralClock = (IRC_OSC / (LPC_SC->PCLKSEL & 0x1F));
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EMCClock = (IRC_OSC / ((LPC_SC->EMCCLKSEL & 0x01)+1));
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}
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else { /* sysclk = osc_clk */
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if ((LPC_SC->SCS & 0x40) == 0) {
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SystemCoreClock = 0; /* this should never happen! */
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PeripheralClock = 0;
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EMCClock = 0;
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}
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else {
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SystemCoreClock = (OSC_CLK / (LPC_SC->CCLKSEL & 0x1F));
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PeripheralClock = (OSC_CLK / (LPC_SC->PCLKSEL & 0x1F));
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EMCClock = (OSC_CLK / ((LPC_SC->EMCCLKSEL & 0x01)+1));
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}
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}
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}
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else { /* cclk = pll_clk */
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if ((LPC_SC->PLL0STAT & 0x100) == 0) { /* PLL0 not enabled */
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SystemCoreClock = 0; /* this should never happen! */
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PeripheralClock = 0;
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EMCClock = 0;
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}
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else {
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if ((LPC_SC->CLKSRCSEL & 0x01) == 0) { /* sysclk = irc_clk */
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SystemCoreClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->CCLKSEL & 0x1F));
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PeripheralClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->PCLKSEL & 0x1F));
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EMCClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / ((LPC_SC->EMCCLKSEL & 0x01)+1));
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}
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else { /* sysclk = osc_clk */
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if ((LPC_SC->SCS & 0x40) == 0) {
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SystemCoreClock = 0; /* this should never happen! */
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PeripheralClock = 0;
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EMCClock = 0;
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}
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else {
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SystemCoreClock = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->CCLKSEL & 0x1F));
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PeripheralClock = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->PCLKSEL & 0x1F));
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EMCClock = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / ((LPC_SC->EMCCLKSEL & 0x01)+1));
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}
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}
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}
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}
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/* ---update USBClock------------------*/
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if(LPC_SC->USBCLKSEL & (0x01<<8))//Use PLL0 as the input to the USB clock divider
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{
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switch (LPC_SC->USBCLKSEL & 0x1F)
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{
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case 0:
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USBClock = 0; //no clock will be provided to the USB subsystem
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break;
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case 4:
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case 6:
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if(LPC_SC->CLKSRCSEL & 0x01) //pll_clk_in = main_osc
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USBClock = (OSC_CLK * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->USBCLKSEL & 0x1F));
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else //pll_clk_in = irc_clk
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USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1) / (LPC_SC->USBCLKSEL & 0x1F));
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break;
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default:
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USBClock = 0; /* this should never happen! */
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}
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}
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else if(LPC_SC->USBCLKSEL & (0x02<<8))//usb_input_clk = alt_pll (pll1)
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{
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if(LPC_SC->CLKSRCSEL & 0x01) //pll1_clk_in = main_osc
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USBClock = (OSC_CLK * ((LPC_SC->PLL1STAT & 0x1F) + 1));
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else //pll1_clk_in = irc_clk
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USBClock = (IRC_OSC * ((LPC_SC->PLL0STAT & 0x1F) + 1));
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}
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else
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USBClock = 0; /* this should never happen! */
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}
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/* Determine clock frequency according to clock register values */
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/**
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* Initialize the system
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*
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* @param none
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* @return none
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*
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* @brief Setup the microcontroller system.
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* Initialize the System.
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*/
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void SystemInit (void)
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{
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#if (CLOCK_SETUP) /* Clock Setup */
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LPC_SC->SCS = SCS_Val;
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if (SCS_Val & (1 << 5)) { /* If Main Oscillator is enabled */
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while ((LPC_SC->SCS & (1<<6)) == 0);/* Wait for Oscillator to be ready */
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||
}
|
||
|
||
LPC_SC->CLKSRCSEL = CLKSRCSEL_Val; /* Select Clock Source for sysclk/PLL0*/
|
||
|
||
#if (PLL0_SETUP)
|
||
LPC_SC->PLL0CFG = PLL0CFG_Val;
|
||
LPC_SC->PLL0CON = 0x01; /* PLL0 Enable */
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||
LPC_SC->PLL0FEED = 0xAA;
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||
LPC_SC->PLL0FEED = 0x55;
|
||
while (!(LPC_SC->PLL0STAT & (1<<10)));/* Wait for PLOCK0 */
|
||
#endif
|
||
|
||
#if (PLL1_SETUP)
|
||
LPC_SC->PLL1CFG = PLL1CFG_Val;
|
||
LPC_SC->PLL1CON = 0x01; /* PLL1 Enable */
|
||
LPC_SC->PLL1FEED = 0xAA;
|
||
LPC_SC->PLL1FEED = 0x55;
|
||
while (!(LPC_SC->PLL1STAT & (1<<10)));/* Wait for PLOCK1 */
|
||
#endif
|
||
|
||
LPC_SC->CCLKSEL = CCLKSEL_Val; /* Setup Clock Divider */
|
||
LPC_SC->USBCLKSEL = USBCLKSEL_Val; /* Setup USB Clock Divider */
|
||
LPC_SC->EMCCLKSEL = EMCCLKSEL_Val; /* EMC Clock Selection */
|
||
LPC_SC->PCLKSEL = PCLKSEL_Val; /* Peripheral Clock Selection */
|
||
LPC_SC->PCONP = PCONP_Val; /* Power Control for Peripherals */
|
||
LPC_SC->CLKOUTCFG = CLKOUTCFG_Val; /* Clock Output Configuration */
|
||
#endif
|
||
|
||
#if (FLASH_SETUP == 1) /* Flash Accelerator Setup */
|
||
LPC_SC->FLASHCFG = FLASHCFG_Val|0x03A;
|
||
#endif
|
||
#ifdef __RAM_MODE__
|
||
SCB->VTOR = 0x10000000 & 0x3FFFFF80;
|
||
#else
|
||
SCB->VTOR = 0x00000000 & 0x3FFFFF80;
|
||
#endif
|
||
}
|