From aed00ceda268e57327d4bfff9c4176be9253d5dd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bruno=20Ryb=C3=A1rsky?= Date: Mon, 11 May 2026 18:55:56 +0200 Subject: [PATCH] finish es8311 manual --- main/drivers/es8311.c | 216 ++++++++++++++++----------- main/drivers/es8311.h | 335 +++++++++++++++++++++++++++++++----------- main/drivers/i2s.c | 3 +- main/main.c | 4 +- 4 files changed, 385 insertions(+), 173 deletions(-) diff --git a/main/drivers/es8311.c b/main/drivers/es8311.c index 31c15bf..5317d5f 100644 --- a/main/drivers/es8311.c +++ b/main/drivers/es8311.c @@ -22,28 +22,29 @@ int es8311_write(uint8_t reg, uint8_t val) { return 0; } +static uint8_t db_to_es8311_vol(float db) { + if (db < -95.5f) + db = -95.5f; + if (db > 32.0f) + db = 32.0f; + + // ES8311 typically uses 0.5 dB steps + int v = (int)((db + 95.5f) * 2.0f); + + if (v < 0) + v = 0; + if (v > 255) + v = 255; + + return (uint8_t)v; +} + void es8311_set_dac_volume(float vol) { - if (vol < -95.5f) { - vol = -95.5f; - } - if (vol > 32) { - vol = 32; - } - vol *= 2; - uint8_t volByte = vol; - es8311_write(ES8311_DAC_REG32, volByte); + es8311_write(ES8311_DAC_REG32, db_to_es8311_vol(vol)); } void es8311_set_adc_volume(float vol) { - if (vol < -95.5f) { - vol = -95.5f; - } - if (vol > 32) { - vol = 32; - } - vol *= 2; - uint8_t volByte = vol; - es8311_write(ES8311_ADC_REG17, volByte); + es8311_write(ES8311_ADC_REG17, db_to_es8311_vol(vol)); } uint8_t es8311_read(uint8_t reg) { @@ -56,6 +57,34 @@ uint8_t es8311_read(uint8_t reg) { return val; } +static void es8311_write_eq_coeff(uint8_t reg_base, uint32_t coeff) { + coeff &= 0x3FFFFFFF; + + es8311_write(reg_base + 0, (uint8_t)((coeff >> 24) & 0x3F)); + es8311_write(reg_base + 1, (uint8_t)(coeff >> 16)); + es8311_write(reg_base + 2, (uint8_t)(coeff >> 8)); + es8311_write(reg_base + 3, (uint8_t)(coeff)); +} +void es8311_set_eq(const es8311_eq_t *eq) { + if (!eq) + return; + + // B0 + es8311_write_eq_coeff(0x1D, eq->b0); + + // A1 + es8311_write_eq_coeff(0x21, eq->a1); + + // A2 + es8311_write_eq_coeff(0x25, eq->a2); + + // B1 + es8311_write_eq_coeff(0x29, eq->b1); + + // B2 + es8311_write_eq_coeff(0x2D, eq->b2); +} + void es8311_init(void) { printf("ES8311: Starting initialization...\n"); @@ -70,63 +99,70 @@ void es8311_init(void) { return; } + // Reset sequence + es8311_write(ES8311_RESET_REG00, 0x1F); + vTaskDelay(pdMS_TO_TICKS(20)); + es8311_write(ES8311_RESET_REG00, 0x00); + es8311_write(ES8311_RESET_REG00, 0x80); // Power-on + vTaskDelay(pdMS_TO_TICKS(20)); + + // Start analog circuitry + es8311_write(ES8311_SYSTEM_REG0D, 0x01); + vTaskDelay(pdMS_TO_TICKS(20)); + + // Configure I2S format - Slave mode + es8311_write(ES8311_RESET_REG00, 0x80); // Ensure slave mode + es8311_write(ES8311_SDPIN_REG, - ES8311_SDPIN_FORMAT_I2S | ES8311_SDPIN_WORD_24BIT | + ES8311_SDPIN_FORMAT_I2S | ES8311_SDPIN_WORD_16BIT | ES8311_SDPIN_LR_NORMAL_POLARITY | ES8311_SDPIN_UNMUTE | ES8311_SDPIN_SEL_LEFT_TO_DAC); es8311_write(ES8311_SDPOUT_REG, - ES8311_SDPOUT_FORMAT_I2S | ES8311_SDPOUT_WORD_24BIT | + ES8311_SDPOUT_FORMAT_I2S | ES8311_SDPOUT_WORD_16BIT | ES8311_SDPOUT_LR_NORMAL_POLARITY | ES8311_SDPOUT_UNMUTE); - es8311_write(ES8311_RESET_REG00, - ES8311_RESET_CSM_MSC_SLAVE | ES8311_RESET_CSM_ON); - - es8311_write(ES8311_CLK_MANAGER_REG07, - ES8311_CLK_MANAGER_REG07_ADCDAT_NORMAL_MODE | - ES8311_CLK_MANAGER_REG07_BCLK_LRCLK_NORMAL_MODE); - + /* + // Clock configuration for 48kHz from BCLK es8311_write(ES8311_CLK_MANAGER_REG01, ES8311_CLK_MANAGER_REG01_MCLK_INV_OFF | - ES8311_CLK_MANAGER_REG01_MCLK_OFF | + ES8311_CLK_MANAGER_REG01_MCLK_ON | ES8311_CLK_MANAGER_REG01_MCLK_SEL_FROM_BCLK | - ES8311_CLK_MANAGER_REG01_BCLK_OFF); + ES8311_CLK_MANAGER_REG01_BCLK_ON); + */ - // mclk 12.288 MHz LRCK 48kHz + es8311_write(ES8311_CLK_MANAGER_REG01, + ES8311_CLK_MANAGER_REG01_BCLK_ON); + + /* es8311_write(ES8311_CLK_MANAGER_REG02, 0x00); es8311_write(ES8311_CLK_MANAGER_REG03, 0x10); es8311_write(ES8311_CLK_MANAGER_REG04, 0x10); es8311_write(ES8311_CLK_MANAGER_REG05, 0x00); - es8311_write(ES8311_ADC_REG16, 0x04); // 24 db gain - // off in slave mode, we dont care + */ + + // CRITICAL: Set LRCK divider es8311_write(ES8311_CLK_MANAGER_REG06, ES8311_CLK_MANAGER_REG06_CONTINUAL_BCLK | ES8311_CLK_MANAGER_REG06_NORMAL_BCLK | - ES8311_CLK_MANAGER_REG06_DIV_BCLK_3); + ES8311_CLK_MANAGER_REG06_DIV_BCLK_4); + + es8311_write(ES8311_CLK_MANAGER_REG07, + ES8311_CLK_MANAGER_REG07_ADCDAT_NORMAL_MODE | + ES8311_CLK_MANAGER_REG07_BCLK_LRCLK_NORMAL_MODE); + + // MISSING REGISTER - LRCK divider low byte + es8311_write(ES8311_CLK_MANAGER_REG08, 0xFF); - // lrck divider is ignored, since we are in slave mode + vTaskDelay(pdMS_TO_TICKS(20)); - es8311_write(ES8311_RESET_REG00, - ES8311_RESET_CSM_MSC_SLAVE | ES8311_RESET_CSM_ON | - ES8311_RESET_DIGITAL_RUN | ES8311_RESET_CLOCK_MANAGER_RUN | - ES8311_RESET_MASTER_RUN | ES8311_RESET_ADC_DIGITAL_RUN | - ES8311_RESET_DAC_DIGITAL_RUN); + // Power up and enable everything + es8311_write(ES8311_SYSTEM_REG0E, ES8311_SYSTEM_REG0E_PGA_ENABLE | + ES8311_SYSTEM_REG0E_PDN_MOD_ENABLE | + ES8311_SYSTEM_REG0E_MOD_NORMAL); - es8311_write(ES8311_SYSTEM_REG0D, - ES8311_SYSTEM_REG0D_ANALOG_ENABLED | - ES8311_SYSTEM_REG0D_ANALOG_BIAS_ENABLED | - ES8311_SYSTEM_REG0D_ANALOG_ADC_BIAS_ENABLED | - ES8311_SYSTEM_REG0D_ANALOG_ADC_REFERENCE_ENABLED | - ES8311_SYSTEM_REG0D_ANALOG_DAC_REFERENCE_ENABLED | - ES8311_SYSTEM_REG0D_VMID_START_NORMAL_SPEED); - - es8311_write(ES8311_SYSTEM_REG0D, - ES8311_SYSTEM_REG0D_ANALOG_ENABLED | - ES8311_SYSTEM_REG0D_ANALOG_BIAS_ENABLED | - ES8311_SYSTEM_REG0D_ANALOG_ADC_BIAS_ENABLED | - ES8311_SYSTEM_REG0D_ANALOG_ADC_REFERENCE_ENABLED | - ES8311_SYSTEM_REG0D_ANALOG_DAC_REFERENCE_ENABLED | - ES8311_SYSTEM_REG0D_VMID_NORMAL); + es8311_write(ES8311_SYSTEM_REG12, 0x00); // DAC on + es8311_write(ES8311_SYSTEM_REG13, 0x10); // Output enable es8311_write(ES8311_SYSTEM_REG0F, ES8311_SYSTEM_REG0F_DAC_NORMAL_MODE | @@ -138,37 +174,48 @@ void es8311_init(void) { ES8311_SYSTEM_REG0F_FLASH_NORMAL_MODE | ES8311_SYSTEM_REG0F_INT1_NORMAL_MODE); - es8311_write(ES8311_SYSTEM_REG0E, - ES8311_SYSTEM_REG0E_PGA_ENABLE | - ES8311_SYSTEM_REG0E_PDN_MOD_ENABLE | - ES8311_SYSTEM_REG0E_MOD_NORMAL - ); + // Microphone configuration + es8311_write(ES8311_SYSTEM_REG14, ES8311_SYSTEM_REG14_DMIC_OFF | + ES8311_SYSTEM_REG14_MIC1 | + ES8311_SYSTEM_REG14_GAIN_30DB); - es8311_write(ES8311_SYSTEM_REG14, - ES8311_SYSTEM_REG14_DMIC_OFF | - ES8311_SYSTEM_REG14_MIC1 | - ES8311_SYSTEM_REG14_GAIN_30DB - ); + es8311_write(ES8311_ADC_REG16, ES8311_ADC_REG16_ADC_GAIN_24DB); + + es8311_write(ES8311_ADC_REG1C, ES8311_ADC_REG1C_HPF_DYNAMIC_HPF | + ES8311_ADC_REG1C_ADCEQ_BYPASS); + + es8311_write(ES8311_ADC_REG18, ES8311_ADC_REG18_AUTO_LEVEL_CONTROL_ENABLE | + ES8311_ADC_REG18_AUTO_MUTE_DISABLE | + ES8311_ADC_REG18_0_25DB_PER_65536LRCK); - es8311_write(ES8311_ADC_REG1C, - ES8311_ADC_REG1C_HPF_DYNAMIC_HPF | - ES8311_ADC_REG1C_ADCEQ_BYPASS - ); - es8311_write(ES8311_ADC_REG18, - ES8311_ADC_REG18_AUTO_LEVEL_CONTROL_ENABLE | - ES8311_ADC_REG18_AUTO_MUTE_DISABLE | - ES8311_ADC_REG18_0_25DB_PER_65536LRCK - ); + es8311_write(ES8311_ADC_REG19, ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_30_1DB | + ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_6_0DB); - es8311_write(ES8311_ADC_REG19, - ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_30_1DB | - ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_6_0DB - ); + es8311_write(ES8311_ADC_REG1A, ES8311_ADC_REG1A_AUTOMUTE_NEG_96DB | + ES8311_ADC_REG1A_AUTOMUTE_32768_SAMPLES); - es8311_write(ES8311_ADC_REG1A, - ES8311_ADC_REG1A_AUTOMUTE_NEG_96DB | - ES8311_ADC_REG1A_AUTOMUTE_32768_SAMPLES - ); + es8311_write(ES8311_GPIO_REG44, ES8311_GPIO_REG44_ADCDAT_SEL_ADC_ADC | + ES8311_GPIO_REG44_ADCDAT_SEL_NO_LOOPBACK); + //ES8311_GPIO_REG44_ADCDAT_ADC_TO_DAC); + + es8311_write(ES8311_ADC_REG15, ES8311_ADC_REG15_RAMPRATE_0_25_4096LRCK); + es8311_write(ES8311_DAC_REG37, ES8311_DAC_REG37_RAMPRATE_0_25_4096LRCK); + + es8311_set_adc_volume(5); + es8311_set_dac_volume(5); + + es8311_write(ES8311_DAC_REG31, ES8311_DAC_REG31_MUTE_TO8 | + ES8311_DAC_REG31_DSM_UNMUTE | + ES8311_DAC_REG31_DEM_UNMUTE); + + es8311_write(ES8311_DAC_REG34, + ES8311_DAC_REG34_DRC_DISABLE | + ES8311_DAC_REG34_DRC_WINSIZE_0_25_65536LRCK); + + es8311_write(ES8311_DAC_REG35, ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_6_0DB | + ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_30_1DB); + + printf("ES8311: Initialization complete\n"); } int audio_write(const int16_t *samples, size_t count) { @@ -212,9 +259,9 @@ void audio_beep(void) { } void audio_test_tone(void) { - const int sample_rate = 44100; - const int duration_ms = 1000; - const int freq_hz = 440; // A4 note + const int sample_rate = 48000; + const int duration_ms = 100; + const int freq_hz = 1000; // A4 note const int num_samples = (sample_rate * duration_ms) / 1000; int16_t *buf = malloc(num_samples * 2 * sizeof(int16_t)); @@ -230,7 +277,6 @@ void audio_test_tone(void) { buf[i * 2 + 1] = sample; // Right } - printf("Playing 440Hz tone for 1 second...\n"); audio_write(buf, num_samples * 2); free(buf); } \ No newline at end of file diff --git a/main/drivers/es8311.h b/main/drivers/es8311.h index 0cdda1e..09d4956 100644 --- a/main/drivers/es8311.h +++ b/main/drivers/es8311.h @@ -3,26 +3,40 @@ #include #include + +#define ES8311_BIT(pos) (1U << (pos)) +#define ES8311_FLD(pos, val) ((val) << (pos)) + // ---------------------- // I2C // ---------------------- #define ES8311_RESET_REG00 0x00 /*reset digital,csm,clock manager etc.*/ #define ES8311_RESET_CSM_OFF (0 << 7) -#define ES8311_RESET_CSM_ON (1 << 7) +#define ES8311_RESET_CSM_ON ES8311_BIT(7) #define ES8311_RESET_CSM_MSC_SLAVE (0 << 6) -#define ES8311_RESET_CSM_MSC_MASTER (1 << 6) +#define ES8311_RESET_CSM_MSC_MASTER ES8311_BIT(6) // #define ES8311_RESET_CSM_MSC_SLAVE (0 << 5) -// #define ES8311_RESET_CSM_MSC_MASTER (1 << 5) +// #define ES8311_RESET_CSM_MSC_MASTER ES8311_BIT(5) #define ES8311_RESET_DIGITAL_RUN (0 << 4) -#define ES8311_RESET_DIGITAL_RST (1 << 4) +#define ES8311_RESET_DIGITAL_RST ES8311_BIT(4) #define ES8311_RESET_CLOCK_MANAGER_RUN (0 << 3) -#define ES8311_RESET_CLOCK_MANAGER_RST (1 << 3) +#define ES8311_RESET_CLOCK_MANAGER_RST ES8311_BIT(3) #define ES8311_RESET_MASTER_RUN (0 << 2) -#define ES8311_RESET_MASTER_RST (1 << 2) +#define ES8311_RESET_MASTER_RST ES8311_BIT(2) #define ES8311_RESET_ADC_DIGITAL_RUN (0 << 1) -#define ES8311_RESET_ADC_DIGITAL_RST (1 << 1) -#define ES8311_RESET_DAC_DIGITAL_RUN (0 << 0) -#define ES8311_RESET_DAC_DIGITAL_RST (1 << 0) +#define ES8311_RESET_ADC_DIGITAL_RST ES8311_BIT(1) +#define ES8311_RESET_DAC_DIGITAL_RUN (0) +#define ES8311_RESET_DAC_DIGITAL_RST ES8311_BIT(0) + +typedef struct { + uint32_t b0; + uint32_t a1; + uint32_t a2; + uint32_t b1; + uint32_t b2; +} es8311_eq_t; + +void es8311_set_eq(const es8311_eq_t *eq); /* * Clock Scheme Register definition @@ -30,24 +44,40 @@ #define ES8311_CLK_MANAGER_REG01 \ 0x01 /* select clk src for mclk, enable clock for codec */ #define ES8311_CLK_MANAGER_REG01_MCLK_SEL_FROM_MCLK (0 << 7) -#define ES8311_CLK_MANAGER_REG01_MCLK_SEL_FROM_BCLK (1 << 7) +#define ES8311_CLK_MANAGER_REG01_MCLK_SEL_FROM_BCLK ES8311_BIT(7) #define ES8311_CLK_MANAGER_REG01_MCLK_INV_OFF (0 << 6) -#define ES8311_CLK_MANAGER_REG01_MCLK_INV_ON (1 << 6) +#define ES8311_CLK_MANAGER_REG01_MCLK_INV_ON ES8311_BIT(6) #define ES8311_CLK_MANAGER_REG01_MCLK_OFF (0 << 5) -#define ES8311_CLK_MANAGER_REG01_MCLK_ON (1 << 5) +#define ES8311_CLK_MANAGER_REG01_MCLK_ON ES8311_BIT(5) #define ES8311_CLK_MANAGER_REG01_BCLK_OFF (0 << 4) -#define ES8311_CLK_MANAGER_REG01_BCLK_ON (1 << 4) +#define ES8311_CLK_MANAGER_REG01_BCLK_ON ES8311_BIT(4) #define ES8311_CLK_MANAGER_REG02 0x02 /* clk divider and clk multiplier */ #define ES8311_CLK_MANAGER_REG03 0x03 /* adc fsmode and osr */ +#define ES8311_CLK_MANAGER_REG03_ADC_FSMODE_SINGLE_SPEED (0 << 6) +#define ES8311_CLK_MANAGER_REG03_ADC_FSMODE_DOUBLE_SPEED ES8311_BIT(6) +/* +ADC_OSR 5:0 ADC delta sigma over sample rate +0~14 – not use +15 – 60*fs(ss) / (ds not support) +16 – 64*fs(ss) / 32*fs(ds) (default) +... +31 – 124*fs(ss) / 62*fs(ds) +32 – 128*fs(ss) / 64*fs(ds) +... +63 – 252*fs(ss) / 126*fs(ds) + +*/ + + #define ES8311_CLK_MANAGER_REG04 0x04 /* dac osr */ #define ES8311_CLK_MANAGER_REG05 0x05 /* clk divier for adc and dac */ #define ES8311_CLK_MANAGER_REG06 0x06 /* bclk inverter and divider */ #define ES8311_CLK_MANAGER_REG06_CONTINUAL_BCLK (0 << 6) -#define ES8311_CLK_MANAGER_REG06_WHEN_DATA_TRANSFER_BCLK (1 << 6) +#define ES8311_CLK_MANAGER_REG06_WHEN_DATA_TRANSFER_BCLK ES8311_BIT(6) #define ES8311_CLK_MANAGER_REG06_NORMAL_BCLK (0 << 5) -#define ES8311_CLK_MANAGER_REG06_INVERT_BCLK (1 << 5) +#define ES8311_CLK_MANAGER_REG06_INVERT_BCLK ES8311_BIT(5) #define ES8311_CLK_MANAGER_REG06_DIV_BCLK_1 0x00 #define ES8311_CLK_MANAGER_REG06_DIV_BCLK_2 0x01 #define ES8311_CLK_MANAGER_REG06_DIV_BCLK_3 0x02 @@ -84,42 +114,42 @@ #define ES8311_CLK_MANAGER_REG07 0x07 /* tri-state, lrck divider */ #define ES8311_CLK_MANAGER_REG07_BCLK_LRCLK_NORMAL_MODE (0 << 5) -#define ES8311_CLK_MANAGER_REG07_BCLK_LRCLK_TRISTATE_MODE (1 << 5) +#define ES8311_CLK_MANAGER_REG07_BCLK_LRCLK_TRISTATE_MODE ES8311_BIT(5) #define ES8311_CLK_MANAGER_REG07_ADCDAT_NORMAL_MODE (0 << 4) -#define ES8311_CLK_MANAGER_REG07_ADCDAT_TRISTATE_MODE (1 << 4) +#define ES8311_CLK_MANAGER_REG07_ADCDAT_TRISTATE_MODE ES8311_BIT(4) #define ES8311_CLK_MANAGER_REG08 0x08 /* lrck divider */ /* * SDP */ #define ES8311_SDPIN_REG 0x09 #define ES8311_SDPIN_SEL_LEFT_TO_DAC (0 << 7) -#define ES8311_SDPIN_SEL_RIGHT_TO_DAC (1 << 7) +#define ES8311_SDPIN_SEL_RIGHT_TO_DAC ES8311_BIT(7) #define ES8311_SDPIN_UNMUTE (0 << 6) -#define ES8311_SDPIN_MUTE (1 << 6) +#define ES8311_SDPIN_MUTE ES8311_BIT(6) #define ES8311_SDPIN_LR_NORMAL_POLARITY (0 << 5) -#define ES8311_SDPIN_LR_INVERTED_POLARITY (1 << 5) +#define ES8311_SDPIN_LR_INVERTED_POLARITY ES8311_BIT(5) #define ES8311_SDPIN_WORD_24BIT (0 << 2) -#define ES8311_SDPIN_WORD_20BIT (1 << 2) +#define ES8311_SDPIN_WORD_20BIT ES8311_BIT(2) #define ES8311_SDPIN_WORD_18BIT (2 << 2) #define ES8311_SDPIN_WORD_16BIT (3 << 2) #define ES8311_SDPIN_WORD_32BIT (4 << 2) -#define ES8311_SDPIN_FORMAT_I2S (0 << 0) -#define ES8311_SDPIN_FORMAT_LEFT_JUSTIFY_SERIAL (1 << 0) -#define ES8311_SDPIN_FORMAT_PCM (3 << 0) +#define ES8311_SDPIN_FORMAT_I2S (0) +#define ES8311_SDPIN_FORMAT_LEFT_JUSTIFY_SERIAL ES8311_BIT(0) +#define ES8311_SDPIN_FORMAT_PCM (0) #define ES8311_SDPOUT_REG 0x0A #define ES8311_SDPOUT_UNMUTE (0 << 6) -#define ES8311_SDPOUT_MUTE (1 << 6) +#define ES8311_SDPOUT_MUTE ES8311_BIT(6) #define ES8311_SDPOUT_LR_NORMAL_POLARITY (0 << 5) -#define ES8311_SDPOUT_LR_INVERTED_POLARITY (1 << 5) +#define ES8311_SDPOUT_LR_INVERTED_POLARITY ES8311_BIT(5) #define ES8311_SDPOUT_WORD_24BIT (0 << 2) -#define ES8311_SDPOUT_WORD_20BIT (1 << 2) +#define ES8311_SDPOUT_WORD_20BIT ES8311_BIT(2) #define ES8311_SDPOUT_WORD_18BIT (2 << 2) #define ES8311_SDPOUT_WORD_16BIT (3 << 2) #define ES8311_SDPOUT_WORD_32BIT (4 << 2) -#define ES8311_SDPOUT_FORMAT_I2S (0 << 0) -#define ES8311_SDPOUT_FORMAT_LEFT_JUSTIFY_SERIAL (1 << 0) -#define ES8311_SDPOUT_FORMAT_PCM (3 << 0) +#define ES8311_SDPOUT_FORMAT_I2S (0) +#define ES8311_SDPOUT_FORMAT_LEFT_JUSTIFY_SERIAL ES8311_BIT(0) +#define ES8311_SDPOUT_FORMAT_PCM (0) /* * SYSTEM */ @@ -128,15 +158,15 @@ #define ES8311_SYSTEM_REG0D 0x0D /* system, power up/down */ #define ES8311_SYSTEM_REG0D_ANALOG_ENABLED (0 << 7) -#define ES8311_SYSTEM_REG0D_ANALOG_DISABLED (1 << 7) +#define ES8311_SYSTEM_REG0D_ANALOG_DISABLED ES8311_BIT(7) #define ES8311_SYSTEM_REG0D_ANALOG_BIAS_ENABLED (0 << 6) -#define ES8311_SYSTEM_REG0D_ANALOG_BIAS_DISABLED (1 << 6) +#define ES8311_SYSTEM_REG0D_ANALOG_BIAS_DISABLED ES8311_BIT(6) #define ES8311_SYSTEM_REG0D_ANALOG_ADC_BIAS_ENABLED (0 << 5) -#define ES8311_SYSTEM_REG0D_ANALOG_ADC_BIAS_DISABLED (1 << 5) +#define ES8311_SYSTEM_REG0D_ANALOG_ADC_BIAS_DISABLED ES8311_BIT(5) #define ES8311_SYSTEM_REG0D_ANALOG_ADC_REFERENCE_ENABLED (0 << 4) -#define ES8311_SYSTEM_REG0D_ANALOG_ADC_REFERENCE_DISABLED (1 << 4) +#define ES8311_SYSTEM_REG0D_ANALOG_ADC_REFERENCE_DISABLED ES8311_BIT(4) #define ES8311_SYSTEM_REG0D_ANALOG_DAC_REFERENCE_ENABLED (0 << 3) -#define ES8311_SYSTEM_REG0D_ANALOG_DAC_REFERENCE_DISABLED (1 << 3) +#define ES8311_SYSTEM_REG0D_ANALOG_DAC_REFERENCE_DISABLED ES8311_BIT(3) #define ES8311_SYSTEM_REG0D_VMID_POWER_DOWN 0x00 #define ES8311_SYSTEM_REG0D_VMID_START_NORMAL_SPEED 0x01 #define ES8311_SYSTEM_REG0D_VMID_NORMAL 0x02 @@ -145,31 +175,31 @@ #define ES8311_SYSTEM_REG0E 0x0E /* system, power up/down */ #define ES8311_SYSTEM_REG0E_PGA_ENABLE (0 << 6) -#define ES8311_SYSTEM_REG0E_PGA_DISABLE (1 << 6) +#define ES8311_SYSTEM_REG0E_PGA_DISABLE ES8311_BIT(6) #define ES8311_SYSTEM_REG0E_PDN_MOD_ENABLE (0 << 5) -#define ES8311_SYSTEM_REG0E_PDN_MOD_DISABLE (1 << 5) +#define ES8311_SYSTEM_REG0E_PDN_MOD_DISABLE ES8311_BIT(5) #define ES8311_SYSTEM_REG0E_MOD_NORMAL (0 << 4) -#define ES8311_SYSTEM_REG0E_MOD_RESET (1 << 4) +#define ES8311_SYSTEM_REG0E_MOD_RESET ES8311_BIT(4) #define ES8311_SYSTEM_REG0F 0x0F /* system, low power */ #define ES8311_SYSTEM_REG0F_DAC_NORMAL_MODE (0 << 7) -#define ES8311_SYSTEM_REG0F_DAC_LOW_POWER_MODE (1 << 7) +#define ES8311_SYSTEM_REG0F_DAC_LOW_POWER_MODE ES8311_BIT(7) #define ES8311_SYSTEM_REG0F_PGA_NORMAL_MODE (0 << 6) -#define ES8311_SYSTEM_REG0F_PGA_LOW_POWER_MODE (1 << 6) +#define ES8311_SYSTEM_REG0F_PGA_LOW_POWER_MODE ES8311_BIT(6) #define ES8311_SYSTEM_REG0F_PGA_OUTPUT_NORMAL_MODE (0 << 5) -#define ES8311_SYSTEM_REG0F_PGA_OUTPUT_LOW_POWER_MODE (1 << 5) +#define ES8311_SYSTEM_REG0F_PGA_OUTPUT_LOW_POWER_MODE ES8311_BIT(5) #define ES8311_SYSTEM_REG0F_VCMMOD_NORMAL_MODE (0 << 4) -#define ES8311_SYSTEM_REG0F_VCMMOD_LOW_POWER_MODE (1 << 4) +#define ES8311_SYSTEM_REG0F_VCMMOD_LOW_POWER_MODE ES8311_BIT(4) #define ES8311_SYSTEM_REG0F_ADC_REFERENCE_NORMAL_MODE (0 << 3) -#define ES8311_SYSTEM_REG0F_ADC_REFERENCE_LOW_POWER_MODE (1 << 3) +#define ES8311_SYSTEM_REG0F_ADC_REFERENCE_LOW_POWER_MODE ES8311_BIT(3) #define ES8311_SYSTEM_REG0F_DAC_REFERENCE_NORMAL_MODE (0 << 2) -#define ES8311_SYSTEM_REG0F_DAC_REFERENCE_LOW_POWER_MODE (1 << 2) +#define ES8311_SYSTEM_REG0F_DAC_REFERENCE_LOW_POWER_MODE ES8311_BIT(2) #define ES8311_SYSTEM_REG0F_FLASH_NORMAL_MODE (0 << 1) -#define ES8311_SYSTEM_REG0F_FLASH_LOW_POWER_MODE (1 << 1) -#define ES8311_SYSTEM_REG0F_INT1_NORMAL_MODE (0 << 0) -#define ES8311_SYSTEM_REG0F_INT1_LOW_POWER_MODE (1 << 0) +#define ES8311_SYSTEM_REG0F_FLASH_LOW_POWER_MODE ES8311_BIT(1) +#define ES8311_SYSTEM_REG0F_INT1_NORMAL_MODE (0) +#define ES8311_SYSTEM_REG0F_INT1_LOW_POWER_MODE ES8311_BIT(0) @@ -182,9 +212,9 @@ 0x14 /* system, select DMIC, select analog pga gain */ #define ES8311_SYSTEM_REG14_DMIC_OFF (0 << 6) -#define ES8311_SYSTEM_REG14_DMIC_AND_DMIC_SDA (1 << 6) +#define ES8311_SYSTEM_REG14_DMIC_AND_DMIC_SDA ES8311_BIT(6) #define ES8311_SYSTEM_REG14_NO_MIC (0 << 4) -#define ES8311_SYSTEM_REG14_MIC1 (1 << 4) +#define ES8311_SYSTEM_REG14_MIC1 ES8311_BIT(4) #define ES8311_SYSTEM_REG14_MIC2 (2 << 4) #define ES8311_SYSTEM_REG14_MIC1_MIC2 (3 << 4) #define ES8311_SYSTEM_REG14_GAIN_0DB 0 @@ -198,6 +228,8 @@ #define ES8311_SYSTEM_REG14_GAIN_24DB 8 #define ES8311_SYSTEM_REG14_GAIN_27DB 9 #define ES8311_SYSTEM_REG14_GAIN_30DB 10 +#define ES8311_SYSTEM_REG14_DMIC_CLOCK_POSITIVE (0) +#define ES8311_SYSTEM_REG14_DMIC_CLOCK_NEGATIVE ES8311_BIT(0) @@ -205,14 +237,44 @@ * ADC */ #define ES8311_ADC_REG15 0x15 /* ADC, adc ramp rate, dmic sense */ +#define ES8311_ADC_REG15_RAMPRATE_DISABLE (0x00 << 4) +#define ES8311_ADC_REG15_RAMPRATE_0_25_4LRCK (0x01 << 4) +#define ES8311_ADC_REG15_RAMPRATE_0_25_8LRCK (0x02 << 4) +#define ES8311_ADC_REG15_RAMPRATE_0_25_16LRCK (0x03 << 4) +#define ES8311_ADC_REG15_RAMPRATE_0_25_32LRCK (0x04 << 4) +#define ES8311_ADC_REG15_RAMPRATE_0_25_64LRCK (0x05 << 4) +#define ES8311_ADC_REG15_RAMPRATE_0_25_128LRCK (0x06 << 4) +#define ES8311_ADC_REG15_RAMPRATE_0_25_256LRCK (0x07 << 4) +#define ES8311_ADC_REG15_RAMPRATE_0_25_512LRCK (0x08 << 4) +#define ES8311_ADC_REG15_RAMPRATE_0_25_1024LRCK (0x09 << 4) +#define ES8311_ADC_REG15_RAMPRATE_0_25_2048LRCK (0x0a << 4) +#define ES8311_ADC_REG15_RAMPRATE_0_25_4096LRCK (0x0b << 4) +#define ES8311_ADC_REG15_RAMPRATE_0_25_8192LRCK (0x0c << 4) +#define ES8311_ADC_REG15_RAMPRATE_0_25_16384LRCK (0x0d << 4) +#define ES8311_ADC_REG15_RAMPRATE_0_25_32768LRCK (0x0e << 4) +#define ES8311_ADC_REG15_RAMPRATE_0_25_65536LRCK (0x0f << 4) + + + #define ES8311_ADC_REG16 0x16 /* ADC */ -#define ES8311_ADC_REG16_ADC_RAM_CLR (1 << 3) +#define ES8311_ADC_REG16_ADC_GAIN_0DB 0x00 +#define ES8311_ADC_REG16_ADC_GAIN_6DB 0x01 +#define ES8311_ADC_REG16_ADC_GAIN_12DB 0x02 +#define ES8311_ADC_REG16_ADC_GAIN_18DB 0x03 +#define ES8311_ADC_REG16_ADC_GAIN_24DB 0x04 +#define ES8311_ADC_REG16_ADC_GAIN_30DB 0x05 +#define ES8311_ADC_REG16_ADC_GAIN_36DB 0x06 +#define ES8311_ADC_REG16_ADC_GAIN_42DB 0x07 + + + +#define ES8311_ADC_REG16_ADC_RAM_CLR ES8311_BIT(3) #define ES8311_ADC_REG17 0x17 /* ADC, volume */ #define ES8311_ADC_REG18 0x18 /* ADC, alc enable and winsize */ #define ES8311_ADC_REG18_AUTO_LEVEL_CONTROL_DISABLE (0 << 7) -#define ES8311_ADC_REG18_AUTO_LEVEL_CONTROL_ENABLE (1 << 7) +#define ES8311_ADC_REG18_AUTO_LEVEL_CONTROL_ENABLE ES8311_BIT(7) #define ES8311_ADC_REG18_AUTO_MUTE_DISABLE (0 << 6) -#define ES8311_ADC_REG18_AUTO_MUTE_ENABLE (1 << 6) +#define ES8311_ADC_REG18_AUTO_MUTE_ENABLE ES8311_BIT(6) #define ES8311_ADC_REG18_0_25DB_PER_2LRCK 0x00 #define ES8311_ADC_REG18_0_25DB_PER_4LRCK 0x01 #define ES8311_ADC_REG18_0_25DB_PER_8LRCK 0x02 @@ -249,16 +311,16 @@ #define ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_6_6DB (0x0E << 4) #define ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_6_0DB (0x0F << 4) -#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_30_1DB (0x00 << 0) -#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_24_1DB (0x01 << 0) -#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_20_6DB (0x02 << 0) -#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_18_1DB (0x03 << 0) -#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_16_1DB (0x04 << 0) -#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_14_5DB (0x05 << 0) -#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_13_2DB (0x06 << 0) -#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_12_0DB (0x07 << 0) -#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_11_0DB (0x08 << 0) -#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_10_1DB (0x09 << 0) +#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_30_1DB (0x00) +#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_24_1DB (0x00) +#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_20_6DB (0x00) +#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_18_1DB (0x00) +#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_16_1DB (0x00) +#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_14_5DB (0x00) +#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_13_2DB (0x00) +#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_12_0DB (0x00) +#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_11_0DB (0x00) +#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_10_1DB (0x00) #define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_9_3DB (0x0A << 0) #define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_8_5DB (0x0B << 0) #define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_7_8DB (0x0C << 0) @@ -285,16 +347,16 @@ #define ES8311_ADC_REG1A_AUTOMUTE_30720_SAMPLES (0x0E << 4) #define ES8311_ADC_REG1A_AUTOMUTE_32768_SAMPLES (0x0F << 4) -#define ES8311_ADC_REG1A_AUTOMUTE_NEG_96DB (0x00 << 0) -#define ES8311_ADC_REG1A_AUTOMUTE_NEG_90DB (0x01 << 0) -#define ES8311_ADC_REG1A_AUTOMUTE_NEG_84DB (0x02 << 0) -#define ES8311_ADC_REG1A_AUTOMUTE_NEG_78DB (0x03 << 0) -#define ES8311_ADC_REG1A_AUTOMUTE_NEG_72DB (0x04 << 0) -#define ES8311_ADC_REG1A_AUTOMUTE_NEG_66DB (0x05 << 0) -#define ES8311_ADC_REG1A_AUTOMUTE_NEG_60DB (0x06 << 0) -#define ES8311_ADC_REG1A_AUTOMUTE_NEG_54DB (0x07 << 0) -#define ES8311_ADC_REG1A_AUTOMUTE_NEG_51DB (0x08 << 0) -#define ES8311_ADC_REG1A_AUTOMUTE_NEG_48DB (0x09 << 0) +#define ES8311_ADC_REG1A_AUTOMUTE_NEG_96DB (0x00) +#define ES8311_ADC_REG1A_AUTOMUTE_NEG_90DB (0x00) +#define ES8311_ADC_REG1A_AUTOMUTE_NEG_84DB (0x00) +#define ES8311_ADC_REG1A_AUTOMUTE_NEG_78DB (0x00) +#define ES8311_ADC_REG1A_AUTOMUTE_NEG_72DB (0x00) +#define ES8311_ADC_REG1A_AUTOMUTE_NEG_66DB (0x00) +#define ES8311_ADC_REG1A_AUTOMUTE_NEG_60DB (0x00) +#define ES8311_ADC_REG1A_AUTOMUTE_NEG_54DB (0x00) +#define ES8311_ADC_REG1A_AUTOMUTE_NEG_51DB (0x00) +#define ES8311_ADC_REG1A_AUTOMUTE_NEG_48DB (0x00) #define ES8311_ADC_REG1A_AUTOMUTE_NEG_45DB (0x0A << 0) #define ES8311_ADC_REG1A_AUTOMUTE_NEG_42DB (0x0B << 0) #define ES8311_ADC_REG1A_AUTOMUTE_NEG_39DB (0x0C << 0) @@ -307,39 +369,140 @@ // bits 4:0 have ADCHPF stage 1 coefficient - reg1b #define ES8311_ADC_REG1C 0x1C /* ADC, equalizer, hpf s2 */ #define ES8311_ADC_REG1C_ADCEQ_NORMAL (0 << 6) -#define ES8311_ADC_REG1C_ADCEQ_BYPASS (1 << 6) +#define ES8311_ADC_REG1C_ADCEQ_BYPASS ES8311_BIT(6) #define ES8311_ADC_REG1C_HPF_FREEZE_OFFSET (0 << 5) -#define ES8311_ADC_REG1C_HPF_DYNAMIC_HPF (1 << 5) +#define ES8311_ADC_REG1C_HPF_DYNAMIC_HPF ES8311_BIT(5) // bits 4:0 have ADCHPF stage 2 coefficient - reg1c /* reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ -reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ -reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ -reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ -reg1d - ADCEQ_A1[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ -reg1d - ADCEQ_A1[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ -reg1d - ADCEQ_A1[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ -reg1d - ADCEQ_A1[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ -reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ -reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ -reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ -reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ -reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ +reg1e - ADCEQ_B0[23:16] - bit 7:0 30-bit B0 coefficient for ADCEQ +reg1f - ADCEQ_B0[15:8] - bit 7:0 30-bit B0 coefficient for ADCEQ +reg20 - ADCEQ_B0[7:0] - bit 7:0 30-bit B0 coefficient for ADCEQ + +reg21 - ADCEQ_A1[29:24] - bit 5:0 30-bit A1 coefficient for ADCEQ +reg22 - ADCEQ_A1[23:16] - bit 7:0 30-bit A1 coefficient for ADCEQ +reg23 - ADCEQ_A1[15:8] - bit 7:0 30-bit A1 coefficient for ADCEQ +reg24 - ADCEQ_A1[7:0] - bit 7:0 30-bit A1 coefficient for ADCEQ + +reg25 - ADCEQ_A2[29:24] - bit 5:0 30-bit A2 coefficient for ADCEQ +reg26 - ADCEQ_A2[23:16] - bit 7:0 30-bit A2 coefficient for ADCEQ +reg27 - ADCEQ_A2[15:8] - bit 7:0 30-bit A2 coefficient for ADCEQ +reg28 - ADCEQ_A2[7:0] - bit 7:0 30-bit A2 coefficient for ADCEQ + +reg29 - ADCEQ_B1[29:24] - bit 5:0 30-bit B1 coefficient for ADCEQ +reg2a - ADCEQ_B1[23:16] - bit 7:0 30-bit B1 coefficient for ADCEQ +reg2b - ADCEQ_B1[15:8] - bit 7:0 30-bit B1 coefficient for ADCEQ +reg2c - ADCEQ_B1[7:0] - bit 7:0 30-bit B1 coefficient for ADCEQ + +reg2d - ADCEQ_B2[29:24] - bit 5:0 30-bit B1 coefficient for ADCEQ +reg2e - ADCEQ_B2[23:16] - bit 7:0 30-bit B1 coefficient for ADCEQ +reg2f - ADCEQ_B2[15:8] - bit 7:0 30-bit B1 coefficient for ADCEQ +reg30 - ADCEQ_B2[7:0] - bit 7:0 30-bit B1 coefficient for ADCEQ */ /* * DAC */ #define ES8311_DAC_REG31 0x31 /* DAC, mute */ +#define ES8311_DAC_REG31_MUTE_TO8 (0 << 7) +#define ES8311_DAC_REG31_MUTE_TO7_9 ES8311_BIT(7) +#define ES8311_DAC_REG31_DSM_UNMUTE (0 << 6) +#define ES8311_DAC_REG31_DSM_MUTE ES8311_BIT(6) +#define ES8311_DAC_REG31_DEM_UNMUTE (0 << 5) +#define ES8311_DAC_REG31_DEM_MUTE ES8311_BIT(5) + + + #define ES8311_DAC_REG32 0x32 /* DAC, volume */ #define ES8311_DAC_REG33 0x33 /* DAC, offset */ #define ES8311_DAC_REG34 0x34 /* DAC, drc enable, drc winsize */ +#define ES8311_DAC_REG34_DRC_DISABLE (0 << 7) +#define ES8311_DAC_REG34_DRC_ENABLE ES8311_BIT(7) +#define ES8311_DAC_REG34_DRC_WINSIZE_DISABLE (0x00) +#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_4LRCK (0x00) +#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_8LRCK (0x00) +#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_16LRCK (0x00) +#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_32LRCK (0x00) +#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_64LRCK (0x00) +#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_128LRCK (0x00) +#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_256LRCK (0x00) +#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_512LRCK (0x00) +#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_1024LRCK (0x00) +#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_2048LRCK (0x0a << 0) +#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_4096LRCK (0x0b << 0) +#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_8192LRCK (0x0c << 0) +#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_16384LRCK (0x0d << 0) +#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_32768LRCK (0x0e << 0) +#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_65536LRCK (0x0f << 0) + #define ES8311_DAC_REG35 0x35 /* DAC, drc maxlevel, minilevel */ +#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_30_1DB (0x00 << 4) +#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_24_1DB (0x01 << 4) +#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_20_6DB (0x02 << 4) +#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_18_1DB (0x03 << 4) +#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_16_1DB (0x04 << 4) +#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_14_5DB (0x05 << 4) +#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_13_2DB (0x06 << 4) +#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_12_0DB (0x07 << 4) +#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_11_0DB (0x08 << 4) +#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_10_1DB (0x09 << 4) +#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_9_3DB (0x0A << 4) +#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_8_5DB (0x0B << 4) +#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_7_8DB (0x0C << 4) +#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_7_2DB (0x0D << 4) +#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_6_6DB (0x0E << 4) +#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_6_0DB (0x0F << 4) + +#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_30_1DB (0x00) +#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_24_1DB (0x00) +#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_20_6DB (0x00) +#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_18_1DB (0x00) +#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_16_1DB (0x00) +#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_14_5DB (0x00) +#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_13_2DB (0x00) +#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_12_0DB (0x00) +#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_11_0DB (0x00) +#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_10_1DB (0x00) +#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_9_3DB (0x0A << 0) +#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_8_5DB (0x0B << 0) +#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_7_8DB (0x0C << 0) +#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_7_2DB (0x0D << 0) +#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_6_6DB (0x0E << 0) +#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_6_0DB (0x0F << 0) + + #define ES8311_DAC_REG37 0x37 /* DAC, ramprate */ +#define ES8311_DAC_REG37_RAMPRATE_DISABLE (0x00 << 4) +#define ES8311_DAC_REG37_RAMPRATE_0_25_4LRCK (0x01 << 4) +#define ES8311_DAC_REG37_RAMPRATE_0_25_8LRCK (0x02 << 4) +#define ES8311_DAC_REG37_RAMPRATE_0_25_16LRCK (0x03 << 4) +#define ES8311_DAC_REG37_RAMPRATE_0_25_32LRCK (0x04 << 4) +#define ES8311_DAC_REG37_RAMPRATE_0_25_64LRCK (0x05 << 4) +#define ES8311_DAC_REG37_RAMPRATE_0_25_128LRCK (0x06 << 4) +#define ES8311_DAC_REG37_RAMPRATE_0_25_256LRCK (0x07 << 4) +#define ES8311_DAC_REG37_RAMPRATE_0_25_512LRCK (0x08 << 4) +#define ES8311_DAC_REG37_RAMPRATE_0_25_1024LRCK (0x09 << 4) +#define ES8311_DAC_REG37_RAMPRATE_0_25_2048LRCK (0x0a << 4) +#define ES8311_DAC_REG37_RAMPRATE_0_25_4096LRCK (0x0b << 4) +#define ES8311_DAC_REG37_RAMPRATE_0_25_8192LRCK (0x0c << 4) +#define ES8311_DAC_REG37_RAMPRATE_0_25_16384LRCK (0x0d << 4) +#define ES8311_DAC_REG37_RAMPRATE_0_25_32768LRCK (0x0e << 4) +#define ES8311_DAC_REG37_RAMPRATE_0_25_65536LRCK (0x0f << 4) /* *GPIO */ #define ES8311_GPIO_REG44 0x44 /* GPIO, dac2adc for test */ +#define ES8311_GPIO_REG44_ADCDAT_SEL_NO_LOOPBACK (0 << 7) +#define ES8311_GPIO_REG44_ADCDAT_ADC_TO_DAC ES8311_BIT(7) +#define ES8311_GPIO_REG44_ADCDAT_SEL_ADC_ADC (0x00 << 4) +#define ES8311_GPIO_REG44_ADCDAT_SEL_ADC_0 (0x01 << 4) +#define ES8311_GPIO_REG44_ADCDAT_SEL_0_ADC (0x02 << 4) +#define ES8311_GPIO_REG44_ADCDAT_SEL_0_0 (0x03 << 4) +#define ES8311_GPIO_REG44_ADCDAT_SEL_DACL_ADC (0x04 << 4) +#define ES8311_GPIO_REG44_ADCDAT_SEL_ADC_DACR (0x05 << 4) +#define ES8311_GPIO_REG44_ADCDAT_SEL_DACL_DACR (0x06 << 4) +//#define ES8311_GPIO_REG44_ADCDAT_SEL_NA (0x07 << 4) + #define ES8311_GP_REG45 0x45 /* GP CONTROL */ /* * CHIP diff --git a/main/drivers/i2s.c b/main/drivers/i2s.c index c674c1b..b9c205f 100644 --- a/main/drivers/i2s.c +++ b/main/drivers/i2s.c @@ -1,4 +1,5 @@ #include "i2s.h" +#include "hal/i2s_types.h" #include "pins.h" i2s_chan_handle_t i2s_tx; @@ -10,7 +11,7 @@ void audio_i2s_init(void) { i2s_new_channel(&cfg, &i2s_tx, &i2s_rx); i2s_std_config_t stdcfg = { - .clk_cfg = I2S_STD_CLK_DEFAULT_CONFIG(44100), + .clk_cfg = I2S_STD_CLK_DEFAULT_CONFIG(48000), .slot_cfg = I2S_STD_MSB_SLOT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_16BIT, I2S_SLOT_MODE_STEREO), diff --git a/main/main.c b/main/main.c index 3079ad3..4cdc78b 100644 --- a/main/main.c +++ b/main/main.c @@ -28,6 +28,8 @@ void app_main(void) { i2c_init(BUS_I2C_SDA, BUS_I2C_SCL); ws2812_init(); + audio_i2s_init(); + vTaskDelay(pdMS_TO_TICKS(10)); es8311_init(); tca8418_init(); if (!bmi270_init()) { @@ -69,7 +71,7 @@ void app_main(void) { printf("%s\n", buf); st7789_draw_string(30, 30, buf, 0x07E0, 0x0000, true, fontHitachi); - //audio_test_tone(); + audio_beep(); } bmi270_data_t bmiData;