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Author SHA1 Message Date
Bruno Rybársky
77c9d4a4d5 update 2026-05-18 22:59:45 +02:00
Bruno Rybársky
aed00ceda2 finish es8311 manual 2026-05-11 18:55:56 +02:00
12 changed files with 1489 additions and 211 deletions
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dependencies.lock
+12 -1
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@@ -1,4 +1,14 @@
dependencies: dependencies:
espressif/esp_codec_dev:
component_hash: 896c67360ae1f8dedaf8a53dfe48c015317fa455f061a5165307892296990028
dependencies:
- name: idf
require: private
version: '>=4.0'
source:
registry_url: https://components.espressif.com/
type: service
version: 1.5.10
espressif/esp_tinyusb: espressif/esp_tinyusb:
component_hash: 8e57a14ac14d8e4d4588b5b9222977b96475323bcebae3c838919bb4e8587887 component_hash: 8e57a14ac14d8e4d4588b5b9222977b96475323bcebae3c838919bb4e8587887
dependencies: dependencies:
@@ -49,9 +59,10 @@ dependencies:
type: idf type: idf
version: 6.0.0 version: 6.0.0
direct_dependencies: direct_dependencies:
- espressif/esp_codec_dev
- espressif/esp_tinyusb - espressif/esp_tinyusb
- espressif/led_strip - espressif/led_strip
- idf - idf
manifest_hash: 4367414e2d87717eea085884b361169910107724286ca676c237567381b84306 manifest_hash: ef62d5f630d2fef4437689964fe6bd9bff7fe496aa1d7a7d95e6cd6db62ff7c7
target: esp32s3 target: esp32s3
version: 3.0.0 version: 3.0.0
main/CMakeLists.txt
+4
View File
@@ -23,6 +23,10 @@ idf_component_register(SRCS "main.c"
"drivers/fonts.c" "drivers/fonts.c"
"drivers/st7789.c" "drivers/st7789.c"
"drivers/st7789.h" "drivers/st7789.h"
"drivers/servergprs.c"
"drivers/servergprs.h"
"drivers/sim800.c"
"drivers/sim800.h"
"drivers/tca8418.c" "drivers/tca8418.c"
"drivers/tca8418.h" "drivers/tca8418.h"
"drivers/ws2812.c" "drivers/ws2812.c"
main/drivers/es8311.c
+60 -114
View File
@@ -11,6 +11,8 @@
#include <math.h> #include <math.h>
#include <stdint.h> #include <stdint.h>
#define TAG "ES8311"
i2c_master_dev_handle_t es8311_i2c_dev; i2c_master_dev_handle_t es8311_i2c_dev;
int es8311_write(uint8_t reg, uint8_t val) { int es8311_write(uint8_t reg, uint8_t val) {
@@ -22,28 +24,29 @@ int es8311_write(uint8_t reg, uint8_t val) {
return 0; return 0;
} }
static uint8_t db_to_es8311_vol(float db) {
if (db < -95.5f)
db = -95.5f;
if (db > 32.0f)
db = 32.0f;
// ES8311 typically uses 0.5 dB steps
int v = (int)((db + 95.5f) * 2.0f);
if (v < 0)
v = 0;
if (v > 255)
v = 255;
return (uint8_t)v;
}
void es8311_set_dac_volume(float vol) { void es8311_set_dac_volume(float vol) {
if (vol < -95.5f) { es8311_write(ES8311_DAC_REG32, db_to_es8311_vol(vol));
vol = -95.5f;
}
if (vol > 32) {
vol = 32;
}
vol *= 2;
uint8_t volByte = vol;
es8311_write(ES8311_DAC_REG32, volByte);
} }
void es8311_set_adc_volume(float vol) { void es8311_set_adc_volume(float vol) {
if (vol < -95.5f) { es8311_write(ES8311_ADC_REG17, db_to_es8311_vol(vol));
vol = -95.5f;
}
if (vol > 32) {
vol = 32;
}
vol *= 2;
uint8_t volByte = vol;
es8311_write(ES8311_ADC_REG17, volByte);
} }
uint8_t es8311_read(uint8_t reg) { uint8_t es8311_read(uint8_t reg) {
@@ -56,6 +59,34 @@ uint8_t es8311_read(uint8_t reg) {
return val; return val;
} }
static void es8311_write_eq_coeff(uint8_t reg_base, uint32_t coeff) {
coeff &= 0x3FFFFFFF;
es8311_write(reg_base + 0, (uint8_t)((coeff >> 24) & 0x3F));
es8311_write(reg_base + 1, (uint8_t)(coeff >> 16));
es8311_write(reg_base + 2, (uint8_t)(coeff >> 8));
es8311_write(reg_base + 3, (uint8_t)(coeff));
}
void es8311_set_eq(const es8311_eq_t *eq) {
if (!eq)
return;
// B0
es8311_write_eq_coeff(0x1D, eq->b0);
// A1
es8311_write_eq_coeff(0x21, eq->a1);
// A2
es8311_write_eq_coeff(0x25, eq->a2);
// B1
es8311_write_eq_coeff(0x29, eq->b1);
// B2
es8311_write_eq_coeff(0x2D, eq->b2);
}
void es8311_init(void) { void es8311_init(void) {
printf("ES8311: Starting initialization...\n"); printf("ES8311: Starting initialization...\n");
@@ -70,104 +101,20 @@ void es8311_init(void) {
return; return;
} }
es8311_write(ES8311_SDPIN_REG, // Reset sequence
ES8311_SDPIN_FORMAT_I2S | ES8311_SDPIN_WORD_24BIT | es8311_write(ES8311_RESET_REG00, 0x1F);
ES8311_SDPIN_LR_NORMAL_POLARITY | ES8311_SDPIN_UNMUTE | vTaskDelay(pdMS_TO_TICKS(20));
ES8311_SDPIN_SEL_LEFT_TO_DAC); es8311_write(ES8311_RESET_REG00, 0x00);
es8311_write(ES8311_RESET_REG00, 0x80); // Power-on command
es8311_write(ES8311_SDPOUT_REG,
ES8311_SDPOUT_FORMAT_I2S | ES8311_SDPOUT_WORD_24BIT |
ES8311_SDPOUT_LR_NORMAL_POLARITY | ES8311_SDPOUT_UNMUTE);
es8311_write(ES8311_RESET_REG00,
ES8311_RESET_CSM_MSC_SLAVE | ES8311_RESET_CSM_ON);
es8311_write(ES8311_CLK_MANAGER_REG07,
ES8311_CLK_MANAGER_REG07_ADCDAT_NORMAL_MODE |
ES8311_CLK_MANAGER_REG07_BCLK_LRCLK_NORMAL_MODE);
es8311_write(ES8311_CLK_MANAGER_REG01, es8311_write(ES8311_CLK_MANAGER_REG01,
ES8311_CLK_MANAGER_REG01_MCLK_INV_OFF |
ES8311_CLK_MANAGER_REG01_MCLK_OFF |
ES8311_CLK_MANAGER_REG01_MCLK_SEL_FROM_BCLK | ES8311_CLK_MANAGER_REG01_MCLK_SEL_FROM_BCLK |
ES8311_CLK_MANAGER_REG01_BCLK_OFF); 0x3F
);
// mclk 12.288 MHz LRCK 48kHz
es8311_write(ES8311_CLK_MANAGER_REG02, 0x00);
es8311_write(ES8311_CLK_MANAGER_REG03, 0x10);
es8311_write(ES8311_CLK_MANAGER_REG04, 0x10);
es8311_write(ES8311_CLK_MANAGER_REG05, 0x00);
es8311_write(ES8311_ADC_REG16, 0x04); // 24 db gain
// off in slave mode, we dont care
es8311_write(ES8311_CLK_MANAGER_REG06, es8311_write(ES8311_CLK_MANAGER_REG06,
ES8311_CLK_MANAGER_REG06_CONTINUAL_BCLK |
ES8311_CLK_MANAGER_REG06_NORMAL_BCLK | ES8311_CLK_MANAGER_REG06_NORMAL_BCLK |
ES8311_CLK_MANAGER_REG06_DIV_BCLK_3); ES8311_CLK_MANAGER_REG06_CONTINUAL_BCLK
// lrck divider is ignored, since we are in slave mode
es8311_write(ES8311_RESET_REG00,
ES8311_RESET_CSM_MSC_SLAVE | ES8311_RESET_CSM_ON |
ES8311_RESET_DIGITAL_RUN | ES8311_RESET_CLOCK_MANAGER_RUN |
ES8311_RESET_MASTER_RUN | ES8311_RESET_ADC_DIGITAL_RUN |
ES8311_RESET_DAC_DIGITAL_RUN);
es8311_write(ES8311_SYSTEM_REG0D,
ES8311_SYSTEM_REG0D_ANALOG_ENABLED |
ES8311_SYSTEM_REG0D_ANALOG_BIAS_ENABLED |
ES8311_SYSTEM_REG0D_ANALOG_ADC_BIAS_ENABLED |
ES8311_SYSTEM_REG0D_ANALOG_ADC_REFERENCE_ENABLED |
ES8311_SYSTEM_REG0D_ANALOG_DAC_REFERENCE_ENABLED |
ES8311_SYSTEM_REG0D_VMID_START_NORMAL_SPEED);
es8311_write(ES8311_SYSTEM_REG0D,
ES8311_SYSTEM_REG0D_ANALOG_ENABLED |
ES8311_SYSTEM_REG0D_ANALOG_BIAS_ENABLED |
ES8311_SYSTEM_REG0D_ANALOG_ADC_BIAS_ENABLED |
ES8311_SYSTEM_REG0D_ANALOG_ADC_REFERENCE_ENABLED |
ES8311_SYSTEM_REG0D_ANALOG_DAC_REFERENCE_ENABLED |
ES8311_SYSTEM_REG0D_VMID_NORMAL);
es8311_write(ES8311_SYSTEM_REG0F,
ES8311_SYSTEM_REG0F_DAC_NORMAL_MODE |
ES8311_SYSTEM_REG0F_PGA_NORMAL_MODE |
ES8311_SYSTEM_REG0F_PGA_OUTPUT_NORMAL_MODE |
ES8311_SYSTEM_REG0F_VCMMOD_NORMAL_MODE |
ES8311_SYSTEM_REG0F_ADC_REFERENCE_NORMAL_MODE |
ES8311_SYSTEM_REG0F_DAC_REFERENCE_NORMAL_MODE |
ES8311_SYSTEM_REG0F_FLASH_NORMAL_MODE |
ES8311_SYSTEM_REG0F_INT1_NORMAL_MODE);
es8311_write(ES8311_SYSTEM_REG0E,
ES8311_SYSTEM_REG0E_PGA_ENABLE |
ES8311_SYSTEM_REG0E_PDN_MOD_ENABLE |
ES8311_SYSTEM_REG0E_MOD_NORMAL
);
es8311_write(ES8311_SYSTEM_REG14,
ES8311_SYSTEM_REG14_DMIC_OFF |
ES8311_SYSTEM_REG14_MIC1 |
ES8311_SYSTEM_REG14_GAIN_30DB
);
es8311_write(ES8311_ADC_REG1C,
ES8311_ADC_REG1C_HPF_DYNAMIC_HPF |
ES8311_ADC_REG1C_ADCEQ_BYPASS
);
es8311_write(ES8311_ADC_REG18,
ES8311_ADC_REG18_AUTO_LEVEL_CONTROL_ENABLE |
ES8311_ADC_REG18_AUTO_MUTE_DISABLE |
ES8311_ADC_REG18_0_25DB_PER_65536LRCK
);
es8311_write(ES8311_ADC_REG19,
ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_30_1DB |
ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_6_0DB
);
es8311_write(ES8311_ADC_REG1A,
ES8311_ADC_REG1A_AUTOMUTE_NEG_96DB |
ES8311_ADC_REG1A_AUTOMUTE_32768_SAMPLES
); );
} }
@@ -212,9 +159,9 @@ void audio_beep(void) {
} }
void audio_test_tone(void) { void audio_test_tone(void) {
const int sample_rate = 44100; const int sample_rate = 48000;
const int duration_ms = 1000; const int duration_ms = 100;
const int freq_hz = 440; // A4 note const int freq_hz = 1000; // A4 note
const int num_samples = (sample_rate * duration_ms) / 1000; const int num_samples = (sample_rate * duration_ms) / 1000;
int16_t *buf = malloc(num_samples * 2 * sizeof(int16_t)); int16_t *buf = malloc(num_samples * 2 * sizeof(int16_t));
@@ -230,7 +177,6 @@ void audio_test_tone(void) {
buf[i * 2 + 1] = sample; // Right buf[i * 2 + 1] = sample; // Right
} }
printf("Playing 440Hz tone for 1 second...\n");
audio_write(buf, num_samples * 2); audio_write(buf, num_samples * 2);
free(buf); free(buf);
} }
main/drivers/es8311.h
+249 -86
View File
@@ -3,26 +3,40 @@
#include <stddef.h> #include <stddef.h>
#include <stdint.h> #include <stdint.h>
#define ES8311_BIT(pos) (1U << (pos))
#define ES8311_FLD(pos, val) ((val) << (pos))
// ---------------------- // ----------------------
// I2C // I2C
// ---------------------- // ----------------------
#define ES8311_RESET_REG00 0x00 /*reset digital,csm,clock manager etc.*/ #define ES8311_RESET_REG00 0x00 /*reset digital,csm,clock manager etc.*/
#define ES8311_RESET_CSM_OFF (0 << 7) #define ES8311_RESET_CSM_OFF (0 << 7)
#define ES8311_RESET_CSM_ON (1 << 7) #define ES8311_RESET_CSM_ON ES8311_BIT(7)
#define ES8311_RESET_CSM_MSC_SLAVE (0 << 6) #define ES8311_RESET_CSM_MSC_SLAVE (0 << 6)
#define ES8311_RESET_CSM_MSC_MASTER (1 << 6) #define ES8311_RESET_CSM_MSC_MASTER ES8311_BIT(6)
// #define ES8311_RESET_CSM_MSC_SLAVE (0 << 5) // #define ES8311_RESET_CSM_MSC_SLAVE (0 << 5)
// #define ES8311_RESET_CSM_MSC_MASTER (1 << 5) // #define ES8311_RESET_CSM_MSC_MASTER ES8311_BIT(5)
#define ES8311_RESET_DIGITAL_RUN (0 << 4) #define ES8311_RESET_DIGITAL_RUN (0 << 4)
#define ES8311_RESET_DIGITAL_RST (1 << 4) #define ES8311_RESET_DIGITAL_RST ES8311_BIT(4)
#define ES8311_RESET_CLOCK_MANAGER_RUN (0 << 3) #define ES8311_RESET_CLOCK_MANAGER_RUN (0 << 3)
#define ES8311_RESET_CLOCK_MANAGER_RST (1 << 3) #define ES8311_RESET_CLOCK_MANAGER_RST ES8311_BIT(3)
#define ES8311_RESET_MASTER_RUN (0 << 2) #define ES8311_RESET_MASTER_RUN (0 << 2)
#define ES8311_RESET_MASTER_RST (1 << 2) #define ES8311_RESET_MASTER_RST ES8311_BIT(2)
#define ES8311_RESET_ADC_DIGITAL_RUN (0 << 1) #define ES8311_RESET_ADC_DIGITAL_RUN (0 << 1)
#define ES8311_RESET_ADC_DIGITAL_RST (1 << 1) #define ES8311_RESET_ADC_DIGITAL_RST ES8311_BIT(1)
#define ES8311_RESET_DAC_DIGITAL_RUN (0 << 0) #define ES8311_RESET_DAC_DIGITAL_RUN (0)
#define ES8311_RESET_DAC_DIGITAL_RST (1 << 0) #define ES8311_RESET_DAC_DIGITAL_RST ES8311_BIT(0)
typedef struct {
uint32_t b0;
uint32_t a1;
uint32_t a2;
uint32_t b1;
uint32_t b2;
} es8311_eq_t;
void es8311_set_eq(const es8311_eq_t *eq);
/* /*
* Clock Scheme Register definition * Clock Scheme Register definition
@@ -30,24 +44,40 @@
#define ES8311_CLK_MANAGER_REG01 \ #define ES8311_CLK_MANAGER_REG01 \
0x01 /* select clk src for mclk, enable clock for codec */ 0x01 /* select clk src for mclk, enable clock for codec */
#define ES8311_CLK_MANAGER_REG01_MCLK_SEL_FROM_MCLK (0 << 7) #define ES8311_CLK_MANAGER_REG01_MCLK_SEL_FROM_MCLK (0 << 7)
#define ES8311_CLK_MANAGER_REG01_MCLK_SEL_FROM_BCLK (1 << 7) #define ES8311_CLK_MANAGER_REG01_MCLK_SEL_FROM_BCLK ES8311_BIT(7)
#define ES8311_CLK_MANAGER_REG01_MCLK_INV_OFF (0 << 6) #define ES8311_CLK_MANAGER_REG01_MCLK_INV_OFF (0 << 6)
#define ES8311_CLK_MANAGER_REG01_MCLK_INV_ON (1 << 6) #define ES8311_CLK_MANAGER_REG01_MCLK_INV_ON ES8311_BIT(6)
#define ES8311_CLK_MANAGER_REG01_MCLK_OFF (0 << 5) #define ES8311_CLK_MANAGER_REG01_MCLK_OFF (0 << 5)
#define ES8311_CLK_MANAGER_REG01_MCLK_ON (1 << 5) #define ES8311_CLK_MANAGER_REG01_MCLK_ON ES8311_BIT(5)
#define ES8311_CLK_MANAGER_REG01_BCLK_OFF (0 << 4) #define ES8311_CLK_MANAGER_REG01_BCLK_OFF (0 << 4)
#define ES8311_CLK_MANAGER_REG01_BCLK_ON (1 << 4) #define ES8311_CLK_MANAGER_REG01_BCLK_ON ES8311_BIT(4)
#define ES8311_CLK_MANAGER_REG02 0x02 /* clk divider and clk multiplier */ #define ES8311_CLK_MANAGER_REG02 0x02 /* clk divider and clk multiplier */
#define ES8311_CLK_MANAGER_REG03 0x03 /* adc fsmode and osr */ #define ES8311_CLK_MANAGER_REG03 0x03 /* adc fsmode and osr */
#define ES8311_CLK_MANAGER_REG03_ADC_FSMODE_SINGLE_SPEED (0 << 6)
#define ES8311_CLK_MANAGER_REG03_ADC_FSMODE_DOUBLE_SPEED ES8311_BIT(6)
/*
ADC_OSR 5:0 ADC delta sigma over sample rate
0~14 – not use
15 – 60*fs(ss) / (ds not support)
16 – 64*fs(ss) / 32*fs(ds) (default)
...
31 – 124*fs(ss) / 62*fs(ds)
32 – 128*fs(ss) / 64*fs(ds)
...
63 – 252*fs(ss) / 126*fs(ds)
*/
#define ES8311_CLK_MANAGER_REG04 0x04 /* dac osr */ #define ES8311_CLK_MANAGER_REG04 0x04 /* dac osr */
#define ES8311_CLK_MANAGER_REG05 0x05 /* clk divier for adc and dac */ #define ES8311_CLK_MANAGER_REG05 0x05 /* clk divier for adc and dac */
#define ES8311_CLK_MANAGER_REG06 0x06 /* bclk inverter and divider */ #define ES8311_CLK_MANAGER_REG06 0x06 /* bclk inverter and divider */
#define ES8311_CLK_MANAGER_REG06_CONTINUAL_BCLK (0 << 6) #define ES8311_CLK_MANAGER_REG06_CONTINUAL_BCLK (0 << 6)
#define ES8311_CLK_MANAGER_REG06_WHEN_DATA_TRANSFER_BCLK (1 << 6) #define ES8311_CLK_MANAGER_REG06_WHEN_DATA_TRANSFER_BCLK ES8311_BIT(6)
#define ES8311_CLK_MANAGER_REG06_NORMAL_BCLK (0 << 5) #define ES8311_CLK_MANAGER_REG06_NORMAL_BCLK (0 << 5)
#define ES8311_CLK_MANAGER_REG06_INVERT_BCLK (1 << 5) #define ES8311_CLK_MANAGER_REG06_INVERT_BCLK ES8311_BIT(5)
#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_1 0x00 #define ES8311_CLK_MANAGER_REG06_DIV_BCLK_1 0x00
#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_2 0x01 #define ES8311_CLK_MANAGER_REG06_DIV_BCLK_2 0x01
#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_3 0x02 #define ES8311_CLK_MANAGER_REG06_DIV_BCLK_3 0x02
@@ -84,42 +114,42 @@
#define ES8311_CLK_MANAGER_REG07 0x07 /* tri-state, lrck divider */ #define ES8311_CLK_MANAGER_REG07 0x07 /* tri-state, lrck divider */
#define ES8311_CLK_MANAGER_REG07_BCLK_LRCLK_NORMAL_MODE (0 << 5) #define ES8311_CLK_MANAGER_REG07_BCLK_LRCLK_NORMAL_MODE (0 << 5)
#define ES8311_CLK_MANAGER_REG07_BCLK_LRCLK_TRISTATE_MODE (1 << 5) #define ES8311_CLK_MANAGER_REG07_BCLK_LRCLK_TRISTATE_MODE ES8311_BIT(5)
#define ES8311_CLK_MANAGER_REG07_ADCDAT_NORMAL_MODE (0 << 4) #define ES8311_CLK_MANAGER_REG07_ADCDAT_NORMAL_MODE (0 << 4)
#define ES8311_CLK_MANAGER_REG07_ADCDAT_TRISTATE_MODE (1 << 4) #define ES8311_CLK_MANAGER_REG07_ADCDAT_TRISTATE_MODE ES8311_BIT(4)
#define ES8311_CLK_MANAGER_REG08 0x08 /* lrck divider */ #define ES8311_CLK_MANAGER_REG08 0x08 /* lrck divider */
/* /*
* SDP * SDP
*/ */
#define ES8311_SDPIN_REG 0x09 #define ES8311_SDPIN_REG 0x09
#define ES8311_SDPIN_SEL_LEFT_TO_DAC (0 << 7) #define ES8311_SDPIN_SEL_LEFT_TO_DAC (0 << 7)
#define ES8311_SDPIN_SEL_RIGHT_TO_DAC (1 << 7) #define ES8311_SDPIN_SEL_RIGHT_TO_DAC ES8311_BIT(7)
#define ES8311_SDPIN_UNMUTE (0 << 6) #define ES8311_SDPIN_UNMUTE (0 << 6)
#define ES8311_SDPIN_MUTE (1 << 6) #define ES8311_SDPIN_MUTE ES8311_BIT(6)
#define ES8311_SDPIN_LR_NORMAL_POLARITY (0 << 5) #define ES8311_SDPIN_LR_NORMAL_POLARITY (0 << 5)
#define ES8311_SDPIN_LR_INVERTED_POLARITY (1 << 5) #define ES8311_SDPIN_LR_INVERTED_POLARITY ES8311_BIT(5)
#define ES8311_SDPIN_WORD_24BIT (0 << 2) #define ES8311_SDPIN_WORD_24BIT (0 << 2)
#define ES8311_SDPIN_WORD_20BIT (1 << 2) #define ES8311_SDPIN_WORD_20BIT ES8311_BIT(2)
#define ES8311_SDPIN_WORD_18BIT (2 << 2) #define ES8311_SDPIN_WORD_18BIT (2 << 2)
#define ES8311_SDPIN_WORD_16BIT (3 << 2) #define ES8311_SDPIN_WORD_16BIT (3 << 2)
#define ES8311_SDPIN_WORD_32BIT (4 << 2) #define ES8311_SDPIN_WORD_32BIT (4 << 2)
#define ES8311_SDPIN_FORMAT_I2S (0 << 0) #define ES8311_SDPIN_FORMAT_I2S (0)
#define ES8311_SDPIN_FORMAT_LEFT_JUSTIFY_SERIAL (1 << 0) #define ES8311_SDPIN_FORMAT_LEFT_JUSTIFY_SERIAL ES8311_BIT(0)
#define ES8311_SDPIN_FORMAT_PCM (3 << 0) #define ES8311_SDPIN_FORMAT_PCM (0)
#define ES8311_SDPOUT_REG 0x0A #define ES8311_SDPOUT_REG 0x0A
#define ES8311_SDPOUT_UNMUTE (0 << 6) #define ES8311_SDPOUT_UNMUTE (0 << 6)
#define ES8311_SDPOUT_MUTE (1 << 6) #define ES8311_SDPOUT_MUTE ES8311_BIT(6)
#define ES8311_SDPOUT_LR_NORMAL_POLARITY (0 << 5) #define ES8311_SDPOUT_LR_NORMAL_POLARITY (0 << 5)
#define ES8311_SDPOUT_LR_INVERTED_POLARITY (1 << 5) #define ES8311_SDPOUT_LR_INVERTED_POLARITY ES8311_BIT(5)
#define ES8311_SDPOUT_WORD_24BIT (0 << 2) #define ES8311_SDPOUT_WORD_24BIT (0 << 2)
#define ES8311_SDPOUT_WORD_20BIT (1 << 2) #define ES8311_SDPOUT_WORD_20BIT ES8311_BIT(2)
#define ES8311_SDPOUT_WORD_18BIT (2 << 2) #define ES8311_SDPOUT_WORD_18BIT (2 << 2)
#define ES8311_SDPOUT_WORD_16BIT (3 << 2) #define ES8311_SDPOUT_WORD_16BIT (3 << 2)
#define ES8311_SDPOUT_WORD_32BIT (4 << 2) #define ES8311_SDPOUT_WORD_32BIT (4 << 2)
#define ES8311_SDPOUT_FORMAT_I2S (0 << 0) #define ES8311_SDPOUT_FORMAT_I2S (0)
#define ES8311_SDPOUT_FORMAT_LEFT_JUSTIFY_SERIAL (1 << 0) #define ES8311_SDPOUT_FORMAT_LEFT_JUSTIFY_SERIAL ES8311_BIT(0)
#define ES8311_SDPOUT_FORMAT_PCM (3 << 0) #define ES8311_SDPOUT_FORMAT_PCM (0)
/* /*
* SYSTEM * SYSTEM
*/ */
@@ -128,15 +158,15 @@
#define ES8311_SYSTEM_REG0D 0x0D /* system, power up/down */ #define ES8311_SYSTEM_REG0D 0x0D /* system, power up/down */
#define ES8311_SYSTEM_REG0D_ANALOG_ENABLED (0 << 7) #define ES8311_SYSTEM_REG0D_ANALOG_ENABLED (0 << 7)
#define ES8311_SYSTEM_REG0D_ANALOG_DISABLED (1 << 7) #define ES8311_SYSTEM_REG0D_ANALOG_DISABLED ES8311_BIT(7)
#define ES8311_SYSTEM_REG0D_ANALOG_BIAS_ENABLED (0 << 6) #define ES8311_SYSTEM_REG0D_ANALOG_BIAS_ENABLED (0 << 6)
#define ES8311_SYSTEM_REG0D_ANALOG_BIAS_DISABLED (1 << 6) #define ES8311_SYSTEM_REG0D_ANALOG_BIAS_DISABLED ES8311_BIT(6)
#define ES8311_SYSTEM_REG0D_ANALOG_ADC_BIAS_ENABLED (0 << 5) #define ES8311_SYSTEM_REG0D_ANALOG_ADC_BIAS_ENABLED (0 << 5)
#define ES8311_SYSTEM_REG0D_ANALOG_ADC_BIAS_DISABLED (1 << 5) #define ES8311_SYSTEM_REG0D_ANALOG_ADC_BIAS_DISABLED ES8311_BIT(5)
#define ES8311_SYSTEM_REG0D_ANALOG_ADC_REFERENCE_ENABLED (0 << 4) #define ES8311_SYSTEM_REG0D_ANALOG_ADC_REFERENCE_ENABLED (0 << 4)
#define ES8311_SYSTEM_REG0D_ANALOG_ADC_REFERENCE_DISABLED (1 << 4) #define ES8311_SYSTEM_REG0D_ANALOG_ADC_REFERENCE_DISABLED ES8311_BIT(4)
#define ES8311_SYSTEM_REG0D_ANALOG_DAC_REFERENCE_ENABLED (0 << 3) #define ES8311_SYSTEM_REG0D_ANALOG_DAC_REFERENCE_ENABLED (0 << 3)
#define ES8311_SYSTEM_REG0D_ANALOG_DAC_REFERENCE_DISABLED (1 << 3) #define ES8311_SYSTEM_REG0D_ANALOG_DAC_REFERENCE_DISABLED ES8311_BIT(3)
#define ES8311_SYSTEM_REG0D_VMID_POWER_DOWN 0x00 #define ES8311_SYSTEM_REG0D_VMID_POWER_DOWN 0x00
#define ES8311_SYSTEM_REG0D_VMID_START_NORMAL_SPEED 0x01 #define ES8311_SYSTEM_REG0D_VMID_START_NORMAL_SPEED 0x01
#define ES8311_SYSTEM_REG0D_VMID_NORMAL 0x02 #define ES8311_SYSTEM_REG0D_VMID_NORMAL 0x02
@@ -145,31 +175,31 @@
#define ES8311_SYSTEM_REG0E 0x0E /* system, power up/down */ #define ES8311_SYSTEM_REG0E 0x0E /* system, power up/down */
#define ES8311_SYSTEM_REG0E_PGA_ENABLE (0 << 6) #define ES8311_SYSTEM_REG0E_PGA_ENABLE (0 << 6)
#define ES8311_SYSTEM_REG0E_PGA_DISABLE (1 << 6) #define ES8311_SYSTEM_REG0E_PGA_DISABLE ES8311_BIT(6)
#define ES8311_SYSTEM_REG0E_PDN_MOD_ENABLE (0 << 5) #define ES8311_SYSTEM_REG0E_PDN_MOD_ENABLE (0 << 5)
#define ES8311_SYSTEM_REG0E_PDN_MOD_DISABLE (1 << 5) #define ES8311_SYSTEM_REG0E_PDN_MOD_DISABLE ES8311_BIT(5)
#define ES8311_SYSTEM_REG0E_MOD_NORMAL (0 << 4) #define ES8311_SYSTEM_REG0E_MOD_NORMAL (0 << 4)
#define ES8311_SYSTEM_REG0E_MOD_RESET (1 << 4) #define ES8311_SYSTEM_REG0E_MOD_RESET ES8311_BIT(4)
#define ES8311_SYSTEM_REG0F 0x0F /* system, low power */ #define ES8311_SYSTEM_REG0F 0x0F /* system, low power */
#define ES8311_SYSTEM_REG0F_DAC_NORMAL_MODE (0 << 7) #define ES8311_SYSTEM_REG0F_DAC_NORMAL_MODE (0 << 7)
#define ES8311_SYSTEM_REG0F_DAC_LOW_POWER_MODE (1 << 7) #define ES8311_SYSTEM_REG0F_DAC_LOW_POWER_MODE ES8311_BIT(7)
#define ES8311_SYSTEM_REG0F_PGA_NORMAL_MODE (0 << 6) #define ES8311_SYSTEM_REG0F_PGA_NORMAL_MODE (0 << 6)
#define ES8311_SYSTEM_REG0F_PGA_LOW_POWER_MODE (1 << 6) #define ES8311_SYSTEM_REG0F_PGA_LOW_POWER_MODE ES8311_BIT(6)
#define ES8311_SYSTEM_REG0F_PGA_OUTPUT_NORMAL_MODE (0 << 5) #define ES8311_SYSTEM_REG0F_PGA_OUTPUT_NORMAL_MODE (0 << 5)
#define ES8311_SYSTEM_REG0F_PGA_OUTPUT_LOW_POWER_MODE (1 << 5) #define ES8311_SYSTEM_REG0F_PGA_OUTPUT_LOW_POWER_MODE ES8311_BIT(5)
#define ES8311_SYSTEM_REG0F_VCMMOD_NORMAL_MODE (0 << 4) #define ES8311_SYSTEM_REG0F_VCMMOD_NORMAL_MODE (0 << 4)
#define ES8311_SYSTEM_REG0F_VCMMOD_LOW_POWER_MODE (1 << 4) #define ES8311_SYSTEM_REG0F_VCMMOD_LOW_POWER_MODE ES8311_BIT(4)
#define ES8311_SYSTEM_REG0F_ADC_REFERENCE_NORMAL_MODE (0 << 3) #define ES8311_SYSTEM_REG0F_ADC_REFERENCE_NORMAL_MODE (0 << 3)
#define ES8311_SYSTEM_REG0F_ADC_REFERENCE_LOW_POWER_MODE (1 << 3) #define ES8311_SYSTEM_REG0F_ADC_REFERENCE_LOW_POWER_MODE ES8311_BIT(3)
#define ES8311_SYSTEM_REG0F_DAC_REFERENCE_NORMAL_MODE (0 << 2) #define ES8311_SYSTEM_REG0F_DAC_REFERENCE_NORMAL_MODE (0 << 2)
#define ES8311_SYSTEM_REG0F_DAC_REFERENCE_LOW_POWER_MODE (1 << 2) #define ES8311_SYSTEM_REG0F_DAC_REFERENCE_LOW_POWER_MODE ES8311_BIT(2)
#define ES8311_SYSTEM_REG0F_FLASH_NORMAL_MODE (0 << 1) #define ES8311_SYSTEM_REG0F_FLASH_NORMAL_MODE (0 << 1)
#define ES8311_SYSTEM_REG0F_FLASH_LOW_POWER_MODE (1 << 1) #define ES8311_SYSTEM_REG0F_FLASH_LOW_POWER_MODE ES8311_BIT(1)
#define ES8311_SYSTEM_REG0F_INT1_NORMAL_MODE (0 << 0) #define ES8311_SYSTEM_REG0F_INT1_NORMAL_MODE (0)
#define ES8311_SYSTEM_REG0F_INT1_LOW_POWER_MODE (1 << 0) #define ES8311_SYSTEM_REG0F_INT1_LOW_POWER_MODE ES8311_BIT(0)
@@ -182,9 +212,9 @@
0x14 /* system, select DMIC, select analog pga gain */ 0x14 /* system, select DMIC, select analog pga gain */
#define ES8311_SYSTEM_REG14_DMIC_OFF (0 << 6) #define ES8311_SYSTEM_REG14_DMIC_OFF (0 << 6)
#define ES8311_SYSTEM_REG14_DMIC_AND_DMIC_SDA (1 << 6) #define ES8311_SYSTEM_REG14_DMIC_AND_DMIC_SDA ES8311_BIT(6)
#define ES8311_SYSTEM_REG14_NO_MIC (0 << 4) #define ES8311_SYSTEM_REG14_NO_MIC (0 << 4)
#define ES8311_SYSTEM_REG14_MIC1 (1 << 4) #define ES8311_SYSTEM_REG14_MIC1 ES8311_BIT(4)
#define ES8311_SYSTEM_REG14_MIC2 (2 << 4) #define ES8311_SYSTEM_REG14_MIC2 (2 << 4)
#define ES8311_SYSTEM_REG14_MIC1_MIC2 (3 << 4) #define ES8311_SYSTEM_REG14_MIC1_MIC2 (3 << 4)
#define ES8311_SYSTEM_REG14_GAIN_0DB 0 #define ES8311_SYSTEM_REG14_GAIN_0DB 0
@@ -198,6 +228,8 @@
#define ES8311_SYSTEM_REG14_GAIN_24DB 8 #define ES8311_SYSTEM_REG14_GAIN_24DB 8
#define ES8311_SYSTEM_REG14_GAIN_27DB 9 #define ES8311_SYSTEM_REG14_GAIN_27DB 9
#define ES8311_SYSTEM_REG14_GAIN_30DB 10 #define ES8311_SYSTEM_REG14_GAIN_30DB 10
#define ES8311_SYSTEM_REG14_DMIC_CLOCK_POSITIVE (0)
#define ES8311_SYSTEM_REG14_DMIC_CLOCK_NEGATIVE ES8311_BIT(0)
@@ -205,14 +237,44 @@
* ADC * ADC
*/ */
#define ES8311_ADC_REG15 0x15 /* ADC, adc ramp rate, dmic sense */ #define ES8311_ADC_REG15 0x15 /* ADC, adc ramp rate, dmic sense */
#define ES8311_ADC_REG15_RAMPRATE_DISABLE (0x00 << 4)
#define ES8311_ADC_REG15_RAMPRATE_0_25_4LRCK (0x01 << 4)
#define ES8311_ADC_REG15_RAMPRATE_0_25_8LRCK (0x02 << 4)
#define ES8311_ADC_REG15_RAMPRATE_0_25_16LRCK (0x03 << 4)
#define ES8311_ADC_REG15_RAMPRATE_0_25_32LRCK (0x04 << 4)
#define ES8311_ADC_REG15_RAMPRATE_0_25_64LRCK (0x05 << 4)
#define ES8311_ADC_REG15_RAMPRATE_0_25_128LRCK (0x06 << 4)
#define ES8311_ADC_REG15_RAMPRATE_0_25_256LRCK (0x07 << 4)
#define ES8311_ADC_REG15_RAMPRATE_0_25_512LRCK (0x08 << 4)
#define ES8311_ADC_REG15_RAMPRATE_0_25_1024LRCK (0x09 << 4)
#define ES8311_ADC_REG15_RAMPRATE_0_25_2048LRCK (0x0a << 4)
#define ES8311_ADC_REG15_RAMPRATE_0_25_4096LRCK (0x0b << 4)
#define ES8311_ADC_REG15_RAMPRATE_0_25_8192LRCK (0x0c << 4)
#define ES8311_ADC_REG15_RAMPRATE_0_25_16384LRCK (0x0d << 4)
#define ES8311_ADC_REG15_RAMPRATE_0_25_32768LRCK (0x0e << 4)
#define ES8311_ADC_REG15_RAMPRATE_0_25_65536LRCK (0x0f << 4)
#define ES8311_ADC_REG16 0x16 /* ADC */ #define ES8311_ADC_REG16 0x16 /* ADC */
#define ES8311_ADC_REG16_ADC_RAM_CLR (1 << 3) #define ES8311_ADC_REG16_ADC_GAIN_0DB 0x00
#define ES8311_ADC_REG16_ADC_GAIN_6DB 0x01
#define ES8311_ADC_REG16_ADC_GAIN_12DB 0x02
#define ES8311_ADC_REG16_ADC_GAIN_18DB 0x03
#define ES8311_ADC_REG16_ADC_GAIN_24DB 0x04
#define ES8311_ADC_REG16_ADC_GAIN_30DB 0x05
#define ES8311_ADC_REG16_ADC_GAIN_36DB 0x06
#define ES8311_ADC_REG16_ADC_GAIN_42DB 0x07
#define ES8311_ADC_REG16_ADC_RAM_CLR ES8311_BIT(3)
#define ES8311_ADC_REG17 0x17 /* ADC, volume */ #define ES8311_ADC_REG17 0x17 /* ADC, volume */
#define ES8311_ADC_REG18 0x18 /* ADC, alc enable and winsize */ #define ES8311_ADC_REG18 0x18 /* ADC, alc enable and winsize */
#define ES8311_ADC_REG18_AUTO_LEVEL_CONTROL_DISABLE (0 << 7) #define ES8311_ADC_REG18_AUTO_LEVEL_CONTROL_DISABLE (0 << 7)
#define ES8311_ADC_REG18_AUTO_LEVEL_CONTROL_ENABLE (1 << 7) #define ES8311_ADC_REG18_AUTO_LEVEL_CONTROL_ENABLE ES8311_BIT(7)
#define ES8311_ADC_REG18_AUTO_MUTE_DISABLE (0 << 6) #define ES8311_ADC_REG18_AUTO_MUTE_DISABLE (0 << 6)
#define ES8311_ADC_REG18_AUTO_MUTE_ENABLE (1 << 6) #define ES8311_ADC_REG18_AUTO_MUTE_ENABLE ES8311_BIT(6)
#define ES8311_ADC_REG18_0_25DB_PER_2LRCK 0x00 #define ES8311_ADC_REG18_0_25DB_PER_2LRCK 0x00
#define ES8311_ADC_REG18_0_25DB_PER_4LRCK 0x01 #define ES8311_ADC_REG18_0_25DB_PER_4LRCK 0x01
#define ES8311_ADC_REG18_0_25DB_PER_8LRCK 0x02 #define ES8311_ADC_REG18_0_25DB_PER_8LRCK 0x02
@@ -249,16 +311,16 @@
#define ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_6_6DB (0x0E << 4) #define ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_6_6DB (0x0E << 4)
#define ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_6_0DB (0x0F << 4) #define ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_6_0DB (0x0F << 4)
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_30_1DB (0x00 << 0) #define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_30_1DB (0x00)
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_24_1DB (0x01 << 0) #define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_24_1DB (0x00)
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_20_6DB (0x02 << 0) #define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_20_6DB (0x00)
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_18_1DB (0x03 << 0) #define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_18_1DB (0x00)
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_16_1DB (0x04 << 0) #define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_16_1DB (0x00)
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_14_5DB (0x05 << 0) #define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_14_5DB (0x00)
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_13_2DB (0x06 << 0) #define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_13_2DB (0x00)
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_12_0DB (0x07 << 0) #define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_12_0DB (0x00)
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_11_0DB (0x08 << 0) #define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_11_0DB (0x00)
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_10_1DB (0x09 << 0) #define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_10_1DB (0x00)
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_9_3DB (0x0A << 0) #define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_9_3DB (0x0A << 0)
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_8_5DB (0x0B << 0) #define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_8_5DB (0x0B << 0)
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_7_8DB (0x0C << 0) #define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_7_8DB (0x0C << 0)
@@ -285,16 +347,16 @@
#define ES8311_ADC_REG1A_AUTOMUTE_30720_SAMPLES (0x0E << 4) #define ES8311_ADC_REG1A_AUTOMUTE_30720_SAMPLES (0x0E << 4)
#define ES8311_ADC_REG1A_AUTOMUTE_32768_SAMPLES (0x0F << 4) #define ES8311_ADC_REG1A_AUTOMUTE_32768_SAMPLES (0x0F << 4)
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_96DB (0x00 << 0) #define ES8311_ADC_REG1A_AUTOMUTE_NEG_96DB (0x00)
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_90DB (0x01 << 0) #define ES8311_ADC_REG1A_AUTOMUTE_NEG_90DB (0x00)
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_84DB (0x02 << 0) #define ES8311_ADC_REG1A_AUTOMUTE_NEG_84DB (0x00)
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_78DB (0x03 << 0) #define ES8311_ADC_REG1A_AUTOMUTE_NEG_78DB (0x00)
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_72DB (0x04 << 0) #define ES8311_ADC_REG1A_AUTOMUTE_NEG_72DB (0x00)
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_66DB (0x05 << 0) #define ES8311_ADC_REG1A_AUTOMUTE_NEG_66DB (0x00)
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_60DB (0x06 << 0) #define ES8311_ADC_REG1A_AUTOMUTE_NEG_60DB (0x00)
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_54DB (0x07 << 0) #define ES8311_ADC_REG1A_AUTOMUTE_NEG_54DB (0x00)
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_51DB (0x08 << 0) #define ES8311_ADC_REG1A_AUTOMUTE_NEG_51DB (0x00)
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_48DB (0x09 << 0) #define ES8311_ADC_REG1A_AUTOMUTE_NEG_48DB (0x00)
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_45DB (0x0A << 0) #define ES8311_ADC_REG1A_AUTOMUTE_NEG_45DB (0x0A << 0)
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_42DB (0x0B << 0) #define ES8311_ADC_REG1A_AUTOMUTE_NEG_42DB (0x0B << 0)
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_39DB (0x0C << 0) #define ES8311_ADC_REG1A_AUTOMUTE_NEG_39DB (0x0C << 0)
@@ -307,39 +369,140 @@
// bits 4:0 have ADCHPF stage 1 coefficient - reg1b // bits 4:0 have ADCHPF stage 1 coefficient - reg1b
#define ES8311_ADC_REG1C 0x1C /* ADC, equalizer, hpf s2 */ #define ES8311_ADC_REG1C 0x1C /* ADC, equalizer, hpf s2 */
#define ES8311_ADC_REG1C_ADCEQ_NORMAL (0 << 6) #define ES8311_ADC_REG1C_ADCEQ_NORMAL (0 << 6)
#define ES8311_ADC_REG1C_ADCEQ_BYPASS (1 << 6) #define ES8311_ADC_REG1C_ADCEQ_BYPASS ES8311_BIT(6)
#define ES8311_ADC_REG1C_HPF_FREEZE_OFFSET (0 << 5) #define ES8311_ADC_REG1C_HPF_FREEZE_OFFSET (0 << 5)
#define ES8311_ADC_REG1C_HPF_DYNAMIC_HPF (1 << 5) #define ES8311_ADC_REG1C_HPF_DYNAMIC_HPF ES8311_BIT(5)
// bits 4:0 have ADCHPF stage 2 coefficient - reg1c // bits 4:0 have ADCHPF stage 2 coefficient - reg1c
/* /*
reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ reg1e - ADCEQ_B0[23:16] - bit 7:0 30-bit B0 coefficient for ADCEQ
reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ reg1f - ADCEQ_B0[15:8] - bit 7:0 30-bit B0 coefficient for ADCEQ
reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ reg20 - ADCEQ_B0[7:0] - bit 7:0 30-bit B0 coefficient for ADCEQ
reg1d - ADCEQ_A1[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
reg1d - ADCEQ_A1[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ reg21 - ADCEQ_A1[29:24] - bit 5:0 30-bit A1 coefficient for ADCEQ
reg1d - ADCEQ_A1[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ reg22 - ADCEQ_A1[23:16] - bit 7:0 30-bit A1 coefficient for ADCEQ
reg1d - ADCEQ_A1[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ reg23 - ADCEQ_A1[15:8] - bit 7:0 30-bit A1 coefficient for ADCEQ
reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ reg24 - ADCEQ_A1[7:0] - bit 7:0 30-bit A1 coefficient for ADCEQ
reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ reg25 - ADCEQ_A2[29:24] - bit 5:0 30-bit A2 coefficient for ADCEQ
reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ reg26 - ADCEQ_A2[23:16] - bit 7:0 30-bit A2 coefficient for ADCEQ
reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ reg27 - ADCEQ_A2[15:8] - bit 7:0 30-bit A2 coefficient for ADCEQ
reg28 - ADCEQ_A2[7:0] - bit 7:0 30-bit A2 coefficient for ADCEQ
reg29 - ADCEQ_B1[29:24] - bit 5:0 30-bit B1 coefficient for ADCEQ
reg2a - ADCEQ_B1[23:16] - bit 7:0 30-bit B1 coefficient for ADCEQ
reg2b - ADCEQ_B1[15:8] - bit 7:0 30-bit B1 coefficient for ADCEQ
reg2c - ADCEQ_B1[7:0] - bit 7:0 30-bit B1 coefficient for ADCEQ
reg2d - ADCEQ_B2[29:24] - bit 5:0 30-bit B1 coefficient for ADCEQ
reg2e - ADCEQ_B2[23:16] - bit 7:0 30-bit B1 coefficient for ADCEQ
reg2f - ADCEQ_B2[15:8] - bit 7:0 30-bit B1 coefficient for ADCEQ
reg30 - ADCEQ_B2[7:0] - bit 7:0 30-bit B1 coefficient for ADCEQ
*/ */
/* /*
* DAC * DAC
*/ */
#define ES8311_DAC_REG31 0x31 /* DAC, mute */ #define ES8311_DAC_REG31 0x31 /* DAC, mute */
#define ES8311_DAC_REG31_MUTE_TO8 (0 << 7)
#define ES8311_DAC_REG31_MUTE_TO7_9 ES8311_BIT(7)
#define ES8311_DAC_REG31_DSM_UNMUTE (0 << 6)
#define ES8311_DAC_REG31_DSM_MUTE ES8311_BIT(6)
#define ES8311_DAC_REG31_DEM_UNMUTE (0 << 5)
#define ES8311_DAC_REG31_DEM_MUTE ES8311_BIT(5)
#define ES8311_DAC_REG32 0x32 /* DAC, volume */ #define ES8311_DAC_REG32 0x32 /* DAC, volume */
#define ES8311_DAC_REG33 0x33 /* DAC, offset */ #define ES8311_DAC_REG33 0x33 /* DAC, offset */
#define ES8311_DAC_REG34 0x34 /* DAC, drc enable, drc winsize */ #define ES8311_DAC_REG34 0x34 /* DAC, drc enable, drc winsize */
#define ES8311_DAC_REG34_DRC_DISABLE (0 << 7)
#define ES8311_DAC_REG34_DRC_ENABLE ES8311_BIT(7)
#define ES8311_DAC_REG34_DRC_WINSIZE_DISABLE (0x00)
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_4LRCK (0x00)
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_8LRCK (0x00)
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_16LRCK (0x00)
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_32LRCK (0x00)
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_64LRCK (0x00)
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_128LRCK (0x00)
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_256LRCK (0x00)
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_512LRCK (0x00)
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_1024LRCK (0x00)
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_2048LRCK (0x0a << 0)
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_4096LRCK (0x0b << 0)
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_8192LRCK (0x0c << 0)
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_16384LRCK (0x0d << 0)
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_32768LRCK (0x0e << 0)
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_65536LRCK (0x0f << 0)
#define ES8311_DAC_REG35 0x35 /* DAC, drc maxlevel, minilevel */ #define ES8311_DAC_REG35 0x35 /* DAC, drc maxlevel, minilevel */
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_30_1DB (0x00 << 4)
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_24_1DB (0x01 << 4)
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_20_6DB (0x02 << 4)
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_18_1DB (0x03 << 4)
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_16_1DB (0x04 << 4)
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_14_5DB (0x05 << 4)
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_13_2DB (0x06 << 4)
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_12_0DB (0x07 << 4)
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_11_0DB (0x08 << 4)
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_10_1DB (0x09 << 4)
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_9_3DB (0x0A << 4)
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_8_5DB (0x0B << 4)
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_7_8DB (0x0C << 4)
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_7_2DB (0x0D << 4)
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_6_6DB (0x0E << 4)
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_6_0DB (0x0F << 4)
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_30_1DB (0x00)
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_24_1DB (0x00)
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_20_6DB (0x00)
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_18_1DB (0x00)
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_16_1DB (0x00)
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_14_5DB (0x00)
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_13_2DB (0x00)
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_12_0DB (0x00)
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_11_0DB (0x00)
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_10_1DB (0x00)
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_9_3DB (0x0A << 0)
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_8_5DB (0x0B << 0)
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_7_8DB (0x0C << 0)
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_7_2DB (0x0D << 0)
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_6_6DB (0x0E << 0)
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_6_0DB (0x0F << 0)
#define ES8311_DAC_REG37 0x37 /* DAC, ramprate */ #define ES8311_DAC_REG37 0x37 /* DAC, ramprate */
#define ES8311_DAC_REG37_RAMPRATE_DISABLE (0x00 << 4)
#define ES8311_DAC_REG37_RAMPRATE_0_25_4LRCK (0x01 << 4)
#define ES8311_DAC_REG37_RAMPRATE_0_25_8LRCK (0x02 << 4)
#define ES8311_DAC_REG37_RAMPRATE_0_25_16LRCK (0x03 << 4)
#define ES8311_DAC_REG37_RAMPRATE_0_25_32LRCK (0x04 << 4)
#define ES8311_DAC_REG37_RAMPRATE_0_25_64LRCK (0x05 << 4)
#define ES8311_DAC_REG37_RAMPRATE_0_25_128LRCK (0x06 << 4)
#define ES8311_DAC_REG37_RAMPRATE_0_25_256LRCK (0x07 << 4)
#define ES8311_DAC_REG37_RAMPRATE_0_25_512LRCK (0x08 << 4)
#define ES8311_DAC_REG37_RAMPRATE_0_25_1024LRCK (0x09 << 4)
#define ES8311_DAC_REG37_RAMPRATE_0_25_2048LRCK (0x0a << 4)
#define ES8311_DAC_REG37_RAMPRATE_0_25_4096LRCK (0x0b << 4)
#define ES8311_DAC_REG37_RAMPRATE_0_25_8192LRCK (0x0c << 4)
#define ES8311_DAC_REG37_RAMPRATE_0_25_16384LRCK (0x0d << 4)
#define ES8311_DAC_REG37_RAMPRATE_0_25_32768LRCK (0x0e << 4)
#define ES8311_DAC_REG37_RAMPRATE_0_25_65536LRCK (0x0f << 4)
/* /*
*GPIO *GPIO
*/ */
#define ES8311_GPIO_REG44 0x44 /* GPIO, dac2adc for test */ #define ES8311_GPIO_REG44 0x44 /* GPIO, dac2adc for test */
#define ES8311_GPIO_REG44_ADCDAT_SEL_NO_LOOPBACK (0 << 7)
#define ES8311_GPIO_REG44_ADCDAT_ADC_TO_DAC ES8311_BIT(7)
#define ES8311_GPIO_REG44_ADCDAT_SEL_ADC_ADC (0x00 << 4)
#define ES8311_GPIO_REG44_ADCDAT_SEL_ADC_0 (0x01 << 4)
#define ES8311_GPIO_REG44_ADCDAT_SEL_0_ADC (0x02 << 4)
#define ES8311_GPIO_REG44_ADCDAT_SEL_0_0 (0x03 << 4)
#define ES8311_GPIO_REG44_ADCDAT_SEL_DACL_ADC (0x04 << 4)
#define ES8311_GPIO_REG44_ADCDAT_SEL_ADC_DACR (0x05 << 4)
#define ES8311_GPIO_REG44_ADCDAT_SEL_DACL_DACR (0x06 << 4)
//#define ES8311_GPIO_REG44_ADCDAT_SEL_NA (0x07 << 4)
#define ES8311_GP_REG45 0x45 /* GP CONTROL */ #define ES8311_GP_REG45 0x45 /* GP CONTROL */
/* /*
* CHIP * CHIP
main/drivers/i2s.c
+2 -1
View File
@@ -1,4 +1,5 @@
#include "i2s.h" #include "i2s.h"
#include "hal/i2s_types.h"
#include "pins.h" #include "pins.h"
i2s_chan_handle_t i2s_tx; i2s_chan_handle_t i2s_tx;
@@ -10,7 +11,7 @@ void audio_i2s_init(void) {
i2s_new_channel(&cfg, &i2s_tx, &i2s_rx); i2s_new_channel(&cfg, &i2s_tx, &i2s_rx);
i2s_std_config_t stdcfg = { i2s_std_config_t stdcfg = {
.clk_cfg = I2S_STD_CLK_DEFAULT_CONFIG(44100), .clk_cfg = I2S_STD_CLK_DEFAULT_CONFIG(48000),
.slot_cfg = I2S_STD_MSB_SLOT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_16BIT, .slot_cfg = I2S_STD_MSB_SLOT_DEFAULT_CONFIG(I2S_DATA_BIT_WIDTH_16BIT,
I2S_SLOT_MODE_STEREO), I2S_SLOT_MODE_STEREO),
main/drivers/pins.h
+2 -2
View File
@@ -51,7 +51,7 @@
*/ */
#define HEADER_CS GPIO_NUM_5 #define HEADER_CS GPIO_NUM_5
// also has i2c bus // also has i2c bus
#define HEADER_UART_RX GPIO_NUM_13 #define HEADER_UART_RX GPIO_NUM_15
#define HEADER_UART_TX GPIO_NUM_15 #define HEADER_UART_TX GPIO_NUM_13
void set_pin_dirs(); void set_pin_dirs();
main/drivers/servergprs.c
+130
View File
@@ -0,0 +1,130 @@
#include "servergprs.h"
#include "psa_crypto_driver_esp_aes_gcm.h"
char linebufIn[1024];
char *linebufInPtr = linebufIn;
#define MAX_FRAME 512
static uint8_t rx_buf[MAX_FRAME];
static size_t rx_len = 0;
static uint16_t expected_len = 0;
static int state = 0;
void process_encrypted_frame(uint8_t *data, size_t len)
{
// layout:
// [4B device_id][4B counter][12B nonce][ciphertext...][16B tag]
if (len < 36) return;
uint8_t *device_id = data;
uint8_t *counter = data + 4;
uint8_t *nonce = data + 8;
uint8_t *cipher = data + 20;
size_t cipher_len = len - 36;
uint8_t *tag = data + len - 16;
uint8_t plaintext[512];
size_t plaintext_len = 0;
psa_key_attributes_t attr = PSA_KEY_ATTRIBUTES_INIT;
psa_status_t st = esp_crypto_aes_gcm_decrypt(
&attr,
shared_key,
sizeof(shared_key),
PSA_ALG_GCM,
nonce, 12,
NULL, 0,
cipher, cipher_len,
plaintext, sizeof(plaintext),
&plaintext_len
);
if (st != PSA_SUCCESS) {
return;
}
handle_message(plaintext, plaintext_len);
}
void send_secure_packet(uint8_t *msg, size_t msg_len)
{
uint8_t nonce[12];
generate_random(nonce, 12);
uint8_t cipher[512];
size_t cipher_len = 0;
uint8_t tag[16];
size_t tag_len = 0;
esp_crypto_aes_gcm_encrypt(
&attr,
shared_key,
sizeof(shared_key),
PSA_ALG_GCM,
nonce, 12,
NULL, 0,
msg, msg_len,
cipher, sizeof(cipher),
&cipher_len
);
// build frame:
// [LEN][NONCE][CIPHER][TAG]
uint16_t total =
12 + cipher_len + 16;
uint8_t out[600];
out[0] = (total >> 8) & 0xFF;
out[1] = total & 0xFF;
memcpy(out + 2, nonce, 12);
memcpy(out + 14, cipher, cipher_len);
memcpy(out + 14 + cipher_len, tag, 16);
sim800_tcp_send(out, total + 2);
}
void tcp_on_byte(char c)
{
switch (state)
{
// WAIT FOR LENGTH (2 bytes)
case 0:
rx_buf[rx_len++] = c;
if (rx_len == 2)
{
expected_len = (rx_buf[0] << 8) | rx_buf[1];
rx_len = 0;
if (expected_len > MAX_FRAME) {
rx_len = 0;
state = 0;
return;
}
state = 1;
}
break;
// READ FRAME
case 1:
rx_buf[rx_len++] = c;
if (rx_len >= expected_len)
{
process_encrypted_frame(rx_buf, rx_len);
rx_len = 0;
state = 0;
}
break;
}
}
main/drivers/servergprs.h
+12
View File
@@ -0,0 +1,12 @@
#pragma once
#include "string.h"
#include "stddef.h"
#include "ctype.h"
#include "sim800.h"
//#include <mbedtls/chachapoly.h>
extern char linebufIn[1024];
extern char *linebufInPtr;
void tcp_on_byte(char c);
main/drivers/sim800.c
+855
View File
@@ -0,0 +1,855 @@
#include "sim800.h"
#include "drivers/pins.h"
#include "esp_log.h"
#include "freertos/idf_additions.h"
#include "projdefs.h"
#include <stdio.h>
#define SIM800_UART UART_NUM_2
static QueueHandle_t uart_queue;
static char smsBufSend[512];
static uint8_t tcp_internal_buf[512];
static uint8_t *tcp_send_buf = NULL;
static volatile int tcp_send_len = 0;
static volatile bool tcp_waiting_prompt = false;
static volatile bool tcp_send_in_progress = false;
static char line_buf[512];
static volatile size_t line_pos = 0;
static const char *TAG = "SIM800";
static volatile bool sim_ready = false;
static volatile bool sms_ready = false;
static volatile bool sim_needs_pin = false;
static SemaphoreHandle_t sim800_done;
static bool sim800_waiting = false;
static bool sim800_result = false;
static modem_t modem;
static bool sms_waiting_prompt = false;
static SemaphoreHandle_t sim800_mutex;
static SemaphoreHandle_t sms_mutex;
void print_state() {
switch (modem.state) {
case MODEM_STATE_OFF:
ESP_LOGI(TAG, "State is OFF");
break;
case MODEM_STATE_INIT:
ESP_LOGI(TAG, "State is INIT");
break;
case MODEM_STATE_READY:
ESP_LOGI(TAG, "State is Ready");
break;
case MODEM_STATE_REGISTERING:
ESP_LOGI(TAG, "State is Registering");
break;
case MODEM_STATE_REGISTERED:
ESP_LOGI(TAG, "State is Registered");
break;
case MODEM_STATE_SMS_READY:
ESP_LOGI(TAG, "State is SMS Ready");
break;
case MODEM_STATE_CALL_ACTIVE:
ESP_LOGI(TAG, "State is Call active");
break;
case MODEM_STATE_GPRS_CONNECTING:
ESP_LOGI(TAG, "State is GPRS Connecting");
break;
case MODEM_STATE_GPRS_UP:
ESP_LOGI(TAG, "State is GPRS UP");
break;
case MODEM_STATE_TCP_CONNECTING:
ESP_LOGI(TAG, "State is TCP Connecting");
break;
case MODEM_STATE_TCP_CONNECTED:
ESP_LOGI(TAG, "State is TCP Connected");
break;
case MODEM_STATE_ERROR:
ESP_LOGI(TAG, "State is Error");
break;
}
}
void sim800_uart_init(void) {
uart_config_t uart_config = {
.baud_rate = 9600,
.data_bits = UART_DATA_8_BITS,
.parity = UART_PARITY_DISABLE,
.stop_bits = UART_STOP_BITS_1,
.flow_ctrl = UART_HW_FLOWCTRL_DISABLE,
.source_clk = UART_SCLK_APB,
};
uart_driver_install(SIM800_UART, 2048, 2048, 20, &uart_queue, 0);
ESP_LOGI(TAG, "UART queue: %p", uart_queue);
uart_param_config(SIM800_UART, &uart_config);
uart_set_pin(SIM800_UART, HEADER_UART_TX, HEADER_UART_RX, UART_PIN_NO_CHANGE,
UART_PIN_NO_CHANGE);
}
void modem_update_flags(void) {
modem.in_call = (modem.state == MODEM_STATE_CALL_ACTIVE);
modem.gprs_active = (modem.state == MODEM_STATE_GPRS_UP);
}
void modem_set_state(modem_state_t new_state) {
xSemaphoreTake(modem.state_mutex, portMAX_DELAY);
if (modem.state == new_state) {
xSemaphoreGive(modem.state_mutex);
return;
}
ESP_LOGI(TAG, "STATE: %d -> %d", modem.state, new_state);
modem.state = new_state;
print_state();
xSemaphoreGive(modem.state_mutex);
modem_update_flags();
}
void modem_handle_event(modem_event_t ev) {
switch (modem.state) {
// -----------------------
case MODEM_STATE_INIT:
if (ev == EV_MODEM_OK) {
modem_set_state(MODEM_STATE_READY);
}
break;
// -----------------------
case MODEM_STATE_READY:
if (ev == EV_NETWORK_REG_OK) {
modem_set_state(MODEM_STATE_REGISTERED);
}
if (ev == EV_INCOMING_CALL) {
bool was_gprs = modem.gprs_active;
modem_set_state(MODEM_STATE_CALL_ACTIVE);
if (was_gprs) {
sim800_command("AT+CIPSHUT", 5000);
modem_handle_event(EV_GPRS_DOWN);
}
}
if (ev == EV_SMS_RECEIVED) {
// stay in same state (SMS is async service)
}
break;
// -----------------------
case MODEM_STATE_REGISTERED:
if (ev == EV_GPRS_UP) {
modem_set_state(MODEM_STATE_GPRS_UP);
}
if (ev == EV_INCOMING_CALL) {
modem_set_state(MODEM_STATE_CALL_ACTIVE);
}
if (ev == EV_NETWORK_LOST) {
modem_set_state(MODEM_STATE_REGISTERING);
}
break;
// -----------------------
case MODEM_STATE_GPRS_UP:
if (ev == EV_GPRS_DOWN) {
modem.tcp_connected = false;
modem_set_state(MODEM_STATE_SMS_READY);
}
if (ev == EV_INCOMING_CALL) {
// SIM800 limitation: calls break data
modem_set_state(MODEM_STATE_CALL_ACTIVE);
}
break;
// -----------------------
case MODEM_STATE_CALL_ACTIVE:
if (ev == EV_CALL_ENDED) {
modem_set_state(MODEM_STATE_SMS_READY);
}
break;
default:
break;
}
}
bool modem_start_gprs(void) {
if (modem.state != MODEM_STATE_REGISTERED &&
modem.state != MODEM_STATE_SMS_READY)
return false;
modem_set_state(MODEM_STATE_GPRS_CONNECTING);
// Always reset stack first
sim800_command("AT+CIPSHUT", 10000);
sim800_command("AT+CIPMUX=0", 10000);
// Ensure network attach (retry is IMPORTANT)
for (int i = 0; i < 5; i++) {
if (sim800_command("AT+CGATT=1", 3000))
break;
vTaskDelay(pdMS_TO_TICKS(100));
}
if (!sim800_command("AT+CGATT?", 2000)) {
ESP_LOGW(TAG, "CGATT check failed");
}
if (!sim800_command("AT+CSTT=\"internet\"", 5000))
return false;
if (!sim800_command("AT+CIICR", 15000))
return false;
vTaskDelay(pdMS_TO_TICKS(100));
sim800_command("AT+CIFSR", 100);
if (!sim800_command("AT+CIPHEAD=1", 15000))
return false;
modem_handle_event(EV_GPRS_UP);
modem_set_state(MODEM_STATE_GPRS_UP);
ESP_LOGI(TAG, "STARTED GPRS");
return true;
}
void sim800_csq_task(void *arg) {
while (1) {
/*
if (modem.state == MODEM_STATE_TCP_CONNECTED ||
modem.state == MODEM_STATE_GPRS_UP) {
sim800_command("AT+CSQ", 2000);
}
*/
if (modem.need_gprs_restart && modem.network_registered) {
modem.need_gprs_restart = false;
ESP_LOGI(TAG, "STARTING GPRS");
print_state();
modem_start_gprs();
print_state();
vTaskDelay(pdMS_TO_TICKS(100));
}
print_state();
if (modem.state == MODEM_STATE_GPRS_UP) {
sim800_tcp_connect("brn.systems", 6969);
if (modem.state != MODEM_STATE_TCP_CONNECTED) {
vTaskDelay(pdMS_TO_TICKS(1000));
}
}
vTaskDelay(pdMS_TO_TICKS(5000));
}
}
void sim800_task(void *arg)
{
uart_event_t event;
uint8_t *data = malloc(1024);
char lineBuf[128];
int linePos = 0;
int ipdRemaining = 0;
int ipdActive = 0;
while (1)
{
if (xQueueReceive(uart_queue, &event, portMAX_DELAY))
{
if (event.type == UART_DATA)
{
int len = uart_read_bytes(SIM800_UART, data, event.size, pdMS_TO_TICKS(100));
for (int i = 0; i < len; i++)
{
char c = data[i];
/* =========================
RAW TCP MODE (NO PARSING)
========================= */
if (ipdActive)
{
tcp_on_byte(c);
if (--ipdRemaining <= 0)
{
ipdActive = 0;
ESP_LOGI(TAG, "TCP RX END");
}
continue;
}
/* =========================
CONTROL LINE BUILDING
========================= */
if (c == '\r')
continue;
if (c == '\n')
{
if (linePos > 0)
{
lineBuf[linePos] = 0;
/* =========================
DETECT +IPD HEADER
========================= */
if (strncmp(lineBuf, "+IPD,", 5) == 0)
{
int len = 0;
char *p = strchr(lineBuf, ':');
if (p)
{
*p = 0;
sscanf(lineBuf, "+IPD,%d", &len);
ipdRemaining = len;
ipdActive = 1;
ESP_LOGI(TAG, "TCP RX START len=%d", len);
// if data after ':' already exists in same packet
p++;
while (*p && ipdRemaining > 0)
{
tcp_on_byte(*p++);
ipdRemaining--;
}
if (ipdRemaining <= 0)
{
ipdActive = 0;
ESP_LOGI(TAG, "TCP RX END (inline)");
}
}
}
else
{
sim800_handle_line(lineBuf);
}
linePos = 0;
}
continue;
}
/* =========================
BUILD LINE BUFFER (CTRL)
========================= */
if (linePos < sizeof(lineBuf) - 1)
{
lineBuf[linePos++] = c;
}
}
}
if (event.type == UART_FIFO_OVF)
{
ESP_LOGW(TAG, "FIFO overflow");
uart_flush_input(SIM800_UART);
xQueueReset(uart_queue);
}
}
}
free(data);
}
void sim800_handle_line(char *line) {
ESP_LOGI(TAG, "LINE: [%s]", line);
// -------------------------
// COMMAND RESPONSE HANDLER
// -------------------------
if (sim800_waiting) {
if (strcmp(line, "OK") == 0) {
ESP_LOGI(TAG, "Command successful");
sim800_result = true;
sim800_waiting = false;
xSemaphoreGive(sim800_done);
return;
}
if (strcmp(line, "ERROR") == 0) {
sim800_result = false;
sim800_waiting = false;
tcp_send_in_progress = false;
xSemaphoreGive(sim800_done);
return;
}
if (strstr(line, "ERROR") != 0) {
sim800_result = false;
sim800_waiting = false;
tcp_send_in_progress = false;
xSemaphoreGive(sim800_done);
return;
}
}
// -------------------------
// CALL EVENTS
// -------------------------
if (strcmp(line, "RING") == 0) {
ESP_LOGI(TAG, "Incoming call");
modem.in_call = true;
if (modem.state == MODEM_STATE_GPRS_UP) {
sim800_command("AT+CIPSHUT", 10000);
modem_handle_event(EV_GPRS_DOWN);
}
modem_handle_event(EV_INCOMING_CALL);
return;
}
if (strncmp(line, "NO CARRIER", 11) == 0) {
ESP_LOGI(TAG, "Call ended");
modem.in_call = false;
modem_handle_event(EV_CALL_ENDED);
if (modem.network_registered) {
modem.need_gprs_restart = true;
}
return;
}
if (strncmp(line, "BUSY", 4) == 0) {
modem.in_call = false;
modem_handle_event(EV_CALL_ENDED);
if (modem.network_registered) {
modem.need_gprs_restart = true;
}
return;
}
// -------------------------
// SMS EVENTS
// -------------------------
if (strncmp(line, "+CMTI:", 6) == 0) {
int index = -1;
sscanf(line, "+CMTI: \"SM\",%d", &index);
ESP_LOGI(TAG, "New SMS at index %d", index);
char cmd[32];
snprintf(cmd, sizeof(cmd), "AT+CMGR=%d", index);
sim800_command(cmd, 5000);
modem_handle_event(EV_SMS_RECEIVED);
return;
}
if (strncmp(line, "+CMGR:", 6) == 0) {
ESP_LOGI(TAG, "SMS header received");
return;
}
// -------------------------
// SIGNAL QUALITY
// -------------------------
if (strncmp(line, "+CSQ:", 5) == 0) {
int rssi, ber;
if (sscanf(line, "+CSQ: %d,%d", &rssi, &ber) == 2) {
modem.signal = rssi;
modem.last_rssi = rssi;
modem.last_ber = ber;
ESP_LOGI(TAG, "CSQ RSSI=%d BER=%d", rssi, ber);
// Optional: trigger behavior
if (rssi == 99) {
ESP_LOGW(TAG, "No signal");
} else if (rssi < 10) {
ESP_LOGW(TAG, "Weak signal");
}
}
return;
}
// -------------------------
// NETWORK REGISTRATION
// -------------------------
if (strncmp(line, "+CREG:", 6) == 0) {
ESP_LOGI(TAG, "Network registration: %s", line);
int n, stat;
if (strlen(line) > 10) {
sscanf(line, "+CREG: %d,%d", &n, &stat);
ESP_LOGI(TAG, "Network registration data: %d,%d", n, stat);
if (stat == 1 || stat == 5) {
modem.network_registered = 1;
ESP_LOGI(TAG, "REGISTERED");
modem_handle_event(EV_NETWORK_REG_OK);
} else {
modem.network_registered = 0;
modem_handle_event(EV_NETWORK_LOST);
}
} else {
sscanf(line, "+CREG: %d", &stat);
ESP_LOGI(TAG, "Network registration data: %d,%d", stat);
if (stat == 1 || stat == 5) {
modem.network_registered = 1;
ESP_LOGI(TAG, "REGISTERED");
modem_handle_event(EV_NETWORK_REG_OK);
} else {
modem.network_registered = 0;
modem_handle_event(EV_NETWORK_LOST);
}
}
return;
}
// -------------------------
// GPRS / DATA EVENTS
// -------------------------
if (strncmp(line, "CONNECT OK", 10) == 0) {
ESP_LOGI(TAG, "TCP connected");
modem_set_state(MODEM_STATE_TCP_CONNECTED);
modem.tcp_connected = true;
modem_set_state(MODEM_STATE_TCP_CONNECTED);
return;
}
if (strstr(line, "CONNECT FAIL")) {
modem.tcp_connected = false;
modem_set_state(MODEM_STATE_GPRS_UP);
}
if (strstr(line, "+CPIN: READY")) {
sim_ready = true;
modem_handle_event(EV_MODEM_OK);
ESP_LOGI(TAG, "SIM ready");
return;
}
if (strstr(line, "+CPIN: SIM PIN")) {
sim_needs_pin = true;
ESP_LOGI(TAG, "SIM needs pin");
return;
}
if (strstr(line, "CALL Ready")) {
modem.network_registered = 1;
ESP_LOGI(TAG, "SMS subsystem ready");
return;
}
if (strstr(line, "SMS Ready")) {
sms_ready = true;
modem.network_registered = 1;
ESP_LOGI(TAG, "SMS subsystem ready");
return;
}
if (strncmp(line, "SEND OK", 7) == 0) {
ESP_LOGI(TAG, "Data sent");
tcp_send_in_progress = false;
return;
}
if (strncmp(line, "CLOSED", 6) == 0) {
tcp_send_in_progress = false;
modem.tcp_connected = false;
modem_set_state(MODEM_STATE_GPRS_UP);
return;
}
/*
if (strncmp(line, "+IPD,", 5) == 0) {
ESP_LOGI(TAG, "TCP DATA: %s", line);
int len = 0;
sscanf(line, "+IPD,%d", &len);
// format: +IPD,len:data
char *p = strchr(line, ':');
if (p) {
p++;
ESP_LOGI(TAG, "RX TCP payload: %s", p);
// TODO: forward to your app layer
tcp_on_data(p, len);
}
return;
}
if (strncmp(line, "+RECEIVE", 8) == 0) {
char *payload = strchr(line, ':');
int pipe = 0;
if (payload) {
payload++; // skip ':'
int len = 0;
sscanf(line, "+RECEIVE,%d,%d", &pipe, &len);
ESP_LOGI(TAG, "TCP RX (%d): %.*s", pipe, len, payload);
tcp_on_data(payload, len);
}
return;
}
*/
}
void sim800_parse(char *data) {
while (*data) {
char c = *data++;
putchar(c);
if (c == '\r')
continue;
if (line_buf[0] == '>') {
if (sms_waiting_prompt) {
sms_waiting_prompt = false;
uart_write_bytes(SIM800_UART, smsBufSend, strlen(smsBufSend));
uint8_t ctrlz = 0x1A;
uart_write_bytes(SIM800_UART, &ctrlz, 1);
}
if (tcp_waiting_prompt) {
ESP_LOGI(TAG, "Got TCP >");
tcp_waiting_prompt = false;
uart_write_bytes(SIM800_UART, tcp_send_buf, tcp_send_len);
uint8_t ctrlz = 0x1A;
uart_write_bytes(SIM800_UART, &ctrlz, 1);
tcp_send_in_progress = false;
}
continue;
}
if (c == '\n') {
if (line_pos > 0) {
line_buf[line_pos] = 0;
sim800_handle_line(line_buf);
line_pos = 0;
}
continue;
}
if (line_pos < sizeof(line_buf) - 1) {
line_buf[line_pos++] = c;
}
}
}
void sim800_send(const char *cmd) {
ESP_LOGI(TAG, "TX: %s", cmd);
uart_write_bytes(SIM800_UART, cmd, strlen(cmd));
uart_write_bytes(SIM800_UART, "\r\n", 2);
}
bool sim800_command(const char *cmd, uint32_t timeout_ms) {
xSemaphoreTake(sim800_mutex, portMAX_DELAY);
sim800_waiting = true;
sim800_result = false;
sim800_send(cmd);
bool ok = xSemaphoreTake(sim800_done, pdMS_TO_TICKS(timeout_ms));
if (!ok) {
sim800_waiting = false; // important cleanup
ESP_LOGW(TAG, "Timeout");
xSemaphoreGive(sim800_mutex);
return false;
}
bool result = sim800_result;
sim800_waiting = false;
xSemaphoreGive(sim800_mutex);
return result;
}
void init_modem(void *arg) {
modem.state_mutex = xSemaphoreCreateMutex();
modem.state = MODEM_STATE_INIT;
modem.network_registered = 0;
modem.in_call = false;
modem.gprs_active = false;
modem.need_gprs_restart = true;
sim800_done = xSemaphoreCreateBinary();
sim800_mutex = xSemaphoreCreateMutex();
sms_mutex = xSemaphoreCreateMutex();
xTaskCreate(sim800_task, "sim800_task", 4096, NULL, 10, NULL);
sim800_command("AT+CFUN=1,1", 1);
while (1) {
if (sim800_command("AT", 1000)) {
ESP_LOGI(TAG, "Modem alive");
sim800_command("ATE0", 100);
sim800_command("AT+IPR=115200", 100);
uart_set_baudrate(SIM800_UART, 115200);
vTaskDelay(pdMS_TO_TICKS(50));
while (!sim_needs_pin) {
vTaskDelay(pdMS_TO_TICKS(100));
}
sim800_command("AT+CPIN=\"1577\"", 5000); // change to used sim, this is a test pin
while (!sim_ready) {
vTaskDelay(pdMS_TO_TICKS(100));
}
/*
while (!sms_ready) {
vTaskDelay(pdMS_TO_TICKS(100));
}
*/
sim800_command("AT+CREG=1", 3000);
while (!modem.network_registered) {
sim800_command("AT+CREG?", 3000);
vTaskDelay(pdMS_TO_TICKS(100));
}
sim800_command("AT+CMEE=2", 100);
sim800_command("AT+CMGF=1", 3000);
sim800_command("AT+CNMI=2,1,0,0,0", 3000);
xTaskCreate(sim800_csq_task, "csq_task", 3072, NULL, 5, NULL);
break;
} else {
ESP_LOGE(TAG, "No response");
}
}
while (1) {
vTaskDelay(pdTICKS_TO_MS(1000));
}
}
bool sim800_send_sms(const char *number, const char *msg) {
xSemaphoreTake(sms_mutex, portMAX_DELAY);
strcpy(smsBufSend, msg);
char cmd[64];
snprintf(cmd, sizeof(cmd), "AT+CMGS=\"%s\"", number);
sms_waiting_prompt = true;
sim800_send(cmd);
return true;
}
bool sim800_call(const char *number) {
if (modem.gprs_active) {
sim800_command("AT+CIPSHUT", 5000);
modem_handle_event(EV_GPRS_DOWN);
}
char cmd[64];
snprintf(cmd, sizeof(cmd), "ATD%s;", number);
return sim800_command(cmd, 15000);
}
bool sim800_hangup(void) { return sim800_command("ATH", 3000); }
bool sim800_answer(void) { return sim800_command("ATA", 5000); }
bool sim800_tcp_connect(const char *host, int port) {
if (modem.state != MODEM_STATE_GPRS_UP)
return false;
snprintf(modem.tcp_host, sizeof(modem.tcp_host), "%s", host);
modem.tcp_port = port;
modem_set_state(MODEM_STATE_TCP_CONNECTING);
char cmd[128];
snprintf(cmd, sizeof(cmd), "AT+CIPSTART=\"TCP\",\"%s\",\"%d\"", host, port);
if (!sim800_command(cmd, 15000)) {
modem_set_state(MODEM_STATE_GPRS_UP);
return false;
}
return true;
}
bool sim800_tcp_send(const void *data, int len) {
if (modem.state != MODEM_STATE_TCP_CONNECTED)
return false;
if (tcp_send_in_progress)
return false;
tcp_send_in_progress = true;
xSemaphoreTake(sim800_mutex, portMAX_DELAY);
memcpy(tcp_internal_buf, data, len);
tcp_send_buf = tcp_internal_buf;
tcp_send_len = len;
tcp_waiting_prompt = true;
char cmd[32];
snprintf(cmd, sizeof(cmd), "AT+CIPSEND=%d", len);
sim800_send(cmd);
// actual sending happens when '>' arrives in parser
xSemaphoreGive(sim800_mutex);
return true;
}
bool sim800_tcp_close(void) {
if (!modem.tcp_connected)
return true;
bool ok = sim800_command("AT+CIPCLOSE", 5000);
modem.tcp_connected = false;
modem_set_state(MODEM_STATE_GPRS_UP);
return ok;
}
main/drivers/sim800.h
+115
View File
@@ -0,0 +1,115 @@
#pragma once
#include "driver/uart.h"
#include "esp_log.h"
#include "freertos/FreeRTOS.h"
#include "freertos/queue.h"
#include "freertos/task.h"
#include "pins.h"
#include "servergprs.h"
typedef struct {
SemaphoreHandle_t done;
char response[256];
bool success;
} sim800_cmd_t;
typedef enum {
MODEM_STATE_OFF = 0,
MODEM_STATE_INIT,
MODEM_STATE_READY,
MODEM_STATE_REGISTERING,
MODEM_STATE_REGISTERED,
MODEM_STATE_SMS_READY,
MODEM_STATE_CALL_ACTIVE,
MODEM_STATE_GPRS_CONNECTING,
MODEM_STATE_GPRS_UP,
MODEM_STATE_TCP_CONNECTING,
MODEM_STATE_TCP_CONNECTED,
MODEM_STATE_ERROR
} modem_state_t;
typedef struct {
modem_state_t state;
bool in_call;
bool gprs_active;
bool need_gprs_restart;
int signal;
int network_registered;
int last_rssi;
int last_ber;
bool tcp_connected;
char tcp_host[64];
int tcp_port;
SemaphoreHandle_t state_mutex;
} modem_t;
typedef enum {
EV_NONE = 0,
EV_MODEM_OK,
EV_MODEM_ERROR,
EV_NETWORK_REG_OK,
EV_NETWORK_LOST,
EV_INCOMING_CALL,
EV_CALL_ENDED,
EV_SMS_RECEIVED,
EV_GPRS_UP,
EV_GPRS_DOWN
} modem_event_t;
void print_state();
void sim800_uart_init(void);
void modem_update_flags(void);
void modem_set_state(modem_state_t new_state);
void modem_handle_event(modem_event_t ev);
bool modem_start_gprs(void);
void sim800_csq_task(void *arg);
void sim800_task(void *arg);
void sim800_handle_line(char *line);
void sim800_parse(char *data);
void sim800_send(const char *cmd);
bool sim800_command(const char *cmd, uint32_t timeout_ms);
void init_modem(void *arg);
bool sim800_send_sms(const char *number, const char *msg);
bool sim800_call(const char *number);
bool sim800_hangup(void);
bool sim800_answer(void);
bool sim800_tcp_connect(const char *host, int port);
bool sim800_tcp_send(const void *data, int len);
bool sim800_tcp_close(void);
main/idf_component.yml
+1
View File
@@ -16,3 +16,4 @@ dependencies:
# public: true # public: true
espressif/esp_tinyusb: ~2.2.0 espressif/esp_tinyusb: ~2.2.0
espressif/led_strip: ^3.0.0 espressif/led_strip: ^3.0.0
espressif/esp_codec_dev: ^1.5.9
main/main.c
+42 -2
View File
@@ -1,9 +1,12 @@
#include <ctype.h>
#include <stdint.h> #include <stdint.h>
#include <stdio.h> #include <stdio.h>
#include <string.h>
#include "driver/gpio.h" #include "driver/gpio.h"
#include "drivers/fonts.h" #include "drivers/fonts.h"
#include "drivers/i2c.h" #include "drivers/i2c.h"
#include "drivers/sim800.h"
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"
#include "freertos/task.h" #include "freertos/task.h"
@@ -21,13 +24,21 @@
#include "hal/gpio_types.h" #include "hal/gpio_types.h"
#include "projdefs.h" #include "projdefs.h"
char linebuf[1024];
char *linebufPtr = linebuf;
void app_main(void) { void app_main(void) {
memset(linebuf, 0, sizeof(linebuf));
printf("boot\n"); printf("boot\n");
set_pin_dirs(); set_pin_dirs();
battery_start_task(); battery_start_task();
i2c_init(BUS_I2C_SDA, BUS_I2C_SCL); i2c_init(BUS_I2C_SDA, BUS_I2C_SCL);
ws2812_init(); ws2812_init();
sim800_uart_init();
xTaskCreate(init_modem, "init_modem", 4096, NULL, 10, NULL);
audio_i2s_init();
vTaskDelay(pdMS_TO_TICKS(10));
es8311_init(); es8311_init();
tca8418_init(); tca8418_init();
if (!bmi270_init()) { if (!bmi270_init()) {
@@ -64,13 +75,40 @@ void app_main(void) {
font5x7); font5x7);
while (tca8418_read(&key, &pressed)) { while (tca8418_read(&key, &pressed)) {
char c = getKeyboardChar(key);
if (!pressed) {
if (isprint(c)) {
*(linebufPtr++) = c;
} else {
switch (c) {
case '\n':
sim800_tcp_send(linebuf, linebufPtr - linebuf);
linebufPtr = linebuf;
memset(linebuf, 0, sizeof(linebuf));
break;
case '\b':
if (linebufPtr > linebuf) {
*(linebufPtr--) = 0;
}
}
}
if (linebufPtr > linebuf + 1023) {
linebufPtr = linebuf + 1023;
}
}
/*
snprintf(buf, sizeof(buf), "key=%c %s %d %s", getKeyboardChar(key), snprintf(buf, sizeof(buf), "key=%c %s %d %s", getKeyboardChar(key),
getKeyboardKeyName(key), key, pressed ? "pressed" : "released"); getKeyboardKeyName(key), key, pressed ? "pressed" : "released");
printf("%s\n", buf); printf("%s\n", buf);
st7789_draw_string(30, 30, buf, 0x07E0, 0x0000, true, fontHitachi); */
//audio_test_tone();
// audio_beep();
} }
st7789_draw_string(30, 30, linebuf, 0x07E0, 0x0000, true, fontHitachi);
bmi270_data_t bmiData; bmi270_data_t bmiData;
@@ -86,6 +124,8 @@ void app_main(void) {
snprintf(buf, sizeof(buf), "BAT: %d%%(%.3fV)", getBatteryPercentage(), snprintf(buf, sizeof(buf), "BAT: %d%%(%.3fV)", getBatteryPercentage(),
getBatteryVoltage()); getBatteryVoltage());
st7789_draw_string(140, 10, buf, 0x07E0, 0x0000, true, fontHitachi); st7789_draw_string(140, 10, buf, 0x07E0, 0x0000, true, fontHitachi);
st7789_draw_string(30, 90, linebufIn, 0x07E0, 0x0000, true, fontHitachi);
st7789_flush(); st7789_flush();
vTaskDelay(pdMS_TO_TICKS(20)); // 50 fps max vTaskDelay(pdMS_TO_TICKS(20)); // 50 fps max