399 lines
17 KiB
C
399 lines
17 KiB
C
#pragma once
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#include <stddef.h>
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#include <stdint.h>
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// ----------------------
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// I2C
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// ----------------------
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#define ES8311_RESET_REG00 0x00 /*reset digital,csm,clock manager etc.*/
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#define ES8311_RESET_CSM_OFF (0 << 7)
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#define ES8311_RESET_CSM_ON (1 << 7)
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#define ES8311_RESET_CSM_MSC_SLAVE (0 << 6)
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#define ES8311_RESET_CSM_MSC_MASTER (1 << 6)
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// #define ES8311_RESET_CSM_MSC_SLAVE (0 << 5)
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// #define ES8311_RESET_CSM_MSC_MASTER (1 << 5)
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#define ES8311_RESET_DIGITAL_RUN (0 << 4)
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#define ES8311_RESET_DIGITAL_RST (1 << 4)
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#define ES8311_RESET_CLOCK_MANAGER_RUN (0 << 3)
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#define ES8311_RESET_CLOCK_MANAGER_RST (1 << 3)
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#define ES8311_RESET_MASTER_RUN (0 << 2)
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#define ES8311_RESET_MASTER_RST (1 << 2)
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#define ES8311_RESET_ADC_DIGITAL_RUN (0 << 1)
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#define ES8311_RESET_ADC_DIGITAL_RST (1 << 1)
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#define ES8311_RESET_DAC_DIGITAL_RUN (0 << 0)
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#define ES8311_RESET_DAC_DIGITAL_RST (1 << 0)
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/*
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* Clock Scheme Register definition
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*/
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#define ES8311_CLK_MANAGER_REG01 \
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0x01 /* select clk src for mclk, enable clock for codec */
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#define ES8311_CLK_MANAGER_REG01_MCLK_SEL_FROM_MCLK (0 << 7)
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#define ES8311_CLK_MANAGER_REG01_MCLK_SEL_FROM_BCLK (1 << 7)
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#define ES8311_CLK_MANAGER_REG01_MCLK_INV_OFF (0 << 6)
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#define ES8311_CLK_MANAGER_REG01_MCLK_INV_ON (1 << 6)
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#define ES8311_CLK_MANAGER_REG01_MCLK_OFF (0 << 5)
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#define ES8311_CLK_MANAGER_REG01_MCLK_ON (1 << 5)
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#define ES8311_CLK_MANAGER_REG01_BCLK_OFF (0 << 4)
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#define ES8311_CLK_MANAGER_REG01_BCLK_ON (1 << 4)
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#define ES8311_CLK_MANAGER_REG02 0x02 /* clk divider and clk multiplier */
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#define ES8311_CLK_MANAGER_REG03 0x03 /* adc fsmode and osr */
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#define ES8311_CLK_MANAGER_REG04 0x04 /* dac osr */
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#define ES8311_CLK_MANAGER_REG05 0x05 /* clk divier for adc and dac */
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#define ES8311_CLK_MANAGER_REG06 0x06 /* bclk inverter and divider */
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#define ES8311_CLK_MANAGER_REG06_CONTINUAL_BCLK (0 << 6)
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#define ES8311_CLK_MANAGER_REG06_WHEN_DATA_TRANSFER_BCLK (1 << 6)
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#define ES8311_CLK_MANAGER_REG06_NORMAL_BCLK (0 << 5)
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#define ES8311_CLK_MANAGER_REG06_INVERT_BCLK (1 << 5)
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_1 0x00
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_2 0x01
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_3 0x02
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_4 0x03
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_5 0x04
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_6 0x05
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_7 0x06
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_8 0x07
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_9 0x08
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_10 0x09
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_11 0x0A
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_12 0x0B
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_13 0x0C
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_14 0x0D
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_15 0x0E
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_16 0x0F
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_17 0x10
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_18 0x11
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_19 0x12
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_20 0x13
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_22 0x14
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_24 0x15
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_25 0x16
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_30 0x17
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_32 0x18
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_33 0x19
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_34 0x1A
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_36 0x1B
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_44 0x1C
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_48 0x1D
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_66 0x1E
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_72 0x1F
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#define ES8311_CLK_MANAGER_REG07 0x07 /* tri-state, lrck divider */
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#define ES8311_CLK_MANAGER_REG07_BCLK_LRCLK_NORMAL_MODE (0 << 5)
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#define ES8311_CLK_MANAGER_REG07_BCLK_LRCLK_TRISTATE_MODE (1 << 5)
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#define ES8311_CLK_MANAGER_REG07_ADCDAT_NORMAL_MODE (0 << 4)
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#define ES8311_CLK_MANAGER_REG07_ADCDAT_TRISTATE_MODE (1 << 4)
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#define ES8311_CLK_MANAGER_REG08 0x08 /* lrck divider */
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/*
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* SDP
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*/
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#define ES8311_SDPIN_REG 0x09
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#define ES8311_SDPIN_SEL_LEFT_TO_DAC (0 << 7)
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#define ES8311_SDPIN_SEL_RIGHT_TO_DAC (1 << 7)
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#define ES8311_SDPIN_UNMUTE (0 << 6)
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#define ES8311_SDPIN_MUTE (1 << 6)
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#define ES8311_SDPIN_LR_NORMAL_POLARITY (0 << 5)
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#define ES8311_SDPIN_LR_INVERTED_POLARITY (1 << 5)
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#define ES8311_SDPIN_WORD_24BIT (0 << 2)
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#define ES8311_SDPIN_WORD_20BIT (1 << 2)
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#define ES8311_SDPIN_WORD_18BIT (2 << 2)
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#define ES8311_SDPIN_WORD_16BIT (3 << 2)
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#define ES8311_SDPIN_WORD_32BIT (4 << 2)
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#define ES8311_SDPIN_FORMAT_I2S (0 << 0)
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#define ES8311_SDPIN_FORMAT_LEFT_JUSTIFY_SERIAL (1 << 0)
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#define ES8311_SDPIN_FORMAT_PCM (3 << 0)
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#define ES8311_SDPOUT_REG 0x0A
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#define ES8311_SDPOUT_UNMUTE (0 << 6)
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#define ES8311_SDPOUT_MUTE (1 << 6)
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#define ES8311_SDPOUT_LR_NORMAL_POLARITY (0 << 5)
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#define ES8311_SDPOUT_LR_INVERTED_POLARITY (1 << 5)
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#define ES8311_SDPOUT_WORD_24BIT (0 << 2)
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#define ES8311_SDPOUT_WORD_20BIT (1 << 2)
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#define ES8311_SDPOUT_WORD_18BIT (2 << 2)
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#define ES8311_SDPOUT_WORD_16BIT (3 << 2)
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#define ES8311_SDPOUT_WORD_32BIT (4 << 2)
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#define ES8311_SDPOUT_FORMAT_I2S (0 << 0)
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#define ES8311_SDPOUT_FORMAT_LEFT_JUSTIFY_SERIAL (1 << 0)
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#define ES8311_SDPOUT_FORMAT_PCM (3 << 0)
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/*
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* SYSTEM
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*/
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#define ES8311_SYSTEM_REG0B 0x0B /* system */
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#define ES8311_SYSTEM_REG0C 0x0C /* system */
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#define ES8311_SYSTEM_REG0D 0x0D /* system, power up/down */
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#define ES8311_SYSTEM_REG0D_ANALOG_ENABLED (0 << 7)
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#define ES8311_SYSTEM_REG0D_ANALOG_DISABLED (1 << 7)
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#define ES8311_SYSTEM_REG0D_ANALOG_BIAS_ENABLED (0 << 6)
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#define ES8311_SYSTEM_REG0D_ANALOG_BIAS_DISABLED (1 << 6)
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#define ES8311_SYSTEM_REG0D_ANALOG_ADC_BIAS_ENABLED (0 << 5)
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#define ES8311_SYSTEM_REG0D_ANALOG_ADC_BIAS_DISABLED (1 << 5)
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#define ES8311_SYSTEM_REG0D_ANALOG_ADC_REFERENCE_ENABLED (0 << 4)
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#define ES8311_SYSTEM_REG0D_ANALOG_ADC_REFERENCE_DISABLED (1 << 4)
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#define ES8311_SYSTEM_REG0D_ANALOG_DAC_REFERENCE_ENABLED (0 << 3)
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#define ES8311_SYSTEM_REG0D_ANALOG_DAC_REFERENCE_DISABLED (1 << 3)
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#define ES8311_SYSTEM_REG0D_VMID_POWER_DOWN 0x00
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#define ES8311_SYSTEM_REG0D_VMID_START_NORMAL_SPEED 0x01
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#define ES8311_SYSTEM_REG0D_VMID_NORMAL 0x02
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#define ES8311_SYSTEM_REG0D_VMID_START_FAST_SPEED 0x03
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#define ES8311_SYSTEM_REG0E 0x0E /* system, power up/down */
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#define ES8311_SYSTEM_REG0E_PGA_ENABLE (0 << 6)
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#define ES8311_SYSTEM_REG0E_PGA_DISABLE (1 << 6)
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#define ES8311_SYSTEM_REG0E_PDN_MOD_ENABLE (0 << 5)
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#define ES8311_SYSTEM_REG0E_PDN_MOD_DISABLE (1 << 5)
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#define ES8311_SYSTEM_REG0E_MOD_NORMAL (0 << 4)
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#define ES8311_SYSTEM_REG0E_MOD_RESET (1 << 4)
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#define ES8311_SYSTEM_REG0F 0x0F /* system, low power */
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#define ES8311_SYSTEM_REG0F_DAC_NORMAL_MODE (0 << 7)
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#define ES8311_SYSTEM_REG0F_DAC_LOW_POWER_MODE (1 << 7)
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#define ES8311_SYSTEM_REG0F_PGA_NORMAL_MODE (0 << 6)
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#define ES8311_SYSTEM_REG0F_PGA_LOW_POWER_MODE (1 << 6)
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#define ES8311_SYSTEM_REG0F_PGA_OUTPUT_NORMAL_MODE (0 << 5)
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#define ES8311_SYSTEM_REG0F_PGA_OUTPUT_LOW_POWER_MODE (1 << 5)
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#define ES8311_SYSTEM_REG0F_VCMMOD_NORMAL_MODE (0 << 4)
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#define ES8311_SYSTEM_REG0F_VCMMOD_LOW_POWER_MODE (1 << 4)
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#define ES8311_SYSTEM_REG0F_ADC_REFERENCE_NORMAL_MODE (0 << 3)
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#define ES8311_SYSTEM_REG0F_ADC_REFERENCE_LOW_POWER_MODE (1 << 3)
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#define ES8311_SYSTEM_REG0F_DAC_REFERENCE_NORMAL_MODE (0 << 2)
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#define ES8311_SYSTEM_REG0F_DAC_REFERENCE_LOW_POWER_MODE (1 << 2)
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#define ES8311_SYSTEM_REG0F_FLASH_NORMAL_MODE (0 << 1)
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#define ES8311_SYSTEM_REG0F_FLASH_LOW_POWER_MODE (1 << 1)
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#define ES8311_SYSTEM_REG0F_INT1_NORMAL_MODE (0 << 0)
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#define ES8311_SYSTEM_REG0F_INT1_LOW_POWER_MODE (1 << 0)
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#define ES8311_SYSTEM_REG10 0x10 /* system */
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#define ES8311_SYSTEM_REG11 0x11 /* system */
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#define ES8311_SYSTEM_REG12 0x12 /* system, Enable DAC */
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#define ES8311_SYSTEM_REG13 0x13 /* system */
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#define ES8311_SYSTEM_REG14 \
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0x14 /* system, select DMIC, select analog pga gain */
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#define ES8311_SYSTEM_REG14_DMIC_OFF (0 << 6)
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#define ES8311_SYSTEM_REG14_DMIC_AND_DMIC_SDA (1 << 6)
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#define ES8311_SYSTEM_REG14_NO_MIC (0 << 4)
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#define ES8311_SYSTEM_REG14_MIC1 (1 << 4)
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#define ES8311_SYSTEM_REG14_MIC2 (2 << 4)
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#define ES8311_SYSTEM_REG14_MIC1_MIC2 (3 << 4)
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#define ES8311_SYSTEM_REG14_GAIN_0DB 0
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#define ES8311_SYSTEM_REG14_GAIN_3DB 1
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#define ES8311_SYSTEM_REG14_GAIN_6DB 2
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#define ES8311_SYSTEM_REG14_GAIN_9DB 3
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#define ES8311_SYSTEM_REG14_GAIN_12DB 4
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#define ES8311_SYSTEM_REG14_GAIN_15DB 5
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#define ES8311_SYSTEM_REG14_GAIN_18DB 6
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#define ES8311_SYSTEM_REG14_GAIN_21DB 7
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#define ES8311_SYSTEM_REG14_GAIN_24DB 8
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#define ES8311_SYSTEM_REG14_GAIN_27DB 9
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#define ES8311_SYSTEM_REG14_GAIN_30DB 10
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/*
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* ADC
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*/
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#define ES8311_ADC_REG15 0x15 /* ADC, adc ramp rate, dmic sense */
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#define ES8311_ADC_REG16 0x16 /* ADC */
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#define ES8311_ADC_REG16_ADC_RAM_CLR (1 << 3)
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#define ES8311_ADC_REG17 0x17 /* ADC, volume */
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#define ES8311_ADC_REG18 0x18 /* ADC, alc enable and winsize */
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#define ES8311_ADC_REG18_AUTO_LEVEL_CONTROL_DISABLE (0 << 7)
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#define ES8311_ADC_REG18_AUTO_LEVEL_CONTROL_ENABLE (1 << 7)
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#define ES8311_ADC_REG18_AUTO_MUTE_DISABLE (0 << 6)
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#define ES8311_ADC_REG18_AUTO_MUTE_ENABLE (1 << 6)
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#define ES8311_ADC_REG18_0_25DB_PER_2LRCK 0x00
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#define ES8311_ADC_REG18_0_25DB_PER_4LRCK 0x01
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#define ES8311_ADC_REG18_0_25DB_PER_8LRCK 0x02
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#define ES8311_ADC_REG18_0_25DB_PER_16LRCK 0x03
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#define ES8311_ADC_REG18_0_25DB_PER_32LRCK 0x04
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#define ES8311_ADC_REG18_0_25DB_PER_64LRCK 0x05
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#define ES8311_ADC_REG18_0_25DB_PER_128LRCK 0x06
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#define ES8311_ADC_REG18_0_25DB_PER_256LRCK 0x07
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#define ES8311_ADC_REG18_0_25DB_PER_512LRCK 0x08
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#define ES8311_ADC_REG18_0_25DB_PER_1024LRCK 0x09
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#define ES8311_ADC_REG18_0_25DB_PER_2048LRCK 0x0A
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#define ES8311_ADC_REG18_0_25DB_PER_4096LRCK 0x0B
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#define ES8311_ADC_REG18_0_25DB_PER_8192LRCK 0x0C
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#define ES8311_ADC_REG18_0_25DB_PER_16384LRCK 0x0D
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#define ES8311_ADC_REG18_0_25DB_PER_32768LRCK 0x0E
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#define ES8311_ADC_REG18_0_25DB_PER_65536LRCK 0x0F
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#define ES8311_ADC_REG19 0x19 /* ADC, alc maxlevel */
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#define ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_30_1DB (0x00 << 4)
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#define ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_24_1DB (0x01 << 4)
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#define ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_20_6DB (0x02 << 4)
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#define ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_18_1DB (0x03 << 4)
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#define ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_16_1DB (0x04 << 4)
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#define ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_14_5DB (0x05 << 4)
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#define ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_13_2DB (0x06 << 4)
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#define ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_12_0DB (0x07 << 4)
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#define ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_11_0DB (0x08 << 4)
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#define ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_10_1DB (0x09 << 4)
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#define ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_9_3DB (0x0A << 4)
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#define ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_8_5DB (0x0B << 4)
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#define ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_7_8DB (0x0C << 4)
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#define ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_7_2DB (0x0D << 4)
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#define ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_6_6DB (0x0E << 4)
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#define ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_6_0DB (0x0F << 4)
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#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_30_1DB (0x00 << 0)
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#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_24_1DB (0x01 << 0)
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#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_20_6DB (0x02 << 0)
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#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_18_1DB (0x03 << 0)
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#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_16_1DB (0x04 << 0)
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#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_14_5DB (0x05 << 0)
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#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_13_2DB (0x06 << 0)
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#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_12_0DB (0x07 << 0)
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#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_11_0DB (0x08 << 0)
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#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_10_1DB (0x09 << 0)
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#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_9_3DB (0x0A << 0)
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#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_8_5DB (0x0B << 0)
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#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_7_8DB (0x0C << 0)
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#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_7_2DB (0x0D << 0)
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#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_6_6DB (0x0E << 0)
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#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_6_0DB (0x0F << 0)
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#define ES8311_ADC_REG1A 0x1A /* ADC, alc automute */
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#define ES8311_ADC_REG1A_AUTOMUTE_2048_SAMPLES (0x00 << 4)
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#define ES8311_ADC_REG1A_AUTOMUTE_4096_SAMPLES (0x01 << 4)
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#define ES8311_ADC_REG1A_AUTOMUTE_6144_SAMPLES (0x02 << 4)
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#define ES8311_ADC_REG1A_AUTOMUTE_8192_SAMPLES (0x03 << 4)
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#define ES8311_ADC_REG1A_AUTOMUTE_10240_SAMPLES (0x04 << 4)
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#define ES8311_ADC_REG1A_AUTOMUTE_12288_SAMPLES (0x05 << 4)
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#define ES8311_ADC_REG1A_AUTOMUTE_14336_SAMPLES (0x06 << 4)
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#define ES8311_ADC_REG1A_AUTOMUTE_16384_SAMPLES (0x07 << 4)
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#define ES8311_ADC_REG1A_AUTOMUTE_18432_SAMPLES (0x08 << 4)
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#define ES8311_ADC_REG1A_AUTOMUTE_20480_SAMPLES (0x09 << 4)
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#define ES8311_ADC_REG1A_AUTOMUTE_22528_SAMPLES (0x0A << 4)
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#define ES8311_ADC_REG1A_AUTOMUTE_24576_SAMPLES (0x0B << 4)
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#define ES8311_ADC_REG1A_AUTOMUTE_26624_SAMPLES (0x0C << 4)
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#define ES8311_ADC_REG1A_AUTOMUTE_28672_SAMPLES (0x0D << 4)
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#define ES8311_ADC_REG1A_AUTOMUTE_30720_SAMPLES (0x0E << 4)
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#define ES8311_ADC_REG1A_AUTOMUTE_32768_SAMPLES (0x0F << 4)
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#define ES8311_ADC_REG1A_AUTOMUTE_NEG_96DB (0x00 << 0)
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#define ES8311_ADC_REG1A_AUTOMUTE_NEG_90DB (0x01 << 0)
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#define ES8311_ADC_REG1A_AUTOMUTE_NEG_84DB (0x02 << 0)
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#define ES8311_ADC_REG1A_AUTOMUTE_NEG_78DB (0x03 << 0)
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#define ES8311_ADC_REG1A_AUTOMUTE_NEG_72DB (0x04 << 0)
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#define ES8311_ADC_REG1A_AUTOMUTE_NEG_66DB (0x05 << 0)
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#define ES8311_ADC_REG1A_AUTOMUTE_NEG_60DB (0x06 << 0)
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#define ES8311_ADC_REG1A_AUTOMUTE_NEG_54DB (0x07 << 0)
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#define ES8311_ADC_REG1A_AUTOMUTE_NEG_51DB (0x08 << 0)
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#define ES8311_ADC_REG1A_AUTOMUTE_NEG_48DB (0x09 << 0)
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#define ES8311_ADC_REG1A_AUTOMUTE_NEG_45DB (0x0A << 0)
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#define ES8311_ADC_REG1A_AUTOMUTE_NEG_42DB (0x0B << 0)
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#define ES8311_ADC_REG1A_AUTOMUTE_NEG_39DB (0x0C << 0)
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#define ES8311_ADC_REG1A_AUTOMUTE_NEG_36DB (0x0D << 0)
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#define ES8311_ADC_REG1A_AUTOMUTE_NEG_33DB (0x0E << 0)
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#define ES8311_ADC_REG1A_AUTOMUTE_NEG_30DB (0x0F << 0)
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#define ES8311_ADC_REG1B 0x1B /* ADC, alc automute, adc hpf s1 */
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// bits 4:0 have ADCHPF stage 1 coefficient - reg1b
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#define ES8311_ADC_REG1C 0x1C /* ADC, equalizer, hpf s2 */
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#define ES8311_ADC_REG1C_ADCEQ_NORMAL (0 << 6)
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#define ES8311_ADC_REG1C_ADCEQ_BYPASS (1 << 6)
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#define ES8311_ADC_REG1C_HPF_FREEZE_OFFSET (0 << 5)
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#define ES8311_ADC_REG1C_HPF_DYNAMIC_HPF (1 << 5)
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// bits 4:0 have ADCHPF stage 2 coefficient - reg1c
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/*
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reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
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reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
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reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
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reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
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reg1d - ADCEQ_A1[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
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reg1d - ADCEQ_A1[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
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reg1d - ADCEQ_A1[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
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reg1d - ADCEQ_A1[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
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reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
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reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
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reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
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reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
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reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
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*/
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/*
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* DAC
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*/
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#define ES8311_DAC_REG31 0x31 /* DAC, mute */
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#define ES8311_DAC_REG32 0x32 /* DAC, volume */
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#define ES8311_DAC_REG33 0x33 /* DAC, offset */
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#define ES8311_DAC_REG34 0x34 /* DAC, drc enable, drc winsize */
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#define ES8311_DAC_REG35 0x35 /* DAC, drc maxlevel, minilevel */
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#define ES8311_DAC_REG37 0x37 /* DAC, ramprate */
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/*
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*GPIO
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*/
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#define ES8311_GPIO_REG44 0x44 /* GPIO, dac2adc for test */
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#define ES8311_GP_REG45 0x45 /* GP CONTROL */
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/*
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* CHIP
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*/
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#define ES8311_CHD1_REGFD 0xFD /* CHIP ID1 */
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#define ES8311_CHD2_REGFE 0xFE /* CHIP ID2 */
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#define ES8311_CHVER_REGFF 0xFF /* VERSION */
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#define ES8311_CHD1_REGFD 0xFD /* CHIP ID1 */
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#define ES8311_MAX_REGISTER 0xFF
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typedef enum {
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ES8311_MIC_GAIN_MIN = -1,
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ES8311_MIC_GAIN_0DB,
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ES8311_MIC_GAIN_6DB,
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ES8311_MIC_GAIN_12DB,
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ES8311_MIC_GAIN_18DB,
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ES8311_MIC_GAIN_24DB,
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ES8311_MIC_GAIN_30DB,
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ES8311_MIC_GAIN_36DB,
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ES8311_MIC_GAIN_42DB,
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ES8311_MIC_GAIN_MAX
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} es8311_mic_gain_t;
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// ----------------------
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// Timing Constants (milliseconds)
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// ----------------------
|
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#define ES8311_RESET_DELAY_MS 20
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#define ES8311_POWER_DELAY_MS 10
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#define ES8311_STARTUP_DELAY_MS 50
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// ----------------------
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// Beep Configuration
|
|
// ----------------------
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#define ES8311_BEEP_DURATION_SAMPLES 4410 // 100ms at 44.1kHz
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#define ES8311_BEEP_AMPLITUDE 12000 // ~36% of 16-bit max
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#define ES8311_BEEP_HALF_PERIOD 20 // ~2.2kHz tone
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void es8311_init(void);
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void es8311_set_dac_volume(float vol);
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void es8311_set_adc_volume(float vol);
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int audio_write(const int16_t *samples, size_t count);
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int audio_read(int16_t *samples, size_t count);
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void audio_beep(void);
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void audio_test_tone(void);
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int es8311_write(uint8_t reg, uint8_t val);
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uint8_t es8311_read(uint8_t reg);
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void es8311_verify_init(void);
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