From a9c67372ad45e03a4cc9e97d657ed2ea51466ca2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bruno=20Ryb=C3=A1rsky?= Date: Fri, 26 Jun 2026 00:25:59 +0200 Subject: [PATCH] init --- .cproject | 290 + .mrs/meshcorenortos.mrs-workspace | 27 + .project | 42 + .template | 27 + Core/core_riscv.c | 392 + Core/core_riscv.h | 599 + Debug/debug.c | 253 + Debug/debug.h | 55 + Ld/Link.ld | 1 + Peripheral/inc/ch32v30x.h | 6637 ++++++ Peripheral/inc/ch32v30x_adc.h | 230 + Peripheral/inc/ch32v30x_bkp.h | 99 + Peripheral/inc/ch32v30x_can.h | 376 + Peripheral/inc/ch32v30x_crc.h | 39 + Peripheral/inc/ch32v30x_dac.h | 122 + Peripheral/inc/ch32v30x_dbgmcu.h | 60 + Peripheral/inc/ch32v30x_dma.h | 270 + Peripheral/inc/ch32v30x_dvp.h | 69 + Peripheral/inc/ch32v30x_eth.h | 1338 ++ Peripheral/inc/ch32v30x_exti.h | 92 + Peripheral/inc/ch32v30x_flash.h | 148 + Peripheral/inc/ch32v30x_fsmc.h | 268 + Peripheral/inc/ch32v30x_gpio.h | 196 + Peripheral/inc/ch32v30x_i2c.h | 439 + Peripheral/inc/ch32v30x_iwdg.h | 58 + Peripheral/inc/ch32v30x_misc.h | 93 + Peripheral/inc/ch32v30x_opa.h | 77 + Peripheral/inc/ch32v30x_pwr.h | 77 + Peripheral/inc/ch32v30x_rcc.h | 464 + Peripheral/inc/ch32v30x_rng.h | 43 + Peripheral/inc/ch32v30x_rtc.h | 56 + Peripheral/inc/ch32v30x_sdio.h | 266 + Peripheral/inc/ch32v30x_spi.h | 231 + Peripheral/inc/ch32v30x_tim.h | 517 + Peripheral/inc/ch32v30x_usart.h | 195 + Peripheral/inc/ch32v30x_usb.h | 834 + Peripheral/inc/ch32v30x_wwdg.h | 44 + Peripheral/src/ch32v30x_adc.c | 1182 + Peripheral/src/ch32v30x_bkp.c | 244 + Peripheral/src/ch32v30x_can.c | 1297 ++ Peripheral/src/ch32v30x_crc.c | 100 + Peripheral/src/ch32v30x_dac.c | 304 + Peripheral/src/ch32v30x_dbgmcu.c | 129 + Peripheral/src/ch32v30x_dma.c | 692 + Peripheral/src/ch32v30x_dvp.c | 135 + Peripheral/src/ch32v30x_eth.c | 2524 +++ Peripheral/src/ch32v30x_exti.c | 182 + Peripheral/src/ch32v30x_flash.c | 1226 ++ Peripheral/src/ch32v30x_fsmc.c | 378 + Peripheral/src/ch32v30x_gpio.c | 895 + Peripheral/src/ch32v30x_i2c.c | 1012 + Peripheral/src/ch32v30x_iwdg.c | 123 + Peripheral/src/ch32v30x_misc.c | 105 + Peripheral/src/ch32v30x_opa.c | 86 + Peripheral/src/ch32v30x_pwr.c | 361 + Peripheral/src/ch32v30x_rcc.c | 1477 ++ Peripheral/src/ch32v30x_rng.c | 154 + Peripheral/src/ch32v30x_rtc.c | 315 + Peripheral/src/ch32v30x_sdio.c | 672 + Peripheral/src/ch32v30x_spi.c | 668 + Peripheral/src/ch32v30x_tim.c | 2362 ++ Peripheral/src/ch32v30x_usart.c | 783 + Peripheral/src/ch32v30x_wwdg.c | 141 + Startup/startup_ch32v30x_D8.S | 356 + Startup/startup_ch32v30x_D8C.S | 374 + User/ch32v30x_conf.h | 45 + User/ch32v30x_it.c | 46 + User/ch32v30x_it.h | 20 + User/lib/adc/temperature.c | 253 + User/lib/adc/temperature.h | 113 + User/lib/base64.c | 23 + User/lib/base64.h | 8 + User/lib/cifra/aes.c | 415 + User/lib/cifra/aes.h | 158 + User/lib/cifra/bitops.h | 294 + User/lib/cifra/blockwise.c | 195 + User/lib/cifra/blockwise.h | 147 + User/lib/cifra/cf_config.h | 59 + User/lib/cifra/chash.c | 28 + User/lib/cifra/chash.h | 137 + User/lib/cifra/handy.h | 86 + User/lib/cifra/hmac.c | 117 + User/lib/cifra/hmac.h | 82 + User/lib/cifra/prp.h | 64 + User/lib/cifra/sha2.h | 89 + User/lib/cifra/sha256.c | 177 + User/lib/cifra/tassert.h | 32 + User/lib/config.c | 274 + User/lib/config.h | 80 + User/lib/monocypher/monocypher-ed25519.c | 503 + User/lib/monocypher/monocypher-ed25519.h | 140 + User/lib/monocypher/monocypher.c | 2988 +++ User/lib/monocypher/monocypher.h | 321 + User/lib/rtc/rtc.c | 292 + User/lib/rtc/rtc.h | 95 + User/lib/telemetry/telemetry.c | 0 User/lib/telemetry/telemetry.h | 93 + User/main.c | 217 + User/meshcore/meshcore.c | 79 + User/meshcore/meshcore.h | 16 + User/meshcore/meshframing.c | 562 + User/meshcore/meshframing.h | 46 + User/meshcore/packets/ack.c | 43 + User/meshcore/packets/ack.h | 8 + User/meshcore/packets/advert.c | 302 + User/meshcore/packets/advert.h | 14 + User/meshcore/packets/anonymous.c | 234 + User/meshcore/packets/anonymous.h | 11 + User/meshcore/packets/control.c | 148 + User/meshcore/packets/control.h | 16 + User/meshcore/packets/custom.c | 3 + User/meshcore/packets/custom.h | 5 + User/meshcore/packets/encrypted.c | 837 + User/meshcore/packets/encrypted.h | 30 + User/meshcore/packets/group.c | 107 + User/meshcore/packets/group.h | 13 + User/meshcore/packets/multipart.c | 4 + User/meshcore/packets/multipart.h | 4 + User/meshcore/packets/trace.c | 4 + User/meshcore/packets/trace.h | 5 + User/meshcore/packetstructs.h | 248 + User/meshcore/stats.c | 6 + User/meshcore/stats.h | 11 + User/sx1262.c | 991 + User/sx1262.h | 452 + User/system_ch32v30x.c | 1036 + User/system_ch32v30x.h | 32 + User/util/hexdump.c | 39 + User/util/hexdump.h | 11 + User/util/log.h | 33 + meshcorenortos.launch | 62 + meshcorenortos.wvproj | 421 + obj/Core/core_riscv.d | 1 + obj/Core/core_riscv.o | Bin 0 -> 20792 bytes obj/Core/subdir.mk | 29 + obj/Debug/debug.d | 90 + obj/Debug/debug.o | Bin 0 -> 30800 bytes obj/Debug/subdir.mk | 29 + obj/Peripheral/src/ch32v30x_adc.d | 88 + obj/Peripheral/src/ch32v30x_adc.o | Bin 0 -> 84128 bytes obj/Peripheral/src/ch32v30x_bkp.d | 88 + obj/Peripheral/src/ch32v30x_bkp.o | Bin 0 -> 31292 bytes obj/Peripheral/src/ch32v30x_can.d | 88 + obj/Peripheral/src/ch32v30x_can.o | Bin 0 -> 95052 bytes obj/Peripheral/src/ch32v30x_crc.d | 88 + obj/Peripheral/src/ch32v30x_crc.o | Bin 0 -> 17636 bytes obj/Peripheral/src/ch32v30x_dac.d | 88 + obj/Peripheral/src/ch32v30x_dac.o | Bin 0 -> 31416 bytes obj/Peripheral/src/ch32v30x_dbgmcu.d | 88 + obj/Peripheral/src/ch32v30x_dbgmcu.o | Bin 0 -> 17536 bytes obj/Peripheral/src/ch32v30x_dma.d | 88 + obj/Peripheral/src/ch32v30x_dma.o | Bin 0 -> 33272 bytes obj/Peripheral/src/ch32v30x_dvp.d | 91 + obj/Peripheral/src/ch32v30x_dvp.o | Bin 0 -> 18672 bytes obj/Peripheral/src/ch32v30x_eth.d | 91 + obj/Peripheral/src/ch32v30x_eth.o | Bin 0 -> 172668 bytes obj/Peripheral/src/ch32v30x_exti.d | 88 + obj/Peripheral/src/ch32v30x_exti.o | Bin 0 -> 23464 bytes obj/Peripheral/src/ch32v30x_flash.d | 88 + obj/Peripheral/src/ch32v30x_flash.o | Bin 0 -> 105884 bytes obj/Peripheral/src/ch32v30x_fsmc.d | 88 + obj/Peripheral/src/ch32v30x_fsmc.o | Bin 0 -> 38360 bytes obj/Peripheral/src/ch32v30x_gpio.d | 88 + obj/Peripheral/src/ch32v30x_gpio.o | Bin 0 -> 61280 bytes obj/Peripheral/src/ch32v30x_i2c.d | 88 + obj/Peripheral/src/ch32v30x_i2c.o | Bin 0 -> 65412 bytes obj/Peripheral/src/ch32v30x_iwdg.d | 88 + obj/Peripheral/src/ch32v30x_iwdg.o | Bin 0 -> 18264 bytes obj/Peripheral/src/ch32v30x_misc.d | 88 + obj/Peripheral/src/ch32v30x_misc.o | Bin 0 -> 23744 bytes obj/Peripheral/src/ch32v30x_opa.d | 91 + obj/Peripheral/src/ch32v30x_opa.o | Bin 0 -> 17912 bytes obj/Peripheral/src/ch32v30x_pwr.d | 88 + obj/Peripheral/src/ch32v30x_pwr.o | Bin 0 -> 40168 bytes obj/Peripheral/src/ch32v30x_rcc.d | 88 + obj/Peripheral/src/ch32v30x_rcc.o | Bin 0 -> 90764 bytes obj/Peripheral/src/ch32v30x_rng.d | 91 + obj/Peripheral/src/ch32v30x_rng.o | Bin 0 -> 19012 bytes obj/Peripheral/src/ch32v30x_rtc.d | 88 + obj/Peripheral/src/ch32v30x_rtc.o | Bin 0 -> 36784 bytes obj/Peripheral/src/ch32v30x_sdio.d | 88 + obj/Peripheral/src/ch32v30x_sdio.o | Bin 0 -> 47324 bytes obj/Peripheral/src/ch32v30x_spi.d | 88 + obj/Peripheral/src/ch32v30x_spi.o | Bin 0 -> 52456 bytes obj/Peripheral/src/ch32v30x_tim.d | 88 + obj/Peripheral/src/ch32v30x_tim.o | Bin 0 -> 174412 bytes obj/Peripheral/src/ch32v30x_usart.d | 88 + obj/Peripheral/src/ch32v30x_usart.o | Bin 0 -> 59668 bytes obj/Peripheral/src/ch32v30x_wwdg.d | 88 + obj/Peripheral/src/ch32v30x_wwdg.o | Bin 0 -> 20296 bytes obj/Peripheral/src/subdir.mk | 104 + obj/Startup/startup_ch32v30x_D8C.d | 1 + obj/Startup/startup_ch32v30x_D8C.o | Bin 0 -> 10028 bytes obj/Startup/subdir.mk | 29 + obj/User/ch32v30x_it.d | 90 + obj/User/ch32v30x_it.o | Bin 0 -> 14600 bytes obj/User/lib/adc/subdir.mk | 29 + obj/User/lib/adc/temperature.d | 91 + obj/User/lib/adc/temperature.o | Bin 0 -> 40780 bytes obj/User/lib/base64.d | 3 + obj/User/lib/base64.o | Bin 0 -> 9096 bytes obj/User/lib/cifra/aes.d | 16 + obj/User/lib/cifra/aes.o | Bin 0 -> 80680 bytes obj/User/lib/cifra/blockwise.d | 11 + obj/User/lib/cifra/blockwise.o | Bin 0 -> 42684 bytes obj/User/lib/cifra/chash.d | 9 + obj/User/lib/cifra/chash.o | Bin 0 -> 16352 bytes obj/User/lib/cifra/hmac.d | 16 + obj/User/lib/cifra/hmac.o | Bin 0 -> 35244 bytes obj/User/lib/cifra/sha256.d | 16 + obj/User/lib/cifra/sha256.o | Bin 0 -> 42664 bytes obj/User/lib/cifra/subdir.mk | 41 + obj/User/lib/config.d | 117 + obj/User/lib/config.o | Bin 0 -> 67468 bytes obj/User/lib/monocypher/monocypher-ed25519.d | 8 + obj/User/lib/monocypher/monocypher-ed25519.o | Bin 0 -> 116872 bytes obj/User/lib/monocypher/monocypher.d | 4 + obj/User/lib/monocypher/monocypher.o | Bin 0 -> 901692 bytes obj/User/lib/monocypher/subdir.mk | 32 + obj/User/lib/rtc/rtc.d | 91 + obj/User/lib/rtc/rtc.o | Bin 0 -> 60172 bytes obj/User/lib/rtc/subdir.mk | 29 + obj/User/lib/subdir.mk | 32 + obj/User/lib/telemetry/subdir.mk | 29 + obj/User/lib/telemetry/telemetry.d | 1 + obj/User/lib/telemetry/telemetry.o | Bin 0 -> 1012 bytes obj/User/main.d | 165 + obj/User/main.o | Bin 0 -> 53048 bytes obj/User/meshcore/meshcore.d | 69 + obj/User/meshcore/meshcore.o | Bin 0 -> 28404 bytes obj/User/meshcore/meshframing.d | 127 + obj/User/meshcore/meshframing.o | Bin 0 -> 87616 bytes obj/User/meshcore/packets/ack.d | 31 + obj/User/meshcore/packets/ack.o | Bin 0 -> 22212 bytes obj/User/meshcore/packets/advert.d | 130 + obj/User/meshcore/packets/advert.o | Bin 0 -> 52612 bytes obj/User/meshcore/packets/anonymous.d | 130 + obj/User/meshcore/packets/anonymous.o | Bin 0 -> 56320 bytes obj/User/meshcore/packets/control.d | 37 + obj/User/meshcore/packets/control.o | Bin 0 -> 41480 bytes obj/User/meshcore/packets/custom.d | 4 + obj/User/meshcore/packets/custom.o | Bin 0 -> 2228 bytes obj/User/meshcore/packets/encrypted.d | 142 + obj/User/meshcore/packets/encrypted.o | Bin 0 -> 133464 bytes obj/User/meshcore/packets/group.d | 121 + obj/User/meshcore/packets/group.o | Bin 0 -> 35716 bytes obj/User/meshcore/packets/multipart.d | 7 + obj/User/meshcore/packets/multipart.o | Bin 0 -> 2236 bytes obj/User/meshcore/packets/subdir.mk | 53 + obj/User/meshcore/packets/trace.d | 7 + obj/User/meshcore/packets/trace.o | Bin 0 -> 2228 bytes obj/User/meshcore/stats.d | 6 + obj/User/meshcore/stats.o | Bin 0 -> 4780 bytes obj/User/meshcore/subdir.mk | 35 + obj/User/subdir.mk | 38 + obj/User/sx1262.d | 93 + obj/User/sx1262.o | Bin 0 -> 179668 bytes obj/User/system_ch32v30x.d | 88 + obj/User/system_ch32v30x.o | Bin 0 -> 27660 bytes obj/User/util/hexdump.d | 3 + obj/User/util/hexdump.o | Bin 0 -> 22672 bytes obj/User/util/subdir.mk | 29 + obj/makefile | 84 + obj/meshcorenortos.elf | Bin 0 -> 694156 bytes obj/meshcorenortos.hex | 3657 ++++ obj/meshcorenortos.lst | 19482 +++++++++++++++++ obj/meshcorenortos.map | 4201 ++++ obj/objects.mk | 9 + obj/sources.mk | 43 + 269 files changed, 78764 insertions(+) create mode 100644 .cproject create mode 100644 .mrs/meshcorenortos.mrs-workspace create mode 100644 .project create mode 100644 .template create mode 100644 Core/core_riscv.c create mode 100644 Core/core_riscv.h create mode 100644 Debug/debug.c create mode 100644 Debug/debug.h create mode 100644 Ld/Link.ld create mode 100644 Peripheral/inc/ch32v30x.h create mode 100644 Peripheral/inc/ch32v30x_adc.h create mode 100644 Peripheral/inc/ch32v30x_bkp.h create mode 100644 Peripheral/inc/ch32v30x_can.h create mode 100644 Peripheral/inc/ch32v30x_crc.h create mode 100644 Peripheral/inc/ch32v30x_dac.h create mode 100644 Peripheral/inc/ch32v30x_dbgmcu.h create mode 100644 Peripheral/inc/ch32v30x_dma.h create mode 100644 Peripheral/inc/ch32v30x_dvp.h create mode 100644 Peripheral/inc/ch32v30x_eth.h create mode 100644 Peripheral/inc/ch32v30x_exti.h create mode 100644 Peripheral/inc/ch32v30x_flash.h create mode 100644 Peripheral/inc/ch32v30x_fsmc.h create mode 100644 Peripheral/inc/ch32v30x_gpio.h create mode 100644 Peripheral/inc/ch32v30x_i2c.h create mode 100644 Peripheral/inc/ch32v30x_iwdg.h create mode 100644 Peripheral/inc/ch32v30x_misc.h create mode 100644 Peripheral/inc/ch32v30x_opa.h create mode 100644 Peripheral/inc/ch32v30x_pwr.h create mode 100644 Peripheral/inc/ch32v30x_rcc.h create mode 100644 Peripheral/inc/ch32v30x_rng.h create mode 100644 Peripheral/inc/ch32v30x_rtc.h create mode 100644 Peripheral/inc/ch32v30x_sdio.h create mode 100644 Peripheral/inc/ch32v30x_spi.h create mode 100644 Peripheral/inc/ch32v30x_tim.h create mode 100644 Peripheral/inc/ch32v30x_usart.h create mode 100644 Peripheral/inc/ch32v30x_usb.h create mode 100644 Peripheral/inc/ch32v30x_wwdg.h create mode 100644 Peripheral/src/ch32v30x_adc.c create mode 100644 Peripheral/src/ch32v30x_bkp.c create mode 100644 Peripheral/src/ch32v30x_can.c create mode 100644 Peripheral/src/ch32v30x_crc.c create mode 100644 Peripheral/src/ch32v30x_dac.c create mode 100644 Peripheral/src/ch32v30x_dbgmcu.c create mode 100644 Peripheral/src/ch32v30x_dma.c create mode 100644 Peripheral/src/ch32v30x_dvp.c create mode 100644 Peripheral/src/ch32v30x_eth.c create mode 100644 Peripheral/src/ch32v30x_exti.c create mode 100644 Peripheral/src/ch32v30x_flash.c create mode 100644 Peripheral/src/ch32v30x_fsmc.c create mode 100644 Peripheral/src/ch32v30x_gpio.c create mode 100644 Peripheral/src/ch32v30x_i2c.c create mode 100644 Peripheral/src/ch32v30x_iwdg.c create mode 100644 Peripheral/src/ch32v30x_misc.c create mode 100644 Peripheral/src/ch32v30x_opa.c create mode 100644 Peripheral/src/ch32v30x_pwr.c create mode 100644 Peripheral/src/ch32v30x_rcc.c create mode 100644 Peripheral/src/ch32v30x_rng.c create mode 100644 Peripheral/src/ch32v30x_rtc.c create mode 100644 Peripheral/src/ch32v30x_sdio.c create mode 100644 Peripheral/src/ch32v30x_spi.c create mode 100644 Peripheral/src/ch32v30x_tim.c create mode 100644 Peripheral/src/ch32v30x_usart.c create mode 100644 Peripheral/src/ch32v30x_wwdg.c create mode 100644 Startup/startup_ch32v30x_D8.S create mode 100644 Startup/startup_ch32v30x_D8C.S create mode 100644 User/ch32v30x_conf.h create mode 100644 User/ch32v30x_it.c create mode 100644 User/ch32v30x_it.h create mode 100644 User/lib/adc/temperature.c create mode 100644 User/lib/adc/temperature.h create mode 100644 User/lib/base64.c create mode 100644 User/lib/base64.h create mode 100644 User/lib/cifra/aes.c create mode 100644 User/lib/cifra/aes.h create mode 100644 User/lib/cifra/bitops.h create mode 100644 User/lib/cifra/blockwise.c create mode 100644 User/lib/cifra/blockwise.h create mode 100644 User/lib/cifra/cf_config.h create mode 100644 User/lib/cifra/chash.c create mode 100644 User/lib/cifra/chash.h create mode 100644 User/lib/cifra/handy.h create mode 100644 User/lib/cifra/hmac.c create mode 100644 User/lib/cifra/hmac.h create mode 100644 User/lib/cifra/prp.h create mode 100644 User/lib/cifra/sha2.h create mode 100644 User/lib/cifra/sha256.c create mode 100644 User/lib/cifra/tassert.h create mode 100644 User/lib/config.c create mode 100644 User/lib/config.h create mode 100644 User/lib/monocypher/monocypher-ed25519.c create mode 100644 User/lib/monocypher/monocypher-ed25519.h create mode 100644 User/lib/monocypher/monocypher.c create mode 100644 User/lib/monocypher/monocypher.h create mode 100644 User/lib/rtc/rtc.c create mode 100644 User/lib/rtc/rtc.h create mode 100644 User/lib/telemetry/telemetry.c create mode 100644 User/lib/telemetry/telemetry.h create mode 100644 User/main.c create mode 100644 User/meshcore/meshcore.c create mode 100644 User/meshcore/meshcore.h create mode 100644 User/meshcore/meshframing.c create mode 100644 User/meshcore/meshframing.h create mode 100644 User/meshcore/packets/ack.c create mode 100644 User/meshcore/packets/ack.h create mode 100644 User/meshcore/packets/advert.c create mode 100644 User/meshcore/packets/advert.h create mode 100644 User/meshcore/packets/anonymous.c create mode 100644 User/meshcore/packets/anonymous.h create mode 100644 User/meshcore/packets/control.c create mode 100644 User/meshcore/packets/control.h create mode 100644 User/meshcore/packets/custom.c create mode 100644 User/meshcore/packets/custom.h create mode 100644 User/meshcore/packets/encrypted.c create mode 100644 User/meshcore/packets/encrypted.h create mode 100644 User/meshcore/packets/group.c create mode 100644 User/meshcore/packets/group.h create mode 100644 User/meshcore/packets/multipart.c create mode 100644 User/meshcore/packets/multipart.h create mode 100644 User/meshcore/packets/trace.c create mode 100644 User/meshcore/packets/trace.h create mode 100644 User/meshcore/packetstructs.h create mode 100644 User/meshcore/stats.c create mode 100644 User/meshcore/stats.h create mode 100644 User/sx1262.c create mode 100644 User/sx1262.h create mode 100644 User/system_ch32v30x.c create mode 100644 User/system_ch32v30x.h create mode 100644 User/util/hexdump.c create mode 100644 User/util/hexdump.h create mode 100644 User/util/log.h create mode 100644 meshcorenortos.launch create mode 100644 meshcorenortos.wvproj create mode 100644 obj/Core/core_riscv.d create mode 100644 obj/Core/core_riscv.o create mode 100644 obj/Core/subdir.mk create mode 100644 obj/Debug/debug.d create mode 100644 obj/Debug/debug.o create mode 100644 obj/Debug/subdir.mk create mode 100644 obj/Peripheral/src/ch32v30x_adc.d create mode 100644 obj/Peripheral/src/ch32v30x_adc.o create mode 100644 obj/Peripheral/src/ch32v30x_bkp.d create mode 100644 obj/Peripheral/src/ch32v30x_bkp.o create mode 100644 obj/Peripheral/src/ch32v30x_can.d create mode 100644 obj/Peripheral/src/ch32v30x_can.o create mode 100644 obj/Peripheral/src/ch32v30x_crc.d create mode 100644 obj/Peripheral/src/ch32v30x_crc.o create mode 100644 obj/Peripheral/src/ch32v30x_dac.d create mode 100644 obj/Peripheral/src/ch32v30x_dac.o create mode 100644 obj/Peripheral/src/ch32v30x_dbgmcu.d create mode 100644 obj/Peripheral/src/ch32v30x_dbgmcu.o create mode 100644 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create mode 100644 obj/Peripheral/src/ch32v30x_misc.o create mode 100644 obj/Peripheral/src/ch32v30x_opa.d create mode 100644 obj/Peripheral/src/ch32v30x_opa.o create mode 100644 obj/Peripheral/src/ch32v30x_pwr.d create mode 100644 obj/Peripheral/src/ch32v30x_pwr.o create mode 100644 obj/Peripheral/src/ch32v30x_rcc.d create mode 100644 obj/Peripheral/src/ch32v30x_rcc.o create mode 100644 obj/Peripheral/src/ch32v30x_rng.d create mode 100644 obj/Peripheral/src/ch32v30x_rng.o create mode 100644 obj/Peripheral/src/ch32v30x_rtc.d create mode 100644 obj/Peripheral/src/ch32v30x_rtc.o create mode 100644 obj/Peripheral/src/ch32v30x_sdio.d create mode 100644 obj/Peripheral/src/ch32v30x_sdio.o create mode 100644 obj/Peripheral/src/ch32v30x_spi.d create mode 100644 obj/Peripheral/src/ch32v30x_spi.o create mode 100644 obj/Peripheral/src/ch32v30x_tim.d create mode 100644 obj/Peripheral/src/ch32v30x_tim.o create mode 100644 obj/Peripheral/src/ch32v30x_usart.d create mode 100644 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0000000..f6bacf3 --- /dev/null +++ b/.cproject @@ -0,0 +1,290 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/.mrs/meshcorenortos.mrs-workspace b/.mrs/meshcorenortos.mrs-workspace new file mode 100644 index 0000000..8cadd84 --- /dev/null +++ b/.mrs/meshcorenortos.mrs-workspace @@ -0,0 +1,27 @@ +{ + "folders": [ + { + "path": "." + }, + { + "name": "meshcorenortos", + "path": "/home/bruno/mounriver-studio-projects/meshcorenortos" + } + ], + "settings": { + "mrs.workspace.type": "project", + "mrs.init.arg": "", + "files.associations": { + "*.c": "c", + "*.h": "cpp", + "*.hxx": "cpp", + "*.hpp": "cpp", + "*.c++": "cpp", + "*.cpp": "cpp", + "*.cxx": "cpp", + "*.cc": "cpp", + "*.hh": "cpp", + "*.h++": "cpp" + } + } +} \ No newline at end of file diff --git a/.project b/.project new file mode 100644 index 0000000..6cc3b7d --- /dev/null +++ b/.project @@ -0,0 +1,42 @@ + + + meshcorenortos + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + + + 6 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-*.wvproj + + + + User + 6 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-FreeRTOSConfig.h + + + + \ No newline at end of file diff --git a/.template b/.template new file mode 100644 index 0000000..ee10337 --- /dev/null +++ b/.template @@ -0,0 +1,27 @@ +Vendor=WCH +Toolchain=RISC-V +Series=CH32V307 +RTOS=NoneOS +CalibrateSupport=false +CalibrateCommand= +MCU=CH32V307VCT6 +Link=WCH-Link +PeripheralVersion=2.9 +Description=Website: http://www.wch.cn/products/CH32V307.html?\nROM(byte): 256K, SRAM(byte): 64K, CHIP PINS: 100, GPIO PORTS: 80.\nWCH CH32V3 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools. +TempratureScope=CH32V307VCT6{-40℃~85℃} +ArtifactType=executable +Mcu Type=CH32V30x +Address=0x08000000 +Target Path=obj/meshcorenortos.hex +Exe Path= +Exe Arguments= +CLKSpeed=1 +DebugInterfaceMode=0 +Erase All=true +Program=true +Verify=true +Reset=true +SDIPrintf=false +Disable Power Output=false +Clear CodeFlash=false +Disable Code-Protect=false \ No newline at end of file diff --git a/Core/core_riscv.c b/Core/core_riscv.c new file mode 100644 index 0000000..f9ca871 --- /dev/null +++ b/Core/core_riscv.c @@ -0,0 +1,392 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : core_riscv.c +* Author : WCH +* Version : V1.0.1 +* Date : 2023/11/11 +* Description : RISC-V V4 Core Peripheral Access Layer Source File for CH32V30x +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include + +/* define compiler specific symbols */ +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + + +/********************************************************************* + * @fn __get_FFLAGS + * + * @brief Return the Floating-Point Accrued Exceptions + * + * @return fflags value + */ +uint32_t __get_FFLAGS(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "fflags" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_FFLAGS + * + * @brief Set the Floating-Point Accrued Exceptions + * + * @param value - set FFLAGS value + * + * @return none + */ +void __set_FFLAGS(uint32_t value) +{ + __ASM volatile ("csrw fflags, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_FRM + * + * @brief Return the Floating-Point Dynamic Rounding Mode + * + * @return frm value + */ +uint32_t __get_FRM(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "frm" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_FRM + * + * @brief Set the Floating-Point Dynamic Rounding Mode + * + * @param value - set frm value + * + * @return none + */ +void __set_FRM(uint32_t value) +{ + __ASM volatile ("csrw frm, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_FCSR + * + * @brief Return the Floating-Point Control and Status Register + * + * @return fcsr value + */ +uint32_t __get_FCSR(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "fcsr" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_FCSR + * + * @brief Set the Floating-Point Dynamic Rounding Mode + * + * @param value - set fcsr value + * + * @return none + */ +void __set_FCSR(uint32_t value) +{ + __ASM volatile ("csrw fcsr, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MSTATUS + * + * @brief Return the Machine Status Register + * + * @return mstatus value + */ +uint32_t __get_MSTATUS(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mstatus" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MSTATUS + * + * @brief Set the Machine Status Register + * + * @param value - set mstatus value + * + * @return none + */ +void __set_MSTATUS(uint32_t value) +{ + __ASM volatile ("csrw mstatus, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MISA + * + * @brief Return the Machine ISA Register + * + * @return misa value + */ +uint32_t __get_MISA(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "misa" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MISA + * + * @brief Set the Machine ISA Register + * + * @param value - set misa value + * + * @return none + */ +void __set_MISA(uint32_t value) +{ + __ASM volatile ("csrw misa, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MTVEC + * + * @brief Return the Machine Trap-Vector Base-Address Register + * + * @return mtvec value + */ +uint32_t __get_MTVEC(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mtvec" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MTVEC + * + * @brief Set the Machine Trap-Vector Base-Address Register + * + * @param value - set mtvec value + * + * @return none + */ +void __set_MTVEC(uint32_t value) +{ + __ASM volatile ("csrw mtvec, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MSCRATCH + * + * @brief Return the Machine Seratch Register + * + * @return mscratch value + */ +uint32_t __get_MSCRATCH(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mscratch" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MSCRATCH + * + * @brief Set the Machine Seratch Register + * + * @param value - set mscratch value + * + * @return none + */ +void __set_MSCRATCH(uint32_t value) +{ + __ASM volatile ("csrw mscratch, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MEPC + * + * @brief Return the Machine Exception Program Register + * + * @return mepc value + */ +uint32_t __get_MEPC(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mepc" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Exception Program Register + * + * @return mepc value + */ +void __set_MEPC(uint32_t value) +{ + __ASM volatile ("csrw mepc, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MCAUSE + * + * @brief Return the Machine Cause Register + * + * @return mcause value + */ +uint32_t __get_MCAUSE(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mcause" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Cause Register + * + * @return mcause value + */ +void __set_MCAUSE(uint32_t value) +{ + __ASM volatile ("csrw mcause, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MTVAL + * + * @brief Return the Machine Trap Value Register + * + * @return mtval value + */ +uint32_t __get_MTVAL(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mtval" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __set_MTVAL + * + * @brief Set the Machine Trap Value Register + * + * @return mtval value + */ +void __set_MTVAL(uint32_t value) +{ + __ASM volatile ("csrw mtval, %0" : : "r" (value) ); +} + +/********************************************************************* + * @fn __get_MVENDORID + * + * @brief Return Vendor ID Register + * + * @return mvendorid value + */ +uint32_t __get_MVENDORID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MARCHID + * + * @brief Return Machine Architecture ID Register + * + * @return marchid value + */ +uint32_t __get_MARCHID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "marchid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MIMPID + * + * @brief Return Machine Implementation ID Register + * + * @return mimpid value + */ +uint32_t __get_MIMPID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mimpid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_MHARTID + * + * @brief Return Hart ID Register + * + * @return mhartid value + */ +uint32_t __get_MHARTID(void) +{ + uint32_t result; + + __ASM volatile ( "csrr %0," "mhartid" : "=r" (result) ); + return (result); +} + +/********************************************************************* + * @fn __get_SP + * + * @brief Return SP Register + * + * @return SP value + */ +uint32_t __get_SP(void) +{ + uint32_t result; + + __ASM volatile ( "mv %0," "sp" : "=r"(result) : ); + return (result); +} + diff --git a/Core/core_riscv.h b/Core/core_riscv.h new file mode 100644 index 0000000..cd44ac3 --- /dev/null +++ b/Core/core_riscv.h @@ -0,0 +1,599 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : core_riscv.h +* Author : WCH +* Version : V1.0.2 +* Date : 2025/03/06 +* Description : RISC-V V4 Core Peripheral Access Layer Header File for CH32V30x +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CORE_RISCV_H__ +#define __CORE_RISCV_H__ + +#ifdef __cplusplus + extern "C" { +#endif + +/* IO definitions */ +#ifdef __cplusplus + #define __I volatile /* defines 'read only' permissions */ +#else + #define __I volatile const /* defines 'read only' permissions */ +#endif +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + +/* Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef __I uint64_t vuc64; /* Read Only */ +typedef __I uint32_t vuc32; /* Read Only */ +typedef __I uint16_t vuc16; /* Read Only */ +typedef __I uint8_t vuc8; /* Read Only */ + +typedef const uint64_t uc64; /* Read Only */ +typedef const uint32_t uc32; /* Read Only */ +typedef const uint16_t uc16; /* Read Only */ +typedef const uint8_t uc8; /* Read Only */ + +typedef __I int64_t vsc64; /* Read Only */ +typedef __I int32_t vsc32; /* Read Only */ +typedef __I int16_t vsc16; /* Read Only */ +typedef __I int8_t vsc8; /* Read Only */ + +typedef const int64_t sc64; /* Read Only */ +typedef const int32_t sc32; /* Read Only */ +typedef const int16_t sc16; /* Read Only */ +typedef const int8_t sc8; /* Read Only */ + +typedef __IO uint64_t vu64; +typedef __IO uint32_t vu32; +//typedef __IO uint16_t volatile uint16_t; +//typedef __IO uint8_t volatile uint8_t; + +typedef uint64_t u64; +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef __IO int64_t vs64; +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef int64_t s64; +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +#define RV_STATIC_INLINE static inline + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct{ + __I uint32_t ISR[8]; + __I uint32_t IPR[8]; + __IO uint32_t ITHRESDR; + __IO uint32_t RESERVED; + __IO uint32_t CFGR; + __I uint32_t GISR; + __IO uint8_t VTFIDR[4]; + uint8_t RESERVED0[12]; + __IO uint32_t VTFADDR[4]; + uint8_t RESERVED1[0x90]; + __O uint32_t IENR[8]; + uint8_t RESERVED2[0x60]; + __O uint32_t IRER[8]; + uint8_t RESERVED3[0x60]; + __O uint32_t IPSR[8]; + uint8_t RESERVED4[0x60]; + __O uint32_t IPRR[8]; + uint8_t RESERVED5[0x60]; + __IO uint32_t IACTR[8]; + uint8_t RESERVED6[0xE0]; + __IO uint8_t IPRIOR[256]; + uint8_t RESERVED7[0x810]; + __IO uint32_t SCTLR; +}PFIC_Type; + +/* memory mapped structure for SysTick */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SR; + __IO uint64_t CNT; + __IO uint64_t CMP; +}SysTick_Type; + + +#define PFIC ((PFIC_Type *) 0xE000E000 ) +#define NVIC PFIC +#define NVIC_KEY1 ((uint32_t)0xFA050000) +#define NVIC_KEY2 ((uint32_t)0xBCAF0000) +#define NVIC_KEY3 ((uint32_t)0xBEEF0000) + +#define SysTick ((SysTick_Type *) 0xE000F000) + +/********************************************************************* + * @fn __enable_irq + * + * @brief Enable Global Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq() +{ + __asm volatile ("csrs 0x800, %0" : : "r" (0x88) ); +} + +/********************************************************************* + * @fn __disable_irq + * + * @brief Disable Global Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq() +{ + __asm volatile ("csrc 0x800, %0" : : "r" (0x88) ); + __asm volatile ("fence.i"); +} + +/********************************************************************* + * @fn __NOP + * + * @brief nop + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP() +{ + __asm volatile ("nop"); +} + +/********************************************************************* + * @fn NVIC_EnableIRQ + * + * @brief Enable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_DisableIRQ + * + * @brief Disable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); + __asm volatile ("fence.i"); +} + +/********************************************************************* + * @fn NVIC_GetStatusIRQ + * + * @brief Get Interrupt Enable State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Enable + * 0 - Interrupt Disable + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_GetPendingIRQ + * + * @brief Get Interrupt Pending State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Pending Enable + * 0 - Interrupt Pending Disable + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPendingIRQ + * + * @brief Set Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_ClearPendingIRQ + * + * @brief Clear Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetActive + * + * @brief Get Interrupt Active State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Active + * 0 - Interrupt No Active + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPriority + * + * @brief Set Interrupt Priority + * + * @param IRQn - Interrupt Numbers + * interrupt nesting enable-8 Level(CSR-0x804 bit1 = 1 bit[3:2] = 3) + * priority - bit[7:5] - Preemption Priority + * bit[4:0] - Reserve + * interrupt nesting enable-4 Level(CSR-0x804 bit1 = 1 bit[3:2] = 2) + * priority - bit[7:6] - Preemption Priority + * bit[5] - Sub priority + * bit[4:0] - Reserve + * interrupt nesting enable-2 Level(CSR-0x804 bit1 = 1 bit[3:2] = 1) + * priority - bit[7] - Preemption Priority + * bit[6:5] - Sub priority + * bit[4:0] - Reserve + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * priority - bit[7:5] - Sub priority + * bit[4:0] - Reserve + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) +{ + NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; +} + +/********************************************************************* + * @fn __WFI + * + * @brief Wait for Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) +{ + NVIC->SCTLR &= ~(1<<3); // wfi + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn _SEV + * + * @brief Set Event + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void) +{ + uint32_t t; + + t = NVIC->SCTLR; + NVIC->SCTLR |= (1<<3)|(1<<5); + NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5)); +} + +/********************************************************************* + * @fn _WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void) +{ + NVIC->SCTLR |= (1<<3); + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn __WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) +{ + _SEV(); + _WFE(); + _WFE(); +} + +/********************************************************************* + * @fn SetVTFIRQ + * + * @brief Set VTF Interrupt + * + * @param add - VTF interrupt service function base address. + * IRQn -Interrupt Numbers + * num - VTF Interrupt Numbers + * NewState - DISABLE or ENABLE + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState) +{ + if(num > 3) return ; + + if (NewState != DISABLE) + { + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1); + } + else + { + NVIC->VTFIDR[num] = IRQn; + NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1)); + } +} + +/********************************************************************* + * @fn NVIC_SystemReset + * + * @brief Initiate a system reset request + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void) +{ + NVIC->CFGR = NVIC_KEY3|(1<<7); +} + +/********************************************************************* + * @fn __AMOADD_W + * + * @brief Atomic Add with 32bit value + * Atomically ADD 32bit value with value in memory using amoadd.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ADDed + * + * @return return memory value + add value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoadd.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOAND_W + * + * @brief Atomic And with 32bit value + * Atomically AND 32bit value with value in memory using amoand.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ANDed + * + * @return return memory value & and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoand.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMAX_W + * + * @brief Atomic signed MAX with 32bit value + * Atomically signed max compare 32bit value with value in memory using amomax.d. + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return return the bigger value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amomax.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMAXU_W + * + * @brief Atomic unsigned MAX with 32bit value + * Atomically unsigned max compare 32bit value with value in memory using amomaxu.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return return the bigger value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value) +{ + uint32_t result; + + __asm volatile ("amomaxu.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMIN_W + * + * @brief Atomic signed MIN with 32bit value + * Atomically signed min compare 32bit value with value in memory using amomin.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return return the smaller value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amomin.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMINU_W + * + * @brief Atomic unsigned MIN with 32bit value + * Atomically unsigned min compare 32bit value with value in memory using amominu.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return return the smaller value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value) +{ + uint32_t result; + + __asm volatile ("amominu.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOOR_W + * + * @brief Atomic OR with 32bit value + * Atomically OR 32bit value with value in memory using amoor.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ORed + * + * @return return memory value | and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoor.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOSWAP_W + * + * @brief Atomically swap new 32bit value into memory using amoswap.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * newval - New value to be stored into the address + * + * @return return the original value in memory + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval) +{ + uint32_t result; + + __asm volatile ("amoswap.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(newval) : "memory"); + return result; +} + +/********************************************************************* + * @fn __AMOXOR_W + * + * @brief Atomic XOR with 32bit value + * Atomically XOR 32bit value with value in memory using amoxor.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be XORed + * + * @return return memory value ^ and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoxor.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/* Core_Exported_Functions */ +extern uint32_t __get_FFLAGS(void); +extern void __set_FFLAGS(uint32_t value); +extern uint32_t __get_FRM(void); +extern void __set_FRM(uint32_t value); +extern uint32_t __get_FCSR(void); +extern void __set_FCSR(uint32_t value); +extern uint32_t __get_MSTATUS(void); +extern void __set_MSTATUS(uint32_t value); +extern uint32_t __get_MISA(void); +extern void __set_MISA(uint32_t value); +extern uint32_t __get_MTVEC(void); +extern void __set_MTVEC(uint32_t value); +extern uint32_t __get_MSCRATCH(void); +extern void __set_MSCRATCH(uint32_t value); +extern uint32_t __get_MEPC(void); +extern void __set_MEPC(uint32_t value); +extern uint32_t __get_MCAUSE(void); +extern void __set_MCAUSE(uint32_t value); +extern uint32_t __get_MTVAL(void); +extern void __set_MTVAL(uint32_t value); +extern uint32_t __get_MVENDORID(void); +extern uint32_t __get_MARCHID(void); +extern uint32_t __get_MIMPID(void); +extern uint32_t __get_MHARTID(void); +extern uint32_t __get_SP(void); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/Debug/debug.c b/Debug/debug.c new file mode 100644 index 0000000..e0eb24d --- /dev/null +++ b/Debug/debug.c @@ -0,0 +1,253 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : debug.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for UART +* Printf , Delay functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "debug.h" + +static uint8_t p_us = 0; +static uint16_t p_ms = 0; + +#define DEBUG_DATA0_ADDRESS ((volatile uint32_t*)0xE0000380) +#define DEBUG_DATA1_ADDRESS ((volatile uint32_t*)0xE0000384) + +/********************************************************************* + * @fn Delay_Init + * + * @brief Initializes Delay Funcation. + * + * @return none + */ +void Delay_Init(void) +{ + p_us = SystemCoreClock / 8000000; + p_ms = (uint16_t)p_us * 1000; +} + +/********************************************************************* + * @fn Delay_Us + * + * @brief Microsecond Delay Time. + * + * @param n - Microsecond number. + * + * @return None + */ +void Delay_Us(uint32_t n) +{ + uint32_t i; + + SysTick->SR &= ~(1 << 0); + i = (uint32_t)n * p_us; + + SysTick->CMP = i; + SysTick->CTLR |= (1 << 4); + SysTick->CTLR |= (1 << 5) | (1 << 0); + + while((SysTick->SR & (1 << 0)) != (1 << 0)) + ; + SysTick->CTLR &= ~(1 << 0); +} + +/********************************************************************* + * @fn Delay_Ms + * + * @brief Millisecond Delay Time. + * + * @param n - Millisecond number. + * + * @return None + */ +void Delay_Ms(uint32_t n) +{ + uint32_t i; + + SysTick->SR &= ~(1 << 0); + i = (uint32_t)n * p_ms; + + SysTick->CMP = i; + SysTick->CTLR |= (1 << 4); + SysTick->CTLR |= (1 << 5) | (1 << 0); + + while((SysTick->SR & (1 << 0)) != (1 << 0)) + ; + SysTick->CTLR &= ~(1 << 0); +} + +/********************************************************************* + * @fn USART_Printf_Init + * + * @brief Initializes the USARTx peripheral. + * + * @param baudrate - USART communication baud rate. + * + * @return None + */ +void USART_Printf_Init(uint32_t baudrate) +{ + GPIO_InitTypeDef GPIO_InitStructure; + USART_InitTypeDef USART_InitStructure; + +#if(DEBUG == DEBUG_UART1) + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + +#elif(DEBUG == DEBUG_UART2) + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + +#elif(DEBUG == DEBUG_UART3) + RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOB, &GPIO_InitStructure); + +#endif + + USART_InitStructure.USART_BaudRate = baudrate; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Tx; + +#if(DEBUG == DEBUG_UART1) + USART_Init(USART1, &USART_InitStructure); + USART_Cmd(USART1, ENABLE); + +#elif(DEBUG == DEBUG_UART2) + USART_Init(USART2, &USART_InitStructure); + USART_Cmd(USART2, ENABLE); + +#elif(DEBUG == DEBUG_UART3) + USART_Init(USART3, &USART_InitStructure); + USART_Cmd(USART3, ENABLE); + +#endif +} + +/********************************************************************* + * @fn SDI_Printf_Enable + * + * @brief Initializes the SDI printf Function. + * + * @param None + * + * @return None + */ +void SDI_Printf_Enable(void) +{ + *(DEBUG_DATA0_ADDRESS) = 0; + Delay_Init(); + Delay_Ms(1); +} + +/********************************************************************* + * @fn _write + * + * @brief Support Printf Function + * + * @param *buf - UART send Data. + * size - Data length + * + * @return size: Data length + */ +__attribute__((used)) int _write(int fd, char *buf, int size) +{ + int i = 0; + +#if (SDI_PRINT == SDI_PR_OPEN) + int writeSize = size; + + do + { + + /** + * data0 data1 8 bytes + * data0 The lowest byte storage length, the maximum is 7 + * + */ + + while( (*(DEBUG_DATA0_ADDRESS) != 0u)) + { + + } + + if(writeSize>7) + { + *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24); + *(DEBUG_DATA0_ADDRESS) = (7u) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24); + + i += 7; + writeSize -= 7; + } + else + { + *(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24); + *(DEBUG_DATA0_ADDRESS) = (writeSize) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24); + + writeSize = 0; + } + + } while (writeSize); + + +#else + for(i = 0; i < size; i++) + { +#if(DEBUG == DEBUG_UART1) + while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET); + USART_SendData(USART1, *buf++); +#elif(DEBUG == DEBUG_UART2) + while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET); + USART_SendData(USART2, *buf++); +#elif(DEBUG == DEBUG_UART3) + while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET); + USART_SendData(USART3, *buf++); +#endif + } +#endif + return size; +} + +/********************************************************************* + * @fn _sbrk + * + * @brief Change the spatial position of data segment. + * + * @return size: Data length + */ +__attribute__((used)) void *_sbrk(ptrdiff_t incr) +{ + extern char _end[]; + extern char _heap_end[]; + static char *curbrk = _end; + + if ((curbrk + incr < _end) || (curbrk + incr > _heap_end)) + return NULL - 1; + + curbrk += incr; + return curbrk - incr; +} + + + diff --git a/Debug/debug.h b/Debug/debug.h new file mode 100644 index 0000000..03dd5bd --- /dev/null +++ b/Debug/debug.h @@ -0,0 +1,55 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : debug.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for UART +* Printf , Delay functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __DEBUG_H +#define __DEBUG_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "stdio.h" +#include "ch32v30x.h" + +/* UART Printf Definition */ +#define DEBUG_UART1 1 +#define DEBUG_UART2 2 +#define DEBUG_UART3 3 + +/* DEBUG UATR Definition */ +#ifndef DEBUG +#define DEBUG DEBUG_UART1 +#endif + +/* SDI Printf Definition */ +#define SDI_PR_CLOSE 0 +#define SDI_PR_OPEN 1 + +#ifndef SDI_PRINT +#define SDI_PRINT SDI_PR_CLOSE +#endif + + +void Delay_Init(void); +void Delay_Us (uint32_t n); +void Delay_Ms (uint32_t n); +void USART_Printf_Init(uint32_t baudrate); +void SDI_Printf_Enable(void); + +#ifdef __cplusplus +} +#endif + +#endif + + + diff --git a/Ld/Link.ld b/Ld/Link.ld new file mode 100644 index 0000000..c02eb65 --- /dev/null +++ b/Ld/Link.ld @@ -0,0 +1 @@ +ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V30x_D8C - CH32V305RB-CH32V305FB CH32V30x_D8 - CH32V303CB-CH32V303RB */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 128K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K */ /* CH32V30x_D8C - CH32V307VC-CH32V307WC-CH32V307RC-CH32V305CC CH32V30x_D8 - CH32V303VC-CH32V303RC FLASH + RAM supports the following configuration For specific choices, please refer :CH32FV2x_V3xRM.PDF\Table 32-3 FLASH-192K + RAM-128K FLASH-224K + RAM-96K FLASH-256K + RAM-64K FLASH-288K + RAM-32K FLASH-128K + RAM-192K */ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 288K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } \ No newline at end of file diff --git a/Peripheral/inc/ch32v30x.h b/Peripheral/inc/ch32v30x.h new file mode 100644 index 0000000..765a018 --- /dev/null +++ b/Peripheral/inc/ch32v30x.h @@ -0,0 +1,6637 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x.h +* Author : WCH +* Version : V1.0.1 +* Date : 2025/04/09 +* Description : CH32V30x Device Peripheral Access Layer Header File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_H +#define __CH32V30x_H + +#ifdef __cplusplus + extern "C" { +#endif + +#if !defined(CH32V30x_D8) && !defined(CH32V30x_D8C) +//#define CH32V30x_D8 /* CH32V303x */ +#define CH32V30x_D8C /* CH32V307x-CH32V305x-CH32V317x */ + +#endif + +#define __MPU_PRESENT 0 /* Other CH32 devices does not provide an MPU */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + +#ifndef HSE_VALUE +#define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */ +#endif + +/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x1000) /* Time out for HSE start up */ + +#define HSI_VALUE ((uint32_t)8000000) /* Value of the Internal oscillator in Hz */ + +/* CH32V30x Standard Peripheral Library version number */ +#define __CH32V30x_STDPERIPH_VERSION_MAIN (0x02) /* [15:8] main version */ +#define __CH32V30x_STDPERIPH_VERSION_SUB (0x09) /* [7:0] sub version */ +#define __CH32V30x_STDPERIPH_VERSION ( (__CH32V30x_STDPERIPH_VERSION_MAIN << 8)\ + |(__CH32V30x_STDPERIPH_VERSION_SUB << 0)) + + +/* Interrupt Number Definition, according to the selected device */ +typedef enum IRQn +{ + /****** RISC-V Processor Exceptions Numbers *******************************************************/ + NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ + EXC_IRQn = 3, /* 3 Exception Interrupt */ + Ecall_M_Mode_IRQn = 5, /* 5 Ecall M Mode Interrupt */ + Ecall_U_Mode_IRQn = 8, /* 8 Ecall U Mode Interrupt */ + Break_Point_IRQn = 9, /* 9 Break Point Interrupt */ + SysTick_IRQn = 12, /* 12 System timer Interrupt */ + Software_IRQn = 14, /* 14 software Interrupt */ + + /****** RISC-V specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 16, /* Window WatchDog Interrupt */ + PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 18, /* Tamper Interrupt */ + RTC_IRQn = 19, /* RTC global Interrupt */ + FLASH_IRQn = 20, /* FLASH global Interrupt */ + RCC_IRQn = 21, /* RCC global Interrupt */ + EXTI0_IRQn = 22, /* EXTI Line0 Interrupt */ + EXTI1_IRQn = 23, /* EXTI Line1 Interrupt */ + EXTI2_IRQn = 24, /* EXTI Line2 Interrupt */ + EXTI3_IRQn = 25, /* EXTI Line3 Interrupt */ + EXTI4_IRQn = 26, /* EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 27, /* DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 28, /* DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 29, /* DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 30, /* DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 31, /* DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 32, /* DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 33, /* DMA1 Channel 7 global Interrupt */ + ADC_IRQn = 34, /* ADC1 and ADC2 global Interrupt */ + USB_HP_CAN1_TX_IRQn = 35, /* USB Device High Priority or CAN1 TX Interrupts */ + USB_LP_CAN1_RX0_IRQn = 36, /* USB Device Low Priority or CAN1 RX0 Interrupts */ + CAN1_RX1_IRQn = 37, /* CAN1 RX1 Interrupt */ + CAN1_SCE_IRQn = 38, /* CAN1 SCE Interrupt */ + EXTI9_5_IRQn = 39, /* External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 40, /* TIM1 Break Interrupt */ + TIM1_UP_IRQn = 41, /* TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 42, /* TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 43, /* TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 44, /* TIM2 global Interrupt */ + TIM3_IRQn = 45, /* TIM3 global Interrupt */ + TIM4_IRQn = 46, /* TIM4 global Interrupt */ + I2C1_EV_IRQn = 47, /* I2C1 Event Interrupt */ + I2C1_ER_IRQn = 48, /* I2C1 Error Interrupt */ + I2C2_EV_IRQn = 49, /* I2C2 Event Interrupt */ + I2C2_ER_IRQn = 50, /* I2C2 Error Interrupt */ + SPI1_IRQn = 51, /* SPI1 global Interrupt */ + SPI2_IRQn = 52, /* SPI2 global Interrupt */ + USART1_IRQn = 53, /* USART1 global Interrupt */ + USART2_IRQn = 54, /* USART2 global Interrupt */ + USART3_IRQn = 55, /* USART3 global Interrupt */ + EXTI15_10_IRQn = 56, /* External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 57, /* RTC Alarm through EXTI Line Interrupt */ + +#ifdef CH32V30x_D8 + TIM8_BRK_IRQn = 59, /* TIM8 Break Interrupt */ + TIM8_UP_IRQn = 60, /* TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 61, /* TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 62, /* TIM8 Capture Compare Interrupt */ + RNG_IRQn = 63, /* RNG global Interrupt */ + SDIO_IRQn = 65, /* SDIO global Interrupt */ + TIM5_IRQn = 66, /* TIM5 global Interrupt */ + SPI3_IRQn = 67, /* SPI3 global Interrupt */ + UART4_IRQn = 68, /* UART4 global Interrupt */ + UART5_IRQn = 69, /* UART5 global Interrupt */ + TIM6_IRQn = 70, /* TIM6 global Interrupt */ + TIM7_IRQn = 71, /* TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 72, /* DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 73, /* DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 74, /* DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 75, /* DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 76, /* DMA2 Channel 5 global Interrupt */ + USBFS_IRQn = 83, /* USBFS global Interrupt */ + UART6_IRQn = 87, /* UART6 global Interrupt */ + UART7_IRQn = 88, /* UART7 global Interrupt */ + UART8_IRQn = 89, /* UART8 global Interrupt */ + TIM9_BRK_IRQn = 90, /* TIM9 Break Interrupt */ + TIM9_UP_IRQn = 91, /* TIM9 Update Interrupt */ + TIM9_TRG_COM_IRQn = 92, /* TIM9 Trigger and Commutation Interrupt */ + TIM9_CC_IRQn = 93, /* TIM9 Capture Compare Interrupt */ + TIM10_BRK_IRQn = 94, /* TIM10 Break Interrupt */ + TIM10_UP_IRQn = 95, /* TIM10 Update Interrupt */ + TIM10_TRG_COM_IRQn = 96, /* TIM10 Trigger and Commutation Interrupt */ + TIM10_CC_IRQn = 97, /* TIM10 Capture Compare Interrupt */ + DMA2_Channel6_IRQn = 98, /* DMA2 Channel 6 global Interrupt */ + DMA2_Channel7_IRQn = 99, /* DMA2 Channel 7 global Interrupt */ + DMA2_Channel8_IRQn = 100, /* DMA2 Channel 8 global Interrupt */ + DMA2_Channel9_IRQn = 101, /* DMA2 Channel 9 global Interrupt */ + DMA2_Channel10_IRQn = 102, /* DMA2 Channel 10 global Interrupt */ + DMA2_Channel11_IRQn = 103, /* DMA2 Channel 11 global Interrupt */ + +#elif defined (CH32V30x_D8C) + USBWakeUp_IRQn = 58, /* USB Device WakeUp from suspend through EXTI Line Interrupt */ + TIM8_BRK_IRQn = 59, /* TIM8 Break Interrupt */ + TIM8_UP_IRQn = 60, /* TIM8 Update Interrupt */ + TIM8_TRG_COM_IRQn = 61, /* TIM8 Trigger and Commutation Interrupt */ + TIM8_CC_IRQn = 62, /* TIM8 Capture Compare Interrupt */ + RNG_IRQn = 63, /* RNG global Interrupt */ + SDIO_IRQn = 65, /* SDIO global Interrupt */ + TIM5_IRQn = 66, /* TIM5 global Interrupt */ + SPI3_IRQn = 67, /* SPI3 global Interrupt */ + UART4_IRQn = 68, /* UART4 global Interrupt */ + UART5_IRQn = 69, /* UART5 global Interrupt */ + TIM6_IRQn = 70, /* TIM6 global Interrupt */ + TIM7_IRQn = 71, /* TIM7 global Interrupt */ + DMA2_Channel1_IRQn = 72, /* DMA2 Channel 1 global Interrupt */ + DMA2_Channel2_IRQn = 73, /* DMA2 Channel 2 global Interrupt */ + DMA2_Channel3_IRQn = 74, /* DMA2 Channel 3 global Interrupt */ + DMA2_Channel4_IRQn = 75, /* DMA2 Channel 4 global Interrupt */ + DMA2_Channel5_IRQn = 76, /* DMA2 Channel 5 global Interrupt */ + ETH_IRQn = 77, /* ETH global Interrupt */ + ETH_WKUP_IRQn = 78, /* ETH WakeUp Interrupt */ + CAN2_TX_IRQn = 79, /* CAN2 TX Interrupts */ + CAN2_RX0_IRQn = 80, /* CAN2 RX0 Interrupts */ + CAN2_RX1_IRQn = 81, /* CAN2 RX1 Interrupt */ + CAN2_SCE_IRQn = 82, /* CAN2 SCE Interrupt */ + USBFS_IRQn = 83, /* USBFS global Interrupt */ + USBHSWakeup_IRQn = 84, /* USBHS WakeUp Interrupt */ + USBHS_IRQn = 85, /* USBHS global Interrupt */ + DVP_IRQn = 86, /* DVP global Interrupt */ + UART6_IRQn = 87, /* UART6 global Interrupt */ + UART7_IRQn = 88, /* UART7 global Interrupt */ + UART8_IRQn = 89, /* UART8 global Interrupt */ + TIM9_BRK_IRQn = 90, /* TIM9 Break Interrupt */ + TIM9_UP_IRQn = 91, /* TIM9 Update Interrupt */ + TIM9_TRG_COM_IRQn = 92, /* TIM9 Trigger and Commutation Interrupt */ + TIM9_CC_IRQn = 93, /* TIM9 Capture Compare Interrupt */ + TIM10_BRK_IRQn = 94, /* TIM10 Break Interrupt */ + TIM10_UP_IRQn = 95, /* TIM10 Update Interrupt */ + TIM10_TRG_COM_IRQn = 96, /* TIM10 Trigger and Commutation Interrupt */ + TIM10_CC_IRQn = 97, /* TIM10 Capture Compare Interrupt */ + DMA2_Channel6_IRQn = 98, /* DMA2 Channel 6 global Interrupt */ + DMA2_Channel7_IRQn = 99, /* DMA2 Channel 7 global Interrupt */ + DMA2_Channel8_IRQn = 100, /* DMA2 Channel 8 global Interrupt */ + DMA2_Channel9_IRQn = 101, /* DMA2 Channel 9 global Interrupt */ + DMA2_Channel10_IRQn = 102, /* DMA2 Channel 10 global Interrupt */ + DMA2_Channel11_IRQn = 103, /* DMA2 Channel 11 global Interrupt */ + +#endif +} IRQn_Type; + +#define HardFault_IRQn EXC_IRQn +#define ADC1_2_IRQn ADC_IRQn + +#define SysTicK_IRQn SysTick_IRQn +#define OTG_FS_IRQn USBFS_IRQn +#define OTG_FS_IRQHandler USBFS_IRQHandler + +#define USBHD_IRQHandler USBFS_IRQHandler + +#define USBOTG_FS USBFSD +#define USBOTG_H_FS USBFSH + +#include +#include "core_riscv.h" +#include "system_ch32v30x.h" + + +/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSI_Value HSI_VALUE +#define HSE_Value HSE_VALUE +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT + +/* Analog to Digital Converter */ +typedef struct +{ + __IO uint32_t STATR; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t SAMPTR1; + __IO uint32_t SAMPTR2; + __IO uint32_t IOFR1; + __IO uint32_t IOFR2; + __IO uint32_t IOFR3; + __IO uint32_t IOFR4; + __IO uint32_t WDHTR; + __IO uint32_t WDLTR; + __IO uint32_t RSQR1; + __IO uint32_t RSQR2; + __IO uint32_t RSQR3; + __IO uint32_t ISQR; + __IO uint32_t IDATAR1; + __IO uint32_t IDATAR2; + __IO uint32_t IDATAR3; + __IO uint32_t IDATAR4; + __IO uint32_t RDATAR; + uint32_t RESERVED0; + __IO uint32_t AUX; +} ADC_TypeDef; + +/* Backup Registers */ +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DATAR1; + uint16_t RESERVED1; + __IO uint16_t DATAR2; + uint16_t RESERVED2; + __IO uint16_t DATAR3; + uint16_t RESERVED3; + __IO uint16_t DATAR4; + uint16_t RESERVED4; + __IO uint16_t DATAR5; + uint16_t RESERVED5; + __IO uint16_t DATAR6; + uint16_t RESERVED6; + __IO uint16_t DATAR7; + uint16_t RESERVED7; + __IO uint16_t DATAR8; + uint16_t RESERVED8; + __IO uint16_t DATAR9; + uint16_t RESERVED9; + __IO uint16_t DATAR10; + uint16_t RESERVED10; + __IO uint16_t OCTLR; + uint16_t RESERVED11; + __IO uint16_t TPCTLR; + uint16_t RESERVED12; + __IO uint16_t TPCSR; + uint16_t RESERVED13[5]; + __IO uint16_t DATAR11; + uint16_t RESERVED14; + __IO uint16_t DATAR12; + uint16_t RESERVED15; + __IO uint16_t DATAR13; + uint16_t RESERVED16; + __IO uint16_t DATAR14; + uint16_t RESERVED17; + __IO uint16_t DATAR15; + uint16_t RESERVED18; + __IO uint16_t DATAR16; + uint16_t RESERVED19; + __IO uint16_t DATAR17; + uint16_t RESERVED20; + __IO uint16_t DATAR18; + uint16_t RESERVED21; + __IO uint16_t DATAR19; + uint16_t RESERVED22; + __IO uint16_t DATAR20; + uint16_t RESERVED23; + __IO uint16_t DATAR21; + uint16_t RESERVED24; + __IO uint16_t DATAR22; + uint16_t RESERVED25; + __IO uint16_t DATAR23; + uint16_t RESERVED26; + __IO uint16_t DATAR24; + uint16_t RESERVED27; + __IO uint16_t DATAR25; + uint16_t RESERVED28; + __IO uint16_t DATAR26; + uint16_t RESERVED29; + __IO uint16_t DATAR27; + uint16_t RESERVED30; + __IO uint16_t DATAR28; + uint16_t RESERVED31; + __IO uint16_t DATAR29; + uint16_t RESERVED32; + __IO uint16_t DATAR30; + uint16_t RESERVED33; + __IO uint16_t DATAR31; + uint16_t RESERVED34; + __IO uint16_t DATAR32; + uint16_t RESERVED35; + __IO uint16_t DATAR33; + uint16_t RESERVED36; + __IO uint16_t DATAR34; + uint16_t RESERVED37; + __IO uint16_t DATAR35; + uint16_t RESERVED38; + __IO uint16_t DATAR36; + uint16_t RESERVED39; + __IO uint16_t DATAR37; + uint16_t RESERVED40; + __IO uint16_t DATAR38; + uint16_t RESERVED41; + __IO uint16_t DATAR39; + uint16_t RESERVED42; + __IO uint16_t DATAR40; + uint16_t RESERVED43; + __IO uint16_t DATAR41; + uint16_t RESERVED44; + __IO uint16_t DATAR42; + uint16_t RESERVED45; +} BKP_TypeDef; + +/* Controller Area Network TxMailBox */ +typedef struct +{ + __IO uint32_t TXMIR; + __IO uint32_t TXMDTR; + __IO uint32_t TXMDLR; + __IO uint32_t TXMDHR; +} CAN_TxMailBox_TypeDef; + +/* Controller Area Network FIFOMailBox */ +typedef struct +{ + __IO uint32_t RXMIR; + __IO uint32_t RXMDTR; + __IO uint32_t RXMDLR; + __IO uint32_t RXMDHR; +} CAN_FIFOMailBox_TypeDef; + +/* Controller Area Network FilterRegister */ +typedef struct +{ + __IO uint32_t FR1; + __IO uint32_t FR2; +} CAN_FilterRegister_TypeDef; + +/* Controller Area Network */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t STATR; + __IO uint32_t TSTATR; + __IO uint32_t RFIFO0; + __IO uint32_t RFIFO1; + __IO uint32_t INTENR; + __IO uint32_t ERRSR; + __IO uint32_t BTIMR; + uint32_t RESERVED0[88]; + CAN_TxMailBox_TypeDef sTxMailBox[3]; + CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; + uint32_t RESERVED1[12]; + __IO uint32_t FCTLR; + __IO uint32_t FMCFGR; + uint32_t RESERVED2; + __IO uint32_t FSCFGR; + uint32_t RESERVED3; + __IO uint32_t FAFIFOR; + uint32_t RESERVED4; + __IO uint32_t FWR; + uint32_t RESERVED5[8]; + CAN_FilterRegister_TypeDef sFilterRegister[28]; +} CAN_TypeDef; + +/* CRC Calculation Unit */ +typedef struct +{ + __IO uint32_t DATAR; + __IO uint8_t IDATAR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CTLR; +} CRC_TypeDef; + +/* Digital to Analog Converter */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SWTR; + __IO uint32_t R12BDHR1; + __IO uint32_t L12BDHR1; + __IO uint32_t R8BDHR1; + __IO uint32_t R12BDHR2; + __IO uint32_t L12BDHR2; + __IO uint32_t R8BDHR2; + __IO uint32_t RD12BDHR; + __IO uint32_t LD12BDHR; + __IO uint32_t RD8BDHR; + __IO uint32_t DOR1; + __IO uint32_t DOR2; +} DAC_TypeDef; + +/* DMA Channel Controller */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t CNTR; + __IO uint32_t PADDR; + __IO uint32_t MADDR; +} DMA_Channel_TypeDef; + +/* DMA Controller */ +typedef struct +{ + __IO uint32_t INTFR; + __IO uint32_t INTFCR; +} DMA_TypeDef; + +/* External Interrupt/Event Controller */ +typedef struct +{ + __IO uint32_t INTENR; + __IO uint32_t EVENR; + __IO uint32_t RTENR; + __IO uint32_t FTENR; + __IO uint32_t SWIEVR; + __IO uint32_t INTFR; +} EXTI_TypeDef; + +/* FLASH Registers */ +typedef struct +{ + __IO uint32_t ACTLR; + __IO uint32_t KEYR; + __IO uint32_t OBKEYR; + __IO uint32_t STATR; + __IO uint32_t CTLR; + __IO uint32_t ADDR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WPR; + __IO uint32_t MODEKEYR; +} FLASH_TypeDef; + +/* Option Bytes Registers */ +typedef struct +{ + __IO uint16_t RDPR; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRPR0; + __IO uint16_t WRPR1; + __IO uint16_t WRPR2; + __IO uint16_t WRPR3; +} OB_TypeDef; + +/* FSMC Bank1 Registers */ +typedef struct +{ + __IO uint32_t BTCR[8]; +} FSMC_Bank1_TypeDef; + +/* FSMC Bank1E Registers */ +typedef struct +{ + __IO uint32_t BWTR[7]; +} FSMC_Bank1E_TypeDef; + +/* FSMC Bank2 Registers */ +typedef struct +{ + __IO uint32_t PCR2; + __IO uint32_t SR2; + __IO uint32_t PMEM2; + __IO uint32_t PATT2; + uint32_t RESERVED0; + __IO uint32_t ECCR2; +} FSMC_Bank2_TypeDef; + +/* General Purpose I/O */ +typedef struct +{ + __IO uint32_t CFGLR; + __IO uint32_t CFGHR; + __IO uint32_t INDR; + __IO uint32_t OUTDR; + __IO uint32_t BSHR; + __IO uint32_t BCR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/* Alternate Function I/O */ +typedef struct +{ + __IO uint32_t ECR; + __IO uint32_t PCFR1; + __IO uint32_t EXTICR[4]; + uint32_t RESERVED0; + __IO uint32_t PCFR2; +} AFIO_TypeDef; + +/* Inter Integrated Circuit Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DATAR; + uint16_t RESERVED4; + __IO uint16_t STAR1; + uint16_t RESERVED5; + __IO uint16_t STAR2; + uint16_t RESERVED6; + __IO uint16_t CKCFGR; + uint16_t RESERVED7; + __IO uint16_t RTR; + uint16_t RESERVED8; +} I2C_TypeDef; + +/* Independent WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t PSCR; + __IO uint32_t RLDR; + __IO uint32_t STATR; +} IWDG_TypeDef; + +/* Power Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/* Reset and Clock Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR0; + __IO uint32_t INTR; + __IO uint32_t APB2PRSTR; + __IO uint32_t APB1PRSTR; + __IO uint32_t AHBPCENR; + __IO uint32_t APB2PCENR; + __IO uint32_t APB1PCENR; + __IO uint32_t BDCTLR; + __IO uint32_t RSTSCKR; + __IO uint32_t AHBRSTR; + __IO uint32_t CFGR2; +} RCC_TypeDef; + +/* Real-Time Clock */ +typedef struct +{ + __IO uint16_t CTLRH; + uint16_t RESERVED0; + __IO uint16_t CTLRL; + uint16_t RESERVED1; + __IO uint16_t PSCRH; + uint16_t RESERVED2; + __IO uint16_t PSCRL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRMH; + uint16_t RESERVED8; + __IO uint16_t ALRML; + uint16_t RESERVED9; +} RTC_TypeDef; + +/* SDIO Registers */ +typedef struct +{ + __IO uint32_t POWER; + __IO uint32_t CLKCR; + __IO uint32_t ARG; + __IO uint32_t CMD; + __I uint32_t RESPCMD; + __I uint32_t RESP1; + __I uint32_t RESP2; + __I uint32_t RESP3; + __I uint32_t RESP4; + __IO uint32_t DTIMER; + __IO uint32_t DLEN; + __IO uint32_t DCTRL; + __I uint32_t DCOUNT; + __I uint32_t STA; + __IO uint32_t ICR; + __IO uint32_t MASK; + uint32_t RESERVED0[2]; + __I uint32_t FIFOCNT; + uint32_t RESERVED1[5]; + __IO uint32_t DCTRL2; + uint32_t RESERVED2[7]; + __IO uint32_t FIFO; +} SDIO_TypeDef; + +/* Serial Peripheral Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t STATR; + uint16_t RESERVED2; + __IO uint16_t DATAR; + uint16_t RESERVED3; + __IO uint16_t CRCR; + uint16_t RESERVED4; + __IO uint16_t RCRCR; + uint16_t RESERVED5; + __IO uint16_t TCRCR; + uint16_t RESERVED6; + __IO uint16_t I2SCFGR; + uint16_t RESERVED7; + __IO uint16_t I2SPR; + uint16_t RESERVED8; + __IO uint16_t HSCR; + uint16_t RESERVED9; +} SPI_TypeDef; + +/* TIM */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t SMCFGR; + uint16_t RESERVED2; + __IO uint16_t DMAINTENR; + uint16_t RESERVED3; + __IO uint16_t INTFR; + uint16_t RESERVED4; + __IO uint16_t SWEVGR; + uint16_t RESERVED5; + __IO uint16_t CHCTLR1; + uint16_t RESERVED6; + __IO uint16_t CHCTLR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ATRLR; + uint16_t RESERVED11; + __IO uint16_t RPTCR; + uint16_t RESERVED12; + __IO uint16_t CH1CVR; + uint16_t RESERVED13; + __IO uint16_t CH2CVR; + uint16_t RESERVED14; + __IO uint16_t CH3CVR; + uint16_t RESERVED15; + __IO uint16_t CH4CVR; + uint16_t RESERVED16; + __IO uint16_t BDTR; + uint16_t RESERVED17; + __IO uint16_t DMACFGR; + uint16_t RESERVED18; + __IO uint16_t DMAADR; + uint16_t RESERVED19; + __IO uint16_t AUX; + uint16_t RESERVED20; +} TIM_TypeDef; + +/* Universal Synchronous Asynchronous Receiver Transmitter */ +typedef struct +{ + __IO uint16_t STATR; + uint16_t RESERVED0; + __IO uint16_t DATAR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CTLR1; + uint16_t RESERVED3; + __IO uint16_t CTLR2; + uint16_t RESERVED4; + __IO uint16_t CTLR3; + uint16_t RESERVED5; + __IO uint16_t GPR; + uint16_t RESERVED6; + __IO uint16_t CTLR4; + uint16_t RESERVED7; +} USART_TypeDef; + +/* Window WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR; + __IO uint32_t STATR; +} WWDG_TypeDef; + +/* Enhanced Registers */ +typedef struct +{ + __IO uint32_t EXTEN_CTR; + uint32_t RESERVED0; + __IO uint32_t EXTEN_CTR2; +} EXTEN_TypeDef; + +/* OPA Registers */ +typedef struct +{ + __IO uint32_t CR; +} OPA_TypeDef; + +/* RNG Registers */ +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SR; + __IO uint32_t DR; +} RNG_TypeDef; + +/* DVP Registers */ +typedef struct +{ + __IO uint8_t CR0; + __IO uint8_t CR1; + __IO uint8_t IER; + __IO uint8_t Reserved0; + __IO uint16_t ROW_NUM; + __IO uint16_t COL_NUM; + __IO uint32_t DMA_BUF0; + __IO uint32_t DMA_BUF1; + __IO uint8_t IFR; + __IO uint8_t STATUS; + __IO uint16_t Reserved1; + __IO uint16_t ROW_CNT; + __IO uint16_t Reserved2; + __IO uint16_t HOFFCNT; + __IO uint16_t VST; + __IO uint16_t CAPCNT; + __IO uint16_t VLINE; + __IO uint32_t DR; +} DVP_TypeDef; + +/* USBHS Registers */ +typedef struct +{ + __IO uint8_t CONTROL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_AD; + __IO uint16_t FRAME_NO; + __IO uint8_t SUSPEND; + __IO uint8_t RESERVED0; + __IO uint8_t SPEED_TYPE; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t RESERVED1; + __IO uint32_t ENDP_CONFIG; + __IO uint32_t ENDP_TYPE; + __IO uint32_t BUF_MODE; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_RX_DMA; + __IO uint32_t UEP2_RX_DMA; + __IO uint32_t UEP3_RX_DMA; + __IO uint32_t UEP4_RX_DMA; + __IO uint32_t UEP5_RX_DMA; + __IO uint32_t UEP6_RX_DMA; + __IO uint32_t UEP7_RX_DMA; + __IO uint32_t UEP8_RX_DMA; + __IO uint32_t UEP9_RX_DMA; + __IO uint32_t UEP10_RX_DMA; + __IO uint32_t UEP11_RX_DMA; + __IO uint32_t UEP12_RX_DMA; + __IO uint32_t UEP13_RX_DMA; + __IO uint32_t UEP14_RX_DMA; + __IO uint32_t UEP15_RX_DMA; + __IO uint32_t UEP1_TX_DMA; + __IO uint32_t UEP2_TX_DMA; + __IO uint32_t UEP3_TX_DMA; + __IO uint32_t UEP4_TX_DMA; + __IO uint32_t UEP5_TX_DMA; + __IO uint32_t UEP6_TX_DMA; + __IO uint32_t UEP7_TX_DMA; + __IO uint32_t UEP8_TX_DMA; + __IO uint32_t UEP9_TX_DMA; + __IO uint32_t UEP10_TX_DMA; + __IO uint32_t UEP11_TX_DMA; + __IO uint32_t UEP12_TX_DMA; + __IO uint32_t UEP13_TX_DMA; + __IO uint32_t UEP14_TX_DMA; + __IO uint32_t UEP15_TX_DMA; + __IO uint16_t UEP0_MAX_LEN; + __IO uint16_t RESERVED2; + __IO uint16_t UEP1_MAX_LEN; + __IO uint16_t RESERVED3; + __IO uint16_t UEP2_MAX_LEN; + __IO uint16_t RESERVED4; + __IO uint16_t UEP3_MAX_LEN; + __IO uint16_t RESERVED5; + __IO uint16_t UEP4_MAX_LEN; + __IO uint16_t RESERVED6; + __IO uint16_t UEP5_MAX_LEN; + __IO uint16_t RESERVED7; + __IO uint16_t UEP6_MAX_LEN; + __IO uint16_t RESERVED8; + __IO uint16_t UEP7_MAX_LEN; + __IO uint16_t RESERVED9; + __IO uint16_t UEP8_MAX_LEN; + __IO uint16_t RESERVED10; + __IO uint16_t UEP9_MAX_LEN; + __IO uint16_t RESERVED11; + __IO uint16_t UEP10_MAX_LEN; + __IO uint16_t RESERVED12; + __IO uint16_t UEP11_MAX_LEN; + __IO uint16_t RESERVED13; + __IO uint16_t UEP12_MAX_LEN; + __IO uint16_t RESERVED14; + __IO uint16_t UEP13_MAX_LEN; + __IO uint16_t RESERVED15; + __IO uint16_t UEP14_MAX_LEN; + __IO uint16_t RESERVED16; + __IO uint16_t UEP15_MAX_LEN; + __IO uint16_t RESERVED17; + __IO uint16_t UEP0_TX_LEN; + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t UEP0_RX_CTRL; + __IO uint16_t UEP1_TX_LEN; + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t UEP1_RX_CTRL; + __IO uint16_t UEP2_TX_LEN; + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t UEP2_RX_CTRL; + __IO uint16_t UEP3_TX_LEN; + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t UEP3_RX_CTRL; + __IO uint16_t UEP4_TX_LEN; + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t UEP4_RX_CTRL; + __IO uint16_t UEP5_TX_LEN; + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t UEP5_RX_CTRL; + __IO uint16_t UEP6_TX_LEN; + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t UEP6_RX_CTRL; + __IO uint16_t UEP7_TX_LEN; + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t UEP7_RX_CTRL; + __IO uint16_t UEP8_TX_LEN; + __IO uint8_t UEP8_TX_CTRL; + __IO uint8_t UEP8_RX_CTRL; + __IO uint16_t UEP9_TX_LEN; + __IO uint8_t UEP9_TX_CTRL; + __IO uint8_t UEP9_RX_CTRL; + __IO uint16_t UEP10_TX_LEN; + __IO uint8_t UEP10_TX_CTRL; + __IO uint8_t UEP10_RX_CTRL; + __IO uint16_t UEP11_TX_LEN; + __IO uint8_t UEP11_TX_CTRL; + __IO uint8_t UEP11_RX_CTRL; + __IO uint16_t UEP12_TX_LEN; + __IO uint8_t UEP12_TX_CTRL; + __IO uint8_t UEP12_RX_CTRL; + __IO uint16_t UEP13_TX_LEN; + __IO uint8_t UEP13_TX_CTRL; + __IO uint8_t UEP13_RX_CTRL; + __IO uint16_t UEP14_TX_LEN; + __IO uint8_t UEP14_TX_CTRL; + __IO uint8_t UEP14_RX_CTRL; + __IO uint16_t UEP15_TX_LEN; + __IO uint8_t UEP15_TX_CTRL; + __IO uint8_t UEP15_RX_CTRL; +} USBHSD_TypeDef; + +typedef struct __attribute__((packed)) +{ + __IO uint8_t CONTROL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_AD; + __IO uint16_t FRAME_NO; + __IO uint8_t SUSPEND; + __IO uint8_t RESERVED0; + __IO uint8_t SPEED_TYPE; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t RESERVED1; + __IO uint32_t HOST_EP_CONFIG; + __IO uint32_t HOST_EP_TYPE; + __IO uint32_t RESERVED2; + __IO uint32_t RESERVED3; + __IO uint32_t RESERVED4; + __IO uint32_t HOST_RX_DMA; + __IO uint32_t RESERVED5; + __IO uint32_t RESERVED6; + __IO uint32_t RESERVED7; + __IO uint32_t RESERVED8; + __IO uint32_t RESERVED9; + __IO uint32_t RESERVED10; + __IO uint32_t RESERVED11; + __IO uint32_t RESERVED12; + __IO uint32_t RESERVED13; + __IO uint32_t RESERVED14; + __IO uint32_t RESERVED15; + __IO uint32_t RESERVED16; + __IO uint32_t RESERVED17; + __IO uint32_t RESERVED18; + __IO uint32_t RESERVED19; + __IO uint32_t HOST_TX_DMA; + __IO uint32_t RESERVED20; + __IO uint32_t RESERVED21; + __IO uint32_t RESERVED22; + __IO uint32_t RESERVED23; + __IO uint32_t RESERVED24; + __IO uint32_t RESERVED25; + __IO uint32_t RESERVED26; + __IO uint32_t RESERVED27; + __IO uint32_t RESERVED28; + __IO uint32_t RESERVED29; + __IO uint32_t RESERVED30; + __IO uint32_t RESERVED31; + __IO uint32_t RESERVED32; + __IO uint32_t RESERVED33; + __IO uint16_t HOST_RX_MAX_LEN; + __IO uint16_t RESERVED34; + __IO uint32_t RESERVED35; + __IO uint32_t RESERVED36; + __IO uint32_t RESERVED37; + __IO uint32_t RESERVED38; + __IO uint32_t RESERVED39; + __IO uint32_t RESERVED40; + __IO uint32_t RESERVED41; + __IO uint32_t RESERVED42; + __IO uint32_t RESERVED43; + __IO uint32_t RESERVED44; + __IO uint32_t RESERVED45; + __IO uint32_t RESERVED46; + __IO uint32_t RESERVED47; + __IO uint32_t RESERVED48; + __IO uint32_t RESERVED49; + __IO uint8_t HOST_EP_PID; + __IO uint8_t RESERVED50; + __IO uint8_t RESERVED51; + __IO uint8_t HOST_RX_CTRL; + __IO uint16_t HOST_TX_LEN; + __IO uint8_t HOST_TX_CTRL; + __IO uint8_t RESERVED52; + __IO uint16_t HOST_SPLIT_DATA; +} USBHSH_TypeDef; + + +/* USBOTG_FS Registers */ +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t UDEV_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t Reserve0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t Reserve1; + __IO uint8_t UEP4_1_MOD; + __IO uint8_t UEP2_3_MOD; + __IO uint8_t UEP5_6_MOD; + __IO uint8_t UEP7_MOD; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_DMA; + __IO uint32_t UEP2_DMA; + __IO uint32_t UEP3_DMA; + __IO uint32_t UEP4_DMA; + __IO uint32_t UEP5_DMA; + __IO uint32_t UEP6_DMA; + __IO uint32_t UEP7_DMA; + __IO uint16_t UEP0_TX_LEN; + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t UEP0_RX_CTRL; + __IO uint16_t UEP1_TX_LEN; + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t UEP1_RX_CTRL; + __IO uint16_t UEP2_TX_LEN; + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t UEP2_RX_CTRL; + __IO uint16_t UEP3_TX_LEN; + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t UEP3_RX_CTRL; + __IO uint16_t UEP4_TX_LEN; + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t UEP4_RX_CTRL; + __IO uint16_t UEP5_TX_LEN; + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t UEP5_RX_CTRL; + __IO uint16_t UEP6_TX_LEN; + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t UEP6_RX_CTRL; + __IO uint16_t UEP7_TX_LEN; + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t UEP7_RX_CTRL; + __IO uint32_t Reserve2; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +}USBFSD_TypeDef; + +typedef struct __attribute__((packed)) +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t Reserve0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t Reserve1; + __IO uint8_t Reserve2; + __IO uint8_t HOST_EP_MOD; + __IO uint16_t Reserve3; + __IO uint32_t Reserve4; + __IO uint32_t Reserve5; + __IO uint32_t HOST_RX_DMA; + __IO uint32_t HOST_TX_DMA; + __IO uint32_t Reserve6; + __IO uint32_t Reserve7; + __IO uint32_t Reserve8; + __IO uint32_t Reserve9; + __IO uint32_t Reserve10; + __IO uint16_t Reserve11; + __IO uint16_t HOST_SETUP; + __IO uint8_t HOST_EP_PID; + __IO uint8_t Reserve12; + __IO uint8_t Reserve13; + __IO uint8_t HOST_RX_CTRL; + __IO uint16_t HOST_TX_LEN; + __IO uint8_t HOST_TX_CTRL; + __IO uint8_t Reserve14; + __IO uint32_t Reserve15; + __IO uint32_t Reserve16; + __IO uint32_t Reserve17; + __IO uint32_t Reserve18; + __IO uint32_t Reserve19; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +}USBFSH_TypeDef; + +/* Ethernet MAC */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACFFR; + __IO uint32_t MACHTHR; + __IO uint32_t MACHTLR; + __IO uint32_t MACMIIAR; + __IO uint32_t MACMIIDR; + __IO uint32_t MACFCR; + __IO uint32_t MACVLANTR; + uint32_t RESERVED0[2]; + __IO uint32_t MACRWUFFR; + __IO uint32_t MACPMTCSR; + uint32_t RESERVED1[2]; + __IO uint32_t MACSR; + __IO uint32_t MACIMR; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED2[14]; + __IO uint32_t MACCFG0; + uint32_t RESERVED10[25]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED3[14]; + __IO uint32_t MMCTGFSCCR; + __IO uint32_t MMCTGFMSCCR; + uint32_t RESERVED4[5]; + __IO uint32_t MMCTGFCR; + uint32_t RESERVED5[10]; + __IO uint32_t MMCRFCECR; + __IO uint32_t MMCRFAECR; + uint32_t RESERVED6[10]; + __IO uint32_t MMCRGUFCR; + uint32_t RESERVED7[334]; + __IO uint32_t PTPTSCR; + __IO uint32_t PTPSSIR; + __IO uint32_t PTPTSHR; + __IO uint32_t PTPTSLR; + __IO uint32_t PTPTSHUR; + __IO uint32_t PTPTSLUR; + __IO uint32_t PTPTSAR; + __IO uint32_t PTPTTHR; + __IO uint32_t PTPTTLR; + uint32_t RESERVED8[567]; + __IO uint32_t DMABMR; + __IO uint32_t DMATPDR; + __IO uint32_t DMARPDR; + __IO uint32_t DMARDLAR; + __IO uint32_t DMATDLAR; + __IO uint32_t DMASR; + __IO uint32_t DMAOMR; + __IO uint32_t DMAIER; + __IO uint32_t DMAMFBOCR; + uint32_t RESERVED9[9]; + __IO uint32_t DMACHTDR; + __IO uint32_t DMACHRDR; + __IO uint32_t DMACHTBAR; + __IO uint32_t DMACHRBAR; +} ETH_TypeDef; + + + +/* Peripheral memory map */ +#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ + +#define FSMC_R_BASE ((uint32_t)0xA0000000) /* FSMC registers base address */ + + +#define APB1PERIPH_BASE (PERIPH_BASE) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define UART6_BASE (APB1PERIPH_BASE + 0x1800) +#define UART7_BASE (APB1PERIPH_BASE + 0x1C00) +#define UART8_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define CAN1_BASE (APB1PERIPH_BASE + 0x6400) +#define CAN2_BASE (APB1PERIPH_BASE + 0x6800) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) +#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) +#define SDIO_BASE (APB2PERIPH_BASE + 0x8000) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) +#define DMA2_Channel6_BASE (AHBPERIPH_BASE + 0x046C) +#define DMA2_Channel7_BASE (AHBPERIPH_BASE + 0x0480) +#define DMA2_Channel8_BASE (AHBPERIPH_BASE + 0x0490) +#define DMA2_Channel9_BASE (AHBPERIPH_BASE + 0x04A0) +#define DMA2_Channel10_BASE (AHBPERIPH_BASE + 0x04B0) +#define DMA2_Channel11_BASE (AHBPERIPH_BASE + 0x04C0) +#define DMA2_EXTEN_BASE (AHBPERIPH_BASE + 0x04D0) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) +#define USBHS_BASE (AHBPERIPH_BASE + 0x3400) +#define EXTEN_BASE (AHBPERIPH_BASE + 0x3800) +#define OPA_BASE (AHBPERIPH_BASE + 0x3804) +#define RNG_BASE (AHBPERIPH_BASE + 0x3C00) + +#define ETH_BASE (AHBPERIPH_BASE + 0x8000) +#define ETH_MAC_BASE (ETH_BASE) +#define ETH_MMC_BASE (ETH_BASE + 0x0100) +#define ETH_PTP_BASE (ETH_BASE + 0x0700) +#define ETH_DMA_BASE (ETH_BASE + 0x1000) + +#define USBFS_BASE ((uint32_t)0x50000000) +#define DVP_BASE ((uint32_t)0x50050000) + +#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) +#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) +#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) + +#define OB_BASE ((uint32_t)0x1FFFF800) +#define FEATURE_SIGN ((uint32_t)0x1FFFF7D0) + +/* Peripheral declaration */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM4 ((TIM_TypeDef *) TIM4_BASE) +#define TIM5 ((TIM_TypeDef *) TIM5_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define UART6 ((USART_TypeDef *) UART6_BASE) +#define UART7 ((USART_TypeDef *) UART7_BASE) +#define UART8 ((USART_TypeDef *) UART8_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define SPI3 ((SPI_TypeDef *) SPI3_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define UART4 ((USART_TypeDef *) UART4_BASE) +#define UART5 ((USART_TypeDef *) UART5_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CAN2 ((CAN_TypeDef *) CAN2_BASE) +#define BKP ((BKP_TypeDef *) BKP_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC ((DAC_TypeDef *) DAC_BASE) + +#define AFIO ((AFIO_TypeDef *) AFIO_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC2 ((ADC_TypeDef *) ADC2_BASE) +#define TKey1 ((ADC_TypeDef *) ADC1_BASE) +#define TKey2 ((ADC_TypeDef *) ADC2_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define TIM8 ((TIM_TypeDef *) TIM8_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define ADC3 ((ADC_TypeDef *) ADC3_BASE) +#define TIM9 ((TIM_TypeDef *) TIM9_BASE) +#define TIM10 ((TIM_TypeDef *) TIM10_BASE) +#define SDIO ((SDIO_TypeDef *) SDIO_BASE) + +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA2 ((DMA_TypeDef *) DMA2_BASE) +#define DMA2_EXTEN ((DMA_TypeDef *) DMA2_EXTEN_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE) +#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE) +#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE) +#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE) +#define DMA2_Channel9 ((DMA_Channel_TypeDef *) DMA2_Channel9_BASE) +#define DMA2_Channel10 ((DMA_Channel_TypeDef *) DMA2_Channel10_BASE) +#define DMA2_Channel11 ((DMA_Channel_TypeDef *) DMA2_Channel11_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define USBHSD ((USBHSD_TypeDef *) USBHS_BASE) +#define USBHSH ((USBHSH_TypeDef *) USBHS_BASE) +#define USBFSD ((USBFSD_TypeDef *)USBFS_BASE) +#define USBFSH ((USBFSH_TypeDef *)USBFS_BASE) +#define EXTEN ((EXTEN_TypeDef *) EXTEN_BASE) +#define OPA ((OPA_TypeDef *) OPA_BASE) +#define RNG ((RNG_TypeDef *) RNG_BASE) +#define ETH ((ETH_TypeDef *) ETH_BASE) + +#define DVP ((DVP_TypeDef *) DVP_BASE) + +#define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE) +#define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE) +#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE) + +#define OB ((OB_TypeDef *) OB_BASE) + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* Analog to Digital Converter */ +/******************************************************************************/ + +/******************** Bit definition for ADC_STATR register ********************/ +#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ +#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ +#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ +#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ +#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ + +/******************* Bit definition for ADC_CTLR1 register ********************/ +#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ +#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ +#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ +#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ +#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ + +#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ +#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ + +#define ADC_DUALMOD ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ +#define ADC_DUALMOD_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define ADC_DUALMOD_1 ((uint32_t)0x00020000) /* Bit 1 */ +#define ADC_DUALMOD_2 ((uint32_t)0x00040000) /* Bit 2 */ +#define ADC_DUALMOD_3 ((uint32_t)0x00080000) /* Bit 3 */ + +#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ + +#define ADC_TKENABLE ((uint32_t)0x01000000) /*TKEY enable*/ +#define ADC_TKITUNE ((uint32_t)0x02000000) +#define ADC_BUFEN ((uint32_t)0x04000000) + +#define ADC_PGA ((uint32_t)0x18000000) +#define ADC_PGA_0 ((uint32_t)0x08000000) +#define ADC_PGA_1 ((uint32_t)0x10000000) +/******************* Bit definition for ADC_CTLR2 register ********************/ +#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ +#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ +#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ +#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ +#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ + +#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ + +#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ +#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ +#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ + +#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ +#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ +#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ + +/****************** Bit definition for ADC_SAMPTR1 register *******************/ +#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ + +/****************** Bit definition for ADC_SAMPTR2 register *******************/ +#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ +#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ +#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ + +/****************** Bit definition for ADC_IOFR1 register *******************/ +#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_IOFR2 register *******************/ +#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_IOFR3 register *******************/ +#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_IOFR4 register *******************/ +#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_WDHTR register ********************/ +#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ + +/******************* Bit definition for ADC_WDLTR register ********************/ +#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ + +/******************* Bit definition for ADC_RSQR1 register *******************/ +#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ + +/******************* Bit definition for ADC_RSQR2 register *******************/ +#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_RSQR3 register *******************/ +#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_ISQR register *******************/ +#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ + +/******************* Bit definition for ADC_IDATAR1 register *******************/ +#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR2 register *******************/ +#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR3 register *******************/ +#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR4 register *******************/ +#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************** Bit definition for ADC_RDATAR register ********************/ +#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ +#define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */ + +/******************** Bit definition for ADC_AUX register ********************/ +#define ADC_SMP_SEL_0 ((uint32_t)0x00000001) /* channel_0 */ +#define ADC_SMP_SEL_1 ((uint32_t)0x00000002) /* channel_1 */ +#define ADC_SMP_SEL_2 ((uint32_t)0x00000004) /* channel_2 */ +#define ADC_SMP_SEL_3 ((uint32_t)0x00000008) /* channel_3 */ +#define ADC_SMP_SEL_4 ((uint32_t)0x00000010) /* channel_4 */ +#define ADC_SMP_SEL_5 ((uint32_t)0x00000020) /* channel_5 */ +#define ADC_SMP_SEL_6 ((uint32_t)0x00000040) /* channel_6 */ +#define ADC_SMP_SEL_7 ((uint32_t)0x00000080) /* channel_7 */ +#define ADC_SMP_SEL_8 ((uint32_t)0x00000100) /* channel_8 */ +#define ADC_SMP_SEL_9 ((uint32_t)0x00000200) /* channel_9 */ +#define ADC_SMP_SEL_10 ((uint32_t)0x00000400) /* channel_10 */ +#define ADC_SMP_SEL_11 ((uint32_t)0x00000800) /* channel_11 */ +#define ADC_SMP_SEL_12 ((uint32_t)0x00001000) /* channel_12 */ +#define ADC_SMP_SEL_13 ((uint32_t)0x00002000) /* channel_13 */ +#define ADC_SMP_SEL_14 ((uint32_t)0x00004000) /* channel_14 */ +#define ADC_SMP_SEL_15 ((uint32_t)0x00008000) /* channel_15 */ +#define ADC_SMP_SEL_16 ((uint32_t)0x00010000) /* channel_16 */ +#define ADC_SMP_SEL_17 ((uint32_t)0x00020000) /* channel_17 */ + +/******************************************************************************/ +/* Backup registers */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DATAR1 register ********************/ +#define BKP_DATAR1_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR2 register ********************/ +#define BKP_DATAR2_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR3 register ********************/ +#define BKP_DATAR3_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR4 register ********************/ +#define BKP_DATAR4_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR5 register ********************/ +#define BKP_DATAR5_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR6 register ********************/ +#define BKP_DATAR6_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR7 register ********************/ +#define BKP_DATAR7_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR8 register ********************/ +#define BKP_DATAR8_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR9 register ********************/ +#define BKP_DATAR9_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR10 register *******************/ +#define BKP_DATAR10_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR11 register *******************/ +#define BKP_DATAR11_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR12 register *******************/ +#define BKP_DATAR12_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR13 register *******************/ +#define BKP_DATAR13_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR14 register *******************/ +#define BKP_DATAR14_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR15 register *******************/ +#define BKP_DATAR15_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR16 register *******************/ +#define BKP_DATAR16_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR17 register *******************/ +#define BKP_DATAR17_D ((uint16_t)0xFFFF) /* Backup data */ + +/****************** Bit definition for BKP_DATAR18 register ********************/ +#define BKP_DATAR18_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR19 register *******************/ +#define BKP_DATAR19_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR20 register *******************/ +#define BKP_DATAR20_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR21 register *******************/ +#define BKP_DATAR21_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR22 register *******************/ +#define BKP_DATAR22_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR23 register *******************/ +#define BKP_DATAR23_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR24 register *******************/ +#define BKP_DATAR24_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR25 register *******************/ +#define BKP_DATAR25_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR26 register *******************/ +#define BKP_DATAR26_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR27 register *******************/ +#define BKP_DATAR27_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR28 register *******************/ +#define BKP_DATAR28_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR29 register *******************/ +#define BKP_DATAR29_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR30 register *******************/ +#define BKP_DATAR30_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR31 register *******************/ +#define BKP_DATAR31_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR32 register *******************/ +#define BKP_DATAR32_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR33 register *******************/ +#define BKP_DATAR33_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR34 register *******************/ +#define BKP_DATAR34_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR35 register *******************/ +#define BKP_DATAR35_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR36 register *******************/ +#define BKP_DATAR36_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR37 register *******************/ +#define BKP_DATAR37_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR38 register *******************/ +#define BKP_DATAR38_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR39 register *******************/ +#define BKP_DATAR39_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR40 register *******************/ +#define BKP_DATAR40_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR41 register *******************/ +#define BKP_DATAR41_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR42 register *******************/ +#define BKP_DATAR42_D ((uint16_t)0xFFFF) /* Backup data */ + +/****************** Bit definition for BKP_OCTLR register *******************/ +#define BKP_CAL ((uint16_t)0x007F) /* Calibration value */ +#define BKP_CCO ((uint16_t)0x0080) /* Calibration Clock Output */ +#define BKP_ASOE ((uint16_t)0x0100) /* Alarm or Second Output Enable */ +#define BKP_ASOS ((uint16_t)0x0200) /* Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_TPCTLR register ********************/ +#define BKP_TPE ((uint8_t)0x01) /* TAMPER pin enable */ +#define BKP_TPAL ((uint8_t)0x02) /* TAMPER pin active level */ + +/******************* Bit definition for BKP_TPCSR register ********************/ +#define BKP_CTE ((uint16_t)0x0001) /* Clear Tamper event */ +#define BKP_CTI ((uint16_t)0x0002) /* Clear Tamper Interrupt */ +#define BKP_TPIE ((uint16_t)0x0004) /* TAMPER Pin interrupt enable */ +#define BKP_TEF ((uint16_t)0x0100) /* Tamper Event Flag */ +#define BKP_TIF ((uint16_t)0x0200) /* Tamper Interrupt Flag */ + +/******************************************************************************/ +/* Controller Area Network */ +/******************************************************************************/ + +/******************* Bit definition for CAN_CTLR register ********************/ +#define CAN_CTLR_INRQ ((uint16_t)0x0001) /* Initialization Request */ +#define CAN_CTLR_SLEEP ((uint16_t)0x0002) /* Sleep Mode Request */ +#define CAN_CTLR_TXFP ((uint16_t)0x0004) /* Transmit FIFO Priority */ +#define CAN_CTLR_RFLM ((uint16_t)0x0008) /* Receive FIFO Locked Mode */ +#define CAN_CTLR_NART ((uint16_t)0x0010) /* No Automatic Retransmission */ +#define CAN_CTLR_AWUM ((uint16_t)0x0020) /* Automatic Wakeup Mode */ +#define CAN_CTLR_ABOM ((uint16_t)0x0040) /* Automatic Bus-Off Management */ +#define CAN_CTLR_TTCM ((uint16_t)0x0080) /* Time Triggered Communication Mode */ +#define CAN_CTLR_RESET ((uint16_t)0x8000) /* CAN software master reset */ +#define CAN_CTLR_DBF ((uint32_t)0x10000) + +/******************* Bit definition for CAN_STATR register ********************/ +#define CAN_STATR_INAK ((uint16_t)0x0001) /* Initialization Acknowledge */ +#define CAN_STATR_SLAK ((uint16_t)0x0002) /* Sleep Acknowledge */ +#define CAN_STATR_ERRI ((uint16_t)0x0004) /* Error Interrupt */ +#define CAN_STATR_WKUI ((uint16_t)0x0008) /* Wakeup Interrupt */ +#define CAN_STATR_SLAKI ((uint16_t)0x0010) /* Sleep Acknowledge Interrupt */ +#define CAN_STATR_TXM ((uint16_t)0x0100) /* Transmit Mode */ +#define CAN_STATR_RXM ((uint16_t)0x0200) /* Receive Mode */ +#define CAN_STATR_SAMP ((uint16_t)0x0400) /* Last Sample Point */ +#define CAN_STATR_RX ((uint16_t)0x0800) /* CAN Rx Signal */ + +/******************* Bit definition for CAN_TSTATR register ********************/ +#define CAN_TSTATR_RQCP0 ((uint32_t)0x00000001) /* Request Completed Mailbox0 */ +#define CAN_TSTATR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of Mailbox0 */ +#define CAN_TSTATR_ALST0 ((uint32_t)0x00000004) /* Arbitration Lost for Mailbox0 */ +#define CAN_TSTATR_TERR0 ((uint32_t)0x00000008) /* Transmission Error of Mailbox0 */ +#define CAN_TSTATR_ABRQ0 ((uint32_t)0x00000080) /* Abort Request for Mailbox0 */ +#define CAN_TSTATR_RQCP1 ((uint32_t)0x00000100) /* Request Completed Mailbox1 */ +#define CAN_TSTATR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of Mailbox1 */ +#define CAN_TSTATR_ALST1 ((uint32_t)0x00000400) /* Arbitration Lost for Mailbox1 */ +#define CAN_TSTATR_TERR1 ((uint32_t)0x00000800) /* Transmission Error of Mailbox1 */ +#define CAN_TSTATR_ABRQ1 ((uint32_t)0x00008000) /* Abort Request for Mailbox 1 */ +#define CAN_TSTATR_RQCP2 ((uint32_t)0x00010000) /* Request Completed Mailbox2 */ +#define CAN_TSTATR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of Mailbox 2 */ +#define CAN_TSTATR_ALST2 ((uint32_t)0x00040000) /* Arbitration Lost for mailbox 2 */ +#define CAN_TSTATR_TERR2 ((uint32_t)0x00080000) /* Transmission Error of Mailbox 2 */ +#define CAN_TSTATR_ABRQ2 ((uint32_t)0x00800000) /* Abort Request for Mailbox 2 */ +#define CAN_TSTATR_CODE ((uint32_t)0x03000000) /* Mailbox Code */ + +#define CAN_TSTATR_TME ((uint32_t)0x1C000000) /* TME[2:0] bits */ +#define CAN_TSTATR_TME0 ((uint32_t)0x04000000) /* Transmit Mailbox 0 Empty */ +#define CAN_TSTATR_TME1 ((uint32_t)0x08000000) /* Transmit Mailbox 1 Empty */ +#define CAN_TSTATR_TME2 ((uint32_t)0x10000000) /* Transmit Mailbox 2 Empty */ + +#define CAN_TSTATR_LOW ((uint32_t)0xE0000000) /* LOW[2:0] bits */ +#define CAN_TSTATR_LOW0 ((uint32_t)0x20000000) /* Lowest Priority Flag for Mailbox 0 */ +#define CAN_TSTATR_LOW1 ((uint32_t)0x40000000) /* Lowest Priority Flag for Mailbox 1 */ +#define CAN_TSTATR_LOW2 ((uint32_t)0x80000000) /* Lowest Priority Flag for Mailbox 2 */ + +/******************* Bit definition for CAN_RFIFO0 register *******************/ +#define CAN_RFIFO0_FMP0 ((uint8_t)0x03) /* FIFO 0 Message Pending */ +#define CAN_RFIFO0_FULL0 ((uint8_t)0x08) /* FIFO 0 Full */ +#define CAN_RFIFO0_FOVR0 ((uint8_t)0x10) /* FIFO 0 Overrun */ +#define CAN_RFIFO0_RFOM0 ((uint8_t)0x20) /* Release FIFO 0 Output Mailbox */ + +/******************* Bit definition for CAN_RFIFO1 register *******************/ +#define CAN_RFIFO1_FMP1 ((uint8_t)0x03) /* FIFO 1 Message Pending */ +#define CAN_RFIFO1_FULL1 ((uint8_t)0x08) /* FIFO 1 Full */ +#define CAN_RFIFO1_FOVR1 ((uint8_t)0x10) /* FIFO 1 Overrun */ +#define CAN_RFIFO1_RFOM1 ((uint8_t)0x20) /* Release FIFO 1 Output Mailbox */ + +/******************** Bit definition for CAN_INTENR register *******************/ +#define CAN_INTENR_TMEIE ((uint32_t)0x00000001) /* Transmit Mailbox Empty Interrupt Enable */ +#define CAN_INTENR_FMPIE0 ((uint32_t)0x00000002) /* FIFO Message Pending Interrupt Enable */ +#define CAN_INTENR_FFIE0 ((uint32_t)0x00000004) /* FIFO Full Interrupt Enable */ +#define CAN_INTENR_FOVIE0 ((uint32_t)0x00000008) /* FIFO Overrun Interrupt Enable */ +#define CAN_INTENR_FMPIE1 ((uint32_t)0x00000010) /* FIFO Message Pending Interrupt Enable */ +#define CAN_INTENR_FFIE1 ((uint32_t)0x00000020) /* FIFO Full Interrupt Enable */ +#define CAN_INTENR_FOVIE1 ((uint32_t)0x00000040) /* FIFO Overrun Interrupt Enable */ +#define CAN_INTENR_EWGIE ((uint32_t)0x00000100) /* Error Warning Interrupt Enable */ +#define CAN_INTENR_EPVIE ((uint32_t)0x00000200) /* Error Passive Interrupt Enable */ +#define CAN_INTENR_BOFIE ((uint32_t)0x00000400) /* Bus-Off Interrupt Enable */ +#define CAN_INTENR_LECIE ((uint32_t)0x00000800) /* Last Error Code Interrupt Enable */ +#define CAN_INTENR_ERRIE ((uint32_t)0x00008000) /* Error Interrupt Enable */ +#define CAN_INTENR_WKUIE ((uint32_t)0x00010000) /* Wakeup Interrupt Enable */ +#define CAN_INTENR_SLKIE ((uint32_t)0x00020000) /* Sleep Interrupt Enable */ + +/******************** Bit definition for CAN_ERRSR register *******************/ +#define CAN_ERRSR_EWGF ((uint32_t)0x00000001) /* Error Warning Flag */ +#define CAN_ERRSR_EPVF ((uint32_t)0x00000002) /* Error Passive Flag */ +#define CAN_ERRSR_BOFF ((uint32_t)0x00000004) /* Bus-Off Flag */ + +#define CAN_ERRSR_LEC ((uint32_t)0x00000070) /* LEC[2:0] bits (Last Error Code) */ +#define CAN_ERRSR_LEC_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define CAN_ERRSR_LEC_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define CAN_ERRSR_LEC_2 ((uint32_t)0x00000040) /* Bit 2 */ + +#define CAN_ERRSR_TEC ((uint32_t)0x00FF0000) /* Least significant byte of the 9-bit Transmit Error Counter */ +#define CAN_ERRSR_REC ((uint32_t)0xFF000000) /* Receive Error Counter */ + +/******************* Bit definition for CAN_TTCTLR register ********************/ +#define CAN_TTCTLR_TIMCMV ((uint32_t)0x0000FFFF) +#define CAN_TTCTLR_TIMRST ((uint32_t)0x00010000) +#define CAN_TTCTLR_MODE ((uint32_t)0x00020000) + +/******************* Bit definition for CAN_TTCNT register ********************/ +#define CAN_TTCNT_TIMCNT ((uint32_t)0x0000FFFF) + +/****************** Bit definition for CAN_TXMI0R register ********************/ +#define CAN_TXMI0R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_TXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/****************** Bit definition for CAN_TXMDT0R register *******************/ +#define CAN_TXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT0R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/****************** Bit definition for CAN_TXMDL0R register *******************/ +#define CAN_TXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/****************** Bit definition for CAN_TXMDH0R register *******************/ +#define CAN_TXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_TXMI1R register *******************/ +#define CAN_TXMI1R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_TXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TXMDT1R register ******************/ +#define CAN_TXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT1R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_TXMDL1R register ******************/ +#define CAN_TXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_TXMDH1R register ******************/ +#define CAN_TXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_TXMI2R register *******************/ +#define CAN_TXMI2R_TXRQ ((uint32_t)0x00000001) /* Transmit Mailbox Request */ +#define CAN_TXMI2R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_TXMI2R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_TXMI2R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ +#define CAN_TXMI2R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_TXMDT2R register ******************/ +#define CAN_TXMDT2R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_TXMDT2R_TGT ((uint32_t)0x00000100) /* Transmit Global Time */ +#define CAN_TXMDT2R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_TXMDL2R register ******************/ +#define CAN_TXMDL2R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_TXMDL2R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_TXMDL2R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_TXMDL2R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_TXMDH2R register ******************/ +#define CAN_TXMDH2R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_TXMDH2R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_TXMDH2R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_TXMDH2R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_RXMI0R register *******************/ +#define CAN_RXMI0R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_RXMI0R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_RXMI0R_EXID ((uint32_t)0x001FFFF8) /* Extended Identifier */ +#define CAN_RXMI0R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RXMDT0R register ******************/ +#define CAN_RXMDT0R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_RXMDT0R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ +#define CAN_RXMDT0R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_RXMDL0R register ******************/ +#define CAN_RXMDL0R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_RXMDL0R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_RXMDL0R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_RXMDL0R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_RXMDH0R register ******************/ +#define CAN_RXMDH0R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_RXMDH0R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_RXMDH0R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_RXMDH0R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_RXMI1R register *******************/ +#define CAN_RXMI1R_RTR ((uint32_t)0x00000002) /* Remote Transmission Request */ +#define CAN_RXMI1R_IDE ((uint32_t)0x00000004) /* Identifier Extension */ +#define CAN_RXMI1R_EXID ((uint32_t)0x001FFFF8) /* Extended identifier */ +#define CAN_RXMI1R_STID ((uint32_t)0xFFE00000) /* Standard Identifier or Extended Identifier */ + +/******************* Bit definition for CAN_RXMDT1R register ******************/ +#define CAN_RXMDT1R_DLC ((uint32_t)0x0000000F) /* Data Length Code */ +#define CAN_RXMDT1R_FMI ((uint32_t)0x0000FF00) /* Filter Match Index */ +#define CAN_RXMDT1R_TIME ((uint32_t)0xFFFF0000) /* Message Time Stamp */ + +/******************* Bit definition for CAN_RXMDL1R register ******************/ +#define CAN_RXMDL1R_DATA0 ((uint32_t)0x000000FF) /* Data byte 0 */ +#define CAN_RXMDL1R_DATA1 ((uint32_t)0x0000FF00) /* Data byte 1 */ +#define CAN_RXMDL1R_DATA2 ((uint32_t)0x00FF0000) /* Data byte 2 */ +#define CAN_RXMDL1R_DATA3 ((uint32_t)0xFF000000) /* Data byte 3 */ + +/******************* Bit definition for CAN_RXMDH1R register ******************/ +#define CAN_RXMDH1R_DATA4 ((uint32_t)0x000000FF) /* Data byte 4 */ +#define CAN_RXMDH1R_DATA5 ((uint32_t)0x0000FF00) /* Data byte 5 */ +#define CAN_RXMDH1R_DATA6 ((uint32_t)0x00FF0000) /* Data byte 6 */ +#define CAN_RXMDH1R_DATA7 ((uint32_t)0xFF000000) /* Data byte 7 */ + +/******************* Bit definition for CAN_FCTLR register ********************/ +#define CAN_FCTLR_FINIT ((uint8_t)0x01) /* Filter Init Mode */ +#define CAN_FCTLR_CAN2SB ((uint16_t)0x3F00) + +/******************* Bit definition for CAN_FMCFGR register *******************/ +#define CAN_FMCFGR_FBM ((uint16_t)0x3FFF) /* Filter Mode */ +#define CAN_FMCFGR_FBM0 ((uint16_t)0x0001) /* Filter Init Mode bit 0 */ +#define CAN_FMCFGR_FBM1 ((uint16_t)0x0002) /* Filter Init Mode bit 1 */ +#define CAN_FMCFGR_FBM2 ((uint16_t)0x0004) /* Filter Init Mode bit 2 */ +#define CAN_FMCFGR_FBM3 ((uint16_t)0x0008) /* Filter Init Mode bit 3 */ +#define CAN_FMCFGR_FBM4 ((uint16_t)0x0010) /* Filter Init Mode bit 4 */ +#define CAN_FMCFGR_FBM5 ((uint16_t)0x0020) /* Filter Init Mode bit 5 */ +#define CAN_FMCFGR_FBM6 ((uint16_t)0x0040) /* Filter Init Mode bit 6 */ +#define CAN_FMCFGR_FBM7 ((uint16_t)0x0080) /* Filter Init Mode bit 7 */ +#define CAN_FMCFGR_FBM8 ((uint16_t)0x0100) /* Filter Init Mode bit 8 */ +#define CAN_FMCFGR_FBM9 ((uint16_t)0x0200) /* Filter Init Mode bit 9 */ +#define CAN_FMCFGR_FBM10 ((uint16_t)0x0400) /* Filter Init Mode bit 10 */ +#define CAN_FMCFGR_FBM11 ((uint16_t)0x0800) /* Filter Init Mode bit 11 */ +#define CAN_FMCFGR_FBM12 ((uint16_t)0x1000) /* Filter Init Mode bit 12 */ +#define CAN_FMCFGR_FBM13 ((uint16_t)0x2000) /* Filter Init Mode bit 13 */ +#define CAN_FMCFGR_FBM14 ((uint16_t)0x4000) /* Filter Init Mode bit 14 */ +#define CAN_FMCFGR_FBM15 ((uint16_t)0x8000) /* Filter Init Mode bit 15 */ +#define CAN_FMCFGR_FBM16 ((uint32_t)0x10000) /* Filter Init Mode bit 16 */ +#define CAN_FMCFGR_FBM17 ((uint32_t)0x20000) /* Filter Init Mode bit 17 */ +#define CAN_FMCFGR_FBM18 ((uint32_t)0x40000) /* Filter Init Mode bit 18 */ +#define CAN_FMCFGR_FBM19 ((uint32_t)0x80000) /* Filter Init Mode bit 19 */ +#define CAN_FMCFGR_FBM20 ((uint32_t)0x100000) /* Filter Init Mode bit 20 */ +#define CAN_FMCFGR_FBM21 ((uint32_t)0x200000) /* Filter Init Mode bit 21 */ +#define CAN_FMCFGR_FBM22 ((uint32_t)0x400000) /* Filter Init Mode bit 22 */ +#define CAN_FMCFGR_FBM23 ((uint32_t)0x800000) /* Filter Init Mode bit 23 */ +#define CAN_FMCFGR_FBM24 ((uint32_t)0x1000000) /* Filter Init Mode bit 24 */ +#define CAN_FMCFGR_FBM25 ((uint32_t)0x2000000) /* Filter Init Mode bit 25 */ +#define CAN_FMCFGR_FBM26 ((uint32_t)0x4000000) /* Filter Init Mode bit 26 */ +#define CAN_FMCFGR_FBM27 ((uint32_t)0x8000000) /* Filter Init Mode bit 27 */ + +/******************* Bit definition for CAN_FSCFGR register *******************/ +#define CAN_FSCFGR_FSC ((uint16_t)0x3FFF) /* Filter Scale Configuration */ +#define CAN_FSCFGR_FSC0 ((uint16_t)0x0001) /* Filter Scale Configuration bit 0 */ +#define CAN_FSCFGR_FSC1 ((uint16_t)0x0002) /* Filter Scale Configuration bit 1 */ +#define CAN_FSCFGR_FSC2 ((uint16_t)0x0004) /* Filter Scale Configuration bit 2 */ +#define CAN_FSCFGR_FSC3 ((uint16_t)0x0008) /* Filter Scale Configuration bit 3 */ +#define CAN_FSCFGR_FSC4 ((uint16_t)0x0010) /* Filter Scale Configuration bit 4 */ +#define CAN_FSCFGR_FSC5 ((uint16_t)0x0020) /* Filter Scale Configuration bit 5 */ +#define CAN_FSCFGR_FSC6 ((uint16_t)0x0040) /* Filter Scale Configuration bit 6 */ +#define CAN_FSCFGR_FSC7 ((uint16_t)0x0080) /* Filter Scale Configuration bit 7 */ +#define CAN_FSCFGR_FSC8 ((uint16_t)0x0100) /* Filter Scale Configuration bit 8 */ +#define CAN_FSCFGR_FSC9 ((uint16_t)0x0200) /* Filter Scale Configuration bit 9 */ +#define CAN_FSCFGR_FSC10 ((uint16_t)0x0400) /* Filter Scale Configuration bit 10 */ +#define CAN_FSCFGR_FSC11 ((uint16_t)0x0800) /* Filter Scale Configuration bit 11 */ +#define CAN_FSCFGR_FSC12 ((uint16_t)0x1000) /* Filter Scale Configuration bit 12 */ +#define CAN_FSCFGR_FSC13 ((uint16_t)0x2000) /* Filter Scale Configuration bit 13 */ +#define CAN_FSCFGR_FSC14 ((uint16_t)0x4000) /* Filter Scale Configuration bit 14 */ +#define CAN_FSCFGR_FSC15 ((uint16_t)0x8000) /* Filter Scale Configuration bit 15 */ +#define CAN_FSCFGR_FSC16 ((uint32_t)0x10000) /* Filter Scale Configuration bit 16 */ +#define CAN_FSCFGR_FSC17 ((uint32_t)0x20000) /* Filter Scale Configuration bit 17 */ +#define CAN_FSCFGR_FSC18 ((uint32_t)0x40000) /* Filter Scale Configuration bit 18 */ +#define CAN_FSCFGR_FSC19 ((uint32_t)0x80000) /* Filter Scale Configuration bit 19 */ +#define CAN_FSCFGR_FSC20 ((uint32_t)0x100000) /* Filter Scale Configuration bit 20 */ +#define CAN_FSCFGR_FSC21 ((uint32_t)0x200000) /* Filter Scale Configuration bit 21 */ +#define CAN_FSCFGR_FSC22 ((uint32_t)0x400000) /* Filter Scale Configuration bit 22 */ +#define CAN_FSCFGR_FSC23 ((uint32_t)0x800000) /* Filter Scale Configuration bit 23 */ +#define CAN_FSCFGR_FSC24 ((uint32_t)0x1000000) /* Filter Scale Configuration bit 24 */ +#define CAN_FSCFGR_FSC25 ((uint32_t)0x2000000) /* Filter Scale Configuration bit 25 */ +#define CAN_FSCFGR_FSC26 ((uint32_t)0x4000000) /* Filter Scale Configuration bit 26 */ +#define CAN_FSCFGR_FSC27 ((uint32_t)0x8000000) /* Filter Scale Configuration bit 27 */ + +/****************** Bit definition for CAN_FAFIFOR register *******************/ +#define CAN_FAFIFOR_FFA ((uint16_t)0x3FFF) /* Filter FIFO Assignment */ +#define CAN_FAFIFOR_FFA0 ((uint16_t)0x0001) /* Filter FIFO Assignment for Filter 0 */ +#define CAN_FAFIFOR_FFA1 ((uint16_t)0x0002) /* Filter FIFO Assignment for Filter 1 */ +#define CAN_FAFIFOR_FFA2 ((uint16_t)0x0004) /* Filter FIFO Assignment for Filter 2 */ +#define CAN_FAFIFOR_FFA3 ((uint16_t)0x0008) /* Filter FIFO Assignment for Filter 3 */ +#define CAN_FAFIFOR_FFA4 ((uint16_t)0x0010) /* Filter FIFO Assignment for Filter 4 */ +#define CAN_FAFIFOR_FFA5 ((uint16_t)0x0020) /* Filter FIFO Assignment for Filter 5 */ +#define CAN_FAFIFOR_FFA6 ((uint16_t)0x0040) /* Filter FIFO Assignment for Filter 6 */ +#define CAN_FAFIFOR_FFA7 ((uint16_t)0x0080) /* Filter FIFO Assignment for Filter 7 */ +#define CAN_FAFIFOR_FFA8 ((uint16_t)0x0100) /* Filter FIFO Assignment for Filter 8 */ +#define CAN_FAFIFOR_FFA9 ((uint16_t)0x0200) /* Filter FIFO Assignment for Filter 9 */ +#define CAN_FAFIFOR_FFA10 ((uint16_t)0x0400) /* Filter FIFO Assignment for Filter 10 */ +#define CAN_FAFIFOR_FFA11 ((uint16_t)0x0800) /* Filter FIFO Assignment for Filter 11 */ +#define CAN_FAFIFOR_FFA12 ((uint16_t)0x1000) /* Filter FIFO Assignment for Filter 12 */ +#define CAN_FAFIFOR_FFA13 ((uint16_t)0x2000) /* Filter FIFO Assignment for Filter 13 */ +#define CAN_FAFIFOR_FFA14 ((uint32_t)0x4000) /* Filter FIFO Assignment for Filter 14 */ +#define CAN_FAFIFOR_FFA15 ((uint32_t)0x8000) /* Filter FIFO Assignment for Filter 15 */ +#define CAN_FAFIFOR_FFA16 ((uint32_t)0x10000) /* Filter FIFO Assignment for Filter 16 */ +#define CAN_FAFIFOR_FFA17 ((uint32_t)0x20000) /* Filter FIFO Assignment for Filter 17 */ +#define CAN_FAFIFOR_FFA18 ((uint32_t)0x40000) /* Filter FIFO Assignment for Filter 18 */ +#define CAN_FAFIFOR_FFA19 ((uint32_t)0x80000) /* Filter FIFO Assignment for Filter 19 */ +#define CAN_FAFIFOR_FFA20 ((uint32_t)0x100000) /* Filter FIFO Assignment for Filter 20 */ +#define CAN_FAFIFOR_FFA21 ((uint32_t)0x200000) /* Filter FIFO Assignment for Filter 21 */ +#define CAN_FAFIFOR_FFA22 ((uint32_t)0x400000) /* Filter FIFO Assignment for Filter 22 */ +#define CAN_FAFIFOR_FFA23 ((uint32_t)0x800000) /* Filter FIFO Assignment for Filter 23 */ +#define CAN_FAFIFOR_FFA24 ((uint32_t)0x1000000) /* Filter FIFO Assignment for Filter 24 */ +#define CAN_FAFIFOR_FFA25 ((uint32_t)0x2000000) /* Filter FIFO Assignment for Filter 25 */ +#define CAN_FAFIFOR_FFA26 ((uint32_t)0x4000000) /* Filter FIFO Assignment for Filter 26 */ +#define CAN_FAFIFOR_FFA27 ((uint32_t)0x8000000) /* Filter FIFO Assignment for Filter 27 */ + +/******************* Bit definition for CAN_FWR register *******************/ +#define CAN_FWR_FACT ((uint16_t)0x3FFF) /* Filter Active */ +#define CAN_FWR_FACT0 ((uint16_t)0x0001) /* Filter 0 Active */ +#define CAN_FWR_FACT1 ((uint16_t)0x0002) /* Filter 1 Active */ +#define CAN_FWR_FACT2 ((uint16_t)0x0004) /* Filter 2 Active */ +#define CAN_FWR_FACT3 ((uint16_t)0x0008) /* Filter 3 Active */ +#define CAN_FWR_FACT4 ((uint16_t)0x0010) /* Filter 4 Active */ +#define CAN_FWR_FACT5 ((uint16_t)0x0020) /* Filter 5 Active */ +#define CAN_FWR_FACT6 ((uint16_t)0x0040) /* Filter 6 Active */ +#define CAN_FWR_FACT7 ((uint16_t)0x0080) /* Filter 7 Active */ +#define CAN_FWR_FACT8 ((uint16_t)0x0100) /* Filter 8 Active */ +#define CAN_FWR_FACT9 ((uint16_t)0x0200) /* Filter 9 Active */ +#define CAN_FWR_FACT10 ((uint16_t)0x0400) /* Filter 10 Active */ +#define CAN_FWR_FACT11 ((uint16_t)0x0800) /* Filter 11 Active */ +#define CAN_FWR_FACT12 ((uint16_t)0x1000) /* Filter 12 Active */ +#define CAN_FWR_FACT13 ((uint16_t)0x2000) /* Filter 13 Active */ +#define CAN_FWR_FACT14 ((uint16_t)0x4000) /* Filter 14 Active */ +#define CAN_FWR_FACT15 ((uint16_t)0x8000) /* Filter 15 Active */ +#define CAN_FWR_FACT16 ((uint32_t)0x10000) /* Filter 16 Active */ +#define CAN_FWR_FACT17 ((uint32_t)0x20000) /* Filter 17 Active */ +#define CAN_FWR_FACT18 ((uint32_t)0x40000) /* Filter 18 Active */ +#define CAN_FWR_FACT19 ((uint32_t)0x80000) /* Filter 19 Active */ +#define CAN_FWR_FACT20 ((uint32_t)0x100000) /* Filter 20 Active */ +#define CAN_FWR_FACT21 ((uint32_t)0x200000) /* Filter 21 Active */ +#define CAN_FWR_FACT22 ((uint32_t)0x400000) /* Filter 22 Active */ +#define CAN_FWR_FACT23 ((uint32_t)0x800000) /* Filter 23 Active */ +#define CAN_FWR_FACT24 ((uint32_t)0x1000000) /* Filter 24 Active */ +#define CAN_FWR_FACT25 ((uint32_t)0x2000000) /* Filter 25 Active */ +#define CAN_FWR_FACT26 ((uint32_t)0x4000000) /* Filter 26 Active */ +#define CAN_FWR_FACT27 ((uint32_t)0x8000000) /* Filter 27 Active */ + +/******************* Bit definition for CAN_F0R1 register *******************/ +#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F1R1 register *******************/ +#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F2R1 register *******************/ +#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F3R1 register *******************/ +#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F4R1 register *******************/ +#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F5R1 register *******************/ +#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F6R1 register *******************/ +#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F7R1 register *******************/ +#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F8R1 register *******************/ +#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F9R1 register *******************/ +#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F10R1 register ******************/ +#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F11R1 register ******************/ +#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F12R1 register ******************/ +#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F13R1 register ******************/ +#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F14R1 register ******************/ +#define CAN_F14R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F14R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F14R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F14R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F14R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F14R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F14R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F14R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F14R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F14R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F14R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F14R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F14R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F14R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F14R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F14R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F14R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F14R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F14R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F14R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F14R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F14R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F14R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F14R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F14R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F14R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F14R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F14R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F14R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F14R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F14R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F14R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + + +/******************* Bit definition for CAN_F15R1 register *******************/ +#define CAN_F15R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F15R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F15R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F15R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F15R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F15R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F15R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F15R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F15R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F15R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F15R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F15R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F15R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F15R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F15R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F15R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F15R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F15R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F15R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F15R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F15R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F15R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F15R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F15R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F15R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F15R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F15R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F15R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F15R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F15R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F15R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F15R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F16R1 register *******************/ +#define CAN_F16R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F16R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F16R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F16R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F16R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F16R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F16R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F16R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F16R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F16R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F16R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F16R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F16R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F16R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F16R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F16R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F16R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F16R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F16R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F16R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F16R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F16R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F16R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F16R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F16R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F16R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F16R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F16R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F16R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F16R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F16R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F16R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F17R1 register *******************/ +#define CAN_F17R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F17R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F17R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F17R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F17R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F17R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F17R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F17R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F17R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F17R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F17R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F17R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F17R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F17R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F17R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F17R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F17R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F17R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F17R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F17R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F17R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F17R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F17R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F17R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F17R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F17R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F17R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F17R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F17R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F17R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F17R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F17R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F18R1 register *******************/ +#define CAN_F18R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F18R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F18R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F18R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F18R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F18R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F18R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F18R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F18R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F18R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F18R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F18R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F18R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F18R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F18R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F18R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F18R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F18R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F18R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F18R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F18R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F18R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F18R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F18R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F18R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F18R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F18R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F18R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F18R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F18R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F18R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F18R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F19R1 register *******************/ +#define CAN_F19R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F19R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F19R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F19R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F19R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F19R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F19R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F19R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F19R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F19R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F19R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F19R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F19R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F19R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F19R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F19R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F19R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F19R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F19R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F19R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F19R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F19R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F19R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F19R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F19R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F19R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F19R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F19R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F19R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F19R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F19R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F19R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F20R1 register *******************/ +#define CAN_F20R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F20R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F20R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F20R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F20R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F20R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F20R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F20R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F20R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F20R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F20R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F20R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F20R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F20R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F20R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F20R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F20R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F20R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F20R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F20R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F20R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F20R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F20R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F20R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F20R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F20R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F20R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F20R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F20R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F20R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F20R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F20R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F21R1 register *******************/ +#define CAN_F21R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F21R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F21R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F21R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F21R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F21R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F21R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F21R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F21R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F21R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F21R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F21R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F21R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F21R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F21R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F21R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F21R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F21R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F21R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F21R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F21R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F21R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F21R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F21R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F21R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F21R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F21R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F21R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F21R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F21R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F21R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F21R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F22R1 register *******************/ +#define CAN_F22R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F22R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F22R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F22R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F22R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F22R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F22R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F22R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F22R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F22R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F22R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F22R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F22R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F22R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F22R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F22R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F22R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F22R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F22R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F22R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F22R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F22R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F22R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F22R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F22R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F22R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F22R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F22R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F22R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F22R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F22R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F22R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F23R1 register ******************/ +#define CAN_F23R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F23R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F23R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F23R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F23R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F23R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F23R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F23R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F23R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F23R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F23R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F23R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F23R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F23R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F23R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F23R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F23R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F23R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F23R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F23R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F23R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F23R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F23R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F23R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F23R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F23R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F23R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F23R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F23R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F23R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F23R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F23R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F24R1 register ******************/ +#define CAN_F24R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F24R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F24R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F24R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F24R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F24R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F24R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F24R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F24R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F24R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F24R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F24R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F24R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F24R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F24R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F24R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F24R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F24R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F24R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F24R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F24R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F24R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F24R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F24R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F24R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F24R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F24R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F24R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F24R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F24R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F24R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F24R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F25R1 register ******************/ +#define CAN_F25R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F25R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F25R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F25R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F25R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F25R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F25R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F25R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F25R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F25R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F25R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F25R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F25R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F25R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F25R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F25R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F25R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F25R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F25R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F25R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F25R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F25R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F25R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F25R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F25R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F25R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F25R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F25R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F25R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F25R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F25R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F25R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F26R1 register ******************/ +#define CAN_F26R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F26R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F26R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F26R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F26R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F26R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F26R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F26R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F26R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F26R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F26R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F26R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F26R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F26R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F26R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F26R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F26R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F26R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F26R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F26R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F26R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F26R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F26R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F26R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F26R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F26R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F26R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F26R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F26R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F26R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F26R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F26R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F27R1 register ******************/ +#define CAN_F27R1_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F27R1_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F27R1_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F27R1_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F27R1_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F27R1_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F27R1_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F27R1_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F27R1_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F27R1_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F27R1_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F27R1_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F27R1_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F27R1_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F27R1_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F27R1_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F27R1_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F27R1_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F27R1_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F27R1_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F27R1_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F27R1_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F27R1_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F27R1_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F27R1_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F27R1_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F27R1_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F27R1_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F27R1_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F27R1_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F27R1_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F27R1_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F0R2 register *******************/ +#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F1R2 register *******************/ +#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F2R2 register *******************/ +#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F3R2 register *******************/ +#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F4R2 register *******************/ +#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F5R2 register *******************/ +#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F6R2 register *******************/ +#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F7R2 register *******************/ +#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F8R2 register *******************/ +#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F9R2 register *******************/ +#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F10R2 register ******************/ +#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F11R2 register ******************/ +#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F12R2 register ******************/ +#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F13R2 register ******************/ +#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F14R2 register *******************/ +#define CAN_F14R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F14R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F14R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F14R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F14R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F14R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F14R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F14R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F14R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F14R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F14R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F14R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F14R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F14R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F14R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F14R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F14R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F14R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F14R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F14R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F14R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F14R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F14R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F14R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F14R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F14R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F14R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F14R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F14R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F14R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F14R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F14R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F15R2 register *******************/ +#define CAN_F15R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F15R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F15R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F15R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F15R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F15R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F15R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F15R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F15R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F15R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F15R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F15R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F15R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F15R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F15R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F15R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F15R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F15R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F15R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F15R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F15R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F15R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F15R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F15R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F15R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F15R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F15R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F15R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F15R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F15R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F15R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F15R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F16R2 register *******************/ +#define CAN_F16R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F16R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F16R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F16R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F16R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F16R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F16R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F16R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F16R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F16R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F16R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F16R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F16R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F16R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F16R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F16R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F16R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F16R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F16R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F16R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F16R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F16R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F16R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F16R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F16R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F16R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F16R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F16R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F16R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F16R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F16R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F16R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F17R2 register *******************/ +#define CAN_F17R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F17R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F17R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F17R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F17R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F17R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F17R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F17R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F17R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F17R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F17R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F17R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F17R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F17R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F17R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F17R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F17R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F17R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F17R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F17R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F17R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F17R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F17R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F17R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F17R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F17R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F17R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F17R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F17R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F17R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F17R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F17R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F18R2 register *******************/ +#define CAN_F18R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F18R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F18R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F18R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F18R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F18R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F18R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F18R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F18R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F18R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F18R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F18R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F18R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F18R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F18R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F18R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F18R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F18R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F18R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F18R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F18R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F18R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F18R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F18R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F18R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F18R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F18R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F18R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F18R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F18R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F18R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F18R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F19R2 register *******************/ +#define CAN_F19R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F19R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F19R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F19R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F19R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F19R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F19R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F19R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F19R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F19R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F19R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F19R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F19R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F19R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F19R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F19R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F19R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F19R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F19R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F19R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F19R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F19R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F19R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F19R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F19R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F19R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F19R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F19R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F19R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F19R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F19R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F19R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F20R2 register *******************/ +#define CAN_F20R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F20R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F20R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F20R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F20R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F20R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F20R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F20R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F20R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F20R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F20R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F20R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F20R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F20R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F20R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F20R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F20R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F20R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F20R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F20R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F20R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F20R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F20R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F20R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F20R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F20R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F20R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F20R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F20R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F20R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F20R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F20R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F21R2 register *******************/ +#define CAN_F21R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F21R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F21R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F21R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F21R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F21R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F21R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F21R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F21R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F21R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F21R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F21R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F21R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F21R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F21R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F21R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F21R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F21R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F21R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F21R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F21R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F21R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F21R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F21R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F21R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F21R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F21R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F21R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F21R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F21R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F21R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F21R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F22R2 register *******************/ +#define CAN_F22R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F22R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F22R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F22R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F22R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F22R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F22R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F22R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F22R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F22R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F22R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F22R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F22R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F22R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F22R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F22R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F22R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F22R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F22R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F22R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F22R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F22R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F22R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F22R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F22R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F22R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F22R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F22R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F22R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F22R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F22R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F22R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F23R2 register *******************/ +#define CAN_F23R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F23R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F23R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F23R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F23R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F23R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F23R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F23R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F23R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F23R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F23R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F23R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F23R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F23R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F23R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F23R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F23R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F23R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F23R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F23R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F23R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F23R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F23R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F23R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F23R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F23R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F23R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F23R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F23R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F23R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F23R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F23R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F24R2 register ******************/ +#define CAN_F24R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F24R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F24R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F24R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F24R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F24R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F24R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F24R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F24R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F24R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F24R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F24R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F24R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F24R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F24R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F24R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F24R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F24R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F24R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F24R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F24R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F24R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F24R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F24R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F24R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F24R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F24R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F24R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F24R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F24R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F24R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F24R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F25R2 register ******************/ +#define CAN_F25R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F25R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F25R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F25R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F25R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F25R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F25R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F25R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F25R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F25R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F25R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F25R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F25R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F25R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F25R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F25R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F25R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F25R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F25R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F25R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F25R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F25R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F25R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F25R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F25R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F25R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F25R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F25R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F25R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F25R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F25R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F25R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F26R2 register ******************/ +#define CAN_F26R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F26R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F26R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F26R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F26R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F26R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F26R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F26R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F26R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F26R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F26R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F26R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F26R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F26R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F26R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F26R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F26R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F26R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F26R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F26R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F26R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F26R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F26R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F26R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F26R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F26R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F26R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F26R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F26R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F26R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F26R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F26R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************* Bit definition for CAN_F27R2 register ******************/ +#define CAN_F27R2_FB0 ((uint32_t)0x00000001) /* Filter bit 0 */ +#define CAN_F27R2_FB1 ((uint32_t)0x00000002) /* Filter bit 1 */ +#define CAN_F27R2_FB2 ((uint32_t)0x00000004) /* Filter bit 2 */ +#define CAN_F27R2_FB3 ((uint32_t)0x00000008) /* Filter bit 3 */ +#define CAN_F27R2_FB4 ((uint32_t)0x00000010) /* Filter bit 4 */ +#define CAN_F27R2_FB5 ((uint32_t)0x00000020) /* Filter bit 5 */ +#define CAN_F27R2_FB6 ((uint32_t)0x00000040) /* Filter bit 6 */ +#define CAN_F27R2_FB7 ((uint32_t)0x00000080) /* Filter bit 7 */ +#define CAN_F27R2_FB8 ((uint32_t)0x00000100) /* Filter bit 8 */ +#define CAN_F27R2_FB9 ((uint32_t)0x00000200) /* Filter bit 9 */ +#define CAN_F27R2_FB10 ((uint32_t)0x00000400) /* Filter bit 10 */ +#define CAN_F27R2_FB11 ((uint32_t)0x00000800) /* Filter bit 11 */ +#define CAN_F27R2_FB12 ((uint32_t)0x00001000) /* Filter bit 12 */ +#define CAN_F27R2_FB13 ((uint32_t)0x00002000) /* Filter bit 13 */ +#define CAN_F27R2_FB14 ((uint32_t)0x00004000) /* Filter bit 14 */ +#define CAN_F27R2_FB15 ((uint32_t)0x00008000) /* Filter bit 15 */ +#define CAN_F27R2_FB16 ((uint32_t)0x00010000) /* Filter bit 16 */ +#define CAN_F27R2_FB17 ((uint32_t)0x00020000) /* Filter bit 17 */ +#define CAN_F27R2_FB18 ((uint32_t)0x00040000) /* Filter bit 18 */ +#define CAN_F27R2_FB19 ((uint32_t)0x00080000) /* Filter bit 19 */ +#define CAN_F27R2_FB20 ((uint32_t)0x00100000) /* Filter bit 20 */ +#define CAN_F27R2_FB21 ((uint32_t)0x00200000) /* Filter bit 21 */ +#define CAN_F27R2_FB22 ((uint32_t)0x00400000) /* Filter bit 22 */ +#define CAN_F27R2_FB23 ((uint32_t)0x00800000) /* Filter bit 23 */ +#define CAN_F27R2_FB24 ((uint32_t)0x01000000) /* Filter bit 24 */ +#define CAN_F27R2_FB25 ((uint32_t)0x02000000) /* Filter bit 25 */ +#define CAN_F27R2_FB26 ((uint32_t)0x04000000) /* Filter bit 26 */ +#define CAN_F27R2_FB27 ((uint32_t)0x08000000) /* Filter bit 27 */ +#define CAN_F27R2_FB28 ((uint32_t)0x10000000) /* Filter bit 28 */ +#define CAN_F27R2_FB29 ((uint32_t)0x20000000) /* Filter bit 29 */ +#define CAN_F27R2_FB30 ((uint32_t)0x40000000) /* Filter bit 30 */ +#define CAN_F27R2_FB31 ((uint32_t)0x80000000) /* Filter bit 31 */ + +/******************************************************************************/ +/* CRC Calculation Unit */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DATAR register *********************/ +#define CRC_DATAR_DR ((uint32_t)0xFFFFFFFF) /* Data register bits */ + + +/******************* Bit definition for CRC_IDATAR register ********************/ +#define CRC_IDR_IDATAR ((uint8_t)0xFF) /* General-purpose 8-bit data register bits */ + + +/******************** Bit definition for CRC_CTLR register ********************/ +#define CRC_CTLR_RESET ((uint8_t)0x01) /* RESET bit */ + +/******************************************************************************/ +/* Digital to Analog Converter */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CTLR register ********************/ +#define DAC_EN1 ((uint32_t)0x00000001) /* DAC channel1 enable */ +#define DAC_BOFF1 ((uint32_t)0x00000002) /* DAC channel1 output buffer disable */ +#define DAC_TEN1 ((uint32_t)0x00000004) /* DAC channel1 Trigger enable */ + +#define DAC_TSEL1 ((uint32_t)0x00000038) /* TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_TSEL1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define DAC_TSEL1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define DAC_TSEL1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define DAC_WAVE1 ((uint32_t)0x000000C0) /* WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_WAVE1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define DAC_WAVE1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define DAC_MAMP1 ((uint32_t)0x00000F00) /* MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_MAMP1_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define DAC_MAMP1_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define DAC_MAMP1_2 ((uint32_t)0x00000400) /* Bit 2 */ +#define DAC_MAMP1_3 ((uint32_t)0x00000800) /* Bit 3 */ + +#define DAC_DMAEN1 ((uint32_t)0x00001000) /* DAC channel1 DMA enable */ +#define DAC_EN2 ((uint32_t)0x00010000) /* DAC channel2 enable */ +#define DAC_BOFF2 ((uint32_t)0x00020000) /* DAC channel2 output buffer disable */ +#define DAC_TEN2 ((uint32_t)0x00040000) /* DAC channel2 Trigger enable */ + +#define DAC_TSEL2 ((uint32_t)0x00380000) /* TSEL2[2:0] (DAC channel2 Trigger selection) */ +#define DAC_TSEL2_0 ((uint32_t)0x00080000) /* Bit 0 */ +#define DAC_TSEL2_1 ((uint32_t)0x00100000) /* Bit 1 */ +#define DAC_TSEL2_2 ((uint32_t)0x00200000) /* Bit 2 */ + +#define DAC_WAVE2 ((uint32_t)0x00C00000) /* WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ +#define DAC_WAVE2_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define DAC_WAVE2_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define DAC_MAMP2 ((uint32_t)0x0F000000) /* MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ +#define DAC_MAMP2_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define DAC_MAMP2_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define DAC_MAMP2_2 ((uint32_t)0x04000000) /* Bit 2 */ +#define DAC_MAMP2_3 ((uint32_t)0x08000000) /* Bit 3 */ + +#define DAC_DMAEN2 ((uint32_t)0x10000000) /* DAC channel2 DMA enabled */ + +/***************** Bit definition for DAC_SWTR register ******************/ +#define DAC_SWTRIG1 ((uint8_t)0x01) /* DAC channel1 software trigger */ +#define DAC_SWTRIG2 ((uint8_t)0x02) /* DAC channel2 software trigger */ + +/***************** Bit definition for DAC_R12BDHR1 register ******************/ +#define DAC_DHR12R1 ((uint16_t)0x0FFF) /* DAC channel1 12-bit Right aligned data */ + +/***************** Bit definition for DAC_L12BDHR1 register ******************/ +#define DAC_DHR12L1 ((uint16_t)0xFFF0) /* DAC channel1 12-bit Left aligned data */ + +/****************** Bit definition for DAC_R8BDHR1 register ******************/ +#define DAC_DHR8R1 ((uint8_t)0xFF) /* DAC channel1 8-bit Right aligned data */ + +/***************** Bit definition for DAC_R12BDHR2 register ******************/ +#define DAC_DHR12R2 ((uint16_t)0x0FFF) /* DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_L12BDHR2 register ******************/ +#define DAC_DHR12L2 ((uint16_t)0xFFF0) /* DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_R8BDHR2 register ******************/ +#define DAC_DHR8R2 ((uint8_t)0xFF) /* DAC channel2 8-bit Right aligned data */ + +/***************** Bit definition for DAC_RD12BDHR register ******************/ +#define DAC_RD12BDHR_DACC1DHR ((uint32_t)0x00000FFF) /* DAC channel1 12-bit Right aligned data */ +#define DAC_RD12BDHR_DACC2DHR ((uint32_t)0x0FFF0000) /* DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_LD12BDHR register ******************/ +#define DAC_LD12BDHR_DACC1DHR ((uint32_t)0x0000FFF0) /* DAC channel1 12-bit Left aligned data */ +#define DAC_LD12BDHR_DACC2DHR ((uint32_t)0xFFF00000) /* DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_RD8BDHR register ******************/ +#define DAC_RD8BDHR_DACC1DHR ((uint16_t)0x00FF) /* DAC channel1 8-bit Right aligned data */ +#define DAC_RD8BDHR_DACC2DHR ((uint16_t)0xFF00) /* DAC channel2 8-bit Right aligned data */ + +/******************* Bit definition for DAC_DOR1 register *******************/ +#define DAC_DACC1DOR ((uint16_t)0x0FFF) /* DAC channel1 data output */ + +/******************* Bit definition for DAC_DOR2 register *******************/ +#define DAC_DACC2DOR ((uint16_t)0x0FFF) /* DAC channel2 data output */ + +/******************************************************************************/ +/* DMA Controller */ +/******************************************************************************/ + +/******************* Bit definition for DMA_INTFR register ********************/ +#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ + +#define DMA_GIF8 ((uint32_t)0x00000001) /* Channel 8 Global interrupt flag */ +#define DMA_TCIF8 ((uint32_t)0x00000002) /* Channel 8 Transfer Complete flag */ +#define DMA_HTIF8 ((uint32_t)0x00000004) /* Channel 8 Half Transfer flag */ +#define DMA_TEIF8 ((uint32_t)0x00000008) /* Channel 8 Transfer Error flag */ +#define DMA_GIF9 ((uint32_t)0x00000010) /* Channel 9 Global interrupt flag */ +#define DMA_TCIF9 ((uint32_t)0x00000020) /* Channel 9 Transfer Complete flag */ +#define DMA_HTIF9 ((uint32_t)0x00000040) /* Channel 9 Half Transfer flag */ +#define DMA_TEIF9 ((uint32_t)0x00000080) /* Channel 9 Transfer Error flag */ +#define DMA_GIF10 ((uint32_t)0x00000100) /* Channel 10 Global interrupt flag */ +#define DMA_TCIF10 ((uint32_t)0x00000200) /* Channel 10 Transfer Complete flag */ +#define DMA_HTIF10 ((uint32_t)0x00000400) /* Channel 10 Half Transfer flag */ +#define DMA_TEIF10 ((uint32_t)0x00000800) /* Channel 10 Transfer Error flag */ +#define DMA_GIF11 ((uint32_t)0x00001000) /* Channel 11 Global interrupt flag */ +#define DMA_TCIF11 ((uint32_t)0x00002000) /* Channel 11 Transfer Complete flag */ +#define DMA_HTIF11 ((uint32_t)0x00004000) /* Channel 11 Half Transfer flag */ +#define DMA_TEIF11 ((uint32_t)0x00008000) /* Channel 11 Transfer Error flag */ + +/******************* Bit definition for DMA_INTFCR register *******************/ +#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ +#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ +#define DMA_CGIF8 ((uint32_t)0x10000000) /* Channel 8 Global interrupt clear */ +#define DMA_CTCIF8 ((uint32_t)0x20000000) /* Channel 8 Transfer Complete clear */ +#define DMA_CHTIF8 ((uint32_t)0x40000000) /* Channel 8 Half Transfer clear */ +#define DMA_CTEIF8 ((uint32_t)0x80000000) /* Channel 8 Transfer Error clear */ + +/******************* Bit definition for DMA_CFGR1 register *******************/ +#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ +#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR2 register *******************/ +#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR3 register *******************/ +#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG4 register *******************/ +#define DMA_CFG4_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG4_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG4_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG4_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/****************** Bit definition for DMA_CFG5 register *******************/ +#define DMA_CFG5_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG5_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG5_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG5_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFG6 register *******************/ +#define DMA_CFG6_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG6_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG6_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG6_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG7 register *******************/ +#define DMA_CFG7_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG7_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG7_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG7_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNTR1 register ******************/ +#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR2 register ******************/ +#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR3 register ******************/ +#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR4 register ******************/ +#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR5 register ******************/ +#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR6 register ******************/ +#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR7 register ******************/ +#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR8 register ******************/ +#define DMA_CNTR8_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_PADDR1 register *******************/ +#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR2 register *******************/ +#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR3 register *******************/ +#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR4 register *******************/ +#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR5 register *******************/ +#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR6 register *******************/ +#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR7 register *******************/ +#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR8 register *******************/ +#define DMA_PADDR8_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_MADDR1 register *******************/ +#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR2 register *******************/ +#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR3 register *******************/ +#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR4 register *******************/ +#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR5 register *******************/ +#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR6 register *******************/ +#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR7 register *******************/ +#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR8 register *******************/ +#define DMA_MADDR8_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/******************************************************************************/ +/* External Interrupt/Event Controller */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_INTENR register *******************/ +#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ +#define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ +#define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ +#define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ +#define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ +#define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ +#define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ +#define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ +#define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ +#define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ +#define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */ +#define EXTI_INTENR_MR20 ((uint32_t)0x00100000) /* Interrupt Mask on line 20 */ + +/******************* Bit definition for EXTI_EVENR register *******************/ +#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ +#define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ +#define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ +#define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ +#define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ +#define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ +#define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ +#define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ +#define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ +#define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ +#define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */ +#define EXTI_EVENR_MR20 ((uint32_t)0x00100000) /* Event Mask on line 20 */ + +/****************** Bit definition for EXTI_RTENR register *******************/ +#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ +#define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ +#define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ +#define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ +#define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ +#define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ +#define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ +#define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ +#define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ +#define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ +#define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */ +#define EXTI_RTENR_TR20 ((uint32_t)0x00100000) /* Rising trigger event configuration bit of line 20 */ + +/****************** Bit definition for EXTI_FTENR register *******************/ +#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ +#define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ +#define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ +#define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ +#define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ +#define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ +#define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ +#define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ +#define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ +#define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ +#define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */ +#define EXTI_FTENR_TR20 ((uint32_t)0x00100000) /* Falling trigger event configuration bit of line 20 */ + +/****************** Bit definition for EXTI_SWIEVR register ******************/ +#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ +#define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ +#define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ +#define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ +#define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ +#define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ +#define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ +#define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ +#define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ +#define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ +#define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */ +#define EXTI_SWIEVR_SWIEVR20 ((uint32_t)0x00100000) /* Software Interrupt on line 20 */ + +/******************* Bit definition for EXTI_INTFR register ********************/ +#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ +#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ +#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ +#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ +#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ +#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ +#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ +#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ +#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ +#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ +#define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ +#define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ +#define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ +#define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ +#define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ +#define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ +#define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ +#define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ +#define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ +#define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */ +#define EXTI_INTF_INTF20 ((uint32_t)0x00100000) /* Pending bit for line 20 */ + +/******************************************************************************/ +/* FLASH and Option Bytes Registers */ +/******************************************************************************/ + + +/******************* Bit definition for FLASH_ACTLR register ******************/ + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ +#define FLASH_KEYR_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEYR_KEY2 ((uint32_t)0xCDEF89AB) + +/***************** Bit definition for FLASH_OBKEYR register ****************/ +#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ + +/****************** Bit definition for FLASH_STATR register *******************/ +#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ +#define FLASH_STATR_WRBSY ((uint8_t)0x02) +#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ +#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ +#define FLASH_STATR_EHMODS ((uint8_t)0x80) + +/******************* Bit definition for FLASH_CTLR register *******************/ +#define FLASH_CTLR_PG ((uint32_t)0x00000001) /* Programming */ +#define FLASH_CTLR_PER ((uint32_t)0x00000002) /* Sector Erase 4K */ +#define FLASH_CTLR_MER ((uint32_t)0x00000004) /* Mass Erase */ +#define FLASH_CTLR_OPTPG ((uint32_t)0x00000010) /* Option Byte Programming */ +#define FLASH_CTLR_OPTER ((uint32_t)0x00000020) /* Option Byte Erase */ +#define FLASH_CTLR_STRT ((uint32_t)0x00000040) /* Start */ +#define FLASH_CTLR_LOCK ((uint32_t)0x00000080) /* Lock */ +#define FLASH_CTLR_OPTWRE ((uint32_t)0x00000200) /* Option Bytes Write Enable */ +#define FLASH_CTLR_ERRIE ((uint32_t)0x00000400) /* Error Interrupt Enable */ +#define FLASH_CTLR_EOPIE ((uint32_t)0x00001000) /* End of operation interrupt enable */ +#define FLASH_CTLR_FAST_LOCK ((uint32_t)0x00008000) /* Fast Lock */ +#define FLASH_CTLR_PAGE_PG ((uint32_t)0x00010000) /* Page Programming 256Byte */ +#define FLASH_CTLR_PAGE_ER ((uint32_t)0x00020000) /* Page Erase 256Byte */ +#define FLASH_CTLR_PAGE_BER32 ((uint32_t)0x00040000) /* Block Erase 32K */ +#define FLASH_CTLR_PAGE_BER64 ((uint32_t)0x00080000) /* Block Erase 64K */ +#define FLASH_CTLR_PG_STRT ((uint32_t)0x00200000) /* Page Programming Start */ +#define FLASH_CTLR_RSENACT ((uint32_t)0x00400000) +#define FLASH_CTLR_EHMOD ((uint32_t)0x01000000) +#define FLASH_CTLR_SCKMOD ((uint32_t)0x02000000) + +/******************* Bit definition for FLASH_ADDR register *******************/ +#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ + +#define FLASH_OBR_USER ((uint16_t)0x03FC) /* User Option Bytes */ +#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ +#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */ +#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */ +#define FLASH_OBR_RAM_CODE_MOD ((uint16_t)0x0300) +#define FLASH_OBR_RAM_CODE_MOD_BIT1 ((uint16_t)0x0100) +#define FLASH_OBR_RAM_CODE_MOD_BIT2 ((uint16_t)0x0200) + +/****************** Bit definition for FLASH_WPR register ******************/ +#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ + +/****************** Bit definition for FLASH_MODEKEYR register ******************/ +#define FLASH_MODEKEYR_KEY1 ((uint32_t)0x45670123) +#define FLASH_MODEKEYR_KEY2 ((uint32_t)0xCDEF89AB) + +/****************** Bit definition for FLASH_RDPR register *******************/ +#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ +#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRPR0 register ******************/ +#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR1 register ******************/ +#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR2 register ******************/ +#define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR3 register ******************/ +#define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/******************************************************************************/ +/* General Purpose and Alternate Function I/O */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CFGLR register *******************/ +#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_CFGHR register *******************/ +#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_INDR register *******************/ +#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ +#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ +#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ +#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ +#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ +#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ +#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ +#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ +#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ +#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ +#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ +#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ +#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ +#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ +#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ +#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ + +/******************* Bit definition for GPIO_OUTDR register *******************/ +#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ +#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ +#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ +#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ +#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ +#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ +#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ +#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ +#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ +#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ +#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ +#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ +#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ +#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ +#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ +#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSHR register *******************/ +#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ +#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ +#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ +#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ +#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ +#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ +#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ +#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ +#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ + +#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ +#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ +#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ +#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ +#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ +#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ +#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ +#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ +#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BCR register *******************/ +#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ +#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ +#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ +#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ +#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ +#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ +#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ +#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ +#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ +#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ +#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ +#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ +#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ +#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ +#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ +#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ +#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ +#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ +#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ +#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ +#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ +#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ +#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ +#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ + + +/****************** Bit definition for AFIO_ECR register *******************/ +#define AFIO_ECR_PIN ((uint8_t)0x0F) /* PIN[3:0] bits (Pin selection) */ +#define AFIO_ECR_PIN_0 ((uint8_t)0x01) /* Bit 0 */ +#define AFIO_ECR_PIN_1 ((uint8_t)0x02) /* Bit 1 */ +#define AFIO_ECR_PIN_2 ((uint8_t)0x04) /* Bit 2 */ +#define AFIO_ECR_PIN_3 ((uint8_t)0x08) /* Bit 3 */ + +#define AFIO_ECR_PIN_PX0 ((uint8_t)0x00) /* Pin 0 selected */ +#define AFIO_ECR_PIN_PX1 ((uint8_t)0x01) /* Pin 1 selected */ +#define AFIO_ECR_PIN_PX2 ((uint8_t)0x02) /* Pin 2 selected */ +#define AFIO_ECR_PIN_PX3 ((uint8_t)0x03) /* Pin 3 selected */ +#define AFIO_ECR_PIN_PX4 ((uint8_t)0x04) /* Pin 4 selected */ +#define AFIO_ECR_PIN_PX5 ((uint8_t)0x05) /* Pin 5 selected */ +#define AFIO_ECR_PIN_PX6 ((uint8_t)0x06) /* Pin 6 selected */ +#define AFIO_ECR_PIN_PX7 ((uint8_t)0x07) /* Pin 7 selected */ +#define AFIO_ECR_PIN_PX8 ((uint8_t)0x08) /* Pin 8 selected */ +#define AFIO_ECR_PIN_PX9 ((uint8_t)0x09) /* Pin 9 selected */ +#define AFIO_ECR_PIN_PX10 ((uint8_t)0x0A) /* Pin 10 selected */ +#define AFIO_ECR_PIN_PX11 ((uint8_t)0x0B) /* Pin 11 selected */ +#define AFIO_ECR_PIN_PX12 ((uint8_t)0x0C) /* Pin 12 selected */ +#define AFIO_ECR_PIN_PX13 ((uint8_t)0x0D) /* Pin 13 selected */ +#define AFIO_ECR_PIN_PX14 ((uint8_t)0x0E) /* Pin 14 selected */ +#define AFIO_ECR_PIN_PX15 ((uint8_t)0x0F) /* Pin 15 selected */ + +#define AFIO_ECR_PORT ((uint8_t)0x70) /* PORT[2:0] bits (Port selection) */ +#define AFIO_ECR_PORT_0 ((uint8_t)0x10) /* Bit 0 */ +#define AFIO_ECR_PORT_1 ((uint8_t)0x20) /* Bit 1 */ +#define AFIO_ECR_PORT_2 ((uint8_t)0x40) /* Bit 2 */ + +#define AFIO_ECR_PORT_PA ((uint8_t)0x00) /* Port A selected */ +#define AFIO_ECR_PORT_PB ((uint8_t)0x10) /* Port B selected */ +#define AFIO_ECR_PORT_PC ((uint8_t)0x20) /* Port C selected */ +#define AFIO_ECR_PORT_PD ((uint8_t)0x30) /* Port D selected */ +#define AFIO_ECR_PORT_PE ((uint8_t)0x40) /* Port E selected */ + +#define AFIO_ECR_EVOE ((uint8_t)0x80) /* Event Output Enable */ + +/****************** Bit definition for AFIO_PCFR1register *******************/ +#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */ +#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */ +#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000004) /* USART1 remapping */ +#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000008) /* USART2 remapping */ + +#define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define AFIO_PCFR1_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP1 ((uint32_t)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP2 ((uint32_t)0x00000020) +#define AFIO_PCFR1_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define AFIO_PCFR1_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define AFIO_PCFR1_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define AFIO_PCFR1_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_PCFR1_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_PCFR1_TIM4_REMAP ((uint32_t)0x00001000) /* TIM4_REMAP bit (TIM4 remapping) */ + +#define AFIO_PCFR1_CAN_REMAP ((uint32_t)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_PCFR1_CAN_REMAP_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define AFIO_PCFR1_CAN_REMAP_1 ((uint32_t)0x00004000) /* Bit 1 */ + +#define AFIO_PCFR1_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_PCFR1_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_PCFR1_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_PCFR1_PD01_REMAP ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCFR1_TIM5CH4_IREMAP ((uint32_t)0x00010000) /* TIM5 Channel4 Internal Remap */ +#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_PCFR1_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */ +#define AFIO_PCFR1_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */ +#define AFIO_PCFR1_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */ + +#define AFIO_PCFR1_ETH_REMAP ((uint32_t)0x00200000) + +#define AFIO_PCFR1_CAN2_REMAP ((uint32_t)0x00400000) + +#define AFIO_PCFR1_MII_RMII_REMAP ((uint32_t)0x00800000) + +#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */ +#define AFIO_PCFR1_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */ +#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */ +#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */ + +#define AFIO_PCFR1_SPI3_REMAP ((uint32_t)0x10000000) + +#define AFIO_PCFR1_TIM2ITR1_REMAP ((uint32_t)0x20000000) + +#define AFIO_PCFR1_PTP_PPS_REMAP ((uint32_t)0x40000000) + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /* EXTI 3 configuration */ + +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /* PE[0] pin */ + +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /* PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /* PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /* PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /* PE[1] pin */ + +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /* PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /* PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /* PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /* PE[2] pin */ + +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /* PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /* PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /* PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /* PE[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /* EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /* EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /* EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /* EXTI 7 configuration */ + +#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /* PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /* PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /* PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /* PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /* PE[4] pin */ + +#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /* PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /* PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /* PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /* PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /* PE[5] pin */ + +#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /* PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /* PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /* PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /* PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /* PE[6] pin */ + +#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /* PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /* PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /* PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /* PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /* PE[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /* EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /* EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /* EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /* EXTI 11 configuration */ + +#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /* PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /* PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /* PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /* PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /* PE[8] pin */ + +#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /* PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /* PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /* PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /* PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /* PE[9] pin */ + +#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /* PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /* PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /* PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /* PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /* PE[10] pin */ + +#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /* PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /* PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /* PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /* PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /* PE[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /* EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /* EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /* EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /* EXTI 15 configuration */ + +#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /* PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /* PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /* PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /* PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /* PE[12] pin */ + +#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /* PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /* PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /* PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /* PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /* PE[13] pin */ + +#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /* PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /* PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /* PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /* PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /* PE[14] pin *// + +#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /* PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /* PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /* PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /* PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /* PE[15] pin */ + +/****************** Bit definition for AFIO_PCFR2register *******************/ +#define AFIO_PCFR2_TIM8_REMAP ((uint32_t)0x00000004) + +#define AFIO_PCFR2_TIM9_REMAP ((uint32_t)0x00000018) +#define AFIO_PCFR2_TIM9_REMAP_0 ((uint32_t)0x00000008) +#define AFIO_PCFR2_TIM9_REMAP_1 ((uint32_t)0x00000010) + +#define AFIO_PCFR2_TIM9_REMAP_NOREMAP ((uint32_t)0x00000000) +#define AFIO_PCFR2_TIM9_REMAP_PARTIALREMAP ((uint32_t)0x00000008) +#define AFIO_PCFR2_TIM9_REMAP_FULLREMAP ((uint32_t)0x00000010) + +#define AFIO_PCFR2_TIM10_REMAP ((uint32_t)0x00000060) +#define AFIO_PCFR2_TIM10_REMAP_0 ((uint32_t)0x00000020) +#define AFIO_PCFR2_TIM10_REMAP_1 ((uint32_t)0x00000040) + +#define AFIO_PCFR2_TIM10_REMAP_NOREMAP ((uint32_t)0x00000000) +#define AFIO_PCFR2_TIM10_REMAP_PARTIALREMAP ((uint32_t)0x00000020) +#define AFIO_PCFR2_TIM10_REMAP_FULLREMAP ((uint32_t)0x00000040) + +#define AFIO_PCFR2_FSMC_NADV_REMAP ((uint32_t)0x00000400) + + +#define AFIO_PCFR2_USART4_REMAP ((uint32_t)0x00030000) +#define AFIO_PCFR2_USART4_REMAP_0 ((uint32_t)0x00010000) +#define AFIO_PCFR2_USART4_REMAP_1 ((uint32_t)0x00020000) + +#define AFIO_PCFR2_USART4_REMAP_NOREMAP ((uint32_t)0x00000000) +#define AFIO_PCFR2_USART4_REMAP_PARTIALREMAP ((uint32_t)0x00010000) +#define AFIO_PCFR2_USART4_REMAP_FULLREMAP ((uint32_t)0x00020000) + +#define AFIO_PCFR2_USART5_REMAP ((uint32_t)0x000C0000) +#define AFIO_PCFR2_USART5_REMAP_0 ((uint32_t)0x00040000) +#define AFIO_PCFR2_USART5_REMAP_1 ((uint32_t)0x00080000) + +#define AFIO_PCFR2_USART5_REMAP_NOREMAP ((uint32_t)0x00000000) +#define AFIO_PCFR2_USART5_REMAP_PARTIALREMAP ((uint32_t)0x00040000) +#define AFIO_PCFR2_USART5_REMAP_FULLREMAP ((uint32_t)0x00080000) + +#define AFIO_PCFR2_USART6_REMAP ((uint32_t)0x00300000) +#define AFIO_PCFR2_USART6_REMAP_0 ((uint32_t)0x00100000) +#define AFIO_PCFR2_USART6_REMAP_1 ((uint32_t)0x00200000) + +#define AFIO_PCFR2_USART6_REMAP_NOREMAP ((uint32_t)0x00000000) +#define AFIO_PCFR2_USART6_REMAP_PARTIALREMAP ((uint32_t)0x00100000) +#define AFIO_PCFR2_USART6_REMAP_FULLREMAP ((uint32_t)0x00200000) + +#define AFIO_PCFR2_USART7_REMAP ((uint32_t)0x00C00000) +#define AFIO_PCFR2_USART7_REMAP_0 ((uint32_t)0x00400000) +#define AFIO_PCFR2_USART7_REMAP_1 ((uint32_t)0x00800000) + +#define AFIO_PCFR2_USART7_REMAP_NOREMAP ((uint32_t)0x00000000) +#define AFIO_PCFR2_USART7_REMAP_PARTIALREMAP ((uint32_t)0x00400000) +#define AFIO_PCFR2_USART7_REMAP_FULLREMAP ((uint32_t)0x00800000) + +#define AFIO_PCFR2_USART8_REMAP ((uint32_t)0x03000000) +#define AFIO_PCFR2_USART8_REMAP_0 ((uint32_t)0x01000000) +#define AFIO_PCFR2_USART8_REMAP_1 ((uint32_t)0x02000000) + +#define AFIO_PCFR2_USART8_REMAP_NOREMAP ((uint32_t)0x00000000) +#define AFIO_PCFR2_USART8_REMAP_PARTIALREMAP ((uint32_t)0x01000000) +#define AFIO_PCFR2_USART8_REMAP_FULLREMAP ((uint32_t)0x02000000) + +#define AFIO_PCFR2_USART1_REMAP ((uint32_t)0x04000000) + +/******************************************************************************/ +/* Independent WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_CTLR register ********************/ +#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PSCR register ********************/ +#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ +#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ +#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ + +/******************* Bit definition for IWDG_RLDR register *******************/ +#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ + +/******************* Bit definition for IWDG_STATR register ********************/ +#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ +#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ + +/******************************************************************************/ +/* Inter-integrated Circuit Interface */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CTLR1 register ********************/ +#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ +#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ +#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ +#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ +#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ +#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ +#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ +#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ +#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ +#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ +#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ +#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ + +/******************* Bit definition for I2C_CTLR2 register ********************/ +#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ + +#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ +#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ +#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ +#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ + +/******************* Bit definition for I2C_OADDR1 register *******************/ +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) +#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ +#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ + +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ +#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ +#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ +#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ +#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ + +#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OADDR2 register *******************/ +#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ +#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ + +/******************** Bit definition for I2C_DATAR register ********************/ +#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ + +/******************* Bit definition for I2C_STAR1 register ********************/ +#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ +#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ +#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ +#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ +#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ +#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ +#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ +#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ +#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ + +/******************* Bit definition for I2C_STAR2 register ********************/ +#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ +#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ +#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ +#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ +#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ +#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ +#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ + +/******************* Bit definition for I2C_CKCFGR register ********************/ +#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ + +/****************** Bit definition for I2C_RTR register *******************/ +#define I2C_RTR_TRISE ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */ + + +/******************************************************************************/ +/* Power Control */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CTLR register ********************/ +#define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */ +#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ +#define PWR_CTLR_CWUF ((uint16_t)0x0004) /* Clear Wakeup Flag */ +#define PWR_CTLR_CSBF ((uint16_t)0x0008) /* Clear Standby Flag */ +#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ + +#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ +#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ + +#define PWR_CTLR_PLS_MODE0 ((uint16_t)0x0000) +#define PWR_CTLR_PLS_MODE1 ((uint16_t)0x0020) +#define PWR_CTLR_PLS_MODE2 ((uint16_t)0x0040) +#define PWR_CTLR_PLS_MODE3 ((uint16_t)0x0060) +#define PWR_CTLR_PLS_MODE4 ((uint16_t)0x0080) +#define PWR_CTLR_PLS_MODE5 ((uint16_t)0x00A0) +#define PWR_CTLR_PLS_MODE6 ((uint16_t)0x00C0) +#define PWR_CTLR_PLS_MODE7 ((uint16_t)0x00E0) + +#define PWR_CTLR_PLS_2V2 PWR_CTLR_PLS_MODE0 +#define PWR_CTLR_PLS_2V3 PWR_CTLR_PLS_MODE1 +#define PWR_CTLR_PLS_2V4 PWR_CTLR_PLS_MODE2 +#define PWR_CTLR_PLS_2V5 PWR_CTLR_PLS_MODE3 +#define PWR_CTLR_PLS_2V6 PWR_CTLR_PLS_MODE4 +#define PWR_CTLR_PLS_2V7 PWR_CTLR_PLS_MODE5 +#define PWR_CTLR_PLS_2V8 PWR_CTLR_PLS_MODE6 +#define PWR_CTLR_PLS_2V9 PWR_CTLR_PLS_MODE7 + +#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ + +#define PWR_CTLR_R2KSTY ((uint32_t)0x10000) +#define PWR_CTLR_R30KSTY ((uint32_t)0x20000) +#define PWR_CTLR_R2KVBAT ((uint32_t)0x40000) +#define PWR_CTLR_R30KVBAT ((uint32_t)0x80000) +#define PWR_CTLR_RAMLV ((uint32_t)0x100000) + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */ + + + +/******************************************************************************/ +/* Reset and Clock Control */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTLR register ********************/ +#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ +#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ +#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ +#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ +#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ +#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ +#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ +#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ +#define RCC_PLL2ON ((uint32_t)0x04000000) +#define RCC_PLL2RDY ((uint32_t)0x08000000) +#define RCC_PLL3ON ((uint32_t)0x10000000) +#define RCC_PLL3RDY ((uint32_t)0x20000000) + +/******************* Bit definition for RCC_CFGR0 register *******************/ +#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ +#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ +#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ +#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ + +#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ +#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ +#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ + +#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ +#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ +#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ + +#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ +#define RCC_HPRE_DIV2 ((uint32_t)0x00000080) /* SYSCLK divided by 2 */ +#define RCC_HPRE_DIV4 ((uint32_t)0x00000090) /* SYSCLK divided by 4 */ +#define RCC_HPRE_DIV8 ((uint32_t)0x000000A0) /* SYSCLK divided by 8 */ +#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_HPRE_DIV64 ((uint32_t)0x000000C0) /* SYSCLK divided by 64 */ +#define RCC_HPRE_DIV128 ((uint32_t)0x000000D0) /* SYSCLK divided by 128 */ +#define RCC_HPRE_DIV256 ((uint32_t)0x000000E0) /* SYSCLK divided by 256 */ +#define RCC_HPRE_DIV512 ((uint32_t)0x000000F0) /* SYSCLK divided by 512 */ + +#define RCC_PPRE1 ((uint32_t)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_PPRE1_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_PPRE1_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define RCC_PPRE1_2 ((uint32_t)0x00000400) /* Bit 2 */ + +#define RCC_PPRE1_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ +#define RCC_PPRE1_DIV2 ((uint32_t)0x00000400) /* HCLK divided by 2 */ +#define RCC_PPRE1_DIV4 ((uint32_t)0x00000500) /* HCLK divided by 4 */ +#define RCC_PPRE1_DIV8 ((uint32_t)0x00000600) /* HCLK divided by 8 */ +#define RCC_PPRE1_DIV16 ((uint32_t)0x00000700) /* HCLK divided by 16 */ + +#define RCC_PPRE2 ((uint32_t)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_PPRE2_0 ((uint32_t)0x00000800) /* Bit 0 */ +#define RCC_PPRE2_1 ((uint32_t)0x00001000) /* Bit 1 */ +#define RCC_PPRE2_2 ((uint32_t)0x00002000) /* Bit 2 */ + +#define RCC_PPRE2_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ +#define RCC_PPRE2_DIV2 ((uint32_t)0x00002000) /* HCLK divided by 2 */ +#define RCC_PPRE2_DIV4 ((uint32_t)0x00002800) /* HCLK divided by 4 */ +#define RCC_PPRE2_DIV8 ((uint32_t)0x00003000) /* HCLK divided by 8 */ +#define RCC_PPRE2_DIV16 ((uint32_t)0x00003800) /* HCLK divided by 16 */ + +#define RCC_ADCPRE ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_ADCPRE_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define RCC_ADCPRE_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* PCLK2 divided by 2 */ +#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* PCLK2 divided by 4 */ +#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* PCLK2 divided by 6 */ +#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* PCLK2 divided by 8 */ + +#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ + +#define RCC_PLLXTPRE ((uint32_t)0x00020000) /* HSE divider for PLL entry */ + +#define RCC_PLLMULL ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_PLLMULL_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define RCC_PLLMULL_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define RCC_PLLMULL_2 ((uint32_t)0x00100000) /* Bit 2 */ +#define RCC_PLLMULL_3 ((uint32_t)0x00200000) /* Bit 3 */ + +#define RCC_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /* HSI clock divided by 2 selected as PLL entry clock source */ +#define RCC_PLLSRC_HSE ((uint32_t)0x00010000) /* HSE clock selected as PLL entry clock source */ + +#define RCC_PLLXTPRE_HSE ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */ +#define RCC_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */ + +/* CH32V303x */ +#define RCC_PLLMULL2 ((uint32_t)0x00000000) /* PLL input clock*2 */ +#define RCC_PLLMULL3 ((uint32_t)0x00040000) /* PLL input clock*3 */ +#define RCC_PLLMULL4 ((uint32_t)0x00080000) /* PLL input clock*4 */ +#define RCC_PLLMULL5 ((uint32_t)0x000C0000) /* PLL input clock*5 */ +#define RCC_PLLMULL6 ((uint32_t)0x00100000) /* PLL input clock*6 */ +#define RCC_PLLMULL7 ((uint32_t)0x00140000) /* PLL input clock*7 */ +#define RCC_PLLMULL8 ((uint32_t)0x00180000) /* PLL input clock*8 */ +#define RCC_PLLMULL9 ((uint32_t)0x001C0000) /* PLL input clock*9 */ +#define RCC_PLLMULL10 ((uint32_t)0x00200000) /* PLL input clock10 */ +#define RCC_PLLMULL11 ((uint32_t)0x00240000) /* PLL input clock*11 */ +#define RCC_PLLMULL12 ((uint32_t)0x00280000) /* PLL input clock*12 */ +#define RCC_PLLMULL13 ((uint32_t)0x002C0000) /* PLL input clock*13 */ +#define RCC_PLLMULL14 ((uint32_t)0x00300000) /* PLL input clock*14 */ +#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */ +#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */ +#define RCC_PLLMULL18 ((uint32_t)0x003C0000) /* PLL input clock*18 */ +/* CH32V307x-CH32V305x */ +#define RCC_PLLMULL18_EXTEN ((uint32_t)0x00000000) /* PLL input clock*18 */ +#define RCC_PLLMULL3_EXTEN ((uint32_t)0x00040000) /* PLL input clock*3 */ +#define RCC_PLLMULL4_EXTEN ((uint32_t)0x00080000) /* PLL input clock*4 */ +#define RCC_PLLMULL5_EXTEN ((uint32_t)0x000C0000) /* PLL input clock*5 */ +#define RCC_PLLMULL6_EXTEN ((uint32_t)0x00100000) /* PLL input clock*6 */ +#define RCC_PLLMULL7_EXTEN ((uint32_t)0x00140000) /* PLL input clock*7 */ +#define RCC_PLLMULL8_EXTEN ((uint32_t)0x00180000) /* PLL input clock*8 */ +#define RCC_PLLMULL9_EXTEN ((uint32_t)0x001C0000) /* PLL input clock*9 */ +#define RCC_PLLMULL10_EXTEN ((uint32_t)0x00200000) /* PLL input clock10 */ +#define RCC_PLLMULL11_EXTEN ((uint32_t)0x00240000) /* PLL input clock*11 */ +#define RCC_PLLMULL12_EXTEN ((uint32_t)0x00280000) /* PLL input clock*12 */ +#define RCC_PLLMULL13_EXTEN ((uint32_t)0x002C0000) /* PLL input clock*13 */ +#define RCC_PLLMULL14_EXTEN ((uint32_t)0x00300000) /* PLL input clock*14 */ +#define RCC_PLLMULL6_5_EXTEN ((uint32_t)0x00340000) /* PLL input clock*6.5 */ +#define RCC_PLLMULL15_EXTEN ((uint32_t)0x00380000) /* PLL input clock*15 */ +#define RCC_PLLMULL16_EXTEN ((uint32_t)0x003C0000) /* PLL input clock*16 */ + +#define RCC_USBPRE ((uint32_t)0x00400000) /* USB Device prescaler */ + +#define RCC_CFGR0_MCO ((uint32_t)0x0F000000) /* MCO[3:0] bits (Microcontroller Clock Output) */ +#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ +#define RCC_MCO_3 ((uint32_t)0x08000000) /* Bit 3 */ + +#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ +#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ +#define RCC_CFGR0_MCO_PLL2 ((uint32_t)0x08000000) +#define RCC_CFGR0_MCO_PLL3D2 ((uint32_t)0x09000000) /* PLL3 clock divided by 2 selected as MCO source */ +#define RCC_CFGR0_MCO_XT1 ((uint32_t)0x0A000000) +#define RCC_CFGR0_MCO_PLL3 ((uint32_t)0x0B000000) + +#define RCC_CFGR0_ETHPRE ((uint32_t)0x10000000) +#define RCC_CFGR0_ADCDUTY ((uint32_t)0x80000000) +#define RCC_CFGR0_ADCDUTY_SEL ((uint32_t)0x40000000) + +/******************* Bit definition for RCC_INTR register ********************/ +#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ +#define RCC_LSERDYF ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */ +#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ +#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ +#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ +#define RCC_PLL2RDYF ((uint32_t)0x00000020) +#define RCC_PLL3RDYF ((uint32_t)0x00000040) +#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ +#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ +#define RCC_LSERDYIE ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */ +#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ +#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ +#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ +#define RCC_PLL2RDYIE ((uint32_t)0x00002000) +#define RCC_PLL3RDYIE ((uint32_t)0x00004000) +#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ +#define RCC_LSERDYC ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */ +#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ +#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ +#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ +#define RCC_PLL2RDYC ((uint32_t)0x00200000) +#define RCC_PLL3RDYC ((uint32_t)0x00400000) +#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ + +/***************** Bit definition for RCC_APB2PRSTR register *****************/ +#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ +#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ +#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ +#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ +#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ +#define RCC_IOPERST ((uint32_t)0x00000040) +#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ +#define RCC_ADC2RST ((uint32_t)0x00000400) /* ADC 2 interface reset */ +#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ +#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ +#define RCC_TIM8RST ((uint32_t)0x00002000) +#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ +#define RCC_TIM9RST ((uint32_t)0x00080000) +#define RCC_TIM10RST ((uint32_t)0x00100000) + +/***************** Bit definition for RCC_APB1PRSTR register *****************/ +#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ +#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ +#define RCC_TIM4RST ((uint32_t)0x00000004) /* Timer 4 reset */ +#define RCC_TIM5RST ((uint32_t)0x00000008) /* Timer 5 reset */ +#define RCC_TIM6RST ((uint32_t)0x00000010) /* Timer 6 reset */ +#define RCC_TIM7RST ((uint32_t)0x00000020) /* Timer 7 reset */ +#define RCC_USART6RST ((uint32_t)0x00000040) /* USART 2 reset */ +#define RCC_USART7RST ((uint32_t)0x00000080) /* USART 2 reset */ +#define RCC_USART8RST ((uint32_t)0x00000100) /* USART 2 reset */ +#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ +#define RCC_SPI2RST ((uint32_t)0x00004000) /* SPI 2 reset */ +#define RCC_SPI3RST ((uint32_t)0x00008000) /* SPI 3 reset */ +#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ +#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */ +#define RCC_USART4RST ((uint32_t)0x00080000) /* USART 4 reset */ +#define RCC_USART5RST ((uint32_t)0x00100000) /* USART 5 reset */ +#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ +#define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 2 reset */ +#define RCC_USBRST ((uint32_t)0x00800000) /* USB Device reset */ +#define RCC_CAN1RST ((uint32_t)0x02000000) /* CAN1 reset */ +#define RCC_CAN2RST ((uint32_t)0x04000000) /* CAN2 reset */ +#define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */ +#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ +#define RCC_DACRST ((uint32_t)0x20000000) /* DAC reset */ + +/****************** Bit definition for RCC_AHBPCENR register ******************/ +#define RCC_DMA1EN ((uint16_t)0x0001) /* DMA1 clock enable */ +#define RCC_DMA2EN ((uint16_t)0x0002) +#define RCC_SRAMEN ((uint16_t)0x0004) /* SRAM interface clock enable */ +#define RCC_CRCEN ((uint16_t)0x0040) /* CRC clock enable */ +#define RCC_FSMCEN ((uint16_t)0x0100) +#define RCC_RNGEN ((uint16_t)0x0200) +#define RCC_SDIOEN ((uint16_t)0x0400) +#define RCC_USBHSEN ((uint16_t)0x0800) +#define RCC_OTGFSEN ((uint16_t)0x1000) +#define RCC_DVPEN ((uint16_t)0x2000) +#define RCC_ETHMACEN ((uint16_t)0x4000) +#define RCC_ETHMACTXEN ((uint16_t)0x8000) +#define RCC_ETHMACRXEN ((uint32_t)0x10000) +#define RCC_BLEC ((uint32_t)0x10000) +#define RCC_BLES ((uint32_t)0x20000) + +/****************** Bit definition for RCC_APB2PCENR register *****************/ +#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ +#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ +#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ +#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ +#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ +#define RCC_IOPEEN ((uint32_t)0x00000040) +#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ +#define RCC_ADC2EN ((uint32_t)0x00000400) /* ADC 2 interface clock enable */ +#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ +#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ +#define RCC_TIM8EN ((uint32_t)0x00002000) +#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ +#define RCC_TIM9EN ((uint32_t)0x00080000) +#define RCC_TIM10EN ((uint32_t)0x00100000) + +/***************** Bit definition for RCC_APB1PCENR register ******************/ +#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ +#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ +#define RCC_TIM4EN ((uint32_t)0x00000004) +#define RCC_TIM5EN ((uint32_t)0x00000008) +#define RCC_TIM6EN ((uint32_t)0x00000010) +#define RCC_TIM7EN ((uint32_t)0x00000020) +#define RCC_USART6EN ((uint32_t)0x00000040) +#define RCC_USART7EN ((uint32_t)0x00000080) +#define RCC_USART8EN ((uint32_t)0x00000100) +#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ +#define RCC_SPI2EN ((uint32_t)0x00004000) +#define RCC_SPI3EN ((uint32_t)0x00008000) +#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ +#define RCC_USART3EN ((uint32_t)0x00040000) +#define RCC_USART4EN ((uint32_t)0x00080000) +#define RCC_USART5EN ((uint32_t)0x00100000) +#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ +#define RCC_I2C2EN ((uint32_t)0x00400000) +#define RCC_USBEN ((uint32_t)0x00800000) /* USB Device clock enable */ +#define RCC_CAN1EN ((uint32_t)0x02000000) +#define RCC_CAN2EN ((uint32_t)0x04000000) +#define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */ +#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ +#define RCC_DACEN ((uint32_t)0x20000000) + +/******************* Bit definition for RCC_BDCTLR register *******************/ +#define RCC_LSEON ((uint32_t)0x00000001) /* External Low Speed oscillator enable */ +#define RCC_LSERDY ((uint32_t)0x00000002) /* External Low Speed oscillator Ready */ +#define RCC_LSEBYP ((uint32_t)0x00000004) /* External Low Speed oscillator Bypass */ + +#define RCC_RTCSEL ((uint32_t)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_RTCSEL_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_RTCSEL_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define RCC_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_RTCSEL_LSE ((uint32_t)0x00000100) /* LSE oscillator clock used as RTC clock */ +#define RCC_RTCSEL_LSI ((uint32_t)0x00000200) /* LSI oscillator clock used as RTC clock */ +#define RCC_RTCSEL_HSE ((uint32_t)0x00000300) + +#define RCC_RTCEN ((uint32_t)0x00008000) /* RTC clock enable */ +#define RCC_BDRST ((uint32_t)0x00010000) /* Backup domain software reset */ + +/******************* Bit definition for RCC_RSTSCKR register ********************/ +#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ +#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ +#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ +#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ +#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ +#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ +#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ +#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ +#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ + +/******************* Bit definition for RCC_AHBRSTR register ********************/ +#define RCC_OTGFSRST ((uint32_t)0x00001000) +#define RCC_DVPRST ((uint32_t)0x00002000) +#define RCC_ETHMACRST ((uint32_t)0x00004000) + +/******************* Bit definition for RCC_CFGR2 register ********************/ +#define RCC_PREDIV1 ((uint32_t)0x0000000F) +#define RCC_PREDIV1_0 ((uint32_t)0x00000001) +#define RCC_PREDIV1_1 ((uint32_t)0x00000002) +#define RCC_PREDIV1_2 ((uint32_t)0x00000004) +#define RCC_PREDIV1_3 ((uint32_t)0x00000008) + +#define RCC_PREDIV2 ((uint32_t)0x000000F0) +#define RCC_PREDIV2_0 ((uint32_t)0x00000010) +#define RCC_PREDIV2_1 ((uint32_t)0x00000020) +#define RCC_PREDIV2_2 ((uint32_t)0x00000040) +#define RCC_PREDIV2_3 ((uint32_t)0x00000080) + +#define RCC_PLL2MUL ((uint32_t)0x00000F00) +#define RCC_PLL2MUL_0 ((uint32_t)0x00000100) +#define RCC_PLL2MUL_1 ((uint32_t)0x00000200) +#define RCC_PLL2MUL_2 ((uint32_t)0x00000400) +#define RCC_PLL2MUL_3 ((uint32_t)0x00000800) + +#define RCC_PLL3MUL ((uint32_t)0x0000F000) +#define RCC_PLL3MUL_0 ((uint32_t)0x00001000) +#define RCC_PLL3MUL_1 ((uint32_t)0x00002000) +#define RCC_PLL3MUL_2 ((uint32_t)0x00004000) +#define RCC_PLL3MUL_3 ((uint32_t)0x00008000) + +#define RCC_PREDIV1SRC ((uint32_t)0x00010000) +#define RCC_I2S2SRC ((uint32_t)0x00020000) +#define RCC_I2S3SRC ((uint32_t)0x00040000) +#define RCC_RNGSRC ((uint32_t)0x00080000) + +#define RCC_ETH1GSRC ((uint32_t)0x00300000) +#define RCC_ETH1GSRC_0 ((uint32_t)0x00100000) +#define RCC_ETH1GSRC_1 ((uint32_t)0x00200000) + +#define RCC_ETH1GEN ((uint32_t)0x00400000) + +#define RCC_USBHSDIV ((uint32_t)0x07000000) +#define RCC_USBHSDIV_0 ((uint32_t)0x01000000) +#define RCC_USBHSDIV_1 ((uint32_t)0x02000000) +#define RCC_USBHSDIV_2 ((uint32_t)0x04000000) + +#define RCC_USBHSPLLSRC ((uint32_t)0x08000000) + +#define RCC_USBHSCLK ((uint32_t)0x30000000) +#define RCC_USBHSCLK_0 ((uint32_t)0x10000000) +#define RCC_USBHSCLK_1 ((uint32_t)0x20000000) + +#define RCC_USBHSPLL ((uint32_t)0x40000000) +#define RCC_USBFSSRC ((uint32_t)0x80000000) + +/******************* Bit definition for RCC_HSE_CAL_CTRL register ********************/ +#define RCC_HSEITRIM ((uint32_t)0x01000000) +#define RCC_HSEFAULT ((uint32_t)0x08000000) + +#define RCC_HSEC ((uint32_t)0x70000000) +#define RCC_HSEC_0 ((uint32_t)0x10000000) +#define RCC_HSEC_1 ((uint32_t)0x20000000) +#define RCC_HSEC_2 ((uint32_t)0x40000000) + +/******************* Bit definition for RCC_LSI32K_TUNE register ********************/ +#define RCC_HTUNE ((uint16_t)0x1000) +#define RCC_LTUNE ((uint16_t)0x0011) + +/******************* Bit definition for RCC_LSI32K_CAL_CFG register ********************/ +#define RCC_CNTVLU ((uint8_t)0x0F) +#define RCC_CNTVLU_0 ((uint8_t)0x01) +#define RCC_CNTVLU_1 ((uint8_t)0x02) +#define RCC_CNTVLU_2 ((uint8_t)0x04) +#define RCC_CNTVLU_3 ((uint8_t)0x08) +#define RCC_HALTMD ((uint8_t)0x10) +#define RCC_WKUPEN ((uint8_t)0x20) +#define RCC_LPEN ((uint8_t)0x40) + +/******************* Bit definition for RCC_LSI32K_CAL_STATR register ********************/ +#define RCC_CNTOV ((uint16_t)0x4000) +#define RCC_IFEND ((uint16_t)0x8000) + +/******************* Bit definition for RCC_LSI32K_CAL_CTRL register ********************/ +#define RCC_CALINTEN ((uint8_t)0x01) +#define RCC_CALEN ((uint8_t)0x02) +#define RCC_HALT ((uint8_t)0x80) + +/******************************************************************************/ +/* RNG */ +/******************************************************************************/ +/******************** Bit definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN ((uint32_t)0x00000004) +#define RNG_CR_IE ((uint32_t)0x00000008) + +/******************** Bit definition for RNG_SR register *******************/ +#define RNG_SR_DRDY ((uint32_t)0x00000001) +#define RNG_SR_CECS ((uint32_t)0x00000002) +#define RNG_SR_SECS ((uint32_t)0x00000004) +#define RNG_SR_CEIS ((uint32_t)0x00000020) +#define RNG_SR_SEIS ((uint32_t)0x00000040) + +/******************************************************************************/ +/* Real-Time Clock */ +/******************************************************************************/ + +/******************* Bit definition for RTC_CTLRH register ********************/ +#define RTC_CTLRH_SECIE ((uint8_t)0x01) /* Second Interrupt Enable */ +#define RTC_CTLRH_ALRIE ((uint8_t)0x02) /* Alarm Interrupt Enable */ +#define RTC_CTLRH_OWIE ((uint8_t)0x04) /* OverfloW Interrupt Enable */ + +/******************* Bit definition for RTC_CTLRL register ********************/ +#define RTC_CTLRL_SECF ((uint8_t)0x01) /* Second Flag */ +#define RTC_CTLRL_ALRF ((uint8_t)0x02) /* Alarm Flag */ +#define RTC_CTLRL_OWF ((uint8_t)0x04) /* OverfloW Flag */ +#define RTC_CTLRL_RSF ((uint8_t)0x08) /* Registers Synchronized Flag */ +#define RTC_CTLRL_CNF ((uint8_t)0x10) /* Configuration Flag */ +#define RTC_CTLRL_RTOFF ((uint8_t)0x20) /* RTC operation OFF */ + +/******************* Bit definition for RTC_PSCH register *******************/ +#define RTC_PSCH_PRL ((uint16_t)0x000F) /* RTC Prescaler Reload Value High */ + +/******************* Bit definition for RTC_PRLL register *******************/ +#define RTC_PSCL_PRL ((uint16_t)0xFFFF) /* RTC Prescaler Reload Value Low */ + +/******************* Bit definition for RTC_DIVH register *******************/ +#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /* RTC Clock Divider High */ + +/******************* Bit definition for RTC_DIVL register *******************/ +#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /* RTC Clock Divider Low */ + +/******************* Bit definition for RTC_CNTH register *******************/ +#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter High */ + +/******************* Bit definition for RTC_CNTL register *******************/ +#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter Low */ + +/******************* Bit definition for RTC_ALRMH register *******************/ +#define RTC_ALRMH_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm High */ + +/******************* Bit definition for RTC_ALRML register *******************/ +#define RTC_ALRML_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm Low */ + +/******************************************************************************/ +/* Serial Peripheral Interface */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CTLR1 register ********************/ +#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ +#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ +#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ + +#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ +#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ +#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ + +#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ +#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /* Frame Format */ +#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ +#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ +#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ +#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ +#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ +#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ +#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CTLR2 register ********************/ +#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ +#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ +#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ +#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ +#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_STATR register ********************/ +#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ +#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ +#define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */ +#define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */ +#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ +#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ +#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ +#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ + +/******************** Bit definition for SPI_DATAR register ********************/ +#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ + +/******************* Bit definition for SPI_CRCR register ******************/ +#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ + +/****************** Bit definition for SPI_RCRCR register ******************/ +#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ + +/****************** Bit definition for SPI_TCRCR register ******************/ +#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ + +/****************** Bit definition for SPI_I2SCFGR register *****************/ +#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /* Channel length (number of bits per audio channel) */ + +#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /* DATLEN[1:0] bits (Data length to be transferred) */ +#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /* Bit 0 */ +#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /* Bit 1 */ + +#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /* steady state clock polarity */ + +#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /* I2SSTD[1:0] bits (I2S standard selection) */ +#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /* Bit 0 */ +#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /* Bit 1 */ + +#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /* PCM frame synchronization */ + +#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /* I2SCFG[1:0] bits (I2S configuration mode) */ +#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /* Bit 0 */ +#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /* I2S Enable */ +#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /* I2S mode selection */ + +/****************** Bit definition for SPI_I2SPR register *******************/ +#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /* I2S Linear prescaler */ +#define SPI_I2SPR_ODD ((uint16_t)0x0100) /* Odd factor for the prescaler */ +#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /* Master Clock Output Enable */ + +/****************** Bit definition for SPI_HSCR register *******************/ +#define SPI_HSCR_HSRXEN ((uint16_t)0x0001) +#define SPI_HSCR_HSRXEN2 ((uint16_t)0x0004) + +/******************************************************************************/ +/* TIM */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CTLR1 register ********************/ +#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ +#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ +#define TIM_URS ((uint16_t)0x0004) /* Update request source */ +#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ +#define TIM_DIR ((uint16_t)0x0010) /* Direction */ + +#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ + +#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ + +/******************* Bit definition for TIM_CTLR2 register ********************/ +#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ +#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ +#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ + +#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ +#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ +#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ +#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ +#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ +#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ +#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ +#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCFGR register *******************/ +#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ + +#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ + +#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ + +#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ +#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ + +/******************* Bit definition for TIM_DMAINTENR register *******************/ +#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ +#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ +#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ +#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ +#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ +#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ +#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ + +/******************** Bit definition for TIM_INTFR register ********************/ +#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ +#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ +#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ +#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ +#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_SWEVGR register ********************/ +#define TIM_UG ((uint8_t)0x01) /* Update Generation */ +#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ +#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ +#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ +#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ +#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ +#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ +#define TIM_BG ((uint8_t)0x80) /* Break Generation */ + +/****************** Bit definition for TIM_CHCTLR1 register *******************/ +#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ +#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ +#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ + + +#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/****************** Bit definition for TIM_CHCTLR2 register *******************/ +#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ +#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ + +#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ + +#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ +#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ + +#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ + + +#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ +#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ +#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ +#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ +#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ + +/******************* Bit definition for TIM_ATRLR register ********************/ +#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ + +/******************* Bit definition for TIM_RPTCR register ********************/ +#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ + +/******************* Bit definition for TIM_CH1CVR register *******************/ +#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ + +/******************* Bit definition for TIM_CH2CVR register *******************/ +#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ + +/******************* Bit definition for TIM_CH3CVR register *******************/ +#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ + +/******************* Bit definition for TIM_CH4CVR register *******************/ +#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ +#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ +#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ +#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ +#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ +#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ +#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ +#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ +#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ + +/******************* Bit definition for TIM_DMACFGR register ********************/ +#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ + +#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ +#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ + +/******************* Bit definition for TIM_DMAADR register *******************/ +#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ + +/******************* Bit definition for TIM_AUX register *******************/ +#define TIM_AUX_CAPCH2_ED ((uint16_t)0x0001) +#define TIM_AUX_CAPCH3_ED ((uint16_t)0x0002) +#define TIM_AUX_CAPCH4_ED ((uint16_t)0x0004) + +/******************************************************************************/ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/******************************************************************************/ + +/******************* Bit definition for USART_STATR register *******************/ +#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ +#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ +#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ +#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ +#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ +#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ +#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ +#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ +#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ +#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ +#define USART_STATR_RX_BUSY ((uint16_t)0x0400) +#define USART_STATR_MS_ERR ((uint16_t)0x0800) + +/******************* Bit definition for USART_DATAR register *******************/ +#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CTLR1 register *******************/ +#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ +#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ +#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ +#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ +#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ +#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ +#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ +#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ +#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ +#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ +#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ +#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ +#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ +#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ +#define USART_CTLR1_M_EXT_0 ((uint16_t)0x4000) +#define USART_CTLR1_M_EXT_1 ((uint16_t)0x8000) +#define USART_CTLR1_M_EXT5 ((uint16_t)0xC000) +#define USART_CTLR1_M_EXT6 ((uint16_t)0x8000) +#define USART_CTLR1_M_EXT7 ((uint16_t)0x4000) + +/****************** Bit definition for USART_CTLR2 register *******************/ +#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ +#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ +#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ +#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ +#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ +#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ +#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ + +#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ +#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ +#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ + +/****************** Bit definition for USART_CTLR3 register *******************/ +#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ +#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ +#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ +#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ +#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ +#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ +#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ +#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ +#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ +#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ +#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ +#define USART_CTLR3_ONEBIT ((uint16_t)0x0800) /* One Bit method */ + +/****************** Bit definition for USART_GPR register ******************/ +#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ +#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ +#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ +#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ +#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ +#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ +#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ +#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ + +/****************** Bit definition for USART_CTLR4 register ******************/ +#define USART_CTLR4_MS_ERRIE ((uint16_t)0x0002) +#define USART_CTLR4_CHECK_SEL ((uint16_t)0x000C) +#define USART_CTLR4_CHECK_MARKENABLE ((uint16_t)0x0008) +#define USART_CTLR4_CHECK_APACEENABLE ((uint16_t)0x000C) + +/******************************************************************************/ +/* OPA */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTLR register ********************/ +#define OPA_EN1 ((uint32_t)0x0001) +#define OPA_MODE1 ((uint32_t)0x0002) +#define OPA_NSEL1 ((uint32_t)0x0004) +#define OPA_PSEL1 ((uint32_t)0x0008) +#define OPA_EN2 ((uint32_t)0x0010) +#define OPA_MODE2 ((uint32_t)0x0020) +#define OPA_NSEL2 ((uint32_t)0x0040) +#define OPA_PSEL2 ((uint32_t)0x0080) +#define OPA_EN3 ((uint32_t)0x0100) +#define OPA_MODE3 ((uint32_t)0x0200) +#define OPA_NSEL3 ((uint32_t)0x0400) +#define OPA_PSEL3 ((uint32_t)0x0800) +#define OPA_EN4 ((uint32_t)0x1000) +#define OPA_MODE4 ((uint32_t)0x2000) +#define OPA_NSEL4 ((uint32_t)0x4000) +#define OPA_PSEL4 ((uint32_t)0x8000) + +/******************************************************************************/ +/* Window WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTLR register ********************/ +#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ +#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ +#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ +#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ +#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ +#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ +#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ + +#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ + +/******************* Bit definition for WWDG_CFGR register *******************/ +#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ +#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ +#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ +#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ +#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ +#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ +#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ +#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ + +#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ +#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ + +#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_STATR register ********************/ +#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* ENHANCED FUNNCTION */ +/******************************************************************************/ + +/**************************** Enhanced CTLR1 register *****************************/ +#define EXTEN_USBD_LS ((uint32_t)0x00000001) /* Bit 0 */ +#define EXTEN_USBD_PU_EN ((uint32_t)0x00000002) /* Bit 1 */ +#define EXTEN_ETH_10M_EN ((uint32_t)0x00000004) /* Bit 2 */ +#define EXTEN_ETH_RGMII_SEL ((uint32_t)0x00000008) /* Bit 3 */ +#define EXTEN_PLL_HSI_PRE ((uint32_t)0x00000010) /* Bit 4 */ +#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 5 */ +#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ + +#define EXTEN_ULLDO_TRIM ((uint32_t)0x00000300) /* ULLDO_TRIM[1:0] bits */ +#define EXTEN_ULLDO_TRIM0 ((uint32_t)0x00000100) /* Bit 0 */ +#define EXTEN_ULLDO_TRIM1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define EXTEN_LDO_TRIM ((uint32_t)0x00000C00) /* LDO_TRIM[1:0] bits */ +#define EXTEN_LDO_TRIM0 ((uint32_t)0x00000400) /* Bit 0 */ +#define EXTEN_LDO_TRIM1 ((uint32_t)0x00000800) /* Bit 1 */ +#define EXTEN_HSEKPLP ((uint32_t)0x00001000) + +/**************************** Enhanced CTLR2 register *****************************/ +#define EXTEN_CTLR2_OPA1_HSMD ((uint32_t)0x00000001) +#define EXTEN_CTLR2_OPA2_HSMD ((uint32_t)0x00000002) +#define EXTEN_CTLR2_OPA3_HSMD ((uint32_t)0x00000004) +#define EXTEN_CTLR2_OPA4_HSMD ((uint32_t)0x00000008) + +/**************************** Enhanced FEATURE_SIGN register *****************************/ + +#define FEATURE_SIGN_VLEVEL ((uint32_t)0x00000001) + +/******************************************************************************/ +/* DVP */ +/******************************************************************************/ + +/******************* Bit definition for DVP_CR0 register ********************/ +#define RB_DVP_ENABLE 0x01 // RW, DVP enable +#define RB_DVP_V_POLAR 0x02 // RW, DVP VSYNC polarity control: 1 = invert, 0 = not invert +#define RB_DVP_H_POLAR 0x04 // RW, DVP HSYNC polarity control: 1 = invert, 0 = not invert +#define RB_DVP_P_POLAR 0x08 // RW, DVP PCLK polarity control: 1 = invert, 0 = not invert +#define RB_DVP_MSK_DAT_MOD 0x30 +#define RB_DVP_D8_MOD 0x00 // RW, DVP 8bits data mode +#define RB_DVP_D10_MOD 0x10 // RW, DVP 10bits data mode +#define RB_DVP_D12_MOD 0x20 // RW, DVP 12bits data mode +#define RB_DVP_JPEG 0x40 // RW, DVP JPEG mode + +/******************* Bit definition for DVP_CR1 register ********************/ +#define RB_DVP_DMA_EN 0x01 // RW, DVP dma enable +#define RB_DVP_ALL_CLR 0x02 // RW, DVP all clear, high action +#define RB_DVP_RCV_CLR 0x04 // RW, DVP receive logic clear, high action +#define RB_DVP_BUF_TOG 0x08 // RW, DVP bug toggle by software, write 1 to toggle, ignored writing 0 +#define RB_DVP_CM 0x10 // RW, DVP capture mode +#define RB_DVP_CROP 0x20 // RW, DVP Crop feature enable +#define RB_DVP_FCRC 0xC0 // RW, DVP frame capture rate control: +#define DVP_RATE_100P 0x00 //00 = every frame captured (100%) +#define DVP_RATE_50P 0x40 //01 = every alternate frame captured (50%) +#define DVP_RATE_25P 0x80 //10 = one frame in four frame captured (25%) + +/******************* Bit definition for DVP_IER register ********************/ +#define RB_DVP_IE_STR_FRM 0x01 // RW, DVP frame start interrupt enable +#define RB_DVP_IE_ROW_DONE 0x02 // RW, DVP row received done interrupt enable +#define RB_DVP_IE_FRM_DONE 0x04 // RW, DVP frame received done interrupt enable +#define RB_DVP_IE_FIFO_OV 0x08 // RW, DVP receive fifo overflow interrupt enable +#define RB_DVP_IE_STP_FRM 0x10 // RW, DVP frame stop interrupt enable + +/******************* Bit definition for DVP_IFR register ********************/ +#define RB_DVP_IF_STR_FRM 0x01 // RW1, interrupt flag for DVP frame start +#define RB_DVP_IF_ROW_DONE 0x02 // RW1, interrupt flag for DVP row receive done +#define RB_DVP_IF_FRM_DONE 0x04 // RW1, interrupt flag for DVP frame receive done +#define RB_DVP_IF_FIFO_OV 0x08 // RW1, interrupt flag for DVP receive fifo overflow +#define RB_DVP_IF_STP_FRM 0x10 // RW1, interrupt flag for DVP frame stop + +/******************* Bit definition for DVP_STATUS register ********************/ +#define RB_DVP_FIFO_RDY 0x01 // RO, DVP receive fifo ready +#define RB_DVP_FIFO_FULL 0x02 // RO, DVP receive fifo full +#define RB_DVP_FIFO_OV 0x04 // RO, DVP receive fifo overflow +#define RB_DVP_MSK_FIFO_CNT 0x70 // RO, DVP receive fifo count + +/******************* Bit definition for DVP_ROW_CNT register ********************/ +#define RB_DVP_ROW_CNT ((uint16_t)0xFF) + +/******************* Bit definition for DVP_HOFFCNT register ********************/ +#define RB_DVP_HOFFCNT ((uint16_t)0xFF) + +/******************* Bit definition for DVP_VST register ********************/ +#define RB_DVP_VST ((uint16_t)0xFF) + +/******************* Bit definition for DVP_CAPCNT register ********************/ +#define RB_DVP_CAPCNT ((uint16_t)0xFF) + +/******************* Bit definition for DVP_VLINE register ********************/ +#define RB_DVP_VLINE ((uint16_t)0xFF) + +/******************* Bit definition for DVP_DR register ********************/ +#define RB_DVP_DR ((uint16_t)0xFF) + +/******************************************************************************/ +/* TKEY */ +/******************************************************************************/ + +/******************* Bit definition for TKEY_CHARGE1 register *******************/ +#define TKEY_CHARGE1_TKCG10 ((uint32_t)0x0007) +#define TKEY_CHARGE1_TKCG10_1C5 ((uint32_t)0x0000) +#define TKEY_CHARGE1_TKCG10_7C5 ((uint32_t)0x0001) +#define TKEY_CHARGE1_TKCG10_13C5 ((uint32_t)0x0002) +#define TKEY_CHARGE1_TKCG10_28C5 ((uint32_t)0x0003) +#define TKEY_CHARGE1_TKCG10_41C5 ((uint32_t)0x0004) +#define TKEY_CHARGE1_TKCG10_55C5 ((uint32_t)0x0005) +#define TKEY_CHARGE1_TKCG10_71C5 ((uint32_t)0x0006) +#define TKEY_CHARGE1_TKCG10_239C5 ((uint32_t)0x0007) + +#define TKEY_CHARGE1_TKCG11 ((uint32_t)0x0038) +#define TKEY_CHARGE1_TKCG11_1C5 ((uint32_t)0x0000) +#define TKEY_CHARGE1_TKCG11_7C5 ((uint32_t)0x0008) +#define TKEY_CHARGE1_TKCG11_13C5 ((uint32_t)0x0010) +#define TKEY_CHARGE1_TKCG11_28C5 ((uint32_t)0x0018) +#define TKEY_CHARGE1_TKCG11_41C5 ((uint32_t)0x0020) +#define TKEY_CHARGE1_TKCG11_55C5 ((uint32_t)0x0028) +#define TKEY_CHARGE1_TKCG11_71C5 ((uint32_t)0x0030) +#define TKEY_CHARGE1_TKCG11_239C5 ((uint32_t)0x0038) + +#define TKEY_CHARGE1_TKCG12 ((uint32_t)0x01C0) +#define TKEY_CHARGE1_TKCG12_1C5 ((uint32_t)0x0000) +#define TKEY_CHARGE1_TKCG12_7C5 ((uint32_t)0x0040) +#define TKEY_CHARGE1_TKCG12_13C5 ((uint32_t)0x0080) +#define TKEY_CHARGE1_TKCG12_28C5 ((uint32_t)0x00C0) +#define TKEY_CHARGE1_TKCG12_41C5 ((uint32_t)0x0100) +#define TKEY_CHARGE1_TKCG12_55C5 ((uint32_t)0x0140) +#define TKEY_CHARGE1_TKCG12_71C5 ((uint32_t)0x0180) +#define TKEY_CHARGE1_TKCG12_239C5 ((uint32_t)0x01C0) + +#define TKEY_CHARGE1_TKCG13 ((uint32_t)0x0E00) +#define TKEY_CHARGE1_TKCG13_1C5 ((uint32_t)0x0000) +#define TKEY_CHARGE1_TKCG13_7C5 ((uint32_t)0x0200) +#define TKEY_CHARGE1_TKCG13_13C5 ((uint32_t)0x0400) +#define TKEY_CHARGE1_TKCG13_28C5 ((uint32_t)0x0600) +#define TKEY_CHARGE1_TKCG13_41C5 ((uint32_t)0x0800) +#define TKEY_CHARGE1_TKCG13_55C5 ((uint32_t)0x0A00) +#define TKEY_CHARGE1_TKCG13_71C5 ((uint32_t)0x0C00) +#define TKEY_CHARGE1_TKCG13_239C5 ((uint32_t)0x0E00) + +#define TKEY_CHARGE1_TKCG14 ((uint32_t)0x7000) + +#define TKEY_CHARGE1_TKCG15 ((uint32_t)0x38000) +#define TKEY_CHARGE1_TKCG16 ((uint32_t)0x1C0000) +#define TKEY_CHARGE1_TKCG17 ((uint32_t)0xE00000) + + +#include "ch32v30x_conf.h" + + +#ifdef __cplusplus +} +#endif + +#endif + + + + diff --git a/Peripheral/inc/ch32v30x_adc.h b/Peripheral/inc/ch32v30x_adc.h new file mode 100644 index 0000000..b0034ed --- /dev/null +++ b/Peripheral/inc/ch32v30x_adc.h @@ -0,0 +1,230 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_adc.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* ADC firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_ADC_H +#define __CH32V30x_ADC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + + +/* ADC Init structure definition */ +typedef struct +{ + uint32_t ADC_Mode; /* Configures the ADC to operate in independent or + dual mode. + This parameter can be a value of @ref ADC_mode */ + + FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ + + uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group. + This parameter must range from 1 to 16. */ + + uint32_t ADC_OutputBuffer; /* Specifies whether the ADC channel output buffer is enabled or disabled. + This parameter can be a value of @ref ADC_OutputBuffer */ + + uint32_t ADC_Pga; /* Specifies the PGA gain multiple. + This parameter can be a value of @ref ADC_Pga */ +}ADC_InitTypeDef; + +/* ADC_mode */ +#define ADC_Mode_Independent ((uint32_t)0x00000000) +#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) +#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) +#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) +#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) +#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) +#define ADC_Mode_RegSimult ((uint32_t)0x00060000) +#define ADC_Mode_FastInterl ((uint32_t)0x00070000) +#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) +#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) + +/* ADC_external_trigger_sources_for_regular_channels_conversion */ +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) + +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) + +#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000) + + +/* ADC_data_align */ +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) + +/* ADC_channels */ +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) +#define ADC_Channel_11 ((uint8_t)0x0B) +#define ADC_Channel_12 ((uint8_t)0x0C) +#define ADC_Channel_13 ((uint8_t)0x0D) +#define ADC_Channel_14 ((uint8_t)0x0E) +#define ADC_Channel_15 ((uint8_t)0x0F) +#define ADC_Channel_16 ((uint8_t)0x10) +#define ADC_Channel_17 ((uint8_t)0x11) + +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) + +/*ADC_output_buffer*/ +#define ADC_OutputBuffer_Enable ((uint32_t)0x04000000) +#define ADC_OutputBuffer_Disable ((uint32_t)0x00000000) + +/*ADC_pga*/ +#define ADC_Pga_1 ((uint32_t)0x00000000) +#define ADC_Pga_4 ((uint32_t)0x08000000) +#define ADC_Pga_16 ((uint32_t)0x10000000) +#define ADC_Pga_64 ((uint32_t)0x18000000) + +/* ADC_sampling_time */ +#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) +#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) +#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) +#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) +#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) +#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) +#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) +#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) + +/* ADC_external_trigger_sources_for_injected_channels_conversion */ +#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) +#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) +#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) + +#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) + +#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000) +#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000) +#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000) + + +/* ADC_injected_channel_selection */ +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) + +/* ADC_analog_watchdog_selection */ +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +/* ADC_interrupts_definition */ +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +/* ADC_flags_definition */ +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) + + +void ADC_DeInit(ADC_TypeDef* ADCx); +void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState); +void ADC_ResetCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_StartCalibration(ADC_TypeDef* ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx); +void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number); +void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx); +uint32_t ADC_GetDualModeConversionValue(void); +void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx); +void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length); +void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel); +void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel); +void ADC_TempSensorVrefintCmd(FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT); +s32 TempSensor_Volt_To_Temper(s32 Value); +void ADC_BufferCmd(ADC_TypeDef* ADCx, FunctionalState NewState); +int16_t Get_CalibrationValue(ADC_TypeDef* ADCx); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + diff --git a/Peripheral/inc/ch32v30x_bkp.h b/Peripheral/inc/ch32v30x_bkp.h new file mode 100644 index 0000000..898add4 --- /dev/null +++ b/Peripheral/inc/ch32v30x_bkp.h @@ -0,0 +1,99 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_bkp.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* BKP firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_BKP_H +#define __CH32V30x_BKP_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* Tamper_Pin_active_level */ +#define BKP_TamperPinLevel_High ((uint16_t)0x0000) +#define BKP_TamperPinLevel_Low ((uint16_t)0x0001) + +/* RTC_output_source_to_output_on_the_Tamper_pin */ +#define BKP_RTCOutputSource_None ((uint16_t)0x0000) +#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080) +#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100) +#define BKP_RTCOutputSource_Second ((uint16_t)0x0300) + +/* Data_Backup_Register */ +#define BKP_DR1 ((uint16_t)0x0004) +#define BKP_DR2 ((uint16_t)0x0008) +#define BKP_DR3 ((uint16_t)0x000C) +#define BKP_DR4 ((uint16_t)0x0010) +#define BKP_DR5 ((uint16_t)0x0014) +#define BKP_DR6 ((uint16_t)0x0018) +#define BKP_DR7 ((uint16_t)0x001C) +#define BKP_DR8 ((uint16_t)0x0020) +#define BKP_DR9 ((uint16_t)0x0024) +#define BKP_DR10 ((uint16_t)0x0028) +#define BKP_DR11 ((uint16_t)0x0040) +#define BKP_DR12 ((uint16_t)0x0044) +#define BKP_DR13 ((uint16_t)0x0048) +#define BKP_DR14 ((uint16_t)0x004C) +#define BKP_DR15 ((uint16_t)0x0050) +#define BKP_DR16 ((uint16_t)0x0054) +#define BKP_DR17 ((uint16_t)0x0058) +#define BKP_DR18 ((uint16_t)0x005C) +#define BKP_DR19 ((uint16_t)0x0060) +#define BKP_DR20 ((uint16_t)0x0064) +#define BKP_DR21 ((uint16_t)0x0068) +#define BKP_DR22 ((uint16_t)0x006C) +#define BKP_DR23 ((uint16_t)0x0070) +#define BKP_DR24 ((uint16_t)0x0074) +#define BKP_DR25 ((uint16_t)0x0078) +#define BKP_DR26 ((uint16_t)0x007C) +#define BKP_DR27 ((uint16_t)0x0080) +#define BKP_DR28 ((uint16_t)0x0084) +#define BKP_DR29 ((uint16_t)0x0088) +#define BKP_DR30 ((uint16_t)0x008C) +#define BKP_DR31 ((uint16_t)0x0090) +#define BKP_DR32 ((uint16_t)0x0094) +#define BKP_DR33 ((uint16_t)0x0098) +#define BKP_DR34 ((uint16_t)0x009C) +#define BKP_DR35 ((uint16_t)0x00A0) +#define BKP_DR36 ((uint16_t)0x00A4) +#define BKP_DR37 ((uint16_t)0x00A8) +#define BKP_DR38 ((uint16_t)0x00AC) +#define BKP_DR39 ((uint16_t)0x00B0) +#define BKP_DR40 ((uint16_t)0x00B4) +#define BKP_DR41 ((uint16_t)0x00B8) +#define BKP_DR42 ((uint16_t)0x00BC) + + +void BKP_DeInit(void); +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel); +void BKP_TamperPinCmd(FunctionalState NewState); +void BKP_ITConfig(FunctionalState NewState); +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource); +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue); +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data); +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR); +FlagStatus BKP_GetFlagStatus(void); +void BKP_ClearFlag(void); +ITStatus BKP_GetITStatus(void); +void BKP_ClearITPendingBit(void); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/Peripheral/inc/ch32v30x_can.h b/Peripheral/inc/ch32v30x_can.h new file mode 100644 index 0000000..21f7bf0 --- /dev/null +++ b/Peripheral/inc/ch32v30x_can.h @@ -0,0 +1,376 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_can.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* CAN firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_CAN_H +#define __CH32V30x_CAN_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* CAN init structure definition */ +typedef struct +{ + uint16_t CAN_Prescaler; /* Specifies the length of a time quantum. + It ranges from 1 to 1024. */ + + uint8_t CAN_Mode; /* Specifies the CAN operating mode. + This parameter can be a value of + @ref CAN_operating_mode */ + + uint8_t CAN_SJW; /* Specifies the maximum number of time quanta + the CAN hardware is allowed to lengthen or + shorten a bit to perform resynchronization. + This parameter can be a value of + @ref CAN_synchronisation_jump_width */ + + uint8_t CAN_BS1; /* Specifies the number of time quanta in Bit + Segment 1. This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_1 */ + + uint8_t CAN_BS2; /* Specifies the number of time quanta in Bit + Segment 2. + This parameter can be a value of + @ref CAN_time_quantum_in_bit_segment_2 */ + + FunctionalState CAN_TTCM; /* Enable or disable the time triggered + communication mode. This parameter can be set + either to ENABLE or DISABLE. */ + + FunctionalState CAN_ABOM; /* Enable or disable the automatic bus-off + management. This parameter can be set either + to ENABLE or DISABLE. */ + + FunctionalState CAN_AWUM; /* Enable or disable the automatic wake-up mode. + This parameter can be set either to ENABLE or + DISABLE. */ + + FunctionalState CAN_NART; /* Enable or disable the no-automatic + retransmission mode. This parameter can be + set either to ENABLE or DISABLE. */ + + FunctionalState CAN_RFLM; /* Enable or disable the Receive FIFO Locked mode. + This parameter can be set either to ENABLE + or DISABLE. */ + + FunctionalState CAN_TXFP; /* Enable or disable the transmit FIFO priority. + This parameter can be set either to ENABLE + or DISABLE. */ +} CAN_InitTypeDef; + +/* CAN filter init structure definition */ +typedef struct +{ + uint16_t CAN_FilterIdHigh; /* Specifies the filter identification number (MSBs for a 32-bit + configuration, first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterIdLow; /* Specifies the filter identification number (LSBs for a 32-bit + configuration, second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdHigh; /* Specifies the filter mask number or identification number, + according to the mode (MSBs for a 32-bit configuration, + first one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterMaskIdLow; /* Specifies the filter mask number or identification number, + according to the mode (LSBs for a 32-bit configuration, + second one for a 16-bit configuration). + This parameter can be a value between 0x0000 and 0xFFFF */ + + uint16_t CAN_FilterFIFOAssignment; /* Specifies the FIFO (0 or 1) which will be assigned to the filter. + This parameter can be a value of @ref CAN_filter_FIFO */ + + uint8_t CAN_FilterNumber; /* Specifies the filter which will be initialized. It ranges from 0 to 13. */ + + uint8_t CAN_FilterMode; /* Specifies the filter mode to be initialized. + This parameter can be a value of @ref CAN_filter_mode */ + + uint8_t CAN_FilterScale; /* Specifies the filter scale. + This parameter can be a value of @ref CAN_filter_scale */ + + FunctionalState CAN_FilterActivation; /* Enable or disable the filter. + This parameter can be set either to ENABLE or DISABLE. */ +} CAN_FilterInitTypeDef; + +/* CAN Tx message structure definition */ +typedef struct +{ + uint32_t StdId; /* Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /* Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /* Specifies the type of identifier for the message that + will be transmitted. This parameter can be a value + of @ref CAN_identifier_type */ + + uint8_t RTR; /* Specifies the type of frame for the message that will + be transmitted. This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /* Specifies the length of the frame that will be + transmitted. This parameter can be a value between + 0 to 8 */ + + uint8_t Data[8]; /* Contains the data to be transmitted. It ranges from 0 + to 0xFF. */ +} CanTxMsg; + +/* CAN Rx message structure definition */ +typedef struct +{ + uint32_t StdId; /* Specifies the standard identifier. + This parameter can be a value between 0 to 0x7FF. */ + + uint32_t ExtId; /* Specifies the extended identifier. + This parameter can be a value between 0 to 0x1FFFFFFF. */ + + uint8_t IDE; /* Specifies the type of identifier for the message that + will be received. This parameter can be a value of + @ref CAN_identifier_type */ + + uint8_t RTR; /* Specifies the type of frame for the received message. + This parameter can be a value of + @ref CAN_remote_transmission_request */ + + uint8_t DLC; /* Specifies the length of the frame that will be received. + This parameter can be a value between 0 to 8 */ + + uint8_t Data[8]; /* Contains the data to be received. It ranges from 0 to + 0xFF. */ + + uint8_t FMI; /* Specifies the index of the filter the message stored in + the mailbox passes through. This parameter can be a + value between 0 to 0xFF */ +} CanRxMsg; + +/* CAN_sleep_constants */ +#define CAN_InitStatus_Failed ((uint8_t)0x00) /* CAN initialization failed */ +#define CAN_InitStatus_Success ((uint8_t)0x01) /* CAN initialization OK */ + +/* CAN_Mode */ +#define CAN_Mode_Normal ((uint8_t)0x00) /* normal mode */ +#define CAN_Mode_LoopBack ((uint8_t)0x01) /* loopback mode */ +#define CAN_Mode_Silent ((uint8_t)0x02) /* silent mode */ +#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /* loopback combined with silent mode */ + +/* CAN_Operating_Mode */ +#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /* Initialization mode */ +#define CAN_OperatingMode_Normal ((uint8_t)0x01) /* Normal mode */ +#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /* sleep mode */ + +/* CAN_Mode_Status */ +#define CAN_ModeStatus_Failed ((uint8_t)0x00) /* CAN entering the specific mode failed */ +#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /* CAN entering the specific mode Succeed */ + +/* CAN_synchronisation_jump_width */ +#define CAN_SJW_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_SJW_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_SJW_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_SJW_4tq ((uint8_t)0x03) /* 4 time quantum */ + +/* CAN_time_quantum_in_bit_segment_1 */ +#define CAN_BS1_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_BS1_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_BS1_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_BS1_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CAN_BS1_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CAN_BS1_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CAN_BS1_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CAN_BS1_8tq ((uint8_t)0x07) /* 8 time quantum */ +#define CAN_BS1_9tq ((uint8_t)0x08) /* 9 time quantum */ +#define CAN_BS1_10tq ((uint8_t)0x09) /* 10 time quantum */ +#define CAN_BS1_11tq ((uint8_t)0x0A) /* 11 time quantum */ +#define CAN_BS1_12tq ((uint8_t)0x0B) /* 12 time quantum */ +#define CAN_BS1_13tq ((uint8_t)0x0C) /* 13 time quantum */ +#define CAN_BS1_14tq ((uint8_t)0x0D) /* 14 time quantum */ +#define CAN_BS1_15tq ((uint8_t)0x0E) /* 15 time quantum */ +#define CAN_BS1_16tq ((uint8_t)0x0F) /* 16 time quantum */ + +/* CAN_time_quantum_in_bit_segment_2 */ +#define CAN_BS2_1tq ((uint8_t)0x00) /* 1 time quantum */ +#define CAN_BS2_2tq ((uint8_t)0x01) /* 2 time quantum */ +#define CAN_BS2_3tq ((uint8_t)0x02) /* 3 time quantum */ +#define CAN_BS2_4tq ((uint8_t)0x03) /* 4 time quantum */ +#define CAN_BS2_5tq ((uint8_t)0x04) /* 5 time quantum */ +#define CAN_BS2_6tq ((uint8_t)0x05) /* 6 time quantum */ +#define CAN_BS2_7tq ((uint8_t)0x06) /* 7 time quantum */ +#define CAN_BS2_8tq ((uint8_t)0x07) /* 8 time quantum */ + +/* CAN_filter_mode */ +#define CAN_FilterMode_IdMask ((uint8_t)0x00) /* identifier/mask mode */ +#define CAN_FilterMode_IdList ((uint8_t)0x01) /* identifier list mode */ + +/* CAN_filter_scale */ +#define CAN_FilterScale_16bit ((uint8_t)0x00) /* Two 16-bit filters */ +#define CAN_FilterScale_32bit ((uint8_t)0x01) /* One 32-bit filter */ + +/* CAN_filter_FIFO */ +#define CAN_Filter_FIFO0 ((uint8_t)0x00) /* Filter FIFO 0 assignment for filter x */ +#define CAN_Filter_FIFO1 ((uint8_t)0x01) /* Filter FIFO 1 assignment for filter x */ + +/* CAN_identifier_type */ +#define CAN_Id_Standard ((uint32_t)0x00000000) /* Standard Id */ +#define CAN_Id_Extended ((uint32_t)0x00000004) /* Extended Id */ + +/* CAN_remote_transmission_request */ +#define CAN_RTR_Data ((uint32_t)0x00000000) /* Data frame */ +#define CAN_RTR_Remote ((uint32_t)0x00000002) /* Remote frame */ + +/* CAN_transmit_constants */ +#define CAN_TxStatus_Failed ((uint8_t)0x00)/* CAN transmission failed */ +#define CAN_TxStatus_Ok ((uint8_t)0x01) /* CAN transmission succeeded */ +#define CAN_TxStatus_Pending ((uint8_t)0x02) /* CAN transmission pending */ +#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /* CAN cell did not provide an empty mailbox */ + +/* CAN_receive_FIFO_number_constants */ +#define CAN_FIFO0 ((uint8_t)0x00) /* CAN FIFO 0 used to receive */ +#define CAN_FIFO1 ((uint8_t)0x01) /* CAN FIFO 1 used to receive */ + +/* CAN_sleep_constants */ +#define CAN_Sleep_Failed ((uint8_t)0x00) /* CAN did not enter the sleep mode */ +#define CAN_Sleep_Ok ((uint8_t)0x01) /* CAN entered the sleep mode */ + +/* CAN_wake_up_constants */ +#define CAN_WakeUp_Failed ((uint8_t)0x00) /* CAN did not leave the sleep mode */ +#define CAN_WakeUp_Ok ((uint8_t)0x01) /* CAN leaved the sleep mode */ + +/* CAN_Error_Code_constants */ +#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /* No Error */ +#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /* Stuff Error */ +#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /* Form Error */ +#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /* Acknowledgment Error */ +#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /* Bit Recessive Error */ +#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /* Bit Dominant Error */ +#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /* CRC Error */ +#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /* Software Set Error */ + + +/* CAN_flags */ +/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus() + * and CAN_ClearFlag() functions. + * If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function. +*/ +/* Transmit Flags */ +#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /* Request MailBox0 Flag */ +#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /* Request MailBox1 Flag */ +#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /* Request MailBox2 Flag */ + +/* Receive Flags */ +#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /* FIFO 0 Message Pending Flag */ +#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /* FIFO 0 Full Flag */ +#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /* FIFO 0 Overrun Flag */ +#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /* FIFO 1 Message Pending Flag */ +#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /* FIFO 1 Full Flag */ +#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /* FIFO 1 Overrun Flag */ + +/* Operating Mode Flags */ +#define CAN_FLAG_WKU ((uint32_t)0x31000008) /* Wake up Flag */ +#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /* Sleep acknowledge Flag */ +/* Note: + *When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible. + *In this case the SLAK bit can be polled. +*/ + +/* Error Flags */ +#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /* Error Warning Flag */ +#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /* Error Passive Flag */ +#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /* Bus-Off Flag */ +#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /* Last error code Flag */ + + +/* CAN_interrupts */ +#define CAN_IT_TME ((uint32_t)0x00000001) /* Transmit mailbox empty Interrupt*/ + +/* Receive Interrupts */ +#define CAN_IT_FMP0 ((uint32_t)0x00000002) /* FIFO 0 message pending Interrupt*/ +#define CAN_IT_FF0 ((uint32_t)0x00000004) /* FIFO 0 full Interrupt*/ +#define CAN_IT_FOV0 ((uint32_t)0x00000008) /* FIFO 0 overrun Interrupt*/ +#define CAN_IT_FMP1 ((uint32_t)0x00000010) /* FIFO 1 message pending Interrupt*/ +#define CAN_IT_FF1 ((uint32_t)0x00000020) /* FIFO 1 full Interrupt*/ +#define CAN_IT_FOV1 ((uint32_t)0x00000040) /* FIFO 1 overrun Interrupt*/ + +/* Operating Mode Interrupts */ +#define CAN_IT_WKU ((uint32_t)0x00010000) /* Wake-up Interrupt*/ +#define CAN_IT_SLK ((uint32_t)0x00020000) /* Sleep acknowledge Interrupt*/ + +/* Error Interrupts */ +#define CAN_IT_EWG ((uint32_t)0x00000100) /* Error warning Interrupt*/ +#define CAN_IT_EPV ((uint32_t)0x00000200) /* Error passive Interrupt*/ +#define CAN_IT_BOF ((uint32_t)0x00000400) /* Bus-off Interrupt*/ +#define CAN_IT_LEC ((uint32_t)0x00000800) /* Last error code Interrupt*/ +#define CAN_IT_ERR ((uint32_t)0x00008000) /* Error Interrupt*/ + +/* Flags named as Interrupts : kept only for FW compatibility */ +#define CAN_IT_RQCP0 CAN_IT_TME +#define CAN_IT_RQCP1 CAN_IT_TME +#define CAN_IT_RQCP2 CAN_IT_TME + +/* CAN_Legacy */ +#define CANINITFAILED CAN_InitStatus_Failed +#define CANINITOK CAN_InitStatus_Success +#define CAN_FilterFIFO0 CAN_Filter_FIFO0 +#define CAN_FilterFIFO1 CAN_Filter_FIFO1 +#define CAN_ID_STD CAN_Id_Standard +#define CAN_ID_EXT CAN_Id_Extended +#define CAN_RTR_DATA CAN_RTR_Data +#define CAN_RTR_REMOTE CAN_RTR_Remote +#define CANTXFAILE CAN_TxStatus_Failed +#define CANTXOK CAN_TxStatus_Ok +#define CANTXPENDING CAN_TxStatus_Pending +#define CAN_NO_MB CAN_TxStatus_NoMailBox +#define CANSLEEPFAILED CAN_Sleep_Failed +#define CANSLEEPOK CAN_Sleep_Ok +#define CANWAKEUPFAILED CAN_WakeUp_Failed +#define CANWAKEUPOK CAN_WakeUp_Ok + + +void CAN_DeInit(CAN_TypeDef* CANx); +uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct); +void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct); +void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct); +void CAN_SlaveStartBank(uint8_t CAN_BankNumber); +void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState); +void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState); +uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage); +uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox); +void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox); +void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage); +void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber); +uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber); +uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode); +uint8_t CAN_Sleep(CAN_TypeDef* CANx); +uint8_t CAN_WakeUp(CAN_TypeDef* CANx); +uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx); +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx); +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx); +void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState); +FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG); +ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT); +void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/Peripheral/inc/ch32v30x_crc.h b/Peripheral/inc/ch32v30x_crc.h new file mode 100644 index 0000000..026378f --- /dev/null +++ b/Peripheral/inc/ch32v30x_crc.h @@ -0,0 +1,39 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_crc.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* CRC firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_CRC_H +#define __CH32V30x_CRC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + + +void CRC_ResetDR(void); +uint32_t CRC_CalcCRC(uint32_t Data); +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength); +uint32_t CRC_GetCRC(void); +void CRC_SetIDRegister(uint8_t IDValue); +uint8_t CRC_GetIDRegister(void); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/Peripheral/inc/ch32v30x_dac.h b/Peripheral/inc/ch32v30x_dac.h new file mode 100644 index 0000000..ae7d7a8 --- /dev/null +++ b/Peripheral/inc/ch32v30x_dac.h @@ -0,0 +1,122 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dac.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* DAC firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_DAC_H +#define __CH32V30x_DAC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* DAC Init structure definition */ +typedef struct +{ + uint32_t DAC_Trigger; /* Specifies the external trigger for the selected DAC channel. + This parameter can be a value of @ref DAC_trigger_selection */ + + uint32_t DAC_WaveGeneration; /* Specifies whether DAC channel noise waves or triangle waves + are generated, or whether no wave is generated. + This parameter can be a value of @ref DAC_wave_generation */ + + uint32_t DAC_LFSRUnmask_TriangleAmplitude; /* Specifies the LFSR mask for noise wave generation or + the maximum amplitude triangle generation for the DAC channel. + This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */ + + uint32_t DAC_OutputBuffer; /* Specifies whether the DAC channel output buffer is enabled or disabled. + This parameter can be a value of @ref DAC_output_buffer */ +}DAC_InitTypeDef; + + +/* DAC_trigger_selection */ +#define DAC_Trigger_None ((uint32_t)0x00000000) /* Conversion is automatic once the DAC1_DHRxxxx register + has been loaded, and not by external trigger */ +#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /* TIM6 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /* TIM8 TRGO selected as external conversion trigger for DAC channel + only in High-density devices*/ +#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /* TIM7 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /* TIM5 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /* TIM2 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /* TIM4 TRGO selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /* EXTI Line9 event selected as external conversion trigger for DAC channel */ +#define DAC_Trigger_Software ((uint32_t)0x0000003C) /* Conversion started by software trigger for DAC channel */ + +/* DAC_wave_generation */ +#define DAC_WaveGeneration_None ((uint32_t)0x00000000) +#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040) +#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080) + + +/* DAC_lfsrunmask_triangleamplitude */ +#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /* Unmask DAC channel LFSR bit0 for noise wave generation */ +#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /* Unmask DAC channel LFSR bit[1:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /* Unmask DAC channel LFSR bit[2:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /* Unmask DAC channel LFSR bit[3:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /* Unmask DAC channel LFSR bit[4:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /* Unmask DAC channel LFSR bit[5:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /* Unmask DAC channel LFSR bit[6:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /* Unmask DAC channel LFSR bit[7:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /* Unmask DAC channel LFSR bit[8:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /* Unmask DAC channel LFSR bit[9:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /* Unmask DAC channel LFSR bit[10:0] for noise wave generation */ +#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /* Unmask DAC channel LFSR bit[11:0] for noise wave generation */ +#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /* Select max triangle amplitude of 1 */ +#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /* Select max triangle amplitude of 3 */ +#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /* Select max triangle amplitude of 7 */ +#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /* Select max triangle amplitude of 15 */ +#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /* Select max triangle amplitude of 31 */ +#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /* Select max triangle amplitude of 63 */ +#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /* Select max triangle amplitude of 127 */ +#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /* Select max triangle amplitude of 255 */ +#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /* Select max triangle amplitude of 511 */ +#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /* Select max triangle amplitude of 1023 */ +#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /* Select max triangle amplitude of 2047 */ +#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /* Select max triangle amplitude of 4095 */ + +/* DAC_output_buffer */ +#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000) +#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002) + +/* DAC_Channel_selection */ +#define DAC_Channel_1 ((uint32_t)0x00000000) +#define DAC_Channel_2 ((uint32_t)0x00000010) + +/* DAC_data_alignment */ +#define DAC_Align_12b_R ((uint32_t)0x00000000) +#define DAC_Align_12b_L ((uint32_t)0x00000004) +#define DAC_Align_8b_R ((uint32_t)0x00000008) + +/* DAC_wave_generation */ +#define DAC_Wave_Noise ((uint32_t)0x00000040) +#define DAC_Wave_Triangle ((uint32_t)0x00000080) + + +void DAC_DeInit(void); +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct); +void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct); +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState); +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Peripheral/inc/ch32v30x_dbgmcu.h b/Peripheral/inc/ch32v30x_dbgmcu.h new file mode 100644 index 0000000..fbb0ff0 --- /dev/null +++ b/Peripheral/inc/ch32v30x_dbgmcu.h @@ -0,0 +1,60 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dbgmcu.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* DBGMCU firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_DBGMCU_H +#define __CH32V30x_DBGMCU_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +#define DBGMCU_SLEEP ((uint32_t)0x00000001) +#define DBGMCU_STOP ((uint32_t)0x00000002) +#define DBGMCU_STANDBY ((uint32_t)0x00000004) +#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100) +#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200) +#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00000400) +#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00000800) +#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000) +#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000) +#define DBGMCU_TIM3_STOP ((uint32_t)0x00004000) +#define DBGMCU_TIM4_STOP ((uint32_t)0x00008000) +#define DBGMCU_TIM5_STOP ((uint32_t)0x00010000) +#define DBGMCU_TIM6_STOP ((uint32_t)0x00020000) +#define DBGMCU_TIM7_STOP ((uint32_t)0x00040000) +#define DBGMCU_TIM8_STOP ((uint32_t)0x00080000) +#define DBGMCU_CAN1_STOP ((uint32_t)0x00100000) +#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000) +#define DBGMCU_TIM9_STOP ((uint32_t)0x00400000) +#define DBGMCU_TIM10_STOP ((uint32_t)0x00800000) + +uint32_t DBGMCU_GetREVID(void); +uint32_t DBGMCU_GetDEVID(void); +uint32_t __get_DEBUG_CR(void); +void __set_DEBUG_CR(uint32_t value); +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState); +uint32_t DBGMCU_GetCHIPID( void ); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + diff --git a/Peripheral/inc/ch32v30x_dma.h b/Peripheral/inc/ch32v30x_dma.h new file mode 100644 index 0000000..848e9fc --- /dev/null +++ b/Peripheral/inc/ch32v30x_dma.h @@ -0,0 +1,270 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dma.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* DMA firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_DMA_H +#define __CH32V30x_DMA_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* DMA Init structure definition */ +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ + + uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction. */ + + uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +}DMA_InitTypeDef; + +/* DMA_data_transfer_direction */ +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) + +/* DMA_peripheral_incremented_mode */ +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) + +/* DMA_memory_incremented_mode */ +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) + +/* DMA_peripheral_data_size */ +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) + +/* DMA_memory_data_size */ +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) + +/* DMA_circular_normal_mode */ +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) + +/* DMA_priority_level */ +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) + +/* DMA_memory_to_memory */ +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) + +/* DMA_interrupts_definition */ +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) + +#define DMA2_IT_GL1 ((uint32_t)0x10000001) +#define DMA2_IT_TC1 ((uint32_t)0x10000002) +#define DMA2_IT_HT1 ((uint32_t)0x10000004) +#define DMA2_IT_TE1 ((uint32_t)0x10000008) +#define DMA2_IT_GL2 ((uint32_t)0x10000010) +#define DMA2_IT_TC2 ((uint32_t)0x10000020) +#define DMA2_IT_HT2 ((uint32_t)0x10000040) +#define DMA2_IT_TE2 ((uint32_t)0x10000080) +#define DMA2_IT_GL3 ((uint32_t)0x10000100) +#define DMA2_IT_TC3 ((uint32_t)0x10000200) +#define DMA2_IT_HT3 ((uint32_t)0x10000400) +#define DMA2_IT_TE3 ((uint32_t)0x10000800) +#define DMA2_IT_GL4 ((uint32_t)0x10001000) +#define DMA2_IT_TC4 ((uint32_t)0x10002000) +#define DMA2_IT_HT4 ((uint32_t)0x10004000) +#define DMA2_IT_TE4 ((uint32_t)0x10008000) +#define DMA2_IT_GL5 ((uint32_t)0x10010000) +#define DMA2_IT_TC5 ((uint32_t)0x10020000) +#define DMA2_IT_HT5 ((uint32_t)0x10040000) +#define DMA2_IT_TE5 ((uint32_t)0x10080000) +#define DMA2_IT_GL6 ((uint32_t)0x10100000) +#define DMA2_IT_TC6 ((uint32_t)0x10200000) +#define DMA2_IT_HT6 ((uint32_t)0x10400000) +#define DMA2_IT_TE6 ((uint32_t)0x10800000) +#define DMA2_IT_GL7 ((uint32_t)0x11000000) +#define DMA2_IT_TC7 ((uint32_t)0x12000000) +#define DMA2_IT_HT7 ((uint32_t)0x14000000) +#define DMA2_IT_TE7 ((uint32_t)0x18000000) + +#define DMA2_IT_GL8 ((uint32_t)0x20000001) +#define DMA2_IT_TC8 ((uint32_t)0x20000002) +#define DMA2_IT_HT8 ((uint32_t)0x20000004) +#define DMA2_IT_TE8 ((uint32_t)0x20000008) +#define DMA2_IT_GL9 ((uint32_t)0x20000010) +#define DMA2_IT_TC9 ((uint32_t)0x20000020) +#define DMA2_IT_HT9 ((uint32_t)0x20000040) +#define DMA2_IT_TE9 ((uint32_t)0x20000080) +#define DMA2_IT_GL10 ((uint32_t)0x20000100) +#define DMA2_IT_TC10 ((uint32_t)0x20000200) +#define DMA2_IT_HT10 ((uint32_t)0x20000400) +#define DMA2_IT_TE10 ((uint32_t)0x20000800) +#define DMA2_IT_GL11 ((uint32_t)0x20001000) +#define DMA2_IT_TC11 ((uint32_t)0x20002000) +#define DMA2_IT_HT11 ((uint32_t)0x20004000) +#define DMA2_IT_TE11 ((uint32_t)0x20008000) + +/* DMA_flags_definition */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) + +#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) +#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) +#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) +#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) +#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) +#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) +#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) +#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) +#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) +#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) +#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) +#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) +#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) +#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) +#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) +#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) +#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) +#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) +#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) +#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) +#define DMA2_FLAG_GL6 ((uint32_t)0x10100000) +#define DMA2_FLAG_TC6 ((uint32_t)0x10200000) +#define DMA2_FLAG_HT6 ((uint32_t)0x10400000) +#define DMA2_FLAG_TE6 ((uint32_t)0x10800000) +#define DMA2_FLAG_GL7 ((uint32_t)0x11000000) +#define DMA2_FLAG_TC7 ((uint32_t)0x12000000) +#define DMA2_FLAG_HT7 ((uint32_t)0x14000000) +#define DMA2_FLAG_TE7 ((uint32_t)0x18000000) + +#define DMA2_FLAG_GL8 ((uint32_t)0x20000001) +#define DMA2_FLAG_TC8 ((uint32_t)0x20000002) +#define DMA2_FLAG_HT8 ((uint32_t)0x20000004) +#define DMA2_FLAG_TE8 ((uint32_t)0x20000008) +#define DMA2_FLAG_GL9 ((uint32_t)0x20000010) +#define DMA2_FLAG_TC9 ((uint32_t)0x20000020) +#define DMA2_FLAG_HT9 ((uint32_t)0x20000040) +#define DMA2_FLAG_TE9 ((uint32_t)0x20000080) +#define DMA2_FLAG_GL10 ((uint32_t)0x20000100) +#define DMA2_FLAG_TC10 ((uint32_t)0x20000200) +#define DMA2_FLAG_HT10 ((uint32_t)0x20000400) +#define DMA2_FLAG_TE10 ((uint32_t)0x20000800) +#define DMA2_FLAG_GL11 ((uint32_t)0x20001000) +#define DMA2_FLAG_TC11 ((uint32_t)0x20002000) +#define DMA2_FLAG_HT11 ((uint32_t)0x20004000) +#define DMA2_FLAG_TE11 ((uint32_t)0x20008000) + + +void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx); +void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber); +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx); +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); +void DMA_ClearFlag(uint32_t DMAy_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMAy_IT); +void DMA_ClearITPendingBit(uint32_t DMAy_IT); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Peripheral/inc/ch32v30x_dvp.h b/Peripheral/inc/ch32v30x_dvp.h new file mode 100644 index 0000000..fde0693 --- /dev/null +++ b/Peripheral/inc/ch32v30x_dvp.h @@ -0,0 +1,69 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dvp.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* DVP firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_DVP_H +#define __CH32V30x_DVP_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* DVP Data Mode */ +typedef enum +{ + Video_Mode = 0, + JPEG_Mode, +}DVP_Data_ModeTypeDef; + + +/* DVP DMA */ +typedef enum +{ + DVP_DMA_Disable = 0, + DVP_DMA_Enable, +}DVP_DMATypeDef; + +/* DVP FLAG and FIFO Reset */ +typedef enum +{ + DVP_FLAG_FIFO_RESET_Disable = 0, + DVP_FLAG_FIFO_RESET_Enable, +}DVP_FLAG_FIFO_RESETTypeDef; + +/* DVP RX Reset */ +typedef enum +{ + DVP_RX_RESET_Disable = 0, + DVP_RX_RESET_Enable, +}DVP_RX_RESETTypeDef; + + + +void DVP_INTCfg( uint8_t s, uint8_t i ); +void DVP_Mode( uint8_t s, DVP_Data_ModeTypeDef i); +void DVP_Cfg( DVP_DMATypeDef s, DVP_FLAG_FIFO_RESETTypeDef i, DVP_RX_RESETTypeDef j); + + + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + diff --git a/Peripheral/inc/ch32v30x_eth.h b/Peripheral/inc/ch32v30x_eth.h new file mode 100644 index 0000000..88dfafd --- /dev/null +++ b/Peripheral/inc/ch32v30x_eth.h @@ -0,0 +1,1338 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_eth.h +* Author : WCH +* Version : V1.0.1 +* Date : 2025/01/08 +* Description : This file contains all the functions prototypes for the +* ETH firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_ETH_H +#define __CH32V30x_ETH_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + + +#define PHY_10BASE_T_LINKED 1 +#define PHY_10BASE_T_NOT_LINKED 0 + +#define DMA_TPS_Mask ((uint32_t)0x00700000) +#define DMA_RPS_Mask ((uint32_t)0x000E0000) + +/* ETH Init structure definition */ +typedef struct { + uint32_t ETH_AutoNegotiation; /* Selects or not the AutoNegotiation mode for the external PHY + The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) + and the mode (half/full-duplex). + This parameter can be a value of @ref ETH_AutoNegotiation */ + + uint32_t ETH_Watchdog; /* Selects or not the Watchdog timer + When enabled, the MAC allows no more then 2048 bytes to be received. + When disabled, the MAC can receive up to 16384 bytes. + This parameter can be a value of @ref ETH_watchdog */ + + uint32_t ETH_Jabber; /* Selects or not Jabber timer + When enabled, the MAC allows no more then 2048 bytes to be sent. + When disabled, the MAC can send up to 16384 bytes. + This parameter can be a value of @ref ETH_Jabber */ + + uint32_t ETH_InterFrameGap; /* Selects the minimum IFG between frames during transmission + This parameter can be a value of @ref ETH_Inter_Frame_Gap */ + + uint32_t ETH_CarrierSense; /* Selects or not the Carrier Sense + This parameter can be a value of @ref ETH_Carrier_Sense */ + + uint32_t ETH_Speed; /* Sets the Ethernet speed: 10/100 Mbps + This parameter can be a value of @ref ETH_Speed */ + + uint32_t ETH_ReceiveOwn; /* Selects or not the ReceiveOwn + ReceiveOwn allows the reception of frames when the TX_EN signal is asserted + in Half-Duplex mode + This parameter can be a value of @ref ETH_Receive_Own */ + + uint32_t ETH_LoopbackMode; /* Selects or not the internal MAC MII Loopback mode + This parameter can be a value of @ref ETH_Loop_Back_Mode */ + + uint32_t ETH_Mode; /* Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode + This parameter can be a value of @ref ETH_Duplex_Mode */ + + uint32_t ETH_ChecksumOffload; /* Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. + This parameter can be a value of @ref ETH_Checksum_Offload */ + + uint32_t ETH_RetryTransmission; /* Selects or not the MAC attempt retries transmission, based on the settings of BL, + when a colision occurs (Half-Duplex mode) + This parameter can be a value of @ref ETH_Retry_Transmission */ + + uint32_t ETH_AutomaticPadCRCStrip; /* Selects or not the Automatic MAC Pad/CRC Stripping + This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ + + uint32_t ETH_BackOffLimit; /* Selects the BackOff limit value + This parameter can be a value of @ref ETH_Back_Off_Limit */ + + uint32_t ETH_DeferralCheck; /* Selects or not the deferral check function (Half-Duplex mode) + This parameter can be a value of @ref ETH_Deferral_Check */ + + uint32_t ETH_ReceiveAll; /* Selects or not all frames reception by the MAC (No fitering) + This parameter can be a value of @ref ETH_Receive_All */ + + uint32_t ETH_SourceAddrFilter; /* Selects the Source Address Filter mode + This parameter can be a value of @ref ETH_Source_Addr_Filter */ + + uint32_t ETH_PassControlFrames; /* Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) + This parameter can be a value of @ref ETH_Pass_Control_Frames */ + + uint32_t ETH_BroadcastFramesReception; /* Selects or not the reception of Broadcast Frames + This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ + + uint32_t ETH_DestinationAddrFilter; /* Sets the destination filter mode for both unicast and multicast frames + This parameter can be a value of @ref ETH_Destination_Addr_Filter */ + + uint32_t ETH_PromiscuousMode; /* Selects or not the Promiscuous Mode + This parameter can be a value of @ref ETH_Promiscuous_Mode */ + + uint32_t ETH_MulticastFramesFilter; /* Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter + This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ + + uint32_t ETH_UnicastFramesFilter; /* Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter + This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ + + uint32_t ETH_HashTableHigh; /* This field holds the higher 32 bits of Hash table. */ + + uint32_t ETH_HashTableLow; /* This field holds the lower 32 bits of Hash table. */ + + uint32_t ETH_PauseTime; /* This field holds the value to be used in the Pause Time field in the + transmit control frame */ + + uint32_t ETH_ZeroQuantaPause; /* Selects or not the automatic generation of Zero-Quanta Pause Control frames + This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ + + uint32_t ETH_PauseLowThreshold; /* This field configures the threshold of the PAUSE to be checked for + automatic retransmission of PAUSE Frame + This parameter can be a value of @ref ETH_Pause_Low_Threshold */ + + uint32_t ETH_UnicastPauseFrameDetect; /* Selects or not the MAC detection of the Pause frames (with MAC Address0 + unicast address and unique multicast address) + This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ + + uint32_t ETH_ReceiveFlowControl; /* Enables or disables the MAC to decode the received Pause frame and + disable its transmitter for a specified time (Pause Time) + This parameter can be a value of @ref ETH_Receive_Flow_Control */ + + uint32_t ETH_TransmitFlowControl; /* Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) + or the MAC back-pressure operation (Half-Duplex mode) + This parameter can be a value of @ref ETH_Transmit_Flow_Control */ + + uint32_t ETH_VLANTagComparison; /* Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for + comparison and filtering + This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ + + uint32_t ETH_VLANTagIdentifier; /* Holds the VLAN tag identifier for receive frames */ + + uint32_t ETH_DropTCPIPChecksumErrorFrame; /* Selects or not the Dropping of TCP/IP Checksum Error Frames + This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ + + uint32_t ETH_ReceiveStoreForward; /* Enables or disables the Receive store and forward mode + This parameter can be a value of @ref ETH_Receive_Store_Forward */ + + uint32_t ETH_FlushReceivedFrame; /* Enables or disables the flushing of received frames + This parameter can be a value of @ref ETH_Flush_Received_Frame */ + + uint32_t ETH_TransmitStoreForward; /* Enables or disables Transmit store and forward mode + This parameter can be a value of @ref ETH_Transmit_Store_Forward */ + + uint32_t ETH_TransmitThresholdControl; /* Selects or not the Transmit Threshold Control + This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ + + uint32_t ETH_ForwardErrorFrames; /* Selects or not the forward to the DMA of erroneous frames + This parameter can be a value of @ref ETH_Forward_Error_Frames */ + + uint32_t ETH_ForwardUndersizedGoodFrames; /* Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error + and length less than 64 bytes) including pad-bytes and CRC) + This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ + + uint32_t ETH_ReceiveThresholdControl; /* Selects the threshold level of the Receive FIFO + This parameter can be a value of @ref ETH_Receive_Threshold_Control */ + + uint32_t ETH_SecondFrameOperate; /* Selects or not the Operate on second frame mode, which allows the DMA to process a second + frame of Transmit data even before obtaining the status for the first frame. + This parameter can be a value of @ref ETH_Second_Frame_Operate */ + + uint32_t ETH_AddressAlignedBeats; /* Enables or disables the Address Aligned Beats + This parameter can be a value of @ref ETH_Address_Aligned_Beats */ + + uint32_t ETH_FixedBurst; /* Enables or disables the AHB Master interface fixed burst transfers + This parameter can be a value of @ref ETH_Fixed_Burst */ + + uint32_t ETH_RxDMABurstLength; /* Indicates the maximum number of beats to be transferred in one Rx DMA transaction + This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ + + uint32_t ETH_TxDMABurstLength; /* Indicates sthe maximum number of beats to be transferred in one Tx DMA transaction + This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ + + uint32_t ETH_DescriptorSkipLength; /* Specifies the number of word to skip between two unchained descriptors (Ring mode) */ + + uint32_t ETH_DMAArbitration; /* Selects the DMA Tx/Rx arbitration + This parameter can be a value of @ref ETH_DMA_Arbitration */ +}ETH_InitTypeDef; + + + +/* ETH delay.Just for Ethernet */ +#define _eth_delay_ ETH_Delay /* Default _eth_delay_ function with less precise timing */ + +/* definition for Ethernet frame */ +#define ETH_MAX_PACKET_SIZE 1524 /* ETH_HEADER + ETH_EXTRA + MAX_ETH_PAYLOAD + ETH_CRC */ +#define ETH_HEADER 14 /* 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC 4 /* Ethernet CRC */ +#define ETH_EXTRA 2 /* Extra bytes in some cases */ +#define VLAN_TAG 4 /* optional 802.1q VLAN Tag */ +#define MIN_ETH_PAYLOAD 46 /* Minimum Ethernet payload size */ +#define MAX_ETH_PAYLOAD 1500 /* Maximum Ethernet payload size */ +#define JUMBO_FRAME_PAYLOAD 9000 /* Jumbo frame payload size */ + +/* ETH DMA structure definition */ +typedef struct +{ + uint32_t volatile Status; /* Status */ + uint32_t ControlBufferSize; /* Control and Buffer1, Buffer2 lengths */ + uint32_t Buffer1Addr; /* Buffer1 address pointer */ + uint32_t Buffer2NextDescAddr; /* Buffer2 or next descriptor address pointer */ +} ETH_DMADESCTypeDef; + +/** + DMA Tx Desciptor + ----------------------------------------------------------------------------------------------- + TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | + ----------------------------------------------------------------------------------------------- + TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | + ----------------------------------------------------------------------------------------------- + TDES2 | Buffer1 Address [31:0] | + ----------------------------------------------------------------------------------------------- + TDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + ------------------------------------------------------------------------------------------------ +*/ + + +/* Bit or field definition of TDES0 register (DMA Tx descriptor status register)*/ +#define ETH_DMATxDesc_OWN ((uint32_t)0x80000000) /* OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMATxDesc_IC ((uint32_t)0x40000000) /* Interrupt on Completion */ +#define ETH_DMATxDesc_LS ((uint32_t)0x20000000) /* Last Segment */ +#define ETH_DMATxDesc_FS ((uint32_t)0x10000000) /* First Segment */ +#define ETH_DMATxDesc_DC ((uint32_t)0x08000000) /* Disable CRC */ +#define ETH_DMATxDesc_DP ((uint32_t)0x04000000) /* Disable Padding */ +#define ETH_DMATxDesc_TTSE ((uint32_t)0x02000000) /* Transmit Time Stamp Enable */ +#define ETH_DMATxDesc_CIC ((uint32_t)0x00C00000) /* Checksum Insertion Control: 4 cases */ +#define ETH_DMATxDesc_CIC_ByPass ((uint32_t)0x00000000) /* Do Nothing: Checksum Engine is bypassed */ +#define ETH_DMATxDesc_CIC_IPV4Header ((uint32_t)0x00400000) /* IPV4 header Checksum Insertion */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Segment ((uint32_t)0x00800000) /* TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMATxDesc_CIC_TCPUDPICMP_Full ((uint32_t)0x00C00000) /* TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMATxDesc_TER ((uint32_t)0x00200000) /* Transmit End of Ring */ +#define ETH_DMATxDesc_TCH ((uint32_t)0x00100000) /* Second Address Chained */ +#define ETH_DMATxDesc_TTSS ((uint32_t)0x00020000) /* Tx Time Stamp Status */ +#define ETH_DMATxDesc_IHE ((uint32_t)0x00010000) /* IP Header Error */ +#define ETH_DMATxDesc_ES ((uint32_t)0x00008000) /* Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ +#define ETH_DMATxDesc_JT ((uint32_t)0x00004000) /* Jabber Timeout */ +#define ETH_DMATxDesc_FF ((uint32_t)0x00002000) /* Frame Flushed: DMA/MTL flushed the frame due to SW flush */ +#define ETH_DMATxDesc_PCE ((uint32_t)0x00001000) /* Payload Checksum Error */ +#define ETH_DMATxDesc_LCA ((uint32_t)0x00000800) /* Loss of Carrier: carrier lost during tramsmission */ +#define ETH_DMATxDesc_NC ((uint32_t)0x00000400) /* No Carrier: no carrier signal from the tranceiver */ +#define ETH_DMATxDesc_LCO ((uint32_t)0x00000200) /* Late Collision: transmission aborted due to collision */ +#define ETH_DMATxDesc_EC ((uint32_t)0x00000100) /* Excessive Collision: transmission aborted after 16 collisions */ +#define ETH_DMATxDesc_VF ((uint32_t)0x00000080) /* VLAN Frame */ +#define ETH_DMATxDesc_CC ((uint32_t)0x00000078) /* Collision Count */ +#define ETH_DMATxDesc_ED ((uint32_t)0x00000004) /* Excessive Deferral */ +#define ETH_DMATxDesc_UF ((uint32_t)0x00000002) /* Underflow Error: late data arrival from the memory */ +#define ETH_DMATxDesc_DB ((uint32_t)0x00000001) /* Deferred Bit */ + +/* Field definition of TDES1 register */ +#define ETH_DMATxDesc_TBS2 ((uint32_t)0x1FFF0000) /* Transmit Buffer2 Size */ +#define ETH_DMATxDesc_TBS1 ((uint32_t)0x00001FFF) /* Transmit Buffer1 Size */ + +/* Field definition of TDES2 register */ +#define ETH_DMATxDesc_B1AP ((uint32_t)0xFFFFFFFF) /* Buffer1 Address Pointer */ + +/* Field definition of TDES3 register */ +#define ETH_DMATxDesc_B2AP ((uint32_t)0xFFFFFFFF) /* Buffer2 Address Pointer */ + +/** + DMA Rx Desciptor + --------------------------------------------------------------------------------------------------------------------- + RDES0 | OWN(31) | Status [30:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES2 | Buffer1 Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES3 | Buffer2 Address [31:0] / Next Desciptor Address [31:0] | + ---------------------------------------------------------------------------------------------------------------------- +*/ + +/* Bit or field definition of RDES0 register (DMA Rx descriptor status register) */ +#define ETH_DMARxDesc_OWN ((uint32_t)0x80000000) /* OWN bit: descriptor is owned by DMA engine */ +#define ETH_DMARxDesc_AFM ((uint32_t)0x40000000) /* DA Filter Fail for the rx frame */ +#define ETH_DMARxDesc_FL ((uint32_t)0x3FFF0000) /* Receive descriptor frame length */ +#define ETH_DMARxDesc_ES ((uint32_t)0x00008000) /* Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ +#define ETH_DMARxDesc_DE ((uint32_t)0x00004000) /* Desciptor error: no more descriptors for receive frame */ +#define ETH_DMARxDesc_SAF ((uint32_t)0x00002000) /* SA Filter Fail for the received frame */ +#define ETH_DMARxDesc_LE ((uint32_t)0x00001000) /* Frame size not matching with length field */ +#define ETH_DMARxDesc_OE ((uint32_t)0x00000800) /* Overflow Error: Frame was damaged due to buffer overflow */ +#define ETH_DMARxDesc_VLAN ((uint32_t)0x00000400) /* VLAN Tag: received frame is a VLAN frame */ +#define ETH_DMARxDesc_FS ((uint32_t)0x00000200) /* First descriptor of the frame */ +#define ETH_DMARxDesc_LS ((uint32_t)0x00000100) /* Last descriptor of the frame */ +#define ETH_DMARxDesc_IPV4HCE ((uint32_t)0x00000080) /* IPC Checksum Error: Rx Ipv4 header checksum error */ +#define ETH_DMARxDesc_LC ((uint32_t)0x00000040) /* Late collision occurred during reception */ +#define ETH_DMARxDesc_FT ((uint32_t)0x00000020) /* Frame type - Ethernet, otherwise 802.3 */ +#define ETH_DMARxDesc_RWT ((uint32_t)0x00000010) /* Receive Watchdog Timeout: watchdog timer expired during reception */ +#define ETH_DMARxDesc_RE ((uint32_t)0x00000008) /* Receive error: error reported by MII interface */ +#define ETH_DMARxDesc_DBE ((uint32_t)0x00000004) /* Dribble bit error: frame contains non int multiple of 8 bits */ +#define ETH_DMARxDesc_CE ((uint32_t)0x00000002) /* CRC error */ +#define ETH_DMARxDesc_MAMPCE ((uint32_t)0x00000001) /* Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ + +/* Bit or field definition of RDES1 register */ +#define ETH_DMARxDesc_DIC ((uint32_t)0x80000000) /* Disable Interrupt on Completion */ +#define ETH_DMARxDesc_RBS2 ((uint32_t)0x1FFF0000) /* Receive Buffer2 Size */ +#define ETH_DMARxDesc_RER ((uint32_t)0x00008000) /* Receive End of Ring */ +#define ETH_DMARxDesc_RCH ((uint32_t)0x00004000) /* Second Address Chained */ +#define ETH_DMARxDesc_RBS1 ((uint32_t)0x00001FFF) /* Receive Buffer1 Size */ + +/* Field definition of RDES2 register */ +#define ETH_DMARxDesc_B1AP ((uint32_t)0xFFFFFFFF) /* Buffer1 Address Pointer */ + +/* Field definition of RDES3 register */ +#define ETH_DMARxDesc_B2AP ((uint32_t)0xFFFFFFFF) /* Buffer2 Address Pointer */ + +/* Timeout threshold of Reading or writing PHY registers */ +#define PHY_READ_TO ((uint32_t)0x004FFFFF) +#define PHY_WRITE_TO ((uint32_t)0x0004FFFF) + +/* Delay time after reset PHY */ +#define PHY_ResetDelay ((uint32_t)0x000FFFFF) + +/* Delay time after configure PHY */ +#define PHY_ConfigDelay ((uint32_t)0x00FFFFFF) + +/* PHY basic register */ +#define PHY_BCR 0x0 /*PHY transceiver Basic Control Register */ +#define PHY_BSR 0x01 /*PHY transceiver Basic Status Register*/ +#define PHY_ANAR 0x04 /* Auto-Negotiation Advertisement Register */ +#define PHY_ANLPAR 0x05 /* Auto-Negotiation Link Partner Base Page Ability Register*/ +#define PHY_ANER 0x06 /* Auto-Negotiation Expansion Register */ +#define PHY_BMCR PHY_BCR +#define PHY_BMSR PHY_BSR +#define PHY_STATUS 0x10 +#define PHY_MDIX 0x1E + +/* Bit or field definition for PHY basic control register */ +#define PHY_Reset ((uint16_t)0x8000) /* PHY Reset */ +#define PHY_Loopback ((uint16_t)0x4000) /* Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /* Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /* Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /* Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /* Set the half-duplex mode at 10 Mb/s */ +#define PHY_AutoNegotiation ((uint16_t)0x1000) /* Enable auto-negotiation function */ +#define PHY_Restart_AutoNegotiation ((uint16_t)0x0200) /* Restart auto-negotiation function */ +#define PHY_Powerdown ((uint16_t)0x0800) /* Select the power down mode */ +#define PHY_Isolate ((uint16_t)0x0400) /* Isolate PHY from MII */ + +/* Bit or field definition for PHY basic status register */ +#define PHY_AutoNego_Complete ((uint16_t)0x0020) /* Auto-Negotioation process completed */ +#define PHY_Linked_Status ((uint16_t)0x0004) /* Valid link established */ +#define PHY_Jabber_detection ((uint16_t)0x0002) /* Jabber condition detected */ +#define PHY_RMII_Mode ((uint16_t)0x0020) /* RMII */ + + +/* Internal 10BASE-T PHY 50R*4 pull-up resistance enable or disable */ +#define ETH_Internal_Pull_Up_Res_Enable ((uint32_t)0x00100000) +#define ETH_Internal_Pull_Up_Res_Disable ((uint32_t)0x00000000) + +/* MAC autoNegotiation enable or disable */ +#define ETH_AutoNegotiation_Enable ((uint32_t)0x00000001) +#define ETH_AutoNegotiation_Disable ((uint32_t)0x00000000) + +/* MAC watchdog enable or disable */ +#define ETH_Watchdog_Enable ((uint32_t)0x00000000) +#define ETH_Watchdog_Disable ((uint32_t)0x00800000) + +/* Bit description - MAC jabber enable or disable */ +#define ETH_Jabber_Enable ((uint32_t)0x00000000) +#define ETH_Jabber_Disable ((uint32_t)0x00400000) + +/* Value of minimum IFG between frames during transmission */ +#define ETH_InterFrameGap_96Bit ((uint32_t)0x00000000) /* minimum IFG between frames during transmission is 96Bit */ +#define ETH_InterFrameGap_88Bit ((uint32_t)0x00020000) /* minimum IFG between frames during transmission is 88Bit */ +#define ETH_InterFrameGap_80Bit ((uint32_t)0x00040000) /* minimum IFG between frames during transmission is 80Bit */ +#define ETH_InterFrameGap_72Bit ((uint32_t)0x00060000) /* minimum IFG between frames during transmission is 72Bit */ +#define ETH_InterFrameGap_64Bit ((uint32_t)0x00080000) /* minimum IFG between frames during transmission is 64Bit */ +#define ETH_InterFrameGap_56Bit ((uint32_t)0x000A0000) /* minimum IFG between frames during transmission is 56Bit */ +#define ETH_InterFrameGap_48Bit ((uint32_t)0x000C0000) /* minimum IFG between frames during transmission is 48Bit */ +#define ETH_InterFrameGap_40Bit ((uint32_t)0x000E0000) /* minimum IFG between frames during transmission is 40Bit */ + +/* MAC carrier sense enable or disable */ +#define ETH_CarrierSense_Enable ((uint32_t)0x00000000) +#define ETH_CarrierSense_Disable ((uint32_t)0x00010000) + +/* MAC speed */ +#define ETH_Speed_10M ((uint32_t)0x00000000) +#define ETH_Speed_100M ((uint32_t)0x00004000) +#define ETH_Speed_1000M ((uint32_t)0x00008000) + +/* MAC receive own enable or disable */ +#define ETH_ReceiveOwn_Enable ((uint32_t)0x00000000) +#define ETH_ReceiveOwn_Disable ((uint32_t)0x00002000) + +/* MAC Loopback mode enable or disable */ +#define ETH_LoopbackMode_Enable ((uint32_t)0x00001000) +#define ETH_LoopbackMode_Disable ((uint32_t)0x00000000) + +/* MAC fullDuplex or halfDuplex */ +#define ETH_Mode_FullDuplex ((uint32_t)0x00000800) +#define ETH_Mode_HalfDuplex ((uint32_t)0x00000000) + +/* MAC offload checksum enable or disable */ +#define ETH_ChecksumOffload_Enable ((uint32_t)0x00000400) +#define ETH_ChecksumOffload_Disable ((uint32_t)0x00000000) + +/* MAC transmission retry enable or disable */ +#define ETH_RetryTransmission_Enable ((uint32_t)0x00000000) +#define ETH_RetryTransmission_Disable ((uint32_t)0x00000200) + +/* MAC automatic pad CRC strip enable or disable */ +#define ETH_AutomaticPadCRCStrip_Enable ((uint32_t)0x00000080) +#define ETH_AutomaticPadCRCStrip_Disable ((uint32_t)0x00000000) + +/* MAC backoff limitation */ +#define ETH_BackOffLimit_10 ((uint32_t)0x00000000) +#define ETH_BackOffLimit_8 ((uint32_t)0x00000020) +#define ETH_BackOffLimit_4 ((uint32_t)0x00000040) +#define ETH_BackOffLimit_1 ((uint32_t)0x00000060) + +/* MAC deferral check enable or disable */ +#define ETH_DeferralCheck_Enable ((uint32_t)0x00000010) +#define ETH_DeferralCheck_Disable ((uint32_t)0x00000000) + +/* Bit description : MAC receive all frame enable or disable */ +#define ETH_ReceiveAll_Enable ((uint32_t)0x80000000) +#define ETH_ReceiveAll_Disable ((uint32_t)0x00000000) + +/* MAC backoff limitation */ +#define ETH_SourceAddrFilter_Normal_Enable ((uint32_t)0x00000200) +#define ETH_SourceAddrFilter_Inverse_Enable ((uint32_t)0x00000300) +#define ETH_SourceAddrFilter_Disable ((uint32_t)0x00000000) + +/* MAC Pass control frames */ +#define ETH_PassControlFrames_BlockAll ((uint32_t)0x00000040) /* MAC filters all control frames from reaching the application */ +#define ETH_PassControlFrames_ForwardAll ((uint32_t)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ +#define ETH_PassControlFrames_ForwardPassedAddrFilter ((uint32_t)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ + +/* MAC broadcast frames reception */ +#define ETH_BroadcastFramesReception_Enable ((uint32_t)0x00000000) +#define ETH_BroadcastFramesReception_Disable ((uint32_t)0x00000020) + +/* MAC destination address filter */ +#define ETH_DestinationAddrFilter_Normal ((uint32_t)0x00000000) +#define ETH_DestinationAddrFilter_Inverse ((uint32_t)0x00000008) + +/* MAC Promiscuous mode enable or disable */ +#define ETH_PromiscuousMode_Enable ((uint32_t)0x00000001) +#define ETH_PromiscuousMode_Disable ((uint32_t)0x00000000) + +/* MAC multicast frames filter */ +#define ETH_MulticastFramesFilter_PerfectHashTable ((uint32_t)0x00000404) +#define ETH_MulticastFramesFilter_HashTable ((uint32_t)0x00000004) +#define ETH_MulticastFramesFilter_Perfect ((uint32_t)0x00000000) +#define ETH_MulticastFramesFilter_None ((uint32_t)0x00000010) + +/* MAC unicast frames filter */ +#define ETH_UnicastFramesFilter_PerfectHashTable ((uint32_t)0x00000402) +#define ETH_UnicastFramesFilter_HashTable ((uint32_t)0x00000002) +#define ETH_UnicastFramesFilter_Perfect ((uint32_t)0x00000000) + +/* Bit description : MAC zero quanta pause */ +#define ETH_ZeroQuantaPause_Enable ((uint32_t)0x00000000) +#define ETH_ZeroQuantaPause_Disable ((uint32_t)0x00000080) + +/* Field description : MAC pause low threshold */ +#define ETH_PauseLowThreshold_Minus4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */ +#define ETH_PauseLowThreshold_Minus28 ((uint32_t)0x00000010) /* Pause time minus 28 slot times */ +#define ETH_PauseLowThreshold_Minus144 ((uint32_t)0x00000020) /* Pause time minus 144 slot times */ +#define ETH_PauseLowThreshold_Minus256 ((uint32_t)0x00000030) /* Pause time minus 256 slot times */ + +/* MAC unicast pause frame detect enable or disable*/ +#define ETH_UnicastPauseFrameDetect_Enable ((uint32_t)0x00000008) +#define ETH_UnicastPauseFrameDetect_Disable ((uint32_t)0x00000000) + +/* MAC receive flow control frame enable or disable */ +#define ETH_ReceiveFlowControl_Enable ((uint32_t)0x00000004) +#define ETH_ReceiveFlowControl_Disable ((uint32_t)0x00000000) + +/* MAC transmit flow control enable or disable */ +#define ETH_TransmitFlowControl_Enable ((uint32_t)0x00000002) +#define ETH_TransmitFlowControl_Disable ((uint32_t)0x00000000) + +/* MAC VLAN tag comparison */ +#define ETH_VLANTagComparison_12Bit ((uint32_t)0x00010000) +#define ETH_VLANTagComparison_16Bit ((uint32_t)0x00000000) + +/* MAC flag */ +#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /* Time stamp trigger flag (on MAC) */ +#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /* MMC transmit flag */ +#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /* MMC receive flag */ +#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /* MMC flag (on MAC) */ +#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /* PMT flag (on MAC) */ + +/* MAC interrupt */ +#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /* Time stamp trigger interrupt (on MAC) */ +#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /* MMC transmit interrupt */ +#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /* MMC receive interrupt */ +#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /* MMC interrupt (on MAC) */ +#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /* PMT interrupt (on MAC) */ + +/* MAC address */ +#define ETH_MAC_Address0 ((uint32_t)0x00000000) +#define ETH_MAC_Address1 ((uint32_t)0x00000008) +#define ETH_MAC_Address2 ((uint32_t)0x00000010) +#define ETH_MAC_Address3 ((uint32_t)0x00000018) + +/* MAC address filter select */ +#define ETH_MAC_AddressFilter_SA ((uint32_t)0x00000000) +#define ETH_MAC_AddressFilter_DA ((uint32_t)0x00000008) + +/* MAC address mask */ +#define ETH_MAC_AddressMask_Byte6 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte5 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */ +#define ETH_MAC_AddressMask_Byte4 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */ +#define ETH_MAC_AddressMask_Byte3 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */ +#define ETH_MAC_AddressMask_Byte2 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */ +#define ETH_MAC_AddressMask_Byte1 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [70] */ + + +/******************************************************************************/ +/* */ +/* MAC Descriptor Register */ +/* */ +/******************************************************************************/ + +/* DMA descriptor segment */ +#define ETH_DMATxDesc_LastSegment ((uint32_t)0x40000000) /* Last Segment */ +#define ETH_DMATxDesc_FirstSegment ((uint32_t)0x20000000) /* First Segment */ + +/* DMA descriptor checksum setting */ +#define ETH_DMATxDesc_ChecksumByPass ((uint32_t)0x00000000) /* Checksum engine bypass */ +#define ETH_DMATxDesc_ChecksumIPV4Header ((uint32_t)0x00400000) /* IPv4 header checksum insertion */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPSegment ((uint32_t)0x00800000) /* TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ +#define ETH_DMATxDesc_ChecksumTCPUDPICMPFull ((uint32_t)0x00C00000) /* TCP/UDP/ICMP checksum fully in hardware including pseudo header */ + +/* DMA RX & TX buffer */ +#define ETH_DMARxDesc_Buffer1 ((uint32_t)0x00000000) /* DMA Rx Desc Buffer1 */ +#define ETH_DMARxDesc_Buffer2 ((uint32_t)0x00000001) /* DMA Rx Desc Buffer2 */ + + +/******************************************************************************/ +/* */ +/* ETH DMA Register */ +/* */ +/******************************************************************************/ + +/* DMA drop TCPIP checksum error frame enable or disable */ +#define ETH_DropTCPIPChecksumErrorFrame_Enable ((uint32_t)0x00000000) +#define ETH_DropTCPIPChecksumErrorFrame_Disable ((uint32_t)0x04000000) + +/* DMA receive store forward enable or disable */ +#define ETH_ReceiveStoreForward_Enable ((uint32_t)0x02000000) +#define ETH_ReceiveStoreForward_Disable ((uint32_t)0x00000000) + +/* DMA flush received frame enable or disable */ +#define ETH_FlushReceivedFrame_Enable ((uint32_t)0x00000000) +#define ETH_FlushReceivedFrame_Disable ((uint32_t)0x01000000) + +/* DMA transmit store forward enable or disable */ +#define ETH_TransmitStoreForward_Enable ((uint32_t)0x00200000) +#define ETH_TransmitStoreForward_Disable ((uint32_t)0x00000000) + +/* DMA transmit threshold control */ +#define ETH_TransmitThresholdControl_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ +#define ETH_TransmitThresholdControl_128Bytes ((uint32_t)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ +#define ETH_TransmitThresholdControl_192Bytes ((uint32_t)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ +#define ETH_TransmitThresholdControl_256Bytes ((uint32_t)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ +#define ETH_TransmitThresholdControl_40Bytes ((uint32_t)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ +#define ETH_TransmitThresholdControl_32Bytes ((uint32_t)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ +#define ETH_TransmitThresholdControl_24Bytes ((uint32_t)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ +#define ETH_TransmitThresholdControl_16Bytes ((uint32_t)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ + +/* DMA forward error frames */ +#define ETH_ForwardErrorFrames_Enable ((uint32_t)0x00000080) +#define ETH_ForwardErrorFrames_Disable ((uint32_t)0x00000000) + +/* DMA forward undersized good frames enable or disable */ +#define ETH_ForwardUndersizedGoodFrames_Enable ((uint32_t)0x00000040) +#define ETH_ForwardUndersizedGoodFrames_Disable ((uint32_t)0x00000000) + +/* DMA receive threshold control */ +#define ETH_ReceiveThresholdControl_64Bytes ((uint32_t)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ +#define ETH_ReceiveThresholdControl_32Bytes ((uint32_t)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ +#define ETH_ReceiveThresholdControl_96Bytes ((uint32_t)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ +#define ETH_ReceiveThresholdControl_128Bytes ((uint32_t)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ + +/* DMA second frame operate enable or disable */ +#define ETH_SecondFrameOperate_Enable ((uint32_t)0x00000004) +#define ETH_SecondFrameOperate_Disable ((uint32_t)0x00000000) + +/* Address aligned beats enable or disable */ +#define ETH_AddressAlignedBeats_Enable ((uint32_t)0x02000000) +#define ETH_AddressAlignedBeats_Disable ((uint32_t)0x00000000) + +/* DMA Fixed burst enable or disable */ +#define ETH_FixedBurst_Enable ((uint32_t)0x00010000) +#define ETH_FixedBurst_Disable ((uint32_t)0x00000000) + + +/* RX DMA burst length */ +#define ETH_RxDMABurstLength_1Beat ((uint32_t)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ +#define ETH_RxDMABurstLength_2Beat ((uint32_t)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ +#define ETH_RxDMABurstLength_4Beat ((uint32_t)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_8Beat ((uint32_t)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_16Beat ((uint32_t)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_32Beat ((uint32_t)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_RxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_RxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_RxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_RxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ +#define ETH_RxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ + + +/* TX DMA burst length */ +#define ETH_TxDMABurstLength_1Beat ((uint32_t)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ +#define ETH_TxDMABurstLength_2Beat ((uint32_t)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ +#define ETH_TxDMABurstLength_4Beat ((uint32_t)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_8Beat ((uint32_t)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_16Beat ((uint32_t)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_32Beat ((uint32_t)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_4xPBL_4Beat ((uint32_t)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_TxDMABurstLength_4xPBL_8Beat ((uint32_t)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_TxDMABurstLength_4xPBL_16Beat ((uint32_t)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_TxDMABurstLength_4xPBL_32Beat ((uint32_t)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_TxDMABurstLength_4xPBL_64Beat ((uint32_t)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ +#define ETH_TxDMABurstLength_4xPBL_128Beat ((uint32_t)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ + +/* DMA arbitration_round robin */ +#define ETH_DMAArbitration_RoundRobin_RxTx_1_1 ((uint32_t)0x00000000) +#define ETH_DMAArbitration_RoundRobin_RxTx_2_1 ((uint32_t)0x00004000) +#define ETH_DMAArbitration_RoundRobin_RxTx_3_1 ((uint32_t)0x00008000) +#define ETH_DMAArbitration_RoundRobin_RxTx_4_1 ((uint32_t)0x0000C000) +#define ETH_DMAArbitration_RxPriorTx ((uint32_t)0x00000002) + +/* DMA interrupt FALG */ +#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /* Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /* PMT interrupt (on DMA) */ +#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /* MMC interrupt (on DMA) */ +#define ETH_DMA_FLAG_DataTransferError ((uint32_t)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMA_FLAG_ReadWriteError ((uint32_t)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ +#define ETH_DMA_FLAG_AccessError ((uint32_t)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ +#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /* Normal interrupt summary flag */ +#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary flag */ +#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /* Early receive flag */ +#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /* Fatal bus error flag */ +#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /* Early transmit flag */ +#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /* Receive watchdog timeout flag */ +#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /* Receive process stopped flag */ +#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /* Receive buffer unavailable flag */ +#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /* Receive flag */ +#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /* Underflow flag */ +#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /* Overflow flag */ +#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /* Transmit jabber timeout flag */ +#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /* Transmit buffer unavailable flag */ +#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /* Transmit process stopped flag */ +#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /* Transmit flag */ + +/* DMA interrupt */ +#define ETH_DMA_IT_PHYLINK ((uint32_t)0x80000000) /* Internal PHY link status change interrupt */ +#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /* Time-stamp trigger interrupt (on DMA) */ +#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /* PMT interrupt (on DMA) */ +#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /* MMC interrupt (on DMA) */ +#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /* Normal interrupt summary */ +#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /* Early receive interrupt */ +#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /* Fatal bus error interrupt */ +#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /* Early transmit interrupt */ +#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /* Receive watchdog timeout interrupt */ +#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /* Receive process stopped interrupt */ +#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /* Receive buffer unavailable interrupt */ +#define ETH_DMA_IT_R ((uint32_t)0x00000040) /* Receive interrupt */ +#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /* Underflow interrupt */ +#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /* Overflow interrupt */ +#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /* Transmit jabber timeout interrupt */ +#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /* Transmit buffer unavailable interrupt */ +#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /* Transmit process stopped interrupt */ +#define ETH_DMA_IT_T ((uint32_t)0x00000001) /* Transmit interrupt */ + +/* DMA transmit process */ +#define ETH_DMA_TransmitProcess_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ +#define ETH_DMA_TransmitProcess_Fetching ((uint32_t)0x00100000) /* Running - fetching the Tx descriptor */ +#define ETH_DMA_TransmitProcess_Waiting ((uint32_t)0x00200000) /* Running - waiting for status */ +#define ETH_DMA_TransmitProcess_Reading ((uint32_t)0x00300000) /* Running - reading the data from host memory */ +#define ETH_DMA_TransmitProcess_Suspended ((uint32_t)0x00600000) /* Suspended - Tx Desciptor unavailabe */ +#define ETH_DMA_TransmitProcess_Closing ((uint32_t)0x00700000) /* Running - closing Rx descriptor */ + +/* DMA receive Process */ +#define ETH_DMA_ReceiveProcess_Stopped ((uint32_t)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ +#define ETH_DMA_ReceiveProcess_Fetching ((uint32_t)0x00020000) /* Running - fetching the Rx descriptor */ +#define ETH_DMA_ReceiveProcess_Waiting ((uint32_t)0x00060000) /* Running - waiting for packet */ +#define ETH_DMA_ReceiveProcess_Suspended ((uint32_t)0x00080000) /* Suspended - Rx Desciptor unavailable */ +#define ETH_DMA_ReceiveProcess_Closing ((uint32_t)0x000A0000) /* Running - closing descriptor */ +#define ETH_DMA_ReceiveProcess_Queuing ((uint32_t)0x000E0000) /* Running - queuing the recieve frame into host memory */ + +/* DMA overflow */ +#define ETH_DMA_Overflow_RxFIFOCounter ((uint32_t)0x10000000) /* Overflow bit for FIFO overflow counter */ +#define ETH_DMA_Overflow_MissedFrameCounter ((uint32_t)0x00010000) /* Overflow bit for missed frame counter */ + + +/********************************************************************************* +* Ethernet PMT defines +**********************************************************************************/ + +/* PMT flag */ +#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /* Wake-Up Frame Filter Register Poniter Reset */ +#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /* Wake-Up Frame Received */ +#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /* Magic Packet Received */ + +/********************************************************************************* +* Ethernet MMC defines +**********************************************************************************/ + +/* MMC TX interrupt flag */ +#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /* When Tx good frame counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /* When Tx good multi col counter reaches half the maximum value */ +#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /* When Tx good single col counter reaches half the maximum value */ + +/* MMC RX interrupt flag */ +#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /* When Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /* When Rx alignment error counter reaches half the maximum value */ +#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /* When Rx crc error counter reaches half the maximum value */ + + +/* MMC description */ +#define ETH_MMCCR ((uint32_t)0x00000100) /* MMC CR register */ +#define ETH_MMCRIR ((uint32_t)0x00000104) /* MMC RIR register */ +#define ETH_MMCTIR ((uint32_t)0x00000108) /* MMC TIR register */ +#define ETH_MMCRIMR ((uint32_t)0x0000010C) /* MMC RIMR register */ +#define ETH_MMCTIMR ((uint32_t)0x00000110) /* MMC TIMR register */ +#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /* MMC TGFSCCR register */ +#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /* MMC TGFMSCCR register */ +#define ETH_MMCTGFCR ((uint32_t)0x00000168) /* MMC TGFCR register */ +#define ETH_MMCRFCECR ((uint32_t)0x00000194) /* MMC RFCECR register */ +#define ETH_MMCRFAECR ((uint32_t)0x00000198) /* MMC RFAECR register */ +#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /* MMC RGUFCR register */ + + +/********************************************************************************* +* Ethernet PTP defines +**********************************************************************************/ + +/* PTP fine update method or coarse Update method */ +#define ETH_PTP_FineUpdate ((uint32_t)0x00000001) /* Fine Update method */ +#define ETH_PTP_CoarseUpdate ((uint32_t)0x00000000) /* Coarse Update method */ + + +/* PTP time stamp control */ +#define ETH_PTP_FLAG_TSARU ((uint32_t)0x00000020) /* Addend Register Update */ +#define ETH_PTP_FLAG_TSITE ((uint32_t)0x00000010) /* Time Stamp Interrupt Trigger */ +#define ETH_PTP_FLAG_TSSTU ((uint32_t)0x00000008) /* Time Stamp Update */ +#define ETH_PTP_FLAG_TSSTI ((uint32_t)0x00000004) /* Time Stamp Initialize */ + +/* PTP positive/negative time value */ +#define ETH_PTP_PositiveTime ((uint32_t)0x00000000) /* Positive time value */ +#define ETH_PTP_NegativeTime ((uint32_t)0x80000000) /* Negative time value */ + + +/******************************************************************************/ +/* */ +/* PTP Register */ +/* */ +/******************************************************************************/ +#define ETH_PTPTSCR ((uint32_t)0x00000700) /* PTP TSCR register */ +#define ETH_PTPSSIR ((uint32_t)0x00000704) /* PTP SSIR register */ +#define ETH_PTPTSHR ((uint32_t)0x00000708) /* PTP TSHR register */ +#define ETH_PTPTSLR ((uint32_t)0x0000070C) /* PTP TSLR register */ +#define ETH_PTPTSHUR ((uint32_t)0x00000710) /* PTP TSHUR register */ +#define ETH_PTPTSLUR ((uint32_t)0x00000714) /* PTP TSLUR register */ +#define ETH_PTPTSAR ((uint32_t)0x00000718) /* PTP TSAR register */ +#define ETH_PTPTTHR ((uint32_t)0x0000071C) /* PTP TTHR register */ +#define ETH_PTPTTLR ((uint32_t)0x00000720) /* PTP TTLR register */ + +#define ETH_DMASR_TSTS ((unsigned int)0x20000000) /* Time-stamp trigger status */ +#define ETH_DMASR_PMTS ((unsigned int)0x10000000) /* PMT status */ +#define ETH_DMASR_MMCS ((unsigned int)0x08000000) /* MMC status */ +#define ETH_DMASR_EBS ((unsigned int)0x03800000) /* Error bits status */ + #define ETH_DMASR_EBS_DescAccess ((unsigned int)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ + #define ETH_DMASR_EBS_ReadTransf ((unsigned int)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ + #define ETH_DMASR_EBS_DataTransfTx ((unsigned int)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMASR_TPS ((unsigned int)0x00700000) /* Transmit process state */ + #define ETH_DMASR_TPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ + #define ETH_DMASR_TPS_Fetching ((unsigned int)0x00100000) /* Running - fetching the Tx descriptor */ + #define ETH_DMASR_TPS_Waiting ((unsigned int)0x00200000) /* Running - waiting for status */ + #define ETH_DMASR_TPS_Reading ((unsigned int)0x00300000) /* Running - reading the data from host memory */ + #define ETH_DMASR_TPS_Suspended ((unsigned int)0x00600000) /* Suspended - Tx Descriptor unavailabe */ + #define ETH_DMASR_TPS_Closing ((unsigned int)0x00700000) /* Running - closing Rx descriptor */ +#define ETH_DMASR_RPS ((unsigned int)0x000E0000) /* Receive process state */ + #define ETH_DMASR_RPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ + #define ETH_DMASR_RPS_Fetching ((unsigned int)0x00020000) /* Running - fetching the Rx descriptor */ + #define ETH_DMASR_RPS_Waiting ((unsigned int)0x00060000) /* Running - waiting for packet */ + #define ETH_DMASR_RPS_Suspended ((unsigned int)0x00080000) /* Suspended - Rx Descriptor unavailable */ + #define ETH_DMASR_RPS_Closing ((unsigned int)0x000A0000) /* Running - closing descriptor */ + #define ETH_DMASR_RPS_Queuing ((unsigned int)0x000E0000) /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_NIS ((unsigned int)0x00010000) /* Normal interrupt summary */ +#define ETH_DMASR_AIS ((unsigned int)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMASR_ERS ((unsigned int)0x00004000) /* Early receive status */ +#define ETH_DMASR_FBES ((unsigned int)0x00002000) /* Fatal bus error status */ +#define ETH_DMASR_ETS ((unsigned int)0x00000400) /* Early transmit status */ +#define ETH_DMASR_RWTS ((unsigned int)0x00000200) /* Receive watchdog timeout status */ +#define ETH_DMASR_RPSS ((unsigned int)0x00000100) /* Receive process stopped status */ +#define ETH_DMASR_RBUS ((unsigned int)0x00000080) /* Receive buffer unavailable status */ +#define ETH_DMASR_RS ((unsigned int)0x00000040) /* Receive status */ +#define ETH_DMASR_TUS ((unsigned int)0x00000020) /* Transmit underflow status */ +#define ETH_DMASR_ROS ((unsigned int)0x00000010) /* Receive overflow status */ +#define ETH_DMASR_TJTS ((unsigned int)0x00000008) /* Transmit jabber timeout status */ +#define ETH_DMASR_TBUS ((unsigned int)0x00000004) /* Transmit buffer unavailable status */ +#define ETH_DMASR_TPSS ((unsigned int)0x00000002) /* Transmit process stopped status */ +#define ETH_DMASR_TS ((unsigned int)0x00000001) /* Transmit status */ + + +/******************************************************************************/ +/* */ +/* ETH MAC Register */ +/* */ +/******************************************************************************/ +#define ETH_MACCR_WD ((unsigned int)0x00800000) /* Watchdog disable */ +#define ETH_MACCR_JD ((unsigned int)0x00400000) /* Jabber disable */ +#define ETH_MACCR_IFG ((unsigned int)0x000E0000) /* Inter-frame gap */ +#define ETH_MACCR_IFG_96Bit ((unsigned int)0x00000000) /* Minimum IFG between frames during transmission is 96Bit */ + #define ETH_MACCR_IFG_88Bit ((unsigned int)0x00020000) /* Minimum IFG between frames during transmission is 88Bit */ + #define ETH_MACCR_IFG_80Bit ((unsigned int)0x00040000) /* Minimum IFG between frames during transmission is 80Bit */ + #define ETH_MACCR_IFG_72Bit ((unsigned int)0x00060000) /* Minimum IFG between frames during transmission is 72Bit */ + #define ETH_MACCR_IFG_64Bit ((unsigned int)0x00080000) /* Minimum IFG between frames during transmission is 64Bit */ + #define ETH_MACCR_IFG_56Bit ((unsigned int)0x000A0000) /* Minimum IFG between frames during transmission is 56Bit */ + #define ETH_MACCR_IFG_48Bit ((unsigned int)0x000C0000) /* Minimum IFG between frames during transmission is 48Bit */ + #define ETH_MACCR_IFG_40Bit ((unsigned int)0x000E0000) /* Minimum IFG between frames during transmission is 40Bit */ +#define ETH_MACCR_CSD ((unsigned int)0x00010000) /* Carrier sense disable (during transmission) */ +#define ETH_MACCR_FES ((unsigned int)0x00004000) /* Fast ethernet speed */ +#define ETH_MACCR_ROD ((unsigned int)0x00002000) /* Receive own disable */ +#define ETH_MACCR_LM ((unsigned int)0x00001000) /* loopback mode */ +#define ETH_MACCR_DM ((unsigned int)0x00000800) /* Duplex mode */ +#define ETH_MACCR_IPCO ((unsigned int)0x00000400) /* IP Checksum offload */ +#define ETH_MACCR_RD ((unsigned int)0x00000200) /* Retry disable */ +#define ETH_MACCR_APCS ((unsigned int)0x00000080) /* Automatic Pad/CRC stripping */ +#define ETH_MACCR_BL ((unsigned int)0x00000060) /* Back-off limit: random integer number (r) of slot time delays before reschedulinga transmission attempt during retries after a collision: 0 =< r <2^k */ + #define ETH_MACCR_BL_10 ((unsigned int)0x00000000) /* k = min (n, 10) */ + #define ETH_MACCR_BL_8 ((unsigned int)0x00000020) /* k = min (n, 8) */ + #define ETH_MACCR_BL_4 ((unsigned int)0x00000040) /* k = min (n, 4) */ + #define ETH_MACCR_BL_1 ((unsigned int)0x00000060) /* k = min (n, 1) */ +#define ETH_MACCR_DC ((unsigned int)0x00000010) /* Defferal check */ +#define ETH_MACCR_TE ((unsigned int)0x00000008) /* Transmitter enable */ +#define ETH_MACCR_RE ((unsigned int)0x00000004) /* Receiver enable */ + +#define ETH_MACFFR_RA ((unsigned int)0x80000000) /* Receive all */ +#define ETH_MACFFR_HPF ((unsigned int)0x00000400) /* Hash or perfect filter */ +#define ETH_MACFFR_SAF ((unsigned int)0x00000200) /* Source address filter enable */ +#define ETH_MACFFR_SAIF ((unsigned int)0x00000100) /* SA inverse filtering */ +#define ETH_MACFFR_PCF ((unsigned int)0x000000C0) /* Pass control frames: 3 cases */ + #define ETH_MACFFR_PCF_BlockAll ((unsigned int)0x00000040) /* MAC filters all control frames from reaching the application */ + #define ETH_MACFFR_PCF_ForwardAll ((unsigned int)0x00000080) /* MAC forwards all control frames to application even if they fail the Address Filter */ + #define ETH_MACFFR_PCF_ForwardPassedAddrFilter ((unsigned int)0x000000C0) /* MAC forwards control frames that pass the Address Filter. */ +#define ETH_MACFFR_BFD ((unsigned int)0x00000020) /* Broadcast frame disable */ +#define ETH_MACFFR_PAM ((unsigned int)0x00000010) /* Pass all mutlicast */ +#define ETH_MACFFR_DAIF ((unsigned int)0x00000008) /* DA Inverse filtering */ +#define ETH_MACFFR_HM ((unsigned int)0x00000004) /* Hash multicast */ +#define ETH_MACFFR_HU ((unsigned int)0x00000002) /* Hash unicast */ +#define ETH_MACFFR_PM ((unsigned int)0x00000001) /* Promiscuous mode */ + +#define ETH_MACHTHR_HTH ((unsigned int)0xFFFFFFFF) /* Hash table high */ +#define ETH_MACHTLR_HTL ((unsigned int)0xFFFFFFFF) /* Hash table low */ + +#define ETH_MACMIIAR_PA ((unsigned int)0x0000F800) /* Physical layer address */ +#define ETH_MACMIIAR_MR ((unsigned int)0x000007C0) /* MII register in the selected PHY */ +#define ETH_MACMIIAR_CR ((unsigned int)0x0000001C) /* CR clock range: 6 cases */ + #define ETH_MACMIIAR_CR_Div42 ((unsigned int)0x00000000) /* HCLK:60-100 MHz; MDC clock= HCLK/42 */ + #define ETH_MACMIIAR_CR_Div16 ((unsigned int)0x00000008) /* HCLK:20-35 MHz; MDC clock= HCLK/16 */ + #define ETH_MACMIIAR_CR_Div26 ((unsigned int)0x0000000C) /* HCLK:35-60 MHz; MDC clock= HCLK/26 */ +#define ETH_MACMIIAR_MW ((unsigned int)0x00000002) /* MII write */ +#define ETH_MACMIIAR_MB ((unsigned int)0x00000001) /* MII busy */ +#define ETH_MACMIIDR_MD ((unsigned int)0x0000FFFF) /* MII data: read/write data from/to PHY */ +#define ETH_MACFCR_PT ((unsigned int)0xFFFF0000) /* Pause time */ +#define ETH_MACFCR_ZQPD ((unsigned int)0x00000080) /* Zero-quanta pause disable */ +#define ETH_MACFCR_PLT ((unsigned int)0x00000030) /* Pause low threshold: 4 cases */ + #define ETH_MACFCR_PLT_Minus4 ((unsigned int)0x00000000) /* Pause time minus 4 slot times */ + #define ETH_MACFCR_PLT_Minus28 ((unsigned int)0x00000010) /* Pause time minus 28 slot times */ + #define ETH_MACFCR_PLT_Minus144 ((unsigned int)0x00000020) /* Pause time minus 144 slot times */ + #define ETH_MACFCR_PLT_Minus256 ((unsigned int)0x00000030) /* Pause time minus 256 slot times */ +#define ETH_MACFCR_UPFD ((unsigned int)0x00000008) /* Unicast pause frame detect */ +#define ETH_MACFCR_RFCE ((unsigned int)0x00000004) /* Receive flow control enable */ +#define ETH_MACFCR_TFCE ((unsigned int)0x00000002) /* Transmit flow control enable */ +#define ETH_MACFCR_FCBBPA ((unsigned int)0x00000001) /* Flow control busy/backpressure activate */ + +#define ETH_MACVLANTR_VLANTC ((unsigned int)0x00010000) /* 12-bit VLAN tag comparison */ +#define ETH_MACVLANTR_VLANTI ((unsigned int)0x0000FFFF) /* VLAN tag identifier (for receive frames) */ + +#define ETH_MACRWUFFR_D ((unsigned int)0xFFFFFFFF) /* Wake-up frame filter register data */ +/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers. +Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */ + +/* +Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask +Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask +Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask +Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask +Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - + RSVD - Filter1 Command - RSVD - Filter0 Command +Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset +Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16 +Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */ + +#define ETH_MACPMTCSR_WFFRPR ((unsigned int)0x80000000) /* Wake-Up Frame Filter Register Pointer Reset */ +#define ETH_MACPMTCSR_GU ((unsigned int)0x00000200) /* Global Unicast */ +#define ETH_MACPMTCSR_WFR ((unsigned int)0x00000040) /* Wake-Up Frame Received */ +#define ETH_MACPMTCSR_MPR ((unsigned int)0x00000020) /* Magic Packet Received */ +#define ETH_MACPMTCSR_WFE ((unsigned int)0x00000004) /* Wake-Up Frame Enable */ +#define ETH_MACPMTCSR_MPE ((unsigned int)0x00000002) /* Magic Packet Enable */ +#define ETH_MACPMTCSR_PD ((unsigned int)0x00000001) /* Power Down */ + +#define ETH_MACSR_TSTS ((unsigned int)0x00000200) /* Time stamp trigger status */ +#define ETH_MACSR_MMCTS ((unsigned int)0x00000040) /* MMC transmit status */ +#define ETH_MACSR_MMMCRS ((unsigned int)0x00000020) /* MMC receive status */ +#define ETH_MACSR_MMCS ((unsigned int)0x00000010) /* MMC status */ +#define ETH_MACSR_PMTS ((unsigned int)0x00000008) /* PMT status */ + +#define ETH_MACIMR_TSTIM ((unsigned int)0x00000200) /* Time stamp trigger interrupt mask */ +#define ETH_MACIMR_PMTIM ((unsigned int)0x00000008) /* PMT interrupt mask */ + +#define ETH_MACA0HR_MACA0H ((unsigned int)0x0000FFFF) /* MAC address0 high */ + +#define ETH_MACA0LR_MACA0L ((unsigned int)0xFFFFFFFF) /* MAC address0 low */ + +#define ETH_MACA1HR_AE ((unsigned int)0x80000000) /* Address enable */ +#define ETH_MACA1HR_SA ((unsigned int)0x40000000) /* Source address */ +#define ETH_MACA1HR_MBC ((unsigned int)0x3F000000) /* Mask byte control: bits to mask for comparison of the MAC Address bytes */ + #define ETH_MACA1HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA1HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA1HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA1HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA1HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA1HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [7:0] */ +#define ETH_MACA1HR_MACA1H ((unsigned int)0x0000FFFF) /* MAC address1 high */ + +#define ETH_MACA1LR_MACA1L ((unsigned int)0xFFFFFFFF) /* MAC address1 low */ + +#define ETH_MACA2HR_AE ((unsigned int)0x80000000) /* Address enable */ +#define ETH_MACA2HR_SA ((unsigned int)0x40000000) /* Source address */ +#define ETH_MACA2HR_MBC ((unsigned int)0x3F000000) /* Mask byte control */ + #define ETH_MACA2HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA2HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA2HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA2HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA2HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA2HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [70] */ + +#define ETH_MACA2HR_MACA2H ((unsigned int)0x0000FFFF) /* MAC address1 high */ +#define ETH_MACA2LR_MACA2L ((unsigned int)0xFFFFFFFF) /* MAC address2 low */ + +#define ETH_MACA3HR_AE ((unsigned int)0x80000000) /* Address enable */ +#define ETH_MACA3HR_SA ((unsigned int)0x40000000) /* Source address */ +#define ETH_MACA3HR_MBC ((unsigned int)0x3F000000) /* Mask byte control */ + #define ETH_MACA3HR_MBC_HBits15_8 ((unsigned int)0x20000000) /* Mask MAC Address high reg bits [15:8] */ + #define ETH_MACA3HR_MBC_HBits7_0 ((unsigned int)0x10000000) /* Mask MAC Address high reg bits [7:0] */ + #define ETH_MACA3HR_MBC_LBits31_24 ((unsigned int)0x08000000) /* Mask MAC Address low reg bits [31:24] */ + #define ETH_MACA3HR_MBC_LBits23_16 ((unsigned int)0x04000000) /* Mask MAC Address low reg bits [23:16] */ + #define ETH_MACA3HR_MBC_LBits15_8 ((unsigned int)0x02000000) /* Mask MAC Address low reg bits [15:8] */ + #define ETH_MACA3HR_MBC_LBits7_0 ((unsigned int)0x01000000) /* Mask MAC Address low reg bits [70] */ +#define ETH_MACA3HR_MACA3H ((unsigned int)0x0000FFFF) /* MAC address3 high */ +#define ETH_MACA3LR_MACA3L ((unsigned int)0xFFFFFFFF) /* MAC address3 low */ + +/******************************************************************************/ +/* */ +/* ETH MMC Register */ +/* */ +/******************************************************************************/ +#define ETH_MMCCR_MCFHP ((unsigned int)0x00000020) /* MMC counter Full-Half preset */ +#define ETH_MMCCR_MCP ((unsigned int)0x00000010) /* MMC counter preset */ +#define ETH_MMCCR_MCF ((unsigned int)0x00000008) /* MMC Counter Freeze */ +#define ETH_MMCCR_ROR ((unsigned int)0x00000004) /* Reset on Read */ +#define ETH_MMCCR_CSR ((unsigned int)0x00000002) /* Counter Stop Rollover */ +#define ETH_MMCCR_CR ((unsigned int)0x00000001) /* Counters Reset */ + +#define ETH_MMCRIR_RGUFS ((unsigned int)0x00020000) /* Set when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIR_RFAES ((unsigned int)0x00000040) /* Set when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIR_RFCES ((unsigned int)0x00000020) /* Set when Rx crc error counter reaches half the maximum value */ + +#define ETH_MMCTIR_TGFS ((unsigned int)0x00200000) /* Set when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFMSCS ((unsigned int)0x00008000) /* Set when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIR_TGFSCS ((unsigned int)0x00004000) /* Set when Tx good single col counter reaches half the maximum value */ + +#define ETH_MMCRIMR_RGUFM ((unsigned int)0x00020000) /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFAEM ((unsigned int)0x00000040) /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */ +#define ETH_MMCRIMR_RFCEM ((unsigned int)0x00000020) /* Mask the interrupt when Rx crc error counter reaches half the maximum value */ + +#define ETH_MMCTIMR_TGFM ((unsigned int)0x00200000) /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFMSCM ((unsigned int)0x00008000) /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */ +#define ETH_MMCTIMR_TGFSCM ((unsigned int)0x00004000) /* Mask the interrupt when Tx good single col counter reaches half the maximum value */ + +#define ETH_MMCTGFSCCR_TGFSCC ((unsigned int)0xFFFFFFFF) /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */ + +#define ETH_MMCTGFMSCCR_TGFMSCC ((unsigned int)0xFFFFFFFF) /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */ + +#define ETH_MMCTGFCR_TGFC ((unsigned int)0xFFFFFFFF) /* Number of good frames transmitted. */ + +#define ETH_MMCRFCECR_RFCEC ((unsigned int)0xFFFFFFFF) /* Number of frames received with CRC error. */ + +#define ETH_MMCRFAECR_RFAEC ((unsigned int)0xFFFFFFFF) /* Number of frames received with alignment (dribble) error */ + +#define ETH_MMCRGUFCR_RGUFC ((unsigned int)0xFFFFFFFF) /* Number of good unicast frames received. */ + + +/******************************************************************************/ +/* */ +/* ETH Precise Clock Protocol Register */ +/* */ +/******************************************************************************/ +#define ETH_PTPTSCR_TSCNT ((unsigned int)0x00030000) /* Time stamp clock node type */ +#define ETH_PTPTSSR_TSSMRME ((unsigned int)0x00008000) /* Time stamp snapshot for message relevant to master enable */ +#define ETH_PTPTSSR_TSSEME ((unsigned int)0x00004000) /* Time stamp snapshot for event message enable */ +#define ETH_PTPTSSR_TSSIPV4FE ((unsigned int)0x00002000) /* Time stamp snapshot for IPv4 frames enable */ +#define ETH_PTPTSSR_TSSIPV6FE ((unsigned int)0x00001000) /* Time stamp snapshot for IPv6 frames enable */ +#define ETH_PTPTSSR_TSSPTPOEFE ((unsigned int)0x00000800) /* Time stamp snapshot for PTP over ethernet frames enable */ +#define ETH_PTPTSSR_TSPTPPSV2E ((unsigned int)0x00000400) /* Time stamp PTP packet snooping for version2 format enable */ +#define ETH_PTPTSSR_TSSSR ((unsigned int)0x00000200) /* Time stamp Sub-seconds rollover */ +#define ETH_PTPTSSR_TSSARFE ((unsigned int)0x00000100) /* Time stamp snapshot for all received frames enable */ + +#define ETH_PTPTSCR_TSARU ((unsigned int)0x00000020) /* Addend register update */ +#define ETH_PTPTSCR_TSITE ((unsigned int)0x00000010) /* Time stamp interrupt trigger enable */ +#define ETH_PTPTSCR_TSSTU ((unsigned int)0x00000008) /* Time stamp update */ +#define ETH_PTPTSCR_TSSTI ((unsigned int)0x00000004) /* Time stamp initialize */ +#define ETH_PTPTSCR_TSFCU ((unsigned int)0x00000002) /* Time stamp fine or coarse update */ +#define ETH_PTPTSCR_TSE ((unsigned int)0x00000001) /* Time stamp enable */ + +#define ETH_PTPSSIR_STSSI ((unsigned int)0x000000FF) /* System time Sub-second increment value */ + +#define ETH_PTPTSHR_STS ((unsigned int)0xFFFFFFFF) /* System Time second */ + +#define ETH_PTPTSLR_STPNS ((unsigned int)0x80000000) /* System Time Positive or negative time */ +#define ETH_PTPTSLR_STSS ((unsigned int)0x7FFFFFFF) /* System Time sub-seconds */ + +#define ETH_PTPTSHUR_TSUS ((unsigned int)0xFFFFFFFF) /* Time stamp update seconds */ + +#define ETH_PTPTSLUR_TSUPNS ((unsigned int)0x80000000) /* Time stamp update Positive or negative time */ +#define ETH_PTPTSLUR_TSUSS ((unsigned int)0x7FFFFFFF) /* Time stamp update sub-seconds */ + +#define ETH_PTPTSAR_TSA ((unsigned int)0xFFFFFFFF) /* Time stamp addend */ + +#define ETH_PTPTTHR_TTSH ((unsigned int)0xFFFFFFFF) /* Target time stamp high */ + +#define ETH_PTPTTLR_TTSL ((unsigned int)0xFFFFFFFF) /* Target time stamp low */ + +#define ETH_PTPTSSR_TSTTR ((unsigned int)0x00000020) /* Time stamp target time reached */ +#define ETH_PTPTSSR_TSSO ((unsigned int)0x00000010) /* Time stamp seconds overflow */ + +/******************************************************************************/ +/* */ +/* ETH DMA Register */ +/* */ +/******************************************************************************/ +#define ETH_DMABMR_AAB ((unsigned int)0x02000000) /* Address-Aligned beats */ +#define ETH_DMABMR_FPM ((unsigned int)0x01000000) /* 4xPBL mode */ +#define ETH_DMABMR_USP ((unsigned int)0x00800000) /* Use separate PBL */ +#define ETH_DMABMR_RDP ((unsigned int)0x007E0000) /* RxDMA PBL */ + #define ETH_DMABMR_RDP_1Beat ((unsigned int)0x00020000) /* maximum number of beats to be transferred in one RxDMA transaction is 1 */ + #define ETH_DMABMR_RDP_2Beat ((unsigned int)0x00040000) /* maximum number of beats to be transferred in one RxDMA transaction is 2 */ + #define ETH_DMABMR_RDP_4Beat ((unsigned int)0x00080000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ + #define ETH_DMABMR_RDP_8Beat ((unsigned int)0x00100000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ + #define ETH_DMABMR_RDP_16Beat ((unsigned int)0x00200000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ + #define ETH_DMABMR_RDP_32Beat ((unsigned int)0x00400000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + #define ETH_DMABMR_RDP_4xPBL_4Beat ((unsigned int)0x01020000) /* maximum number of beats to be transferred in one RxDMA transaction is 4 */ + #define ETH_DMABMR_RDP_4xPBL_8Beat ((unsigned int)0x01040000) /* maximum number of beats to be transferred in one RxDMA transaction is 8 */ + #define ETH_DMABMR_RDP_4xPBL_16Beat ((unsigned int)0x01080000) /* maximum number of beats to be transferred in one RxDMA transaction is 16 */ + #define ETH_DMABMR_RDP_4xPBL_32Beat ((unsigned int)0x01100000) /* maximum number of beats to be transferred in one RxDMA transaction is 32 */ + #define ETH_DMABMR_RDP_4xPBL_64Beat ((unsigned int)0x01200000) /* maximum number of beats to be transferred in one RxDMA transaction is 64 */ + #define ETH_DMABMR_RDP_4xPBL_128Beat ((unsigned int)0x01400000) /* maximum number of beats to be transferred in one RxDMA transaction is 128 */ +#define ETH_DMABMR_FB ((unsigned int)0x00010000) /* Fixed Burst */ +#define ETH_DMABMR_RTPR ((unsigned int)0x0000C000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_1_1 ((unsigned int)0x00000000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_2_1 ((unsigned int)0x00004000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_3_1 ((unsigned int)0x00008000) /* Rx Tx priority ratio */ + #define ETH_DMABMR_RTPR_4_1 ((unsigned int)0x0000C000) /* Rx Tx priority ratio */ +#define ETH_DMABMR_PBL ((unsigned int)0x00003F00) /* Programmable burst length */ + #define ETH_DMABMR_PBL_1Beat ((unsigned int)0x00000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ + #define ETH_DMABMR_PBL_2Beat ((unsigned int)0x00000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ + #define ETH_DMABMR_PBL_4Beat ((unsigned int)0x00000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ + #define ETH_DMABMR_PBL_8Beat ((unsigned int)0x00000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ + #define ETH_DMABMR_PBL_16Beat ((unsigned int)0x00001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ + #define ETH_DMABMR_PBL_32Beat ((unsigned int)0x00002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + #define ETH_DMABMR_PBL_4xPBL_4Beat ((unsigned int)0x01000100) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ + #define ETH_DMABMR_PBL_4xPBL_8Beat ((unsigned int)0x01000200) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ + #define ETH_DMABMR_PBL_4xPBL_16Beat ((unsigned int)0x01000400) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ + #define ETH_DMABMR_PBL_4xPBL_32Beat ((unsigned int)0x01000800) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ + #define ETH_DMABMR_PBL_4xPBL_64Beat ((unsigned int)0x01001000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ + #define ETH_DMABMR_PBL_4xPBL_128Beat ((unsigned int)0x01002000) /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +#define ETH_DMABMR_EDE ((unsigned int)0x00000080) /* Enhanced Descriptor Enable */ +#define ETH_DMABMR_DSL ((unsigned int)0x0000007C) /* Descriptor Skip Length */ +#define ETH_DMABMR_DA ((unsigned int)0x00000002) /* DMA arbitration scheme */ +#define ETH_DMABMR_SR ((unsigned int)0x00000001) /* Software reset */ + +#define ETH_DMATPDR_TPD ((unsigned int)0xFFFFFFFF) /* Transmit poll demand */ + +#define ETH_DMARPDR_RPD ((unsigned int)0xFFFFFFFF) /* Receive poll demand */ + +#define ETH_DMARDLAR_SRL ((unsigned int)0xFFFFFFFF) /* Start of receive list */ + +#define ETH_DMATDLAR_STL ((unsigned int)0xFFFFFFFF) /* Start of transmit list */ + +#define ETH_DMASR_TSTS ((unsigned int)0x20000000) /* Time-stamp trigger status */ +#define ETH_DMASR_PMTS ((unsigned int)0x10000000) /* PMT status */ +#define ETH_DMASR_MMCS ((unsigned int)0x08000000) /* MMC status */ +#define ETH_DMASR_EBS ((unsigned int)0x03800000) /* Error bits status */ + #define ETH_DMASR_EBS_DescAccess ((unsigned int)0x02000000) /* Error bits 0-data buffer, 1-desc. access */ + #define ETH_DMASR_EBS_ReadTransf ((unsigned int)0x01000000) /* Error bits 0-write trnsf, 1-read transfr */ + #define ETH_DMASR_EBS_DataTransfTx ((unsigned int)0x00800000) /* Error bits 0-Rx DMA, 1-Tx DMA */ +#define ETH_DMASR_TPS ((unsigned int)0x00700000) /* Transmit process state */ + #define ETH_DMASR_TPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Tx Command issued */ + #define ETH_DMASR_TPS_Fetching ((unsigned int)0x00100000) /* Running - fetching the Tx descriptor */ + #define ETH_DMASR_TPS_Waiting ((unsigned int)0x00200000) /* Running - waiting for status */ + #define ETH_DMASR_TPS_Reading ((unsigned int)0x00300000) /* Running - reading the data from host memory */ + #define ETH_DMASR_TPS_Suspended ((unsigned int)0x00600000) /* Suspended - Tx Descriptor unavailabe */ + #define ETH_DMASR_TPS_Closing ((unsigned int)0x00700000) /* Running - closing Rx descriptor */ +#define ETH_DMASR_RPS ((unsigned int)0x000E0000) /* Receive process state */ + #define ETH_DMASR_RPS_Stopped ((unsigned int)0x00000000) /* Stopped - Reset or Stop Rx Command issued */ + #define ETH_DMASR_RPS_Fetching ((unsigned int)0x00020000) /* Running - fetching the Rx descriptor */ + #define ETH_DMASR_RPS_Waiting ((unsigned int)0x00060000) /* Running - waiting for packet */ + #define ETH_DMASR_RPS_Suspended ((unsigned int)0x00080000) /* Suspended - Rx Descriptor unavailable */ + #define ETH_DMASR_RPS_Closing ((unsigned int)0x000A0000) /* Running - closing descriptor */ + #define ETH_DMASR_RPS_Queuing ((unsigned int)0x000E0000) /* Running - queuing the recieve frame into host memory */ +#define ETH_DMASR_NIS ((unsigned int)0x00010000) /* Normal interrupt summary */ +#define ETH_DMASR_AIS ((unsigned int)0x00008000) /* Abnormal interrupt summary */ +#define ETH_DMASR_ERS ((unsigned int)0x00004000) /* Early receive status */ +#define ETH_DMASR_FBES ((unsigned int)0x00002000) /* Fatal bus error status */ +#define ETH_DMASR_ETS ((unsigned int)0x00000400) /* Early transmit status */ +#define ETH_DMASR_RWTS ((unsigned int)0x00000200) /* Receive watchdog timeout status */ +#define ETH_DMASR_RPSS ((unsigned int)0x00000100) /* Receive process stopped status */ +#define ETH_DMASR_RBUS ((unsigned int)0x00000080) /* Receive buffer unavailable status */ +#define ETH_DMASR_RS ((unsigned int)0x00000040) /* Receive status */ +#define ETH_DMASR_TUS ((unsigned int)0x00000020) /* Transmit underflow status */ +#define ETH_DMASR_ROS ((unsigned int)0x00000010) /* Receive overflow status */ +#define ETH_DMASR_TJTS ((unsigned int)0x00000008) /* Transmit jabber timeout status */ +#define ETH_DMASR_TBUS ((unsigned int)0x00000004) /* Transmit buffer unavailable status */ +#define ETH_DMASR_TPSS ((unsigned int)0x00000002) /* Transmit process stopped status */ +#define ETH_DMASR_TS ((unsigned int)0x00000001) /* Transmit status */ + +#define ETH_DMAOMR_DTCEFD ((unsigned int)0x04000000) /* Disable Dropping of TCP/IP checksum error frames */ +#define ETH_DMAOMR_RSF ((unsigned int)0x02000000) /* Receive store and forward */ +#define ETH_DMAOMR_DFRF ((unsigned int)0x01000000) /* Disable flushing of received frames */ +#define ETH_DMAOMR_TSF ((unsigned int)0x00200000) /* Transmit store and forward */ +#define ETH_DMAOMR_FTF ((unsigned int)0x00100000) /* Flush transmit FIFO */ +#define ETH_DMAOMR_TTC ((unsigned int)0x0001C000) /* Transmit threshold control */ + #define ETH_DMAOMR_TTC_64Bytes ((unsigned int)0x00000000) /* threshold level of the MTL Transmit FIFO is 64 Bytes */ + #define ETH_DMAOMR_TTC_128Bytes ((unsigned int)0x00004000) /* threshold level of the MTL Transmit FIFO is 128 Bytes */ + #define ETH_DMAOMR_TTC_192Bytes ((unsigned int)0x00008000) /* threshold level of the MTL Transmit FIFO is 192 Bytes */ + #define ETH_DMAOMR_TTC_256Bytes ((unsigned int)0x0000C000) /* threshold level of the MTL Transmit FIFO is 256 Bytes */ + #define ETH_DMAOMR_TTC_40Bytes ((unsigned int)0x00010000) /* threshold level of the MTL Transmit FIFO is 40 Bytes */ + #define ETH_DMAOMR_TTC_32Bytes ((unsigned int)0x00014000) /* threshold level of the MTL Transmit FIFO is 32 Bytes */ + #define ETH_DMAOMR_TTC_24Bytes ((unsigned int)0x00018000) /* threshold level of the MTL Transmit FIFO is 24 Bytes */ + #define ETH_DMAOMR_TTC_16Bytes ((unsigned int)0x0001C000) /* threshold level of the MTL Transmit FIFO is 16 Bytes */ +#define ETH_DMAOMR_ST ((unsigned int)0x00002000) /* Start/stop transmission command */ +#define ETH_DMAOMR_FEF ((unsigned int)0x00000080) /* Forward error frames */ +#define ETH_DMAOMR_FUGF ((unsigned int)0x00000040) /* Forward undersized good frames */ +#define ETH_DMAOMR_RTC ((unsigned int)0x00000018) /* receive threshold control */ + #define ETH_DMAOMR_RTC_64Bytes ((unsigned int)0x00000000) /* threshold level of the MTL Receive FIFO is 64 Bytes */ + #define ETH_DMAOMR_RTC_32Bytes ((unsigned int)0x00000008) /* threshold level of the MTL Receive FIFO is 32 Bytes */ + #define ETH_DMAOMR_RTC_96Bytes ((unsigned int)0x00000010) /* threshold level of the MTL Receive FIFO is 96 Bytes */ + #define ETH_DMAOMR_RTC_128Bytes ((unsigned int)0x00000018) /* threshold level of the MTL Receive FIFO is 128 Bytes */ +#define ETH_DMAOMR_OSF ((unsigned int)0x00000004) /* operate on second frame */ +#define ETH_DMAOMR_SR ((unsigned int)0x00000002) /* Start/stop receive */ + +#define ETH_DMAIER_NISE ((unsigned int)0x00010000) /* Normal interrupt summary enable */ +#define ETH_DMAIER_AISE ((unsigned int)0x00008000) /* Abnormal interrupt summary enable */ +#define ETH_DMAIER_ERIE ((unsigned int)0x00004000) /* Early receive interrupt enable */ +#define ETH_DMAIER_FBEIE ((unsigned int)0x00002000) /* Fatal bus error interrupt enable */ +#define ETH_DMAIER_ETIE ((unsigned int)0x00000400) /* Early transmit interrupt enable */ +#define ETH_DMAIER_RWTIE ((unsigned int)0x00000200) /* Receive watchdog timeout interrupt enable */ +#define ETH_DMAIER_RPSIE ((unsigned int)0x00000100) /* Receive process stopped interrupt enable */ +#define ETH_DMAIER_RBUIE ((unsigned int)0x00000080) /* Receive buffer unavailable interrupt enable */ +#define ETH_DMAIER_RIE ((unsigned int)0x00000040) /* Receive interrupt enable */ +#define ETH_DMAIER_TUIE ((unsigned int)0x00000020) /* Transmit Underflow interrupt enable */ +#define ETH_DMAIER_ROIE ((unsigned int)0x00000010) /* Receive Overflow interrupt enable */ +#define ETH_DMAIER_TJTIE ((unsigned int)0x00000008) /* Transmit jabber timeout interrupt enable */ +#define ETH_DMAIER_TBUIE ((unsigned int)0x00000004) /* Transmit buffer unavailable interrupt enable */ +#define ETH_DMAIER_TPSIE ((unsigned int)0x00000002) /* Transmit process stopped interrupt enable */ +#define ETH_DMAIER_TIE ((unsigned int)0x00000001) /* Transmit interrupt enable */ + +#define ETH_DMAMFBOCR_OFOC ((unsigned int)0x10000000) /* Overflow bit for FIFO overflow counter */ +#define ETH_DMAMFBOCR_MFA ((unsigned int)0x0FFE0000) /* Number of frames missed by the application */ +#define ETH_DMAMFBOCR_OMFC ((unsigned int)0x00010000) /* Overflow bit for missed frame counter */ +#define ETH_DMAMFBOCR_MFC ((unsigned int)0x0000FFFF) /* Number of frames missed by the controller */ + +#define ETH_DMACHTDR_HTDAP ((unsigned int)0xFFFFFFFF) /* Host transmit descriptor address pointer */ +#define ETH_DMACHRDR_HRDAP ((unsigned int)0xFFFFFFFF) /* Host receive descriptor address pointer */ +#define ETH_DMACHTBAR_HTBAP ((unsigned int)0xFFFFFFFF) /* Host transmit buffer address pointer */ +#define ETH_DMACHRBAR_HRBAP ((unsigned int)0xFFFFFFFF) /* Host receive buffer address pointer */ + + +#define ETH_MAC_ADDR_HBASE (ETH_MAC_BASE + 0x40) /* ETHERNET MAC address high offset */ +#define ETH_MAC_ADDR_LBASE (ETH_MAC_BASE + 0x44) /* ETHERNET MAC address low offset */ + +/* ETHERNET MACMIIAR register Mask */ +#define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3) + +/* ETHERNET MACCR register Mask */ +#define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F) + +/* ETHERNET MACFCR register Mask */ +#define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41) + +/* ETHERNET DMAOMR register Mask */ +#define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23) + +/* ETHERNET Remote Wake-up frame register length */ +#define ETH_WAKEUP_REGISTER_LENGTH 8 + +/* ETHERNET Missed frames counter Shift */ +#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17 + +/* ETHERNET DMA Tx descriptors Collision Count Shift */ +#define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3 + +/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ +#define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16 + +/* ETHERNET DMA Rx descriptors Frame Length Shift */ +#define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16 + +/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ +#define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16 + +/* ETHERNET errors */ +#define ETH_ERROR ((uint32_t)0) +#define ETH_SUCCESS ((uint32_t)1) + + +void ETH_DeInit(void); +void ETH_StructInit(ETH_InitTypeDef* ETH_InitStruct); +void ETH_SoftwareReset(void); +FlagStatus ETH_GetSoftwareResetStatus(void); +FlagStatus ETH_GetlinkStaus (void); +void ETH_Start(void); +uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength); +void delay_clk (uint32_t nCount); +void printf_dmasr (void); +void print_dmasr_tbus(void); +void print_dmasr_rps(void); +void print_dmasr_tps(void); +uint32_t ETH_HandleRxPkt(uint8_t *ppkt); +uint32_t ETH_GetRxPktSize(void); +void ETH_DropRxPkt(void); +uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg); +uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue); +uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState); + +void ETH_MACTransmissionCmd(FunctionalState NewState); +void ETH_MACReceptionCmd(FunctionalState NewState); +FlagStatus ETH_GetFlowControlBusyStatus(void); +void ETH_InitiatePauseControlFrame(void); +void ETH_BackPressureActivationCmd(FunctionalState NewState); +FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG); +ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT); +void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState); +void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr); +void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr); +void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState); +void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter); +void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte); + +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount); +void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount); +FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag); +uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc); +void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc); +void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment); +void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum); +void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState); +void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2); +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); +void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount); +FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag); +void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc); +uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc); +void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState); +uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer); + +FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG); +void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG); +ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT); +void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT); +uint32_t ETH_GetTransmitProcessState(void); +uint32_t ETH_GetReceiveProcessState(void); +void ETH_FlushTransmitFIFO(void); +FlagStatus ETH_GetFlushTransmitFIFOStatus(void); +void ETH_DMATransmissionCmd(FunctionalState NewState); +void ETH_DMAReceptionCmd(FunctionalState NewState); +void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState); +FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow); +uint32_t ETH_GetRxOverflowMissedFrameCounter(void); +uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void); +uint32_t ETH_GetCurrentTxDescStartAddress(void); +uint32_t ETH_GetCurrentRxDescStartAddress(void); +uint32_t ETH_GetCurrentTxBufferAddress(void); +uint32_t ETH_GetCurrentRxBufferAddress(void); +void ETH_ResumeDMATransmission(void); +void ETH_ResumeDMAReception(void); + +void ETH_ResetWakeUpFrameFilterRegisterPointer(void); +void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer); +void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState); +FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG); +void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState); +void ETH_MagicPacketDetectionCmd(FunctionalState NewState); +void ETH_PowerDownCmd(FunctionalState NewState); + +void ETH_MMCCounterFreezeCmd(FunctionalState NewState); +void ETH_MMCResetOnReadCmd(FunctionalState NewState); +void ETH_MMCCounterRolloverCmd(FunctionalState NewState); +void ETH_MMCCountersReset(void); +void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState); +ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT); +uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg); + +uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab); +uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab); +void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount); +void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); +void ETH_EnablePTPTimeStampAddend(void); +void ETH_EnablePTPTimeStampInterruptTrigger(void); +void ETH_EnablePTPTimeStampUpdate(void); +void ETH_InitializePTPTimeStamp(void); +void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod); +void ETH_PTPTimeStampCmd(FunctionalState NewState); +FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG); +void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue); +void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue); +void ETH_SetPTPTimeStampAddend(uint32_t Value); +void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue); +uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg); +void RGMII_TXC_Delay(uint8_t clock_polarity,uint8_t delay_time); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Peripheral/inc/ch32v30x_exti.h b/Peripheral/inc/ch32v30x_exti.h new file mode 100644 index 0000000..1e65983 --- /dev/null +++ b/Peripheral/inc/ch32v30x_exti.h @@ -0,0 +1,92 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_exti.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* EXTI firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_EXTI_H +#define __CH32V30x_EXTI_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* EXTI mode enumeration */ +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +}EXTIMode_TypeDef; + +/* EXTI Trigger enumeration */ +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +}EXTITrigger_TypeDef; + +/* EXTI Init Structure definition */ +typedef struct +{ + uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. + This parameter can be any combination of @ref EXTI_Lines */ + + EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTIMode_TypeDef */ + + FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ +}EXTI_InitTypeDef; + + +/* EXTI_Lines */ +#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */ +#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */ +#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */ +#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */ +#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */ +#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */ +#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */ +#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */ +#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */ +#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */ +#define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */ +#define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */ +#define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */ +#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */ +#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */ +#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */ +#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */ +#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */ +#define EXTI_Line18 ((uint32_t)0x40000) /* External interrupt line 18 Connected to the USBD/USBFS OTG + Wakeup from suspend event */ +#define EXTI_Line19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the Ethernet Wakeup event */ +#define EXTI_Line20 ((uint32_t)0x100000) /* External interrupt line 20 Connected to the USBHS Wakeup event */ + +void EXTI_DeInit(void); +void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct); +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line); +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line); +void EXTI_ClearFlag(uint32_t EXTI_Line); +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line); +void EXTI_ClearITPendingBit(uint32_t EXTI_Line); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Peripheral/inc/ch32v30x_flash.h b/Peripheral/inc/ch32v30x_flash.h new file mode 100644 index 0000000..bac3871 --- /dev/null +++ b/Peripheral/inc/ch32v30x_flash.h @@ -0,0 +1,148 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_flash.h +* Author : WCH +* Version : V1.0.0 +* Date : 2024/05/24 +* Description : This file contains all the functions prototypes for the FLASH +* firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_FLASH_H +#define __CH32V30x_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* FLASH Status */ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERROR_PG, + FLASH_ERROR_WRP, + FLASH_COMPLETE, + FLASH_TIMEOUT, + FLASH_OP_RANGE_ERROR = 0xFD, + FLASH_ALIGN_ERROR = 0xFE, + FLASH_ADR_RANGE_ERROR = 0xFF, +}FLASH_Status; + + +/* Write Protect */ +#define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of setor 0 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of setor 1 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of setor 2 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of setor 3 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of setor 4 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of setor 5 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of setor 6 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of setor 7 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of setor 8 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of setor 9 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of setor 10 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of setor 11 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of setor 12 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of setor 13 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of setor 14 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of setor 15 ,4K bytes/sector */ +#define FLASH_WRProt_Sectorint16_t ((uint32_t)0x00010000) /* Write protection of setor 16 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of setor 17 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of setor 18 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of setor 19 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of setor 20 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of setor 21 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of setor 22 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of setor 23 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of setor 24 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of setor 25 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of setor 26 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of setor 27 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of setor 28 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of setor 29 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of setor 30 ,4K bytes/sector */ +#define FLASH_WRProt_Sectors31to127 ((uint32_t)0x80000000) /* Write protection of page 31 to 127 */ + +#define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */ + +/* Option_Bytes_IWatchdog */ +#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ +#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ + +/* Option_Bytes_nRST_STOP */ +#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ +#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ + +/* Option_Bytes_nRST_STDBY */ +#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ +#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ + +/* FLASH_Interrupts */ +#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ +#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ +#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */ +#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */ + +/* FLASH_Flags */ +#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ +#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ +#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ +#define FLASH_FLAG_OPTERR ((uint32_t)0x80000001) /* FLASH Option Byte error flag */ + +#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/ +#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */ +#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */ + +/* FLASH_Access_CLK */ +#define FLASH_Access_SYSTEM_HALF ((uint32_t)0x00000000) /* FLASH Access Clock = SYSTEM/2 */ +#define FLASH_Access_SYSTEM ((uint32_t)0x02000000) /* FLASH Access Clock = SYSTEM */ + + +/*Functions used for all devices*/ +void FLASH_Unlock(void); +void FLASH_Lock(void); +FLASH_Status FLASH_ErasePage(uint32_t Page_Address); +FLASH_Status FLASH_EraseAllPages(void); +FLASH_Status FLASH_EraseOptionBytes(void); +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data); +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data); +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data); +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors); +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState); +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY); +uint32_t FLASH_GetUserOptionByte(void); +uint32_t FLASH_GetWriteProtectionOptionByte(void); +FlagStatus FLASH_GetReadOutProtectionStatus(void); +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState); +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG); +void FLASH_ClearFlag(uint32_t FLASH_FLAG); +FLASH_Status FLASH_GetStatus(void); +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout); +void FLASH_Unlock_Fast(void); +void FLASH_Lock_Fast(void); +void FLASH_ErasePage_Fast(uint32_t Page_Address); +void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address); +void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t* pbuf); +void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK); +void FLASH_Enhance_Mode(FunctionalState NewState); + +/* New function used for all devices */ +void FLASH_UnlockBank1(void); +void FLASH_LockBank1(void); +FLASH_Status FLASH_EraseAllBank1Pages(void); +FLASH_Status FLASH_GetBank1Status(void); +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout); +FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length); +FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length); + +#ifdef __cplusplus +} +#endif + + +#endif + diff --git a/Peripheral/inc/ch32v30x_fsmc.h b/Peripheral/inc/ch32v30x_fsmc.h new file mode 100644 index 0000000..be50861 --- /dev/null +++ b/Peripheral/inc/ch32v30x_fsmc.h @@ -0,0 +1,268 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_fsmc.h +* Author : WCH +* Version : V1.0.1 +* Date : 2025/03/06 +* Description : This file contains all the functions prototypes for the FSMC +* firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_FSMC_H +#define __CH32V30x_FSMC_H + +#ifdef __cplusplus + extern "C" { +#endif + + +#include "ch32v30x.h" + + +/* FSMC Init structure definition */ +typedef struct +{ + uint32_t FSMC_AddressSetupTime; /* Defines the number of HCLK cycles to configure + the duration of the address setup time. + This parameter can be a value between 0 and 0xF. + @note: It is not used with synchronous NOR Flash memories. */ + + uint32_t FSMC_AddressHoldTime; /* Defines the number of HCLK cycles to configure + the duration of the address hold time. + This parameter can be a value between 0 and 0xF. + @note: It is not used with synchronous NOR Flash memories.*/ + + uint32_t FSMC_DataSetupTime; /* Defines the number of HCLK cycles to configure + the duration of the data setup time. + This parameter can be a value between 0 and 0xFF. + @note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */ + + uint32_t FSMC_BusTurnAroundDuration; /* Defines the number of HCLK cycles to configure + the duration of the bus turnaround. + This parameter can be a value between 0 and 0xF. + @note: It is only used for multiplexed NOR Flash memories. */ + + uint32_t FSMC_CLKDivision; /* Defines the period of CLK clock output signal, expressed in number of HCLK cycles. + This parameter can be a value between 1 and 0xF. + @note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */ + + uint32_t FSMC_DataLatency; /* Defines the number of memory clock cycles to issue + to the memory before getting the first data. + The value of this parameter depends on the memory type as shown below: + - It must be set to 0 in case of a CRAM + - It is don't care in asynchronous NOR, SRAM or ROM accesses + - It may assume a value between 0 and 0xF in NOR Flash memories + with synchronous burst mode enable */ + + uint32_t FSMC_AccessMode; /* Specifies the asynchronous access mode. + This parameter can be a value of @ref FSMC_Access_Mode */ +}FSMC_NORSRAMTimingInitTypeDef; + + +typedef struct +{ + uint32_t FSMC_Bank; /* Specifies the NOR/SRAM memory bank that will be used. + This parameter can be a value of @ref FSMC_NORSRAM_Bank */ + + uint32_t FSMC_DataAddressMux; /* Specifies whether the address and data values are + multiplexed on the databus or not. + This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */ + + uint32_t FSMC_MemoryType; /* Specifies the type of external memory attached to + the corresponding memory bank. + This parameter can be a value of @ref FSMC_Memory_Type */ + + uint32_t FSMC_MemoryDataWidth; /* Specifies the external memory device width. + This parameter can be a value of @ref FSMC_Data_Width */ + + uint32_t FSMC_BurstAccessMode; /* Enables or disables the burst access mode for Flash memory, + valid only with synchronous burst Flash memories. + This parameter can be a value of @ref FSMC_Burst_Access_Mode */ + + uint32_t FSMC_AsynchronousWait; /* Enables or disables wait signal during asynchronous transfers, + valid only with asynchronous Flash memories. + This parameter can be a value of @ref FSMC_AsynchronousWait */ + + uint32_t FSMC_WaitSignalPolarity; /* Specifies the wait signal polarity, valid only when accessing + the Flash memory in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */ + + uint32_t FSMC_WaitSignalActive; /* Specifies if the wait signal is asserted by the memory one + clock cycle before the wait state or during the wait state, + valid only when accessing memories in burst mode. + This parameter can be a value of @ref FSMC_Wait_Timing */ + + uint32_t FSMC_WriteOperation; /* Enables or disables the write operation in the selected bank by the FSMC. + This parameter can be a value of @ref FSMC_Write_Operation */ + + uint32_t FSMC_WaitSignal; /* Enables or disables the wait-state insertion via wait + signal, valid for Flash memory access in burst mode. + This parameter can be a value of @ref FSMC_Wait_Signal */ + + uint32_t FSMC_ExtendedMode; /* Enables or disables the extended mode. + This parameter can be a value of @ref FSMC_Extended_Mode */ + + uint32_t FSMC_WriteBurst; /* Enables or disables the write burst operation. + This parameter can be a value of @ref FSMC_Write_Burst */ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /* Timing Parameters for write and read access if the ExtendedMode is not used*/ + + FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /* Timing Parameters for write access if the ExtendedMode is used*/ +}FSMC_NORSRAMInitTypeDef; + + +typedef struct +{ + uint32_t FSMC_SetupTime; /* Defines the number of HCLK cycles to setup address before + the command assertion for NAND-Flash read or write access + to common/Attribute or I/O memory space (depending on + the memory space timing to be configured). + This parameter can be a value between 0 and 0xFF.*/ + + uint32_t FSMC_WaitSetupTime; /* Defines the minimum number of HCLK cycles to assert the + command for NAND-Flash read or write access to + common/Attribute or I/O memory space (depending on the + memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HoldSetupTime; /* Defines the number of HCLK clock cycles to hold address + (and data for write access) after the command deassertion + for NAND-Flash read or write access to common/Attribute + or I/O memory space (depending on the memory space timing + to be configured). + This parameter can be a number between 0x00 and 0xFF */ + + uint32_t FSMC_HiZSetupTime; /* Defines the number of HCLK clock cycles during which the + databus is kept in HiZ after the start of a NAND-Flash + write access to common/Attribute or I/O memory space (depending + on the memory space timing to be configured). + This parameter can be a number between 0x00 and 0xFF */ +}FSMC_NAND_PCCARDTimingInitTypeDef; + + +typedef struct +{ + uint32_t FSMC_Bank; /* Specifies the NAND memory bank that will be used. + This parameter can be a value of @ref FSMC_NAND_Bank */ + + uint32_t FSMC_Waitfeature; /* Enables or disables the Wait feature for the NAND Memory Bank. + This parameter can be any value of @ref FSMC_Wait_feature */ + + uint32_t FSMC_MemoryDataWidth; /* Specifies the external memory device width. + This parameter can be any value of @ref FSMC_Data_Width */ + + uint32_t FSMC_ECC; /* Enables or disables the ECC computation. + This parameter can be any value of @ref FSMC_ECC */ + + uint32_t FSMC_ECCPageSize; /* Defines the page size for the extended ECC. + This parameter can be any value of @ref FSMC_ECC_Page_Size */ + + uint32_t FSMC_TCLRSetupTime; /* Defines the number of HCLK cycles to configure the + delay between CLE low and RE low. + This parameter can be a value between 0 and 0xFF. */ + + uint32_t FSMC_TARSetupTime; /* Defines the number of HCLK cycles to configure the + delay between ALE low and RE low. + This parameter can be a number between 0x0 and 0xFF */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /* FSMC Common Space Timing */ + + FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /* FSMC Attribute Space Timing */ +}FSMC_NANDInitTypeDef; + + +/* FSMC_NORSRAM_Bank */ +#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000) + +/* FSMC_NAND_Bank */ +#define FSMC_Bank2_NAND ((uint32_t)0x00000010) + +/* FSMC_Data_Address_Bus_Multiplexing */ +#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000) +#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002) + +/* FSMC_Memory_Type */ +#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000) +#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004) +#define FSMC_MemoryType_NOR ((uint32_t)0x00000008) + +/* FSMC_Data_Width */ +#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000) +#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010) + +/* FSMC_Burst_Access_Mode */ +#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000) +#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100) + +/* FSMC_AsynchronousWait */ +#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000) +#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000) + +/* FSMC_Wait_Signal_Polarity */ +#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000) +#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200) + +/* FSMC_Wait_Timing */ +#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000) +#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800) + +/* FSMC_Write_Operation */ +#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000) +#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000) + +/* FSMC_Wait_Signal */ +#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000) +#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000) + +/* FSMC_Extended_Mode */ +#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000) +#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000) + +/* FSMC_Write_Burst */ +#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000) +#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000) + +/* FSMC_Access_Mode */ +#define FSMC_AccessMode_A ((uint32_t)0x00000000) +#define FSMC_AccessMode_B ((uint32_t)0x10000000) +#define FSMC_AccessMode_C ((uint32_t)0x20000000) +#define FSMC_AccessMode_D ((uint32_t)0x30000000) + +/* FSMC_Wait_feature */ +#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000) +#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002) + +/* FSMC_ECC */ +#define FSMC_ECC_Disable ((uint32_t)0x00000000) +#define FSMC_ECC_Enable ((uint32_t)0x00000040) + +/* FSMC_ECC_Page_Size */ +#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000) +#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000) +#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000) +#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000) +#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000) +#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000) + +#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040) + + +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank); +void FSMC_NANDDeInit(uint32_t FSMC_Bank); +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct); +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct); +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState); +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState); +uint32_t FSMC_GetECC(uint32_t FSMC_Bank); +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Peripheral/inc/ch32v30x_gpio.h b/Peripheral/inc/ch32v30x_gpio.h new file mode 100644 index 0000000..f261140 --- /dev/null +++ b/Peripheral/inc/ch32v30x_gpio.h @@ -0,0 +1,196 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_gpio.h +* Author : WCH +* Version : V1.0.1 +* Date : 2025/04/09 +* Description : This file contains all the functions prototypes for the +* GPIO firmware library. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_GPIO_H +#define __CH32V30x_GPIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* Output Maximum frequency selection */ +typedef enum +{ + GPIO_Speed_10MHz = 1, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +}GPIOSpeed_TypeDef; + +/* Configuration Mode enumeration */ +typedef enum +{ GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +}GPIOMode_TypeDef; + +/* GPIO Init structure definition */ +typedef struct +{ + uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ +}GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +}BitAction; + +/* GPIO_pins_define */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ + +/* GPIO_Remap_define */ +/* PCFR1 */ +#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */ +#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */ +#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /* USART1 Alternate Function mapping low bit */ +#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /* USART2 Alternate Function mapping */ +#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /* USART3 Partial Alternate Function mapping */ +#define GPIO_PartialRemap1_USART3 ((uint32_t)0x00140020) /* USART3 Partial1 Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */ +#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */ +#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */ +#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */ +#define GPIO_Remap_PD0PD1 ((uint32_t)0x00008000) /* PD0 and PD1 Alternate Function mapping */ +#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */ +#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_ETH ((uint32_t)0x00200020) /* Ethernet remapping (only for Connectivity line devices) */ +#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /* CAN2 remapping (only for Connectivity line devices) */ +#define GPIO_Remap_MII_RMII_SEL ((uint32_t)0x00200080) /* MII or RMII selection */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled */ +#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /* SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */ +#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected + to TIM2 Internal Trigger 1 for calibration + (only for Connectivity line devices) */ +#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /* Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */ +#define GPIO_Remap_PD01 GPIO_Remap_PD0PD1 + +/* PCFR2 */ +#define GPIO_Remap_TIM8 ((uint32_t)0x80000004) /* TIM8 Alternate Function mapping */ +#define GPIO_PartialRemap_TIM9 ((uint32_t)0x80130008) /* TIM9 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM9 ((uint32_t)0x80130010) /* TIM9 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM10 ((uint32_t)0x80150020) /* TIM10 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM10 ((uint32_t)0x80150040) /* TIM10 Full Alternate Function mapping */ +#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /* FSMC_NADV Alternate Function mapping */ +#define GPIO_PartialRemap_USART4 ((uint32_t)0x80300001) /* USART4 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART4 ((uint32_t)0x80300002) /* USART4 Full Alternate Function mapping */ +#define GPIO_PartialRemap_USART5 ((uint32_t)0x80320004) /* USART5 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART5 ((uint32_t)0x80320008) /* USART5 Full Alternate Function mapping */ +#define GPIO_PartialRemap_USART6 ((uint32_t)0x80340010) /* USART6 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART6 ((uint32_t)0x80340020) /* USART6 Full Alternate Function mapping */ +#define GPIO_PartialRemap_USART7 ((uint32_t)0x80360040) /* USART7 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART7 ((uint32_t)0x80360080) /* USART7 Full Alternate Function mapping */ +#define GPIO_PartialRemap_USART8 ((uint32_t)0x80380100) /* USART8 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART8 ((uint32_t)0x80380200) /* USART8 Full Alternate Function mapping */ +#define GPIO_Remap_USART1_HighBit ((uint32_t)0x80200400) /* USART1 Alternate Function mapping high bit */ + + +/* GPIO_Port_Sources */ +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) +#define GPIO_PortSourceGPIOE ((uint8_t)0x04) + +/* GPIO_Pin_sources */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +/* Ethernet_Media_Interface */ +#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000) +#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001) + + +void GPIO_DeInit(GPIO_TypeDef* GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx); +void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin); +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_EventOutputCmd(FunctionalState NewState); +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + diff --git a/Peripheral/inc/ch32v30x_i2c.h b/Peripheral/inc/ch32v30x_i2c.h new file mode 100644 index 0000000..7b4b1a2 --- /dev/null +++ b/Peripheral/inc/ch32v30x_i2c.h @@ -0,0 +1,439 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_i2c.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* I2C firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_I2C_H +#define __CH32V30x_I2C_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* I2C Init structure definition */ +typedef struct +{ + uint32_t I2C_ClockSpeed; /* Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz */ + + uint16_t I2C_Mode; /* Specifies the I2C mode. + This parameter can be a value of @ref I2C_mode */ + + uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */ + + uint16_t I2C_OwnAddress1; /* Specifies the first device own address. + This parameter can be a 7-bit or 10-bit address. */ + + uint16_t I2C_Ack; /* Enables or disables the acknowledgement. + This parameter can be a value of @ref I2C_acknowledgement */ + + uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged. + This parameter can be a value of @ref I2C_acknowledged_address */ +}I2C_InitTypeDef; + +/* I2C_mode */ +#define I2C_Mode_I2C ((uint16_t)0x0000) +#define I2C_Mode_SMBusDevice ((uint16_t)0x0002) +#define I2C_Mode_SMBusHost ((uint16_t)0x000A) + +/* I2C_duty_cycle_in_fast_mode */ +#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */ + +/* I2C_acknowledgement */ +#define I2C_Ack_Enable ((uint16_t)0x0400) +#define I2C_Ack_Disable ((uint16_t)0x0000) + +/* I2C_transfer_direction */ +#define I2C_Direction_Transmitter ((uint8_t)0x00) +#define I2C_Direction_Receiver ((uint8_t)0x01) + +/* I2C_acknowledged_address */ +#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000) +#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000) + +/* I2C_registers */ +#define I2C_Register_CTLR1 ((uint8_t)0x00) +#define I2C_Register_CTLR2 ((uint8_t)0x04) +#define I2C_Register_OADDR1 ((uint8_t)0x08) +#define I2C_Register_OADDR2 ((uint8_t)0x0C) +#define I2C_Register_DATAR ((uint8_t)0x10) +#define I2C_Register_STAR1 ((uint8_t)0x14) +#define I2C_Register_STAR2 ((uint8_t)0x18) +#define I2C_Register_CKCFGR ((uint8_t)0x1C) +#define I2C_Register_RTR ((uint8_t)0x20) + +/* I2C_SMBus_alert_pin_level */ +#define I2C_SMBusAlert_Low ((uint16_t)0x2000) +#define I2C_SMBusAlert_High ((uint16_t)0xDFFF) + +/* I2C_PEC_position */ +#define I2C_PECPosition_Next ((uint16_t)0x0800) +#define I2C_PECPosition_Current ((uint16_t)0xF7FF) + +/* I2C_NACK_position */ +#define I2C_NACKPosition_Next ((uint16_t)0x0800) +#define I2C_NACKPosition_Current ((uint16_t)0xF7FF) + +/* I2C_interrupts_definition */ +#define I2C_IT_BUF ((uint16_t)0x0400) +#define I2C_IT_EVT ((uint16_t)0x0200) +#define I2C_IT_ERR ((uint16_t)0x0100) + +/* I2C_interrupts_definition */ +#define I2C_IT_SMBALERT ((uint32_t)0x01008000) +#define I2C_IT_TIMEOUT ((uint32_t)0x01004000) +#define I2C_IT_PECERR ((uint32_t)0x01001000) +#define I2C_IT_OVR ((uint32_t)0x01000800) +#define I2C_IT_AF ((uint32_t)0x01000400) +#define I2C_IT_ARLO ((uint32_t)0x01000200) +#define I2C_IT_BERR ((uint32_t)0x01000100) +#define I2C_IT_TXE ((uint32_t)0x06000080) +#define I2C_IT_RXNE ((uint32_t)0x06000040) +#define I2C_IT_STOPF ((uint32_t)0x02000010) +#define I2C_IT_ADD10 ((uint32_t)0x02000008) +#define I2C_IT_BTF ((uint32_t)0x02000004) +#define I2C_IT_ADDR ((uint32_t)0x02000002) +#define I2C_IT_SB ((uint32_t)0x02000001) + +/* SR2 register flags */ +#define I2C_FLAG_DUALF ((uint32_t)0x00800000) +#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000) +#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000) +#define I2C_FLAG_GENCALL ((uint32_t)0x00100000) +#define I2C_FLAG_TRA ((uint32_t)0x00040000) +#define I2C_FLAG_BUSY ((uint32_t)0x00020000) +#define I2C_FLAG_MSL ((uint32_t)0x00010000) + +/* SR1 register flags */ +#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000) +#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000) +#define I2C_FLAG_PECERR ((uint32_t)0x10001000) +#define I2C_FLAG_OVR ((uint32_t)0x10000800) +#define I2C_FLAG_AF ((uint32_t)0x10000400) +#define I2C_FLAG_ARLO ((uint32_t)0x10000200) +#define I2C_FLAG_BERR ((uint32_t)0x10000100) +#define I2C_FLAG_TXE ((uint32_t)0x10000080) +#define I2C_FLAG_RXNE ((uint32_t)0x10000040) +#define I2C_FLAG_STOPF ((uint32_t)0x10000010) +#define I2C_FLAG_ADD10 ((uint32_t)0x10000008) +#define I2C_FLAG_BTF ((uint32_t)0x10000004) +#define I2C_FLAG_ADDR ((uint32_t)0x10000002) +#define I2C_FLAG_SB ((uint32_t)0x10000001) + + +/****************I2C Master Events (Events grouped in order of communication)********************/ + +/******************************************************************************************************************** + * @brief Start communicate + * + * After master use I2C_GenerateSTART() function sending the START condition,the master + * has to wait for event 5(the Start condition has been correctly + * released on the I2C bus ). + * + */ +/* EVT5 */ +#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */ + +/******************************************************************************************************************** + * @brief Address Acknowledge + * + * When start condition correctly released on the bus(check EVT5), the + * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate + * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges + * his address. If an acknowledge is sent on the bus, one of the following events will be set: + * + * + * + * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED + * event is set. + * + * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED + * is set + * + * 3) In case of 10-Bit addressing mode, the master (after generating the START + * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode. + * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent + * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part + * of the 10-bit address (LSB) . Then master should wait for event 6. + * + * + */ + +/* EVT6 */ +#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */ +#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */ +/*EVT9 */ +#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * If START condition has generated and slave address + * been acknowledged. then the master has to check one of the following events for + * communication procedures: + * + * 1) Master Receiver mode: The master has to wait on the event EVT7 then use + * I2C_ReceiveData() function to read the data received from the slave . + * + * 2) Master Transmitter mode: The master use I2C_SendData() function to send data + * then to wait on event EVT8 or EVT8_2. + * These two events are similar: + * - EVT8 means that the data has been written in the data register and is + * being shifted out. + * - EVT8_2 means that the data has been physically shifted out and output + * on the bus. + * In most cases, using EVT8 is sufficient for the application. + * Using EVT8_2 will leads to a slower communication speed but will more reliable . + * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission + * + * + * Note: + * In case the user software does not guarantee that this event EVT7 is managed before + * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower. + * + * + */ + +/* Master Receive mode */ +/* EVT7 */ +#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */ + +/* Master Transmitter mode*/ +/* EVT8 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */ +/* EVT8_2 */ +#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */ + + +/******************I2C Slave Events (Events grouped in order of communication)******************/ + +/******************************************************************************************************************** + * @brief Start Communicate events + * + * Wait on one of these events at the start of the communication. It means that + * the I2C peripheral detected a start condition of master device generate on the bus. + * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus. + * + * + * + * a) In normal case (only one address managed by the slave), when the address + * sent by the master matches the own address of the peripheral (configured by + * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set + * (where XXX could be TRANSMITTER or RECEIVER). + * + * b) In case the address sent by the master matches the second address of the + * peripheral (configured by the function I2C_OwnAddress2Config() and enabled + * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED + * (where XXX could be TRANSMITTER or RECEIVER) are set. + * + * c) In case the address sent by the master is General Call (address 0x00) and + * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) + * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED. + * + */ + +/* EVT1 */ +/* a) Case of One Single Address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */ + +/* b) Case of Dual address managed by the slave */ +#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */ +#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */ + +/* c) Case of General Call enabled for the slave */ +#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */ + +/******************************************************************************************************************** + * @brief Communication events + * + * Wait on one of these events when EVT1 has already been checked : + * + * - Slave Receiver mode: + * - EVT2--The device is expecting to receive a data byte . + * - EVT4--The device is expecting the end of the communication: master + * sends a stop condition and data transmission is stopped. + * + * - Slave Transmitter mode: + * - EVT3--When a byte has been transmitted by the slave and the Master is expecting + * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and + * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee + * the EVT3 is managed before the current byte end of transfer The second one can optionally + * be used. + * - EVT3_2--When the master sends a NACK to tell slave device that data transmission + * shall end . The slave device has to stop sending + * data bytes and wait a Stop condition from bus. + * + * Note: + * If the user software does not guarantee that the event 2 is + * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED + * and I2C_FLAG_BTF flag at the same time . + * In this case the communication will be slower. + * + */ + +/* Slave Receiver mode*/ +/* EVT2 */ +#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */ +/* EVT4 */ +#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */ + +/* Slave Transmitter mode*/ +/* EVT3 */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */ +#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */ +/*EVT3_2 */ +#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */ + + +void I2C_DeInit(I2C_TypeDef* I2Cx); +void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct); +void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct); +void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address); +void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState); +void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data); +uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx); +void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction); +uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register); +void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition); +void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert); +void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition); +void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState); +uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx); +void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); +void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle); + + +/***************************************************************************************** + * + * I2C State Monitoring Functions + * + **************************************************************************************** + * This I2C driver provides three different ways for I2C state monitoring + * profit the application requirements and constraints: + * + * + * a) First way: + * Using I2C_CheckEvent() function: + * It compares the status registers (STARR1 and STAR2) content to a given event + * (can be the combination of more flags). + * If the current status registers includes the given flags will return SUCCESS. + * and if the current status registers miss flags will returns ERROR. + * - When to use: + * - This function is suitable for most applications as well as for startup + * activity since the events are fully described in the product reference manual + * (CH32FV2x-V3xRM). + * - It is also suitable for users who need to define their own events. + * - Limitations: + * - If an error occurs besides to the monitored error, + * the I2C_CheckEvent() function may return SUCCESS despite the communication + * in corrupted state. it is suggeted to use error interrupts to monitor the error + * events and handle them in IRQ handler. + * + * + * Note: + * The following functions are recommended for error management: : + * - I2C_ITConfig() main function of configure and enable the error interrupts. + * - I2Cx_ER_IRQHandler() will be called when the error interrupt happen. + * Where x is the peripheral instance (I2C1, I2C2 ...) + * - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions + * to determine which error occurred. + * - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd() + * \ I2C_GenerateStop() will be use to clear the error flag and source, + * and return to correct communication status. + * + * + * b) Second way: + * Using the function to get a single word(uint32_t) composed of status register 1 and register 2. + * (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1). + * - When to use: + * + * - This function is suitable for the same applications above but it + * don't have the limitations of I2C_GetFlagStatus() function . + * The returned value could be compared to events already defined in the + * library (CH32V30x_i2c.h) or to custom values defined by user. + * - This function can be used to monitor the status of multiple flags simultaneously. + * - Contrary to the I2C_CheckEvent () function, this function can choose the time to + * accept the event according to the user's needs (when all event flags are set and + * no other flags are set, or only when the required flags are set) + * + * - Limitations: + * - User may need to define his own events. + * - Same remark concerning the error management is applicable for this + * function if user decides to check only regular communication flags (and + * ignores error flags). + * + * + * c) Third way: + * Using the function I2C_GetFlagStatus() get the status of + * one single flag . + * - When to use: + * - This function could be used for specific applications or in debug phase. + * - It is suitable when only one flag checking is needed . + * + * - Limitations: + * - Call this function to access the status register. Some flag bits may be cleared. + * - Function may need to be called twice or more in order to monitor one single event. + */ + + + +/********************************************************* + * + * a) Basic state monitoring(First way) + ******************************************************** + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT); +/********************************************************* + * + * b) Advanced state monitoring(Second way:) + ******************************************************** + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx); +/********************************************************* + * + * c) Flag-based state monitoring(Third way) + ********************************************************* + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); + +void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG); +ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT); +void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + + diff --git a/Peripheral/inc/ch32v30x_iwdg.h b/Peripheral/inc/ch32v30x_iwdg.h new file mode 100644 index 0000000..e506d75 --- /dev/null +++ b/Peripheral/inc/ch32v30x_iwdg.h @@ -0,0 +1,58 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_iwdg.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* IWDG firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_IWDG_H +#define __CH32V30x_IWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* IWDG_WriteAccess */ +#define IWDG_WriteAccess_Enable ((uint16_t)0x5555) +#define IWDG_WriteAccess_Disable ((uint16_t)0x0000) + +/* IWDG_prescaler */ +#define IWDG_Prescaler_4 ((uint8_t)0x00) +#define IWDG_Prescaler_8 ((uint8_t)0x01) +#define IWDG_Prescaler_16 ((uint8_t)0x02) +#define IWDG_Prescaler_32 ((uint8_t)0x03) +#define IWDG_Prescaler_64 ((uint8_t)0x04) +#define IWDG_Prescaler_128 ((uint8_t)0x05) +#define IWDG_Prescaler_256 ((uint8_t)0x06) + +/* IWDG_Flag */ +#define IWDG_FLAG_PVU ((uint16_t)0x0001) +#define IWDG_FLAG_RVU ((uint16_t)0x0002) + + +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess); +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler); +void IWDG_SetReload(uint16_t Reload); +void IWDG_ReloadCounter(void); +void IWDG_Enable(void); +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + diff --git a/Peripheral/inc/ch32v30x_misc.h b/Peripheral/inc/ch32v30x_misc.h new file mode 100644 index 0000000..ad37278 --- /dev/null +++ b/Peripheral/inc/ch32v30x_misc.h @@ -0,0 +1,93 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_misc.h +* Author : WCH +* Version : V1.0.0 +* Date : 2024/03/06 +* Description : This file contains all the functions prototypes for the +* miscellaneous firmware library functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30X_MISC_H +#define __CH32V30X_MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* CSR_INTSYSCR_INEST_definition */ +#define INTSYSCR_INEST_NoEN 0x00 /* interrupt nesting disable(CSR-0x804 bit1 = 0) */ +#define INTSYSCR_INEST_EN_2Level 0x01 /* interrupt nesting enable-2 Level(CSR-0x804 bit1 = 1 bit[3:2] = 1) */ +#define INTSYSCR_INEST_EN_4Level 0x02 /* interrupt nesting enable-4 Level(CSR-0x804 bit1 = 1 bit[3:2] = 2) */ +#define INTSYSCR_INEST_EN_8Level 0x03 /* interrupt nesting enable-8 Level(CSR-0x804 bit1 = 1 bit[3:2] = 3) */ + +/* Check the configuration of CSR(0x804) in the startup file(.S) + * interrupt nesting enable-8 Level(CSR-0x804 bit1 = 1 bit[3:2] = 3) + * priority - bit[7:5] - Preemption Priority + * bit[4:0] - Reserve + * interrupt nesting enable-4 Level(CSR-0x804 bit1 = 1 bit[3:2] = 2) + * priority - bit[7:6] - Preemption Priority + * bit[5] - Sub priority + * bit[4:0] - Reserve + * interrupt nesting enable-2 Level(CSR-0x804 bit1 = 1 bit[3:2] = 1) + * priority - bit[7] - Preemption Priority + * bit[6:5] - Sub priority + * bit[4:0] - Reserve + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * priority - bit[7:5] - Sub priority + * bit[4:0] - Reserve + */ + +#ifndef INTSYSCR_INEST +#define INTSYSCR_INEST INTSYSCR_INEST_EN_4Level +#endif + +/* NVIC Init Structure definition + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * NVIC_IRQChannelPreemptionPriority - range is 0. + * NVIC_IRQChannelSubPriority - range from 0 to 7. + * + * interrupt nesting enable-2 Level(CSR-0x804 bit1 = 1 bit[3:2] = 1) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. + * NVIC_IRQChannelSubPriority - range from 0 to 3. + * + * interrupt nesting enable-4 Level(CSR-0x804 bit1 = 1 bit[3:2] = 2) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 3. + * NVIC_IRQChannelSubPriority - range from 0 to 1. + * + * interrupt nesting enable-8 Level(CSR-0x804 bit1 = 1 bit[3:2] = 3) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 7. + * NVIC_IRQChannelSubPriority - range range is 0. + */ +typedef struct +{ + uint8_t NVIC_IRQChannel; + uint8_t NVIC_IRQChannelPreemptionPriority; + uint8_t NVIC_IRQChannelSubPriority; + FunctionalState NVIC_IRQChannelCmd; +} NVIC_InitTypeDef; + +/* Preemption_Priority_Group */ +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) +#define NVIC_PriorityGroup_0 ((uint32_t)0x00) /* interrupt nesting disable(CSR-0x804 bit1 = 0) */ +#elif (INTSYSCR_INEST == INTSYSCR_INEST_EN_2Level) +#define NVIC_PriorityGroup_1 ((uint32_t)0x01) /* interrupt nesting enable-2 Level(CSR-0x804 bit1 = 1 bit[3:2] = 1) */ +#elif (INTSYSCR_INEST == INTSYSCR_INEST_EN_8Level) +#define NVIC_PriorityGroup_3 ((uint32_t)0x03) /* interrupt nesting enable-8 Level(CSR-0x804 bit1 = 1 bit[3:2] = 3) */ +#else +#define NVIC_PriorityGroup_2 ((uint32_t)0x02) /* interrupt nesting enable-4 Level(CSR-0x804 bit1 = 1 bit[3:2] = 2) */ +#endif + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Peripheral/inc/ch32v30x_opa.h b/Peripheral/inc/ch32v30x_opa.h new file mode 100644 index 0000000..40e71b8 --- /dev/null +++ b/Peripheral/inc/ch32v30x_opa.h @@ -0,0 +1,77 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_opa.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* OPA firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_OPA_H +#define __CH32V30x_OPA_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +#define OPA_PSEL_OFFSET 3 +#define OPA_NSEL_OFFSET 2 +#define OPA_MODE_OFFSET 1 + + +/* OPA member enumeration */ +typedef enum +{ + OPA1=0, + OPA2, + OPA3, + OPA4 +}OPA_Num_TypeDef; + +/* OPA PSEL enumeration */ +typedef enum +{ + CHP0=0, + CHP1 +}OPA_PSEL_TypeDef; + +/* OPA NSEL enumeration */ +typedef enum +{ + CHN0=0, + CHN1 +}OPA_NSEL_TypeDef; + +/* OPA out channel enumeration */ +typedef enum +{ + OUT_IO_OUT0=0, + OUT_IO_OUT1 +}OPA_Mode_TypeDef; + +/* OPA Init Structure definition */ +typedef struct +{ + OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */ + OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */ + OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */ + OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */ +}OPA_InitTypeDef; + + +void OPA_DeInit(void); +void OPA_Init(OPA_InitTypeDef* OPA_InitStruct); +void OPA_StructInit(OPA_InitTypeDef* OPA_InitStruct); +void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Peripheral/inc/ch32v30x_pwr.h b/Peripheral/inc/ch32v30x_pwr.h new file mode 100644 index 0000000..7b726e0 --- /dev/null +++ b/Peripheral/inc/ch32v30x_pwr.h @@ -0,0 +1,77 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_pwr.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the PWR +* firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_PWR_H +#define __CH32V30x_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* PVD_detection_level */ +#define PWR_PVDLevel_MODE0 ((uint32_t)0x00000000) +#define PWR_PVDLevel_MODE1 ((uint32_t)0x00000020) +#define PWR_PVDLevel_MODE2 ((uint32_t)0x00000040) +#define PWR_PVDLevel_MODE3 ((uint32_t)0x00000060) +#define PWR_PVDLevel_MODE4 ((uint32_t)0x00000080) +#define PWR_PVDLevel_MODE5 ((uint32_t)0x000000A0) +#define PWR_PVDLevel_MODE6 ((uint32_t)0x000000C0) +#define PWR_PVDLevel_MODE7 ((uint32_t)0x000000E0) + + + +#define PWR_PVDLevel_2V2 PWR_PVDLevel_MODE0 +#define PWR_PVDLevel_2V3 PWR_PVDLevel_MODE1 +#define PWR_PVDLevel_2V4 PWR_PVDLevel_MODE2 +#define PWR_PVDLevel_2V5 PWR_PVDLevel_MODE3 +#define PWR_PVDLevel_2V6 PWR_PVDLevel_MODE4 +#define PWR_PVDLevel_2V7 PWR_PVDLevel_MODE5 +#define PWR_PVDLevel_2V8 PWR_PVDLevel_MODE6 +#define PWR_PVDLevel_2V9 PWR_PVDLevel_MODE7 + +/* Regulator_state_is_STOP_mode */ +#define PWR_Regulator_ON ((uint32_t)0x00000000) +#define PWR_Regulator_LowPower ((uint32_t)0x00000001) + +/* STOP_mode_entry */ +#define PWR_STOPEntry_WFI ((uint8_t)0x01) +#define PWR_STOPEntry_WFE ((uint8_t)0x02) + +/* PWR_Flag */ +#define PWR_FLAG_WU ((uint32_t)0x00000001) +#define PWR_FLAG_SB ((uint32_t)0x00000002) +#define PWR_FLAG_PVDO ((uint32_t)0x00000004) + + +void PWR_DeInit(void); +void PWR_BackupAccessCmd(FunctionalState NewState); +void PWR_PVDCmd(FunctionalState NewState); +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); +void PWR_WakeUpPinCmd(FunctionalState NewState); +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); +void PWR_EnterSTANDBYMode(void); +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG); +void PWR_ClearFlag(uint32_t PWR_FLAG); +void PWR_EnterSTANDBYMode_RAM(void); +void PWR_EnterSTANDBYMode_RAM_LV(void); +void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void); +void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void); +void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Peripheral/inc/ch32v30x_rcc.h b/Peripheral/inc/ch32v30x_rcc.h new file mode 100644 index 0000000..a43a12b --- /dev/null +++ b/Peripheral/inc/ch32v30x_rcc.h @@ -0,0 +1,464 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_rcc.h +* Author : WCH +* Version : V1.0.0 +* Date : 2024/03/06 +* Description : This file provides all the RCC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_RCC_H +#define __CH32V30x_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* RCC_Exported_Types */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */ + uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */ +}RCC_ClocksTypeDef; + +/* HSE_configuration */ +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) + +/* PLL_entry_clock_source */ +#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) + +#ifdef CH32V30x_D8 +#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) +#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) + +#else +#define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000) + +#endif + +/* PLL_multiplication_factor */ +#ifdef CH32V30x_D8 +#define RCC_PLLMul_2 ((uint32_t)0x00000000) +#define RCC_PLLMul_3 ((uint32_t)0x00040000) +#define RCC_PLLMul_4 ((uint32_t)0x00080000) +#define RCC_PLLMul_5 ((uint32_t)0x000C0000) +#define RCC_PLLMul_6 ((uint32_t)0x00100000) +#define RCC_PLLMul_7 ((uint32_t)0x00140000) +#define RCC_PLLMul_8 ((uint32_t)0x00180000) +#define RCC_PLLMul_9 ((uint32_t)0x001C0000) +#define RCC_PLLMul_10 ((uint32_t)0x00200000) +#define RCC_PLLMul_11 ((uint32_t)0x00240000) +#define RCC_PLLMul_12 ((uint32_t)0x00280000) +#define RCC_PLLMul_13 ((uint32_t)0x002C0000) +#define RCC_PLLMul_14 ((uint32_t)0x00300000) +#define RCC_PLLMul_15 ((uint32_t)0x00340000) +#define RCC_PLLMul_16 ((uint32_t)0x00380000) +#define RCC_PLLMul_18 ((uint32_t)0x003C0000) + +#else +#define RCC_PLLMul_18_EXTEN ((uint32_t)0x00000000) +#define RCC_PLLMul_3_EXTEN ((uint32_t)0x00040000) +#define RCC_PLLMul_4_EXTEN ((uint32_t)0x00080000) +#define RCC_PLLMul_5_EXTEN ((uint32_t)0x000C0000) +#define RCC_PLLMul_6_EXTEN ((uint32_t)0x00100000) +#define RCC_PLLMul_7_EXTEN ((uint32_t)0x00140000) +#define RCC_PLLMul_8_EXTEN ((uint32_t)0x00180000) +#define RCC_PLLMul_9_EXTEN ((uint32_t)0x001C0000) +#define RCC_PLLMul_10_EXTEN ((uint32_t)0x00200000) +#define RCC_PLLMul_11_EXTEN ((uint32_t)0x00240000) +#define RCC_PLLMul_12_EXTEN ((uint32_t)0x00280000) +#define RCC_PLLMul_13_EXTEN ((uint32_t)0x002C0000) +#define RCC_PLLMul_14_EXTEN ((uint32_t)0x00300000) +#define RCC_PLLMul_6_5_EXTEN ((uint32_t)0x00340000) +#define RCC_PLLMul_15_EXTEN ((uint32_t)0x00380000) +#define RCC_PLLMul_16_EXTEN ((uint32_t)0x003C0000) + +#endif + +/* PREDIV1_division_factor */ +#ifdef CH32V30x_D8C +#define RCC_PREDIV1_Div1 ((uint32_t)0x00000000) +#define RCC_PREDIV1_Div2 ((uint32_t)0x00000001) +#define RCC_PREDIV1_Div3 ((uint32_t)0x00000002) +#define RCC_PREDIV1_Div4 ((uint32_t)0x00000003) +#define RCC_PREDIV1_Div5 ((uint32_t)0x00000004) +#define RCC_PREDIV1_Div6 ((uint32_t)0x00000005) +#define RCC_PREDIV1_Div7 ((uint32_t)0x00000006) +#define RCC_PREDIV1_Div8 ((uint32_t)0x00000007) +#define RCC_PREDIV1_Div9 ((uint32_t)0x00000008) +#define RCC_PREDIV1_Div10 ((uint32_t)0x00000009) +#define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A) +#define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B) +#define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C) +#define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D) +#define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E) +#define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F) + +#endif + +/* PREDIV1_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000) +#define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000) + +#endif + +/* PREDIV2_division_factor */ +#ifdef CH32V30x_D8C +#define RCC_PREDIV2_Div1 ((uint32_t)0x00000000) +#define RCC_PREDIV2_Div2 ((uint32_t)0x00000010) +#define RCC_PREDIV2_Div3 ((uint32_t)0x00000020) +#define RCC_PREDIV2_Div4 ((uint32_t)0x00000030) +#define RCC_PREDIV2_Div5 ((uint32_t)0x00000040) +#define RCC_PREDIV2_Div6 ((uint32_t)0x00000050) +#define RCC_PREDIV2_Div7 ((uint32_t)0x00000060) +#define RCC_PREDIV2_Div8 ((uint32_t)0x00000070) +#define RCC_PREDIV2_Div9 ((uint32_t)0x00000080) +#define RCC_PREDIV2_Div10 ((uint32_t)0x00000090) +#define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0) +#define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0) +#define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0) +#define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0) +#define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0) +#define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0) + +#endif + +/* PLL2_multiplication_factor */ +#ifdef CH32V30x_D8C +#define RCC_PLL2Mul_2_5 ((uint32_t)0x00000000) +#define RCC_PLL2Mul_12_5 ((uint32_t)0x00000100) +#define RCC_PLL2Mul_4 ((uint32_t)0x00000200) +#define RCC_PLL2Mul_5 ((uint32_t)0x00000300) +#define RCC_PLL2Mul_6 ((uint32_t)0x00000400) +#define RCC_PLL2Mul_7 ((uint32_t)0x00000500) +#define RCC_PLL2Mul_8 ((uint32_t)0x00000600) +#define RCC_PLL2Mul_9 ((uint32_t)0x00000700) +#define RCC_PLL2Mul_10 ((uint32_t)0x00000800) +#define RCC_PLL2Mul_11 ((uint32_t)0x00000900) +#define RCC_PLL2Mul_12 ((uint32_t)0x00000A00) +#define RCC_PLL2Mul_13 ((uint32_t)0x00000B00) +#define RCC_PLL2Mul_14 ((uint32_t)0x00000C00) +#define RCC_PLL2Mul_15 ((uint32_t)0x00000D00) +#define RCC_PLL2Mul_16 ((uint32_t)0x00000E00) +#define RCC_PLL2Mul_20 ((uint32_t)0x00000F00) + +#endif + +/* PLL3_multiplication_factor */ +#ifdef CH32V30x_D8C +#define RCC_PLL3Mul_2_5 ((uint32_t)0x00000000) +#define RCC_PLL3Mul_12_5 ((uint32_t)0x00001000) +#define RCC_PLL3Mul_4 ((uint32_t)0x00002000) +#define RCC_PLL3Mul_5 ((uint32_t)0x00003000) +#define RCC_PLL3Mul_6 ((uint32_t)0x00004000) +#define RCC_PLL3Mul_7 ((uint32_t)0x00005000) +#define RCC_PLL3Mul_8 ((uint32_t)0x00006000) +#define RCC_PLL3Mul_9 ((uint32_t)0x00007000) +#define RCC_PLL3Mul_10 ((uint32_t)0x00008000) +#define RCC_PLL3Mul_11 ((uint32_t)0x00009000) +#define RCC_PLL3Mul_12 ((uint32_t)0x0000A000) +#define RCC_PLL3Mul_13 ((uint32_t)0x0000B000) +#define RCC_PLL3Mul_14 ((uint32_t)0x0000C000) +#define RCC_PLL3Mul_15 ((uint32_t)0x0000D000) +#define RCC_PLL3Mul_16 ((uint32_t)0x0000E000) +#define RCC_PLL3Mul_20 ((uint32_t)0x0000F000) + +#endif + +/* System_clock_source */ +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) + +/* AHB_clock_source */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) + +/* APB1_APB2_clock_source */ +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00000400) +#define RCC_HCLK_Div4 ((uint32_t)0x00000500) +#define RCC_HCLK_Div8 ((uint32_t)0x00000600) +#define RCC_HCLK_Div16 ((uint32_t)0x00000700) + +/* RCC_Interrupt_source */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) + +#ifdef CH32V30x_D8C +#define RCC_IT_PLL2RDY ((uint8_t)0x20) +#define RCC_IT_PLL3RDY ((uint8_t)0x40) + +#endif + +/* USBFS_clock_source */ +#define RCC_USBFSCLKSource_PLLCLK_Div1 ((uint8_t)0x00) +#define RCC_USBFSCLKSource_PLLCLK_Div2 ((uint8_t)0x01) +#define RCC_USBFSCLKSource_PLLCLK_Div3 ((uint8_t)0x02) + +#define RCC_OTGFSCLKSource_PLLCLK_Div1 RCC_USBFSCLKSource_PLLCLK_Div1 +#define RCC_OTGFSCLKSource_PLLCLK_Div2 RCC_USBFSCLKSource_PLLCLK_Div2 +#define RCC_OTGFSCLKSource_PLLCLK_Div3 RCC_USBFSCLKSource_PLLCLK_Div3 + +/* I2S2_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00) +#define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01) + +#endif + +/* I2S3_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00) +#define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01) + +#endif + +/* ADC_clock_source */ +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) + +/* LSE_configuration */ +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) + +/* RTC_clock_source */ +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) + +/* AHB_peripheral */ +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) +#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) +#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) +#define RCC_AHBPeriph_RNG ((uint32_t)0x00000200) +#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) +#define RCC_AHBPeriph_USBHS ((uint32_t)0x00000800) +#define RCC_AHBPeriph_USBFS ((uint32_t)0x00001000) +#define RCC_AHBPeriph_DVP ((uint32_t)0x00002000) +#define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000) +#define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000) +#define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000) +#define RCC_AHBPeriph_OTG_FS RCC_AHBPeriph_USBFS + +/* APB2_peripheral */ +#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) +#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) +#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) + +/* APB1_peripheral */ +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) +#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) +#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) +#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) +#define RCC_APB1Periph_UART6 ((uint32_t)0x00000040) +#define RCC_APB1Periph_UART7 ((uint32_t)0x00000080) +#define RCC_APB1Periph_UART8 ((uint32_t)0x00000100) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) +#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000) +#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) +#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1Periph_USB ((uint32_t)0x00800000) +#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) +#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) + +/* Clock_source_to_output_on_MCO_pin */ +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) + +#ifdef CH32V30x_D8C +#define RCC_MCO_PLL2CLK ((uint8_t)0x08) +#define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09) +#define RCC_MCO_XT1 ((uint8_t)0x0A) +#define RCC_MCO_PLL3CLK ((uint8_t)0x0B) + +#endif + +/* RCC_Flag */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +#ifdef CH32V30x_D8C +#define RCC_FLAG_PLL2RDY ((uint8_t)0x3B) +#define RCC_FLAG_PLL3RDY ((uint8_t)0x3D) + +#endif + +/* SysTick_clock_source */ +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) + +/* RNG_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_RNGCLKSource_SYSCLK ((uint32_t)0x00) +#define RCC_RNGCLKSource_PLL3_VCO ((uint32_t)0x01) + +#endif + +/* ETH1G_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_ETH1GCLKSource_PLL2_VCO ((uint32_t)0x00) +#define RCC_ETH1GCLKSource_PLL3_VCO ((uint32_t)0x01) +#define RCC_ETH1GCLKSource_PB1_IN ((uint32_t)0x02) + +#endif + +/* USBFS_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_USBPLL_Div1 ((uint32_t)0x00) +#define RCC_USBPLL_Div2 ((uint32_t)0x01) +#define RCC_USBPLL_Div3 ((uint32_t)0x02) +#define RCC_USBPLL_Div4 ((uint32_t)0x03) +#define RCC_USBPLL_Div5 ((uint32_t)0x04) +#define RCC_USBPLL_Div6 ((uint32_t)0x05) +#define RCC_USBPLL_Div7 ((uint32_t)0x06) +#define RCC_USBPLL_Div8 ((uint32_t)0x07) + +#endif + +/* USBHSPLL_clock_source */ +#ifdef CH32V30x_D8C +#define RCC_HSBHSPLLCLKSource_HSE ((uint32_t)0x00) +#define RCC_HSBHSPLLCLKSource_HSI ((uint32_t)0x01) + +#endif + +/* USBHSPLLCKREF_clock_select */ +#ifdef CH32V30x_D8C +#define RCC_USBHSPLLCKREFCLK_3M ((uint32_t)0x00) +#define RCC_USBHSPLLCKREFCLK_4M ((uint32_t)0x01) +#define RCC_USBHSPLLCKREFCLK_8M ((uint32_t)0x02) +#define RCC_USBHSPLLCKREFCLK_5M ((uint32_t)0x03) + +#endif + +/* OTGUSBCLK48M_clock_source */ +#define RCC_USBCLK48MCLKSource_PLLCLK ((uint32_t)0x00) +#define RCC_USBCLK48MCLKSource_USBPHY ((uint32_t)0x01) + + +void RCC_DeInit(void); +void RCC_HSEConfig(uint32_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); +void RCC_PLLCmd(FunctionalState NewState); +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLK1Config(uint32_t RCC_HCLK); +void RCC_PCLK2Config(uint32_t RCC_HCLK); +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); +void RCC_LSEConfig(uint8_t RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks); +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); +void RCC_ADCCLKADJcmd(FunctionalState NewState); +void RCC_USBFSCLKConfig(uint32_t RCC_USBFSCLKSource); +void RCC_USBCLK48MConfig(uint32_t RCC_USBCLK48MSource); +#define RCC_OTGFSCLKConfig RCC_USBFSCLKConfig + +#ifdef CH32V30x_D8C +void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div); +void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div); +void RCC_PLL2Config(uint32_t RCC_PLL2Mul); +void RCC_PLL2Cmd(FunctionalState NewState); +void RCC_PLL3Config(uint32_t RCC_PLL3Mul); +void RCC_PLL3Cmd(FunctionalState NewState); +void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource); +void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource); +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_RNGCLKConfig(uint32_t RCC_RNGCLKSource); +void RCC_ETH1GCLKConfig(uint32_t RCC_ETH1GCLKSource); +void RCC_ETH1G_125Mcmd(FunctionalState NewState); +void RCC_USBHSConfig(uint32_t RCC_USBHS); +void RCC_USBHSPLLCLKConfig(uint32_t RCC_USBHSPLLCLKSource); +void RCC_USBHSPLLCKREFCLKConfig(uint32_t RCC_USBHSPLLCKREFCLKSource); +void RCC_USBHSPHYPLLALIVEcmd(FunctionalState NewState); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif + + + + + diff --git a/Peripheral/inc/ch32v30x_rng.h b/Peripheral/inc/ch32v30x_rng.h new file mode 100644 index 0000000..3163c89 --- /dev/null +++ b/Peripheral/inc/ch32v30x_rng.h @@ -0,0 +1,43 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_rng.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* RNG firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_RNG_H +#define __CH32V30x_RNG_H + +#ifdef __cplusplus + extern "C" { +#endif +#include "ch32v30x.h" + + /* RNG_flags_definition*/ +#define RNG_FLAG_DRDY ((uint8_t)0x0001) /* Data ready */ +#define RNG_FLAG_CECS ((uint8_t)0x0002) /* Clock error current status */ +#define RNG_FLAG_SECS ((uint8_t)0x0004) /* Seed error current status */ + +/* RNG_interrupts_definition */ +#define RNG_IT_CEI ((uint8_t)0x20) /* Clock error interrupt */ +#define RNG_IT_SEI ((uint8_t)0x40) /* Seed error interrupt */ + + +void RNG_Cmd(FunctionalState NewState); +uint32_t RNG_GetRandomNumber(void); +void RNG_ITConfig(FunctionalState NewState); +FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG); +void RNG_ClearFlag(uint8_t RNG_FLAG); +ITStatus RNG_GetITStatus(uint8_t RNG_IT); +void RNG_ClearITPendingBit(uint8_t RNG_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Peripheral/inc/ch32v30x_rtc.h b/Peripheral/inc/ch32v30x_rtc.h new file mode 100644 index 0000000..3e17385 --- /dev/null +++ b/Peripheral/inc/ch32v30x_rtc.h @@ -0,0 +1,56 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_rtc.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the RTC +* firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_RTC_H +#define __CH32V30x_RTC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + + +/* RTC_interrupts_define */ +#define RTC_IT_OW ((uint16_t)0x0004) /* Overflow interrupt */ +#define RTC_IT_ALR ((uint16_t)0x0002) /* Alarm interrupt */ +#define RTC_IT_SEC ((uint16_t)0x0001) /* Second interrupt */ + +/* RTC_interrupts_flags */ +#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /* RTC Operation OFF flag */ +#define RTC_FLAG_RSF ((uint16_t)0x0008) /* Registers Synchronized flag */ +#define RTC_FLAG_OW ((uint16_t)0x0004) /* Overflow flag */ +#define RTC_FLAG_ALR ((uint16_t)0x0002) /* Alarm flag */ +#define RTC_FLAG_SEC ((uint16_t)0x0001) /* Second flag */ + + +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState); +void RTC_EnterConfigMode(void); +void RTC_ExitConfigMode(void); +uint32_t RTC_GetCounter(void); +void RTC_SetCounter(uint32_t CounterValue); +void RTC_SetPrescaler(uint32_t PrescalerValue); +void RTC_SetAlarm(uint32_t AlarmValue); +uint32_t RTC_GetDivider(void); +void RTC_WaitForLastTask(void); +void RTC_WaitForSynchro(void); +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG); +void RTC_ClearFlag(uint16_t RTC_FLAG); +ITStatus RTC_GetITStatus(uint16_t RTC_IT); +void RTC_ClearITPendingBit(uint16_t RTC_IT); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Peripheral/inc/ch32v30x_sdio.h b/Peripheral/inc/ch32v30x_sdio.h new file mode 100644 index 0000000..6f3cfa8 --- /dev/null +++ b/Peripheral/inc/ch32v30x_sdio.h @@ -0,0 +1,266 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_sdio.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the SDIO +* firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_SDIO_H +#define __CH32V30x_SDIO_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* SDIO Init structure definition */ +typedef struct +{ + uint32_t SDIO_ClockEdge; /* Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref SDIO_Clock_Edge */ + + uint32_t SDIO_ClockBypass; /* Specifies whether the SDIO Clock divider bypass is + enabled or disabled. + This parameter can be a value of @ref SDIO_Clock_Bypass */ + + uint32_t SDIO_ClockPowerSave; /* Specifies whether SDIO Clock output is enabled or + disabled when the bus is idle. + This parameter can be a value of @ref SDIO_Clock_Power_Save */ + + uint32_t SDIO_BusWide; /* Specifies the SDIO bus width. + This parameter can be a value of @ref SDIO_Bus_Wide */ + + uint32_t SDIO_HardwareFlowControl; /* Specifies whether the SDIO hardware flow control is enabled or disabled. + This parameter can be a value of @ref SDIO_Hardware_Flow_Control */ + + uint8_t SDIO_ClockDiv; /* Specifies the clock frequency of the SDIO controller. + This parameter can be a value between 0x00 and 0xFF. */ + +} SDIO_InitTypeDef; + + +typedef struct +{ + uint32_t SDIO_Argument; /* Specifies the SDIO command argument which is sent + to a card as part of a command message. If a command + contains an argument, it must be loaded into this register + before writing the command to the command register */ + + uint32_t SDIO_CmdIndex; /* Specifies the SDIO command index. It must be lower than 0x40. */ + + uint32_t SDIO_Response; /* Specifies the SDIO response type. + This parameter can be a value of @ref SDIO_Response_Type */ + + uint32_t SDIO_Wait; /* Specifies whether SDIO wait-for-interrupt request is enabled or disabled. + This parameter can be a value of @ref SDIO_Wait_Interrupt_State */ + + uint32_t SDIO_CPSM; /* Specifies whether SDIO Command path state machine (CPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_CPSM_State */ +} SDIO_CmdInitTypeDef; + +typedef struct +{ + uint32_t SDIO_DataTimeOut; /* Specifies the data timeout period in card bus clock periods. */ + + uint32_t SDIO_DataLength; /* Specifies the number of data bytes to be transferred. */ + + uint32_t SDIO_DataBlockSize; /* Specifies the data block size for block transfer. + This parameter can be a value of @ref SDIO_Data_Block_Size */ + + uint32_t SDIO_TransferDir; /* Specifies the data transfer direction, whether the transfer + is a read or write. + This parameter can be a value of @ref SDIO_Transfer_Direction */ + + uint32_t SDIO_TransferMode; /* Specifies whether data transfer is in stream or block mode. + This parameter can be a value of @ref SDIO_Transfer_Type */ + + uint32_t SDIO_DPSM; /* Specifies whether SDIO Data path state machine (DPSM) + is enabled or disabled. + This parameter can be a value of @ref SDIO_DPSM_State */ +} SDIO_DataInitTypeDef; + + +/* SDIO_Clock_Edge */ +#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000) +#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000) + +/* SDIO_Clock_Bypass */ +#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000) +#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400) + +/* SDIO_Clock_Power_Save */ +#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000) +#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200) + +/* SDIO_Bus_Wide */ +#define SDIO_BusWide_1b ((uint32_t)0x00000000) +#define SDIO_BusWide_4b ((uint32_t)0x00000800) +#define SDIO_BusWide_8b ((uint32_t)0x00001000) + +/* SDIO_Hardware_Flow_Control */ +#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000) +#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000) + +/* SDIO_Power_State */ +#define SDIO_PowerState_OFF ((uint32_t)0x00000000) +#define SDIO_PowerState_ON ((uint32_t)0x00000003) + +/* SDIO_Interrupt_sources */ +#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_IT_RXOVERR ((uint32_t)0x00000020) +#define SDIO_IT_CMDREND ((uint32_t)0x00000040) +#define SDIO_IT_CMDSENT ((uint32_t)0x00000080) +#define SDIO_IT_DATAEND ((uint32_t)0x00000100) +#define SDIO_IT_STBITERR ((uint32_t)0x00000200) +#define SDIO_IT_DBCKEND ((uint32_t)0x00000400) +#define SDIO_IT_CMDACT ((uint32_t)0x00000800) +#define SDIO_IT_TXACT ((uint32_t)0x00001000) +#define SDIO_IT_RXACT ((uint32_t)0x00002000) +#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_IT_TXDAVL ((uint32_t)0x00100000) +#define SDIO_IT_RXDAVL ((uint32_t)0x00200000) +#define SDIO_IT_SDIOIT ((uint32_t)0x00400000) +#define SDIO_IT_CEATAEND ((uint32_t)0x00800000) + +/* SDIO_Response_Type */ +#define SDIO_Response_No ((uint32_t)0x00000000) +#define SDIO_Response_Short ((uint32_t)0x00000040) +#define SDIO_Response_Long ((uint32_t)0x000000C0) + +/* SDIO_Wait_Interrupt_State */ +#define SDIO_Wait_No ((uint32_t)0x00000000) +#define SDIO_Wait_IT ((uint32_t)0x00000100) +#define SDIO_Wait_Pend ((uint32_t)0x00000200) + +/* SDIO_CPSM_State */ +#define SDIO_CPSM_Disable ((uint32_t)0x00000000) +#define SDIO_CPSM_Enable ((uint32_t)0x00000400) + +/* SDIO_Response_Registers */ +#define SDIO_RESP1 ((uint32_t)0x00000000) +#define SDIO_RESP2 ((uint32_t)0x00000004) +#define SDIO_RESP3 ((uint32_t)0x00000008) +#define SDIO_RESP4 ((uint32_t)0x0000000C) + +/* SDIO_Data_Block_Size */ +#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000) +#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010) +#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020) +#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030) +#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040) +#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050) +#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060) +#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070) +#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080) +#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090) +#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0) +#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0) +#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0) +#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0) +#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0) + +/* SDIO_Transfer_Direction */ +#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000) +#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002) + +/* SDIO_Transfer_Type */ +#define SDIO_TransferMode_Block ((uint32_t)0x00000000) +#define SDIO_TransferMode_Stream ((uint32_t)0x00000004) + +/* SDIO_DPSM_State */ +#define SDIO_DPSM_Disable ((uint32_t)0x00000000) +#define SDIO_DPSM_Enable ((uint32_t)0x00000001) + +/* SDIO_Flags */ +#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001) +#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002) +#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004) +#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008) +#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010) +#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020) +#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040) +#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080) +#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100) +#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200) +#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400) +#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800) +#define SDIO_FLAG_TXACT ((uint32_t)0x00001000) +#define SDIO_FLAG_RXACT ((uint32_t)0x00002000) +#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000) +#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000) +#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000) +#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000) +#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000) +#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000) +#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000) +#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000) +#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000) +#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000) + +/* SDIO_Read_Wait_Mode */ +#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001) +#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000) + +#define SDIO_DataControl_DTEN ((uint32_t)0x00000001) +#define SDIO_DataControl_DTDIR ((uint32_t)0x00000002) +#define SDIO_DataControl_DTMODE ((uint32_t)0x00000004) +#define SDIO_DataControl_DMAEN ((uint32_t)0x00000008) +#define SDIO_DataControl_DBLOCKSIZE ((uint32_t)0x000000F0) +#define SDIO_DataControl_RWSTART ((uint32_t)0x00000100) +#define SDIO_DataControl_RWSTOP ((uint32_t)0x00000200) +#define SDIO_DataControl_RWMOD ((uint32_t)0x00000400) +#define SDIO_DataControl_SDIOEN ((uint32_t)0x00000800) + + +void SDIO_DeInit(void); +void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct); +void SDIO_ClockCmd(FunctionalState NewState); +void SDIO_SetPowerState(uint32_t SDIO_PowerState); +uint32_t SDIO_GetPowerState(void); +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState); +void SDIO_DMACmd(FunctionalState NewState); +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct); +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct); +uint8_t SDIO_GetCommandResponse(void); +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP); +void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct); +uint32_t SDIO_GetDataCounter(void); +uint32_t SDIO_ReadData(void); +void SDIO_WriteData(uint32_t Data); +uint32_t SDIO_GetFIFOCount(void); +void SDIO_StartSDIOReadWait(FunctionalState NewState); +void SDIO_StopSDIOReadWait(FunctionalState NewState); +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode); +void SDIO_SetSDIOOperation(FunctionalState NewState); +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState); +void SDIO_CommandCompletionCmd(FunctionalState NewState); +void SDIO_CEATAITCmd(FunctionalState NewState); +void SDIO_SendCEATACmd(FunctionalState NewState); +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG); +void SDIO_ClearFlag(uint32_t SDIO_FLAG); +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT); +void SDIO_ClearITPendingBit(uint32_t SDIO_IT); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/Peripheral/inc/ch32v30x_spi.h b/Peripheral/inc/ch32v30x_spi.h new file mode 100644 index 0000000..46493a5 --- /dev/null +++ b/Peripheral/inc/ch32v30x_spi.h @@ -0,0 +1,231 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_spi.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* SPI firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_SPI_H +#define __CH32V30x_SPI_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* SPI Init structure definition */ +typedef struct +{ + uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_data_direction */ + + uint16_t SPI_Mode; /* Specifies the SPI operating mode. + This parameter can be a value of @ref SPI_mode */ + + uint16_t SPI_DataSize; /* Specifies the SPI data size. + This parameter can be a value of @ref SPI_data_size */ + + uint16_t SPI_CPOL; /* Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_Clock_Polarity */ + + uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_Clock_Phase */ + + uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_Slave_Select_management */ + + uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_BaudRate_Prescaler. + @note The communication clock is derived from the master + clock. The slave clock does not need to be set. */ + + uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_MSB_LSB_transmission */ + + uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */ +}SPI_InitTypeDef; + +/* I2S Init structure definition */ +typedef struct +{ + + uint16_t I2S_Mode; /* Specifies the I2S operating mode. + This parameter can be a value of @ref I2S_Mode */ + + uint16_t I2S_Standard; /* Specifies the standard used for the I2S communication. + This parameter can be a value of @ref I2S_Standard */ + + uint16_t I2S_DataFormat; /* Specifies the data format for the I2S communication. + This parameter can be a value of @ref I2S_Data_Format */ + + uint16_t I2S_MCLKOutput; /* Specifies whether the I2S MCLK output is enabled or not. + This parameter can be a value of @ref I2S_MCLK_Output */ + + uint32_t I2S_AudioFreq; /* Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + + uint16_t I2S_CPOL; /* Specifies the idle state of the I2S clock. + This parameter can be a value of @ref I2S_Clock_Polarity */ +}I2S_InitTypeDef; + +/* SPI_data_direction */ +#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000) +#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400) +#define SPI_Direction_1Line_Rx ((uint16_t)0x8000) +#define SPI_Direction_1Line_Tx ((uint16_t)0xC000) + +/* SPI_mode */ +#define SPI_Mode_Master ((uint16_t)0x0104) +#define SPI_Mode_Slave ((uint16_t)0x0000) + +/* SPI_data_size */ +#define SPI_DataSize_16b ((uint16_t)0x0800) +#define SPI_DataSize_8b ((uint16_t)0x0000) + +/* SPI_Clock_Polarity */ +#define SPI_CPOL_Low ((uint16_t)0x0000) +#define SPI_CPOL_High ((uint16_t)0x0002) + +/* SPI_Clock_Phase */ +#define SPI_CPHA_1Edge ((uint16_t)0x0000) +#define SPI_CPHA_2Edge ((uint16_t)0x0001) + +/* SPI_Slave_Select_management */ +#define SPI_NSS_Soft ((uint16_t)0x0200) +#define SPI_NSS_Hard ((uint16_t)0x0000) + +/* SPI_BaudRate_Prescaler */ +#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000) +#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008) +#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010) +#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018) +#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020) +#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028) +#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030) +#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038) + +/* SPI_MSB_LSB_transmission */ +#define SPI_FirstBit_MSB ((uint16_t)0x0000) +#define SPI_FirstBit_LSB ((uint16_t)0x0080) + +/* I2S_Mode */ +#define I2S_Mode_SlaveTx ((uint16_t)0x0000) +#define I2S_Mode_SlaveRx ((uint16_t)0x0100) +#define I2S_Mode_MasterTx ((uint16_t)0x0200) +#define I2S_Mode_MasterRx ((uint16_t)0x0300) + +/* I2S_Standard */ +#define I2S_Standard_Phillips ((uint16_t)0x0000) +#define I2S_Standard_MSB ((uint16_t)0x0010) +#define I2S_Standard_LSB ((uint16_t)0x0020) +#define I2S_Standard_PCMShort ((uint16_t)0x0030) +#define I2S_Standard_PCMLong ((uint16_t)0x00B0) + +/* I2S_Data_Format */ +#define I2S_DataFormat_16b ((uint16_t)0x0000) +#define I2S_DataFormat_16bextended ((uint16_t)0x0001) +#define I2S_DataFormat_24b ((uint16_t)0x0003) +#define I2S_DataFormat_32b ((uint16_t)0x0005) + +/* I2S_MCLK_Output */ +#define I2S_MCLKOutput_Enable ((uint16_t)0x0200) +#define I2S_MCLKOutput_Disable ((uint16_t)0x0000) + +/* I2S_Audio_Frequency */ +#define I2S_AudioFreq_192k ((uint32_t)192000) +#define I2S_AudioFreq_96k ((uint32_t)96000) +#define I2S_AudioFreq_48k ((uint32_t)48000) +#define I2S_AudioFreq_44k ((uint32_t)44100) +#define I2S_AudioFreq_32k ((uint32_t)32000) +#define I2S_AudioFreq_22k ((uint32_t)22050) +#define I2S_AudioFreq_16k ((uint32_t)16000) +#define I2S_AudioFreq_11k ((uint32_t)11025) +#define I2S_AudioFreq_8k ((uint32_t)8000) +#define I2S_AudioFreq_Default ((uint32_t)2) + +/* I2S_Clock_Polarity */ +#define I2S_CPOL_Low ((uint16_t)0x0000) +#define I2S_CPOL_High ((uint16_t)0x0008) + +/* SPI_I2S_DMA_transfer_requests */ +#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002) +#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001) + +/* SPI_NSS_internal_software_management */ +#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100) +#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF) + +/* SPI_CRC_Transmit_Receive */ +#define SPI_CRC_Tx ((uint8_t)0x00) +#define SPI_CRC_Rx ((uint8_t)0x01) + +/* SPI_direction_transmit_receive */ +#define SPI_Direction_Rx ((uint16_t)0xBFFF) +#define SPI_Direction_Tx ((uint16_t)0x4000) + +/* SPI_I2S_interrupts_definition */ +#define SPI_I2S_IT_TXE ((uint8_t)0x71) +#define SPI_I2S_IT_RXNE ((uint8_t)0x60) +#define SPI_I2S_IT_ERR ((uint8_t)0x50) +#define SPI_I2S_IT_OVR ((uint8_t)0x56) +#define SPI_IT_MODF ((uint8_t)0x55) +#define SPI_IT_CRCERR ((uint8_t)0x54) +#define I2S_IT_UDR ((uint8_t)0x53) + +/* SPI_I2S_flags_definition */ +#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001) +#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002) +#define I2S_FLAG_CHSIDE ((uint16_t)0x0004) +#define I2S_FLAG_UDR ((uint16_t)0x0008) +#define SPI_FLAG_CRCERR ((uint16_t)0x0010) +#define SPI_FLAG_MODF ((uint16_t)0x0020) +#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040) +#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080) + + +void SPI_I2S_DeInit(SPI_TypeDef* SPIx); +void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct); +void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); +void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct); +void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); +void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState); +void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState); +void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data); +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx); +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft); +void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState); +void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize); +void SPI_TransmitCRC(SPI_TypeDef* SPIx); +void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState); +uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC); +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx); +void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction); +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG); +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); +void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + + + diff --git a/Peripheral/inc/ch32v30x_tim.h b/Peripheral/inc/ch32v30x_tim.h new file mode 100644 index 0000000..06f36d0 --- /dev/null +++ b/Peripheral/inc/ch32v30x_tim.h @@ -0,0 +1,517 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_tim.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the +* TIM firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_TIM_H +#define __CH32V30x_TIM_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + +/* TIM Time Base Init structure definition */ +typedef struct +{ + uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /* Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint16_t TIM_Period; /* Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t TIM_ClockDivision; /* Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_TimeBaseInitTypeDef; + +/* TIM Output Compare Init structure definition */ +typedef struct +{ + uint16_t TIM_OCMode; /* Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_OCPolarity; /* Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OCInitTypeDef; + +/* TIM Input Capture Init structure definition */ +typedef struct +{ + uint16_t TIM_Channel; /* Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /* Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /* Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/* BDTR structure definition */ +typedef struct +{ + uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state. + This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters. + This parameter can be a value of @ref Lock_level */ + + uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/* TIM_Output_Compare_and_PWM_modes */ +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) + +/* TIM_One_Pulse_Mode */ +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) + +/* TIM_Channel */ +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +/* TIM_Clock_Division_CKD */ +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) + +/* TIM_Counter_Mode */ +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) + +/* TIM_Output_Compare_Polarity */ +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) + +/* TIM_Output_Compare_N_Polarity */ +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) + +/* TIM_Output_Compare_state */ +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) + +/* TIM_Output_Compare_N_state */ +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) + +/* TIM_Capture_Compare_state */ +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) + +/* TIM_Capture_Compare_N_state */ +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) + +/* Break_Input_enable_disable */ +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) + +/* Break_Polarity */ +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) + +/* TIM_AOE_Bit_Set_Reset */ +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) + +/* Lock_level */ +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) + +/* OSSI_Off_State_Selection_for_Idle_mode_state */ +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) + +/* OSSR_Off_State_Selection_for_Run_mode_state */ +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Idle_State */ +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Output_Compare_N_Idle_State */ +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Input_Capture_Polarity */ +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) + +/* TIM_Input_Capture_Selection */ +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ + +/* TIM_Input_Capture_Prescaler */ +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ + +/* TIM_interrupt_sources */ +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) + +/* TIM_DMA_Base_address */ +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) + +/* TIM_DMA_Burst_Length */ +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) + +/* TIM_DMA_sources */ +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) + +/* TIM_External_Trigger_Prescaler */ +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) + +/* TIM_Internal_Trigger_Selection */ +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) + +/* TIM_TIx_External_Clock_Source */ +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/* TIM_External_Trigger_Polarity */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) + +/* TIM_Prescaler_Reload_Mode */ +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) + +/* TIM_Forced_Action */ +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) + +/* TIM_Encoder_Mode */ +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) + +/* TIM_Event_Source */ +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) + +/* TIM_Update_Source */ +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow + or the setting of UG bit, or an update generation + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ + +/* TIM_Output_Compare_Preload_State */ +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Fast_State */ +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Clear_State */ +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) + +/* TIM_Trigger_Output_Source */ +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) + +/* TIM_Slave_Mode */ +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) + +/* TIM_Master_Slave_Mode */ +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) + +/* TIM_Flags */ +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) + +/* TIM_Legacy */ +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers + + +void TIM_DeInit(TIM_TypeDef* TIMx); +void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct); +void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource); +void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_InternalClockConfig(TIM_TypeDef* TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); +void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode); +void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource); +void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction); +void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); +void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter); +void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload); +void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1); +void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2); +void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3); +void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4); +void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC); +void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD); +uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx); +uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx); +uint16_t TIM_GetCounter(TIM_TypeDef* TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + + diff --git a/Peripheral/inc/ch32v30x_usart.h b/Peripheral/inc/ch32v30x_usart.h new file mode 100644 index 0000000..8dc9bb7 --- /dev/null +++ b/Peripheral/inc/ch32v30x_usart.h @@ -0,0 +1,195 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_usart.h +* Author : WCH +* Version : V1.0.0 +* Date : 2024/03/06 +* Description : This file contains all the functions prototypes for the +* USART firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_USART_H +#define __CH32V30x_USART_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + + +/* USART Init Structure definition */ +typedef struct +{ + uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /* Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/* USART Clock Init Structure definition */ +typedef struct +{ + + uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/* USART_Word_Length */ +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +/* USART_Stop_Bits */ +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) + +/* USART_Parity */ +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) + +/* USART_Mode */ +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) + +/* USART_Hardware_Flow_Control */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) + +/* USART_Clock */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) + +/* USART_Clock_Polarity */ +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) + +/* USART_Clock_Phase */ +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) + +/* USART_Last_Bit */ +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) + +/* USART_Interrupt_definition */ +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +#define USART_IT_ORE USART_IT_ORE_ER + +/* USART_DMA_Requests */ +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) + +/* USART_WakeUp_methods */ +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) + +/* USART_LIN_Break_Detection_Length */ +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) + +/* USART_IrDA_Low_Power */ +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) + +/* USART_Flags */ +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) + + +void USART_DeInit(USART_TypeDef* USARTx); +void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct); +void USART_StructInit(USART_InitTypeDef* USART_InitStruct); +void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState); +void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState); +void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address); +void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SendData(USART_TypeDef* USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef* USARTx); +void USART_SendBreak(USART_TypeDef* USARTx); +void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); +void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); +void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState); +void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif + + + + + + + diff --git a/Peripheral/inc/ch32v30x_usb.h b/Peripheral/inc/ch32v30x_usb.h new file mode 100644 index 0000000..2fb5475 --- /dev/null +++ b/Peripheral/inc/ch32v30x_usb.h @@ -0,0 +1,834 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : system_ch32v30x.h +* Author : WCH +* Version : V1.0.0 +* Date : 2024/05/22 +* Description : CH32V30x Device Peripheral Access Layer System Header File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + +#ifndef __CH32V30x_USB_H +#define __CH32V30x_USB_H + +#ifdef __cplusplus + extern "C" { +#endif + +/*******************************************************************************/ +/* Header File */ +#include "stdint.h" + +/*******************************************************************************/ +/* USB Communication Related Macro Definition */ +/* USB Endpoint0 Size */ +#ifndef DEFAULT_ENDP0_SIZE +#define DEFAULT_ENDP0_SIZE 8 // default maximum packet size for endpoint 0 +#endif +#ifndef MAX_PACKET_SIZE +#define MAX_PACKET_SIZE 64 // maximum packet size +#endif + +/* USB PID */ +#ifndef USB_PID_SETUP +#define USB_PID_NULL 0x00 +#define USB_PID_SOF 0x05 +#define USB_PID_SETUP 0x0D +#define USB_PID_IN 0x09 +#define USB_PID_OUT 0x01 +#define USB_PID_NYET 0x06 +#define USB_PID_ACK 0x02 +#define USB_PID_NAK 0x0A +#define USB_PID_STALL 0x0E +#define USB_PID_DATA0 0x03 +#define USB_PID_DATA1 0x0B +#define USB_PID_DATA2 0x07 +#define USB_PID_MDATA 0x0F +#define USB_PID_PRE 0x0C +#endif + +/* USB standard device request code */ +#ifndef USB_GET_DESCRIPTOR +#define USB_GET_STATUS 0x00 +#define USB_CLEAR_FEATURE 0x01 +#define USB_SET_FEATURE 0x03 +#define USB_SET_ADDRESS 0x05 +#define USB_GET_DESCRIPTOR 0x06 +#define USB_SET_DESCRIPTOR 0x07 +#define USB_GET_CONFIGURATION 0x08 +#define USB_SET_CONFIGURATION 0x09 +#define USB_GET_INTERFACE 0x0A +#define USB_SET_INTERFACE 0x0B +#define USB_SYNCH_FRAME 0x0C +#endif + +#define DEF_STRING_DESC_LANG 0x00 +#define DEF_STRING_DESC_MANU 0x01 +#define DEF_STRING_DESC_PROD 0x02 +#define DEF_STRING_DESC_SERN 0x03 + +/* USB hub class request code */ +#ifndef HUB_GET_DESCRIPTOR +#define HUB_GET_STATUS 0x00 +#define HUB_CLEAR_FEATURE 0x01 +#define HUB_GET_STATE 0x02 +#define HUB_SET_FEATURE 0x03 +#define HUB_GET_DESCRIPTOR 0x06 +#define HUB_SET_DESCRIPTOR 0x07 +#endif + +/* USB HID class request code */ +#ifndef HID_GET_REPORT +#define HID_GET_REPORT 0x01 +#define HID_GET_IDLE 0x02 +#define HID_GET_PROTOCOL 0x03 +#define HID_SET_REPORT 0x09 +#define HID_SET_IDLE 0x0A +#define HID_SET_PROTOCOL 0x0B +#endif + +/* USB CDC Class request code */ +#ifndef CDC_GET_LINE_CODING +#define CDC_GET_LINE_CODING 0x21 /* This request allows the host to find out the currently configured line coding */ +#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */ +#define CDC_SET_LINE_CTLSTE 0x22 /* This request generates RS-232/V.24 style control signals */ +#define CDC_SEND_BREAK 0x23 /* Sends special carrier modulation used to specify RS-232 style break */ +#endif + +/* Bit Define for USB Request Type */ +#ifndef USB_REQ_TYP_MASK +#define USB_REQ_TYP_IN 0x80 +#define USB_REQ_TYP_OUT 0x00 +#define USB_REQ_TYP_READ 0x80 +#define USB_REQ_TYP_WRITE 0x00 +#define USB_REQ_TYP_MASK 0x60 +#define USB_REQ_TYP_STANDARD 0x00 +#define USB_REQ_TYP_CLASS 0x20 +#define USB_REQ_TYP_VENDOR 0x40 +#define USB_REQ_TYP_RESERVED 0x60 +#define USB_REQ_RECIP_MASK 0x1F +#define USB_REQ_RECIP_DEVICE 0x00 +#define USB_REQ_RECIP_INTERF 0x01 +#define USB_REQ_RECIP_ENDP 0x02 +#define USB_REQ_RECIP_OTHER 0x03 +#define USB_REQ_FEAT_REMOTE_WAKEUP 0x01 +#define USB_REQ_FEAT_ENDP_HALT 0x00 +#endif + +/* USB Descriptor Type */ +#ifndef USB_DESCR_TYP_DEVICE +#define USB_DESCR_TYP_DEVICE 0x01 +#define USB_DESCR_TYP_CONFIG 0x02 +#define USB_DESCR_TYP_STRING 0x03 +#define USB_DESCR_TYP_INTERF 0x04 +#define USB_DESCR_TYP_ENDP 0x05 +#define USB_DESCR_TYP_QUALIF 0x06 +#define USB_DESCR_TYP_SPEED 0x07 +#define USB_DESCR_TYP_OTG 0x09 +#define USB_DESCR_TYP_BOS 0X0F +#define USB_DESCR_TYP_HID 0x21 +#define USB_DESCR_TYP_REPORT 0x22 +#define USB_DESCR_TYP_PHYSIC 0x23 +#define USB_DESCR_TYP_CS_INTF 0x24 +#define USB_DESCR_TYP_CS_ENDP 0x25 +#define USB_DESCR_TYP_HUB 0x29 +#endif + +/* USB Device Class */ +#ifndef USB_DEV_CLASS_HUB +#define USB_DEV_CLASS_RESERVED 0x00 +#define USB_DEV_CLASS_AUDIO 0x01 +#define USB_DEV_CLASS_COMMUNIC 0x02 +#define USB_DEV_CLASS_HID 0x03 +#define USB_DEV_CLASS_MONITOR 0x04 +#define USB_DEV_CLASS_PHYSIC_IF 0x05 +#define USB_DEV_CLASS_POWER 0x06 +#define USB_DEV_CLASS_IMAGE 0x06 +#define USB_DEV_CLASS_PRINTER 0x07 +#define USB_DEV_CLASS_STORAGE 0x08 +#define USB_DEV_CLASS_HUB 0x09 +#define USB_DEV_CLASS_VEN_SPEC 0xFF +#endif + +/* USB Hub Class Request */ +#ifndef HUB_GET_HUB_DESCRIPTOR +#define HUB_CLEAR_HUB_FEATURE 0x20 +#define HUB_CLEAR_PORT_FEATURE 0x23 +#define HUB_GET_BUS_STATE 0xA3 +#define HUB_GET_HUB_DESCRIPTOR 0xA0 +#define HUB_GET_HUB_STATUS 0xA0 +#define HUB_GET_PORT_STATUS 0xA3 +#define HUB_SET_HUB_DESCRIPTOR 0x20 +#define HUB_SET_HUB_FEATURE 0x20 +#define HUB_SET_PORT_FEATURE 0x23 +#endif + +/* Hub Class Feature Selectors */ +#ifndef HUB_PORT_RESET +#define HUB_C_HUB_LOCAL_POWER 0 +#define HUB_C_HUB_OVER_CURRENT 1 +#define HUB_PORT_CONNECTION 0 +#define HUB_PORT_ENABLE 1 +#define HUB_PORT_SUSPEND 2 +#define HUB_PORT_OVER_CURRENT 3 +#define HUB_PORT_RESET 4 +#define HUB_PORT_POWER 8 +#define HUB_PORT_LOW_SPEED 9 +#define HUB_C_PORT_CONNECTION 16 +#define HUB_C_PORT_ENABLE 17 +#define HUB_C_PORT_SUSPEND 18 +#define HUB_C_PORT_OVER_CURRENT 19 +#define HUB_C_PORT_RESET 20 +#endif + +/* USB UDisk */ +#ifndef USB_BO_CBW_SIZE +#define USB_BO_CBW_SIZE 0x1F +#define USB_BO_CSW_SIZE 0x0D +#endif +#ifndef USB_BO_CBW_SIG0 +#define USB_BO_CBW_SIG0 0x55 +#define USB_BO_CBW_SIG1 0x53 +#define USB_BO_CBW_SIG2 0x42 +#define USB_BO_CBW_SIG3 0x43 +#define USB_BO_CSW_SIG0 0x55 +#define USB_BO_CSW_SIG1 0x53 +#define USB_BO_CSW_SIG2 0x42 +#define USB_BO_CSW_SIG3 0x53 +#endif + + +/******************************************************************************/ +/* USBHS Clock Configuration Related Macro Definition */ +#define USB_CLK_SRC 0x80000000 +#define USBHS_PLL_ALIVE 0x40000000 +#define USBHS_PLL_CKREF_MASK 0x30000000 +#define USBHS_PLL_CKREF_3M 0x00000000 +#define USBHS_PLL_CKREF_4M 0x10000000 +#define USBHS_PLL_CKREF_8M 0x20000000 +#define USBHS_PLL_CKREF_5M 0x30000000 +#define USBHS_PLL_SRC 0x08000000 +#define USBHS_PLL_SRC_PRE_MASK 0x07000000 +#define USBHS_PLL_SRC_PRE_DIV1 0x00000000 +#define USBHS_PLL_SRC_PRE_DIV2 0x01000000 +#define USBHS_PLL_SRC_PRE_DIV3 0x02000000 +#define USBHS_PLL_SRC_PRE_DIV4 0x03000000 +#define USBHS_PLL_SRC_PRE_DIV5 0x04000000 +#define USBHS_PLL_SRC_PRE_DIV6 0x05000000 +#define USBHS_PLL_SRC_PRE_DIV7 0x06000000 +#define USBHS_PLL_SRC_PRE_DIV8 0x07000000 + + +/*******************************************************************************/ +/* USBHS Related Register Macro Definition */ + +/* R8_USB_CTRL */ +#define USBHS_UC_HOST_MODE 0x80 +#define USBHS_UC_SPEED_TYPE 0x60 +#define USBHS_UC_SPEED_LOW 0x40 +#define USBHS_UC_SPEED_FULL 0x00 +#define USBHS_UC_SPEED_HIGH 0x20 +#define USBHS_UC_DEV_PU_EN 0x10 +#define USBHS_UC_INT_BUSY 0x08 +#define USBHS_UC_RESET_SIE 0x04 +#define USBHS_UC_CLR_ALL 0x02 +#define USBHS_UC_DMA_EN 0x01 + +/* R8_USB_INT_EN */ +#define USBHS_UIE_DEV_NAK 0x80 +#define USBHS_UIE_ISO_ACT 0x40 +#define USBHS_UIE_SETUP_ACT 0x20 +#define USBHS_UIE_FIFO_OV 0x10 +#define USBHS_UIE_SOF_ACT 0x08 +#define USBHS_UIE_SUSPEND 0x04 +#define USBHS_UIE_TRANSFER 0x02 +#define USBHS_UIE_DETECT 0x01 +#define USBHS_UIE_BUS_RST 0x01 + +/* R16_USB_DEV_AD */ +#define USBHS_MASK_USB_ADDR 0x7F + +/* R16_USB_FRAME_NO */ +#define USBHS_MICRO_FRAME_NUM 0xE000 +#define USBHS_SOF_FRAME_NUM 0x07FF + +/* R8_USB_SUSPEND */ +#define USBHS_USB_LINESTATE 0x30 +#define USBHS_USB_WAKEUP_ST 0x04 +#define USBHS_USB_SYS_MOD 0x03 + +/* R8_USB_SPEED_TYPE */ +#define USBHS_USB_SPEED_TYPE 0x03 +#define USBHS_USB_SPEED_LOW 0x02 +#define USBHS_USB_SPEED_FULL 0x00 +#define USBHS_USB_SPEED_HIGH 0x01 + +/* R8_USB_MIS_ST */ +#define USBHS_UMS_SOF_PRES 0x80 +#define USBHS_UMS_SOF_ACT 0x40 +#define USBHS_UMS_SIE_FREE 0x20 +#define USBHS_UMS_R_FIFO_RDY 0x10 +#define USBHS_UMS_BUS_RESET 0x08 +#define USBHS_UMS_SUSPEND 0x04 +#define USBHS_UMS_DEV_ATTACH 0x02 +#define USBHS_UMS_SPLIT_CAN 0x01 + +/* R8_USB_INT_FG */ +#define USBHS_UIF_ISO_ACT 0x40 +#define USBHS_UIF_SETUP_ACT 0x20 +#define USBHS_UIF_FIFO_OV 0x10 +#define USBHS_UIF_HST_SOF 0x08 +#define USBHS_UIF_SUSPEND 0x04 +#define USBHS_UIF_TRANSFER 0x02 +#define USBHS_UIF_DETECT 0x01 +#define USBHS_UIF_BUS_RST 0x01 + +/* R8_USB_INT_ST */ +#define USBHS_UIS_IS_NAK 0x80 +#define USBHS_UIS_TOG_OK 0x40 +#define USBHS_UIS_TOKEN_MASK 0x30 +#define USBHS_UIS_TOKEN_OUT 0x00 +#define USBHS_UIS_TOKEN_SOF 0x10 +#define USBHS_UIS_TOKEN_IN 0x20 +#define USBHS_UIS_TOKEN_SETUP 0x30 +#define USBHS_UIS_ENDP_MASK 0x0F +#define USBHS_UIS_H_RES_MASK 0x0F + +/* R16_USB_RX_LEN */ +#define USBHS_USB_RX_LEN 0xFFFF + +/* R32_UEP_CONFIG */ +#define USBHS_UEP15_R_EN 0x80000000 +#define USBHS_UEP14_R_EN 0x40000000 +#define USBHS_UEP13_R_EN 0x20000000 +#define USBHS_UEP12_R_EN 0x10000000 +#define USBHS_UEP11_R_EN 0x08000000 +#define USBHS_UEP10_R_EN 0x04000000 +#define USBHS_UEP9_R_EN 0x02000000 +#define USBHS_UEP8_R_EN 0x01000000 +#define USBHS_UEP7_R_EN 0x00800000 +#define USBHS_UEP6_R_EN 0x00400000 +#define USBHS_UEP5_R_EN 0x00200000 +#define USBHS_UEP4_R_EN 0x00100000 +#define USBHS_UEP3_R_EN 0x00080000 +#define USBHS_UEP2_R_EN 0x00040000 +#define USBHS_UEP1_R_EN 0x00020000 +#define USBHS_UEP0_R_EN 0x00010000 +#define USBHS_UEP15_T_EN 0x00008000 +#define USBHS_UEP14_T_EN 0x00004000 +#define USBHS_UEP13_T_EN 0x00002000 +#define USBHS_UEP12_T_EN 0x00001000 +#define USBHS_UEP11_T_EN 0x00000800 +#define USBHS_UEP10_T_EN 0x00000400 +#define USBHS_UEP9_T_EN 0x00000200 +#define USBHS_UEP8_T_EN 0x00000100 +#define USBHS_UEP7_T_EN 0x00000080 +#define USBHS_UEP6_T_EN 0x00000040 +#define USBHS_UEP5_T_EN 0x00000020 +#define USBHS_UEP4_T_EN 0x00000010 +#define USBHS_UEP3_T_EN 0x00000008 +#define USBHS_UEP2_T_EN 0x00000004 +#define USBHS_UEP1_T_EN 0x00000002 +#define USBHS_UEP0_T_EN 0x00000001 + +/* R32_UEP_TYPE */ +#define USBHS_UEP15_R_TYPE 0x80000000 +#define USBHS_UEP14_R_TYPE 0x40000000 +#define USBHS_UEP13_R_TYPE 0x20000000 +#define USBHS_UEP12_R_TYPE 0x10000000 +#define USBHS_UEP11_R_TYPE 0x08000000 +#define USBHS_UEP10_R_TYPE 0x04000000 +#define USBHS_UEP9_R_TYPE 0x02000000 +#define USBHS_UEP8_R_TYPE 0x01000000 +#define USBHS_UEP7_R_TYPE 0x00800000 +#define USBHS_UEP6_R_TYPE 0x00400000 +#define USBHS_UEP5_R_TYPE 0x00200000 +#define USBHS_UEP4_R_TYPE 0x00100000 +#define USBHS_UEP3_R_TYPE 0x00080000 +#define USBHS_UEP2_R_TYPE 0x00040000 +#define USBHS_UEP1_R_TYPE 0x00020000 +#define USBHS_UEP0_R_TYPE 0x00010000 +#define USBHS_UEP15_T_TYPE 0x00008000 +#define USBHS_UEP14_T_TYPE 0x00004000 +#define USBHS_UEP13_T_TYPE 0x00002000 +#define USBHS_UEP12_T_TYPE 0x00001000 +#define USBHS_UEP11_T_TYPE 0x00000800 +#define USBHS_UEP10_T_TYPE 0x00000400 +#define USBHS_UEP9_T_TYPE 0x00000200 +#define USBHS_UEP8_T_TYPE 0x00000100 +#define USBHS_UEP7_T_TYPE 0x00000080 +#define USBHS_UEP6_T_TYPE 0x00000040 +#define USBHS_UEP5_T_TYPE 0x00000020 +#define USBHS_UEP4_T_TYPE 0x00000010 +#define USBHS_UEP3_T_TYPE 0x00000008 +#define USBHS_UEP2_T_TYPE 0x00000004 +#define USBHS_UEP1_T_TYPE 0x00000002 +#define USBHS_UEP0_T_TYPE 0x00000001 + +/* R32_UEP_BUF_MOD */ +#define USBHS_UEP15_ISO_BUF_MOD 0x80000000 +#define USBHS_UEP14_ISO_BUF_MOD 0x40000000 +#define USBHS_UEP13_ISO_BUF_MOD 0x20000000 +#define USBHS_UEP12_ISO_BUF_MOD 0x10000000 +#define USBHS_UEP11_ISO_BUF_MOD 0x08000000 +#define USBHS_UEP10_ISO_BUF_MOD 0x04000000 +#define USBHS_UEP9_ISO_BUF_MOD 0x02000000 +#define USBHS_UEP8_ISO_BUF_MOD 0x01000000 +#define USBHS_UEP7_ISO_BUF_MOD 0x00800000 +#define USBHS_UEP6_ISO_BUF_MOD 0x00400000 +#define USBHS_UEP5_ISO_BUF_MOD 0x00200000 +#define USBHS_UEP4_ISO_BUF_MOD 0x00100000 +#define USBHS_UEP3_ISO_BUF_MOD 0x00080000 +#define USBHS_UEP2_ISO_BUF_MOD 0x00040000 +#define USBHS_UEP1_ISO_BUF_MOD 0x00020000 +#define USBHS_UEP0_ISO_BUF_MOD 0x00010000 +#define USBHS_UEP15_BUF_MOD 0x00008000 +#define USBHS_UEP14_BUF_MOD 0x00004000 +#define USBHS_UEP13_BUF_MOD 0x00002000 +#define USBHS_UEP12_BUF_MOD 0x00001000 +#define USBHS_UEP11_BUF_MOD 0x00000800 +#define USBHS_UEP10_BUF_MOD 0x00000400 +#define USBHS_UEP9_BUF_MOD 0x00000200 +#define USBHS_UEP8_BUF_MOD 0x00000100 +#define USBHS_UEP7_BUF_MOD 0x00000080 +#define USBHS_UEP6_BUF_MOD 0x00000040 +#define USBHS_UEP5_BUF_MOD 0x00000020 +#define USBHS_UEP4_BUF_MOD 0x00000010 +#define USBHS_UEP3_BUF_MOD 0x00000008 +#define USBHS_UEP2_BUF_MOD 0x00000004 +#define USBHS_UEP1_BUF_MOD 0x00000002 +#define USBHS_UEP0_BUF_MOD 0x00000001 + +/* R32_UEP0_DMA */ +#define USBHS_UEP0_DMA 0x0000FFFF + +/* R32_UEPn_TX_DMA, n=1-15 */ +#define USBHS_UEPn_TX_DMA 0x0000FFFF + +/* R32_UEPn_RX_DMA, n=1-15 */ +#define USBHS_UEPn_RX_DMA 0x0000FFFF + +/* R16_UEPn_MAX_LEN, n=0-15 */ +#define USBHS_UEPn_MAX_LEN 0x07FF + +/* R16_UEPn_T_LEN, n=0-15 */ +#define USBHS_UEPn_T_LEN 0x07FF + +/* R8_UEPn_TX_CTRL, n=0-15 */ +#define USBHS_UEP_T_TOG_AUTO 0x20 +#define USBHS_UEP_T_TOG_MASK 0x18 +#define USBHS_UEP_T_TOG_DATA0 0x00 +#define USBHS_UEP_T_TOG_DATA1 0x08 +#define USBHS_UEP_T_TOG_DATA2 0x10 +#define USBHS_UEP_T_TOG_MDATA 0x18 +#define USBHS_UEP_T_RES_MASK 0x03 +#define USBHS_UEP_T_RES_ACK 0x00 +#define USBHS_UEP_T_RES_NYET 0x01 +#define USBHS_UEP_T_RES_NAK 0x02 +#define USBHS_UEP_T_RES_STALL 0x03 + +/* R8_UEPn_TX_CTRL, n=0-15 */ +#define USBHS_UEP_R_TOG_AUTO 0x20 +#define USBHS_UEP_R_TOG_MASK 0x18 +#define USBHS_UEP_R_TOG_DATA0 0x00 +#define USBHS_UEP_R_TOG_DATA1 0x08 +#define USBHS_UEP_R_TOG_DATA2 0x10 +#define USBHS_UEP_R_TOG_MDATA 0x18 +#define USBHS_UEP_R_RES_MASK 0x03 +#define USBHS_UEP_R_RES_ACK 0x00 +#define USBHS_UEP_R_RES_NYET 0x01 +#define USBHS_UEP_R_RES_NAK 0x02 +#define USBHS_UEP_R_RES_STALL 0x03 + +/* R8_UHOST_CTRL */ +#define USBHS_UH_SOF_EN 0x80 +#define USBHS_UH_SOF_FREE 0x40 +#define USBHS_UH_PHY_SUSPENDM 0x10 +#define USBHS_UH_REMOTE_WKUP 0x08 +#define USBHS_UH_TX_BUS_RESUME 0x04 +#define USBHS_UH_TX_BUS_SUSPEND 0x02 +#define USBHS_UH_TX_BUS_RESET 0x01 + +/* R32_UH_CONFIG */ +#define USBHS_UH_EP_RX_EN 0x00040000 +#define USBHS_UH_EP_TX_EN 0x00000008 + +/* R32_UH_EP_TYPE */ +#define USBHS_UH_EP_RX_TYPE 0x00040000 +#define USBHS_UH_EP_TX_TYPE 0x00000008 + +/* R32_UH_RX_DMA */ +#define USBHS_UH_RX_DMA 0x0000FFFC + +/* R32_UH_TX_DMA */ +#define USBHS_UH_TX_DMA 0x0000FFFF + +/* R16_UH_RX_MAX_LEN */ +#define USBHS_UH_RX_MAX_LEN 0x07FF + +/* R8_UH_EP_PID */ +#define USBHS_UH_TOKEN_MASK 0xF0 +#define USBHS_UH_ENDP_MASK 0x0F + +/* R8_UH_RX_CTRL */ +#define USBHS_UH_R_DATA_NO 0x40 +#define USBHS_UH_R_TOG_AUTO 0x20 +#define USBHS_UH_R_TOG_MASK 0x18 +#define USBHS_UH_R_TOG_DATA0 0x00 +#define USBHS_UH_R_TOG_DATA1 0x08 +#define USBHS_UH_R_TOG_DATA2 0x10 +#define USBHS_UH_R_TOG_MDATA 0x18 +#define USBHS_UH_R_RES_NO 0x04 +#define USBHS_UH_R_RES_MASK 0x03 +#define USBHS_UH_R_RES_ACK 0x00 +#define USBHS_UH_R_RES_NYET 0x01 +#define USBHS_UH_R_RES_NAK 0x02 +#define USBHS_UH_R_RES_STALL 0x03 + +/* R16_UH_TX_LEN */ +#define USBHS_UH_TX_LEN 0x07FF + +/* R8_UH_TX_CTRL */ +#define USBHS_UH_T_DATA_NO 0x40 +#define USBHS_UH_T_AUTO_TOG 0x20 +#define USBHS_UH_T_TOG_MASK 0x18 +#define USBHS_UH_T_TOG_DATA0 0x00 +#define USBHS_UH_T_TOG_DATA1 0x08 +#define USBHS_UH_T_TOG_DATA2 0x10 +#define USBHS_UH_T_TOG_MDATA 0x18 +#define USBHS_UH_T_RES_NO 0x04 +#define USBHS_UH_T_RES_MASK 0x03 +#define USBHS_UH_T_RES_ACK 0x00 +#define USBHS_UH_T_RES_NYET 0x01 +#define USBHS_UH_T_RES_NAK 0x02 +#define USBHS_UH_T_RES_STALL 0x03 + +/* R16_UH_SPLIT_DATA */ +#define USBHS_UH_SPLIT_DATA 0x0FFF + + +/*******************************************************************************/ +/* USBFS Related Register Macro Definition */ + +/* R8_USB_CTRL */ +#define USBFS_UC_HOST_MODE 0x80 +#define USBFS_UC_LOW_SPEED 0x40 +#define USBFS_UC_DEV_PU_EN 0x20 +#define USBFS_UC_SYS_CTRL_MASK 0x30 +#define USBFS_UC_SYS_CTRL0 0x00 +#define USBFS_UC_SYS_CTRL1 0x10 +#define USBFS_UC_SYS_CTRL2 0x20 +#define USBFS_UC_SYS_CTRL3 0x30 +#define USBFS_UC_INT_BUSY 0x08 +#define USBFS_UC_RESET_SIE 0x04 +#define USBFS_UC_CLR_ALL 0x02 +#define USBFS_UC_DMA_EN 0x01 + +/* R8_USB_INT_EN */ +#define USBFS_UIE_DEV_SOF 0x80 +#define USBFS_UIE_DEV_NAK 0x40 +#define USBFS_1WIRE_MODE 0x20 +#define USBFS_UIE_FIFO_OV 0x10 +#define USBFS_UIE_HST_SOF 0x08 +#define USBFS_UIE_SUSPEND 0x04 +#define USBFS_UIE_TRANSFER 0x02 +#define USBFS_UIE_DETECT 0x01 +#define USBFS_UIE_BUS_RST 0x01 + +/* R8_USB_DEV_AD */ +#define USBFS_UDA_GP_BIT 0x80 +#define USBFS_USB_ADDR_MASK 0x7F + +/* R8_USB_MIS_ST */ +#define USBFS_UMS_SOF_PRES 0x80 +#define USBFS_UMS_SOF_ACT 0x40 +#define USBFS_UMS_SIE_FREE 0x20 +#define USBFS_UMS_R_FIFO_RDY 0x10 +#define USBFS_UMS_BUS_RESET 0x08 +#define USBFS_UMS_SUSPEND 0x04 +#define USBFS_UMS_DM_LEVEL 0x02 +#define USBFS_UMS_DEV_ATTACH 0x01 + +/* R8_USB_INT_FG */ +#define USBFS_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received +#define USBFS_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_U_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define USBFS_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear +#define USBFS_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear +#define USBFS_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear +#define USBFS_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear + +/* R8_USB_INT_ST */ +#define USBFS_UIS_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode +#define USBFS_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode +#define USBFS_UIS_TOKEN_OUT 0x00 +#define USBFS_UIS_TOKEN_SOF 0x10 +#define USBFS_UIS_TOKEN_IN 0x20 +#define USBFS_UIS_TOKEN_SETUP 0x30 +// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode +// 00: OUT token PID received +// 01: SOF token PID received +// 10: IN token PID received +// 11: SETUP token PID received +#define USBFS_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode +#define USBFS_UIS_H_RES_MASK 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received + +/* R32_USB_OTG_CR */ +#define USBFS_CR_SESS_VTH 0x20 +#define USBFS_CR_VBUS_VTH 0x10 +#define USBFS_CR_OTG_EN 0x08 +#define USBFS_CR_IDPU 0x04 +#define USBFS_CR_CHARGE_VBUS 0x02 +#define USBFS_CR_DISCHAR_VBUS 0x01 + +/* R32_USB_OTG_SR */ +#define USBFS_SR_ID_DIG 0x08 +#define USBFS_SR_SESS_END 0x04 +#define USBFS_SR_SESS_VLD 0x02 +#define USBFS_SR_VBUS_VLD 0x01 + +/* R8_UDEV_CTRL */ +#define USBFS_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed +#define USBFS_UD_GP_BIT 0x02 // general purpose bit +#define USBFS_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable + +/* R8_UEP4_1_MOD */ +#define USBFS_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) +#define USBFS_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) +#define USBFS_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 +#define USBFS_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) +#define USBFS_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) +#define USBFS_UEP4_BUF_MOD 0x01 + +/* R8_UEP2_3_MOD */ +#define USBFS_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) +#define USBFS_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) +#define USBFS_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 +#define USBFS_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) +#define USBFS_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) +#define USBFS_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 + +/* R8_UEP5_6_MOD */ +#define USBFS_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT) +#define USBFS_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN) +#define USBFS_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6 +#define USBFS_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT) +#define USBFS_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN) +#define USBFS_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5 + +/* R8_UEP7_MOD */ +#define USBFS_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT) +#define USBFS_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN) +#define USBFS_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7 + +/* R8_UEPn_TX_CTRL */ +#define USBFS_UEP_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_T_TOG 0x04 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 +#define USBFS_UEP_T_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define USBFS_UEP_T_RES_ACK 0x00 +#define USBFS_UEP_T_RES_NONE 0x01 +#define USBFS_UEP_T_RES_NAK 0x02 +#define USBFS_UEP_T_RES_STALL 0x03 +// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) +// 00: DATA0 or DATA1 then expecting ACK (ready) +// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) +// host aux setup + +/* R8_UEPn_RX_CTRL, n=0-7 */ +#define USBFS_UEP_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_R_TOG 0x04 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define USBFS_UEP_R_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define USBFS_UEP_R_RES_ACK 0x00 +#define USBFS_UEP_R_RES_NONE 0x01 +#define USBFS_UEP_R_RES_NAK 0x02 +#define USBFS_UEP_R_RES_STALL 0x03 +// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) +// 00: ACK (ready) +// 01: no response, time out to host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) + +/* R8_UHOST_CTRL */ +#define USBFS_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed +#define USBFS_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset +#define USBFS_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached + +/* R32_UH_EP_MOD */ +#define USBFS_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal +#define USBFS_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint +// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for transmittal (OUT endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes +#define USBFS_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving +#define USBFS_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint +// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for receiving (IN endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes + +/* R16_UH_SETUP */ +#define USBFS_UH_PRE_PID_EN 0x0400 // USB host PRE PID enable for low speed device via hub +#define USBFS_UH_SOF_EN 0x0004 // USB host automatic SOF enable + +/* R8_UH_EP_PID */ +#define USBFS_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer +#define USBFS_UH_ENDP_MASK 0x0F // bit mask of endpoint number for USB host transfer + +/* R8_UH_RX_CTRL */ +#define USBFS_UH_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBFS_UH_R_TOG 0x04 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 +#define USBFS_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions + +/* R8_UH_TX_CTRL */ +#define USBFS_UH_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBFS_UH_T_TOG 0x04 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 +#define USBFS_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions + + +/*******************************************************************************/ +/* Struct Definition */ + +/* USB Setup Request */ +typedef struct __attribute__((packed)) _USB_SETUP_REQ +{ + uint8_t bRequestType; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; +} USB_SETUP_REQ, *PUSB_SETUP_REQ; + +/* USB Device Descriptor */ +typedef struct __attribute__((packed)) _USB_DEVICE_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdUSB; + uint8_t bDeviceClass; + uint8_t bDeviceSubClass; + uint8_t bDeviceProtocol; + uint8_t bMaxPacketSize0; + uint16_t idVendor; + uint16_t idProduct; + uint16_t bcdDevice; + uint8_t iManufacturer; + uint8_t iProduct; + uint8_t iSerialNumber; + uint8_t bNumConfigurations; +} USB_DEV_DESCR, *PUSB_DEV_DESCR; + +/* USB Configuration Descriptor */ +typedef struct __attribute__((packed)) _USB_CONFIG_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumInterfaces; + uint8_t bConfigurationValue; + uint8_t iConfiguration; + uint8_t bmAttributes; + uint8_t MaxPower; +} USB_CFG_DESCR, *PUSB_CFG_DESCR; + +/* USB Interface Descriptor */ +typedef struct __attribute__((packed)) _USB_INTERF_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bInterfaceNumber; + uint8_t bAlternateSetting; + uint8_t bNumEndpoints; + uint8_t bInterfaceClass; + uint8_t bInterfaceSubClass; + uint8_t bInterfaceProtocol; + uint8_t iInterface; +} USB_ITF_DESCR, *PUSB_ITF_DESCR; + +/* USB Endpoint Descriptor */ +typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint8_t wMaxPacketSizeL; + uint8_t wMaxPacketSizeH; + uint8_t bInterval; +} USB_ENDP_DESCR, *PUSB_ENDP_DESCR; + +/* USB Configuration Descriptor Set */ +typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG +{ + USB_CFG_DESCR cfg_descr; + USB_ITF_DESCR itf_descr; + USB_ENDP_DESCR endp_descr[ 1 ]; +} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG; + +/* USB HUB Descriptor */ +typedef struct __attribute__((packed)) _USB_HUB_DESCR +{ + uint8_t bDescLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint8_t wHubCharacteristicsL; + uint8_t wHubCharacteristicsH; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint8_t DeviceRemovable; + uint8_t PortPwrCtrlMask; +} USB_HUB_DESCR, *PUSB_HUB_DESCR; + +/* USB HID Descriptor */ +typedef struct __attribute__((packed)) _USB_HID_DESCR +{ + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdHID; + uint8_t bCountryCode; + uint8_t bNumDescriptors; + uint8_t bDescriptorTypeX; + uint8_t wDescriptorLengthL; + uint8_t wDescriptorLengthH; +} USB_HID_DESCR, *PUSB_HID_DESCR; + +/* USB UDisk */ +typedef struct __attribute__((packed)) _UDISK_BOC_CBW +{ + uint32_t mCBW_Sig; + uint32_t mCBW_Tag; + uint32_t mCBW_DataLen; + uint8_t mCBW_Flag; + uint8_t mCBW_LUN; + uint8_t mCBW_CB_Len; + uint8_t mCBW_CB_Buf[ 16 ]; +} UDISK_BOC_CBW, *PXUDISK_BOC_CBW; + +/* USB UDisk */ +typedef struct __attribute__((packed)) _UDISK_BOC_CSW +{ + uint32_t mCBW_Sig; + uint32_t mCBW_Tag; + uint32_t mCSW_Residue; + uint8_t mCSW_Status; +} UDISK_BOC_CSW, *PXUDISK_BOC_CSW; + + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V30x_USB_H */ diff --git a/Peripheral/inc/ch32v30x_wwdg.h b/Peripheral/inc/ch32v30x_wwdg.h new file mode 100644 index 0000000..809b2ec --- /dev/null +++ b/Peripheral/inc/ch32v30x_wwdg.h @@ -0,0 +1,44 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_wwdg.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains all the functions prototypes for the WWDG +* firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_WWDG_H +#define __CH32V30x_WWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v30x.h" + + +/* WWDG_Prescaler */ +#define WWDG_Prescaler_1 ((uint32_t)0x00000000) +#define WWDG_Prescaler_2 ((uint32_t)0x00000080) +#define WWDG_Prescaler_4 ((uint32_t)0x00000100) +#define WWDG_Prescaler_8 ((uint32_t)0x00000180) + + +void WWDG_DeInit(void); +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler); +void WWDG_SetWindowValue(uint8_t WindowValue); +void WWDG_EnableIT(void); +void WWDG_SetCounter(uint8_t Counter); +void WWDG_Enable(uint8_t Counter); +FlagStatus WWDG_GetFlagStatus(void); +void WWDG_ClearFlag(void); + +#ifdef __cplusplus +} +#endif + +#endif + diff --git a/Peripheral/src/ch32v30x_adc.c b/Peripheral/src/ch32v30x_adc.c new file mode 100644 index 0000000..54ed35e --- /dev/null +++ b/Peripheral/src/ch32v30x_adc.c @@ -0,0 +1,1182 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_adc.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the ADC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_adc.h" +#include "ch32v30x_rcc.h" + +/* ADC DISCNUM mask */ +#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) +#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) +#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +/* CTLR1 register Mask */ +#define CTLR1_CLEAR_Mask ((uint32_t)0xE0F0FEFF) + +/* ADC ADON mask */ +#define CTLR2_ADON_Set ((uint32_t)0x00000001) +#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CTLR2_DMA_Set ((uint32_t)0x00000100) +#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CTLR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CTLR2 register Mask */ +#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define RSQR3_SQ_Set ((uint32_t)0x0000001F) +#define RSQR2_SQ_Set ((uint32_t)0x0000001F) +#define RSQR1_SQ_Set ((uint32_t)0x0000001F) + +/* RSQR1 register Mask */ +#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define ISQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define ISQR_JL_Set ((uint32_t)0x00300000) +#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) +#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC IDATARx registers offset */ +#define IDATAR_Offset ((uint8_t)0x28) + +/* ADC1 RDATAR register base address */ +#define RDATAR_ADDRESS ((uint32_t)0x4001244C) + +/********************************************************************* + * @fn ADC_DeInit + * + * @brief Deinitializes the ADCx peripheral registers to their default + * reset values. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return none + */ +void ADC_DeInit(ADC_TypeDef *ADCx) +{ + if(ADCx == ADC1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + } + else if(ADCx == ADC2) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC2, DISABLE); + } +} + +/********************************************************************* + * @fn ADC_Init + * + * @brief Initializes the ADCx peripheral according to the specified + * parameters in the ADC_InitStruct. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | (uint32_t)ADC_InitStruct->ADC_OutputBuffer | + (uint32_t)ADC_InitStruct->ADC_Pga | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); + ADCx->CTLR1 = tmpreg1; + + tmpreg1 = ADCx->CTLR2; + tmpreg1 &= CTLR2_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | + ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + ADCx->CTLR2 = tmpreg1; + + tmpreg1 = ADCx->RSQR1; + tmpreg1 &= RSQR1_CLEAR_Mask; + tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + ADCx->RSQR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_StructInit + * + * @brief Fills each ADC_InitStruct member with its default value. + * + * @param ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct) +{ + ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStruct->ADC_NbrOfChannel = 1; +} + +/********************************************************************* + * @fn ADC_Cmd + * + * @brief Enables or disables the specified ADC peripheral. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_ADON_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_ADON_Reset; + } +} + +/********************************************************************* + * @fn ADC_DMACmd + * + * @brief Enables or disables the specified ADC DMA request. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_DMA_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_DMA_Reset; + } +} + +/********************************************************************* + * @fn ADC_ITConfig + * + * @brief Enables or disables the specified ADC interrupts. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt sources to be enabled or disabled. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)ADC_IT; + + if(NewState != DISABLE) + { + ADCx->CTLR1 |= itmask; + } + else + { + ADCx->CTLR1 &= (~(uint32_t)itmask); + } +} + +/********************************************************************* + * @fn ADC_ResetCalibration + * + * @brief Resets the selected ADC calibration registers. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return none + */ +void ADC_ResetCalibration(ADC_TypeDef *ADCx) +{ + ADCx->CTLR2 |= CTLR2_RSTCAL_Set; +} + +/********************************************************************* + * @fn ADC_GetResetCalibrationStatus + * + * @brief Gets the selected ADC reset calibration registers status. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_RSTCAL_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_StartCalibration + * + * @brief Starts the selected ADC calibration process. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return None + */ +void ADC_StartCalibration(ADC_TypeDef *ADCx) +{ + ADCx->CTLR2 |= CTLR2_CAL_Set; +} + +/********************************************************************* + * @fn ADC_GetCalibrationStatus + * + * @brief Gets the selected ADC calibration status. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_CAL_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_SoftwareStartConvCmd + * + * @brief Enables or disables the selected ADC software start conversion. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_SWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_SWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartConvStatus + * + * @brief Gets the selected ADC Software start conversion Status. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_SWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_DiscModeChannelCountConfig + * + * @brief Configures the discontinuous mode for the selected ADC regular + * group channel. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * Number - specifies the discontinuous mode regular channel + * count value(1-8). + * + * @return None + */ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_DISCNUM_Reset; + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + ADCx->CTLR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_DiscModeCmd + * + * @brief Enables or disables the discontinuous mode on regular group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_DISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_DISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_RegularChannelConfig + * + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 16. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles. + * ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles. + * ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles. + * ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles. + * ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles. + * ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles. + * ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles. + * ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles. + * + * @return None + */ +void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + if(Rank < 7) + { + tmpreg1 = ADCx->RSQR3; + tmpreg2 = RSQR3_SQ_Set << (5 * (Rank - 1)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + tmpreg1 |= tmpreg2; + ADCx->RSQR3 = tmpreg1; + } + else if(Rank < 13) + { + tmpreg1 = ADCx->RSQR2; + tmpreg2 = RSQR2_SQ_Set << (5 * (Rank - 7)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + tmpreg1 |= tmpreg2; + ADCx->RSQR2 = tmpreg1; + } + else + { + tmpreg1 = ADCx->RSQR1; + tmpreg2 = RSQR1_SQ_Set << (5 * (Rank - 13)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + tmpreg1 |= tmpreg2; + ADCx->RSQR1 = tmpreg1; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigConvCmd + * + * @brief Enables or disables the ADCx conversion through external trigger. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetConversionValue + * + * @brief Returns the last ADCx conversion result data for regular channel. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return ADCx->RDATAR - The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx) +{ + return (uint16_t)ADCx->RDATAR; +} + +/********************************************************************* + * @fn ADC_GetDualModeConversionValue + * + * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode. + * + * @return RDATAR_ADDRESS - The Data conversion value. + */ +uint32_t ADC_GetDualModeConversionValue(void) +{ + return (*(__IO uint32_t *)RDATAR_ADDRESS); +} + +/********************************************************************* + * @fn ADC_AutoInjectedConvCmd + * + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JAUTO_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JAUTO_Reset; + } +} + +/********************************************************************* + * @fn ADC_InjectedDiscModeCmd + * + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JDISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JDISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvConfig + * + * @brief Configures the ADCx external trigger for injected channels conversion. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_ExternalTrigInjecConv - specifies the ADC trigger to start + * injected conversion. + * ADC_ExternalTrigInjecConv_T1_TRGO - Timer1 TRGO event selected. + * ADC_ExternalTrigInjecConv_T1_CC4 - Timer1 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T2_TRGO - Timer2 TRGO event selected. + * ADC_ExternalTrigInjecConv_T2_CC1 - Timer2 capture compare1 selected. + * ADC_ExternalTrigInjecConv_T3_CC4 - Timer3 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T4_TRGO - Timer4 TRGO event selected. + * ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 - External interrupt + * line 15 event selected. + * ADC_ExternalTrigInjecConv_None: Injected conversion started + * by software and not by external trigger. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR2; + tmpreg &= CTLR2_JEXTSEL_Reset; + tmpreg |= ADC_ExternalTrigInjecConv; + ADCx->CTLR2 = tmpreg; +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvCmd + * + * @brief Enables or disables the ADCx injected channels conversion through + * external trigger. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_SoftwareStartInjectedConvCmd + * + * @brief Enables or disables the selected ADC start of the injected + * channels conversion. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_JSWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_JSWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartInjectedConvCmdStatus + * + * @brief Gets the selected ADC Software start injected conversion Status. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_JSWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_InjectedChannelConfig + * + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 4. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles. + * ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles. + * ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles. + * ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles. + * ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles. + * ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles. + * ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles. + * ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles. + * + * @return None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + tmpreg1 = ADCx->ISQR; + tmpreg3 = (tmpreg1 & ISQR_JL_Set) >> 20; + tmpreg2 = ISQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 |= tmpreg2; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_InjectedSequencerLengthConfig + * + * @brief Configures the sequencer length for injected channels. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * Length - The sequencer length. + * This parameter must be a number between 1 to 4. + * + * @return None + */ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->ISQR; + tmpreg1 &= ISQR_JL_Reset; + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_SetInjectedOffset + * + * @brief Set the injected channels conversion value offset. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_InjectedChannel: the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * Offset - the offset value for the selected ADC injected channel. + * This parameter must be a 12bit value. + * + * @return None + */ +void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + *(__IO uint32_t *)tmp = (uint32_t)Offset; +} + +/********************************************************************* + * @fn ADC_GetInjectedConversionValue + * + * @brief Returns the ADC injected channel conversion result. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_InjectedChannel - the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * + * @return tmp - The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + IDATAR_Offset; + + return (uint16_t)(*(__IO uint32_t *)tmp); +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogCmd + * + * @brief Enables or disables the analog watchdog on single/all regular + * or injected channels. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_AnalogWatchdog - the ADC analog watchdog configuration. + * ADC_AnalogWatchdog_SingleRegEnable - Analog watchdog on a + * single regular channel. + * ADC_AnalogWatchdog_SingleInjecEnable - Analog watchdog on a + * single injected channel. + * ADC_AnalogWatchdog_SingleRegOrInjecEnable - Analog watchdog + * on a single regular or injected channel. + * ADC_AnalogWatchdog_AllRegEnable - Analog watchdog on all + * regular channel. + * ADC_AnalogWatchdog_AllInjecEnable - Analog watchdog on all + * injected channel. + * ADC_AnalogWatchdog_AllRegAllInjecEnable - Analog watchdog on + * all regular and injected channels. + * ADC_AnalogWatchdog_None - No channel guarded by the analog + * watchdog. + * + * @return none + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDMode_Reset; + tmpreg |= ADC_AnalogWatchdog; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogThresholdsConfig + * + * @brief Configures the high and low thresholds of the analog watchdog. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * HighThreshold - the ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * LowThreshold - the ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + * + * @return none + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + ADCx->WDHTR = HighThreshold; + ADCx->WDLTR = LowThreshold; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogSingleChannelConfig + * + * @brief Configures the analog watchdog guarded single channel. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * + * @return None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDCH_Reset; + tmpreg |= ADC_Channel; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_TempSensorVrefintCmd + * + * @brief Enables or disables the temperature sensor and Vrefint channel. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_TempSensorVrefintCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADC1->CTLR2 |= CTLR2_TSVREFE_Set; + } + else + { + ADC1->CTLR2 &= CTLR2_TSVREFE_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetFlagStatus + * + * @brief Checks whether the specified ADC flag is set or not. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to check. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->STATR & ADC_FLAG) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearFlag + * + * @brief Clears the ADCx's pending flags. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to clear. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return none + */ +void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + ADCx->STATR = ~(uint32_t)ADC_FLAG; +} + +/********************************************************************* + * @fn ADC_GetITStatus + * + * @brief Checks whether the specified ADC interrupt has occurred or not. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt source to check. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return FlagStatus: SET or RESET. + */ +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + + itmask = ADC_IT >> 8; + enablestatus = (ADCx->CTLR1 & (uint8_t)ADC_IT); + + if(((ADCx->STATR & itmask) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearITPendingBit + * + * @brief Clears the ADCx's interrupt pending bits. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt pending bit to clear. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return none + */ +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)(ADC_IT >> 8); + ADCx->STATR = ~(uint32_t)itmask; +} + +/********************************************************************* + * @fn TempSensor_Volt_To_Temper + * + * @brief Internal Temperature Sensor Voltage to temperature. + * + * @param Value - Voltage Value(mv). + * + * @return Temper - Temperature Value. + */ +s32 TempSensor_Volt_To_Temper(s32 Value) +{ + s32 Temper, Refer_Volt, Refer_Temper; + s32 k = 43; + + Refer_Volt = (s32)((*(u32 *)0x1FFFF720) & 0x0000FFFF); + Refer_Temper = (s32)(((*(u32 *)0x1FFFF720) >> 16) & 0x0000FFFF); + + Temper = Refer_Temper - ((Value - Refer_Volt) * 10 + (k >> 1)) / k; + + return Temper; +} + +/********************************************************************* + * @fn ADC_BufferCmd + * + * @brief Enables or disables the ADCx buffer. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= (1 << 26); + } + else + { + ADCx->CTLR1 &= ~(1 << 26); + } +} + +/********************************************************************* + * @fn Get_CalibrationValue + * + * @brief Get ADCx Calibration Value. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * + * @return CalibrationValue + */ +int16_t Get_CalibrationValue(ADC_TypeDef *ADCx) +{ + __IO uint8_t i, j; + uint16_t buf[10]; + __IO uint16_t t; + + for(i = 0; i < 10; i++) + { + ADC_ResetCalibration(ADCx); + while(ADC_GetResetCalibrationStatus(ADCx)) + ; + ADC_StartCalibration(ADCx); + while(ADC_GetCalibrationStatus(ADCx)) + ; + buf[i] = ADCx->RDATAR; + } + + for(i = 0; i < 10; i++) + { + for(j = 0; j < 9; j++) + { + if(buf[j] > buf[j + 1]) + { + t = buf[j]; + buf[j] = buf[j + 1]; + buf[j + 1] = t; + } + } + } + + t = 0; + for(i = 0; i < 6; i++) + { + t += buf[i + 2]; + } + + t = (t / 6) + ((t % 6) / 3); + + return (int16_t)(2048 - (int16_t)t); +} diff --git a/Peripheral/src/ch32v30x_bkp.c b/Peripheral/src/ch32v30x_bkp.c new file mode 100644 index 0000000..b76b997 --- /dev/null +++ b/Peripheral/src/ch32v30x_bkp.c @@ -0,0 +1,244 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_bkp.c +* Author : WCH +* Version : V1.0.0 +* Date : 2024/03/06 +* Description : This file provides all the BKP firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_bkp.h" +#include "ch32v30x_rcc.h" + +/* BKP registers bit mask */ + +/* OCTLR register bit mask */ +#define OCTLR_CAL_MASK ((uint16_t)0xFF80) +#define OCTLR_MASK ((uint16_t)0xFC7F) + +/********************************************************************* + * @fn BKP_DeInit + * + * @brief Deinitializes the BKP peripheral registers to their default reset values. + * + * @return none + */ +void BKP_DeInit(void) +{ + RCC_BackupResetCmd(ENABLE); + RCC_BackupResetCmd(DISABLE); +} + +/********************************************************************* + * @fn BKP_TamperPinLevelConfig + * + * @brief Configures the Tamper Pin active level. + * + * @param BKP_TamperPinLevel: specifies the Tamper Pin active level. + * BKP_TamperPinLevel_High - Tamper pin active on high level. + * BKP_TamperPinLevel_Low - Tamper pin active on low level. + * + * @return none + */ +void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel) +{ + if(BKP_TamperPinLevel) + { + BKP->TPCTLR |= (1 << 1); + } + else + { + BKP->TPCTLR &= ~(1 << 1); + } +} + +/********************************************************************* + * @fn BKP_TamperPinCmd + * + * @brief Enables or disables the Tamper Pin activation. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void BKP_TamperPinCmd(FunctionalState NewState) +{ + if(NewState) + { + BKP->TPCTLR |= (1 << 0); + } + else + { + BKP->TPCTLR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn BKP_ITConfig + * + * @brief Enables or disables the Tamper Pin Interrupt. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void BKP_ITConfig(FunctionalState NewState) +{ + if(NewState) + { + BKP->TPCSR |= (1 << 2); + } + else + { + BKP->TPCSR &= ~(1 << 2); + } +} + +/********************************************************************* + * @fn BKP_RTCOutputConfig + * + * @brief Select the RTC output source to output on the Tamper pin. + * + * @param BKP_RTCOutputSource - specifies the RTC output source. + * BKP_RTCOutputSource_None - no RTC output on the Tamper pin. + * BKP_RTCOutputSource_CalibClock - output the RTC clock with + * frequency divided by 64 on the Tamper pin. + * BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal + * on the Tamper pin. + * BKP_RTCOutputSource_Second - output the RTC Second pulse + * signal on the Tamper pin. + * + * @return none + */ +void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource) +{ + uint16_t tmpreg = 0; + + tmpreg = BKP->OCTLR; + tmpreg &= OCTLR_MASK; + tmpreg |= BKP_RTCOutputSource; + BKP->OCTLR = tmpreg; +} + +/********************************************************************* + * @fn BKP_SetRTCCalibrationValue + * + * @brief Sets RTC Clock Calibration value. + * + * @param CalibrationValue - specifies the RTC Clock Calibration value. + * This parameter must be a number between 0 and 0x7F. + * + * @return none + */ +void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue) +{ + uint16_t tmpreg = 0; + + tmpreg = BKP->OCTLR; + tmpreg &= OCTLR_CAL_MASK; + tmpreg |= CalibrationValue; + BKP->OCTLR = tmpreg; +} + +/********************************************************************* + * @fn BKP_WriteBackupRegister + * + * @brief Writes user data to the specified Data Backup Register. + * + * @param BKP_DR - specifies the Data Backup Register. + * Data - data to write. + * + * @return none + */ +void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + *(__IO uint32_t *)tmp = Data; +} + +/********************************************************************* + * @fn BKP_ReadBackupRegister + * + * @brief Reads data from the specified Data Backup Register. + * + * @param BKP_DR - specifies the Data Backup Register. + * This parameter can be BKP_DRx where x=[1, 42]. + * + * @return none + */ +uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)BKP_BASE; + tmp += BKP_DR; + + return (*(__IO uint16_t *)tmp); +} + +/********************************************************************* + * @fn BKP_GetFlagStatus + * + * @brief Checks whether the Tamper Pin Event flag is set or not. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus BKP_GetFlagStatus(void) +{ + if(BKP->TPCSR & (1 << 8)) + { + return SET; + } + else + { + return RESET; + } +} + +/********************************************************************* + * @fn BKP_ClearFlag + * + * @brief Clears Tamper Pin Event pending flag. + * + * @return none + */ +void BKP_ClearFlag(void) +{ + BKP->TPCSR |= BKP_CTE; +} + +/********************************************************************* + * @fn BKP_GetITStatus + * + * @brief Checks whether the Tamper Pin Interrupt has occurred or not. + * + * @return ITStatus - SET or RESET. + */ +ITStatus BKP_GetITStatus(void) +{ + if(BKP->TPCSR & (1 << 9)) + { + return SET; + } + else + { + return RESET; + } +} + +/********************************************************************* + * @fn BKP_ClearITPendingBit + * + * @brief Clears Tamper Pin Interrupt pending bit. + * + * @return none + */ +void BKP_ClearITPendingBit(void) +{ + BKP->TPCSR |= BKP_CTI; +} diff --git a/Peripheral/src/ch32v30x_can.c b/Peripheral/src/ch32v30x_can.c new file mode 100644 index 0000000..e1da1f8 --- /dev/null +++ b/Peripheral/src/ch32v30x_can.c @@ -0,0 +1,1297 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_can.c +* Author : WCH +* Version : V1.0.1 +* Date : 2025/04/06 +* Description : This file provides all the CAN firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_can.h" +#include "ch32v30x_rcc.h" + +/* CAN CTLR Register bits */ +#define CTLR_DBF ((uint32_t)0x00010000) + +/* CAN Mailbox Transmit Request */ +#define TMIDxR_TXRQ ((uint32_t)0x00000001) + +/* CAN FCTLR Register bits */ +#define FCTLR_FINIT ((uint32_t)0x00000001) + +/* Time out for INAK bit */ +#define INAK_TIMEOUT ((uint32_t)0x0000FFFF) +/* Time out for SLAK bit */ +#define SLAK_TIMEOUT ((uint32_t)0x0000FFFF) + +/* Flags in TSTATR register */ +#define CAN_FLAGS_TSTATR ((uint32_t)0x08000000) +/* Flags in RFIFO1 register */ +#define CAN_FLAGS_RFIFO1 ((uint32_t)0x04000000) +/* Flags in RFIFO0 register */ +#define CAN_FLAGS_RFIFO0 ((uint32_t)0x02000000) +/* Flags in STATR register */ +#define CAN_FLAGS_STATR ((uint32_t)0x01000000) +/* Flags in ERRSR register */ +#define CAN_FLAGS_ERRSR ((uint32_t)0x00F00000) + +/* Mailboxes definition */ +#define CAN_TXMAILBOX_0 ((uint8_t)0x00) +#define CAN_TXMAILBOX_1 ((uint8_t)0x01) +#define CAN_TXMAILBOX_2 ((uint8_t)0x02) + +#define CAN_MODE_MASK ((uint32_t)0x00000003) + +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit); + +/********************************************************************* + * @fn CAN_DeInit + * + * @brief Deinitializes the CAN peripheral registers to their default reset + * values. + * + * @param CANx - where x can be 1 or 2 to select the CAN peripheral. + * + * @return none + */ +void CAN_DeInit(CAN_TypeDef *CANx) +{ + if(CANx == CAN1) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE); + } + else + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE); + } +} + +/********************************************************************* + * @fn CAN_Init + * + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_InitStruct. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_InitStruct - pointer to a CAN_InitTypeDef structure that + * contains the configuration information for the CAN peripheral. + * + * @return InitStatus - CAN InitStatus state. + * CAN_InitStatus_Failed. + * CAN_InitStatus_Success. + */ +uint8_t CAN_Init(CAN_TypeDef *CANx, CAN_InitTypeDef *CAN_InitStruct) +{ + uint8_t InitStatus = CAN_InitStatus_Failed; + uint32_t wait_ack = 0x00000000; + uint32_t chipid = DBGMCU_GetCHIPID(); + uint32_t chippackid = (chipid >> 4) & 0xf; + if(chippackid >= 4 && chippackid <= 7) + { + if(CAN1 == CANx) + { + (*(__IO uint32_t *)(0x40021010)) |= 0x2000000; + (*(__IO uint32_t *)(0x40021010)) &= ~(0x2000000); + }else if(CAN2 == CANx) + { + (*(__IO uint32_t *)(0x40021010)) |= 0x4000000; + (*(__IO uint32_t *)(0x40021010)) &= ~(0x4000000); + } + + CANx->CTLR &= ~0x2; + CANx->CTLR |= 0x1; + + while(!(CANx->STATR & 0x1) && (wait_ack != 0x0000FFFF)) + { + wait_ack++; + } + + if((CANx->STATR & 0x1)) + { + CANx->BTIMR = ( uint32_t)0xC1100000| \ + ((uint32_t)SystemCoreClock/(((((*(__IO uint32_t *)(0x40021004)) >> 8) & 0x7) < 0x4) ? 1 : (uint32_t)0x2<<(((*(__IO uint32_t *)(0x40021004)) >> 8) & 0x3))/4000000 - 1); + } + else + { + return CAN_InitStatus_Failed; + } + CANx->CTLR &= ~0x1; + wait_ack = 0; + while((CANx->STATR & 0x1) && (wait_ack != 0x0000FFFF)) + { + wait_ack++; + } + + if((CANx->STATR & 0x1)){ + return CAN_InitStatus_Failed; + } + + (*(__IO uint32_t *)(0x4000660C)) |= 0x3; + (*(__IO uint32_t *)(0x40006640)) = 0x0; + (*(__IO uint32_t *)(0x40006644)) = 0x0; + (*(__IO uint32_t *)(0x40006648)) = 0x0; + (*(__IO uint32_t *)(0x4000664C)) = 0x0; + (*(__IO uint32_t *)(0x4000661C)) |= 0x3; + (*(__IO uint32_t *)(0x40006600)) &= ~0x1; + CAN_SlaveStartBank(1); + if(CAN1 == CANx) + { + (*(__IO uint32_t *)(0x40006580)) |= 0x3; + while(!((*(__IO uint32_t *)(0x4000640C)) & 0x3)); + (*(__IO uint32_t *)(0x4000640C)) = 0x38; + }else if (CAN2 == CANx) + { + (*(__IO uint32_t *)(0x40006980)) |= 0x3; + while(!((*(__IO uint32_t *)(0x4000680C)) & 0x3)); + (*(__IO uint32_t *)(0x4000680C)) = 0x38; + } + + if(CAN1 == CANx) + { + (*(__IO uint32_t *)(0x40021010)) |= 0x2000000; + (*(__IO uint32_t *)(0x40021010)) &= ~(0x2000000); + }else if(CAN2 == CANx) + { + (*(__IO uint32_t *)(0x40021010)) |= 0x4000000; + (*(__IO uint32_t *)(0x40021010)) &= ~(0x4000000); + } + + (*(__IO uint32_t *)(0x40006600)) |= 0x1; + (*(__IO uint32_t *)(0x4000660C)) |= 0x3; + (*(__IO uint32_t *)(0x4000661C)) |= 0x3; + (*(__IO uint32_t *)(0x40006600)) &= ~0x1; + CAN_SlaveStartBank(1); + wait_ack = 0; + } + + CANx->CTLR &= (~(uint32_t)CAN_CTLR_SLEEP); + CANx->CTLR |= CAN_CTLR_INRQ; + + while(((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + if((CANx->STATR & CAN_STATR_INAK) != CAN_STATR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + if(CAN_InitStruct->CAN_TTCM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_TTCM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_TTCM; + } + + if(CAN_InitStruct->CAN_ABOM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_ABOM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_ABOM; + } + + if(CAN_InitStruct->CAN_AWUM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_AWUM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_AWUM; + } + + if(CAN_InitStruct->CAN_NART == ENABLE) + { + CANx->CTLR |= CAN_CTLR_NART; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_NART; + } + + if(CAN_InitStruct->CAN_RFLM == ENABLE) + { + CANx->CTLR |= CAN_CTLR_RFLM; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_RFLM; + } + + if(CAN_InitStruct->CAN_TXFP == ENABLE) + { + CANx->CTLR |= CAN_CTLR_TXFP; + } + else + { + CANx->CTLR &= ~(uint32_t)CAN_CTLR_TXFP; + } + + CANx->BTIMR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | + ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | + ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | + ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | + ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); + CANx->CTLR &= ~(uint32_t)CAN_CTLR_INRQ; + wait_ack = 0; + + while(((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) && (wait_ack != INAK_TIMEOUT)) + { + wait_ack++; + } + + if((CANx->STATR & CAN_STATR_INAK) == CAN_STATR_INAK) + { + InitStatus = CAN_InitStatus_Failed; + } + else + { + InitStatus = CAN_InitStatus_Success; + } + } + + return InitStatus; +} + +/********************************************************************* + * @fn CAN_FilterInit + * + * @brief Initializes the CAN peripheral according to the specified + * parameters in the CAN_FilterInitStruct. + * + * @param CAN_FilterInitStruct - pointer to a CAN_FilterInitTypeDef + * structure that contains the configuration information. + * + * @return none + */ +void CAN_FilterInit(CAN_FilterInitTypeDef *CAN_FilterInitStruct) +{ + uint32_t filter_number_bit_pos = 0; + + filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber; + CAN1->FCTLR |= FCTLR_FINIT; + CAN1->FWR &= ~(uint32_t)filter_number_bit_pos; + + if(CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) + { + CAN1->FSCFGR &= ~(uint32_t)filter_number_bit_pos; + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); + } + + if(CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) + { + CAN1->FSCFGR |= filter_number_bit_pos; + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); + + CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = + ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | + (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); + } + + if(CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) + { + CAN1->FMCFGR &= ~(uint32_t)filter_number_bit_pos; + } + else + { + CAN1->FMCFGR |= (uint32_t)filter_number_bit_pos; + } + + if(CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0) + { + CAN1->FAFIFOR &= ~(uint32_t)filter_number_bit_pos; + } + + if(CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1) + { + CAN1->FAFIFOR |= (uint32_t)filter_number_bit_pos; + } + + if(CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) + { + CAN1->FWR |= filter_number_bit_pos; + } + + CAN1->FCTLR &= ~FCTLR_FINIT; +} + +/********************************************************************* + * @fn CAN_StructInit + * + * @brief Fills each CAN_InitStruct member with its default value. + * + * @param CAN_InitStruct - pointer to a CAN_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void CAN_StructInit(CAN_InitTypeDef *CAN_InitStruct) +{ + CAN_InitStruct->CAN_TTCM = DISABLE; + CAN_InitStruct->CAN_ABOM = DISABLE; + CAN_InitStruct->CAN_AWUM = DISABLE; + CAN_InitStruct->CAN_NART = DISABLE; + CAN_InitStruct->CAN_RFLM = DISABLE; + CAN_InitStruct->CAN_TXFP = DISABLE; + CAN_InitStruct->CAN_Mode = CAN_Mode_Normal; + CAN_InitStruct->CAN_SJW = CAN_SJW_1tq; + CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq; + CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq; + CAN_InitStruct->CAN_Prescaler = 1; +} + +/********************************************************************* + * @fn CAN_SlaveStartBank + * + * @brief This function applies only to CH32 Connectivity line devices. + * + * @param CAN_BankNumber - Select the start slave bank filter from 1..27. + * + * @return none + */ +void CAN_SlaveStartBank(uint8_t CAN_BankNumber) +{ + CAN1->FCTLR |= FCTLR_FINIT; + CAN1->FCTLR &= (uint32_t)0xFFFFC0F1; + CAN1->FCTLR |= (uint32_t)(CAN_BankNumber) << 8; + CAN1->FCTLR &= ~FCTLR_FINIT; +} + +/********************************************************************* + * @fn CAN_DBGFreeze + * + * @brief Enables or disables the DBG Freeze for CAN. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void CAN_DBGFreeze(CAN_TypeDef *CANx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + CANx->CTLR |= CTLR_DBF; + } + else + { + CANx->CTLR &= ~CTLR_DBF; + } +} + +/********************************************************************* + * @fn CAN_TTComModeCmd + * + * @brief Enables or disabes the CAN Time TriggerOperation communication mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * NewState - ENABLE or DISABLE. + * Note- + * DLC must be programmed as 8 in order Time Stamp (2 bytes) to be + * sent over the CAN bus. + * + * @return none + */ +void CAN_TTComModeCmd(CAN_TypeDef *CANx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + CANx->CTLR |= CAN_CTLR_TTCM; + + CANx->sTxMailBox[0].TXMDTR |= ((uint32_t)CAN_TXMDT0R_TGT); + CANx->sTxMailBox[1].TXMDTR |= ((uint32_t)CAN_TXMDT1R_TGT); + CANx->sTxMailBox[2].TXMDTR |= ((uint32_t)CAN_TXMDT2R_TGT); + } + else + { + CANx->CTLR &= (uint32_t)(~(uint32_t)CAN_CTLR_TTCM); + + CANx->sTxMailBox[0].TXMDTR &= ((uint32_t)~CAN_TXMDT0R_TGT); + CANx->sTxMailBox[1].TXMDTR &= ((uint32_t)~CAN_TXMDT1R_TGT); + CANx->sTxMailBox[2].TXMDTR &= ((uint32_t)~CAN_TXMDT2R_TGT); + } +} + +/********************************************************************* + * @fn CAN_Transmit + * + * @brief Initiates the transmission of a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * TxMessage - pointer to a structure which contains CAN Id, CAN + * DLC and CAN data. + * + * @return transmit_mailbox - The number of the mailbox that is used for + * transmission or CAN_TxStatus_NoMailBox if there is no empty mailbox. + */ +uint8_t CAN_Transmit(CAN_TypeDef *CANx, CanTxMsg *TxMessage) +{ + uint8_t transmit_mailbox = 0; + + if((CANx->TSTATR & CAN_TSTATR_TME0) == CAN_TSTATR_TME0) + { + transmit_mailbox = 0; + } + else if((CANx->TSTATR & CAN_TSTATR_TME1) == CAN_TSTATR_TME1) + { + transmit_mailbox = 1; + } + else if((CANx->TSTATR & CAN_TSTATR_TME2) == CAN_TSTATR_TME2) + { + transmit_mailbox = 2; + } + else + { + transmit_mailbox = CAN_TxStatus_NoMailBox; + } + + if(transmit_mailbox != CAN_TxStatus_NoMailBox) + { + CANx->sTxMailBox[transmit_mailbox].TXMIR &= TMIDxR_TXRQ; + if(TxMessage->IDE == CAN_Id_Standard) + { + CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->StdId << 21) | + TxMessage->RTR); + } + else + { + CANx->sTxMailBox[transmit_mailbox].TXMIR |= ((TxMessage->ExtId << 3) | + TxMessage->IDE | + TxMessage->RTR); + } + + TxMessage->DLC &= (uint8_t)0x0000000F; + CANx->sTxMailBox[transmit_mailbox].TXMDTR &= (uint32_t)0xFFFFFFF0; + CANx->sTxMailBox[transmit_mailbox].TXMDTR |= TxMessage->DLC; + + CANx->sTxMailBox[transmit_mailbox].TXMDLR = (((uint32_t)TxMessage->Data[3] << 24) | + ((uint32_t)TxMessage->Data[2] << 16) | + ((uint32_t)TxMessage->Data[1] << 8) | + ((uint32_t)TxMessage->Data[0])); + CANx->sTxMailBox[transmit_mailbox].TXMDHR = (((uint32_t)TxMessage->Data[7] << 24) | + ((uint32_t)TxMessage->Data[6] << 16) | + ((uint32_t)TxMessage->Data[5] << 8) | + ((uint32_t)TxMessage->Data[4])); + CANx->sTxMailBox[transmit_mailbox].TXMIR |= TMIDxR_TXRQ; + } + + return transmit_mailbox; +} + +/********************************************************************* + * @fn CAN_TransmitStatus + * + * @brief Checks the transmission of a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * TransmitMailbox - the number of the mailbox that is used for + * transmission. + * + * @return state - + * CAN_TxStatus_Ok. + * CAN_TxStatus_Failed. + */ +uint8_t CAN_TransmitStatus(CAN_TypeDef *CANx, uint8_t TransmitMailbox) +{ + uint32_t state = 0; + + switch(TransmitMailbox) + { + case(CAN_TXMAILBOX_0): + state = CANx->TSTATR & (CAN_TSTATR_RQCP0 | CAN_TSTATR_TXOK0 | CAN_TSTATR_TME0); + break; + + case(CAN_TXMAILBOX_1): + state = CANx->TSTATR & (CAN_TSTATR_RQCP1 | CAN_TSTATR_TXOK1 | CAN_TSTATR_TME1); + break; + + case(CAN_TXMAILBOX_2): + state = CANx->TSTATR & (CAN_TSTATR_RQCP2 | CAN_TSTATR_TXOK2 | CAN_TSTATR_TME2); + break; + + default: + state = CAN_TxStatus_Failed; + break; + } + + switch(state) + { + case(0x0): + state = CAN_TxStatus_Pending; + break; + + case(CAN_TSTATR_RQCP0 | CAN_TSTATR_TME0): + state = CAN_TxStatus_Failed; + break; + + case(CAN_TSTATR_RQCP1 | CAN_TSTATR_TME1): + state = CAN_TxStatus_Failed; + break; + + case(CAN_TSTATR_RQCP2 | CAN_TSTATR_TME2): + state = CAN_TxStatus_Failed; + break; + + case(CAN_TSTATR_RQCP0 | CAN_TSTATR_TXOK0 | CAN_TSTATR_TME0): + state = CAN_TxStatus_Ok; + break; + + case(CAN_TSTATR_RQCP1 | CAN_TSTATR_TXOK1 | CAN_TSTATR_TME1): + state = CAN_TxStatus_Ok; + break; + + case(CAN_TSTATR_RQCP2 | CAN_TSTATR_TXOK2 | CAN_TSTATR_TME2): + state = CAN_TxStatus_Ok; + break; + + default: + state = CAN_TxStatus_Failed; + break; + } + + return (uint8_t)state; +} + +/********************************************************************* + * @fn CAN_CancelTransmit + * + * @brief Cancels a transmit request. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * Mailbox - Mailbox number. + * CAN_TXMAILBOX_0. + * CAN_TXMAILBOX_1. + * CAN_TXMAILBOX_2. + * + * @return none + */ +void CAN_CancelTransmit(CAN_TypeDef *CANx, uint8_t Mailbox) +{ + switch(Mailbox) + { + case(CAN_TXMAILBOX_0): + CANx->TSTATR |= CAN_TSTATR_ABRQ0; + break; + + case(CAN_TXMAILBOX_1): + CANx->TSTATR |= CAN_TSTATR_ABRQ1; + break; + + case(CAN_TXMAILBOX_2): + CANx->TSTATR |= CAN_TSTATR_ABRQ2; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn CAN_Receive + * + * @brief Receives a message. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * RxMessage - pointer to a structure receive message which contains + * CAN Id, CAN DLC, CAN datas and FMI number. + * + * @return none + */ +void CAN_Receive(CAN_TypeDef *CANx, uint8_t FIFONumber, CanRxMsg *RxMessage) +{ + RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RXMIR; + + if(RxMessage->IDE == CAN_Id_Standard) + { + RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 21); + } + else + { + RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RXMIR >> 3); + } + + RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RXMIR; + RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RXMDTR; + RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDTR >> 8); + RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RXMDLR; + RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 8); + RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 16); + RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDLR >> 24); + RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RXMDHR; + RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 8); + RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 16); + RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RXMDHR >> 24); + + if(FIFONumber == CAN_FIFO0) + { + CANx->RFIFO0 |= CAN_RFIFO0_RFOM0; + } + else + { + CANx->RFIFO1 |= CAN_RFIFO1_RFOM1; + } +} + +/********************************************************************* + * @fn CAN_FIFORelease + * + * @brief Releases the specified FIFO. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * + * @return none + */ +void CAN_FIFORelease(CAN_TypeDef *CANx, uint8_t FIFONumber) +{ + if(FIFONumber == CAN_FIFO0) + { + CANx->RFIFO0 |= CAN_RFIFO0_RFOM0; + } + else + { + CANx->RFIFO1 |= CAN_RFIFO1_RFOM1; + } +} + +/********************************************************************* + * @fn CAN_MessagePending + * + * @brief Returns the number of pending messages. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * FIFONumber - Receive FIFO number. + * CAN_FIFO0. + * CAN_FIFO1. + * + * @return message_pending: which is the number of pending message. + */ +uint8_t CAN_MessagePending(CAN_TypeDef *CANx, uint8_t FIFONumber) +{ + uint8_t message_pending = 0; + + if(FIFONumber == CAN_FIFO0) + { + message_pending = (uint8_t)(CANx->RFIFO0 & (uint32_t)0x03); + } + else if(FIFONumber == CAN_FIFO1) + { + message_pending = (uint8_t)(CANx->RFIFO1 & (uint32_t)0x03); + } + else + { + message_pending = 0; + } + + return message_pending; +} + +/********************************************************************* + * @fn CAN_OperatingModeRequest + * + * @brief Select the CAN Operation mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_OperatingMode - CAN Operating Mode. + * CAN_OperatingMode_Initialization. + * CAN_OperatingMode_Normal. + * CAN_OperatingMode_Sleep. + * + * @return status - + * CAN_ModeStatus_Failed - CAN failed entering the specific mode. + * CAN_ModeStatus_Success - CAN Succeed entering the specific mode. + */ +uint8_t CAN_OperatingModeRequest(CAN_TypeDef *CANx, uint8_t CAN_OperatingMode) +{ + uint8_t status = CAN_ModeStatus_Failed; + uint32_t timeout = INAK_TIMEOUT; + + if(CAN_OperatingMode == CAN_OperatingMode_Initialization) + { + CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_SLEEP)) | CAN_CTLR_INRQ); + + while(((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_INAK) && (timeout != 0)) + { + timeout--; + } + if((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_INAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if(CAN_OperatingMode == CAN_OperatingMode_Normal) + { + CANx->CTLR &= (uint32_t)(~(CAN_CTLR_SLEEP | CAN_CTLR_INRQ)); + + while(((CANx->STATR & CAN_MODE_MASK) != 0) && (timeout != 0)) + { + timeout--; + } + if((CANx->STATR & CAN_MODE_MASK) != 0) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else if(CAN_OperatingMode == CAN_OperatingMode_Sleep) + { + CANx->CTLR = (uint32_t)((CANx->CTLR & (uint32_t)(~(uint32_t)CAN_CTLR_INRQ)) | CAN_CTLR_SLEEP); + + while(((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_SLAK) && (timeout != 0)) + { + timeout--; + } + if((CANx->STATR & CAN_MODE_MASK) != CAN_STATR_SLAK) + { + status = CAN_ModeStatus_Failed; + } + else + { + status = CAN_ModeStatus_Success; + } + } + else + { + status = CAN_ModeStatus_Failed; + } + + return (uint8_t)status; +} + +/********************************************************************* + * @fn CAN_Sleep + * + * @brief Enters the low power mode. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return sleepstatus - + * CAN_Sleep_Ok. + * CAN_Sleep_Failed. + */ +uint8_t CAN_Sleep(CAN_TypeDef *CANx) +{ + uint8_t sleepstatus = CAN_Sleep_Failed; + + CANx->CTLR = (((CANx->CTLR) & (uint32_t)(~(uint32_t)CAN_CTLR_INRQ)) | CAN_CTLR_SLEEP); + + if((CANx->STATR & (CAN_STATR_SLAK | CAN_STATR_INAK)) == CAN_STATR_SLAK) + { + sleepstatus = CAN_Sleep_Ok; + } + + return (uint8_t)sleepstatus; +} + +/********************************************************************* + * @fn CAN_WakeUp + * + * @brief Wakes the CAN up. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return wakeupstatus - + * CAN_WakeUp_Ok. + * CAN_WakeUp_Failed. + */ +uint8_t CAN_WakeUp(CAN_TypeDef *CANx) +{ + uint32_t wait_slak = SLAK_TIMEOUT; + uint8_t wakeupstatus = CAN_WakeUp_Failed; + + CANx->CTLR &= ~(uint32_t)CAN_CTLR_SLEEP; + + while(((CANx->STATR & CAN_STATR_SLAK) == CAN_STATR_SLAK) && (wait_slak != 0x00)) + { + wait_slak--; + } + if((CANx->STATR & CAN_STATR_SLAK) != CAN_STATR_SLAK) + { + wakeupstatus = CAN_WakeUp_Ok; + } + + return (uint8_t)wakeupstatus; +} + +/********************************************************************* + * @fn CAN_GetLastErrorCode + * + * @brief Returns the CANx's last error code (LEC). + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return errorcode - specifies the Error code. + * CAN_ErrorCode_NoErr - No Error. + * CAN_ErrorCode_StuffErr - Stuff Error. + * CAN_ErrorCode_FormErr - Form Error. + * CAN_ErrorCode_ACKErr - Acknowledgment Error. + * CAN_ErrorCode_BitRecessiveErr - Bit Recessive Error. + * CAN_ErrorCode_BitDominantErr - Bit Dominant Error. + * CAN_ErrorCode_CRCErr - CRC Error. + * CAN_ErrorCode_SoftwareSetErr - Software Set Error. + */ +uint8_t CAN_GetLastErrorCode(CAN_TypeDef *CANx) +{ + uint8_t errorcode = 0; + + errorcode = (((uint8_t)CANx->ERRSR) & (uint8_t)CAN_ERRSR_LEC); + + return errorcode; +} + +/********************************************************************* + * @fn CAN_GetReceiveErrorCounter + * + * @brief Returns the CANx Receive Error Counter (REC). + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * Note- + * In case of an error during reception, this counter is incremented + * by 1 or by 8 depending on the error condition as defined by the CAN + * standard. After every successful reception, the counter is + * decremented by 1 or reset to 120 if its value was higher than 128. + * When the counter value exceeds 127, the CAN controller enters the + * error passive state. + * @return counter - CAN Receive Error Counter. + */ +uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef *CANx) +{ + uint8_t counter = 0; + + counter = (uint8_t)((CANx->ERRSR & CAN_ERRSR_REC) >> 24); + + return counter; +} + +/********************************************************************* + * @fn CAN_GetLSBTransmitErrorCounter + * + * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC). + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * + * @return counter - LSB of the 9-bit CAN Transmit Error Counter. + */ +uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef *CANx) +{ + uint8_t counter = 0; + + counter = (uint8_t)((CANx->ERRSR & CAN_ERRSR_TEC) >> 16); + + return counter; +} + +/********************************************************************* + * @fn CAN_ITConfig + * + * @brief Enables or disables the specified CANx interrupts. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_IT - specifies the CAN interrupt sources to be enabled or disabled. + * CAN_IT_TME. + * CAN_IT_FMP0. + * CAN_IT_FF0. + * CAN_IT_FOV0. + * CAN_IT_FMP1. + * CAN_IT_FF1. + * CAN_IT_FOV1. + * CAN_IT_EWG. + * CAN_IT_EPV. + * CAN_IT_LEC. + * CAN_IT_ERR. + * CAN_IT_WKU. + * CAN_IT_SLK. + * NewState - ENABLE or DISABLE. + * + * @return counter - LSB of the 9-bit CAN Transmit Error Counter. + */ +void CAN_ITConfig(CAN_TypeDef *CANx, uint32_t CAN_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + CANx->INTENR |= CAN_IT; + } + else + { + CANx->INTENR &= ~CAN_IT; + } +} + +/********************************************************************* + * @fn CAN_GetFlagStatus + * + * @brief Checks whether the specified CAN flag is set or not. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_FLAG - specifies the flag to check. + * CAN_FLAG_EWG. + * CAN_FLAG_EPV. + * CAN_FLAG_BOF. + * CAN_FLAG_RQCP0. + * CAN_FLAG_RQCP1. + * CAN_FLAG_RQCP2. + * CAN_FLAG_FMP1. + * CAN_FLAG_FF1. + * CAN_FLAG_FOV1. + * CAN_FLAG_FMP0. + * CAN_FLAG_FF0. + * CAN_FLAG_FOV0. + * CAN_FLAG_WKU. + * CAN_FLAG_SLAK. + * CAN_FLAG_LEC. + * NewState - ENABLE or DISABLE. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus CAN_GetFlagStatus(CAN_TypeDef *CANx, uint32_t CAN_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((CAN_FLAG & CAN_FLAGS_ERRSR) != (uint32_t)RESET) + { + if((CANx->ERRSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_STATR) != (uint32_t)RESET) + { + if((CANx->STATR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_TSTATR) != (uint32_t)RESET) + { + if((CANx->TSTATR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else if((CAN_FLAG & CAN_FLAGS_RFIFO0) != (uint32_t)RESET) + { + if((CANx->RFIFO0 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((uint32_t)(CANx->RFIFO1 & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/********************************************************************* + * @fn CAN_ClearFlag + * + * @brief Clears the CAN's pending flags. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_FLAG - specifies the flag to clear. + * CAN_FLAG_RQCP0. + * CAN_FLAG_RQCP1. + * CAN_FLAG_RQCP2. + * CAN_FLAG_FF1. + * CAN_FLAG_FOV1. + * CAN_FLAG_FF0. + * CAN_FLAG_FOV0. + * CAN_FLAG_WKU. + * CAN_FLAG_SLAK. + * CAN_FLAG_LEC. + * + * @return none + */ +void CAN_ClearFlag(CAN_TypeDef *CANx, uint32_t CAN_FLAG) +{ + uint32_t flagtmp = 0; + + if(CAN_FLAG == CAN_FLAG_LEC) + { + CANx->ERRSR = (uint32_t)RESET; + } + else + { + flagtmp = CAN_FLAG & 0x000FFFFF; + + if((CAN_FLAG & CAN_FLAGS_RFIFO0) != (uint32_t)RESET) + { + CANx->RFIFO0 = (uint32_t)(flagtmp); + } + else if((CAN_FLAG & CAN_FLAGS_RFIFO1) != (uint32_t)RESET) + { + CANx->RFIFO1 = (uint32_t)(flagtmp); + } + else if((CAN_FLAG & CAN_FLAGS_TSTATR) != (uint32_t)RESET) + { + CANx->TSTATR = (uint32_t)(flagtmp); + } + else + { + CANx->STATR = (uint32_t)(flagtmp); + } + } +} + +/********************************************************************* + * @fn CAN_GetITStatus + * + * @brief Checks whether the specified CANx interrupt has occurred or not. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_IT - specifies the CAN interrupt source to check. + * CAN_IT_TME. + * CAN_IT_FMP0. + * CAN_IT_FF0. + * CAN_IT_FOV0. + * CAN_IT_FMP1. + * CAN_IT_FF1. + * CAN_IT_FOV1. + * CAN_IT_WKU. + * CAN_IT_SLK. + * CAN_IT_EWG. + * CAN_IT_EPV. + * CAN_IT_BOF. + * CAN_IT_LEC. + * CAN_IT_ERR. + * + * @return ITStatus - SET or RESET. + */ +ITStatus CAN_GetITStatus(CAN_TypeDef *CANx, uint32_t CAN_IT) +{ + ITStatus itstatus = RESET; + + if((CANx->INTENR & CAN_IT) != RESET) + { + switch(CAN_IT) + { + case CAN_IT_TME: + itstatus = CheckITStatus(CANx->TSTATR, CAN_TSTATR_RQCP0 | CAN_TSTATR_RQCP1 | CAN_TSTATR_RQCP2); + break; + + case CAN_IT_FMP0: + itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FMP0); + break; + + case CAN_IT_FF0: + itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FULL0); + break; + + case CAN_IT_FOV0: + itstatus = CheckITStatus(CANx->RFIFO0, CAN_RFIFO0_FOVR0); + break; + + case CAN_IT_FMP1: + itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FMP1); + break; + + case CAN_IT_FF1: + itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FULL1); + break; + + case CAN_IT_FOV1: + itstatus = CheckITStatus(CANx->RFIFO1, CAN_RFIFO1_FOVR1); + break; + + case CAN_IT_WKU: + itstatus = CheckITStatus(CANx->STATR, CAN_STATR_WKUI); + break; + + case CAN_IT_SLK: + itstatus = CheckITStatus(CANx->STATR, CAN_STATR_SLAKI); + break; + + case CAN_IT_EWG: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_EWGF); + break; + + case CAN_IT_EPV: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_EPVF); + break; + + case CAN_IT_BOF: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_BOFF); + break; + + case CAN_IT_LEC: + itstatus = CheckITStatus(CANx->ERRSR, CAN_ERRSR_LEC); + break; + + case CAN_IT_ERR: + itstatus = CheckITStatus(CANx->STATR, CAN_STATR_ERRI); + break; + + default: + itstatus = RESET; + break; + } + } + else + { + itstatus = RESET; + } + + return itstatus; +} + +/********************************************************************* + * @fn CAN_ClearITPendingBit + * + * @brief Clears the CANx's interrupt pending bits. + * + * @param CANx - where x can be 1 to select the CAN peripheral. + * CAN_IT - specifies the interrupt pending bit to clear. + * CAN_IT_TME. + * CAN_IT_FF0. + * CAN_IT_FOV0. + * CAN_IT_FF1. + * CAN_IT_FOV1. + * CAN_IT_WKU. + * CAN_IT_SLK. + * CAN_IT_EWG. + * CAN_IT_EPV. + * CAN_IT_BOF. + * CAN_IT_LEC. + * CAN_IT_ERR. + * + * @return none + */ +void CAN_ClearITPendingBit(CAN_TypeDef *CANx, uint32_t CAN_IT) +{ + switch(CAN_IT) + { + case CAN_IT_TME: + CANx->TSTATR = CAN_TSTATR_RQCP0 | CAN_TSTATR_RQCP1 | CAN_TSTATR_RQCP2; + break; + + case CAN_IT_FF0: + CANx->RFIFO0 = CAN_RFIFO0_FULL0; + break; + + case CAN_IT_FOV0: + CANx->RFIFO0 = CAN_RFIFO0_FOVR0; + break; + + case CAN_IT_FF1: + CANx->RFIFO1 = CAN_RFIFO1_FULL1; + break; + + case CAN_IT_FOV1: + CANx->RFIFO1 = CAN_RFIFO1_FOVR1; + break; + + case CAN_IT_WKU: + CANx->STATR = CAN_STATR_WKUI; + break; + + case CAN_IT_SLK: + CANx->STATR = CAN_STATR_SLAKI; + break; + + case CAN_IT_EWG: + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_EPV: + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_BOF: + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_LEC: + CANx->ERRSR = RESET; + CANx->STATR = CAN_STATR_ERRI; + break; + + case CAN_IT_ERR: + CANx->ERRSR = RESET; + CANx->STATR = CAN_STATR_ERRI; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn CheckITStatus + * + * @brief Checks whether the CAN interrupt has occurred or not. + * + * @param CAN_Reg - specifies the CAN interrupt register to check + * It_Bit - specifies the interrupt source bit to check. + * + * @return ITStatus - SET or RESET. + */ +static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit) +{ + ITStatus pendingbitstatus = RESET; + + if((CAN_Reg & It_Bit) != (uint32_t)RESET) + { + pendingbitstatus = SET; + } + else + { + pendingbitstatus = RESET; + } + + return pendingbitstatus; +} diff --git a/Peripheral/src/ch32v30x_crc.c b/Peripheral/src/ch32v30x_crc.c new file mode 100644 index 0000000..d44ad21 --- /dev/null +++ b/Peripheral/src/ch32v30x_crc.c @@ -0,0 +1,100 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_crc.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the CRC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_crc.h" + +/********************************************************************* + * @fn CRC_ResetDR + * + * @brief Resets the CRC Data register (DR). + * + * @return none + */ +void CRC_ResetDR(void) +{ + CRC->CTLR = CRC_CTLR_RESET; +} + +/********************************************************************* + * @fn CRC_CalcCRC + * + * @brief Computes the 32-bit CRC of a given data word(32-bit). + * + * @param Data - data word(32-bit) to compute its CRC. + * + * @return 32-bit CRC. + */ +uint32_t CRC_CalcCRC(uint32_t Data) +{ + CRC->DATAR = Data; + + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_CalcBlockCRC + * + * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit). + * + * @param pBuffer - pointer to the buffer containing the data to be computed. + * BufferLength - length of the buffer to be computed. + * + * @return 32-bit CRC. + */ +uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength) +{ + uint32_t index = 0; + + for(index = 0; index < BufferLength; index++) + { + CRC->DATAR = pBuffer[index]; + } + + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_GetCRC + * + * @brief Returns the current CRC value. + * + * @return 32-bit CRC. + */ +uint32_t CRC_GetCRC(void) +{ + return (CRC->DATAR); +} + +/********************************************************************* + * @fn CRC_SetIDRegister + * + * @brief Stores a 8-bit data in the Independent Data(ID) register. + * + * @param IDValue - 8-bit value to be stored in the ID register. + * + * @return none + */ +void CRC_SetIDRegister(uint8_t IDValue) +{ + CRC->IDATAR = IDValue; +} + +/********************************************************************* + * @fn CRC_GetIDRegister + * + * @brief Returns the 8-bit data stored in the Independent Data(ID) register. + * + * @return 8-bit value of the ID register. + */ +uint8_t CRC_GetIDRegister(void) +{ + return (CRC->IDATAR); +} diff --git a/Peripheral/src/ch32v30x_dac.c b/Peripheral/src/ch32v30x_dac.c new file mode 100644 index 0000000..529ece7 --- /dev/null +++ b/Peripheral/src/ch32v30x_dac.c @@ -0,0 +1,304 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dac.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the DAC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_dac.h" +#include "ch32v30x_rcc.h" + +/* CTLR register Mask */ +#define CTLR_CLEAR_MASK ((uint32_t)0x00000FFE) + +/* DAC Dual Channels SWTR masks */ +#define DUAL_SWTR_SET ((uint32_t)0x00000003) +#define DUAL_SWTR_RESET ((uint32_t)0xFFFFFFFC) + +/* DHR registers offsets */ +#define DHR12R1_OFFSET ((uint32_t)0x00000008) +#define DHR12R2_OFFSET ((uint32_t)0x00000014) +#define DHR12RD_OFFSET ((uint32_t)0x00000020) + +/* DOR register offset */ +#define DOR_OFFSET ((uint32_t)0x0000002C) + +/********************************************************************* + * @fn DAC_DeInit + * + * @brief Deinitializes the DAC peripheral registers to their default reset values. + * + * @return none + */ +void DAC_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE); +} + +/********************************************************************* + * @fn DAC_Init + * + * @brief Initializes the DAC peripheral according to the specified parameters in + * the DAC_InitStruct. + * + * @param DAC_Channel - the selected DAC channel. + * DAC_Channel_1 - DAC Channel1 selected + * DAC_Channel_2 - DAC Channel2 selected + * DAC_InitStruct - pointer to a DAC_InitTypeDef structure. + * + * @return none + */ +void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + tmpreg1 = DAC->CTLR; + tmpreg1 &= ~(CTLR_CLEAR_MASK << DAC_Channel); + tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration | + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer); + tmpreg1 |= tmpreg2 << DAC_Channel; + DAC->CTLR = tmpreg1; +} + +/********************************************************************* + * @fn DAC_StructInit + * + * @brief Fills each DAC_InitStruct member with its default value. + * + * @param DAC_InitStruct - pointer to a DAC_InitTypeDef structure which will be initialized. + * + * @return none + */ +void DAC_StructInit(DAC_InitTypeDef *DAC_InitStruct) +{ + DAC_InitStruct->DAC_Trigger = DAC_Trigger_None; + DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None; + DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0; + DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable; +} + +/********************************************************************* + * @fn DAC_Cmd + * + * @brief Enables or disables the specified DAC channel. + * + * @param DAC_Channel - the selected DAC channel. + * DAC_Channel_1 - DAC Channel1 selected + * DAC_Channel_2 - DAC Channel2 selected + * NewState - new state of the DAC channel(ENABLE or DISABLE). + * + * @return none + */ +void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DAC->CTLR |= (DAC_EN1 << DAC_Channel); + } + else + { + DAC->CTLR &= ~(DAC_EN1 << DAC_Channel); + } +} + +/********************************************************************* + * @fn DAC_DMACmd + * + * @brief Enables or disables the specified DAC channel DMA request. + * + * @param DAC_Channel - the selected DAC channel. + * DAC_Channel_1 - DAC Channel1 selected + * DAC_Channel_2 - DAC Channel2 selected + * NewState - new state of the DAC channel(ENABLE or DISABLE). + * + * @return none + */ +void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DAC->CTLR |= (DAC_DMAEN1 << DAC_Channel); + } + else + { + DAC->CTLR &= ~(DAC_DMAEN1 << DAC_Channel); + } +} + +/********************************************************************* + * @fn DAC_SoftwareTriggerCmd + * + * @brief Enables or disables the selected DAC channel software trigger. + * + * @param DAC_Channel - the selected DAC channel. + * DAC_Channel_1 - DAC Channel1 selected + * DAC_Channel_2 - DAC Channel2 selected + * NewState - new state of the DAC channel(ENABLE or DISABLE). + * + * @return none + */ +void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DAC->SWTR |= (uint32_t)DAC_SWTRIG1 << (DAC_Channel >> 4); + } + else + { + DAC->SWTR &= ~((uint32_t)DAC_SWTRIG1 << (DAC_Channel >> 4)); + } +} + +/********************************************************************* + * @fn DAC_DualSoftwareTriggerCmd + * + * @brief Enables or disables the two DAC channel software trigger. + * + * @param NewState - new state of the DAC channel(ENABLE or DISABLE). + * + * @return none + */ +void DAC_DualSoftwareTriggerCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DAC->SWTR |= DUAL_SWTR_SET; + } + else + { + DAC->SWTR &= DUAL_SWTR_RESET; + } +} + +/********************************************************************* + * @fn DAC_WaveGenerationCmd + * + * @brief Enables or disables the selected DAC channel wave generation. + * + * @param DAC_Channel - the selected DAC channel. + * DAC_Channel_1 - DAC Channel1 selected + * DAC_Channel_2 - DAC Channel2 selected + * DAC_Wave - Specifies the wave type to enable or disable. + * DAC_Wave_Noise - noise wave generation + * DAC_Wave_Triangle - triangle wave generation + * NewState - new state of the DAC channel(ENABLE or DISABLE). + * + * @return none + */ +void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DAC->CTLR |= DAC_Wave << DAC_Channel; + } + else + { + DAC->CTLR &= ~(DAC_Wave << DAC_Channel); + } +} + +/********************************************************************* + * @fn DAC_SetChannel1Data + * + * @brief Set the specified data holding register value for DAC channel1. + * + * @param DAC_Align - Specifies the data alignment for DAC channel1. + * DAC_Align_8b_R - 8bit right data alignment selected + * DAC_Align_12b_L - 12bit left data alignment selected + * DAC_Align_12b_R - 12bit right data alignment selected + * Data - Data to be loaded in the selected data holding register. + * + * @return none + */ +void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R1_OFFSET + DAC_Align; + + *(__IO uint32_t *)tmp = Data; +} + +/********************************************************************* + * @fn DAC_SetChannel2Data + * + * @brief Set the specified data holding register value for DAC channel2. + * + * @param DAC_Align - Specifies the data alignment for DAC channel1. + * DAC_Align_8b_R - 8bit right data alignment selected + * DAC_Align_12b_L - 12bit left data alignment selected + * DAC_Align_12b_R - 12bit right data alignment selected + * Data - Data to be loaded in the selected data holding register. + * + * @return none + */ +void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12R2_OFFSET + DAC_Align; + + *(__IO uint32_t *)tmp = Data; +} + +/********************************************************************* + * @fn DAC_SetDualChannelData + * + * @brief Set the specified data holding register value for two DAC. + * + * @param DAC_Align - Specifies the data alignment for DAC channel1. + * DAC_Align_8b_R - 8bit right data alignment selected + * DAC_Align_12b_L - 12bit left data alignment selected + * DAC_Align_12b_R - 12bit right data alignment selected + * Data - Data to be loaded in the selected data holding register. + * Data1 - Data for DAC Channel1. + * Data2 - Data for DAC Channel2 + * + * @return none + */ +void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1) +{ + uint32_t data = 0, tmp = 0; + + if(DAC_Align == DAC_Align_8b_R) + { + data = ((uint32_t)Data2 << 8) | Data1; + } + else + { + data = ((uint32_t)Data2 << 16) | Data1; + } + + tmp = (uint32_t)DAC_BASE; + tmp += DHR12RD_OFFSET + DAC_Align; + + *(__IO uint32_t *)tmp = data; +} + +/********************************************************************* + * @fn DAC_GetDataOutputValue + * + * @brief Returns the last data output value of the selected DAC channel. + * + * @param DAC_Channel - the selected DAC channel. + * DAC_Channel_1 - DAC Channel1 selected + * DAC_Channel_2 - DAC Channel2 selected + * + * @return none + */ +uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)DAC_BASE; + tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2); + + return (uint16_t)(*(__IO uint32_t *)tmp); +} diff --git a/Peripheral/src/ch32v30x_dbgmcu.c b/Peripheral/src/ch32v30x_dbgmcu.c new file mode 100644 index 0000000..326dc1c --- /dev/null +++ b/Peripheral/src/ch32v30x_dbgmcu.c @@ -0,0 +1,129 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dbgmcu.c +* Author : WCH +* Version : V1.0.0 +* Date : 2024/05/28 +* Description : This file provides all the DBGMCU firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_dbgmcu.h" + +#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF) + +/********************************************************************* + * @fn DBGMCU_GetREVID + * + * @brief Returns the device revision identifier. + * + * @return Revision identifier. + */ +uint32_t DBGMCU_GetREVID(void) +{ + return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK); +} + +/********************************************************************* + * @fn DBGMCU_GetDEVID + * + * @brief Returns the device identifier. + * + * @return Device identifier. + */ +uint32_t DBGMCU_GetDEVID(void) +{ + return ((*(uint32_t *)0x1FFFF704) >> 16); +} + +/********************************************************************* + * @fn __get_DEBUG_CR + * + * @brief Return the DEBUGE Control Register + * + * @return DEBUGE Control value + */ +uint32_t __get_DEBUG_CR(void) +{ + uint32_t result; + + __asm volatile("csrr %0,""0x7C0" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_DEBUG_CR + * + * @brief Set the DEBUGE Control Register + * + * @param value - set DEBUGE Control value + * + * @return none + */ +void __set_DEBUG_CR(uint32_t value) +{ + __asm volatile("csrw 0x7C0, %0" : : "r"(value)); +} + + +/********************************************************************* + * @fn DBGMCU_Config + * + * @brief Configures the specified peripheral and low power mode behavior + * when the MCU under Debug mode. + * + * @param DBGMCU_Periph - specifies the peripheral and low power mode. + * DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted + * DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted + * DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted + * DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState) +{ + uint32_t val; + + if(NewState != DISABLE) + { + __set_DEBUG_CR(DBGMCU_Periph); + } + else + { + val = __get_DEBUG_CR(); + val &= ~(uint32_t)DBGMCU_Periph; + __set_DEBUG_CR(val); + } + +} + +/********************************************************************* + * @fn DBGMCU_GetCHIPID + * + * @brief Returns the CHIP identifier. + * + * @return Device identifier. + * ChipID List- + * CH32V303CBT6-0x303305x4 + * CH32V303RBT6-0x303205x4 + * CH32V303RCT6-0x303105x4 + * CH32V303VCT6-0x303005x4 + * CH32V305FBP6-0x305205x8 + * CH32V305RBT6-0x305005x8 + * CH32V305GBU6-0x305B05x8 + * CH32V305CCT6-0x305C05x8 + * CH32V307WCU6-0x307305x8 + * CH32V307FBP6-0x307205x8 + * CH32V307RCT6-0x307105x8 + * CH32V307VCT6-0x307005x8 + * CH32V317VCT6-0x3170B5X8 + * CH32V317WCU6-0x3173B5X8 + * CH32V317TCU6-0x3175B5X8 + */ +uint32_t DBGMCU_GetCHIPID( void ) +{ + return( *( uint32_t * )0x1FFFF704 ); +} + diff --git a/Peripheral/src/ch32v30x_dma.c b/Peripheral/src/ch32v30x_dma.c new file mode 100644 index 0000000..1b5cbe8 --- /dev/null +++ b/Peripheral/src/ch32v30x_dma.c @@ -0,0 +1,692 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dma.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the DMA firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_dma.h" +#include "ch32v30x_rcc.h" + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) + +/* DMA2 Channelx interrupt pending bit masks */ +#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA2_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA2_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) +#define DMA2_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8)) +#define DMA2_Channel9_IT_Mask ((uint32_t)(DMA_GIF9 | DMA_TCIF9 | DMA_HTIF9 | DMA_TEIF9)) +#define DMA2_Channel10_IT_Mask ((uint32_t)(DMA_GIF10 | DMA_TCIF10 | DMA_HTIF10 | DMA_TEIF10)) +#define DMA2_Channel11_IT_Mask ((uint32_t)(DMA_GIF11 | DMA_TCIF11 | DMA_HTIF11 | DMA_TEIF11)) + +/* DMA2 FLAG mask */ +#define FLAG_Mask ((uint32_t)0x10000000) +#define DMA2_EXTEN_FLAG_Mask ((uint32_t)0x20000000) + +/* DMA registers Masks */ +#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/********************************************************************* + * @fn DMA_DeInit + * + * @brief Deinitializes the DMAy Channelx registers to their default + * reset values. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * + * @return none + */ +void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx) +{ + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + DMAy_Channelx->CFGR = 0; + DMAy_Channelx->CNTR = 0; + DMAy_Channelx->PADDR = 0; + DMAy_Channelx->MADDR = 0; + if(DMAy_Channelx == DMA1_Channel1) + { + DMA1->INTFCR |= DMA1_Channel1_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel2) + { + DMA1->INTFCR |= DMA1_Channel2_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel3) + { + DMA1->INTFCR |= DMA1_Channel3_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel4) + { + DMA1->INTFCR |= DMA1_Channel4_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel5) + { + DMA1->INTFCR |= DMA1_Channel5_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel6) + { + DMA1->INTFCR |= DMA1_Channel6_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel7) + { + DMA1->INTFCR |= DMA1_Channel7_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel1) + { + DMA2->INTFCR |= DMA2_Channel1_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel2) + { + DMA2->INTFCR |= DMA2_Channel2_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel3) + { + DMA2->INTFCR |= DMA2_Channel3_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel4) + { + DMA2->INTFCR |= DMA2_Channel4_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel5) + { + DMA2->INTFCR |= DMA2_Channel5_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel6) + { + DMA2->INTFCR |= DMA2_Channel6_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel7) + { + DMA2->INTFCR |= DMA2_Channel7_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel8) + { + DMA2_EXTEN->INTFCR |= DMA2_Channel8_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel9) + { + DMA2_EXTEN->INTFCR |= DMA2_Channel9_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel10) + { + DMA2_EXTEN->INTFCR |= DMA2_Channel10_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel11) + { + DMA2_EXTEN->INTFCR |= DMA2_Channel11_IT_Mask; + } +} + +/********************************************************************* + * @fn DMA_Init + * + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitStruct. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + tmpreg = DMAy_Channelx->CFGR; + tmpreg &= CFGR_CLEAR_Mask; + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + + DMAy_Channelx->CFGR = tmpreg; + DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize; + DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr; + DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/********************************************************************* + * @fn DMA_StructInit + * + * @brief Fills each DMA_InitStruct member with its default value. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct) +{ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + DMA_InitStruct->DMA_BufferSize = 0; + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/********************************************************************* + * @fn DMA_Cmd + * + * @brief Enables or disables the specified DMAy Channelx. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_CFGR1_EN; + } + else + { + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + } +} + +/********************************************************************* + * @fn DMA_ITConfig + * + * @brief Enables or disables the specified DMAy Channelx interrupts. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * DMA_IT - specifies the DMA interrupts sources to be enabled + * or disabled. + * DMA_IT_TC - Transfer complete interrupt mask + * DMA_IT_HT - Half transfer interrupt mask + * DMA_IT_TE - Transfer error interrupt mask + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_IT; + } + else + { + DMAy_Channelx->CFGR &= ~DMA_IT; + } +} + +/********************************************************************* + * @fn DMA_SetCurrDataCounter + * + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * DataNumber - The number of data units in the current DMAy Channelx + * transfer. + * + * @return none + */ +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber) +{ + DMAy_Channelx->CNTR = DataNumber; +} + +/********************************************************************* + * @fn DMA_GetCurrDataCounter + * + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel. + * + * @return DataNumber - The number of remaining data units in the current + * DMAy Channelx transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx) +{ + return ((uint16_t)(DMAy_Channelx->CNTR)); +} + +/********************************************************************* + * @fn DMA_GetFlagStatus + * + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_FLAG_GL1 - DMA2 Channel1 global flag. + * DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag. + * DMA2_FLAG_GL2 - DMA2 Channel2 global flag. + * DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag. + * DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag. + * DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag. + * DMA2_FLAG_GL3 - DMA2 Channel3 global flag. + * DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag. + * DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag. + * DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag. + * DMA2_FLAG_GL4 - DMA2 Channel4 global flag. + * DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag. + * DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag. + * DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag. + * DMA2_FLAG_GL5 - DMA2 Channel5 global flag. + * DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag. + * DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag. + * DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag. + * DMA2_FLAG_GL6 - DMA2 Channel6 global flag. + * DMA2_FLAG_TC6 - DMA2 Channel6 transfer complete flag. + * DMA2_FLAG_HT6 - DMA2 Channel6 half transfer flag. + * DMA2_FLAG_TE6 - DMA2 Channel6 transfer error flag. + * DMA2_FLAG_GL7 - DMA2 Channel7 global flag. + * DMA2_FLAG_TC7 - DMA2 Channel7 transfer complete flag. + * DMA2_FLAG_HT7 - DMA2 Channel7 half transfer flag. + * DMA2_FLAG_TE7 - DMA2 Channel7 transfer error flag. + * DMA2_FLAG_GL8 - DMA2 Channel8 global flag. + * DMA2_FLAG_TC8 - DMA2 Channel8 transfer complete flag. + * DMA2_FLAG_HT8 - DMA2 Channel8 half transfer flag. + * DMA2_FLAG_TE8 - DMA2 Channel8 transfer error flag. + * DMA2_FLAG_GL9 - DMA2 Channel9 global flag. + * DMA2_FLAG_TC9 - DMA2 Channel9 transfer complete flag. + * DMA2_FLAG_HT9 - DMA2 Channel9 half transfer flag. + * DMA2_FLAG_TE9 - DMA2 Channel9 transfer error flag. + * DMA2_FLAG_GL10 - DMA2 Channel10 global flag. + * DMA2_FLAG_TC10 - DMA2 Channel10 transfer complete flag. + * DMA2_FLAG_HT10 - DMA2 Channel10 half transfer flag. + * DMA2_FLAG_TE10 - DMA2 Channel10 transfer error flag. + * DMA2_FLAG_GL11 - DMA2 Channel11 global flag. + * DMA2_FLAG_TC11 - DMA2 Channel11 transfer complete flag. + * DMA2_FLAG_HT11 - DMA2 Channel11 half transfer flag. + * DMA2_FLAG_TE11 - DMA2 Channel11 transfer error flag. + * + * @return The new state of DMAy_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + if((DMAy_FLAG & FLAG_Mask) == FLAG_Mask) + { + tmpreg = DMA2->INTFR; + } + else if((DMAy_FLAG & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask) + { + tmpreg = DMA2_EXTEN->INTFR; + } + else + { + tmpreg = DMA1->INTFR; + } + + if((tmpreg & DMAy_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearFlag + * + * @brief Clears the DMAy Channelx's pending flags. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_FLAG_GL1 - DMA2 Channel1 global flag. + * DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag. + * DMA2_FLAG_GL2 - DMA2 Channel2 global flag. + * DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag. + * DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag. + * DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag. + * DMA2_FLAG_GL3 - DMA2 Channel3 global flag. + * DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag. + * DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag. + * DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag. + * DMA2_FLAG_GL4 - DMA2 Channel4 global flag. + * DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag. + * DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag. + * DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag. + * DMA2_FLAG_GL5 - DMA2 Channel5 global flag. + * DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag. + * DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag. + * DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag. + * DMA2_FLAG_GL6 - DMA2 Channel6 global flag. + * DMA2_FLAG_TC6 - DMA2 Channel6 transfer complete flag. + * DMA2_FLAG_HT6 - DMA2 Channel6 half transfer flag. + * DMA2_FLAG_TE6 - DMA2 Channel6 transfer error flag. + * DMA2_FLAG_GL7 - DMA2 Channel7 global flag. + * DMA2_FLAG_TC7 - DMA2 Channel7 transfer complete flag. + * DMA2_FLAG_HT7 - DMA2 Channel7 half transfer flag. + * DMA2_FLAG_TE7 - DMA2 Channel7 transfer error flag. + * DMA2_FLAG_GL8 - DMA2 Channel8 global flag. + * DMA2_FLAG_TC8 - DMA2 Channel8 transfer complete flag. + * DMA2_FLAG_HT8 - DMA2 Channel8 half transfer flag. + * DMA2_FLAG_TE8 - DMA2 Channel8 transfer error flag. + * DMA2_FLAG_GL9 - DMA2 Channel9 global flag. + * DMA2_FLAG_TC9 - DMA2 Channel9 transfer complete flag. + * DMA2_FLAG_HT9 - DMA2 Channel9 half transfer flag. + * DMA2_FLAG_TE9 - DMA2 Channel9 transfer error flag. + * DMA2_FLAG_GL10 - DMA2 Channel10 global flag. + * DMA2_FLAG_TC10 - DMA2 Channel10 transfer complete flag. + * DMA2_FLAG_HT10 - DMA2 Channel10 half transfer flag. + * DMA2_FLAG_TE10 - DMA2 Channel10 transfer error flag. + * DMA2_FLAG_GL11 - DMA2 Channel11 global flag. + * DMA2_FLAG_TC11 - DMA2 Channel11 transfer complete flag. + * DMA2_FLAG_HT11 - DMA2 Channel11 half transfer flag. + * DMA2_FLAG_TE11 - DMA2 Channel11 transfer error flag. + * + * @return none + */ +void DMA_ClearFlag(uint32_t DMAy_FLAG) +{ + if((DMAy_FLAG & FLAG_Mask) == FLAG_Mask) + { + DMA2->INTFCR = DMAy_FLAG; + } + else if((DMAy_FLAG & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask) + { + DMA2_EXTEN->INTFCR = DMAy_FLAG; + } + else + { + DMA1->INTFCR = DMAy_FLAG; + } +} + +/********************************************************************* + * @fn DMA_GetITStatus + * + * @brief Checks whether the specified DMAy Channelx interrupt has + * occurred or not. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_IT_GL1 - DMA2 Channel1 global flag. + * DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_IT_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_IT_TE1 - DMA2 Channel1 transfer error flag. + * DMA2_IT_GL2 - DMA2 Channel2 global flag. + * DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag. + * DMA2_IT_HT2 - DMA2 Channel2 half transfer flag. + * DMA2_IT_TE2 - DMA2 Channel2 transfer error flag. + * DMA2_IT_GL3 - DMA2 Channel3 global flag. + * DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag. + * DMA2_IT_HT3 - DMA2 Channel3 half transfer flag. + * DMA2_IT_TE3 - DMA2 Channel3 transfer error flag. + * DMA2_IT_GL4 - DMA2 Channel4 global flag. + * DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag. + * DMA2_IT_HT4 - DMA2 Channel4 half transfer flag. + * DMA2_IT_TE4 - DMA2 Channel4 transfer error flag. + * DMA2_IT_GL5 - DMA2 Channel5 global flag. + * DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag. + * DMA2_IT_HT5 - DMA2 Channel5 half transfer flag. + * DMA2_IT_TE5 - DMA2 Channel5 transfer error flag. + * DMA2_IT_GL6 - DMA2 Channel6 global flag. + * DMA2_IT_TC6 - DMA2 Channel6 transfer complete flag. + * DMA2_IT_HT6 - DMA2 Channel6 half transfer flag. + * DMA2_IT_TE6 - DMA2 Channel6 transfer error flag. + * DMA2_IT_GL7 - DMA2 Channel7 global flag. + * DMA2_IT_TC7 - DMA2 Channel7 transfer complete flag. + * DMA2_IT_HT7 - DMA2 Channel7 half transfer flag. + * DMA2_IT_TE7 - DMA2 Channel7 transfer error flag. + * DMA2_IT_GL8 - DMA2 Channel8 global flag. + * DMA2_IT_TC8 - DMA2 Channel8 transfer complete flag. + * DMA2_IT_HT8 - DMA2 Channel8 half transfer flag. + * DMA2_IT_TE8 - DMA2 Channel8 transfer error flag. + * DMA2_IT_GL9 - DMA2 Channel9 global flag. + * DMA2_IT_TC9 - DMA2 Channel9 transfer complete flag. + * DMA2_IT_HT9 - DMA2 Channel9 half transfer flag. + * DMA2_IT_TE9 - DMA2 Channel9 transfer error flag. + * DMA2_IT_GL10 - DMA2 Channel10 global flag. + * DMA2_IT_TC10 - DMA2 Channel10 transfer complete flag. + * DMA2_IT_HT10 - DMA2 Channel10 half transfer flag. + * DMA2_IT_TE10 - DMA2 Channel10 transfer error flag. + * DMA2_IT_GL11 - DMA2 Channel11 global flag. + * DMA2_IT_TC11 - DMA2 Channel11 transfer complete flag. + * DMA2_IT_HT11 - DMA2 Channel11 half transfer flag. + * DMA2_IT_TE11 - DMA2 Channel11 transfer error flag. + * + * @return The new state of DMAy_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMAy_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + if((DMAy_IT & FLAG_Mask) == FLAG_Mask) + { + tmpreg = DMA2->INTFR; + } + else if((DMAy_IT & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask) + { + tmpreg = DMA2_EXTEN->INTFR; + } + else + { + tmpreg = DMA1->INTFR; + } + + if((tmpreg & DMAy_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearITPendingBit + * + * @brief Clears the DMAy Channelx's interrupt pending bits. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_IT_GL1 - DMA2 Channel1 global flag. + * DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_IT_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_IT_TE1 - DMA2 Channel1 transfer error flag. + * DMA2_IT_GL2 - DMA2 Channel2 global flag. + * DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag. + * DMA2_IT_HT2 - DMA2 Channel2 half transfer flag. + * DMA2_IT_TE2 - DMA2 Channel2 transfer error flag. + * DMA2_IT_GL3 - DMA2 Channel3 global flag. + * DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag. + * DMA2_IT_HT3 - DMA2 Channel3 half transfer flag. + * DMA2_IT_TE3 - DMA2 Channel3 transfer error flag. + * DMA2_IT_GL4 - DMA2 Channel4 global flag. + * DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag. + * DMA2_IT_HT4 - DMA2 Channel4 half transfer flag. + * DMA2_IT_TE4 - DMA2 Channel4 transfer error flag. + * DMA2_IT_GL5 - DMA2 Channel5 global flag. + * DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag. + * DMA2_IT_HT5 - DMA2 Channel5 half transfer flag. + * DMA2_IT_TE5 - DMA2 Channel5 transfer error flag. + * DMA2_IT_GL6 - DMA2 Channel6 global flag. + * DMA2_IT_TC6 - DMA2 Channel6 transfer complete flag. + * DMA2_IT_HT6 - DMA2 Channel6 half transfer flag. + * DMA2_IT_TE6 - DMA2 Channel6 transfer error flag. + * DMA2_IT_GL7 - DMA2 Channel7 global flag. + * DMA2_IT_TC7 - DMA2 Channel7 transfer complete flag. + * DMA2_IT_HT7 - DMA2 Channel7 half transfer flag. + * DMA2_IT_TE7 - DMA2 Channel7 transfer error flag. + * DMA2_IT_GL8 - DMA2 Channel8 global flag. + * DMA2_IT_TC8 - DMA2 Channel8 transfer complete flag. + * DMA2_IT_HT8 - DMA2 Channel8 half transfer flag. + * DMA2_IT_TE8 - DMA2 Channel8 transfer error flag. + * DMA2_IT_GL9 - DMA2 Channel9 global flag. + * DMA2_IT_TC9 - DMA2 Channel9 transfer complete flag. + * DMA2_IT_HT9 - DMA2 Channel9 half transfer flag. + * DMA2_IT_TE9 - DMA2 Channel9 transfer error flag. + * DMA2_IT_GL10 - DMA2 Channel10 global flag. + * DMA2_IT_TC10 - DMA2 Channel10 transfer complete flag. + * DMA2_IT_HT10 - DMA2 Channel10 half transfer flag. + * DMA2_IT_TE10 - DMA2 Channel10 transfer error flag. + * DMA2_IT_GL11 - DMA2 Channel11 global flag. + * DMA2_IT_TC11 - DMA2 Channel11 transfer complete flag. + * DMA2_IT_HT11 - DMA2 Channel11 half transfer flag. + * DMA2_IT_TE11 - DMA2 Channel11 transfer error flag. + * + * @return none + */ +void DMA_ClearITPendingBit(uint32_t DMAy_IT) +{ + if((DMAy_IT & FLAG_Mask) == FLAG_Mask) + { + DMA2->INTFCR = DMAy_IT; + } + else if((DMAy_IT & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask) + { + DMA2_EXTEN->INTFCR = DMAy_IT; + } + else + { + DMA1->INTFCR = DMAy_IT; + } +} diff --git a/Peripheral/src/ch32v30x_dvp.c b/Peripheral/src/ch32v30x_dvp.c new file mode 100644 index 0000000..225f981 --- /dev/null +++ b/Peripheral/src/ch32v30x_dvp.c @@ -0,0 +1,135 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_dvp.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the DVP firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_dvp.h" + +/********************************************************************* + * @fn DVP_INTCfg + * + * @brief DVP interrupt configuration + * + * @param s - interrupt enable + * ENABLE + * DISABLE + * i - interrupt type + * RB_DVP_IE_STP_FRM + * RB_DVP_IE_FIFO_OV + * RB_DVP_IE_FRM_DONE + * RB_DVP_IE_ROW_DONE + * RB_DVP_IE_STR_FRM + * + * @return none + */ +void DVP_INTCfg(uint8_t s, uint8_t i) +{ + if(s) + { + DVP->IER |= i; + } + else + { + DVP->IER &= ~i; + } +} + +/********************************************************************* + * @fn DVP_Mode + * + * @brief DVP mode + * + * @param s - data bit width + * RB_DVP_D8_MOD + * RB_DVP_D10_MOD + * RB_DVP_D12_MOD + * i - interrupt type + * Video_Mode + * JPEG_Mode + * + * @return none + */ +void DVP_Mode(uint8_t s, DVP_Data_ModeTypeDef i) +{ + DVP->CR0 &= ~RB_DVP_MSK_DAT_MOD; + + if(s) + { + DVP->CR0 |= s; + } + else + { + DVP->CR0 &= ~(3 << 4); + } + + if(i) + { + DVP->CR0 |= RB_DVP_JPEG; + } + else + { + DVP->CR0 &= ~RB_DVP_JPEG; + } +} + +/********************************************************************* + * @fn DVP_Cfg + * + * @brief DVP configuration + * + * @param s - DMA enable control + * DVP_DMA_Enable + * DVP_DMA_Disable + * i - DVP all clear + * DVP_FLAG_FIFO_RESET_Enable + * DVP_FLAG_FIFO_RESET_Disable + * j - receive reset enable + * DVP_RX_RESET_Enable + * DVP_RX_RESET_Disable + * + * @return none + */ +void DVP_Cfg(DVP_DMATypeDef s, DVP_FLAG_FIFO_RESETTypeDef i, DVP_RX_RESETTypeDef j) +{ + switch(s) + { + case DVP_DMA_Enable: + DVP->CR1 |= RB_DVP_DMA_EN; + break; + case DVP_DMA_Disable: + DVP->CR1 &= ~RB_DVP_DMA_EN; + break; + default: + break; + } + + switch(i) + { + case DVP_RX_RESET_Enable: + DVP->CR1 |= RB_DVP_ALL_CLR; + break; + case DVP_RX_RESET_Disable: + DVP->CR1 &= ~RB_DVP_ALL_CLR; + break; + default: + break; + } + + switch(j) + { + case DVP_RX_RESET_Enable: + DVP->CR1 |= RB_DVP_RCV_CLR; + break; + case DVP_RX_RESET_Disable: + DVP->CR1 &= ~RB_DVP_RCV_CLR; + break; + default: + break; + } +} diff --git a/Peripheral/src/ch32v30x_eth.c b/Peripheral/src/ch32v30x_eth.c new file mode 100644 index 0000000..2e98991 --- /dev/null +++ b/Peripheral/src/ch32v30x_eth.c @@ -0,0 +1,2524 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_eth.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the ETH firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_eth.h" +#include "ch32v30x_rcc.h" + +ETH_DMADESCTypeDef *DMATxDescToSet; +ETH_DMADESCTypeDef *DMARxDescToGet; +ETH_DMADESCTypeDef *DMAPTPTxDescToSet; +ETH_DMADESCTypeDef *DMAPTPRxDescToGet; + +/********************************************************************* + * @fn ETH_DeInit + * + * @brief ETH hardware initialize again. + * + * @return none + */ +#ifdef CH32V30x_D8C +void ETH_DeInit(void) +{ + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, ENABLE); + RCC_AHBPeriphResetCmd(RCC_AHBPeriph_ETH_MAC, DISABLE); +} + +#endif + +/********************************************************************* + * @fn ETH_StructInit + * + * @brief Fills each ETH_InitStruct member with its default value. + * + * @param ETH_InitStruct - pointer to a ETH_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void ETH_StructInit(ETH_InitTypeDef *ETH_InitStruct) +{ + /*------------------------ MAC -----------------------------------*/ + ETH_InitStruct->ETH_AutoNegotiation = ETH_AutoNegotiation_Disable; + ETH_InitStruct->ETH_Watchdog = ETH_Watchdog_Enable; + ETH_InitStruct->ETH_Jabber = ETH_Jabber_Enable; + ETH_InitStruct->ETH_InterFrameGap = ETH_InterFrameGap_96Bit; + ETH_InitStruct->ETH_CarrierSense = ETH_CarrierSense_Enable; + ETH_InitStruct->ETH_Speed = ETH_Speed_10M; + ETH_InitStruct->ETH_ReceiveOwn = ETH_ReceiveOwn_Enable; + ETH_InitStruct->ETH_LoopbackMode = ETH_LoopbackMode_Disable; + ETH_InitStruct->ETH_Mode = ETH_Mode_HalfDuplex; + ETH_InitStruct->ETH_ChecksumOffload = ETH_ChecksumOffload_Disable; + ETH_InitStruct->ETH_RetryTransmission = ETH_RetryTransmission_Enable; + ETH_InitStruct->ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable; + ETH_InitStruct->ETH_BackOffLimit = ETH_BackOffLimit_10; + ETH_InitStruct->ETH_DeferralCheck = ETH_DeferralCheck_Disable; + ETH_InitStruct->ETH_ReceiveAll = ETH_ReceiveAll_Disable; + ETH_InitStruct->ETH_SourceAddrFilter = ETH_SourceAddrFilter_Disable; + ETH_InitStruct->ETH_PassControlFrames = ETH_PassControlFrames_BlockAll; + ETH_InitStruct->ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Disable; + ETH_InitStruct->ETH_DestinationAddrFilter = ETH_DestinationAddrFilter_Normal; + ETH_InitStruct->ETH_PromiscuousMode = ETH_PromiscuousMode_Disable; + ETH_InitStruct->ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect; + ETH_InitStruct->ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect; + ETH_InitStruct->ETH_HashTableHigh = 0x0; + ETH_InitStruct->ETH_HashTableLow = 0x0; + ETH_InitStruct->ETH_PauseTime = 0x0; + ETH_InitStruct->ETH_ZeroQuantaPause = ETH_ZeroQuantaPause_Disable; + ETH_InitStruct->ETH_PauseLowThreshold = ETH_PauseLowThreshold_Minus4; + ETH_InitStruct->ETH_UnicastPauseFrameDetect = ETH_UnicastPauseFrameDetect_Disable; + ETH_InitStruct->ETH_ReceiveFlowControl = ETH_ReceiveFlowControl_Disable; + ETH_InitStruct->ETH_TransmitFlowControl = ETH_TransmitFlowControl_Disable; + ETH_InitStruct->ETH_VLANTagComparison = ETH_VLANTagComparison_16Bit; + ETH_InitStruct->ETH_VLANTagIdentifier = 0x0; + /*------------------------ DMA -----------------------------------*/ + ETH_InitStruct->ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Disable; + ETH_InitStruct->ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable; + ETH_InitStruct->ETH_FlushReceivedFrame = ETH_FlushReceivedFrame_Enable; + ETH_InitStruct->ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable; + ETH_InitStruct->ETH_TransmitThresholdControl = ETH_TransmitThresholdControl_64Bytes; + ETH_InitStruct->ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable; + ETH_InitStruct->ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable; + ETH_InitStruct->ETH_ReceiveThresholdControl = ETH_ReceiveThresholdControl_64Bytes; + ETH_InitStruct->ETH_SecondFrameOperate = ETH_SecondFrameOperate_Disable; + ETH_InitStruct->ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable; + ETH_InitStruct->ETH_FixedBurst = ETH_FixedBurst_Disable; + ETH_InitStruct->ETH_RxDMABurstLength = ETH_RxDMABurstLength_1Beat; + ETH_InitStruct->ETH_TxDMABurstLength = ETH_TxDMABurstLength_1Beat; + ETH_InitStruct->ETH_DescriptorSkipLength = 0x0; + ETH_InitStruct->ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_1_1; +} + +/********************************************************************* + * @fn ETH_Start + * + * @brief Enables ENET MAC and DMA reception/transmission. + * + * @return none + */ +void ETH_Start(void) +{ + ETH_MACTransmissionCmd(ENABLE); + ETH_FlushTransmitFIFO(); + ETH_MACReceptionCmd(ENABLE); + ETH_DMATransmissionCmd(ENABLE); + ETH_DMAReceptionCmd(ENABLE); +} + +/********************************************************************* + * @fn ETH_HandleTxPkt + * + * @brief Transmits a packet, from application buffer, pointed by ppkt. + * + * @param ppkt - pointer to the application's packet buffer to transmit. + * FrameLength - Tx Packet size. + * + * @return ETH_ERROR - in case of Tx desc owned by DMA. + * ETH_SUCCESS - for correct transmission. + */ +uint32_t ETH_HandleTxPkt(uint8_t *ppkt, uint16_t FrameLength) +{ + uint32_t offset = 0; + + if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) + { + return ETH_ERROR; + } + + for(offset = 0; offset < FrameLength; offset++) + { + (*(__IO uint8_t *)((DMATxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset)); + } + + DMATxDescToSet->ControlBufferSize = (FrameLength & ETH_DMATxDesc_TBS1); + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + + if((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + ETH->DMASR = ETH_DMASR_TBUS; + ETH->DMATPDR = 0; + } + + if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)(DMATxDescToSet->Buffer2NextDescAddr); + } + else + { + if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)(ETH->DMATDLAR); + } + else + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + return ETH_SUCCESS; +} + +/********************************************************************* + * @fn ETH_HandleRxPkt + * + * @brief Receives a packet and copies it to memory pointed by ppkt. + * + * @param ppkt - pointer to the application packet receive buffer. + * + * @return ETH_ERROR - if there is error in reception + * framelength - received packet size if packet reception is correct + */ +uint32_t ETH_HandleRxPkt(uint8_t *ppkt) +{ + uint32_t offset = 0, framelength = 0; + + if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) + { + return ETH_ERROR; + } + + if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; + + for(offset = 0; offset < framelength; offset++) + { + (*(ppkt + offset)) = (*(__IO uint8_t *)((DMARxDescToGet->Buffer1Addr) + offset)); + } + } + else + { + framelength = ETH_ERROR; + } + + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; + + if((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) + { + ETH->DMASR = ETH_DMASR_RBUS; + ETH->DMARPDR = 0; + } + + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(DMARxDescToGet->Buffer2NextDescAddr); + } + else + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(ETH->DMARDLAR); + } + else + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + return (framelength); +} + +/********************************************************************* + * @fn ETH_GetRxPktSize + * + * @brief Get the size of received the received packet. + * + * @return framelength - received packet size + */ +uint32_t ETH_GetRxPktSize(void) +{ + uint32_t frameLength = 0; + if(((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + frameLength = ETH_GetDMARxDescFrameLength(DMARxDescToGet); + } + + return frameLength; +} + +/********************************************************************* + * @fn ETH_DropRxPkt + * + * @brief Drop a Received packet. + * + * @return none + */ +void ETH_DropRxPkt(void) +{ + DMARxDescToGet->Status = ETH_DMARxDesc_OWN; + + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(DMARxDescToGet->Buffer2NextDescAddr); + } + else + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(ETH->DMARDLAR); + } + else + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } +} + +/********************************************************************* + * @fn ETH_ReadPHYRegister + * + * @brief Read a PHY register. + * + * @param PHYAddress - PHY device address, is the index of one of supported 32 PHY devices. + * PHYReg - PHY register address, is the index of one of the 32 PHY register. + * + * @return ETH_ERROR - in case of timeout. + * MAC MIIDR register value - Data read from the selected PHY register. + */ +uint16_t ETH_ReadPHYRegister(uint16_t PHYAddress, uint16_t PHYReg) +{ + uint32_t tmpreg = 0; + __IO uint32_t timeout = 0; + + tmpreg = ETH->MACMIIAR; + tmpreg &= ~MACMIIAR_CR_MASK; + tmpreg |= (((uint32_t)PHYAddress << 11) & ETH_MACMIIAR_PA); + tmpreg |= (((uint32_t)PHYReg << 6) & ETH_MACMIIAR_MR); + tmpreg &= ~ETH_MACMIIAR_MW; + tmpreg |= ETH_MACMIIAR_MB; + ETH->MACMIIAR = tmpreg; + + do + { + timeout++; + tmpreg = ETH->MACMIIAR; + } while((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_READ_TO)); + + if(timeout == PHY_READ_TO) + { + return (uint16_t)ETH_ERROR; + } + + return (uint16_t)(ETH->MACMIIDR); +} + +/********************************************************************* + * @fn ETH_WritePHYRegister + * + * @brief Write to a PHY register. + * + * @param PHYAddress - PHY device address, is the index of one of supported 32 PHY devices. + * PHYReg - PHY register address, is the index of one of the 32 PHY register. + * PHYValue - the value to write. + * + * @return ETH_ERROR - in case of timeout. + * ETH_SUCCESS - for correct write + */ +uint32_t ETH_WritePHYRegister(uint16_t PHYAddress, uint16_t PHYReg, uint16_t PHYValue) +{ + uint32_t tmpreg = 0; + __IO uint32_t timeout = 0; + + tmpreg = ETH->MACMIIAR; + tmpreg &= ~MACMIIAR_CR_MASK; + tmpreg |= (((uint32_t)PHYAddress << 11) & ETH_MACMIIAR_PA); + tmpreg |= (((uint32_t)PHYReg << 6) & ETH_MACMIIAR_MR); + tmpreg |= ETH_MACMIIAR_MW; + tmpreg |= ETH_MACMIIAR_MB; + ETH->MACMIIDR = PHYValue; + ETH->MACMIIAR = tmpreg; + + do + { + timeout++; + tmpreg = ETH->MACMIIAR; + } while((tmpreg & ETH_MACMIIAR_MB) && (timeout < (uint32_t)PHY_WRITE_TO)); + + if(timeout >= PHY_WRITE_TO) + { + return ETH_ERROR; + } + + return ETH_SUCCESS; +} + +/********************************************************************* + * @fn ETH_PHYLoopBackCmd + * + * @brief Enables or disables the PHY loopBack mode. + * + * @param PHYAddress - PHY device address, is the index of one of supported 32 PHY devices. + * NewState - new state of the PHY loopBack mode. + * + * @return ETH_ERROR - in case of bad PHY configuration. + * ETH_SUCCESS - for correct PHY configuration. + */ +uint32_t ETH_PHYLoopBackCmd(uint16_t PHYAddress, FunctionalState NewState) +{ + uint16_t tmpreg = 0; + + tmpreg = ETH_ReadPHYRegister(PHYAddress, PHY_BCR); + + if(NewState != DISABLE) + { + tmpreg |= PHY_Loopback; + } + else + { + tmpreg &= (uint16_t)(~(uint16_t)PHY_Loopback); + } + + if(ETH_WritePHYRegister(PHYAddress, PHY_BCR, tmpreg) != (uint32_t)RESET) + { + return ETH_SUCCESS; + } + else + { + return ETH_ERROR; + } +} + +/********************************************************************* + * @fn ETH_MACTransmissionCmd + * + * @brief Enables or disables the MAC transmission. + * + * @param NewState - new state of the MAC transmission. + * + * @return none + */ +void ETH_MACTransmissionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACCR |= ETH_MACCR_TE; + } + else + { + ETH->MACCR &= ~ETH_MACCR_TE; + } +} + +/********************************************************************* + * @fn ETH_MACReceptionCmd + * + * @brief Enables or disables the MAC reception. + * + * @param NewState - new state of the MAC reception. + * + * @return none + */ +void ETH_MACReceptionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACCR |= ETH_MACCR_RE; + } + else + { + ETH->MACCR &= ~ETH_MACCR_RE; + } +} + +/********************************************************************* + * @fn ETH_GetFlowControlBusyStatus + * + * @brief Enables or disables the MAC reception. + * + * @return The new state of flow control busy status bit (SET or RESET). + */ +FlagStatus ETH_GetFlowControlBusyStatus(void) +{ + FlagStatus bitstatus = RESET; + + if((ETH->MACFCR & ETH_MACFCR_FCBBPA) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_InitiatePauseControlFrame + * + * @brief Initiate a Pause Control Frame (Full-duplex only). + * + * @return none + */ +void ETH_InitiatePauseControlFrame(void) +{ + ETH->MACFCR |= ETH_MACFCR_FCBBPA; +} + +/********************************************************************* + * @fn ETH_BackPressureActivationCmd + * + * @brief Enables or disables the MAC BackPressure operation activation (Half-duplex only). + * + * @param NewState - new state of the MAC BackPressure operation activation. + * + * @return none + */ +void ETH_BackPressureActivationCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACFCR |= ETH_MACFCR_FCBBPA; + } + else + { + ETH->MACFCR &= ~ETH_MACFCR_FCBBPA; + } +} + +/********************************************************************* + * @fn ETH_GetMACFlagStatus + * + * @brief Checks whether the specified ETHERNET MAC flag is set or not. + * + * @param ETH_MAC_FLAG - specifies the flag to check. + * + * @return The new state of ETHERNET MAC flag (SET or RESET). + */ +FlagStatus ETH_GetMACFlagStatus(uint32_t ETH_MAC_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ETH->MACSR & ETH_MAC_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetMACITStatus + * + * @brief Checks whether the specified ETHERNET MAC interrupt has occurred or not. + * + * @param ETH_MAC_IT - specifies the interrupt source to check. + * + * @return The new state of ETHERNET MAC interrupt (SET or RESET). + */ +ITStatus ETH_GetMACITStatus(uint32_t ETH_MAC_IT) +{ + FlagStatus bitstatus = RESET; + + if((ETH->MACSR & ETH_MAC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_MACITConfig + * + * @brief Enables or disables the specified ETHERNET MAC interrupts. + * + * @param ETH_MAC_IT - specifies the interrupt source to check. + * NewState - new state of the specified ETHERNET MAC interrupts. + * + * @return none + */ +void ETH_MACITConfig(uint32_t ETH_MAC_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACIMR &= (~(uint32_t)ETH_MAC_IT); + } + else + { + ETH->MACIMR |= ETH_MAC_IT; + } +} + +/********************************************************************* + * @fn ETH_MACAddressConfig + * + * @brief Configures the selected MAC address. + * + * @param MacAddr - The MAC addres to configure. + * ETH_MAC_Address0 - MAC Address0 + * ETH_MAC_Address1 - MAC Address1 + * ETH_MAC_Address2 - MAC Address2 + * ETH_MAC_Address3 - MAC Address3 + * Addr - Pointer on MAC address buffer data (6 bytes). + * + * @return none + */ +void ETH_MACAddressConfig(uint32_t MacAddr, uint8_t *Addr) +{ + uint32_t tmpreg; + + tmpreg = ((uint32_t)Addr[5] << 8) | (uint32_t)Addr[4]; + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) = tmpreg; + tmpreg = ((uint32_t)Addr[3] << 24) | ((uint32_t)Addr[2] << 16) | ((uint32_t)Addr[1] << 8) | Addr[0]; + + (*(__IO uint32_t *)(ETH_MAC_ADDR_LBASE + MacAddr)) = tmpreg; +} + +/********************************************************************* + * @fn ETH_GetMACAddress + * + * @brief Get the selected MAC address. + * + * @param MacAddr - The MAC address to return. + * ETH_MAC_Address0 - MAC Address0 + * ETH_MAC_Address1 - MAC Address1 + * ETH_MAC_Address2 - MAC Address2 + * ETH_MAC_Address3 - MAC Address3 + * Addr - Pointer on MAC address buffer data (6 bytes). + * + * @return none + */ +void ETH_GetMACAddress(uint32_t MacAddr, uint8_t *Addr) +{ + uint32_t tmpreg; + + tmpreg = (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)); + + Addr[5] = ((tmpreg >> 8) & (uint8_t)0xFF); + Addr[4] = (tmpreg & (uint8_t)0xFF); + tmpreg = (*(__IO uint32_t *)(ETH_MAC_ADDR_LBASE + MacAddr)); + Addr[3] = ((tmpreg >> 24) & (uint8_t)0xFF); + Addr[2] = ((tmpreg >> 16) & (uint8_t)0xFF); + Addr[1] = ((tmpreg >> 8) & (uint8_t)0xFF); + Addr[0] = (tmpreg & (uint8_t)0xFF); +} + +/********************************************************************* + * @fn ETH_MACAddressPerfectFilterCmd + * + * @brief Enables or disables the Address filter module uses the specified. + * + * @param MacAddr - The MAC address to return. + * ETH_MAC_Address0 - MAC Address0 + * ETH_MAC_Address1 - MAC Address1 + * ETH_MAC_Address2 - MAC Address2 + * ETH_MAC_Address3 - MAC Address3 + * NewState - new state of the specified ETHERNET MAC address use. + * + * @return none + */ +void ETH_MACAddressPerfectFilterCmd(uint32_t MacAddr, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_AE; + } + else + { + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) &= (~(uint32_t)ETH_MACA1HR_AE); + } +} + +/********************************************************************* + * @fn ETH_MACAddressFilterConfig + * + * @brief Set the filter type for the specified ETHERNET MAC address. + * + * @param MacAddr - specifies the ETHERNET MAC address. + * ETH_MAC_Address0 - MAC Address0 + * ETH_MAC_Address1 - MAC Address1 + * ETH_MAC_Address2 - MAC Address2 + * ETH_MAC_Address3 - MAC Address3 + * Filter - specifies the used frame received field for comparaison. + * ETH_MAC_AddressFilter_SA - MAC Address is used to compare with the + * SA fields of the received frame. + * ETH_MAC_AddressFilter_DA - MAC Address is used to compare with the + * DA fields of the received frame. + * + * @return none + */ +void ETH_MACAddressFilterConfig(uint32_t MacAddr, uint32_t Filter) +{ + if(Filter != ETH_MAC_AddressFilter_DA) + { + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) |= ETH_MACA1HR_SA; + } + else + { + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) &= (~(uint32_t)ETH_MACA1HR_SA); + } +} + +/********************************************************************* + * @fn ETH_MACAddressMaskBytesFilterConfig + * + * @brief Set the filter type for the specified ETHERNET MAC address. + * + * @param MacAddr - specifies the ETHERNET MAC address. + * ETH_MAC_Address1 - MAC Address1 + * ETH_MAC_Address2 - MAC Address2 + * ETH_MAC_Address3 - MAC Address3 + * MaskByte - specifies the used address bytes for comparaison + * ETH_MAC_AddressMask_Byte5 - Mask MAC Address high reg bits [7:0]. + * ETH_MAC_AddressMask_Byte4 - Mask MAC Address low reg bits [31:24]. + * ETH_MAC_AddressMask_Byte3 - Mask MAC Address low reg bits [23:16]. + * ETH_MAC_AddressMask_Byte2 - Mask MAC Address low reg bits [15:8]. + * ETH_MAC_AddressMask_Byte1 - Mask MAC Address low reg bits [7:0]. + * + * @return none + */ +void ETH_MACAddressMaskBytesFilterConfig(uint32_t MacAddr, uint32_t MaskByte) +{ + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) &= (~(uint32_t)ETH_MACA1HR_MBC); + (*(__IO uint32_t *)(ETH_MAC_ADDR_HBASE + MacAddr)) |= MaskByte; +} + +/********************************************************************* + * @fn ETH_DMATxDescChainInit + * + * @brief Initializes the DMA Tx descriptors in chain mode. + * + * @param DMATxDescTab - Pointer on the first Tx desc list + * TxBuff - Pointer on the first TxBuffer list + * TxBuffCount - Number of the used Tx desc in the list + * + * @return none + */ +void ETH_DMATxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + DMATxDescToSet = DMATxDescTab; + + for(i = 0; i < TxBuffCount; i++) + { + DMATxDesc = DMATxDescTab + i; + DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_IC; + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i * ETH_MAX_PACKET_SIZE]); + + if(i < (TxBuffCount - 1)) + { + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab + i + 1); + } + else + { + DMATxDesc->Buffer2NextDescAddr = (uint32_t)DMATxDescTab; + } + } + + ETH->DMATDLAR = (uint32_t)DMATxDescTab; +} + +/********************************************************************* + * @fn ETH_DMATxDescRingInit + * + * @brief Initializes the DMA Tx descriptors in ring mode. + * + * @param DMATxDescTab - Pointer on the first Tx desc list. + * TxBuff1 - Pointer on the first TxBuffer1 list. + * TxBuff2 - Pointer on the first TxBuffer2 list. + * TxBuffCount - Number of the used Tx desc in the list. + * + * @return none + */ +void ETH_DMATxDescRingInit(ETH_DMADESCTypeDef *DMATxDescTab, uint8_t *TxBuff1, uint8_t *TxBuff2, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + DMATxDescToSet = DMATxDescTab; + + for(i = 0; i < TxBuffCount; i++) + { + DMATxDesc = DMATxDescTab + i; + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff1[i * ETH_MAX_PACKET_SIZE]); + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(&TxBuff2[i * ETH_MAX_PACKET_SIZE]); + + if(i == (TxBuffCount - 1)) + { + DMATxDesc->Status = ETH_DMATxDesc_TER; + } + } + + ETH->DMATDLAR = (uint32_t)DMATxDescTab; +} + +/********************************************************************* + * @fn ETH_GetDMATxDescFlagStatus + * + * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor + * ETH_DMATxDescFlag - specifies the flag to check. + * ETH_DMATxDesc_OWN - OWN bit - descriptor is owned by DMA engine + * ETH_DMATxDesc_IC - Interrupt on completetion + * ETH_DMATxDesc_LS - Last Segment + * ETH_DMATxDesc_FS - First Segment + * ETH_DMATxDesc_DC - Disable CRC + * ETH_DMATxDesc_DP - Disable Pad + * ETH_DMATxDesc_TTSE - Transmit Time Stamp Enable + * ETH_DMATxDesc_TER - Transmit End of Ring + * ETH_DMATxDesc_TCH - Second Address Chained + * ETH_DMATxDesc_TTSS - Tx Time Stamp Status + * ETH_DMATxDesc_IHE - IP Header Error + * ETH_DMATxDesc_ES - Error summary + * ETH_DMATxDesc_JT - Jabber Timeout + * ETH_DMATxDesc_FF - Frame Flushed - DMA/MTL flushed the frame due to SW flush + * ETH_DMATxDesc_PCE - Payload Checksum Error + * ETH_DMATxDesc_LCA - Loss of Carrier - carrier lost during tramsmission + * ETH_DMATxDesc_NC - No Carrier - no carrier signal from the tranceiver + * ETH_DMATxDesc_LCO - Late Collision - transmission aborted due to collision + * ETH_DMATxDesc_EC - Excessive Collision - transmission aborted after 16 collisions + * ETH_DMATxDesc_VF - VLAN Frame + * ETH_DMATxDesc_CC - Collision Count + * ETH_DMATxDesc_ED - Excessive Deferral + * ETH_DMATxDesc_UF - Underflow Error - late data arrival from the memory + * ETH_DMATxDesc_DB - Deferred Bit + * + * @return The new state of ETH_DMATxDescFlag (SET or RESET). + */ +FlagStatus ETH_GetDMATxDescFlagStatus(ETH_DMADESCTypeDef *DMATxDesc, uint32_t ETH_DMATxDescFlag) +{ + FlagStatus bitstatus = RESET; + + if((DMATxDesc->Status & ETH_DMATxDescFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetDMATxDescCollisionCount + * + * @brief Returns the specified ETHERNET DMA Tx Desc collision count. + * + * @param pointer on a DMA Tx descriptor. + * + * @return The Transmit descriptor collision counter value. + */ +uint32_t ETH_GetDMATxDescCollisionCount(ETH_DMADESCTypeDef *DMATxDesc) +{ + return ((DMATxDesc->Status & ETH_DMATxDesc_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT); +} + +/********************************************************************* + * @fn ETH_SetDMATxDescOwnBit + * + * @brief Set the specified DMA Tx Desc Own bit. + * + * @param DMATxDesc - Pointer on a Tx desc + * + * @return none + */ +void ETH_SetDMATxDescOwnBit(ETH_DMADESCTypeDef *DMATxDesc) +{ + DMATxDesc->Status |= ETH_DMATxDesc_OWN; +} + +/********************************************************************* + * @fn ETH_DMATxDescTransmitITConfig + * + * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. + * + * @param Pointer on a Tx desc. + * NewState - new state of the DMA Tx Desc transmit interrupt. + * + * @return none + */ +void ETH_DMATxDescTransmitITConfig(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status |= ETH_DMATxDesc_IC; + } + else + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_IC); + } +} + +/********************************************************************* + * @fn ETH_DMATxDescFrameSegmentConfig + * + * @brief Enables or disables the specified DMA Tx Desc Transmit interrupt. + * + * @param PDMATxDesc - Pointer on a Tx desc. + * ETH_DMATxDesc_FirstSegment - actual Tx desc contain first segment. + * + * @return none + */ +void ETH_DMATxDescFrameSegmentConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_FrameSegment) +{ + DMATxDesc->Status |= DMATxDesc_FrameSegment; +} + +/********************************************************************* + * @fn ETH_DMATxDescChecksumInsertionConfig + * + * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor. + * DMATxDesc_Checksum - specifies is the DMA Tx desc checksum insertion. + * + * @return none + */ +void ETH_DMATxDescChecksumInsertionConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t DMATxDesc_Checksum) +{ + DMATxDesc->Status |= DMATxDesc_Checksum; +} + +/********************************************************************* + * @fn ETH_DMATxDescCRCCmd + * + * @brief Enables or disables the DMA Tx Desc CRC. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor + * NewState - new state of the specified DMA Tx Desc CRC. + * + * @return none + */ +void ETH_DMATxDescCRCCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DC); + } + else + { + DMATxDesc->Status |= ETH_DMATxDesc_DC; + } +} + +/********************************************************************* + * @fn ETH_DMATxDescEndOfRingCmd + * + * @brief Enables or disables the DMA Tx Desc end of ring. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor. + * NewState - new state of the specified DMA Tx Desc end of ring. + * + * @return none + */ +void ETH_DMATxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status |= ETH_DMATxDesc_TER; + } + else + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TER); + } +} + +/********************************************************************* + * @fn ETH_DMATxDescSecondAddressChainedCmd + * + * @brief Enables or disables the DMA Tx Desc second address chained. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor + * NewState - new state of the specified DMA Tx Desc second address chained. + * + * @return none + */ +void ETH_DMATxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status |= ETH_DMATxDesc_TCH; + } + else + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TCH); + } +} + +/********************************************************************* + * @fn ETH_DMATxDescShortFramePaddingCmd + * + * @brief Enables or disables the DMA Tx Desc padding for frame shorter than 64 bytes. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor. + * NewState - new state of the specified DMA Tx Desc padding for frame shorter than 64 bytes. + * + * @return none + */ +void ETH_DMATxDescShortFramePaddingCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_DP); + } + else + { + DMATxDesc->Status |= ETH_DMATxDesc_DP; + } +} + +/********************************************************************* + * @fn ETH_DMATxDescTimeStampCmd + * + * @brief Enables or disables the DMA Tx Desc time stamp. + * + * @param DMATxDesc - pointer on a DMA Tx descriptor + * NewState - new state of the specified DMA Tx Desc time stamp. + * + * @return none + */ +void ETH_DMATxDescTimeStampCmd(ETH_DMADESCTypeDef *DMATxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMATxDesc->Status |= ETH_DMATxDesc_TTSE; + } + else + { + DMATxDesc->Status &= (~(uint32_t)ETH_DMATxDesc_TTSE); + } +} + +/********************************************************************* + * @fn ETH_DMATxDescBufferSizeConfig + * + * @brief Configures the specified DMA Tx Desc buffer1 and buffer2 sizes. + * + * @param DMATxDesc - Pointer on a Tx desc. + * BufferSize1 - specifies the Tx desc buffer1 size. + * RxBuff2 - Pointer on the first RxBuffer2 list + * BufferSize2 - specifies the Tx desc buffer2 size (put "0" if not used). + * + * @return none + */ +void ETH_DMATxDescBufferSizeConfig(ETH_DMADESCTypeDef *DMATxDesc, uint32_t BufferSize1, uint32_t BufferSize2) +{ + DMATxDesc->ControlBufferSize |= (BufferSize1 | (BufferSize2 << ETH_DMATXDESC_BUFFER2_SIZESHIFT)); +} + +/********************************************************************* + * @fn ETH_DMARxDescChainInit + * + * @brief Initializes the DMA Rx descriptors in chain mode. + * + * @param DMARxDescTab - Pointer on the first Rx desc list. + * RxBuff - Pointer on the first RxBuffer list. + * RxBuffCount - Number of the used Rx desc in the list. + * + * @return none + */ +void ETH_DMARxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + DMARxDescToGet = DMARxDescTab; + + for(i = 0; i < RxBuffCount; i++) + { + DMARxDesc = DMARxDescTab + i; + DMARxDesc->Status = ETH_DMARxDesc_OWN; + DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i * ETH_MAX_PACKET_SIZE]); + + if(i < (RxBuffCount - 1)) + { + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + i + 1); + } + else + { + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + } + } + + ETH->DMARDLAR = (uint32_t)DMARxDescTab; +} + +/********************************************************************* + * @fn ETH_DMARxDescRingInit + * + * @brief Initializes the DMA Rx descriptors in ring mode. + * + * @param DMARxDescTab - Pointer on the first Rx desc list. + * RxBuff1 - Pointer on the first RxBuffer1 list. + * RxBuff2 - Pointer on the first RxBuffer2 list + * RxBuffCount - Number of the used Rx desc in the list. + * + * @return none + */ +void ETH_DMARxDescRingInit(ETH_DMADESCTypeDef *DMARxDescTab, uint8_t *RxBuff1, uint8_t *RxBuff2, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + DMARxDescToGet = DMARxDescTab; + + for(i = 0; i < RxBuffCount; i++) + { + DMARxDesc = DMARxDescTab + i; + DMARxDesc->Status = ETH_DMARxDesc_OWN; + DMARxDesc->ControlBufferSize = ETH_MAX_PACKET_SIZE; + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff1[i * ETH_MAX_PACKET_SIZE]); + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(&RxBuff2[i * ETH_MAX_PACKET_SIZE]); + + if(i == (RxBuffCount - 1)) + { + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; + } + } + + ETH->DMARDLAR = (uint32_t)DMARxDescTab; +} + +/********************************************************************* + * @fn ETH_GetDMARxDescFlagStatus + * + * @brief Checks whether the specified ETHERNET Rx Desc flag is set or not. + * + * @param DMARxDesc - pointer on a DMA Rx descriptor. + * ETH_DMARxDescFlag - specifies the flag to check. + * ETH_DMARxDesc_OWN - OWN bit: descriptor is owned by DMA engine + * ETH_DMARxDesc_AFM - DA Filter Fail for the rx frame + * ETH_DMARxDesc_ES - Error summary + * ETH_DMARxDesc_DE - Desciptor error: no more descriptors for receive frame + * ETH_DMARxDesc_SAF - SA Filter Fail for the received frame + * ETH_DMARxDesc_LE - Frame size not matching with length field + * ETH_DMARxDesc_OE - Overflow Error: Frame was damaged due to buffer overflow + * ETH_DMARxDesc_VLAN - VLAN Tag: received frame is a VLAN frame + * ETH_DMARxDesc_FS - First descriptor of the frame + * ETH_DMARxDesc_LS - Last descriptor of the frame + * ETH_DMARxDesc_IPV4HCE - IPC Checksum Error/Giant Frame: Rx Ipv4 header checksum error + * ETH_DMARxDesc_LC - Late collision occurred during reception + * ETH_DMARxDesc_FT - Frame type - Ethernet, otherwise 802.3 + * ETH_DMARxDesc_RWT - Receive Watchdog Timeout: watchdog timer expired during reception + * ETH_DMARxDesc_RE - Receive error: error reported by MII interface + * ETH_DMARxDesc_DE - Dribble bit error: frame contains non int multiple of 8 bits + * ETH_DMARxDesc_CE - CRC error + * ETH_DMARxDesc_MAMPCE - Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error + * + * @return The new state of ETH_DMARxDescFlag (SET or RESET). + */ +FlagStatus ETH_GetDMARxDescFlagStatus(ETH_DMADESCTypeDef *DMARxDesc, uint32_t ETH_DMARxDescFlag) +{ + FlagStatus bitstatus = RESET; + + if((DMARxDesc->Status & ETH_DMARxDescFlag) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_SetDMARxDescOwnBit + * + * @brief Set the specified DMA Rx Desc Own bit. + * + * @param DMARxDesc - Pointer on a Rx desc + * + * @return none + */ +void ETH_SetDMARxDescOwnBit(ETH_DMADESCTypeDef *DMARxDesc) +{ + DMARxDesc->Status |= ETH_DMARxDesc_OWN; +} + +/********************************************************************* + * @fn ETH_GetDMARxDescFrameLength + * + * @brief Returns the specified DMA Rx Desc frame length. + * + * @param DMARxDesc - pointer on a DMA Rx descriptor + * + * @return The Rx descriptor received frame length. + */ +uint32_t ETH_GetDMARxDescFrameLength(ETH_DMADESCTypeDef *DMARxDesc) +{ + return ((DMARxDesc->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT); +} + +/********************************************************************* + * @fn ETH_DMARxDescReceiveITConfig + * + * @brief Enables or disables the specified DMA Rx Desc receive interrupt. + * + * @param DMARxDesc - Pointer on a Rx desc + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ETH_DMARxDescReceiveITConfig(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARxDesc_DIC); + } + else + { + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_DIC; + } +} + +/********************************************************************* + * @fn ETH_DMARxDescEndOfRingCmd + * + * @brief Enables or disables the DMA Rx Desc end of ring. + * + * @param DMARxDesc - pointer on a DMA Rx descriptor. + * NewState - new state of the specified DMA Rx Desc end of ring. + * + * @return none + */ +void ETH_DMARxDescEndOfRingCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RER; + } + else + { + DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARxDesc_RER); + } +} + +/********************************************************************* + * @fn ETH_DMARxDescSecondAddressChainedCmd + * + * @brief Returns the specified ETHERNET DMA Rx Desc buffer size. + * + * @param DMARxDesc - pointer on a DMA Rx descriptor. + * NewState - new state of the specified DMA Rx Desc second address chained. + * + * @return none + */ +void ETH_DMARxDescSecondAddressChainedCmd(ETH_DMADESCTypeDef *DMARxDesc, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMARxDesc->ControlBufferSize |= ETH_DMARxDesc_RCH; + } + else + { + DMARxDesc->ControlBufferSize &= (~(uint32_t)ETH_DMARxDesc_RCH); + } +} + +/********************************************************************* + * @fn ETH_GetDMARxDescBufferSize + * + * @brief Returns the specified ETHERNET DMA Rx Desc buffer size. + * + * @param DMARxDesc - pointer on a DMA Rx descriptor. + * DMARxDesc_Buffer - specifies the DMA Rx Desc buffer. + * ETH_DMARxDesc_Buffer1 - DMA Rx Desc Buffer1 + * ETH_DMARxDesc_Buffer2 - DMA Rx Desc Buffer2 + * + * @return The Receive descriptor frame length. + */ +uint32_t ETH_GetDMARxDescBufferSize(ETH_DMADESCTypeDef *DMARxDesc, uint32_t DMARxDesc_Buffer) +{ + if(DMARxDesc_Buffer != ETH_DMARxDesc_Buffer1) + { + return ((DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS2) >> ETH_DMARXDESC_BUFFER2_SIZESHIFT); + } + else + { + return (DMARxDesc->ControlBufferSize & ETH_DMARxDesc_RBS1); + } +} + +/********************************************************************* + * @fn ETH_SoftwareReset + * + * @brief Resets all MAC subsystem internal registers and logic. + * + * @return none + */ +void ETH_SoftwareReset(void) +{ + ETH->DMABMR |= ETH_DMABMR_SR; +} + +/********************************************************************* + * @fn ETH_GetSoftwareResetStatus + * + * @brief Checks whether the ETHERNET software reset bit is set or not. + * + * @return The new state of DMA Bus Mode register SR bit (SET or RESET). + */ +FlagStatus ETH_GetSoftwareResetStatus(void) +{ + FlagStatus bitstatus = RESET; + if((ETH->DMABMR & ETH_DMABMR_SR) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetlinkStaus + * + * @brief Checks whether the internal 10BASE-T PHY is link or not. + * + * @return Internal 10BASE-T PHY is link or not. + */ +FlagStatus ETH_GetlinkStaus(void) +{ + FlagStatus bitstatus = RESET; + + if((ETH->DMASR & 0x80000000) != (uint32_t)RESET) + { + bitstatus = PHY_10BASE_T_LINKED; + } + else + { + bitstatus = PHY_10BASE_T_NOT_LINKED; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetDMAFlagStatus + * + * @brief Checks whether the specified ETHERNET DMA flag is set or not. + * + * @param ETH_DMA_FLAG - specifies the flag to check. + * ETH_DMA_FLAG_TST - Time-stamp trigger flag + * ETH_DMA_FLAG_PMT - PMT flag + * ETH_DMA_FLAG_MMC - MMC flag + * ETH_DMA_FLAG_DataTransferError - Error bits 0-data buffer, 1-desc. access + * ETH_DMA_FLAG_ReadWriteError - Error bits 0-write trnsf, 1-read transfr + * ETH_DMA_FLAG_AccessError - Error bits 0-Rx DMA, 1-Tx DMA + * ETH_DMA_FLAG_NIS - Normal interrupt summary flag + * ETH_DMA_FLAG_AIS - Abnormal interrupt summary flag + * ETH_DMA_FLAG_ER - Early receive flag + * ETH_DMA_FLAG_FBE - Fatal bus error flag + * ETH_DMA_FLAG_ET - Early transmit flag + * ETH_DMA_FLAG_RWT - Receive watchdog timeout flag + * ETH_DMA_FLAG_RPS - Receive process stopped flag + * ETH_DMA_FLAG_RBU - Receive buffer unavailable flag + * ETH_DMA_FLAG_R - Receive flag + * ETH_DMA_FLAG_TU - Underflow flag + * ETH_DMA_FLAG_RO - Overflow flag + * ETH_DMA_FLAG_TJT - Transmit jabber timeout flag + * ETH_DMA_FLAG_TBU - Transmit buffer unavailable flag + * ETH_DMA_FLAG_TPS - Transmit process stopped flag + * ETH_DMA_FLAG_T - Transmit flag + * + * @return Internal 10BASE-T PHY is link or not. + */ +FlagStatus ETH_GetDMAFlagStatus(uint32_t ETH_DMA_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ETH->DMASR & ETH_DMA_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_DMAClearFlag + * + * @brief Checks whether the specified ETHERNET DMA interrupt has occured or not. + * + * @param ETH_DMA_FLAG - specifies the flag to clear. + * ETH_DMA_FLAG_NIS - Normal interrupt summary flag + * ETH_DMA_FLAG_AIS - Abnormal interrupt summary flag + * ETH_DMA_FLAG_ER - Early receive flag + * ETH_DMA_FLAG_FBE - Fatal bus error flag + * ETH_DMA_FLAG_ETI - Early transmit flag + * ETH_DMA_FLAG_RWT - Receive watchdog timeout flag + * ETH_DMA_FLAG_RPS - Receive process stopped flag + * ETH_DMA_FLAG_RBU - Receive buffer unavailable flag + * ETH_DMA_FLAG_R - Receive flag + * ETH_DMA_FLAG_TU - Transmit Underflow flag + * ETH_DMA_FLAG_RO - Receive Overflow flag + * ETH_DMA_FLAG_TJT - Transmit jabber timeout flag + * ETH_DMA_FLAG_TBU - Transmit buffer unavailable flag + * ETH_DMA_FLAG_TPS - Transmit process stopped flag + * ETH_DMA_FLAG_T - Transmit flag + * + * @return none + */ +void ETH_DMAClearFlag(uint32_t ETH_DMA_FLAG) +{ + ETH->DMASR = (uint32_t)ETH_DMA_FLAG; +} + +/********************************************************************* + * @fn ETH_GetDMAITStatus + * + * @brief Checks whether the specified ETHERNET DMA interrupt has occured or not. + * + * @param ETH_DMA_IT - specifies the interrupt pending bit to clear. + * ETH_DMA_IT_TST - Time-stamp trigger interrupt + * ETH_DMA_IT_PMT - PMT interrupt + * ETH_DMA_IT_MMC - MMC interrupt + * ETH_DMA_IT_NIS - Normal interrupt summary + * ETH_DMA_IT_AIS - Abnormal interrupt summary + * ETH_DMA_IT_ER - Early receive interrupt + * ETH_DMA_IT_FBE - Fatal bus error interrupt + * ETH_DMA_IT_ET - Early transmit interrupt + * ETH_DMA_IT_RWT - Receive watchdog timeout interrupt + * ETH_DMA_IT_RPS - Receive process stopped interrupt + * ETH_DMA_IT_RBU - Receive buffer unavailable interrupt + * ETH_DMA_IT_R - Receive interrupt + * ETH_DMA_IT_TU - Underflow interrupt + * ETH_DMA_IT_RO - Overflow interrupt + * ETH_DMA_IT_TJT - Transmit jabber timeout interrupt + * ETH_DMA_IT_TBU - Transmit buffer unavailable interrupt + * ETH_DMA_IT_TPS - Transmit process stopped interrupt + * ETH_DMA_IT_T - Transmit interrupt + * + * @return The new state of ETH_DMA_IT (SET or RESET). + */ +ITStatus ETH_GetDMAITStatus(uint32_t ETH_DMA_IT) +{ + ITStatus bitstatus = RESET; + + if((ETH->DMASR & ETH_DMA_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_DMAClearITPendingBit + * + * @brief Clears the ETHERNET"s DMA IT pending bit. + * + * @param ETH_DMA_IT - specifies the interrupt pending bit to clear. + * ETH_DMA_IT_NIS - Normal interrupt summary + * ETH_DMA_IT_AIS - Abnormal interrupt summary + * ETH_DMA_IT_ER - Early receive interrupt + * ETH_DMA_IT_FBE - Fatal bus error interrupt + * ETH_DMA_IT_ETI - Early transmit interrupt + * ETH_DMA_IT_RWT - Receive watchdog timeout interrupt + * ETH_DMA_IT_RPS - Receive process stopped interrupt + * ETH_DMA_IT_RBU - Receive buffer unavailable interrupt + * ETH_DMA_IT_R - Receive interrupt + * ETH_DMA_IT_TU - Transmit Underflow interrupt + * ETH_DMA_IT_RO - Receive Overflow interrupt + * ETH_DMA_IT_TJT - Transmit jabber timeout interrupt + * ETH_DMA_IT_TBU - Transmit buffer unavailable interrupt + * ETH_DMA_IT_TPS - Transmit process stopped interrupt + * ETH_DMA_IT_T - Transmit interrupt + * + * @return none + */ +void ETH_DMAClearITPendingBit(uint32_t ETH_DMA_IT) +{ + ETH->DMASR = (uint32_t)ETH_DMA_IT; +} + +/********************************************************************* + * @fn ETH_GetTransmitProcessState + * + * @brief Returns the ETHERNET DMA Transmit Process State. + * + * @return The new ETHERNET DMA Transmit Process State - + * ETH_DMA_TransmitProcess_Stopped - Stopped - Reset or Stop Tx Command issued + * ETH_DMA_TransmitProcess_Fetching - Running - fetching the Tx descriptor + * ETH_DMA_TransmitProcess_Waiting - Running - waiting for status + * ETH_DMA_TransmitProcess_Reading - unning - reading the data from host memory + * ETH_DMA_TransmitProcess_Suspended - Suspended - Tx Desciptor unavailabe + * ETH_DMA_TransmitProcess_Closing - Running - closing Rx descriptor + */ +uint32_t ETH_GetTransmitProcessState(void) +{ + return ((uint32_t)(ETH->DMASR & ETH_DMASR_TS)); +} + +/********************************************************************* + * @fn ETH_GetReceiveProcessState + * + * @brief Returns the ETHERNET DMA Receive Process State. + * + * @return The new ETHERNET DMA Receive Process State: + * ETH_DMA_ReceiveProcess_Stopped - Stopped - Reset or Stop Rx Command issued + * ETH_DMA_ReceiveProcess_Fetching - Running - fetching the Rx descriptor + * ETH_DMA_ReceiveProcess_Waiting - Running - waiting for packet + * ETH_DMA_ReceiveProcess_Suspended - Suspended - Rx Desciptor unavailable + * ETH_DMA_ReceiveProcess_Closing - Running - closing descriptor + * ETH_DMA_ReceiveProcess_Queuing - Running - queuing the recieve frame into host memory + */ +uint32_t ETH_GetReceiveProcessState(void) +{ + return ((uint32_t)(ETH->DMASR & ETH_DMASR_RS)); +} + +/********************************************************************* + * @fn ETH_FlushTransmitFIFO + * + * @brief Clears the ETHERNET transmit FIFO. + * + * @return none + */ +void ETH_FlushTransmitFIFO(void) +{ + ETH->DMAOMR |= ETH_DMAOMR_FTF; +} + +/********************************************************************* + * @fn ETH_GetFlushTransmitFIFOStatus + * + * @brief Checks whether the ETHERNET transmit FIFO bit is cleared or not. + * + * @return The new state of ETHERNET flush transmit FIFO bit (SET or RESET). + */ +FlagStatus ETH_GetFlushTransmitFIFOStatus(void) +{ + FlagStatus bitstatus = RESET; + if((ETH->DMAOMR & ETH_DMAOMR_FTF) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_DMATransmissionCmd + * + * @brief Enables or disables the DMA transmission. + * + * @param NewState - new state of the DMA transmission. + * + * @return none + */ +void ETH_DMATransmissionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->DMAOMR |= ETH_DMAOMR_ST; + } + else + { + ETH->DMAOMR &= ~ETH_DMAOMR_ST; + } +} + +/********************************************************************* + * @fn ETH_DMAReceptionCmd + * + * @brief Enables or disables the DMA reception. + * + * @param NewState - new state of the DMA reception. + * + * @return none + */ +void ETH_DMAReceptionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->DMAOMR |= ETH_DMAOMR_SR; + } + else + { + ETH->DMAOMR &= ~ETH_DMAOMR_SR; + } +} + +/********************************************************************* + * @fn ETH_DMAITConfig + * + * @brief Enables or disables the specified ETHERNET DMA interrupts. + * + * @param ETH_DMA_IT - specifies the ETHERNET DMA interrupt sources to be enabled or disabled. + * ETH_DMA_IT_NIS - Normal interrupt summary + * ETH_DMA_IT_AIS - Abnormal interrupt summary + * ETH_DMA_IT_ER - Early receive interrupt + * ETH_DMA_IT_FBE - Fatal bus error interrupt + * ETH_DMA_IT_ET - Early transmit interrupt + * ETH_DMA_IT_RWT - Receive watchdog timeout interrupt + * ETH_DMA_IT_RPS - Receive process stopped interrupt + * ETH_DMA_IT_RBU - Receive buffer unavailable interrupt + * ETH_DMA_IT_R - Receive interrupt + * ETH_DMA_IT_TU - Underflow interrupt + * ETH_DMA_IT_RO - Overflow interrupt + * ETH_DMA_IT_TJT - Transmit jabber timeout interrupt + * ETH_DMA_IT_TBU - Transmit buffer unavailable interrupt + * ETH_DMA_IT_TPS - Transmit process stopped interrupt + * ETH_DMA_IT_T - Transmit interrupt + * ETH_DMA_Overflow_RxFIFOCounter - Overflow for FIFO Overflow Counter + * ETH_DMA_Overflow_MissedFrameCounter - Overflow for Missed Frame Counter + * NewState - new state of the specified ETHERNET DMA interrupts. + * + * @return new state of the specified ETHERNET DMA interrupts. + */ +void ETH_DMAITConfig(uint32_t ETH_DMA_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->DMAIER |= ETH_DMA_IT; + } + else + { + ETH->DMAIER &= (~(uint32_t)ETH_DMA_IT); + } +} + +/********************************************************************* + * @fn ETH_GetDMAOverflowStatus + * + * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. + * + * @param ETH_DMA_Overflow - specifies the DMA overflow flag to check. + * ETH_DMA_Overflow_RxFIFOCounter - Overflow for FIFO Overflow Counter + * ETH_DMA_Overflow_MissedFrameCounter - Overflow for Missed Frame Counter + * + * @return The new state of ETHERNET DMA overflow Flag (SET or RESET). + */ +FlagStatus ETH_GetDMAOverflowStatus(uint32_t ETH_DMA_Overflow) +{ + FlagStatus bitstatus = RESET; + + if((ETH->DMAMFBOCR & ETH_DMA_Overflow) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetRxOverflowMissedFrameCounter + * + * @brief Get the ETHERNET DMA Rx Overflow Missed Frame Counter value. + * + * @return The value of Rx overflow Missed Frame Counter. + */ +uint32_t ETH_GetRxOverflowMissedFrameCounter(void) +{ + return ((uint32_t)((ETH->DMAMFBOCR & ETH_DMAMFBOCR_MFA) >> ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT)); +} + +/********************************************************************* + * @fn ETH_GetBufferUnavailableMissedFrameCounter + * + * @brief Get the ETHERNET DMA Buffer Unavailable Missed Frame Counter value. + * + * @return The value of Buffer unavailable Missed Frame Counter. + */ +uint32_t ETH_GetBufferUnavailableMissedFrameCounter(void) +{ + return ((uint32_t)(ETH->DMAMFBOCR) & ETH_DMAMFBOCR_MFC); +} + +/********************************************************************* + * @fn ETH_GetCurrentTxDescStartAddress + * + * @brief Get the ETHERNET DMA DMACHTDR register value. + * + * @return The value of the current Tx desc start address. + */ +uint32_t ETH_GetCurrentTxDescStartAddress(void) +{ + return ((uint32_t)(ETH->DMACHTDR)); +} + +/********************************************************************* + * @fn ETH_GetCurrentRxDescStartAddress + * + * @brief Get the ETHERNET DMA DMACHRDR register value. + * + * @return The value of the current Rx desc start address. + */ +uint32_t ETH_GetCurrentRxDescStartAddress(void) +{ + return ((uint32_t)(ETH->DMACHRDR)); +} + +/********************************************************************* + * @fn ETH_GetCurrentTxBufferAddress + * + * @brief Get the ETHERNET DMA DMACHTBAR register value. + * + * @return The value of the current Tx buffer address. + */ +uint32_t ETH_GetCurrentTxBufferAddress(void) +{ + return (DMATxDescToSet->Buffer1Addr); +} + +/********************************************************************* + * @fn ETH_GetCurrentRxBufferAddress + * + * @brief Get the ETHERNET DMA DMACHRBAR register value. + * + * @return The value of the current Rx buffer address. + */ +uint32_t ETH_GetCurrentRxBufferAddress(void) +{ + return ((uint32_t)(ETH->DMACHRBAR)); +} + +/********************************************************************* + * @fn ETH_ResumeDMATransmission + * + * @brief Resumes the DMA Transmission by writing to the DmaTxPollDemand register + * + * @return none + */ +void ETH_ResumeDMATransmission(void) +{ + ETH->DMATPDR = 0; +} + +/********************************************************************* + * @fn ETH_ResumeDMAReception + * + * @brief Resumes the DMA Transmission by writing to the DmaRxPollDemand register. + * + * @return none + */ +void ETH_ResumeDMAReception(void) +{ + ETH->DMARPDR = 0; +} + +/********************************************************************* + * @fn ETH_ResetWakeUpFrameFilterRegisterPointer + * + * @brief Reset Wakeup frame filter register pointer. + * + * @return none + */ +void ETH_ResetWakeUpFrameFilterRegisterPointer(void) +{ + ETH->MACPMTCSR |= ETH_MACPMTCSR_WFFRPR; +} + +/********************************************************************* + * @fn ETH_SetWakeUpFrameFilterRegister + * + * @brief Populates the remote wakeup frame registers. + * + * @param Buffer - Pointer on remote WakeUp Frame Filter Register buffer data (8 words). + * + * @return none + */ +void ETH_SetWakeUpFrameFilterRegister(uint32_t *Buffer) +{ + uint32_t i = 0; + + for(i = 0; i < ETH_WAKEUP_REGISTER_LENGTH; i++) + { + ETH->MACRWUFFR = Buffer[i]; + } +} + +/********************************************************************* + * @fn ETH_GlobalUnicastWakeUpCmd + * + * @brief Enables or disables any unicast packet filtered by the MAC address. + * + * @param NewState - new state of the MAC Global Unicast Wake-Up. + * + * @return none + */ +void ETH_GlobalUnicastWakeUpCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACPMTCSR |= ETH_MACPMTCSR_GU; + } + else + { + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_GU; + } +} + +/********************************************************************* + * @fn ETH_GetPMTFlagStatus + * + * @brief Checks whether the specified ETHERNET PMT flag is set or not. + * + * @param ETH_PMT_FLAG - specifies the flag to check. + * + * @return The new state of ETHERNET PMT Flag (SET or RESET). + */ +FlagStatus ETH_GetPMTFlagStatus(uint32_t ETH_PMT_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ETH->MACPMTCSR & ETH_PMT_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_WakeUpFrameDetectionCmd + * + * @brief Enables or disables the MAC Wake-Up Frame Detection. + * + * @param NewState - new state of the MAC Wake-Up Frame Detection. + * + * @return none + */ +void ETH_WakeUpFrameDetectionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACPMTCSR |= ETH_MACPMTCSR_WFE; + } + else + { + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_WFE; + } +} + +/********************************************************************* + * @fn ETH_MagicPacketDetectionCmd + * + * @brief Enables or disables the MAC Magic Packet Detection. + * + * @param NewState - new state of the MAC Magic Packet Detection. + * + * @return none + */ +void ETH_MagicPacketDetectionCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACPMTCSR |= ETH_MACPMTCSR_MPE; + } + else + { + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_MPE; + } +} + +/********************************************************************* + * @fn ETH_PowerDownCmd + * + * @brief Enables or disables the MAC Power Down. + * + * @param NewState - new state of the MAC Power Down. + * + * @return none + */ +void ETH_PowerDownCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MACPMTCSR |= ETH_MACPMTCSR_PD; + } + else + { + ETH->MACPMTCSR &= ~ETH_MACPMTCSR_PD; + } +} + +/********************************************************************* + * @fn ETH_MMCCounterFreezeCmd + * + * @brief Enables or disables the MMC Counter Freeze. + * + * @param NewState - new state of the MMC Counter Freeze. + * + * @return none + */ +void ETH_MMCCounterFreezeCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MMCCR |= ETH_MMCCR_MCF; + } + else + { + ETH->MMCCR &= ~ETH_MMCCR_MCF; + } +} + +/********************************************************************* + * @fn ETH_MMCResetOnReadCmd + * + * @brief Enables or disables the MMC Reset On Read. + * + * @param NewState - new state of the MMC Reset On Read. + * + * @return none + */ +void ETH_MMCResetOnReadCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MMCCR |= ETH_MMCCR_ROR; + } + else + { + ETH->MMCCR &= ~ETH_MMCCR_ROR; + } +} + +/********************************************************************* + * @fn ETH_MMCCounterRolloverCmd + * + * @brief Enables or disables the MMC Counter Stop Rollover. + * + * @param NewState - new state of the MMC Counter Stop Rollover. + * + * @return none + */ +void ETH_MMCCounterRolloverCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->MMCCR &= ~ETH_MMCCR_CSR; + } + else + { + ETH->MMCCR |= ETH_MMCCR_CSR; + } +} + +/********************************************************************* + * @fn ETH_MMCCountersReset + * + * @brief Resets the MMC Counters. + * + * @return none + */ +void ETH_MMCCountersReset(void) +{ + ETH->MMCCR |= ETH_MMCCR_CR; +} + +/********************************************************************* + * @fn ETH_MMCITConfig + * + * @brief Enables or disables the specified ETHERNET MMC interrupts. + * + * @param ETH_MMC_IT - specifies the ETHERNET MMC interrupt. + * ETH_MMC_IT_TGF - When Tx good frame counter reaches half the maximum value. + * ETH_MMC_IT_TGFMSC - When Tx good multi col counter reaches half the maximum value. + * ETH_MMC_IT_TGFSC - When Tx good single col counter reaches half the maximum value. + * ETH_MMC_IT_RGUF - When Rx good unicast frames counter reaches half the maximum value. + * ETH_MMC_IT_RFAE - When Rx alignment error counter reaches half the maximum value. + * ETH_MMC_IT_RFCE - When Rx crc error counter reaches half the maximum value. + * NewState - new state of the specified ETHERNET MMC interrupts. + * + * @return none + */ +void ETH_MMCITConfig(uint32_t ETH_MMC_IT, FunctionalState NewState) +{ + if((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) + { + ETH_MMC_IT &= 0xEFFFFFFF; + + if(NewState != DISABLE) + { + ETH->MMCRIMR &= (~(uint32_t)ETH_MMC_IT); + } + else + { + ETH->MMCRIMR |= ETH_MMC_IT; + } + } + else + { + if(NewState != DISABLE) + { + ETH->MMCTIMR &= (~(uint32_t)ETH_MMC_IT); + } + else + { + ETH->MMCTIMR |= ETH_MMC_IT; + } + } +} + +/********************************************************************* + * @fn ETH_GetMMCITStatus + * + * @brief Checks whether the specified ETHERNET MMC IT is set or not. + * + * @param ETH_MMC_IT - specifies the ETHERNET MMC interrupt. + * ETH_MMC_IT_TxFCGC - When Tx good frame counter reaches half the maximum value. + * ETH_MMC_IT_TxMCGC - When Tx good multi col counter reaches half the maximum value. + * ETH_MMC_IT_TxSCGC - When Tx good single col counter reaches half the maximum value . + * ETH_MMC_IT_RxUGFC - When Rx good unicast frames counter reaches half the maximum value. + * ETH_MMC_IT_RxAEC - When Rx alignment error counter reaches half the maximum value. + * ETH_MMC_IT_RxCEC - When Rx crc error counter reaches half the maximum value. + * + * @return The value of ETHERNET MMC IT (SET or RESET). + */ +ITStatus ETH_GetMMCITStatus(uint32_t ETH_MMC_IT) +{ + ITStatus bitstatus = RESET; + + if((ETH_MMC_IT & (uint32_t)0x10000000) != (uint32_t)RESET) + { + if((((ETH->MMCRIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((((ETH->MMCTIR & ETH_MMC_IT) != (uint32_t)RESET)) && ((ETH->MMCRIMR & ETH_MMC_IT) != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + + return bitstatus; +} + +/********************************************************************* + * @fn ETH_GetMMCRegister + * + * @brief Get the specified ETHERNET MMC register value. + * + * @param ETH_MMCReg - specifies the ETHERNET MMC register. + * ETH_MMCCR - MMC CR register + * ETH_MMCRIR - MMC RIR register + * ETH_MMCTIR - MMC TIR register + * ETH_MMCRIMR - MMC RIMR register + * ETH_MMCTIMR - MMC TIMR register + * ETH_MMCTGFSCCR - MMC TGFSCCR register + * ETH_MMCTGFMSCCR - MMC TGFMSCCR register + * ETH_MMCTGFCR - MMC TGFCR register + * ETH_MMCRFCECR - MMC RFCECR register + * ETH_MMCRFAECR - MMC RFAECR register + * ETH_MMCRGUFCR - MMC RGUFCRregister + * + * @return The value of ETHERNET MMC Register value. + */ +uint32_t ETH_GetMMCRegister(uint32_t ETH_MMCReg) +{ + return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_MMCReg)); +} + +/********************************************************************* + * @fn ETH_EnablePTPTimeStampAddend + * + * @brief Updated the PTP block for fine correction with the Time Stamp Addend register value. + * + * @return none + */ +void ETH_EnablePTPTimeStampAddend(void) +{ + ETH->PTPTSCR |= ETH_PTPTSCR_TSARU; +} + +/********************************************************************* + * @fn ETH_EnablePTPTimeStampInterruptTrigger + * + * @brief Enable the PTP Time Stamp interrupt trigger + * + * @return none + */ +void ETH_EnablePTPTimeStampInterruptTrigger(void) +{ + ETH->PTPTSCR |= ETH_PTPTSCR_TSITE; +} + +/********************************************************************* + * @fn ETH_EnablePTPTimeStampUpdate + * + * @brief Updated the PTP system time with the Time Stamp Update register value. + * + * @return none + */ +void ETH_EnablePTPTimeStampUpdate(void) +{ + ETH->PTPTSCR |= ETH_PTPTSCR_TSSTU; +} + +/********************************************************************* + * @fn ETH_InitializePTPTimeStamp + * + * @brief Initialize the PTP Time Stamp. + * + * @return none + */ +void ETH_InitializePTPTimeStamp(void) +{ + ETH->PTPTSCR |= ETH_PTPTSCR_TSSTI; +} + +/********************************************************************* + * @fn ETH_PTPUpdateMethodConfig + * + * @brief Selects the PTP Update method. + * + * @param UpdateMethod - the PTP Update method. + * + * @return none + */ +void ETH_PTPUpdateMethodConfig(uint32_t UpdateMethod) +{ + if(UpdateMethod != ETH_PTP_CoarseUpdate) + { + ETH->PTPTSCR |= ETH_PTPTSCR_TSFCU; + } + else + { + ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSFCU); + } +} + +/********************************************************************* + * @fn ETH_PTPTimeStampCmd + * + * @brief Enables or disables the PTP time stamp for transmit and receive frames. + * + * @param NewState - new state of the PTP time stamp for transmit and receive frames. + * + * @return none + */ +void ETH_PTPTimeStampCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ETH->PTPTSCR |= ETH_PTPTSCR_TSE; + } + else + { + ETH->PTPTSCR &= (~(uint32_t)ETH_PTPTSCR_TSE); + } +} + +/********************************************************************* + * @fn ETH_GetPTPFlagStatus + * + * @brief Checks whether the specified ETHERNET PTP flag is set or not. + * + * @param The new state of ETHERNET PTP Flag (SET or RESET). + * + * @return none + */ +FlagStatus ETH_GetPTPFlagStatus(uint32_t ETH_PTP_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ETH->PTPTSCR & ETH_PTP_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn ETH_SetPTPSubSecondIncrement + * + * @brief Sets the system time Sub-Second Increment value. + * + * @param SubSecondValue - specifies the PTP Sub-Second Increment Register value. + * + * @return none + */ +void ETH_SetPTPSubSecondIncrement(uint32_t SubSecondValue) +{ + ETH->PTPSSIR = SubSecondValue; +} + +/********************************************************************* + * @fn ETH_SetPTPTimeStampUpdate + * + * @brief Sets the Time Stamp update sign and values. + * + * @param Sign - specifies the PTP Time update value sign. + * SecondValue - specifies the PTP Time update second value. + * SubSecondValue - specifies the PTP Time update sub-second value. + * + * @return none + */ +void ETH_SetPTPTimeStampUpdate(uint32_t Sign, uint32_t SecondValue, uint32_t SubSecondValue) +{ + ETH->PTPTSHUR = SecondValue; + ETH->PTPTSLUR = Sign | SubSecondValue; +} + +/********************************************************************* + * @fn ETH_SetPTPTimeStampAddend + * + * @brief Sets the Time Stamp Addend value. + * + * @param Value - specifies the PTP Time Stamp Addend Register value. + * + * @return none + */ +void ETH_SetPTPTimeStampAddend(uint32_t Value) +{ + /* Set the PTP Time Stamp Addend Register */ + ETH->PTPTSAR = Value; +} + +/********************************************************************* + * @fn ETH_SetPTPTargetTime + * + * @brief Sets the Target Time registers values. + * + * @param HighValue - specifies the PTP Target Time High Register value. + * LowValue - specifies the PTP Target Time Low Register value. + * + * @return none + */ +void ETH_SetPTPTargetTime(uint32_t HighValue, uint32_t LowValue) +{ + ETH->PTPTTHR = HighValue; + ETH->PTPTTLR = LowValue; +} + +/********************************************************************* + * @fn ETH_GetPTPRegister + * + * @brief Get the specified ETHERNET PTP register value. + * + * @param ETH_PTPReg - specifies the ETHERNET PTP register. + * ETH_PTPTSCR - Sub-Second Increment Register + * ETH_PTPSSIR - Sub-Second Increment Register + * ETH_PTPTSHR - Time Stamp High Register + * ETH_PTPTSLR - Time Stamp Low Register + * ETH_PTPTSHUR - Time Stamp High Update Register + * ETH_PTPTSLUR - Time Stamp Low Update Register + * ETH_PTPTSAR - Time Stamp Addend Register + * ETH_PTPTTHR - Target Time High Register + * ETH_PTPTTLR - Target Time Low Register + * + * @return The value of ETHERNET PTP Register value. + */ +uint32_t ETH_GetPTPRegister(uint32_t ETH_PTPReg) +{ + return (*(__IO uint32_t *)(ETH_MAC_BASE + ETH_PTPReg)); +} + +/********************************************************************* + * @fn ETH_DMAPTPTxDescChainInit + * + * @brief Initializes the DMA Tx descriptors in chain mode with PTP. + * + * @param DMATxDescTab - Pointer on the first Tx desc list. + * DMAPTPTxDescTab - Pointer on the first PTP Tx desc list. + * TxBuff - Pointer on the first TxBuffer list. + * TxBuffCount - Number of the used Tx desc in the list. + * + * @return none. + */ +void ETH_DMAPTPTxDescChainInit(ETH_DMADESCTypeDef *DMATxDescTab, ETH_DMADESCTypeDef *DMAPTPTxDescTab, + uint8_t *TxBuff, uint32_t TxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMATxDesc; + + DMATxDescToSet = DMATxDescTab; + DMAPTPTxDescToSet = DMAPTPTxDescTab; + + for(i = 0; i < TxBuffCount; i++) + { + DMATxDesc = DMATxDescTab + i; + DMATxDesc->Status = ETH_DMATxDesc_TCH | ETH_DMATxDesc_TTSE; + DMATxDesc->Buffer1Addr = (uint32_t)(&TxBuff[i * ETH_MAX_PACKET_SIZE]); + + if(i < (TxBuffCount - 1)) + { + DMATxDesc->Buffer2NextDescAddr = (uint32_t)(DMATxDescTab + i + 1); + } + else + { + DMATxDesc->Buffer2NextDescAddr = (uint32_t)DMATxDescTab; + } + + (&DMAPTPTxDescTab[i])->Buffer1Addr = DMATxDesc->Buffer1Addr; + (&DMAPTPTxDescTab[i])->Buffer2NextDescAddr = DMATxDesc->Buffer2NextDescAddr; + } + + (&DMAPTPTxDescTab[i - 1])->Status = (uint32_t)DMAPTPTxDescTab; + + ETH->DMATDLAR = (uint32_t)DMATxDescTab; +} + +/********************************************************************* + * @fn ETH_DMAPTPRxDescChainInit + * + * @brief Initializes the DMA Rx descriptors in chain mode. + * + * @param DMARxDescTab - Pointer on the first Rx desc list. + * DMAPTPRxDescTab - Pointer on the first PTP Rx desc list. + * RxBuff - Pointer on the first RxBuffer list. + * RxBuffCount - Number of the used Rx desc in the list. + * + * @return none. + */ +void ETH_DMAPTPRxDescChainInit(ETH_DMADESCTypeDef *DMARxDescTab, ETH_DMADESCTypeDef *DMAPTPRxDescTab, + uint8_t *RxBuff, uint32_t RxBuffCount) +{ + uint32_t i = 0; + ETH_DMADESCTypeDef *DMARxDesc; + + DMARxDescToGet = DMARxDescTab; + DMAPTPRxDescToGet = DMAPTPRxDescTab; + + for(i = 0; i < RxBuffCount; i++) + { + DMARxDesc = DMARxDescTab + i; + DMARxDesc->Status = ETH_DMARxDesc_OWN; + DMARxDesc->ControlBufferSize = ETH_DMARxDesc_RCH | (uint32_t)ETH_MAX_PACKET_SIZE; + DMARxDesc->Buffer1Addr = (uint32_t)(&RxBuff[i * ETH_MAX_PACKET_SIZE]); + + if(i < (RxBuffCount - 1)) + { + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab + i + 1); + } + else + { + DMARxDesc->Buffer2NextDescAddr = (uint32_t)(DMARxDescTab); + } + + (&DMAPTPRxDescTab[i])->Buffer1Addr = DMARxDesc->Buffer1Addr; + (&DMAPTPRxDescTab[i])->Buffer2NextDescAddr = DMARxDesc->Buffer2NextDescAddr; + } + + (&DMAPTPRxDescTab[i - 1])->Status = (uint32_t)DMAPTPRxDescTab; + ETH->DMARDLAR = (uint32_t)DMARxDescTab; +} + +/********************************************************************* + * @fn ETH_HandlePTPTxPkt + * + * @brief Transmits a packet, from application buffer, pointed by ppkt with Time Stamp values. + * + * @param ppkt - pointer to application packet buffer to transmit. + * FrameLength - Tx Packet size. + * PTPTxTab - Pointer on the first PTP Tx table to store Time stamp values. + * + * @return none. + */ +uint32_t ETH_HandlePTPTxPkt(uint8_t *ppkt, uint16_t FrameLength, uint32_t *PTPTxTab) +{ + uint32_t offset = 0, timeout = 0; + + if((DMATxDescToSet->Status & ETH_DMATxDesc_OWN) != (uint32_t)RESET) + { + return ETH_ERROR; + } + + for(offset = 0; offset < FrameLength; offset++) + { + (*(__IO uint8_t *)((DMAPTPTxDescToSet->Buffer1Addr) + offset)) = (*(ppkt + offset)); + } + + DMATxDescToSet->ControlBufferSize = (FrameLength & (uint32_t)0x1FFF); + DMATxDescToSet->Status |= ETH_DMATxDesc_LS | ETH_DMATxDesc_FS; + DMATxDescToSet->Status |= ETH_DMATxDesc_OWN; + + if((ETH->DMASR & ETH_DMASR_TBUS) != (uint32_t)RESET) + { + ETH->DMASR = ETH_DMASR_TBUS; + ETH->DMATPDR = 0; + } + + do + { + timeout++; + } while(!(DMATxDescToSet->Status & ETH_DMATxDesc_TTSS) && (timeout < 0xFFFF)); + + if(timeout == PHY_READ_TO) + { + return ETH_ERROR; + } + + DMATxDescToSet->Status &= ~ETH_DMATxDesc_TTSS; + *PTPTxTab++ = DMATxDescToSet->Buffer1Addr; + *PTPTxTab = DMATxDescToSet->Buffer2NextDescAddr; + + if((DMATxDescToSet->Status & ETH_DMATxDesc_TCH) != (uint32_t)RESET) + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)(DMAPTPTxDescToSet->Buffer2NextDescAddr); + if(DMAPTPTxDescToSet->Status != 0) + { + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef *)(DMAPTPTxDescToSet->Status); + } + else + { + DMAPTPTxDescToSet++; + } + } + else + { + if((DMATxDescToSet->Status & ETH_DMATxDesc_TER) != (uint32_t)RESET) + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)(ETH->DMATDLAR); + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef *)(ETH->DMATDLAR); + } + else + { + DMATxDescToSet = (ETH_DMADESCTypeDef *)((uint32_t)DMATxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + DMAPTPTxDescToSet = (ETH_DMADESCTypeDef *)((uint32_t)DMAPTPTxDescToSet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + return ETH_SUCCESS; +} + +/********************************************************************* + * @fn ETH_HandlePTPRxPkt + * + * @brief Receives a packet and copies it to memory pointed by ppkt with Time Stamp values. + * + * @param ppkt - pointer to application packet receive buffer. + * PTPRxTab - Pointer on the first PTP Rx table to store Time stamp values. + * + * @return ETH_ERROR - if there is error in reception. + * framelength - received packet size if packet reception is correct. + */ +uint32_t ETH_HandlePTPRxPkt(uint8_t *ppkt, uint32_t *PTPRxTab) +{ + uint32_t offset = 0, framelength = 0; + + if((DMARxDescToGet->Status & ETH_DMARxDesc_OWN) != (uint32_t)RESET) + { + return ETH_ERROR; + } + if(((DMARxDescToGet->Status & ETH_DMARxDesc_ES) == (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_LS) != (uint32_t)RESET) && + ((DMARxDescToGet->Status & ETH_DMARxDesc_FS) != (uint32_t)RESET)) + { + framelength = ((DMARxDescToGet->Status & ETH_DMARxDesc_FL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4; + + for(offset = 0; offset < framelength; offset++) + { + (*(ppkt + offset)) = (*(__IO uint8_t *)((DMAPTPRxDescToGet->Buffer1Addr) + offset)); + } + } + else + { + framelength = ETH_ERROR; + } + + if((ETH->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) + { + ETH->DMASR = ETH_DMASR_RBUS; + ETH->DMARPDR = 0; + } + + *PTPRxTab++ = DMARxDescToGet->Buffer1Addr; + *PTPRxTab = DMARxDescToGet->Buffer2NextDescAddr; + DMARxDescToGet->Status |= ETH_DMARxDesc_OWN; + + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RCH) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(DMAPTPRxDescToGet->Buffer2NextDescAddr); + if(DMAPTPRxDescToGet->Status != 0) + { + DMAPTPRxDescToGet = (ETH_DMADESCTypeDef *)(DMAPTPRxDescToGet->Status); + } + else + { + DMAPTPRxDescToGet++; + } + } + else + { + if((DMARxDescToGet->ControlBufferSize & ETH_DMARxDesc_RER) != (uint32_t)RESET) + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)(ETH->DMARDLAR); + } + else + { + DMARxDescToGet = (ETH_DMADESCTypeDef *)((uint32_t)DMARxDescToGet + 0x10 + ((ETH->DMABMR & ETH_DMABMR_DSL) >> 2)); + } + } + + return (framelength); +} + +/********************************************************************* + * @fn RGMII_TXC_Delay + * + * @brief Delay time. + * + * @return none + */ +void RGMII_TXC_Delay(uint8_t clock_polarity, uint8_t delay_time) +{ + if(clock_polarity) + { + ETH->MACCR |= (uint32_t)(1 << 1); + } + else + { + ETH->MACCR &= ~(uint32_t)(1 << 1); + } + if(delay_time <= 7) + { + ETH->MACCR &= ~(uint32_t)(7 << 29); + ETH->MACCR |= (uint32_t)(delay_time << 29); + } +} diff --git a/Peripheral/src/ch32v30x_exti.c b/Peripheral/src/ch32v30x_exti.c new file mode 100644 index 0000000..7f10cbf --- /dev/null +++ b/Peripheral/src/ch32v30x_exti.c @@ -0,0 +1,182 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_exti.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the EXTI firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_exti.h" + +/* No interrupt selected */ +#define EXTI_LINENONE ((uint32_t)0x00000) + +/********************************************************************* + * @fn EXTI_DeInit + * + * @brief Deinitializes the EXTI peripheral registers to their default + * reset values. + * + * @return none. + */ +void EXTI_DeInit(void) +{ + EXTI->INTENR = 0x00000000; + EXTI->EVENR = 0x00000000; + EXTI->RTENR = 0x00000000; + EXTI->FTENR = 0x00000000; + EXTI->INTFR = 0x000FFFFF; +} + +/********************************************************************* + * @fn EXTI_Init + * + * @brief Initializes the EXTI peripheral according to the specified + * parameters in the EXTI_InitStruct. + * + * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct) +{ + uint32_t tmp = 0; + + tmp = (uint32_t)EXTI_BASE; + if(EXTI_InitStruct->EXTI_LineCmd != DISABLE) + { + EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line; + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line; + EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line; + if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling) + { + EXTI->RTENR |= EXTI_InitStruct->EXTI_Line; + EXTI->FTENR |= EXTI_InitStruct->EXTI_Line; + } + else + { + tmp = (uint32_t)EXTI_BASE; + tmp += EXTI_InitStruct->EXTI_Trigger; + *(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line; + } + } + else + { + tmp += EXTI_InitStruct->EXTI_Mode; + *(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line; + } +} + +/********************************************************************* + * @fn EXTI_StructInit + * + * @brief Fills each EXTI_InitStruct member with its reset value. + * + * @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure + * + * @return none. + */ +void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/********************************************************************* + * @fn EXTI_GenerateSWInterrupt + * + * @brief Generates a Software interrupt. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none. + */ +void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line) +{ + EXTI->SWIEVR |= EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetFlagStatus + * + * @brief Checks whether the specified EXTI line flag is set or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line) +{ + FlagStatus bitstatus = RESET; + if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearFlag + * + * @brief Clears the EXTI's line pending flags. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return None + */ +void EXTI_ClearFlag(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} + +/********************************************************************* + * @fn EXTI_GetITStatus + * + * @brief Checks whether the specified EXTI line is asserted or not. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return The new state of EXTI_Line (SET or RESET). + */ +ITStatus EXTI_GetITStatus(uint32_t EXTI_Line) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = EXTI->INTENR & EXTI_Line; + if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn EXTI_ClearITPendingBit + * + * @brief Clears the EXTI's line pending bits. + * + * @param EXTI_Line - specifies the EXTI lines to be enabled or disabled. + * + * @return none + */ +void EXTI_ClearITPendingBit(uint32_t EXTI_Line) +{ + EXTI->INTFR = EXTI_Line; +} diff --git a/Peripheral/src/ch32v30x_flash.c b/Peripheral/src/ch32v30x_flash.c new file mode 100644 index 0000000..cf09230 --- /dev/null +++ b/Peripheral/src/ch32v30x_flash.c @@ -0,0 +1,1226 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_flash.c +* Author : WCH +* Version : V1.0.1 +* Date : 2025/04/14 +* Description : This file provides all the FLASH firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_flash.h" + +/* Flash Control Register bits */ +#define CR_PG_Set ((uint32_t)0x00000001) +#define CR_PG_Reset ((uint32_t)0xFFFFFFFE) +#define CR_PER_Set ((uint32_t)0x00000002) +#define CR_PER_Reset ((uint32_t)0xFFFFFFFD) +#define CR_MER_Set ((uint32_t)0x00000004) +#define CR_MER_Reset ((uint32_t)0xFFFFFFFB) +#define CR_OPTPG_Set ((uint32_t)0x00000010) +#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF) +#define CR_OPTER_Set ((uint32_t)0x00000020) +#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF) +#define CR_STRT_Set ((uint32_t)0x00000040) +#define CR_LOCK_Set ((uint32_t)0x00000080) +#define CR_FLOCK_Set ((uint32_t)0x00008000) +#define CR_PAGE_PG ((uint32_t)0x00010000) +#define CR_PAGE_ER ((uint32_t)0x00020000) +#define CR_BER32 ((uint32_t)0x00040000) +#define CR_PG_STRT ((uint32_t)0x00200000) + +/* FLASH Status Register bits */ +#define SR_BSY ((uint32_t)0x00000001) +#define SR_WR_BSY ((uint32_t)0x00000002) +#define SR_WRPRTERR ((uint32_t)0x00000010) +#define SR_EOP ((uint32_t)0x00000020) + +/* FLASH Mask */ +#define RDPRT_Mask ((uint32_t)0x00000002) +#define WRP0_Mask ((uint32_t)0x000000FF) +#define WRP1_Mask ((uint32_t)0x0000FF00) +#define WRP2_Mask ((uint32_t)0x00FF0000) +#define WRP3_Mask ((uint32_t)0xFF000000) +#define OB_USER_BFB2 ((uint16_t)0x0008) + +/* FLASH Keys */ +#define RDP_Key ((uint16_t)0x00A5) +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/* FLASH BANK address */ +#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF) + +/* Delay definition */ +#define EraseTimeout ((uint32_t)0x00130000) +#define ProgramTimeout ((uint32_t)0x00005000) + +/* Flash Program Valid Address */ +#define ValidAddrStart (FLASH_BASE) +#define ValidAddrEnd (FLASH_BASE + 0x78000) + +/* FLASH Size */ +#define Size_256B 0x100 +#define Size_4KB 0x1000 +#define Size_32KB 0x8000 + +#define FLASH_EraseAll_Delay(t) ({for(uint32_t i = 0; iKEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/********************************************************************* + * @fn FLASH_UnlockBank1 + * + * @brief Unlocks the FLASH Bank1 Program Erase Controller. + * equivalent to FLASH_Unlock function. + * + * @return none + */ +void FLASH_UnlockBank1(void) +{ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; +} + +/********************************************************************* + * @fn FLASH_Lock + * + * @brief Locks the FLASH Program Erase Controller. + * + * @return none + */ +void FLASH_Lock(void) +{ + FLASH->CTLR |= CR_LOCK_Set; +} + +/********************************************************************* + * @fn FLASH_LockBank1 + * + * @brief Locks the FLASH Bank1 Program Erase Controller. + * + * @return none + */ +void FLASH_LockBank1(void) +{ + FLASH->CTLR |= CR_LOCK_Set; +} + +/********************************************************************* + * @fn FLASH_ErasePage + * + * @brief Erases a specified FLASH page(page size 4KB). + * + * @param Page_Address - The page address to be erased. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ErasePage(uint32_t Page_Address) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_PER_Set; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_PER_Reset; + } + + return status; +} + +/********************************************************************* + * @fn FLASH_EraseAllPages + * + * @brief Erases all FLASH pages. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllPages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_MER_Set; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastOperation(EraseTimeout); + + FLASH->CTLR &= CR_MER_Reset; + } + FLASH_EraseAll_Delay(300000); + return status; +} + +/********************************************************************* + * @fn FLASH_EraseAllBank1Pages + * + * @brief Erases all Bank1 FLASH pages. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseAllBank1Pages(void) +{ + FLASH_Status status = FLASH_COMPLETE; + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_MER_Set; + FLASH->CTLR |= CR_STRT_Set; + + status = FLASH_WaitForLastBank1Operation(EraseTimeout); + + FLASH->CTLR &= CR_MER_Reset; + } + FLASH_EraseAll_Delay(300000); + return status; +} + +/********************************************************************* + * @fn FLASH_EraseOptionBytes + * + * @brief Erases the FLASH option bytes. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EraseOptionBytes(void) +{ + uint16_t rdptmp = RDP_Key; + uint32_t Address = 0x1FFFF800; + __IO uint8_t i; + + FLASH_Status status = FLASH_COMPLETE; + if(FLASH_GetReadOutProtectionStatus() != RESET) + { + rdptmp = 0x00; + } + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + status = FLASH_WaitForLastOperation(EraseTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR &= CR_OPTER_Reset; + FLASH->CTLR |= CR_OPTPG_Set; + OB->RDPR = (uint16_t)rdptmp; + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + else + { + if(status != FLASH_TIMEOUT) + { + FLASH->CTLR &= CR_OPTPG_Reset; + } + } + + /* Write 0xFF */ + FLASH->CTLR |= CR_OPTPG_Set; + + for(i = 0; i < 8; i++) + { + *(uint16_t *)(Address + 2 * i) = 0x00FF; + while(FLASH->STATR & SR_BSY) + ; + } + + FLASH->CTLR &= ~CR_OPTPG_Set; + } + return status; +} + +/********************************************************************* + * @fn FLASH_ProgramWord + * + * @brief Programs a word at a specified address. + * + * @param Address - specifies the address to be programmed. + * Data - specifies the data to be programmed. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + __IO uint32_t tmp = 0; + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_PG_Set; + + *(__IO uint16_t *)Address = (uint16_t)Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + tmp = Address + 2; + *(__IO uint16_t *)tmp = Data >> 16; + status = FLASH_WaitForLastOperation(ProgramTimeout); + FLASH->CTLR &= CR_PG_Reset; + } + else + { + FLASH->CTLR &= CR_PG_Reset; + } + } + + return status; +} + +/********************************************************************* + * @fn FLASH_ProgramHalfWord + * + * @brief Programs a half word at a specified address. + * + * @param Address - specifies the address to be programmed. + * Data - specifies the data to be programmed. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->CTLR |= CR_PG_Set; + *(__IO uint16_t *)Address = Data; + status = FLASH_WaitForLastOperation(ProgramTimeout); + FLASH->CTLR &= CR_PG_Reset; + } + + return status; +} + +/********************************************************************* + * @fn FLASH_ProgramOptionByteData + * + * @brief Programs a half word at a specified Option Byte Data address. + * + * @param Address - specifies the address to be programmed. + * Data - specifies the data to be programmed. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data) +{ + FLASH_Status status = FLASH_COMPLETE; + uint32_t Addr = 0x1FFFF800; + __IO uint8_t i; + uint16_t pbuf[8]; + + status = FLASH_WaitForLastOperation(ProgramTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + /* Read optionbytes */ + for(i = 0; i < 8; i++) + { + pbuf[i] = *(uint16_t *)(Addr + 2 * i); + } + + /* Erase optionbytes */ + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_OPTER_Set; + + /* Write optionbytes */ + pbuf[((Address - 0x1FFFF800) / 2)] = ((((uint16_t) ~(Data)) << 8) | ((uint16_t)Data)); + + FLASH->CTLR |= CR_OPTPG_Set; + + for(i = 0; i < 8; i++) + { + *(uint16_t *)(Addr + 2 * i) = pbuf[i]; + while(FLASH->STATR & SR_BSY) + ; + } + + FLASH->CTLR &= ~CR_OPTPG_Set; + } + + return status; +} + +/********************************************************************* + * @fn FLASH_EnableWriteProtection + * + * @brief Write protects the desired sectors + * + * @param FLASH_Sectors - specifies the address of the pages to be write protected. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors) +{ + uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF; + FLASH_Status status = FLASH_COMPLETE; + uint32_t Addr = 0x1FFFF800; + __IO uint8_t i; + uint16_t pbuf[8]; + + FLASH_Sectors = (uint32_t)(~FLASH_Sectors); + WRP0_Data = (uint16_t)(FLASH_Sectors & WRP0_Mask); + WRP1_Data = (uint16_t)((FLASH_Sectors & WRP1_Mask) >> 8); + WRP2_Data = (uint16_t)((FLASH_Sectors & WRP2_Mask) >> 16); + WRP3_Data = (uint16_t)((FLASH_Sectors & WRP3_Mask) >> 24); + + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + /* Read optionbytes */ + for(i = 0; i < 8; i++) + { + pbuf[i] = *(uint16_t *)(Addr + 2 * i); + } + + /* Erase optionbytes */ + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_OPTER_Set; + + /* Write optionbytes */ + pbuf[4] = WRP0_Data; + pbuf[5] = WRP1_Data; + pbuf[6] = WRP2_Data; + pbuf[7] = WRP3_Data; + + FLASH->CTLR |= CR_OPTPG_Set; + for(i = 0; i < 8; i++) + { + *(uint16_t *)(Addr + 2 * i) = pbuf[i]; + while(FLASH->STATR & SR_BSY) + ; + } + FLASH->CTLR &= ~CR_OPTPG_Set; + } + return status; +} + +/********************************************************************* + * @fn FLASH_ReadOutProtection + * + * @brief Enables or disables the read out protection. + * + * @param Newstate - new state of the ReadOut Protection(ENABLE or DISABLE). + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState) +{ + FLASH_Status status = FLASH_COMPLETE; + uint32_t Addr = 0x1FFFF800; + __IO uint8_t i; + uint16_t pbuf[8]; + + status = FLASH_WaitForLastOperation(EraseTimeout); + if(status == FLASH_COMPLETE) + { + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + + /* Read optionbytes */ + for(i = 0; i < 8; i++) + { + pbuf[i] = *(uint16_t *)(Addr + 2 * i); + } + + /* Erase optionbytes */ + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_OPTER_Set; + + /* Write optionbytes */ + if(NewState == DISABLE) + pbuf[0] = 0x5AA5; + else + pbuf[0] = 0x00FF; + + FLASH->CTLR |= CR_OPTPG_Set; + for(i = 0; i < 8; i++) + { + *(uint16_t *)(Addr + 2 * i) = pbuf[i]; + while(FLASH->STATR & SR_BSY) + ; + } + FLASH->CTLR &= ~CR_OPTPG_Set; + } + return status; +} + +/********************************************************************* + * @fn FLASH_UserOptionByteConfig + * + * @brief Programs the FLASH User Option Byte - IWDG_SW / RST_STOP / RST_STDBY. + * + * @param OB_IWDG - Selects the IWDG mode + * OB_IWDG_SW - Software IWDG selected + * OB_IWDG_HW - Hardware IWDG selected + * OB_STOP - Reset event when entering STOP mode. + * OB_STOP_NoRST - No reset generated when entering in STOP + * OB_STOP_RST - Reset generated when entering in STOP + * OB_STDBY - Reset event when entering Standby mode. + * OB_STDBY_NoRST - No reset generated when entering in STANDBY + * OB_STDBY_RST - Reset generated when entering in STANDBY + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT. + */ +FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY) +{ + FLASH_Status status = FLASH_COMPLETE; + uint32_t Addr = 0x1FFFF800; + __IO uint8_t i; + uint16_t pbuf[8]; + uint16_t temp; + + FLASH->OBKEYR = FLASH_KEY1; + FLASH->OBKEYR = FLASH_KEY2; + status = FLASH_WaitForLastOperation(ProgramTimeout); + + if(status == FLASH_COMPLETE) + { + /* Read optionbytes */ + for(i = 0; i < 8; i++) + { + pbuf[i] = *(uint16_t *)(Addr + 2 * i); + } + + temp=pbuf[1]&(~0x7); + + /* Erase optionbytes */ + FLASH->CTLR |= CR_OPTER_Set; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_OPTER_Set; + + /* Write optionbytes */ + pbuf[1] = OB_IWDG | (uint16_t)(OB_STOP | (uint16_t)(OB_STDBY | ((uint16_t)temp))); + + FLASH->CTLR |= CR_OPTPG_Set; + for(i = 0; i < 8; i++) + { + *(uint16_t *)(Addr + 2 * i) = pbuf[i]; + while(FLASH->STATR & SR_BSY) + ; + } + FLASH->CTLR &= ~CR_OPTPG_Set; + } + return status; +} + +/********************************************************************* + * @fn FLASH_GetUserOptionByte + * + * @brief Returns the FLASH User Option Bytes values. + * + * @return The FLASH User Option Bytes values:IWDG_SW(Bit0), RST_STOP(Bit1) + * and RST_STDBY(Bit2). + */ +uint32_t FLASH_GetUserOptionByte(void) +{ + return (uint32_t)(FLASH->OBR >> 2); +} + +/********************************************************************* + * @fn FLASH_GetWriteProtectionOptionByte + * + * @brief Returns the FLASH Write Protection Option Bytes Register value. + * + * @return The FLASH Write Protection Option Bytes Register value. + */ +uint32_t FLASH_GetWriteProtectionOptionByte(void) +{ + return (uint32_t)(FLASH->WPR); +} + +/********************************************************************* + * @fn FLASH_GetReadOutProtectionStatus + * + * @brief Checks whether the FLASH Read Out Protection Status is set or not. + * + * @return FLASH ReadOut Protection Status(SET or RESET) + */ +FlagStatus FLASH_GetReadOutProtectionStatus(void) +{ + FlagStatus readoutstatus = RESET; + if((FLASH->OBR & RDPRT_Mask) != (uint32_t)RESET) + { + readoutstatus = SET; + } + else + { + readoutstatus = RESET; + } + return readoutstatus; +} + +/********************************************************************* + * @fn FLASH_ITConfig + * + * @brief Enables or disables the specified FLASH interrupts. + * + * @param FLASH_IT - specifies the FLASH interrupt sources to be enabled or disabled. + * FLASH_IT_ERROR - FLASH Error Interrupt + * FLASH_IT_EOP - FLASH end of operation Interrupt + * NewState - new state of the specified Flash interrupts(ENABLE or DISABLE). + * + * @return FLASH Prefetch Buffer Status (SET or RESET). + */ +void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + FLASH->CTLR |= FLASH_IT; + } + else + { + FLASH->CTLR &= ~(uint32_t)FLASH_IT; + } +} + +/********************************************************************* + * @fn FLASH_GetFlagStatus + * + * @brief Checks whether the specified FLASH flag is set or not. + * + * @param FLASH_FLAG - specifies the FLASH flag to check. + * FLASH_FLAG_BSY - FLASH Busy flag + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * FLASH_FLAG_OPTERR - FLASH Option Byte error flag + * + * @return The new state of FLASH_FLAG (SET or RESET). + */ +FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG) +{ + FlagStatus bitstatus = RESET; + + if(FLASH_FLAG == FLASH_FLAG_OPTERR) + { + if((FLASH->OBR & (1 << 0)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + else + { + if((FLASH->STATR & FLASH_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + } + return bitstatus; +} + +/********************************************************************* + * @fn FLASH_ClearFlag + * + * @brief Clears the FLASH's pending flags. + * + * @param FLASH_FLAG - specifies the FLASH flags to clear. + * FLASH_FLAG_WRPRTERR - FLASH Write protected error flag + * FLASH_FLAG_EOP - FLASH End of Operation flag + * + * @return none + */ +void FLASH_ClearFlag(uint32_t FLASH_FLAG) +{ + FLASH->STATR = FLASH_FLAG; +} + +/********************************************************************* + * @fn FLASH_GetStatus + * + * @brief Returns the FLASH Status. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetStatus(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_GetBank1Status + * + * @brief Returns the FLASH Bank1 Status. + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_GetBank1Status(void) +{ + FLASH_Status flashstatus = FLASH_COMPLETE; + + if((FLASH->STATR & FLASH_FLAG_BANK1_BSY) == FLASH_FLAG_BSY) + { + flashstatus = FLASH_BUSY; + } + else + { + if((FLASH->STATR & FLASH_FLAG_BANK1_WRPRTERR) != 0) + { + flashstatus = FLASH_ERROR_WRP; + } + else + { + flashstatus = FLASH_COMPLETE; + } + } + return flashstatus; +} + +/********************************************************************* + * @fn FLASH_WaitForLastOperation + * + * @brief Waits for a Flash operation to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_BUSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_WaitForLastBank1Operation + * + * @brief Waits for a Flash operation on Bank1 to complete or a TIMEOUT to occur. + * + * @param Timeout - FLASH programming Timeout + * + * @return FLASH Status - The returned value can be: FLASH_BUSY, FLASH_ERROR_PG, + * FLASH_ERROR_WRP or FLASH_COMPLETE. + */ +FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout) +{ + FLASH_Status status = FLASH_COMPLETE; + + status = FLASH_GetBank1Status(); + while((status == FLASH_FLAG_BANK1_BSY) && (Timeout != 0x00)) + { + status = FLASH_GetBank1Status(); + Timeout--; + } + if(Timeout == 0x00) + { + status = FLASH_TIMEOUT; + } + return status; +} + +/********************************************************************* + * @fn FLASH_Unlock_Fast + * + * @brief Unlocks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Unlock_Fast(void) +{ + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; +} + +/********************************************************************* + * @fn FLASH_Lock_Fast + * + * @brief Locks the Fast Program Erase Mode. + * + * @return none + */ +void FLASH_Lock_Fast(void) +{ + FLASH->CTLR |= CR_FLOCK_Set; +} + +/********************************************************************* + * @fn FLASH_ErasePage_Fast + * + * @brief Erases a specified FLASH page (1page = 256Byte). + * + * @param Page_Address - The page address to be erased. + * + * @return none + */ +void FLASH_ErasePage_Fast(uint32_t Page_Address) +{ + Page_Address &= 0xFFFFFF00; + + FLASH->CTLR |= CR_PAGE_ER; + FLASH->ADDR = Page_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_ER; +} + +/********************************************************************* + * @fn FLASH_EraseBlock_32K_Fast + * + * @brief Erases a specified FLASH Block (1Block = 32KByte). + * + * @param Block_Address - The block address to be erased. + * + * @return none + */ +void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address) +{ + Block_Address &= 0xFFFF8000; + + FLASH->CTLR |= CR_BER32; + FLASH->ADDR = Block_Address; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_BER32; +} + +/********************************************************************* + * @fn FLASH_ProgramPage_Fast + * + * @brief Program a specified FLASH page (1page = 256Byte). + * + * @param Page_Address - The page address to be programed. + * + * @return none + */ +void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t *pbuf) +{ + uint8_t size = 64; + + Page_Address &= 0xFFFFFF00; + + FLASH->CTLR |= CR_PAGE_PG; + while(FLASH->STATR & SR_BSY) + ; + while(FLASH->STATR & SR_WR_BSY) + ; + + while(size) + { + *(uint32_t *)Page_Address = *(uint32_t *)pbuf; + Page_Address += 4; + pbuf += 1; + size -= 1; + while(FLASH->STATR & SR_WR_BSY) + ; + } + + FLASH->CTLR |= CR_PG_STRT; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; +} + +/********************************************************************* + * @fn FLASH_Access_Clock_Cfg + * + * @brief Config FLASH Access Clock(Need to unlock ) + * + * @param FLASH_Access_CLK - + * FLASH_Access_SYSTEM_HALF - System clock/2 + * FLASH_Access_SYSTEM - System clock + * + * @return none + */ +void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK) +{ + FLASH->CTLR &= ~(1 << 25); + FLASH->CTLR |= FLASH_Access_CLK; +} + +/********************************************************************* + * @fn FLASH_Enhance_Mode + * + * @brief Read FLASH Enhance Mode + * + * @param Newstate - new state of the ReadOut Protection(ENABLE or DISABLE). + * + * @return none + */ +void FLASH_Enhance_Mode(FunctionalState NewState) +{ + if(NewState) + { + FLASH->CTLR |= (1 << 24); + } + else + { + FLASH->CTLR &= ~(1 << 24); + FLASH->CTLR |= (1 << 22); + } +} + +/********************************************************************* + * @fn ROM_ERASE + * + * @brief Select erases a specified FLASH . + * + * @param StartAddr - Erases Flash start address(StartAddr%256 == 0). + * Cnt - Erases count. + * Erase_Size - Erases size select.The returned value can be: + * Size_32KB, Size_4KB, Size_256B. + * + * @return none. + */ +static void ROM_ERASE(uint32_t StartAddr, uint32_t Cnt, uint32_t Erase_Size) +{ + do{ + if(Erase_Size == Size_32KB) + { + FLASH->CTLR |= CR_BER32; + } + else if(Erase_Size == Size_4KB) + { + FLASH->CTLR |= CR_PER_Set; + } + else if(Erase_Size == Size_256B) + { + FLASH->CTLR |= CR_PAGE_ER; + } + + FLASH->ADDR = StartAddr; + FLASH->CTLR |= CR_STRT_Set; + while(FLASH->STATR & SR_BSY) + ; + + if(Erase_Size == Size_32KB) + { + FLASH->CTLR &= ~CR_BER32; + StartAddr += Size_32KB; + } + else if(Erase_Size == Size_4KB) + { + FLASH->CTLR &= ~CR_PER_Set; + StartAddr += Size_4KB; + } + else if(Erase_Size == Size_256B) + { + FLASH->CTLR &= ~CR_PAGE_ER; + StartAddr += Size_256B; + } + }while(--Cnt); +} + +/********************************************************************* + * @fn FLASH_ROM_ERASE + * + * @brief Erases a specified FLASH . + * + * @param StartAddr - Erases Flash start address(StartAddr%256 == 0). + * Length - Erases Flash start Length(Length%256 == 0). + * + * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, + * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length) +{ + uint32_t Addr0 = 0, Addr1 = 0, Length0 = 0, Length1 = 0; + + FLASH_Status status = FLASH_COMPLETE; + + if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) + { + return FLASH_ADR_RANGE_ERROR; + } + + if((StartAddr + Length) > ValidAddrEnd) + { + return FLASH_OP_RANGE_ERROR; + } + + if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0)) + { + return FLASH_ALIGN_ERROR; + } + + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; + + Addr0 = StartAddr; + + if(Length >= Size_32KB) + { + Length0 = Size_32KB - (Addr0 & (Size_32KB - 1)); + Addr1 = StartAddr + Length0; + Length1 = Length - Length0; + } + else if(Length >= Size_4KB) + { + Length0 = Size_4KB - (Addr0 & (Size_4KB - 1)); + Addr1 = StartAddr + Length0; + Length1 = Length - Length0; + } + else if(Length >= Size_256B) + { + Length0 = Length; + } + + /* Erase 32KB */ + if(Length0 >= Size_32KB)//front + { + Length = Length0; + if(Addr0 & (Size_32KB - 1)) + { + Length0 = Size_32KB - (Addr0 & (Size_32KB - 1)); + } + else + { + Length0 = 0; + } + + ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 15), Size_32KB); + } + + if(Length1 >= Size_32KB)//back + { + StartAddr = Addr1; + Length = Length1; + + if((Addr1 + Length1) & (Size_32KB - 1)) + { + Addr1 = ((StartAddr + Length1) & (~(Size_32KB - 1))); + Length1 = (StartAddr + Length1) & (Size_32KB - 1); + } + else + { + Length1 = 0; + } + + ROM_ERASE(StartAddr, ((Length - Length1) >> 15), Size_32KB); + } + + /* Erase 4KB */ + if(Length0 >= Size_4KB) //front + { + Length = Length0; + if(Addr0 & (Size_4KB - 1)) + { + Length0 = Size_4KB - (Addr0 & (Size_4KB - 1)); + } + else + { + Length0 = 0; + } + + ROM_ERASE((Addr0 + Length0), ((Length - Length0) >> 12), Size_4KB); + } + + if(Length1 >= Size_4KB) //back + { + StartAddr = Addr1; + Length = Length1; + + if((Addr1 + Length1) & (Size_4KB - 1)) + { + Addr1 = ((StartAddr + Length1) & (~(Size_4KB - 1))); + Length1 = (StartAddr + Length1) & (Size_4KB - 1); + } + else + { + Length1 = 0; + } + + ROM_ERASE(StartAddr, ((Length - Length1) >> 12), Size_4KB); + } + + /* Erase 256B */ + if(Length0)//front + { + ROM_ERASE(Addr0, (Length0 >> 8), Size_256B); + } + + if(Length1)//back + { + ROM_ERASE(Addr1, (Length1 >> 8), Size_256B); + } + + FLASH->CTLR |= CR_FLOCK_Set; + FLASH->CTLR |= CR_LOCK_Set; + + return status; +} + +/********************************************************************* + * @fn FLASH_ROM_WRITE + * + * @brief Writes a specified FLASH . + * + * @param StartAddr - Writes Flash start address(StartAddr%256 == 0). + * Length - Writes Flash start Length(Length%256 == 0). + * pbuf - Writes Flash value buffer. + * + * @return FLASH Status - The returned value can be: FLASH_ADR_RANGE_ERROR, + * FLASH_ALIGN_ERROR, FLASH_OP_RANGE_ERROR or FLASH_COMPLETE. + */ +FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length) +{ + uint32_t i; + uint8_t size; + + FLASH_Status status = FLASH_COMPLETE; + + if((StartAddr < ValidAddrStart) || (StartAddr >= ValidAddrEnd)) + { + return FLASH_ADR_RANGE_ERROR; + } + + if((StartAddr + Length) > ValidAddrEnd) + { + return FLASH_OP_RANGE_ERROR; + } + + if((StartAddr & (Size_256B-1)) || (Length & (Size_256B-1)) || (Length == 0)) + { + return FLASH_ALIGN_ERROR; + } + + i = Length >> 8; + + /* Authorize the FPEC of Bank1 Access */ + FLASH->KEYR = FLASH_KEY1; + FLASH->KEYR = FLASH_KEY2; + + /* Fast program mode unlock */ + FLASH->MODEKEYR = FLASH_KEY1; + FLASH->MODEKEYR = FLASH_KEY2; + + do{ + FLASH->CTLR |= CR_PAGE_PG; + while(FLASH->STATR & SR_BSY) + ; + while(FLASH->STATR & SR_WR_BSY) + ; + size = 64; + while(size) + { + *(uint32_t *)StartAddr = *(uint32_t *)pbuf; + StartAddr += 4; + pbuf += 1; + size -= 1; + while(FLASH->STATR & SR_WR_BSY) + ; + } + + FLASH->CTLR |= CR_PG_STRT; + while(FLASH->STATR & SR_BSY) + ; + FLASH->CTLR &= ~CR_PAGE_PG; + }while(--i); + + FLASH->CTLR |= CR_FLOCK_Set; + FLASH->CTLR |= CR_LOCK_Set; + + return status; +} diff --git a/Peripheral/src/ch32v30x_fsmc.c b/Peripheral/src/ch32v30x_fsmc.c new file mode 100644 index 0000000..343307d --- /dev/null +++ b/Peripheral/src/ch32v30x_fsmc.c @@ -0,0 +1,378 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_fsmc.c +* Author : WCH +* Version : V1.0.1 +* Date : 2025/04/06 +* Description : This file provides all the FSMC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_fsmc.h" +#include "ch32v30x_rcc.h" + +/* FSMC BCRx Mask */ +#define BCR_MBKEN_Set ((uint32_t)0x00000001) +#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE) +#define BCR_FACCEN_Set ((uint32_t)0x00000040) + +/* FSMC PCRx Mask */ +#define PCR_PBKEN_Set ((uint32_t)0x00000004) +#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB) +#define PCR_ECCEN_Set ((uint32_t)0x00000040) +#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF) +#define PCR_MemoryType_NAND ((uint32_t)0x00000008) + +/********************************************************************* + * @fn FSMC_NORSRAMDeInit + * + * @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default + * reset values. + * + * @param FSMC_Bank- + * FSMC_Bank1_NORSRAM1 - FSMC Bank1 NOR/SRAM1. + * + * @return none + */ +void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank) +{ + if(FSMC_Bank == FSMC_Bank1_NORSRAM1) + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB; + } + else + { + FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; + } + FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF; + FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF; +} + +/********************************************************************* + * @fn FSMC_NANDDeInit + * + * @brief Deinitializes the FSMC NAND Banks registers to their default + * reset values. + * + * @param FSMC_Bank - + * FSMC_Bank2_NAND - FSMC Bank2 NAND. + * + * @return none + */ +void FSMC_NANDDeInit(uint32_t FSMC_Bank) +{ + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 = 0x00000018; + FSMC_Bank2->SR2 = 0x00000040; + FSMC_Bank2->PMEM2 = 0xFCFCFCFC; + FSMC_Bank2->PATT2 = 0xFCFCFCFC; + } +} + +/********************************************************************* + * @fn FSMC_NORSRAMInit + * + * @brief Initializes the FSMC NOR/SRAM Banks according to the specified + * parameters in the FSMC_NORSRAMInitStruct. + * + * @param SMC_NORSRAMInitStruct:pointer to a FSMC_NORSRAMInitTypeDef + * structure that contains the configuration information for the FSMC NOR/SRAM + * specified Banks. + * + * @return none + */ +void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct) +{ + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux | + FSMC_NORSRAMInitStruct->FSMC_MemoryType | + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth | + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode | + FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity | + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive | + FSMC_NORSRAMInitStruct->FSMC_WriteOperation | + FSMC_NORSRAMInitStruct->FSMC_WaitSignal | + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode | + FSMC_NORSRAMInitStruct->FSMC_WriteBurst; + + if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR) + { + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set; + } + + FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank + 1] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) | + (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) | + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode; + + if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable) + { + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = + (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4) | + (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) | + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode; + } + else + { + FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF; + } +} + +/********************************************************************* + * @fn FSMC_NANDInit + * + * @brief Initializes the FSMC NAND Banks according to the specified + * parameters in the FSMC_NANDInitStruct. + * + * @param FSMC_NANDInitStruct - pointer to a FSMC_NANDInitTypeDef + * structure that contains the configuration information for the FSMC + * NAND specified Banks. + * + * @return none + */ +void FSMC_NANDInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct) +{ + uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; + + tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature | + PCR_MemoryType_NAND | + FSMC_NANDInitStruct->FSMC_MemoryDataWidth | + FSMC_NANDInitStruct->FSMC_ECC | + FSMC_NANDInitStruct->FSMC_ECCPageSize | + (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9) | + (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13); + + tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16) | + (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16) | + (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24); + + if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 = tmppcr; + FSMC_Bank2->PMEM2 = tmppmem; + FSMC_Bank2->PATT2 = tmppatt; + } +} + +/********************************************************************* + * @fn FSMC_NORSRAMStructInit + * + * @brief Fills each FSMC_NORSRAMInitStruct member with its default value. + * + * @param FSMC_NORSRAMInitStruct - pointer to a FSMC_NORSRAMInitTypeDef + * structure which will be initialized. + * + * @return none + */ +void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct) +{ + FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1; + FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable; + FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM; + FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; + FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; + FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable; + FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable; + FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; + FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF; + FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF; + FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; +} + +/********************************************************************* + * @fn FSMC_NANDStructInit + * + * @brief Fills each FSMC_NANDInitStruct member with its default value. + * + * @param FSMC_NANDInitStruct - pointer to a FSMC_NANDInitTypeDef + * structure which will be initialized. + * + * @return none + */ +void FSMC_NANDStructInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct) +{ + FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND; + FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable; + FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b; + FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable; + FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes; + FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC; + FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC; +} + +/********************************************************************* + * @fn FSMC_NORSRAMCmd + * + * @brief Enables or disables the specified NOR/SRAM Memory Bank. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank1_NORSRAM1 - FSMC Bank1 NOR/SRAM1 + * FSMC_Bank1_NORSRAM2 - FSMC Bank1 NOR/SRAM2 + * FSMC_Bank1_NORSRAM3 - FSMC Bank1 NOR/SRAM3 + * FSMC_Bank1_NORSRAM4 - FSMC Bank1 NOR/SRAM4 + * NewState:ENABLE or DISABLE. + * + * @return none + */ +void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set; + } + else + { + FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset; + } +} + +/********************************************************************* + * @fn FSMC_NANDCmd + * + * @brief Enables or disables the specified NAND Memory Bank. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank2_NAND - FSMC Bank2 NAND + * NewStat - ENABLE or DISABLE. + * + * @return none + */ +void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_PBKEN_Set; + } + } + else + { + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset; + } + } +} + +/********************************************************************* + * @fn FSMC_NANDECCCmd + * + * @brief Enables or disables the FSMC NAND ECC feature. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank2_NAND - FSMC Bank2 NAND + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 |= PCR_ECCEN_Set; + } + } + else + { + if(FSMC_Bank == FSMC_Bank2_NAND) + { + FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset; + } + } +} + +/********************************************************************* + * @fn FSMC_GetECC + * + * @brief Returns the error correction code register value. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank2_NAND - FSMC Bank2 NAND + * NewState - ENABLE or DISABLE. + * + * @return eccval - The Error Correction Code (ECC) value. + */ +uint32_t FSMC_GetECC(uint32_t FSMC_Bank) +{ + uint32_t eccval = 0x00000000; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + eccval = FSMC_Bank2->ECCR2; + } + + return (eccval); +} + +/********************************************************************* + * @fn FSMC_GetFlagStatus + * + * @brief Checks whether the specified FSMC flag is set or not. + * + * @param FSMC_Bank - specifies the FSMC Bank to be used + * FSMC_Bank2_NAND - FSMC Bank2 NAND + * FSMC_FLAG - specifies the flag to check. + * FSMC_FLAG_FEMPT - Fifo empty Flag. + * NewState - ENABLE or DISABLE. + * + * @return FlagStatus - The new state of FSMC_FLAG (SET or RESET). + */ +FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpsr = 0x00000000; + + if(FSMC_Bank == FSMC_Bank2_NAND) + { + tmpsr = FSMC_Bank2->SR2; + } + + if((tmpsr & FSMC_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} diff --git a/Peripheral/src/ch32v30x_gpio.c b/Peripheral/src/ch32v30x_gpio.c new file mode 100644 index 0000000..b5a0169 --- /dev/null +++ b/Peripheral/src/ch32v30x_gpio.c @@ -0,0 +1,895 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_gpio.c +* Author : WCH +* Version : V1.0.0 +* Date : 2024/05/06 +* Description : This file provides all the GPIO firmware functions. +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_gpio.h" +#include "ch32v30x_rcc.h" + +/* MASK */ +#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) + +/********************************************************************* + * @fn GPIO_DeInit + * + * @brief Deinitializes the GPIOx peripheral registers to their default + * reset values. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @return none + */ +void GPIO_DeInit(GPIO_TypeDef *GPIOx) +{ + if(GPIOx == GPIOA) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); + } + else if(GPIOx == GPIOB) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); + } + else if(GPIOx == GPIOC) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); + } + else if(GPIOx == GPIOD) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); + } + else if(GPIOx == GPIOE) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); + } +} + +/********************************************************************* + * @fn GPIO_AFIODeInit + * + * @brief Deinitializes the Alternate Functions (remap, event control + * and EXTI configuration) registers to their default reset values. + * + * @return none + */ +void GPIO_AFIODeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); +} + +/********************************************************************* + * @fn GPIO_Init + * + * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that + * contains the configuration information for the specified GPIO peripheral. + * + * @return none + */ +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + uint32_t tmpreg = 0x00, pinmask = 0x00; + + currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + + if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) + { + currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; + } + + if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) + { + tmpreg = GPIOx->CFGLR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << pinpos); + } + else + { + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << pinpos); + } + } + } + } + GPIOx->CFGLR = tmpreg; + } + + if(GPIO_InitStruct->GPIO_Pin > 0x00FF) + { + tmpreg = GPIOx->CFGHR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((uint32_t)0x01) << (pinpos + 0x08)); + currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + } + } + GPIOx->CFGHR = tmpreg; + } +} + +/********************************************************************* + * @fn GPIO_StructInit + * + * @brief Fills each GPIO_InitStruct member with its default + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) +{ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/********************************************************************* + * @fn GPIO_ReadInputDataBit + * + * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @param GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * + * @return The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadInputData + * + * @brief Reads the specified GPIO input data port. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @return The output port pin value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) +{ + return ((uint16_t)GPIOx->INDR); +} + +/********************************************************************* + * @fn GPIO_ReadOutputDataBit + * + * @brief Reads the specified output data port bit. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadOutputData + * + * @brief Reads the specified GPIO output data port. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @return GPIO output port pin value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) +{ + return ((uint16_t)GPIOx->OUTDR); +} + +/********************************************************************* + * @fn GPIO_SetBits + * + * @brief Sets the selected data port bits. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIOx->BSHR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_ResetBits + * + * @brief Clears the selected data port bits. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIOx->BCR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_WriteBit + * + * @brief Sets or clears the selected data port bit. + * + * @param GPIO_Pin - specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * BitVal - specifies the value to be written to the selected bit. + * Bit_RESET - to clear the port pin. + * Bit_SET - to set the port pin. + * + * @return none + */ +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + if(BitVal != Bit_RESET) + { + GPIOx->BSHR = GPIO_Pin; + } + else + { + GPIOx->BCR = GPIO_Pin; + } +} + +/********************************************************************* + * @fn GPIO_Write + * + * @brief Writes data to the specified GPIO data port. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * PortVal - specifies the value to be written to the port output data register. + * + * @return none + */ +void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal) +{ + GPIOx->OUTDR = PortVal; +} + +/********************************************************************* + * @fn GPIO_PinLockConfig + * + * @brief Locks GPIO Pins configuration registers. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp = 0x00010000; + + tmp |= GPIO_Pin; + GPIOx->LCKR = tmp; + GPIOx->LCKR = GPIO_Pin; + GPIOx->LCKR = tmp; + tmp = GPIOx->LCKR; + tmp = GPIOx->LCKR; +} + +/********************************************************************* + * @fn GPIO_EventOutputConfig + * + * @brief Selects the GPIO pin used as Event output. + * + * @param GPIO_PortSource - selects the GPIO port to be used as source + * for Event output. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E). + * GPIO_PinSource - specifies the pin for the Event output. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * + * @return none + */ +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmpreg = 0x00; + + tmpreg = AFIO->ECR; + tmpreg &= ECR_PORTPINCONFIG_MASK; + tmpreg |= (uint32_t)GPIO_PortSource << 0x04; + tmpreg |= GPIO_PinSource; + AFIO->ECR = tmpreg; +} + +/********************************************************************* + * @fn GPIO_EventOutputCmd + * + * @brief Enables or disables the Event Output. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void GPIO_EventOutputCmd(FunctionalState NewState) +{ + if(NewState) + { + AFIO->ECR |= (1 << 7); + } + else + { + AFIO->ECR &= ~(1 << 7); + } +} + +/********************************************************************* + * @fn GPIO_PinRemapConfig + * + * @brief Changes the mapping of the specified pin. + * + * @param GPIO_Remap - selects the pin to remap. + * GPIO_Remap_SPI1 - SPI1 Alternate Function mapping + * GPIO_Remap_SPI3 - SPI3 Alternate Function mapping(CH32V30X_D8,CH32V30X_D8C) + * GPIO_Remap_I2C1 - I2C1 Alternate Function mapping + * GPIO_Remap_USART1 - USART1 Alternate Function mapping + * GPIO_Remap_USART2 - USART2 Alternate Function mapping + * GPIO_PartialRemap_USART3 - USART3 Partial Alternate Function mapping + * GPIO_PartialRemap1_USART3 - USART3 Partial1 Alternate Function mapping + * GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping + * GPIO_PartialRemap_TIM1 - TIM1 Partial Alternate Function mapping + * GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping + * GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping + * GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping + * GPIO_PartialRemap_TIM3 - TIM3 Partial Alternate Function mapping + * GPIO_FullRemap_TIM3 - TIM3 Full Alternate Function mapping + * GPIO_Remap_TIM4 - TIM4 Alternate Function mapping + * GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping + * GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping + * GPIO_Remap_PD0PD1 - PD0 and PD1 Alternate Function mapping + * GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping + * GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping + * GPIO_Remap_ADC2_ETRGINJ - ADC2 External Trigger Injected Conversion remapping + * GPIO_Remap_ADC2_ETRGREG - ADC2 External Trigger Regular Conversion remapping + * GPIO_Remap_ETH - Ethernet remapping + * GPIO_Remap_CAN2 - CAN2 remapping + * GPIO_Remap_MII_RMII_SEL - MII or RMII selection + * GPIO_Remap_SWJ_Disable - Full SWJ Disabled + * GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) connected + * to TIM2 Internal Trigger 1 for calibration + * GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) + * GPIO_Remap_TIM8 - TIM8 Alternate Function mapping + * GPIO_PartialRemap_TIM9 - TIM9 Partial Alternate Function mapping + * GPIO_FullRemap_TIM9 - TIM9 Full Alternate Function mapping + * GPIO_PartialRemap_TIM10 - TIM10 Partial Alternate Function mapping + * GPIO_FullRemap_TIM10 - TIM10 Full Alternate Function mapping + * GPIO_Remap_FSMC_NADV - FSMC_NADV Alternate Function mapping + * GPIO_PartialRemap_USART4 - USART4 Partial Alternate Function mapping + * GPIO_FullRemap_USART4 - USART4 Full Alternate Function mapping + * GPIO_PartialRemap_USART5 - USART5 Partial Alternate Function mapping + * GPIO_FullRemap_USART5 - USART5 Full Alternate Function mapping + * GPIO_PartialRemap_USART6 - USART6 Partial Alternate Function mapping + * GPIO_FullRemap_USART6 - USART6 Full Alternate Function mapping + * GPIO_PartialRemap_USART7 - USART7 Partial Alternate Function mapping + * GPIO_FullRemap_USART7 - USART7 Full Alternate Function mapping + * GPIO_PartialRemap_USART8 - USART8 Partial Alternate Function mapping + * GPIO_FullRemap_USART8 - USART8 Full Alternate Function mapping + * GPIO_Remap_USART1_HighBit - USART1 Alternate Function mapping high bit + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) +{ + uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; + + if((GPIO_Remap & 0x80000000) == 0x80000000) + { + tmpreg = AFIO->PCFR2; + } + else + { + tmpreg = AFIO->PCFR1; + } + + tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; + tmp = GPIO_Remap & LSB_MASK; + + /* Clear bit */ + if((GPIO_Remap & 0x80000000) == 0x80000000) + { /* PCFR2 */ + if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [31:16] 2bit */ + { + tmp1 = ((uint32_t)0x03) << (tmpmask + 0x10); + tmpreg &= ~tmp1; + } + else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */ + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg &= ~tmp1; + } + else /* [31:0] 1bit */ + { + tmpreg &= ~(tmp << (((GPIO_Remap & 0x7FFFFFFF)>> 0x15) * 0x10)); + } + } + else + { /* PCFR1 */ + if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [26:24] 3bit SWD_JTAG */ + { + tmpreg &= DBGAFR_SWJCFG_MASK; + AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK; + } + else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */ + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg &= ~tmp1; + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + else /* [31:0] 1bit */ + { + tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10)); + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + } + + /* Set bit */ + if(NewState != DISABLE) + { + tmpreg |= (tmp << (((GPIO_Remap & 0x7FFFFFFF)>> 0x15) * 0x10)); + } + + if((GPIO_Remap & 0x80000000) == 0x80000000) + { + AFIO->PCFR2 = tmpreg; + } + else + { + AFIO->PCFR1 = tmpreg; + } +} + +/********************************************************************* + * @fn GPIO_EXTILineConfig + * + * @brief Selects the GPIO pin used as EXTI Line. + * + * @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). + * GPIO_PinSource - specifies the EXTI line to be configured. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * + * @return none + */ +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmp = 0x00; + + tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); + AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; + AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); +} + +/********************************************************************* + * @fn GPIO_ETH_MediaInterfaceConfig + * + * @brief Selects the Ethernet media interface. + * + * @param GPIO_ETH_MediaInterface - specifies the Media Interface mode. + * GPIO_ETH_MediaInterface_MII - MII mode + * GPIO_ETH_MediaInterface_RMII - RMII mode + * + * @return none + */ +void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface) +{ + if(GPIO_ETH_MediaInterface) + { + AFIO->PCFR1 |= (1 << 23); + } + else + { + AFIO->PCFR1 &= ~(1 << 23); + } +} +/********************************************************************* + * @fn GPIO_IPD_Unused + * + * @brief Configure unused GPIO as input pull-down. + * + * @param none + * + * @return none + */ +void GPIO_IPD_Unused(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + uint32_t chip = 0; + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC|\ + RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE, ENABLE); + chip = *( uint32_t * )0x1FFFF704 & (~0x000000F0); + switch(chip) + { +#ifdef CH32V30x_D8 + case 0x30330504: //CH32V303CBT6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOE, &GPIO_InitStructure); + break; + } + case 0x30320504: //CH32V303RBT6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_7|GPIO_Pin_8\ + |GPIO_Pin_9|GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_12\ + |GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOE, &GPIO_InitStructure); + break; + } + case 0x30310504: //CH32V303RCT6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_7|GPIO_Pin_8\ + |GPIO_Pin_9|GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_12\ + |GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOE, &GPIO_InitStructure); + break; + } + case 0x30300504: //CH32V303VCT6 + { + break; + } +#elif defined (CH32V30x_D8C) + case 0x30520508: //CH32V305FBP6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_2\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_8|GPIO_Pin_9; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOE, &GPIO_InitStructure); + break; + } + case 0x305C0508: //CH32V305CCT6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7|GPIO_Pin_8\ + |GPIO_Pin_9|GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_12\ + |GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOE, &GPIO_InitStructure); + break; + } + case 0x30500508: //CH32V305RBT6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_7|GPIO_Pin_8\ + |GPIO_Pin_9|GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_12\ + |GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOE, &GPIO_InitStructure); + break; + } + case 0x30710508: //CH32V307RCT6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_7|GPIO_Pin_8\ + |GPIO_Pin_9|GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_12\ + |GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOE, &GPIO_InitStructure); + break; + } + case 0x30730508: //CH32V307WCU6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_7|GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_12\ + |GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1|GPIO_Pin_2\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_7|GPIO_Pin_8\ + |GPIO_Pin_9|GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_12\ + |GPIO_Pin_13|GPIO_Pin_14\ + |GPIO_Pin_15; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOE, &GPIO_InitStructure); + break; + } + case 0x3173B508: //CH32V317WCU6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1|GPIO_Pin_2\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOE, &GPIO_InitStructure); + break; + } + case 0x3175B508: //CH32V317TCU6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9|GPIO_Pin_10; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9|GPIO_Pin_10\ + |GPIO_Pin_11; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_7|GPIO_Pin_8\ + |GPIO_Pin_9|GPIO_Pin_10\ + |GPIO_Pin_11|GPIO_Pin_12\ + |GPIO_Pin_13; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11\ + |GPIO_Pin_12|GPIO_Pin_13\ + |GPIO_Pin_14|GPIO_Pin_15\ + |GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6\ + |GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\ + |GPIO_Pin_3|GPIO_Pin_4\ + |GPIO_Pin_5|GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOE, &GPIO_InitStructure); + break; + } + case 0x30700508: //CH32V307VCT6 + { + break; + } + case 0x3170B508: //CH32V317VCT6 + { + break; + } +#endif + default: + { + break; + } + } +} diff --git a/Peripheral/src/ch32v30x_i2c.c b/Peripheral/src/ch32v30x_i2c.c new file mode 100644 index 0000000..05c9b43 --- /dev/null +++ b/Peripheral/src/ch32v30x_i2c.c @@ -0,0 +1,1012 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_i2c.c +* Author : WCH +* Version : V1.0.0 +* Date : 2024/03/06 +* Description : This file provides all the I2C firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_i2c.h" +#include "ch32v30x_rcc.h" + +/* I2C SPE mask */ +#define CTLR1_PE_Set ((uint16_t)0x0001) +#define CTLR1_PE_Reset ((uint16_t)0xFFFE) + +/* I2C START mask */ +#define CTLR1_START_Set ((uint16_t)0x0100) +#define CTLR1_START_Reset ((uint16_t)0xFEFF) + +/* I2C STOP mask */ +#define CTLR1_STOP_Set ((uint16_t)0x0200) +#define CTLR1_STOP_Reset ((uint16_t)0xFDFF) + +/* I2C ACK mask */ +#define CTLR1_ACK_Set ((uint16_t)0x0400) +#define CTLR1_ACK_Reset ((uint16_t)0xFBFF) + +/* I2C ENGC mask */ +#define CTLR1_ENGC_Set ((uint16_t)0x0040) +#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF) + +/* I2C SWRST mask */ +#define CTLR1_SWRST_Set ((uint16_t)0x8000) +#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF) + +/* I2C PEC mask */ +#define CTLR1_PEC_Set ((uint16_t)0x1000) +#define CTLR1_PEC_Reset ((uint16_t)0xEFFF) + +/* I2C ENPEC mask */ +#define CTLR1_ENPEC_Set ((uint16_t)0x0020) +#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF) + +/* I2C ENARP mask */ +#define CTLR1_ENARP_Set ((uint16_t)0x0010) +#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF) + +/* I2C NOSTRETCH mask */ +#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080) +#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F) + +/* I2C registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xFBF5) + +/* I2C DMAEN mask */ +#define CTLR2_DMAEN_Set ((uint16_t)0x0800) +#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF) + +/* I2C LAST mask */ +#define CTLR2_LAST_Set ((uint16_t)0x1000) +#define CTLR2_LAST_Reset ((uint16_t)0xEFFF) + +/* I2C FREQ mask */ +#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0) + +/* I2C ADD0 mask */ +#define OADDR1_ADD0_Set ((uint16_t)0x0001) +#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE) + +/* I2C ENDUAL mask */ +#define OADDR2_ENDUAL_Set ((uint16_t)0x0001) +#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE) + +/* I2C ADD2 mask */ +#define OADDR2_ADD2_Reset ((uint16_t)0xFF01) + +/* I2C F/S mask */ +#define CKCFGR_FS_Set ((uint16_t)0x8000) + +/* I2C CCR mask */ +#define CKCFGR_CCR_Set ((uint16_t)0x0FFF) + +/* I2C FLAG mask */ +#define FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define ITEN_Mask ((uint32_t)0x07000000) + +/********************************************************************* + * @fn I2C_DeInit + * + * @brief Deinitializes the I2Cx peripheral registers to their default + * reset values. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return none + */ +void I2C_DeInit(I2C_TypeDef *I2Cx) +{ + if(I2Cx == I2C1) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE); + } + else + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE); + } +} + +/********************************************************************* + * @fn I2C_Init + * + * @brief Initializes the I2Cx peripheral according to the specified + * parameters in the I2C_InitStruct. + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_InitStruct - pointer to a I2C_InitTypeDef structure that + * contains the configuration information for the specified I2C peripheral. + * + * @return none + */ +void I2C_Init(I2C_TypeDef *I2Cx, I2C_InitTypeDef *I2C_InitStruct) +{ + uint16_t tmpreg = 0, freqrange = 0; + uint16_t result = 0x04; + uint32_t pclk1 = 8000000; + + RCC_ClocksTypeDef rcc_clocks; + + tmpreg = I2Cx->CTLR2; + tmpreg &= CTLR2_FREQ_Reset; + RCC_GetClocksFreq(&rcc_clocks); + pclk1 = rcc_clocks.PCLK1_Frequency; + freqrange = (uint16_t)(pclk1 / 1000000); + if(freqrange >= 60) + { + freqrange = 60; + } + tmpreg |= freqrange; + I2Cx->CTLR2 = tmpreg; + + I2Cx->CTLR1 &= CTLR1_PE_Reset; + tmpreg = 0; + + if(I2C_InitStruct->I2C_ClockSpeed <= 100000) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1)); + + if(result < 0x04) + { + result = 0x04; + } + + tmpreg |= result; + I2Cx->RTR = freqrange + 1; + } + else + { + if(I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2) + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3)); + } + else + { + result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25)); + result |= I2C_DutyCycle_16_9; + } + + if((result & CKCFGR_CCR_Set) == 0) + { + result |= (uint16_t)0x0001; + } + + tmpreg |= (uint16_t)(result | CKCFGR_FS_Set); + I2Cx->RTR = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1); + } + + I2Cx->CKCFGR = tmpreg; + I2Cx->CTLR1 |= CTLR1_PE_Set; + + tmpreg = I2Cx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack); + I2Cx->CTLR1 = tmpreg; + + I2Cx->OADDR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1); +} + +/********************************************************************* + * @fn I2C_StructInit + * + * @brief Fills each I2C_InitStruct member with its default value. + * + * @param I2C_InitStruct - pointer to an I2C_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void I2C_StructInit(I2C_InitTypeDef *I2C_InitStruct) +{ + I2C_InitStruct->I2C_ClockSpeed = 5000; + I2C_InitStruct->I2C_Mode = I2C_Mode_I2C; + I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2; + I2C_InitStruct->I2C_OwnAddress1 = 0; + I2C_InitStruct->I2C_Ack = I2C_Ack_Disable; + I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit; +} + +/********************************************************************* + * @fn I2C_Cmd + * + * @brief Enables or disables the specified I2C peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_Cmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PE_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PE_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMACmd + * + * @brief Enables or disables the specified I2C DMA requests. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMACmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_DMAEN_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_DMAEN_Reset; + } +} + +/********************************************************************* + * @fn I2C_DMALastTransferCmd + * + * @brief Specifies if the next DMA transfer will be the last one. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DMALastTransferCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= CTLR2_LAST_Set; + } + else + { + I2Cx->CTLR2 &= CTLR2_LAST_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTART + * + * @brief Generates I2Cx communication START condition. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTART(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_START_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_START_Reset; + } +} + +/********************************************************************* + * @fn I2C_GenerateSTOP + * + * @brief Generates I2Cx communication STOP condition. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GenerateSTOP(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_STOP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_STOP_Reset; + } +} + +/********************************************************************* + * @fn I2C_AcknowledgeConfig + * + * @brief Enables or disables the specified I2C acknowledge feature. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_AcknowledgeConfig(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ACK_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ACK_Reset; + } +} + +/********************************************************************* + * @fn I2C_OwnAddress2Config + * + * @brief Configures the specified I2C own address2. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Address - specifies the 7bit I2C own address2. + * + * @return none + */ +void I2C_OwnAddress2Config(I2C_TypeDef *I2Cx, uint8_t Address) +{ + uint16_t tmpreg = 0; + + tmpreg = I2Cx->OADDR2; + tmpreg &= OADDR2_ADD2_Reset; + tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE); + I2Cx->OADDR2 = tmpreg; +} + +/********************************************************************* + * @fn I2C_DualAddressCmd + * + * @brief Enables or disables the specified I2C dual addressing mode. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_DualAddressCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->OADDR2 |= OADDR2_ENDUAL_Set; + } + else + { + I2Cx->OADDR2 &= OADDR2_ENDUAL_Reset; + } +} + +/********************************************************************* + * @fn I2C_GeneralCallCmd + * + * @brief Enables or disables the specified I2C general call feature. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_GeneralCallCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENGC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENGC_Reset; + } +} + +/********************************************************************* + * @fn I2C_ITConfig + * + * @brief Enables or disables the specified I2C interrupts. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_IT - specifies the I2C interrupts sources to be enabled or disabled. + * I2C_IT_BUF - Buffer interrupt mask. + * I2C_IT_EVT - Event interrupt mask. + * I2C_IT_ERR - Error interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_ITConfig(I2C_TypeDef *I2Cx, uint16_t I2C_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR2 |= I2C_IT; + } + else + { + I2Cx->CTLR2 &= (uint16_t)~I2C_IT; + } +} + +/********************************************************************* + * @fn I2C_SendData + * + * @brief Sends a data byte through the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Data - Byte to be transmitted. + * + * @return none + */ +void I2C_SendData(I2C_TypeDef *I2Cx, uint8_t Data) +{ + I2Cx->DATAR = Data; +} + +/********************************************************************* + * @fn I2C_ReceiveData + * + * @brief Returns the most recent received data by the I2Cx peripheral. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return The value of the received data. + */ +uint8_t I2C_ReceiveData(I2C_TypeDef *I2Cx) +{ + return (uint8_t)I2Cx->DATAR; +} + +/********************************************************************* + * @fn I2C_Send7bitAddress + * + * @brief Transmits the address byte to select the slave device. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * Address - specifies the slave address which will be transmitted. + * I2C_Direction - specifies whether the I2C device will be a + * Transmitter or a Receiver. + * I2C_Direction_Transmitter - Transmitter mode. + * I2C_Direction_Receiver - Receiver mode. + * + * @return none + */ +void I2C_Send7bitAddress(I2C_TypeDef *I2Cx, uint8_t Address, uint8_t I2C_Direction) +{ + if(I2C_Direction != I2C_Direction_Transmitter) + { + Address |= OADDR1_ADD0_Set; + } + else + { + Address &= OADDR1_ADD0_Reset; + } + + I2Cx->DATAR = Address; +} + +/********************************************************************* + * @fn I2C_ReadRegister + * + * @brief Reads the specified I2C register and returns its value. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_Register - specifies the register to read. + * I2C_Register_CTLR1. + * I2C_Register_CTLR2. + * I2C_Register_OADDR1. + * I2C_Register_OADDR2. + * I2C_Register_DATAR. + * I2C_Register_STAR1. + * I2C_Register_STAR2. + * I2C_Register_CKCFGR. + * I2C_Register_RTR. + * + * @return none + */ +uint16_t I2C_ReadRegister(I2C_TypeDef *I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)I2Cx; + tmp += I2C_Register; + + return (*(__IO uint16_t *)tmp); +} + +/********************************************************************* + * @fn I2C_SoftwareResetCmd + * + * @brief Enables or disables the specified I2C software reset. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_SoftwareResetCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_SWRST_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_SWRST_Reset; + } +} + +/********************************************************************* + * @fn I2C_NACKPositionConfig + * + * @brief Selects the specified I2C NACK position in master receiver mode. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_NACKPosition - specifies the NACK position. + * I2C_NACKPosition_Next - indicates that the next byte will be + * the last received byte. + * I2C_NACKPosition_Current - indicates that current byte is the + * last received byte. + * Note- + * This function configures the same bit (POS) as I2C_PECPositionConfig() + * but is intended to be used in I2C mode while I2C_PECPositionConfig() + * is intended to used in SMBUS mode. + * @return none + */ +void I2C_NACKPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_NACKPosition) +{ + if(I2C_NACKPosition == I2C_NACKPosition_Next) + { + I2Cx->CTLR1 |= I2C_NACKPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_NACKPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_SMBusAlertConfig + * + * @brief Drives the SMBusAlert pin high or low for the specified I2C. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_SMBusAlert - specifies SMBAlert pin level. + * I2C_SMBusAlert_Low - SMBAlert pin driven low. + * I2C_SMBusAlert_High - SMBAlert pin driven high. + * + * @return none + */ +void I2C_SMBusAlertConfig(I2C_TypeDef *I2Cx, uint16_t I2C_SMBusAlert) +{ + if(I2C_SMBusAlert == I2C_SMBusAlert_Low) + { + I2Cx->CTLR1 |= I2C_SMBusAlert_Low; + } + else + { + I2Cx->CTLR1 &= I2C_SMBusAlert_High; + } +} + +/********************************************************************* + * @fn I2C_TransmitPEC + * + * @brief Enables or disables the specified I2C PEC transfer. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_TransmitPEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_PEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_PEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_PECPositionConfig + * + * @brief Selects the specified I2C PEC position. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_PECPosition - specifies the PEC position. + * I2C_PECPosition_Next - indicates that the next byte is PEC. + * I2C_PECPosition_Current - indicates that current byte is PEC. + * + * @return none + */ +void I2C_PECPositionConfig(I2C_TypeDef *I2Cx, uint16_t I2C_PECPosition) +{ + if(I2C_PECPosition == I2C_PECPosition_Next) + { + I2Cx->CTLR1 |= I2C_PECPosition_Next; + } + else + { + I2Cx->CTLR1 &= I2C_PECPosition_Current; + } +} + +/********************************************************************* + * @fn I2C_CalculatePEC + * + * @brief Enables or disables the PEC value calculation of the transferred bytes. + * + * @param I2Cx- where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_CalculatePEC(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENPEC_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENPEC_Reset; + } +} + +/********************************************************************* + * @fn I2C_GetPEC + * + * @brief Returns the PEC value for the specified I2C. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return The PEC value. + */ +uint8_t I2C_GetPEC(I2C_TypeDef *I2Cx) +{ + return ((I2Cx->STAR2) >> 8); +} + +/********************************************************************* + * @fn I2C_ARPCmd + * + * @brief Enables or disables the specified I2C ARP. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return The PEC value. + */ +void I2C_ARPCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + I2Cx->CTLR1 |= CTLR1_ENARP_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_ENARP_Reset; + } +} + +/********************************************************************* + * @fn I2C_StretchClockCmd + * + * @brief Enables or disables the specified I2C Clock stretching. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2C_StretchClockCmd(I2C_TypeDef *I2Cx, FunctionalState NewState) +{ + if(NewState == DISABLE) + { + I2Cx->CTLR1 |= CTLR1_NOSTRETCH_Set; + } + else + { + I2Cx->CTLR1 &= CTLR1_NOSTRETCH_Reset; + } +} + +/********************************************************************* + * @fn I2C_FastModeDutyCycleConfig + * + * @brief Selects the specified I2C fast mode duty cycle. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_DutyCycle - specifies the fast mode duty cycle. + * I2C_DutyCycle_2 - I2C fast mode Tlow/Thigh = 2. + * I2C_DutyCycle_16_9 - I2C fast mode Tlow/Thigh = 16/9. + * + * @return none + */ +void I2C_FastModeDutyCycleConfig(I2C_TypeDef *I2Cx, uint16_t I2C_DutyCycle) +{ + if(I2C_DutyCycle != I2C_DutyCycle_16_9) + { + I2Cx->CKCFGR &= I2C_DutyCycle_2; + } + else + { + I2Cx->CKCFGR |= I2C_DutyCycle_16_9; + } +} + +/********************************************************************* + * @fn I2C_CheckEvent + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx- where x can be 1 or 2 to select the I2C peripheral. + * I2C_EVENT: specifies the event to be checked. + * I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED - EVT1. + * I2C_EVENT_SLAVE_BYTE_RECEIVED - EVT2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF) - EVT2. + * (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL) - EVT2. + * I2C_EVENT_SLAVE_BYTE_TRANSMITTED - EVT3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF) - EVT3. + * (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL) - EVT3. + * I2C_EVENT_SLAVE_ACK_FAILURE - EVT3_2. + * I2C_EVENT_SLAVE_STOP_DETECTED - EVT4. + * I2C_EVENT_MASTER_MODE_SELECT - EVT5. + * I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED - EVT6. + * I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED - EVT6. + * I2C_EVENT_MASTER_BYTE_RECEIVED - EVT7. + * I2C_EVENT_MASTER_BYTE_TRANSMITTING - EVT8. + * I2C_EVENT_MASTER_BYTE_TRANSMITTED - EVT8_2. + * I2C_EVENT_MASTER_MODE_ADDRESS10 - EVT9. + * + * @return ErrorStatus - READY or NoREADY. + */ +ErrorStatus I2C_CheckEvent(I2C_TypeDef *I2Cx, uint32_t I2C_EVENT) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + ErrorStatus status = NoREADY; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + + lastevent = (flag1 | flag2) & FLAG_Mask; + + if((lastevent & I2C_EVENT) == I2C_EVENT) + { + status = READY; + } + else + { + status = NoREADY; + } + + return status; +} + +/********************************************************************* + * @fn I2C_GetLastEvent + * + * @brief Returns the last I2Cx Event. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * + * @return none + */ +uint32_t I2C_GetLastEvent(I2C_TypeDef *I2Cx) +{ + uint32_t lastevent = 0; + uint32_t flag1 = 0, flag2 = 0; + + flag1 = I2Cx->STAR1; + flag2 = I2Cx->STAR2; + flag2 = flag2 << 16; + lastevent = (flag1 | flag2) & FLAG_Mask; + + return lastevent; +} + +/********************************************************************* + * @fn I2C_GetFlagStatus + * + * @brief Checks whether the last I2Cx Event is equal to the one passed + * as parameter. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to check. + * I2C_FLAG_DUALF - Dual flag (Slave mode). + * I2C_FLAG_SMBHOST - SMBus host header (Slave mode). + * I2C_FLAG_SMBDEFAULT - SMBus default header (Slave mode). + * I2C_FLAG_GENCALL - General call header flag (Slave mode). + * I2C_FLAG_TRA - Transmitter/Receiver flag. + * I2C_FLAG_BUSY - Bus busy flag. + * I2C_FLAG_MSL - Master/Slave flag. + * I2C_FLAG_SMBALERT - SMBus Alert flag. + * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * I2C_FLAG_TXE - Data register empty flag (Transmitter). + * I2C_FLAG_RXNE- Data register not empty (Receiver) flag. + * I2C_FLAG_STOPF - Stop detection flag (Slave mode). + * I2C_FLAG_ADD10 - 10-bit header sent flag (Master mode). + * I2C_FLAG_BTF - Byte transfer finished flag. + * I2C_FLAG_ADDR - Address sent flag (Master mode) "ADSL" + * Address matched flag (Slave mode)"ENDA". + * I2C_FLAG_SB - Start bit flag (Master mode). + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus I2C_GetFlagStatus(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + FlagStatus bitstatus = RESET; + __IO uint32_t i2creg = 0, i2cxbase = 0; + + i2cxbase = (uint32_t)I2Cx; + i2creg = I2C_FLAG >> 28; + I2C_FLAG &= FLAG_Mask; + + if(i2creg != 0) + { + i2cxbase += 0x14; + } + else + { + I2C_FLAG = (uint32_t)(I2C_FLAG >> 16); + i2cxbase += 0x18; + } + + if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearFlag + * + * @brief Clears the I2Cx's pending flags. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_FLAG - specifies the flag to clear. + * I2C_FLAG_SMBALERT - SMBus Alert flag. + * I2C_FLAG_TIMEOUT - Timeout or Tlow error flag. + * I2C_FLAG_PECERR - PEC error in reception flag. + * I2C_FLAG_OVR - Overrun/Underrun flag (Slave mode). + * I2C_FLAG_AF - Acknowledge failure flag. + * I2C_FLAG_ARLO - Arbitration lost flag (Master mode). + * I2C_FLAG_BERR - Bus error flag. + * Note- + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STAR1 register (I2C_GetFlagStatus()) followed by a write operation + * to I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_SATR1 (I2C_GetFlagStatus()) followed by writing the + * second byte of the address in DATAR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_SATR1 register (I2C_GetFlagStatus()) followed by a + * read/write to I2C_DATAR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_SATR1 register (I2C_GetFlagStatus()) followed by a read operation to + * I2C_SATR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared software sequence: a read operation to I2C_STAR1 + * register (I2C_GetFlagStatus()) followed by a write operation to I2C_DATAR + * register (I2C_SendData()). + * @return none + */ +void I2C_ClearFlag(I2C_TypeDef *I2Cx, uint32_t I2C_FLAG) +{ + uint32_t flagpos = 0; + + flagpos = I2C_FLAG & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} + +/********************************************************************* + * @fn I2C_GetITStatus + * + * @brief Checks whether the specified I2C interrupt has occurred or not. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * II2C_IT - specifies the interrupt source to check. + * I2C_IT_SMBALERT - SMBus Alert flag. + * I2C_IT_TIMEOUT - Timeout or Tlow error flag. + * I2C_IT_PECERR - PEC error in reception flag. + * I2C_IT_OVR - Overrun/Underrun flag (Slave mode). + * I2C_IT_AF - Acknowledge failure flag. + * I2C_IT_ARLO - Arbitration lost flag (Master mode). + * I2C_IT_BERR - Bus error flag. + * I2C_IT_TXE - Data register empty flag (Transmitter). + * I2C_IT_RXNE - Data register not empty (Receiver) flag. + * I2C_IT_STOPF - Stop detection flag (Slave mode). + * I2C_IT_ADD10 - 10-bit header sent flag (Master mode). + * I2C_IT_BTF - Byte transfer finished flag. + * I2C_IT_ADDR - Address sent flag (Master mode) "ADSL" Address matched + * flag (Slave mode)"ENDAD". + * I2C_IT_SB - Start bit flag (Master mode). + * + * @return none + */ +ITStatus I2C_GetITStatus(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + ITStatus bitstatus = RESET; + uint32_t enablestatus = 0; + + enablestatus = (uint32_t)(((I2C_IT & ITEN_Mask) >> 16) & (I2Cx->CTLR2)); + I2C_IT &= FLAG_Mask; + + if(((I2Cx->STAR1 & I2C_IT) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn I2C_ClearITPendingBit + * + * @brief Clears the I2Cx interrupt pending bits. + * + * @param I2Cx - where x can be 1 or 2 to select the I2C peripheral. + * I2C_IT - specifies the interrupt pending bit to clear. + * I2C_IT_SMBALERT - SMBus Alert interrupt. + * I2C_IT_TIMEOUT - Timeout or Tlow error interrupt. + * I2C_IT_PECERR - PEC error in reception interrupt. + * I2C_IT_OVR - Overrun/Underrun interrupt (Slave mode). + * I2C_IT_AF - Acknowledge failure interrupt. + * I2C_IT_ARLO - Arbitration lost interrupt (Master mode). + * I2C_IT_BERR - Bus error interrupt. + * Note- + * - STOPF (STOP detection) is cleared by software sequence: a read operation + * to I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_CTLR1 register (I2C_Cmd() to re-enable the I2C peripheral). + * - ADD10 (10-bit header sent) is cleared by software sequence: a read + * operation to I2C_STAR1 (I2C_GetITStatus()) followed by writing the second + * byte of the address in I2C_DATAR register. + * - BTF (Byte Transfer Finished) is cleared by software sequence: a read + * operation to I2C_STAR1 register (I2C_GetITStatus()) followed by a + * read/write to I2C_DATAR register (I2C_SendData()). + * - ADDR (Address sent) is cleared by software sequence: a read operation to + * I2C_STAR1 register (I2C_GetITStatus()) followed by a read operation to + * I2C_STAR2 register ((void)(I2Cx->SR2)). + * - SB (Start Bit) is cleared by software sequence: a read operation to + * I2C_STAR1 register (I2C_GetITStatus()) followed by a write operation to + * I2C_DATAR register (I2C_SendData()). + * + * @return none + */ +void I2C_ClearITPendingBit(I2C_TypeDef *I2Cx, uint32_t I2C_IT) +{ + uint32_t flagpos = 0; + + flagpos = I2C_IT & FLAG_Mask; + I2Cx->STAR1 = (uint16_t)~flagpos; +} diff --git a/Peripheral/src/ch32v30x_iwdg.c b/Peripheral/src/ch32v30x_iwdg.c new file mode 100644 index 0000000..5877d8d --- /dev/null +++ b/Peripheral/src/ch32v30x_iwdg.c @@ -0,0 +1,123 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_iwdg.c +* Author : WCH +* Version : V1.0.0 +* Date : 2024/03/06 +* Description : This file provides all the IWDG firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_iwdg.h" + +/* CTLR register bit mask */ +#define CTLR_KEY_Reload ((uint16_t)0xAAAA) +#define CTLR_KEY_Enable ((uint16_t)0xCCCC) + +/********************************************************************* + * @fn IWDG_WriteAccessCmd + * + * @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers. + * + * @param WDG_WriteAccess - new state of write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and + * IWDG_RLDR registers. + * IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR + * and IWDG_RLDR registers. + * + * @return none + */ +void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess) +{ + IWDG->CTLR = IWDG_WriteAccess; +} + +/********************************************************************* + * @fn IWDG_SetPrescaler + * + * @brief Sets IWDG Prescaler value. + * + * @param IWDG_Prescaler - specifies the IWDG Prescaler value. + * IWDG_Prescaler_4 - IWDG prescaler set to 4. + * IWDG_Prescaler_8 - IWDG prescaler set to 8. + * IWDG_Prescaler_16 - IWDG prescaler set to 16. + * IWDG_Prescaler_32 - IWDG prescaler set to 32. + * IWDG_Prescaler_64 - IWDG prescaler set to 64. + * IWDG_Prescaler_128 - IWDG prescaler set to 128. + * IWDG_Prescaler_256 - IWDG prescaler set to 256. + * + * @return none + */ +void IWDG_SetPrescaler(uint8_t IWDG_Prescaler) +{ + IWDG->PSCR = IWDG_Prescaler; +} + +/********************************************************************* + * @fn IWDG_SetReload + * + * @brief Sets IWDG Reload value. + * + * @param Reload - specifies the IWDG Reload value. + * This parameter must be a number between 0 and 0x0FFF. + * + * @return none + */ +void IWDG_SetReload(uint16_t Reload) +{ + IWDG->RLDR = Reload; +} + +/********************************************************************* + * @fn IWDG_ReloadCounter + * + * @brief Reloads IWDG counter with value defined in the reload register. + * + * @return none + */ +void IWDG_ReloadCounter(void) +{ + IWDG->CTLR = CTLR_KEY_Reload; +} + +/********************************************************************* + * @fn IWDG_Enable + * + * @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled). + * + * @return none + */ +void IWDG_Enable(void) +{ + IWDG->CTLR = CTLR_KEY_Enable; + while((RCC->RSTSCKR & 0x2)==RESET); +} + +/********************************************************************* + * @fn IWDG_GetFlagStatus + * + * @brief Checks whether the specified IWDG flag is set or not. + * + * @param IWDG_FLAG - specifies the flag to check. + * IWDG_FLAG_PVU - Prescaler Value Update on going. + * IWDG_FLAG_RVU - Reload Value Update on going. + * + * @return none + */ +FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} diff --git a/Peripheral/src/ch32v30x_misc.c b/Peripheral/src/ch32v30x_misc.c new file mode 100644 index 0000000..f8c7cfd --- /dev/null +++ b/Peripheral/src/ch32v30x_misc.c @@ -0,0 +1,105 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_misc.c +* Author : WCH +* Version : V1.0.0 +* Date : 2024/03/06 +* Description : This file provides all the miscellaneous firmware functions . +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_misc.h" + +__IO uint32_t NVIC_Priority_Group = 0; + +/********************************************************************* + * @fn NVIC_PriorityGroupConfig + * + * @brief Configures the priority grouping - pre-emption priority and subpriority. + * + * @param NVIC_PriorityGroup - specifies the priority grouping bits length. + * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority + * 3 bits for subpriority + * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority + * 2 bits for subpriority + * NVIC_PriorityGroup_2 - 2 bits for pre-emption priority + * 1 bits for subpriority + * NVIC_PriorityGroup_3 - 3 bits for pre-emption priority + * 0 bits for subpriority + * + * @return none + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ + NVIC_Priority_Group = NVIC_PriorityGroup; +} + +/********************************************************************* + * @fn NVIC_Init + * + * @brief Initializes the NVIC peripheral according to the specified parameters in + * the NVIC_InitStruct. + * + * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the + * configuration information for the specified NVIC peripheral. + * interrupt nesting disable(CSR-0x804 bit1 = 0) + * NVIC_IRQChannelPreemptionPriority - range is 0. + * NVIC_IRQChannelSubPriority - range from 0 to 7. + * + * interrupt nesting enable-2 Level(CSR-0x804 bit1 = 1 bit[3:2] = 1) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. + * NVIC_IRQChannelSubPriority - range from 0 to 3. + * + * interrupt nesting enable-4 Level(CSR-0x804 bit1 = 1 bit[3:2] = 2) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 3. + * NVIC_IRQChannelSubPriority - range from 0 to 1. + * + * interrupt nesting enable-8 Level(CSR-0x804 bit1 = 1 bit[3:2] = 3) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 7. + * NVIC_IRQChannelSubPriority - range range is 0. + * + * @return none + */ +void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) +{ +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) + if(NVIC_Priority_Group == NVIC_PriorityGroup_0) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4); + } +#elif (INTSYSCR_INEST == INTSYSCR_INEST_EN_2Level) + if(NVIC_Priority_Group == NVIC_PriorityGroup_1) + { + if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority < 2) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5)); + } + } +#elif (INTSYSCR_INEST == INTSYSCR_INEST_EN_4Level) + if(NVIC_Priority_Group == NVIC_PriorityGroup_2) + { + if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority < 4) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 6) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5)); + } + } +#elif (INTSYSCR_INEST == INTSYSCR_INEST_EN_8Level) + if(NVIC_Priority_Group == NVIC_PriorityGroup_3) + { + if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority < 8) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 5) ); + } + } +#endif + + if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } + else + { + NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } +} diff --git a/Peripheral/src/ch32v30x_opa.c b/Peripheral/src/ch32v30x_opa.c new file mode 100644 index 0000000..ed84c00 --- /dev/null +++ b/Peripheral/src/ch32v30x_opa.c @@ -0,0 +1,86 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_opa.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the OPA firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_opa.h" + +#define OPA_MASK ((uint32_t)0x000F) +#define OPA_Total_NUM 4 + +/********************************************************************* + * @fn OPA_DeInit + * + * @brief Deinitializes the OPA peripheral registers to their default + * reset values. + * + * @return none + */ +void OPA_DeInit(void) +{ + OPA->CR = 0; +} + +/********************************************************************* + * @fn OPA_Init + * + * @brief Initializes the OPA peripheral according to the specified + * parameters in the OPA_InitStruct. + * + * @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure + * + * @return none + */ +void OPA_Init(OPA_InitTypeDef *OPA_InitStruct) +{ + uint32_t tmp = 0; + tmp = OPA->CR; + tmp &= ~(OPA_MASK << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM)); + tmp |= (((OPA_InitStruct->PSEL << OPA_PSEL_OFFSET) | (OPA_InitStruct->NSEL << OPA_NSEL_OFFSET) | (OPA_InitStruct->Mode << OPA_MODE_OFFSET)) << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM)); + OPA->CR = tmp; +} + +/********************************************************************* + * @fn OPA_StructInit + * + * @brief Fills each OPA_StructInit member with its reset value. + * + * @param OPA_StructInit - pointer to a OPA_InitTypeDef structure + * + * @return none + */ +void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct) +{ + OPA_InitStruct->Mode = OUT_IO_OUT1; + OPA_InitStruct->PSEL = CHP0; + OPA_InitStruct->NSEL = CHN0; + OPA_InitStruct->OPA_NUM = OPA1; +} + +/********************************************************************* + * @fn OPA_Cmd + * + * @brief Enables or disables the specified OPA peripheral. + * + * @param OPA_NUM - Select OPA + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState) +{ + if(NewState == ENABLE) + { + OPA->CR |= (1 << (OPA_NUM * OPA_Total_NUM)); + } + else + { + OPA->CR &= ~(1 << (OPA_NUM * OPA_Total_NUM)); + } +} diff --git a/Peripheral/src/ch32v30x_pwr.c b/Peripheral/src/ch32v30x_pwr.c new file mode 100644 index 0000000..28351c0 --- /dev/null +++ b/Peripheral/src/ch32v30x_pwr.c @@ -0,0 +1,361 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_pwr.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the PWR firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_pwr.h" +#include "ch32v30x_rcc.h" + +/* PWR registers bit mask */ +/* CTLR register bit mask */ +#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFC) +#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F) + +/********************************************************************* + * @fn PWR_DeInit + * + * @brief Deinitializes the PWR peripheral registers to their default + * reset values. + * + * @return none + */ +void PWR_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE); +} + +/********************************************************************* + * @fn PWR_BackupAccessCmd + * + * @brief Enables or disables access to the RTC and backup registers. + * + * @param NewState - new state of the access to the RTC and backup registers, + * This parameter can be: ENABLE or DISABLE. + * + * @return none + */ +void PWR_BackupAccessCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 8); + } + else + { + PWR->CTLR &= ~(1 << 8); + } +} + +/********************************************************************* + * @fn PWR_PVDCmd + * + * @brief Enables or disables the Power Voltage Detector(PVD). + * + * @param NewState - new state of the PVD(ENABLE or DISABLE). + * + * @return none + */ +void PWR_PVDCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CTLR |= (1 << 4); + } + else + { + PWR->CTLR &= ~(1 << 4); + } +} + +/********************************************************************* + * @fn PWR_PVDLevelConfig + * + * @brief Configures the voltage threshold detected by the Power Voltage + * Detector(PVD). + * + * @param PWR_PVDLevel - specifies the PVD detection level + * PWR_PVDLevel_MODE0 - PVD detection level set to mode 0. + * PWR_PVDLevel_MODE1 - PVD detection level set to mode 1. + * PWR_PVDLevel_MODE2 - PVD detection level set to mode 2. + * PWR_PVDLevel_MODE3 - PVD detection level set to mode 3. + * PWR_PVDLevel_MODE4 - PVD detection level set to mode 4. + * PWR_PVDLevel_MODE5 - PVD detection level set to mode 5. + * PWR_PVDLevel_MODE6 - PVD detection level set to mode 6. + * PWR_PVDLevel_MODE7 - PVD detection level set to mode 7. + * + * @return none + */ +void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_PLS_MASK; + tmpreg |= PWR_PVDLevel; + PWR->CTLR = tmpreg; +} + +/********************************************************************* + * @fn PWR_WakeUpPinCmd + * + * @brief Enables or disables the WakeUp Pin functionality. + * + * @param NewState - new state of the WakeUp Pin functionality + * (ENABLE or DISABLE). + * + * @return none + */ +void PWR_WakeUpPinCmd(FunctionalState NewState) +{ + if(NewState) + { + PWR->CSR |= (1 << 8); + } + else + { + PWR->CSR &= ~(1 << 8); + } +} + +/********************************************************************* + * @fn PWR_EnterSTOPMode + * + * @brief Enters STOP mode. + * + * @param PWR_Regulator - specifies the regulator state in STOP mode. + * PWR_Regulator_ON - STOP mode with regulator ON + * PWR_Regulator_LowPower - STOP mode with regulator in low power mode + * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. + * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction + * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction + * + * @return none + */ +void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_DS_MASK; + tmpreg |= PWR_Regulator; + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + __WFI(); + } + else + { + __WFE(); + } + + NVIC->SCTLR &= ~(1 << 2); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode + * + * @brief Enters STANDBY mode. + * + * @return none + */ +void PWR_EnterSTANDBYMode(void) +{ + PWR->CTLR |= PWR_CTLR_CWUF; + PWR->CTLR |= PWR_CTLR_PDDS; + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_GetFlagStatus + * + * @brief Checks whether the specified PWR flag is set or not. + * + * @param PWR_FLAG - specifies the flag to check. + * PWR_FLAG_WU - Wake Up flag + * PWR_FLAG_SB - StandBy flag + * PWR_FLAG_PVDO - PVD Output + * + * @return The new state of PWR_FLAG (SET or RESET). + */ +FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn PWR_ClearFlag + * + * @brief Clears the PWR's pending flags. + * + * @param PWR_FLAG - specifies the flag to clear. + * PWR_FLAG_WU - Wake Up flag + * PWR_FLAG_SB - StandBy flag + * + * @return none + */ +void PWR_ClearFlag(uint32_t PWR_FLAG) +{ + PWR->CTLR |= PWR_FLAG << 2; +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM + * + * @brief Enters STANDBY mode with RAM data retention function on. + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+30K in standby w power. + tmpreg |= (0x1 << 16) | (0x1 << 17); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM_LV + * + * @brief Enters STANDBY mode with RAM data retention function and LV mode on. + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM_LV(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+30K in standby power. + tmpreg |= (0x1 << 16) | (0x1 << 17); + //2K+30K in standby LV . + tmpreg |= (0x1 << 20); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM_VBAT_EN + * + * @brief Enters STANDBY mode with RAM data retention function on (VBAT Enable). + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+30K in standby power (VBAT Enable). + tmpreg |= (0x1 << 18) | (0x1 << 19); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + +/********************************************************************* + * @fn PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN + * + * @brief Enters STANDBY mode with RAM data retention function and LV mode on(VBAT Enable). + * + * @return none + */ +void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + + tmpreg |= PWR_CTLR_CWUF; + tmpreg |= PWR_CTLR_PDDS; + + //2K+30K in standby power (VBAT Enable). + tmpreg |= (0x1 << 18) | (0x1 << 19); + //2K+30K in standby LV . + tmpreg |= (0x1 << 20); + + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + __WFI(); +} + + +/********************************************************************* + * @fn PWR_EnterSTOPMode_RAM_LV + * + * @brief Enters STOP mode with RAM data retention function and LV mode on. + * + * @param PWR_Regulator - specifies the regulator state in STOP mode. + * PWR_Regulator_LowPower - STOP mode with regulator in low power mode + * PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction. + * PWR_STOPEntry_WFI - enter STOP mode with WFI instruction + * PWR_STOPEntry_WFE - enter STOP mode with WFE instruction + * + * @return none + */ +void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) +{ + uint32_t tmpreg = 0; + tmpreg = PWR->CTLR; + tmpreg &= CTLR_DS_MASK; + tmpreg |= PWR_Regulator; + + tmpreg |= (0x1 << 20); + PWR->CTLR = tmpreg; + + NVIC->SCTLR |= (1 << 2); + + if(PWR_STOPEntry == PWR_STOPEntry_WFI) + { + __WFI(); + } + else + { + __WFE(); + } + + NVIC->SCTLR &= ~(1 << 2); +} diff --git a/Peripheral/src/ch32v30x_rcc.c b/Peripheral/src/ch32v30x_rcc.c new file mode 100644 index 0000000..2062e47 --- /dev/null +++ b/Peripheral/src/ch32v30x_rcc.c @@ -0,0 +1,1477 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_rcc.c +* Author : WCH +* Version : V1.0.0 +* Date : 2024/05/28 +* Description : This file provides all the RCC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_rcc.h" + +/* RCC registers bit address in the alias region */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* BDCTLR Register */ +#define BDCTLR_OFFSET (RCC_OFFSET + 0x20) + +/* RCC registers bit mask */ + +/* CTLR register bit mask */ +#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) +#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CTLR_HSEON_Set ((uint32_t)0x00010000) +#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF) +#define CFGR0_PLL_Mask_1 ((uint32_t)0xFFC2FFFF) + +#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) +#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000C000) + +/* RSTSCKR register bit mask */ +#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) + +/* CFGR2 register bit mask */ +#define CFGR2_PREDIV1SRC ((uint32_t)0x00010000) +#define CFGR2_PREDIV1 ((uint32_t)0x0000000F) +#define CFGR2_PREDIV2 ((uint32_t)0x000000F0) +#define CFGR2_PLL2MUL ((uint32_t)0x00000F00) +#define CFGR2_PLL3MUL ((uint32_t)0x0000F000) + +/* RCC Flag Mask */ +#define FLAG_Mask ((uint8_t)0x1F) + +/* INTR register byte 2 (Bits[15:8]) base address */ +#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* INTR register byte 3 (Bits[23:16]) base address */ +#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR0 register byte 4 (Bits[31:24]) base address */ +#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCTLR register base address */ +#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET) + +static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; + +/********************************************************************* + * @fn RCC_DeInit + * + * @brief Resets the RCC clock configuration to the default reset state. + * Note- + * HSE can not be stopped if it is used directly or through the PLL as system clock. + * @return none + */ +void RCC_DeInit(void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + +#ifdef CH32V30x_D8C + RCC->CFGR0 &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR0 &= (uint32_t)0xF0FF0000; +#endif + + RCC->CTLR &= (uint32_t)0xFEF6FFFF; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + +#ifdef CH32V30x_D8C + RCC->CTLR &= (uint32_t)0xEBFFFFFF; + RCC->INTR = 0x00FF0000; + RCC->CFGR2 = 0x00000000; +#else + RCC->INTR = 0x009F0000; +#endif +} + +/********************************************************************* + * @fn RCC_HSEConfig + * + * @brief Configures the External High Speed oscillator (HSE). + * + * @param RCC_HSE - + * RCC_HSE_OFF - HSE oscillator OFF. + * RCC_HSE_ON - HSE oscillator ON. + * RCC_HSE_Bypass - HSE oscillator bypassed with external clock. + * Note- + * HSE can not be stopped if it is used directly or through the PLL as system clock. + * @return none + */ +void RCC_HSEConfig(uint32_t RCC_HSE) +{ + RCC->CTLR &= CTLR_HSEON_Reset; + RCC->CTLR &= CTLR_HSEBYP_Reset; + + switch(RCC_HSE) + { + case RCC_HSE_ON: + RCC->CTLR |= CTLR_HSEON_Set; + break; + + case RCC_HSE_Bypass: + RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn RCC_WaitForHSEStartUp + * + * @brief Waits for HSE start-up. + * + * @return READY - HSE oscillator is stable and ready to use. + * NoREADY - HSE oscillator not yet ready. + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + + ErrorStatus status = NoREADY; + FlagStatus HSEStatus = RESET; + + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); + + if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = READY; + } + else + { + status = NoREADY; + } + + return (status); +} + +/********************************************************************* + * @fn RCC_AdjustHSICalibrationValue + * + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * + * @param HSICalibrationValue - specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * + * @return none + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CTLR; + tmpreg &= CTLR_HSITRIM_Mask; + tmpreg |= (uint32_t)HSICalibrationValue << 3; + RCC->CTLR = tmpreg; +} + +/********************************************************************* + * @fn RCC_HSICmd + * + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_HSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 0); + } + else + { + RCC->CTLR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn RCC_PLLConfig + * + * @brief Configures the PLL clock source and multiplication factor. + * + * @param RCC_PLLSource - specifies the PLL entry clock source. + * RCC_PLLSource_HSI_Div2 - HSI oscillator clock divided by 2 + * selected as PLL clock entry. + * RCC_PLLSource_PREDIV1 - PREDIV1 clock selected as PLL clock + * entry. + * RCC_PLLMul - specifies the PLL multiplication factor. + * This parameter can be RCC_PLLMul_x where x:[2,16]. + * For CH32V307 - + * RCC_PLLMul_18_EXTEN + * RCC_PLLMul_3_EXTEN + * RCC_PLLMul_4_EXTEN + * RCC_PLLMul_5_EXTEN + * RCC_PLLMul_6_EXTEN + * RCC_PLLMul_7_EXTEN + * RCC_PLLMul_8_EXTEN + * RCC_PLLMul_9_EXTEN + * RCC_PLLMul_10_EXTEN + * RCC_PLLMul_11_EXTEN + * RCC_PLLMul_12_EXTEN + * RCC_PLLMul_13_EXTEN + * RCC_PLLMul_14_EXTEN + * RCC_PLLMul_6_5_EXTEN + * RCC_PLLMul_15_EXTEN + * RCC_PLLMul_16_EXTEN + * For other CH32V30x - + * RCC_PLLMul_2 + * RCC_PLLMul_3 + * RCC_PLLMul_4 + * RCC_PLLMul_5 + * RCC_PLLMul_6 + * RCC_PLLMul_7 + * RCC_PLLMul_8 + * RCC_PLLMul_9 + * RCC_PLLMul_10 + * RCC_PLLMul_11 + * RCC_PLLMul_12 + * RCC_PLLMul_13 + * RCC_PLLMul_14 + * RCC_PLLMul_15 + * RCC_PLLMul_16 + * RCC_PLLMul_18 + * + * @return none + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + + if(((*(uint32_t *)0x1FFFF70C) & (1 << 14)) != (1 << 14)) + { /* for other CH32V30x */ + tmpreg &= CFGR0_PLL_Mask; + } + else + { /* for CH32V307 */ + tmpreg &= CFGR0_PLL_Mask_1; + } + + tmpreg |= RCC_PLLSource | RCC_PLLMul; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PLLCmd + * + * @brief Enables or disables the PLL. + * Note-The PLL can not be disabled if it is used as system clock. + * + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 24); + } + else + { + RCC->CTLR &= ~(1 << 24); + } +} + +/********************************************************************* + * @fn RCC_SYSCLKConfig + * + * @brief Configures the system clock (SYSCLK). + * + * @param RCC_SYSCLKSource - specifies the clock source used as system clock. + * RCC_SYSCLKSource_HSI - HSI selected as system clock. + * RCC_SYSCLKSource_HSE - HSE selected as system clock. + * RCC_SYSCLKSource_PLLCLK - PLL selected as system clock. + * + * @return none + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_SW_Mask; + tmpreg |= RCC_SYSCLKSource; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_GetSYSCLKSource + * + * @brief Returns the clock source used as system clock. + * + * @return 0x00 - HSI used as system clock. + * 0x04 - HSE used as system clock. + * 0x08 - PLL used as system clock. + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask)); +} + +/********************************************************************* + * @fn RCC_HCLKConfig + * + * @brief Configures the AHB clock (HCLK). + * + * @param RCC_SYSCLK - defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * RCC_SYSCLK_Div1 - AHB clock = SYSCLK. + * RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2. + * RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4. + * RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8. + * RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16. + * RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64. + * RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128. + * RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256. + * RCC_SYSCLK_Div512 - AHB clock = SYSCLK/512. + * + * @return none + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_HPRE_Reset_Mask; + tmpreg |= RCC_SYSCLK; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PCLK1Config + * + * @brief Configures the Low Speed APB clock (PCLK1). + * + * @param RCC_HCLK - defines the APB1 clock divider. This clock is derived from + * the AHB clock (HCLK). + * RCC_HCLK_Div1 - APB1 clock = HCLK. + * RCC_HCLK_Div2 - APB1 clock = HCLK/2. + * RCC_HCLK_Div4 - APB1 clock = HCLK/4. + * RCC_HCLK_Div8 - APB1 clock = HCLK/8. + * RCC_HCLK_Div16 - APB1 clock = HCLK/16. + * + * @return none + */ +void RCC_PCLK1Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_PPRE1_Reset_Mask; + tmpreg |= RCC_HCLK; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PCLK2Config + * + * @brief Configures the High Speed APB clock (PCLK2). + * + * @param RCC_HCLK - defines the APB2 clock divider. This clock is derived from + * the AHB clock (HCLK). + * RCC_HCLK_Div1 - APB2 clock = HCLK. + * RCC_HCLK_Div2 - APB2 clock = HCLK/2. + * RCC_HCLK_Div4 - APB2 clock = HCLK/4. + * RCC_HCLK_Div8 - APB2 clock = HCLK/8. + * RCC_HCLK_Div16 - APB2 clock = HCLK/16. + * + * @return none + */ +void RCC_PCLK2Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_PPRE2_Reset_Mask; + tmpreg |= RCC_HCLK << 3; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_ITConfig + * + * @brief Enables or disables the specified RCC interrupts. + * + * @param RCC_IT - specifies the RCC interrupt sources to be enabled or disabled. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + *(__IO uint8_t *)INTR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + *(__IO uint8_t *)INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +/********************************************************************* + * @fn RCC_ADCCLKConfig + * + * @brief Configures the ADC clock (ADCCLK). + * + * @param RCC_PCLK2 - defines the ADC clock divider. This clock is derived from + * the APB2 clock (PCLK2). + * RCC_PCLK2_Div2 - ADC clock = PCLK2/2. + * RCC_PCLK2_Div4 - ADC clock = PCLK2/4. + * RCC_PCLK2_Div6 - ADC clock = PCLK2/6. + * RCC_PCLK2_Div8 - ADC clock = PCLK2/8. + * + * @return none + */ +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_ADCPRE_Reset_Mask; + tmpreg |= RCC_PCLK2; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_LSEConfig + * + * @brief Configures the External Low Speed oscillator (LSE). + * + * @param RCC_LSE - specifies the new state of the LSE. + * RCC_LSE_OFF - LSE oscillator OFF. + * RCC_LSE_ON - LSE oscillator ON. + * RCC_LSE_Bypass - LSE oscillator bypassed with external clock. + * + * @return none + */ +void RCC_LSEConfig(uint8_t RCC_LSE) +{ + *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_OFF; + *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_OFF; + + switch(RCC_LSE) + { + case RCC_LSE_ON: + *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_ON; + break; + + case RCC_LSE_Bypass: + *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn RCC_LSICmd + * + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * Note- + * LSI can not be disabled if the IWDG is running. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_LSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->RSTSCKR |= (1 << 0); + } + else + { + RCC->RSTSCKR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn RCC_RTCCLKConfig + * + * @brief Once the RTC clock is selected it can't be changed unless the Backup domain is reset. + * + * @param RCC_RTCCLKSource - specifies the RTC clock source. + * RCC_RTCCLKSource_LSE - LSE selected as RTC clock. + * RCC_RTCCLKSource_LSI - LSI selected as RTC clock. + * RCC_RTCCLKSource_HSE_Div128 - HSE clock divided by 128 selected as RTC clock. + * Note- + * Once the RTC clock is selected it can't be changed unless the Backup domain is reset. + * @return none + */ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + RCC->BDCTLR |= RCC_RTCCLKSource; +} + +/********************************************************************* + * @fn RCC_RTCCLKCmd + * + * @brief This function must be used only after the RTC clock was selected + * using the RCC_RTCCLKConfig function. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->BDCTLR |= (1 << 15); + } + else + { + RCC->BDCTLR &= ~(1 << 15); + } +} + +/********************************************************************* + * @fn RCC_GetClocksFreq + * + * @brief The result of this function could be not correct when using + * fractional value for HSE crystal. + * + * @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * + * @return none + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; + uint8_t Pll_6_5 = 0; + +#ifdef CH32V30x_D8C + uint8_t Pll2mull = 0; + +#endif + + tmp = RCC->CFGR0 & CFGR0_SWS_Mask; + + switch(tmp) + { + case 0x00: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + + case 0x04: + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; + break; + + case 0x08: + pllmull = RCC->CFGR0 & CFGR0_PLLMull_Mask; + pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask; + + pllmull = (pllmull >> 18) + 2; + + if(((*(uint32_t *)0x1FFFF70C) & (1 << 14)) != (1 << 14)) + { /* for other CH32V30x */ + if(pllmull == 17) + pllmull = 18; + } + else + { /* for CH32V307 */ + if(pllmull == 2) + pllmull = 18; + if(pllmull == 15) + { + pllmull = 13; /* *6.5 */ + Pll_6_5 = 1; + } + if(pllmull == 16) + pllmull = 15; + if(pllmull == 17) + pllmull = 16; + } + + if(pllsource == 0x00) + { + if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE) + { + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE)*pllmull; + } + else + { + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; + } + } + else + { +#ifdef CH32V30x_D8 + if((RCC->CFGR0 & CFGR0_PLLXTPRE_Mask) != (uint32_t)RESET) + { + RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; + } + else + { + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; + } +#else + if(RCC->CFGR2 & (1<<16)){ /* PLL2 */ + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE/(((RCC->CFGR2 & 0xF0)>>4) + 1); /* PREDIV2 */ + + Pll2mull = (uint8_t)((RCC->CFGR2 & 0xF00)>>8); + + if(Pll2mull == 0) RCC_Clocks->SYSCLK_Frequency = (RCC_Clocks->SYSCLK_Frequency * 5)>>1; + else if(Pll2mull == 1) RCC_Clocks->SYSCLK_Frequency = (RCC_Clocks->SYSCLK_Frequency * 25)>>1; + else if(Pll2mull == 15) RCC_Clocks->SYSCLK_Frequency = RCC_Clocks->SYSCLK_Frequency * 20; + else RCC_Clocks->SYSCLK_Frequency = RCC_Clocks->SYSCLK_Frequency * (Pll2mull + 2); + + RCC_Clocks->SYSCLK_Frequency = RCC_Clocks->SYSCLK_Frequency/((RCC->CFGR2 & 0xF) + 1); /* PREDIV1 */ + } + else{/* HSE */ + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE/((RCC->CFGR2 & 0xF) + 1); /* PREDIV1 */ + } + + RCC_Clocks->SYSCLK_Frequency = RCC_Clocks->SYSCLK_Frequency * pllmull; + +#endif + } + + if(Pll_6_5 == 1) + RCC_Clocks->SYSCLK_Frequency = (RCC_Clocks->SYSCLK_Frequency / 2); + + break; + + default: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + } + + tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_PPRE1_Set_Mask; + tmp = tmp >> 8; + presc = APBAHBPrescTable[tmp]; + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_PPRE2_Set_Mask; + tmp = tmp >> 11; + presc = APBAHBPrescTable[tmp]; + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask; + tmp = tmp >> 14; + presc = ADCPrescTable[tmp]; + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; +} + +/********************************************************************* + * @fn RCC_AHBPeriphClockCmd + * + * @brief Enables or disables the AHB peripheral clock. + * + * @param RCC_AHBPeriph - specifies the AHB peripheral to gates its clock. + * RCC_AHBPeriph_DMA1. + * RCC_AHBPeriph_DMA2. + * RCC_AHBPeriph_SRAM. + * RCC_AHBPeriph_CRC. + * RCC_AHBPeriph_FSMC + * RCC_AHBPeriph_RNG + * RCC_AHBPeriph_SDIO + * RCC_AHBPeriph_USBHS + * RCC_AHBPeriph_USBFS + * RCC_AHBPeriph_DVP + * RCC_AHBPeriph_ETH_MAC + * RCC_AHBPeriph_ETH_MAC_Tx + * RCC_AHBPeriph_ETH_MAC_Rx + * Note- + * SRAM clock can be disabled only during sleep mode. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->AHBPCENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBPCENR &= ~RCC_AHBPeriph; + } +} + +/********************************************************************* + * @fn RCC_APB2PeriphClockCmd + * + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * + * @param RCC_APB2Periph - specifies the APB2 peripheral to gates its clock. + * RCC_APB2Periph_AFIO. + * RCC_APB2Periph_GPIOA. + * RCC_APB2Periph_GPIOB. + * RCC_APB2Periph_GPIOC. + * RCC_APB2Periph_GPIOD. + * RCC_APB2Periph_GPIOE + * RCC_APB2Periph_ADC1. + * RCC_APB2Periph_ADC2 + * RCC_APB2Periph_TIM1. + * RCC_APB2Periph_SPI1. + * RCC_APB2Periph_TIM8 + * RCC_APB2Periph_USART1. + * RCC_APB2Periph_TIM9 + * RCC_APB2Periph_TIM10 + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB2PCENR |= RCC_APB2Periph; + } + else + { + RCC->APB2PCENR &= ~RCC_APB2Periph; + } +} + +/********************************************************************* + * @fn RCC_APB1PeriphClockCmd + * + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * + * @param RCC_APB1Periph - specifies the APB1 peripheral to gates its clock. + * RCC_APB1Periph_TIM2. + * RCC_APB1Periph_TIM3. + * RCC_APB1Periph_TIM4. + * RCC_APB1Periph_TIM5 + * RCC_APB1Periph_TIM6 + * RCC_APB1Periph_TIM7 + * RCC_APB1Periph_UART6 + * RCC_APB1Periph_UART7 + * RCC_APB1Periph_UART8 + * RCC_APB1Periph_WWDG. + * RCC_APB1Periph_SPI2. + * RCC_APB1Periph_SPI3. + * RCC_APB1Periph_USART2. + * RCC_APB1Periph_USART3. + * RCC_APB1Periph_UART4 + * RCC_APB1Periph_UART5 + * RCC_APB1Periph_I2C1. + * RCC_APB1Periph_I2C2. + * RCC_APB1Periph_USB. + * RCC_APB1Periph_CAN1. + * RCC_APB1Periph_BKP. + * RCC_APB1Periph_PWR. + * RCC_APB1Periph_DAC. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB1PCENR |= RCC_APB1Periph; + } + else + { + RCC->APB1PCENR &= ~RCC_APB1Periph; + } +} + +/********************************************************************* + * @fn RCC_APB2PeriphResetCmd + * + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * + * @param RCC_APB2Periph - specifies the APB2 peripheral to reset. + * RCC_APB2Periph_AFIO. + * RCC_APB2Periph_GPIOA. + * RCC_APB2Periph_GPIOB. + * RCC_APB2Periph_GPIOC. + * RCC_APB2Periph_GPIOD. + * RCC_APB2Periph_GPIOE + * RCC_APB2Periph_ADC1. + * RCC_APB2Periph_ADC2 + * RCC_APB2Periph_TIM1. + * RCC_APB2Periph_SPI1. + * RCC_APB2Periph_TIM8 + * RCC_APB2Periph_USART1. + * RCC_APB2Periph_TIM9 + * RCC_APB2Periph_TIM10 + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB2PRSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2PRSTR &= ~RCC_APB2Periph; + } +} + +/********************************************************************* + * @fn RCC_APB1PeriphResetCmd + * + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * + * @param RCC_APB1Periph - specifies the APB1 peripheral to reset. + * RCC_APB1Periph_TIM2. + * RCC_APB1Periph_TIM3. + * RCC_APB1Periph_TIM4. + * RCC_APB1Periph_TIM5 + * RCC_APB1Periph_TIM6 + * RCC_APB1Periph_TIM7 + * RCC_APB1Periph_UART6 + * RCC_APB1Periph_UART7 + * RCC_APB1Periph_UART8 + * RCC_APB1Periph_WWDG. + * RCC_APB1Periph_SPI2. + * RCC_APB1Periph_SPI3. + * RCC_APB1Periph_USART2. + * RCC_APB1Periph_USART3. + * RCC_APB1Periph_UART4 + * RCC_APB1Periph_UART5 + * RCC_APB1Periph_I2C1. + * RCC_APB1Periph_I2C2. + * RCC_APB1Periph_USB. + * RCC_APB1Periph_CAN1. + * RCC_APB1Periph_BKP. + * RCC_APB1Periph_PWR. + * RCC_APB1Periph_DAC. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB1PRSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1PRSTR &= ~RCC_APB1Periph; + } +} + +/********************************************************************* + * @fn RCC_BackupResetCmd + * + * @brief Forces or releases the Backup domain reset. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->BDCTLR |= (1 << 16); + } + else + { + RCC->BDCTLR &= ~(1 << 16); + } +} + +/********************************************************************* + * @fn RCC_ClockSecuritySystemCmd + * + * @brief Enables or disables the Clock Security System. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 19); + } + else + { + RCC->CTLR &= ~(1 << 19); + } +} + +/********************************************************************* + * @fn RCC_MCOConfig + * + * @brief Selects the clock source to output on MCO pin. + * + * @param RCC_MCO - specifies the clock source to output. + * RCC_MCO_NoClock - No clock selected. + * RCC_MCO_SYSCLK - System clock selected. + * RCC_MCO_HSI - HSI oscillator clock selected. + * RCC_MCO_HSE - HSE oscillator clock selected. + * RCC_MCO_PLLCLK_Div2 - PLL clock divided by 2 selected. + * RCC_MCO_PLL2CLK - PLL2 clock selected + * RCC_MCO_PLL3CLK_Div2 - PLL3 clock divided by 2 selected + * RCC_MCO_XT1 - External 3-25 MHz oscillator clock selected + * RCC_MCO_PLL3CLK - PLL3 clock selected + * + * @return none + */ +void RCC_MCOConfig(uint8_t RCC_MCO) +{ + *(__IO uint8_t *)CFGR0_BYTE4_ADDRESS = RCC_MCO; +} + +/********************************************************************* + * @fn RCC_GetFlagStatus + * + * @brief Checks whether the specified RCC flag is set or not. + * + * @param RCC_FLAG - specifies the flag to check. + * RCC_FLAG_HSIRDY - HSI oscillator clock ready. + * RCC_FLAG_HSERDY - HSE oscillator clock ready. + * RCC_FLAG_PLLRDY - PLL clock ready. + * RCC_FLAG_PLL2RDY - PLL2 clock ready. + * RCC_FLAG_PLL3RDY - PLL3 clock ready. + * RCC_FLAG_LSERDY - LSE oscillator clock ready. + * RCC_FLAG_LSIRDY - LSI oscillator clock ready. + * RCC_FLAG_PINRST - Pin reset. + * RCC_FLAG_PORRST - POR/PDR reset. + * RCC_FLAG_SFTRST - Software reset. + * RCC_FLAG_IWDGRST - Independent Watchdog reset. + * RCC_FLAG_WWDGRST - Window Watchdog reset. + * RCC_FLAG_LPWRRST - Low Power reset. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + + FlagStatus bitstatus = RESET; + tmp = RCC_FLAG >> 5; + + if(tmp == 1) + { + statusreg = RCC->CTLR; + } + else if(tmp == 2) + { + statusreg = RCC->BDCTLR; + } + else + { + statusreg = RCC->RSTSCKR; + } + + tmp = RCC_FLAG & FLAG_Mask; + + if((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearFlag + * + * @brief Clears the RCC reset flags. + * Note- + * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + * @return none + */ +void RCC_ClearFlag(void) +{ + RCC->RSTSCKR |= RSTSCKR_RMVF_Set; +} + +/********************************************************************* + * @fn RCC_GetITStatus + * + * @brief Checks whether the specified RCC interrupt has occurred or not. + * + * @param RCC_IT - specifies the RCC interrupt source to check. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_PLL2RDY - PLL2 ready interrupt. + * RCC_IT_PLL3RDY - PLL3 ready interrupt. + * RCC_IT_CSS - Clock Security System interrupt. + * + * @return ITStatus - SET or RESET. + */ + +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + + if((RCC->INTR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearITPendingBit + * + * @brief Clears the RCC's interrupt pending bits. + * + * @param RCC_IT - specifies the interrupt pending bit to clear. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_PLL2RDY - PLL2 ready interrupt. + * RCC_IT_PLL3RDY - PLL3 ready interrupt. + * RCC_IT_CSS - Clock Security System interrupt. + * + * @return none + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + *(__IO uint8_t *)INTR_BYTE3_ADDRESS = RCC_IT; +} + +/********************************************************************* + * @fn RCC_PREDIV1Config + * + * @brief Configures the PREDIV1 division factor. + * + * @param RCC_PREDIV1_Source - specifies the PREDIV1 clock source. + * RCC_PREDIV1_Source_HSE - HSE selected as PREDIV1 clock + * RCC_PREDIV1_Source_PLL2 - PLL2 selected as PREDIV1 clock + * RCC_PREDIV1_Div - specifies the PREDIV1 clock division factor. + * This parameter can be RCC_PREDIV1_Divx where x[1,16] + * Note- + * - This function must be used only when the PLL is disabled. + * + * @return none + */ +void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR2; + tmpreg &= ~(CFGR2_PREDIV1 | CFGR2_PREDIV1SRC); + tmpreg |= RCC_PREDIV1_Source | RCC_PREDIV1_Div; + RCC->CFGR2 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PREDIV2Config + * + * @brief Configures the PREDIV2 division factor. + * + * @param RCC_PREDIV2_Div - specifies the PREDIV2 clock division factor. + * This parameter can be RCC_PREDIV2_Divx where x:[1,16] + * Note- + * - This function must be used only when both PLL2 and PLL3 are disabled. + * + * @return none + */ +void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR2; + tmpreg &= ~CFGR2_PREDIV2; + tmpreg |= RCC_PREDIV2_Div; + RCC->CFGR2 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PLL2Config + * + * @brief Configures the PLL2 multiplication factor. + * + * @param RCC_PLL2Mul - specifies the PLL2 multiplication factor. + * This parameter can be RCC_PLL2Mul_x where x:{[4,16], 2.5, 12.5, 20} + * Note- + * - This function must be used only when the PLL2 is disabled. + * + * @return none + */ +void RCC_PLL2Config(uint32_t RCC_PLL2Mul) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR2; + tmpreg &= ~CFGR2_PLL2MUL; + tmpreg |= RCC_PLL2Mul; + RCC->CFGR2 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PLL2Cmd + * + * @brief Enables or disables the PLL2. + * + * @param NewState - new state of the PLL2. This parameter can be + * ENABLE or DISABLE. + * Note- + * - The PLL2 can not be disabled if it is used indirectly as system clock + * (i.e. it is used as PLL clock entry that is used as System clock). + * + * @return none + */ +void RCC_PLL2Cmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 26); + } + else + { + RCC->CTLR &= ~(1 << 26); + } +} + +/********************************************************************* + * @fn RCC_PLL3Config + * + * @brief Configures the PLL3 multiplication factor. + * + * @param RCC_PLL3Mul - specifies the PLL3 multiplication factor. + * This parameter can be RCC_PLL3Mul_x where x:{[4,16], 2.5, 12.5, 20} + * Note- + * - This function must be used only when the PLL3 is disabled. + * + * @return none + */ +void RCC_PLL3Config(uint32_t RCC_PLL3Mul) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR2; + tmpreg &= ~CFGR2_PLL3MUL; + tmpreg |= RCC_PLL3Mul; + RCC->CFGR2 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PLL3Cmd + * + * @brief Enables or disables the PLL3. + * + * @param NewState - new state of the PLL2. This parameter can be + * ENABLE or DISABLE. + * + * @return none + */ +void RCC_PLL3Cmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 28); + } + else + { + RCC->CTLR &= ~(1 << 28); + } +} + +/********************************************************************* + * @fn RCC_USBFSCLKConfig + * + * @brief Configures the USB OTG FS clock (USBFSCLK). + * + * @param RCC_USBFSCLKSource - specifies the USB OTG FS clock source. + * RCC_USBFSCLKSource_PLLCLK_Div1 - PLL clock divided by 1 + * selected as USB OTG FS clock source + * RCC_USBFSCLKSource_PLLCLK_Div2 - PLL clock divided by 2 + * selected as USB OTG FS clock source + * RCC_USBFSCLKSource_PLLCLK_Div3 - PLL clock divided by 3 + * selected as USB OTG FS clock source + * + * @return none + */ +void RCC_USBFSCLKConfig(uint32_t RCC_USBFSCLKSource) +{ + RCC->CFGR0 &= ~(3 << 22); + RCC->CFGR0 |= RCC_USBFSCLKSource << 22; +} + +/********************************************************************* + * @fn RCC_I2S2CLKConfig + * + * @brief Configures the I2S2 clock source(I2S2CLK). + * + * @param RCC_I2S2CLKSource - specifies the I2S2 clock source. + * RCC_I2S2CLKSource_SYSCLK - system clock selected as I2S2 clock entry + * RCC_I2S2CLKSource_PLL3_VCO - PLL3 VCO clock selected as I2S2 clock entry + * Note- + * - This function must be called before enabling I2S2 APB clock. + * @return none + */ +void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource) +{ + RCC->CFGR2 &= ~(1 << 17); + RCC->CFGR2 |= RCC_I2S2CLKSource << 17; +} + +/********************************************************************* + * @fn RCC_I2S3CLKConfig + * + * @brief Configures the I2S3 clock source(I2S2CLK). + * + * @param RCC_I2S3CLKSource - specifies the I2S3 clock source. + * RCC_I2S3CLKSource_SYSCLK - system clock selected as I2S3 clock entry + * RCC_I2S3CLKSource_PLL3_VCO - PLL3 VCO clock selected as I2S3 clock entry + * Note- + * - This function must be called before enabling I2S3 APB clock. + * @return none + */ +void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource) +{ + RCC->CFGR2 &= ~(1 << 18); + RCC->CFGR2 |= RCC_I2S3CLKSource << 18; +} + +/********************************************************************* + * @fn RCC_AHBPeriphResetCmd + * + * @brief Forces or releases AHB peripheral reset. + * + * @param RCC_AHBPeriph - specifies the AHB peripheral to reset. + * RCC_AHBPeriph_USBFS + * RCC_AHBPeriph_ETH_MAC + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->AHBRSTR |= RCC_AHBPeriph; + } + else + { + RCC->AHBRSTR &= ~RCC_AHBPeriph; + } +} + +/********************************************************************* + * @fn RCC_ADCCLKADJcmd + * + * @brief Enable ADC clock duty cycle adjustment. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ADCCLKADJcmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->CFGR0 |= (1 << 31); + } + else + { + RCC->CFGR0 &= ~(1 << 31); + } +} + +/********************************************************************* + * @fn RCC_RNGCLKConfig + * + * @brief Configures the RNG clock source. + * + * @param RCC_RNGCLKSource - specifies the RNG clock source. + * RCC_RNGCLKSource_SYSCLK - system clock selected as RNG clock entry + * RCC_RNGCLKSource_PLL3_VCO - PLL3 VCO clock selected as RNG clock entry + * + * @return none + */ +void RCC_RNGCLKConfig(uint32_t RCC_RNGCLKSource) +{ + RCC->CFGR2 &= ~(1 << 19); + RCC->CFGR2 |= RCC_RNGCLKSource << 19; +} + +/********************************************************************* + * @fn RCC_ETH1GCLKConfig + * + * @brief Configures the ETH1G clock source. + * + * @param RCC_RNGCLKSource - specifies the ETH1G clock source. + * RCC_ETH1GCLKSource_PLL2_VCO - system clock selected as ETH1G clock entry + * RCC_ETH1GCLKSource_PLL3_VCO - PLL3 VCO clock selected as ETH1G clock entry + * RCC_ETH1GCLKSource_PB1_IN - GPIO PB1 input clock selected as ETH1G clock entry + * + * @return none + */ +void RCC_ETH1GCLKConfig(uint32_t RCC_ETH1GCLKSource) +{ + RCC->CFGR2 &= ~(3 << 20); + RCC->CFGR2 |= RCC_ETH1GCLKSource << 20; +} + +/********************************************************************* + * @fn RCC_ETH1G_125Mcmd + * + * @brief Enable ETH1G 125M. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ETH1G_125Mcmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->CFGR2 |= (1 << 22); + } + else + { + RCC->CFGR2 &= ~(1 << 22); + } +} + +/********************************************************************* + * @fn RCC_USBHSConfig + * + * @brief Configures the USBHS clock. + * + * @param RCC_USBHS - defines the USBHS clock divider. + * RCC_USBPLL_Div1 - USBHS clock = USBPLL. + * RCC_USBPLL_Div2 - USBHS clock = USBPLL/2. + * RCC_USBPLL_Div3 - USBHS clock = USBPLL/3. + * RCC_USBPLL_Div4 - USBHS clock = USBPLL/4. + * RCC_USBPLL_Div5 - USBHS clock = USBPLL/5. + * RCC_USBPLL_Div6 - USBHS clock = USBPLL/6. + * RCC_USBPLL_Div7 - USBHS clock = USBPLL/7. + * RCC_USBPLL_Div8 - USBHS clock = USBPLL/8. + * + * @return none + */ +void RCC_USBHSConfig(uint32_t RCC_USBHS) +{ + RCC->CFGR2 &= ~(7 << 24); + RCC->CFGR2 |= RCC_USBHS << 24; +} + +/********************************************************************* + * @fn RCC_USBHSPLLCLKConfig + * + * @brief Configures the USBHSPLL clock source. + * + * @param RCC_HSBHSPLLCLKSource - specifies the USBHSPLL clock source. + * RCC_HSBHSPLLCLKSource_HSE - HSE clock selected as USBHSPLL clock entry + * RCC_HSBHSPLLCLKSource_HSI - HSI clock selected as USBHSPLL clock entry + * + * @return none + */ +void RCC_USBHSPLLCLKConfig(uint32_t RCC_USBHSPLLCLKSource) +{ + RCC->CFGR2 &= ~(1 << 27); + RCC->CFGR2 |= RCC_USBHSPLLCLKSource << 27; +} + +/********************************************************************* + * @fn RCC_USBHSPLLCKREFCLKConfig + * + * @brief Configures the USBHSPLL reference clock. + * + * @param RCC_USBHSPLLCKREFCLKSource - Select reference clock. + * RCC_USBHSPLLCKREFCLK_3M - reference clock 3Mhz. + * RCC_USBHSPLLCKREFCLK_4M - reference clock 4Mhz. + * RCC_USBHSPLLCKREFCLK_8M - reference clock 8Mhz. + * RCC_USBHSPLLCKREFCLK_5M - reference clock 5Mhz. + * + * @return none + */ +void RCC_USBHSPLLCKREFCLKConfig(uint32_t RCC_USBHSPLLCKREFCLKSource) +{ + RCC->CFGR2 &= ~(3 << 28); + RCC->CFGR2 |= RCC_USBHSPLLCKREFCLKSource << 28; +} + +/********************************************************************* + * @fn RCC_USBHSPHYPLLALIVEcmd + * + * @brief Enable USBHS PHY control. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_USBHSPHYPLLALIVEcmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->CFGR2 |= (1 << 30); + } + else + { + RCC->CFGR2 &= ~(1 << 30); + } +} + +/********************************************************************* + * @fn RCC_USBCLK48MConfig + * + * @brief Configures the USB clock 48MHz source. + * + * @param RCC_USBCLK48MSource - specifies the USB clock 48MHz source. + * RCC_USBCLK48MCLKSource_PLLCLK - PLLCLK clock selected as USB clock 48MHz clock entry + * RCC_USBCLK48MCLKSource_USBPHY - USBPHY clock selected as USB clock 48MHz clock entry + * + * @return none + */ +void RCC_USBCLK48MConfig(uint32_t RCC_USBCLK48MSource) +{ + RCC->CFGR2 &= ~(1 << 31); + RCC->CFGR2 |= RCC_USBCLK48MSource << 31; +} diff --git a/Peripheral/src/ch32v30x_rng.c b/Peripheral/src/ch32v30x_rng.c new file mode 100644 index 0000000..faea0ab --- /dev/null +++ b/Peripheral/src/ch32v30x_rng.c @@ -0,0 +1,154 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_rng.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the RNG firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_rng.h" +#include "ch32v30x_rcc.h" + +/********************************************************************* + * @fn RNG_Cmd + * + * @brief Enables or disables the RNG peripheral. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RNG_Cmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RNG->CR |= RNG_CR_RNGEN; + } + else + { + RNG->CR &= ~RNG_CR_RNGEN; + } +} + +/********************************************************************* + * @fn RNG_GetRandomNumber + * + * @brief Returns a 32-bit random number. + * + * @return 32-bit random number. + */ +uint32_t RNG_GetRandomNumber(void) +{ + return RNG->DR; +} + +/********************************************************************* + * @fn RNG_ITConfig + * + * @brief Enables or disables the RNG interrupt. + * + * @param NewState - ENABLE or DISABLE. + * + * @return 32-bit random number. + */ +void RNG_ITConfig(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RNG->CR |= RNG_CR_IE; + } + else + { + RNG->CR &= ~RNG_CR_IE; + } +} + +/********************************************************************* + * @fn RNG_GetFlagStatus + * + * @brief Checks whether the specified RNG flag is set or not. + * + * @param RNG_FLAG - specifies the RNG flag to check. + * RNG_FLAG_DRDY - Data Ready flag. + * RNG_FLAG_CECS - Clock Error Current flag. + * RNG_FLAG_SECS - Seed Error Current flag. + * + * @return 32-bit random number. + */ +FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((RNG->SR & RNG_FLAG) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RNG_ClearFlag + * + * @brief Clears the RNG flags. + * + * @param RNG_FLAG - specifies the flag to clear. + * RNG_FLAG_CECS - Clock Error Current flag. + * RNG_FLAG_SECS - Seed Error Current flag. + * + * @return 32-bit random number. + */ +void RNG_ClearFlag(uint8_t RNG_FLAG) +{ + RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4); +} + +/********************************************************************* + * @fn RNG_GetFlagStatus + * + * @brief Checks whether the specified RNG interrupt has occurred or not. + * + * @param RNG_IT - specifies the RNG interrupt source to check. + * RNG_IT_CEI - Clock Error Interrupt. + * RNG_IT_SEI - Seed Error Interrupt. + * + * @return bitstatus:SET or RESET. + */ +ITStatus RNG_GetITStatus(uint8_t RNG_IT) +{ + ITStatus bitstatus = RESET; + + if((RNG->SR & RNG_IT) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RNG_ClearITPendingBit + * + * @brief Clears the RNG interrupt pending bit(s). + * + * @param RNG_IT - specifies the RNG interrupt pending bit(s) to clear. + * RNG_IT_CEI - Clock Error Interrupt. + * RNG_IT_SEI - Seed Error Interrupt. + * + * @return None + */ +void RNG_ClearITPendingBit(uint8_t RNG_IT) +{ + RNG->SR = (uint8_t)~RNG_IT; +} diff --git a/Peripheral/src/ch32v30x_rtc.c b/Peripheral/src/ch32v30x_rtc.c new file mode 100644 index 0000000..0f9ba6d --- /dev/null +++ b/Peripheral/src/ch32v30x_rtc.c @@ -0,0 +1,315 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_rtc.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the RTC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_rtc.h" + +/* RTC_Private_Defines */ +#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /* RTC LSB Mask */ +#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */ + +/********************************************************************* + * @fn RTC_ITConfig + * + * @brief Enables or disables the specified RTC interrupts. + * + * @param RTC_IT - specifies the RTC interrupts sources to be enabled or disabled. + * RTC_IT_OW - Overflow interrupt + * RTC_IT_ALR - Alarm interrupt + * RTC_IT_SEC - Second interrupt + * + * @return NewState - new state of the specified RTC interrupts(ENABLE or DISABLE). + */ +void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RTC->CTLRH |= RTC_IT; + } + else + { + RTC->CTLRH &= (uint16_t)~RTC_IT; + } +} + +/********************************************************************* + * @fn RTC_EnterConfigMode + * + * @brief Enters the RTC configuration mode. + * + * @return none + */ +void RTC_EnterConfigMode(void) +{ + RTC->CTLRL |= RTC_CTLRL_CNF; +} + +/********************************************************************* + * @fn RTC_ExitConfigMode + * + * @brief Exits from the RTC configuration mode. + * + * @return none + */ +void RTC_ExitConfigMode(void) +{ + RTC->CTLRL &= (uint16_t) ~((uint16_t)RTC_CTLRL_CNF); +} + +/********************************************************************* + * @fn RTC_GetCounter + * + * @brief Gets the RTC counter value + * + * @return RTC counter value + */ +uint32_t RTC_GetCounter(void) +{ + uint16_t high1a = 0, high1b = 0, high2a = 0, high2b = 0; + uint16_t low1 = 0, low2 = 0; + + do{ + high1a = RTC->CNTH; + high1b = RTC->CNTH; + }while( high1a != high1b ); + + do{ + low1 = RTC->CNTL; + low2 = RTC->CNTL; + }while( low1 != low2 ); + + do{ + high2a = RTC->CNTH; + high2b = RTC->CNTH; + }while( high2a != high2b ); + + if(high1b != high2b) + { + do{ + low1 = RTC->CNTL; + low2 = RTC->CNTL; + }while( low1 != low2 ); + } + + return (((uint32_t)high2b << 16) | low2); +} + +/********************************************************************* + * @fn RTC_SetCounter + * + * @brief Sets the RTC counter value. + * + * @param CounterValue - RTC counter new value. + * + * @return RTC counter value + */ +void RTC_SetCounter(uint32_t CounterValue) +{ + RTC_EnterConfigMode(); + RTC->CNTH = CounterValue >> 16; + RTC->CNTL = (CounterValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_SetPrescaler + * + * @brief Sets the RTC prescaler value + * + * @param PrescalerValue - RTC prescaler new value + * + * @return none + */ +void RTC_SetPrescaler(uint32_t PrescalerValue) +{ + RTC_EnterConfigMode(); + RTC->PSCRH = (PrescalerValue & PRLH_MSB_MASK) >> 16; + RTC->PSCRL = (PrescalerValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_SetAlarm + * + * @brief Sets the RTC alarm value + * + * @param AlarmValue - RTC alarm new value + * + * @return none + */ +void RTC_SetAlarm(uint32_t AlarmValue) +{ + RTC_EnterConfigMode(); + RTC->ALRMH = AlarmValue >> 16; + RTC->ALRML = (AlarmValue & RTC_LSB_MASK); + RTC_ExitConfigMode(); +} + +/********************************************************************* + * @fn RTC_GetDivider + * + * @brief Gets the RTC divider value + * + * @return RTC Divider value + */ +uint32_t RTC_GetDivider(void) +{ + uint16_t high1a = 0, high1b = 0, high2a = 0, high2b = 0; + uint16_t low1 = 0, low2 = 0; + + do{ + high1a = RTC->DIVH; + high1b = RTC->DIVH; + }while( high1a != high1b ); + + do{ + low1 = RTC->DIVL; + low2 = RTC->DIVL; + }while( low1 != low2 ); + + do{ + high2a = RTC->DIVH; + high2b = RTC->DIVH; + }while( high2a != high2b ); + + if(high1b != high2b) + { + do{ + low1 = RTC->DIVL; + low2 = RTC->DIVL; + }while( low1 != low2 ); + } + + return ((((uint32_t)high2b & (uint32_t)0x000F) << 16) | low2); +} + +/********************************************************************* + * @fn RTC_WaitForLastTask + * + * @brief Waits until last write operation on RTC registers has finished + * Note- + * This function must be called before any write to RTC registers. + * @return none + */ +void RTC_WaitForLastTask(void) +{ + while((RTC->CTLRL & RTC_FLAG_RTOFF) == (uint16_t)RESET) + { + } +} + +/********************************************************************* + * @fn RTC_WaitForSynchro + * + * @brief Waits until the RTC registers are synchronized with RTC APB clock + * Note- + * This function must be called before any read operation after an APB reset + * or an APB clock stop. + * + * @return none + */ +void RTC_WaitForSynchro(void) +{ + RTC->CTLRL &= (uint16_t)~RTC_FLAG_RSF; + while((RTC->CTLRL & RTC_FLAG_RSF) == (uint16_t)RESET) + { + } +} + +/********************************************************************* + * @fn RTC_GetFlagStatus + * + * @brief Checks whether the specified RTC flag is set or not + * + * @param RTC_FLAG- specifies the flag to check + * RTC_FLAG_RTOFF - RTC Operation OFF flag + * RTC_FLAG_RSF - Registers Synchronized flag + * RTC_FLAG_OW - Overflow flag + * RTC_FLAG_ALR - Alarm flag + * RTC_FLAG_SEC - Second flag + * + * @return The new state of RTC_FLAG (SET or RESET) + */ +FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG) +{ + FlagStatus bitstatus = RESET; + if((RTC->CTLRL & RTC_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn RTC_ClearFlag + * + * @brief Clears the RTC's pending flags + * + * @param RTC_FLAG - specifies the flag to clear + * RTC_FLAG_RSF - Registers Synchronized flag + * RTC_FLAG_OW - Overflow flag + * RTC_FLAG_ALR - Alarm flag + * RTC_FLAG_SEC - Second flag + * + * @return none + */ +void RTC_ClearFlag(uint16_t RTC_FLAG) +{ + RTC->CTLRL &= (uint16_t)~RTC_FLAG; +} + +/********************************************************************* + * @fn RTC_GetITStatus + * + * @brief Checks whether the specified RTC interrupt has occurred or not + * + * @param RTC_IT - specifies the RTC interrupts sources to check + * RTC_FLAG_OW - Overflow interrupt + * RTC_FLAG_ALR - Alarm interrupt + * RTC_FLAG_SEC - Second interrupt + * + * @return The new state of the RTC_IT (SET or RESET) + */ +ITStatus RTC_GetITStatus(uint16_t RTC_IT) +{ + ITStatus bitstatus = RESET; + + bitstatus = (ITStatus)(RTC->CTLRL & RTC_IT); + if(((RTC->CTLRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn RTC_ClearITPendingBit + * + * @brief Clears the RTC's interrupt pending bits + * + * @param RTC_IT - specifies the interrupt pending bit to clear + * RTC_FLAG_OW - Overflow interrupt + * RTC_FLAG_ALR - Alarm interrupt + * RTC_FLAG_SEC - Second interrupt + * + * @return none + */ +void RTC_ClearITPendingBit(uint16_t RTC_IT) +{ + RTC->CTLRL &= (uint16_t)~RTC_IT; +} diff --git a/Peripheral/src/ch32v30x_sdio.c b/Peripheral/src/ch32v30x_sdio.c new file mode 100644 index 0000000..ae54bb1 --- /dev/null +++ b/Peripheral/src/ch32v30x_sdio.c @@ -0,0 +1,672 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_SDIO.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the SDIO firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_sdio.h" +#include "ch32v30x_rcc.h" + +#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) + +/* CLKCR register clear mask */ +#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) + +/* SDIO PWRCTRL Mask */ +#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) + +/* SDIO DCTRL Clear Mask */ +#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) + +/* CMD Register clear mask */ +#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) + +/* SDIO RESP Registers Address */ +#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) + +/********************************************************************* + * @fn SDIO_DeInit + * + * @brief Deinitializes the SDIO peripheral registers to their default + * reset values. + * + * @return RTC counter value + */ +void SDIO_DeInit(void) +{ + SDIO->POWER = 0x00000000; + SDIO->CLKCR = 0x00000000; + SDIO->ARG = 0x00000000; + SDIO->CMD = 0x00000000; + SDIO->DTIMER = 0x00000000; + SDIO->DLEN = 0x00000000; + SDIO->DCTRL = 0x00000000; + SDIO->ICR = 0x00C007FF; + SDIO->MASK = 0x00000000; +} + +/********************************************************************* + * @fn SDIO_Init + * + * @brief Initializes the SDIO peripheral according to the specified + * parameters in the SDIO_InitStruct. + * + * @param SDIO_InitStruct - pointer to a SDIO_InitTypeDef structure + * that contains the configuration information for the SDIO peripheral. + * + * @return None + */ +void SDIO_Init(SDIO_InitTypeDef *SDIO_InitStruct) +{ + uint32_t tmpreg = 0; + + tmpreg = SDIO->CLKCR; + tmpreg &= CLKCR_CLEAR_MASK; + tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave | + SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide | + SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); + + SDIO->CLKCR = tmpreg; +} + +/********************************************************************* + * @fn SDIO_StructInit + * + * @brief Fills each SDIO_InitStruct member with its default value. + * + * @param SDIO_InitStruct - pointer to an SDIO_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void SDIO_StructInit(SDIO_InitTypeDef *SDIO_InitStruct) +{ + SDIO_InitStruct->SDIO_ClockDiv = 0x00; + SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising; + SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable; + SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable; + SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b; + SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable; +} + +/********************************************************************* + * @fn SDIO_ClockCmd + * + * @brief Enables or disables the SDIO Clock. + * + * @param SDIO_InitStruct - pointer to an SDIO_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void SDIO_ClockCmd(FunctionalState NewState) +{ + if(NewState) + SDIO->CLKCR |= (1 << 8); + else + SDIO->CLKCR &= ~(1 << 8); +} + +/********************************************************************* + * @fn SDIO_SetPowerState + * + * @brief Sets the power status of the controller. + * + * @param SDIO_PowerState - new state of the Power state. + * SDIO_PowerState_OFF + * SDIO_PowerState_ON + * + * @return none + */ +void SDIO_SetPowerState(uint32_t SDIO_PowerState) +{ + SDIO->POWER &= PWR_PWRCTRL_MASK; + SDIO->POWER |= SDIO_PowerState; +} + +/********************************************************************* + * @fn SDIO_GetPowerState + * + * @brief Gets the power status of the controller. + * + * @param CounterValue - RTC counter new value. + * + * @return power state - + * 0x00 - Power OFF + * 0x02 - Power UP + * 0x03 - Power ON + */ +uint32_t SDIO_GetPowerState(void) +{ + return (SDIO->POWER & (~PWR_PWRCTRL_MASK)); +} + +/********************************************************************* + * @fn SDIO_ITConfig + * + * @brief Enables or disables the SDIO interrupts. + * + * @param DIO_IT - specifies the SDIO interrupt sources to be enabled or disabled. + * SDIO_IT_CCRCFAIL + * SDIO_IT_DCRCFAIL + * SDIO_IT_CTIMEOUT + * SDIO_IT_DTIMEOUT + * SDIO_IT_TXUNDERR + * SDIO_IT_RXOVERR + * SDIO_IT_CMDREND + * SDIO_IT_CMDSENT + * SDIO_IT_DATAEND + * SDIO_IT_STBITERR + * SDIO_IT_DBCKEND + * SDIO_IT_CMDACT + * SDIO_IT_TXACT + * SDIO_IT_RXACT + * SDIO_IT_TXFIFOHE + * SDIO_IT_RXFIFOHF + * SDIO_IT_TXFIFOF + * SDIO_IT_RXFIFOF + * SDIO_IT_TXFIFOE + * SDIO_IT_RXFIFOE + * SDIO_IT_TXDAVL + * SDIO_IT_RXDAVL + * SDIO_IT_SDIOIT + * SDIO_IT_CEATAEND + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SDIO->MASK |= SDIO_IT; + } + else + { + SDIO->MASK &= ~SDIO_IT; + } +} + +/********************************************************************* + * @fn SDIO_DMACmd + * + * @brief Enables or disables the SDIO DMA request. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_DMACmd(FunctionalState NewState) +{ + if(NewState) + SDIO->DCTRL |= (1 << 3); + else + SDIO->DCTRL &= ~(1 << 3); +} + +/********************************************************************* + * @fn SDIO_SendCommand + * + * @brief Initializes the SDIO Command according to the specified + * parameters in the SDIO_CmdInitStruct and send the command. + * @param SDIO_CmdInitStruct - pointer to a SDIO_CmdInitTypeDef + * structure that contains the configuration information for + * ddthe SDIO command. + * + * @return none + */ +void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) +{ + uint32_t tmpreg = 0; + + SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument; + + tmpreg = SDIO->CMD; + tmpreg &= CMD_CLEAR_MASK; + tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM; + + SDIO->CMD = tmpreg; +} + +/********************************************************************* + * @fn SDIO_CmdStructInit + * + * @brief Fills each SDIO_CmdInitStruct member with its default value. + * + * @param SDIO_CmdInitStruct - pointer to an SDIO_CmdInitTypeDef + * structure which will be initialized. + * + * @return none + */ +void SDIO_CmdStructInit(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct) +{ + SDIO_CmdInitStruct->SDIO_Argument = 0x00; + SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00; + SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No; + SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No; + SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable; +} + +/********************************************************************* + * @fn SDIO_GetCommandResponse + * + * @brief Returns command index of last command for which response received. + * + * @return Returns the command index of the last command response received. + */ +uint8_t SDIO_GetCommandResponse(void) +{ + return (uint8_t)(SDIO->RESPCMD); +} + +/********************************************************************* + * @fn SDIO_GetResponse + * + * @brief Returns response received from the card for the last command. + * + * @param SDIO_RESP - Specifies the SDIO response register. + * SDIO_RESP1 - Response Register 1 + * SDIO_RESP2 - Response Register 2 + * SDIO_RESP3 - Response Register 3 + * SDIO_RESP4 - Response Register 4 + * + * @return Returns the command index of the last command response received. + */ +uint32_t SDIO_GetResponse(uint32_t SDIO_RESP) +{ + __IO uint32_t tmp = 0; + + tmp = SDIO_RESP_ADDR + SDIO_RESP; + + return (*(__IO uint32_t *)tmp); +} + +/********************************************************************* + * @fn SDIO_DataConfig + * + * @brief Initializes the SDIO data path according to the specified + * + * @param SDIO_DataInitStruct - pointer to a SDIO_DataInitTypeDef structure that + * contains the configuration information for the SDIO command. + * + * @return none + */ +void SDIO_DataConfig(SDIO_DataInitTypeDef *SDIO_DataInitStruct) +{ + uint32_t tmpreg = 0; + + SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut; + SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength; + tmpreg = SDIO->DCTRL; + tmpreg &= DCTRL_CLEAR_MASK; + tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM; + + SDIO->DCTRL = tmpreg; +} + +/********************************************************************* + * @fn SDIO_DataStructInit + * + * @brief Fills each SDIO_DataInitStruct member with its default value. + * + * @param SDIO_DataInitStruct - pointer to an SDIO_DataInitTypeDef + * structure which will be initialized. + * + * @return RTC counter value + */ +void SDIO_DataStructInit(SDIO_DataInitTypeDef *SDIO_DataInitStruct) +{ + SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF; + SDIO_DataInitStruct->SDIO_DataLength = 0x00; + SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b; + SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard; + SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block; + SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable; +} + +/********************************************************************* + * @fn SDIO_GetDataCounter + * + * @brief Returns number of remaining data bytes to be transferred. + * + * @return Number of remaining data bytes to be transferred + */ +uint32_t SDIO_GetDataCounter(void) +{ + return SDIO->DCOUNT; +} + +/********************************************************************* + * @fn SDIO_ReadData + * + * @brief Read one data word from Rx FIFO. + * + * @return Data received + */ +uint32_t SDIO_ReadData(void) +{ + return SDIO->FIFO; +} + +/********************************************************************* + * @fn SDIO_WriteData + * + * @brief Write one data word to Tx FIFO. + * + * @param Data - 32-bit data word to write. + * + * @return RTC counter value + */ +void SDIO_WriteData(uint32_t Data) +{ + SDIO->FIFO = Data; +} + +/********************************************************************* + * @fn SDIO_GetFIFOCount + * + * @brief Returns the number of words left to be written to or read from FIFO. + * + * @return Remaining number of words. + */ +uint32_t SDIO_GetFIFOCount(void) +{ + return SDIO->FIFOCNT; +} + +/********************************************************************* + * @fn SDIO_StartSDIOReadWait + * + * @brief Starts the SD I/O Read Wait operation. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_StartSDIOReadWait(FunctionalState NewState) +{ + if(NewState) + SDIO->DCTRL |= (1 << 8); + else + SDIO->DCTRL &= ~(1 << 8); +} + +/********************************************************************* + * @fn SDIO_StopSDIOReadWait + * + * @brief Stops the SD I/O Read Wait operation. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_StopSDIOReadWait(FunctionalState NewState) +{ + if(NewState) + SDIO->DCTRL |= (1 << 9); + else + SDIO->DCTRL &= ~(1 << 9); +} + +/********************************************************************* + * @fn SDIO_SetSDIOReadWaitMode + * + * @brief Sets one of the two options of inserting read wait interval. + * + * @param SDIO_ReadWaitMode - SD I/O Read Wait operation mode. + * SDIO_ReadWaitMode_CLK - Read Wait control by stopping SDIOCLK + * SDIO_ReadWaitMode_DATA2 - Read Wait control using SDIO_DATA2 + * + * @return none + */ +void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode) +{ + if(SDIO_ReadWaitMode) + SDIO->DCTRL |= (1 << 10); + else + SDIO->DCTRL &= ~(1 << 10); +} + +/********************************************************************* + * @fn SDIO_SetSDIOOperation + * + * @brief Enables or disables the SD I/O Mode Operation. + * + * @param NewState: ENABLE or DISABLE. + * + * @return none + */ +void SDIO_SetSDIOOperation(FunctionalState NewState) +{ + if(NewState) + SDIO->DCTRL |= (1 << 11); + else + SDIO->DCTRL &= ~(1 << 11); +} + +/********************************************************************* + * @fn SDIO_SendSDIOSuspendCmd + * + * @brief Enables or disables the SD I/O Mode suspend command sending. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_SendSDIOSuspendCmd(FunctionalState NewState) +{ + if(NewState) + SDIO->CMD |= (1 << 11); + else + SDIO->CMD &= ~(1 << 11); +} + +/********************************************************************* + * @fn SDIO_CommandCompletionCmd + * + * @brief Enables or disables the command completion signal. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_CommandCompletionCmd(FunctionalState NewState) +{ + if(NewState) + SDIO->CMD |= (1 << 12); + else + SDIO->CMD &= ~(1 << 12); +} + +/********************************************************************* + * @fn SDIO_CEATAITCmd + * + * @brief Enables or disables the CE-ATA interrupt. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void SDIO_CEATAITCmd(FunctionalState NewState) +{ + if(NewState) + SDIO->CMD |= (1 << 13); + else + SDIO->CMD &= ~(1 << 13); +} + +/********************************************************************* + * @fn SDIO_SendCEATACmd + * + * @brief Sends CE-ATA command (CMD61). + * + * @param NewState - ENABLE or DISABLE. + * + * @return RTC counter value + */ +void SDIO_SendCEATACmd(FunctionalState NewState) +{ + if(NewState) + SDIO->CMD |= (1 << 14); + else + SDIO->CMD &= ~(1 << 14); +} + +/********************************************************************* + * @fn SDIO_GetFlagStatus + * + * @brief Checks whether the specified SDIO flag is set or not. + * + * @param SDIO_FLAG - specifies the flag to check. + * SDIO_FLAG_CCRCFAIL - Command response received (CRC check failed) + * SDIO_FLAG_DCRCFAIL - Data block sent/received (CRC check failed) + * SDIO_FLAG_CTIMEOUT - Command response timeout + * SDIO_FLAG_DTIMEOUT - Data timeout + * SDIO_FLAG_TXUNDERR - Transmit FIFO underrun error + * SDIO_FLAG_RXOVERR - Received FIFO overrun error + * SDIO_FLAG_CMDREND - Command response received (CRC check passed) + * SDIO_FLAG_CMDSENT - Command sent (no response required) + * SDIO_FLAG_DATAEND - Data end (data counter, SDIDCOUNT, is zero) + * SDIO_FLAG_STBITERR - Start bit not detected on all data signals + * in wide bus mode. + * SDIO_FLAG_DBCKEND - Data block sent/received (CRC check passed) + * SDIO_FLAG_CMDACT - Command transfer in progress + * SDIO_FLAG_TXACT - Data transmit in progress + * SDIO_FLAG_RXACT - Data receive in progress + * SDIO_FLAG_TXFIFOHE - Transmit FIFO Half Empty + * SDIO_FLAG_RXFIFOHF - Receive FIFO Half Full + * SDIO_FLAG_TXFIFOF - Transmit FIFO full + * SDIO_FLAG_RXFIFOF - Receive FIFO full + * SDIO_FLAG_TXFIFOE - Transmit FIFO empty + * SDIO_FLAG_RXFIFOE - Receive FIFO empty + * SDIO_FLAG_TXDAVL - Data available in transmit FIFO + * SDIO_FLAG_RXDAVL - Data available in receive FIFO + * SDIO_FLAG_SDIOIT - SD I/O interrupt received + * SDIO_FLAG_CEATAEND - CE-ATA command completion signal received + * for CMD61 + * + * @return ITStatus - SET or RESET + */ +FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn SDIO_ClearFlag + * + * @brief Clears the SDIO's pending flags. + * + * @param SDIO_FLAG - specifies the flag to clear. + * SDIO_FLAG_CCRCFAIL - Command response received (CRC check failed) + * SDIO_FLAG_DCRCFAIL - Data block sent/received (CRC check failed) + * SDIO_FLAG_CTIMEOUT - Command response timeout + * SDIO_FLAG_DTIMEOUT - Data timeout + * SDIO_FLAG_TXUNDERR - Transmit FIFO underrun error + * SDIO_FLAG_RXOVERR - Received FIFO overrun error + * SDIO_FLAG_CMDREND - Command response received (CRC check passed) + * SDIO_FLAG_CMDSENT - Command sent (no response required) + * SDIO_FLAG_DATAEND - Data end (data counter, SDIDCOUNT, is zero) + * SDIO_FLAG_STBITERR - Start bit not detected on all data signals + * in wide bus mode + * SDIO_FLAG_DBCKEND - Data block sent/received (CRC check passed) + * SDIO_FLAG_SDIOIT - SD I/O interrupt received + * SDIO_FLAG_CEATAEND - CE-ATA command completion signal received for CMD61 + * + * @return none + */ +void SDIO_ClearFlag(uint32_t SDIO_FLAG) +{ + SDIO->ICR = SDIO_FLAG; +} + +/********************************************************************* + * @fn SDIO_GetITStatus + * + * @brief Checks whether the specified SDIO interrupt has occurred or not. + * + * @param SDIO_IT: specifies the SDIO interrupt source to check. + * SDIO_IT_CCRCFAIL - Command response received (CRC check failed) interrupt + * SDIO_IT_DCRCFAIL - Data block sent/received (CRC check failed) interrupt + * SDIO_IT_CTIMEOUT - Command response timeout interrupt + * SDIO_IT_DTIMEOUT - Data timeout interrupt + * SDIO_IT_TXUNDERR - Transmit FIFO underrun error interrupt + * SDIO_IT_RXOVERR - Received FIFO overrun error interrupt + * SDIO_IT_CMDREND - Command response received (CRC check passed) interrupt + * SDIO_IT_CMDSENT - Command sent (no response required) interrupt + * SDIO_IT_DATAEND - Data end (data counter, SDIDCOUNT, is zero) interrupt + * SDIO_IT_STBITERR - Start bit not detected on all data signals in wide + * bus mode interrupt + * SDIO_IT_DBCKEND - Data block sent/received (CRC check passed) interrupt + * SDIO_IT_CMDACT - Command transfer in progress interrupt + * SDIO_IT_TXACT - Data transmit in progress interrupt + * SDIO_IT_RXACT - Data receive in progress interrupt + * SDIO_IT_TXFIFOHE - Transmit FIFO Half Empty interrupt + * SDIO_IT_RXFIFOHF - Receive FIFO Half Full interrupt + * SDIO_IT_TXFIFOF - Transmit FIFO full interrupt + * SDIO_IT_RXFIFOF - Receive FIFO full interrupt + * SDIO_IT_TXFIFOE - Transmit FIFO empty interrupt + * SDIO_IT_RXFIFOE - Receive FIFO empty interrupt + * SDIO_IT_TXDAVL - Data available in transmit FIFO interrupt + * SDIO_IT_RXDAVL - Data available in receive FIFO interrupt + * SDIO_IT_SDIOIT - SD I/O interrupt received interrupt + * SDIO_IT_CEATAEND - CE-ATA command completion signal received for CMD61 interrupt + * + * @return ITStatus:SET or RESET + */ +ITStatus SDIO_GetITStatus(uint32_t SDIO_IT) +{ + ITStatus bitstatus = RESET; + + if((SDIO->STA & SDIO_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn SDIO_ClearITPendingBit + * + * @brief Clears the SDIO's interrupt pending bits. + * + * @param SDIO_IT - specifies the interrupt pending bit to clear. + * SDIO_IT_CCRCFAIL - Command response received (CRC check failed) interrupt + * SDIO_IT_DCRCFAIL - Data block sent/received (CRC check failed) interrupt + * SDIO_IT_CTIMEOUT - Command response timeout interrupt + * SDIO_IT_DTIMEOUT - Data timeout interrupt + * SDIO_IT_TXUNDERR - Transmit FIFO underrun error interrupt + * SDIO_IT_RXOVERR - Received FIFO overrun error interrupt + * SDIO_IT_CMDREND - Command response received (CRC check passed) interrupt + * SDIO_IT_CMDSENT - Command sent (no response required) interrupt + * SDIO_IT_DATAEND - Data end (data counter, SDIDCOUNT, is zero) interrupt + * SDIO_IT_STBITERR - Start bit not detected on all data signals in wide + * bus mode interrupt + * SDIO_IT_SDIOIT - SD I/O interrupt received interrupt + * SDIO_IT_CEATAEND - CE-ATA command completion signal received for CMD61 + * + * @return RTC counter value + */ +void SDIO_ClearITPendingBit(uint32_t SDIO_IT) +{ + SDIO->ICR = SDIO_IT; +} diff --git a/Peripheral/src/ch32v30x_spi.c b/Peripheral/src/ch32v30x_spi.c new file mode 100644 index 0000000..6b1fc6b --- /dev/null +++ b/Peripheral/src/ch32v30x_spi.c @@ -0,0 +1,668 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_spi.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the SPI firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_spi.h" +#include "ch32v30x_rcc.h" + +/* SPI SPE mask */ +#define CTLR1_SPE_Set ((uint16_t)0x0040) +#define CTLR1_SPE_Reset ((uint16_t)0xFFBF) + +/* I2S I2SE mask */ +#define I2SCFGR_I2SE_Set ((uint16_t)0x0400) +#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) + +/* SPI CRCNext mask */ +#define CTLR1_CRCNext_Set ((uint16_t)0x1000) + +/* SPI CRCEN mask */ +#define CTLR1_CRCEN_Set ((uint16_t)0x2000) +#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF) + +/* SPI SSOE mask */ +#define CTLR2_SSOE_Set ((uint16_t)0x0004) +#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB) + +/* SPI registers Masks */ +#define CTLR1_CLEAR_Mask ((uint16_t)0x3040) +#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) + +/* SPI or I2S mode selection masks */ +#define SPI_Mode_Select ((uint16_t)0xF7FF) +#define I2S_Mode_Select ((uint16_t)0x0800) + +/* I2S clock source selection masks */ +#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) +#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) +#define I2S_MUL_MASK ((uint32_t)(0x0000F000)) +#define I2S_DIV_MASK ((uint32_t)(0x000000F0)) + +/********************************************************************* + * @fn SPI_I2S_DeInit + * + * @brief Deinitializes the SPIx peripheral registers to their default + * reset values (Affects also the I2Ss). + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * + * @return none + */ +void SPI_I2S_DeInit(SPI_TypeDef *SPIx) +{ + if(SPIx == SPI1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE); + } + else if(SPIx == SPI2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE); + } + else + { + if(SPIx == SPI3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE); + } + } +} + +/********************************************************************* + * @fn SPI_Init + * + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the SPI_InitStruct. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_InitStruct - pointer to a SPI_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral. + * + * @return none + */ +void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct) +{ + uint16_t tmpreg = 0; + + tmpreg = SPIx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode | + SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL | + SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS | + SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit); + + SPIx->CTLR1 = tmpreg; + SPIx->I2SCFGR &= SPI_Mode_Select; + SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial; +} + +/********************************************************************* + * @fn I2S_Init + * + * @brief Initializes the SPIx peripheral according to the specified + * parameters in the I2S_InitStruct. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * (configured in I2S mode). + * I2S_InitStruct - pointer to an I2S_InitTypeDef structure that + * contains the configuration information for the specified SPI peripheral + * configured in I2S mode. + * + * @return none + */ +void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct) +{ + uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1; + uint32_t tmp = 0; + RCC_ClocksTypeDef RCC_Clocks; + uint32_t sourceclock = 0; + + SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask; + SPIx->I2SPR = 0x0002; + tmpreg = SPIx->I2SCFGR; + + if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default) + { + i2sodd = (uint16_t)0; + i2sdiv = (uint16_t)2; + } + else + { + if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b) + { + packetlength = 1; + } + else + { + packetlength = 2; + } + + if(((uint32_t)SPIx) == SPI2_BASE) + { + tmp = I2S2_CLOCK_SRC; + } + else + { + tmp = I2S3_CLOCK_SRC; + } + + RCC_GetClocksFreq(&RCC_Clocks); + + sourceclock = RCC_Clocks.SYSCLK_Frequency; + + if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable) + { + tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + else + { + tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5); + } + + tmp = tmp / 10; + i2sodd = (uint16_t)(tmp & (uint16_t)0x0001); + i2sdiv = (uint16_t)((tmp - i2sodd) / 2); + i2sodd = (uint16_t)(i2sodd << 8); + } + + if((i2sdiv < 2) || (i2sdiv > 0xFF)) + { + i2sdiv = 2; + i2sodd = 0; + } + + SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput)); + tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode | + (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | + (uint16_t)I2S_InitStruct->I2S_CPOL)))); + SPIx->I2SCFGR = tmpreg; +} + +/********************************************************************* + * @fn SPI_StructInit + * + * @brief Fills each SPI_InitStruct member with its default value. + * + * @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct) +{ + SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex; + SPI_InitStruct->SPI_Mode = SPI_Mode_Slave; + SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b; + SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low; + SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge; + SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2; + SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStruct->SPI_CRCPolynomial = 7; +} + +/********************************************************************* + * @fn I2S_StructInit + * + * @brief Fills each I2S_InitStruct member with its default value. + * + * @param I2S_InitStruct - pointer to a I2S_InitTypeDef structure which + * will be initialized. + * + * @return none + */ +void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct) +{ + I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx; + I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips; + I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b; + I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable; + I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default; + I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low; +} + +/********************************************************************* + * @fn SPI_Cmd + * + * @brief Enables or disables the specified SPI peripheral. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_SPE_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_SPE_Reset; + } +} + +/********************************************************************* + * @fn I2S_Cmd + * + * @brief Enables or disables the specified SPI peripheral (in I2S mode). + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->I2SCFGR |= I2SCFGR_I2SE_Set; + } + else + { + SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset; + } +} + +/********************************************************************* + * @fn SPI_I2S_ITConfig + * + * @brief Enables or disables the specified SPI/I2S interrupts. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_IT - specifies the SPI/I2S interrupt source to be + * enabled or disabled. + * SPI_I2S_IT_TXE - Tx buffer empty interrupt mask. + * SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask. + * SPI_I2S_IT_ERR - Error interrupt mask. + * NewState: ENABLE or DISABLE. + * @return none + */ +void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState) +{ + uint16_t itpos = 0, itmask = 0; + + itpos = SPI_I2S_IT >> 4; + itmask = (uint16_t)1 << (uint16_t)itpos; + + if(NewState != DISABLE) + { + SPIx->CTLR2 |= itmask; + } + else + { + SPIx->CTLR2 &= (uint16_t)~itmask; + } +} + +/********************************************************************* + * @fn SPI_I2S_DMACmd + * + * @brief Enables or disables the SPIx/I2Sx DMA interface. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_DMAReq - specifies the SPI/I2S DMA transfer request to + * be enabled or disabled. + * SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request. + * SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= SPI_I2S_DMAReq; + } + else + { + SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq; + } +} + +/********************************************************************* + * @fn SPI_I2S_SendData + * + * @brief Transmits a Data through the SPIx/I2Sx peripheral. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * Data - Data to be transmitted. + * + * @return none + */ +void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data) +{ + SPIx->DATAR = Data; +} + +/********************************************************************* + * @fn SPI_I2S_ReceiveData + * + * @brief Returns the most recent received data by the SPIx/I2Sx peripheral. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * Data - Data to be transmitted. + * + * @return SPIx->DATAR - The value of the received data. + */ +uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx) +{ + return SPIx->DATAR; +} + +/********************************************************************* + * @fn SPI_NSSInternalSoftwareConfig + * + * @brief Configures internally by software the NSS pin for the selected SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_NSSInternalSoft - + * SPI_NSSInternalSoft_Set - Set NSS pin internally. + * SPI_NSSInternalSoft_Reset - Reset NSS pin internally. + * + * @return none + */ +void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft) +{ + if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset) + { + SPIx->CTLR1 |= SPI_NSSInternalSoft_Set; + } + else + { + SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset; + } +} + +/********************************************************************* + * @fn SPI_SSOutputCmd + * + * @brief Enables or disables the SS output for the selected SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * NewState - new state of the SPIx SS output. + * + * @return none + */ +void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR2 |= CTLR2_SSOE_Set; + } + else + { + SPIx->CTLR2 &= CTLR2_SSOE_Reset; + } +} + +/********************************************************************* + * @fn SPI_DataSizeConfig + * + * @brief Configures the data size for the selected SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_DataSize - specifies the SPI data size. + * SPI_DataSize_16b - Set data frame format to 16bit. + * SPI_DataSize_8b - Set data frame format to 8bit. + * + * @return none + */ +void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize) +{ + SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b; + SPIx->CTLR1 |= SPI_DataSize; +} + +/********************************************************************* + * @fn SPI_TransmitCRC + * + * @brief Transmit the SPIx CRC value. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * + * @return none + */ +void SPI_TransmitCRC(SPI_TypeDef *SPIx) +{ + SPIx->CTLR1 |= CTLR1_CRCNext_Set; +} + +/********************************************************************* + * @fn SPI_CalculateCRC + * + * @brief Enables or disables the CRC value calculation of the transferred bytes. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * NewState - new state of the SPIx CRC value calculation. + * + * @return none + */ +void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + SPIx->CTLR1 |= CTLR1_CRCEN_Set; + } + else + { + SPIx->CTLR1 &= CTLR1_CRCEN_Reset; + } +} + +/********************************************************************* + * @fn SPI_GetCRC + * + * @brief Returns the transmit or the receive CRC register value for the specified SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_CRC - specifies the CRC register to be read. + * SPI_CRC_Tx - Selects Tx CRC register. + * SPI_CRC_Rx - Selects Rx CRC register. + * + * @return crcreg: The selected CRC register value. + */ +uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC) +{ + uint16_t crcreg = 0; + + if(SPI_CRC != SPI_CRC_Rx) + { + crcreg = SPIx->TCRCR; + } + else + { + crcreg = SPIx->RCRCR; + } + + return crcreg; +} + +/********************************************************************* + * @fn SPI_GetCRCPolynomial + * + * @brief Returns the CRC Polynomial register value for the specified SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * + * @return SPIx->CRCR - The CRC Polynomial register value. + */ +uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +{ + return SPIx->CRCR; +} + +/********************************************************************* + * @fn SPI_BiDirectionalLineConfig + * + * @brief Selects the data transfer direction in bi-directional mode + * for the specified SPI. + * + * @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral. + * SPI_Direction - specifies the data transfer direction in + * bi-directional mode. + * SPI_Direction_Tx - Selects Tx transmission direction. + * SPI_Direction_Rx - Selects Rx receive direction. + * + * @return none + */ +void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction) +{ + if(SPI_Direction == SPI_Direction_Tx) + { + SPIx->CTLR1 |= SPI_Direction_Tx; + } + else + { + SPIx->CTLR1 &= SPI_Direction_Rx; + } +} + +/********************************************************************* + * @fn SPI_I2S_GetFlagStatus + * + * @brief Checks whether the specified SPI/I2S flag is set or not. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_FLAG - specifies the SPI/I2S flag to check. + * SPI_I2S_FLAG_TXE - Transmit buffer empty flag. + * SPI_I2S_FLAG_RXNE - Receive buffer not empty flag. + * SPI_I2S_FLAG_BSY - Busy flag. + * SPI_I2S_FLAG_OVR - Overrun flag. + * SPI_FLAG_MODF - Mode Fault flag. + * SPI_FLAG_CRCERR - CRC Error flag. + * I2S_FLAG_UDR - Underrun Error flag. + * I2S_FLAG_CHSIDE - Channel Side flag. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearFlag + * + * @brief Clears the SPIx CRC Error (CRCERR) flag. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_FLAG - specifies the SPI flag to clear. + * SPI_FLAG_CRCERR - CRC Error flag. + * Note- + * - OVR (OverRun error) flag is cleared by software sequence: a read + * operation to SPI_DATAR register (SPI_I2S_ReceiveData()) followed by a read + * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()). + * - UDR (UnderRun error) flag is cleared by a read operation to + * SPI_STATR register (SPI_I2S_GetFlagStatus()). + * - MODF (Mode Fault) flag is cleared by software sequence: a read/write + * operation to SPI_STATR register (SPI_I2S_GetFlagStatus()) followed by a + * write operation to SPI_CTLR1 register (SPI_Cmd() to enable the SPI). + * @return FlagStatus: SET or RESET. + */ +void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG) +{ + SPIx->STATR = (uint16_t)~SPI_I2S_FLAG; +} + +/********************************************************************* + * @fn SPI_I2S_GetITStatus + * + * @brief Checks whether the specified SPI/I2S interrupt has occurred or not. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * - 2 or 3 in I2S mode. + * SPI_I2S_IT - specifies the SPI/I2S interrupt source to check.. + * SPI_I2S_IT_TXE - Transmit buffer empty interrupt. + * SPI_I2S_IT_RXNE - Receive buffer not empty interrupt. + * SPI_I2S_IT_OVR - Overrun interrupt. + * SPI_IT_MODF - Mode Fault interrupt. + * SPI_IT_CRCERR - CRC Error interrupt. + * I2S_IT_UDR - Underrun Error interrupt. + * + * @return FlagStatus: SET or RESET. + */ +ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itpos = 0, itmask = 0, enablestatus = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + itmask = SPI_I2S_IT >> 4; + itmask = 0x01 << itmask; + enablestatus = (SPIx->CTLR2 & itmask); + + if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn SPI_I2S_ClearITPendingBit + * + * @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit. + * + * @param SPIx - where x can be + * - 1, 2 or 3 in SPI mode. + * SPI_I2S_IT - specifies the SPI interrupt pending bit to clear. + * SPI_IT_CRCERR - CRC Error interrupt. + * Note- + * - OVR (OverRun Error) interrupt pending bit is cleared by software + * sequence: a read operation to SPI_DATAR register (SPI_I2S_ReceiveData()) + * followed by a read operation to SPI_STATR register (SPI_I2S_GetITStatus()). + * - UDR (UnderRun Error) interrupt pending bit is cleared by a read + * operation to SPI_STATR register (SPI_I2S_GetITStatus()). + * - MODF (Mode Fault) interrupt pending bit is cleared by software sequence: + * a read/write operation to SPI_STATR register (SPI_I2S_GetITStatus()) + * followed by a write operation to SPI_CTLR1 register (SPI_Cmd() to enable + * the SPI). + * @return none + */ +void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT) +{ + uint16_t itpos = 0; + + itpos = 0x01 << (SPI_I2S_IT & 0x0F); + SPIx->STATR = (uint16_t)~itpos; +} diff --git a/Peripheral/src/ch32v30x_tim.c b/Peripheral/src/ch32v30x_tim.c new file mode 100644 index 0000000..0ac663d --- /dev/null +++ b/Peripheral/src/ch32v30x_tim.c @@ -0,0 +1,2362 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_tim.c +* Author : WCH +* Version : V1.0.1 +* Date : 2025/07/04 +* Description : This file provides all the TIM firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_tim.h" +#include "ch32v30x_rcc.h" + +/* TIM registers bit mask */ +#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) +#define CHCTLR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) + +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); + +/********************************************************************* + * @fn TIM_DeInit + * + * @brief Deinitializes the TIMx peripheral registers to their default + * reset values. + * + * @param TIMx - where x can be 1 to 10 to select the TIM peripheral. + * + * @return none + */ +void TIM_DeInit(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + } + else if(TIMx == TIM8) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE); + } + else if(TIMx == TIM9) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE); + } + else if(TIMx == TIM10) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE); + } + else if(TIMx == TIM2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + } + else if(TIMx == TIM3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + } + else if(TIMx == TIM4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); + } + else if(TIMx == TIM5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE); + } + else if(TIMx == TIM6) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE); + } + else if(TIMx == TIM7) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE); + } +} + +/********************************************************************* + * @fn TIM_TimeBaseInit + * + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * + * @param TIMx - where x can be 1 to 10 to select the TIM peripheral. + * TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef + * structure. + * + * @return none + */ +void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + uint32_t temper1 = 0; + temper1 = ((*( uint32_t * )0x1FFFF704) & 0x000000F0) >> 4; + tmpcr1 = TIMx->CTLR1; + + if(((temper1>=4)&&(temper1<=8))&&((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10))) + { + tmpcr1 |= 1<<13; + } + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4) || + (TIMx == TIM5) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + if((TIMx != TIM6) && (TIMx != TIM7)) + { + tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + } + + TIMx->CTLR1 = tmpcr1; + TIMx->ATRLR = TIM_TimeBaseInitStruct->TIM_Period; + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + TIMx->RPTCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + TIMx->SWEVGR = TIM_PSCReloadMode_Immediate; +} + +/********************************************************************* + * @fn TIM_OC1Init + * + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P)); + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NP)); + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NE)); + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1N)); + + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + TIMx->CH1CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2Init + * + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + TIMx->CH2CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3Init + * + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC3E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC3M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC3S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + TIMx->CH3CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4Init + * + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC4E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC4M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC4S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC4P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if((TIMx == TIM1) || (TIMx == TIM8) || (TIMx == TIM9) || (TIMx == TIM10)) + { + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS4)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + TIMx->CH4CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ICInit + * + * @brief IInitializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_PWMIConfig + * + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external + * PWM signal. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + + if(TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + + if(TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_BDTRConfig + * + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * + * @param TIMx - where x can be （1 8 9 10） to select the TIM peripheral. + * TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/********************************************************************* + * @fn TIM_TimeBaseStructInit + * + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * + * @param TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef structure. + * + * @return none + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/********************************************************************* + * @fn TIM_OCStructInit + * + * @brief Fills each TIM_OCInitStruct member with its default value. + * + * @param TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/********************************************************************* + * @fn TIM_ICStructInit + * + * @brief Fills each TIM_ICInitStruct member with its default value. + * + * @param TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/********************************************************************* + * @fn TIM_BDTRStructInit + * + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * + * @param TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/********************************************************************* + * @fn TIM_Cmd + * + * @brief Enables or disables the specified TIM peripheral. + * + * @param TIMx - where x can be 1 to 10 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_CEN; + } + else + { + TIMx->CTLR1 &= (uint16_t)(~((uint16_t)TIM_CEN)); + } +} + +/********************************************************************* + * @fn TIM_CtrlPWMOutputs + * + * @brief Enables or disables the TIM peripheral Main Outputs. + * + * @param TIMx - where x can be 1/8/9/10 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->BDTR |= TIM_MOE; + } + else + { + TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_MOE)); + } +} + +/********************************************************************* + * @fn TIM_ITConfig + * + * @brief Enables or disables the specified TIM interrupts. + * + * @param TIMx - where x can be 1 to 10 to select the TIM peripheral. + * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * TIM6/TIM7 only have TIM_IT_Update. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_IT; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_IT; + } +} + +/********************************************************************* + * @fn TIM_GenerateEvent + * + * @brief Configures the TIMx event to be generate by software. + * + * @param TIMx - where x can be 1 to 10 to general Event. + * TIM_EventSource + * TIM_EventSource_Update - Update Event. + * TIM_EventSource_CC1 - TIM Capture Compare 1 Event. + * TIM_EventSource_CC2 - TIM Capture Compare 2 Event. + * TIM_EventSource_CC3 - TIM Capture Compare 3 Event. + * TIM_EventSource_CC4 - TIM Capture Compare 4 Event. + * TIM_EventSource_COM - TIM Commutation Event. + * TIM_EventSource_Trigger - TIM Trigger Event. + * TIM_EventSource_Break - TIM Break Event. + * TIM6/TIM7 only have TIM_EventSource_Update. + * @return none + */ +void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource) +{ + TIMx->SWEVGR = TIM_EventSource; +} + +/********************************************************************* + * @fn TIM_DMAConfig + * + * @brief Configures the TIMx's DMA interface. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_DMABase: DMA Base address. + * TIM_DMABase_CR. + * TIM_DMABase_CR2. + * TIM_DMABase_SMCR. + * TIM_DMABase_DIER. + * TIM1_DMABase_SR. + * TIM_DMABase_EGR. + * TIM_DMABase_CCMR1. + * TIM_DMABase_CCMR2. + * TIM_DMABase_CCER. + * TIM_DMABase_CNT. + * TIM_DMABase_PSC. + * TIM_DMABase_CCR1. + * TIM_DMABase_CCR2. + * TIM_DMABase_CCR3. + * TIM_DMABase_CCR4. + * TIM_DMABase_BDTR. + * TIM_DMABase_DCR. + * TIM_DMABurstLength - DMA Burst length. + * TIM_DMABurstLength_1Transfer. + * TIM_DMABurstLength_18Transfers. + * + * @return none + */ +void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + TIMx->DMACFGR = TIM_DMABase | TIM_DMABurstLength; +} + +/********************************************************************* + * @fn TIM_DMACmd + * + * @brief Enables or disables the TIMx's DMA Requests. + * + * @param TIMx - where x can be 1 to 10 to select the TIM peripheral. + * TIM_DMASource - specifies the DMA Request sources. + * TIM_DMA_Update - TIM update Interrupt source. + * TIM_DMA_CC1 - TIM Capture Compare 1 DMA source. + * TIM_DMA_CC2 - TIM Capture Compare 2 DMA source. + * TIM_DMA_CC3 - TIM Capture Compare 3 DMA source. + * TIM_DMA_CC4 - TIM Capture Compare 4 DMA source. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * TIM6/TIM7 only have TIM_DMA_Update + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_DMASource; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_DMASource; + } +} + +/********************************************************************* + * @fn TIM_InternalClockConfig + * + * @brief Configures the TIMx internal Clock. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * + * @return none + */ +void TIM_InternalClockConfig(TIM_TypeDef *TIMx) +{ + TIMx->SMCFGR &= (uint16_t)(~((uint16_t)TIM_SMS)); +} + +/********************************************************************* + * @fn TIM_ITRxExternalClockConfig + * + * @brief Configures the TIMx Internal Trigger as External Clock. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_InputTriggerSource: Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * + * @return none + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_TIxExternalClockConfig + * + * @brief Configures the TIMx Trigger as External Clock. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_TIxExternalCLKSource - Trigger source. + * TIM_TIxExternalCLK1Source_TI1ED - TI1 Edge Detector. + * TIM_TIxExternalCLK1Source_TI1 - Filtered Timer Input 1. + * TIM_TIxExternalCLK1Source_TI2 - Filtered Timer Input 2. + * TIM_ICPolarity - specifies the TIx Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * ICFilter - specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + if(TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_ETRClockMode1Config + * + * @brief Configures the External clock Mode1. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_SlaveMode_External1; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_TS_ETRF; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_ETRClockMode2Config + * + * @brief Configures the External clock Mode2. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + TIMx->SMCFGR |= TIM_ECE; +} + +/********************************************************************* + * @fn TIM_ETRConfig + * + * @brief Configures the TIMx External Trigger (ETR). + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= SMCFGR_ETR_Mask; + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_PrescalerConfig + * + * @brief Configures the TIMx Prescaler. + * + * @param TIMx - where x can be 1 to 10 to select the TIM peripheral. + * Prescaler - specifies the Prescaler Register value. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode_Update - The Prescaler is loaded at the update event. + * TIM_PSCReloadMode_Immediate - The Prescaler is loaded immediately. + * + * @return none + */ +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + TIMx->PSC = Prescaler; + TIMx->SWEVGR = TIM_PSCReloadMode; +} + +/********************************************************************* + * @fn TIM_CounterModeConfig + * + * @brief Specifies the TIMx Counter Mode to be used. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_CounterMode - specifies the Counter Mode to be used. + * TIM_CounterMode_Up - TIM Up Counting Mode. + * TIM_CounterMode_Down - TIM Down Counting Mode. + * TIM_CounterMode_CenterAligned1 - TIM Center Aligned Mode1. + * TIM_CounterMode_CenterAligned2 - TIM Center Aligned Mode2. + * TIM_CounterMode_CenterAligned3 - TIM Center Aligned Mode3. + * + * @return none + */ +void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= TIM_CounterMode; + TIMx->CTLR1 = tmpcr1; +} + +/********************************************************************* + * @fn TIM_SelectInputTrigger + * + * @brief Selects the Input Trigger source. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_InputTriggerSource - The Input Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * TIM_TS_TI1F_ED - TI1 Edge Detector. + * TIM_TS_TI1FP1 - Filtered Timer Input 1. + * TIM_TS_TI2FP2 - Filtered Timer Input 2. + * TIM_TS_ETRF - External Trigger input. + * + * @return none + */ +void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_InputTriggerSource; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_EncoderInterfaceConfig + * + * @brief Configures the TIMx Encoder Interface. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_EncoderMode - specifies the TIMx Encoder Mode. + * TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending + * on TI2FP2 level. + * TIM_EncoderMode_TI2 - Counter counts on TI2FP2 edge depending + * on TI1FP1 level. + * TIM_EncoderMode_TI12 - Counter counts on both TI1FP1 and + * TI2FP2 edges depending. + * TIM_IC1Polarity - specifies the IC1 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TTIM_ICPolarity_Rising - IC Rising edge. + * TIM_IC2Polarity - specifies the IC2 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TIM_ICPolarity_Rising - IC Rising edge. + * + * @return none + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_EncoderMode; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & (uint16_t)(~((uint16_t)TIM_CC2S))); + tmpccmr1 |= TIM_CC1S_0 | TIM_CC2S_0; + tmpccer &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1P)) & ((uint16_t) ~((uint16_t)TIM_CC2P))); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + TIMx->SMCFGR = tmpsmcr; + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ForcedOC1Config + * + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC1REF. + * TIM_ForcedAction_InActive - Force inactive level on OC1REF. + * + * @return none + */ +void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1M); + tmpccmr1 |= TIM_ForcedAction; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC2Config + * + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC2REF. + * TIM_ForcedAction_InActive - Force inactive level on OC2REF. + * + * @return none + */ +void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2M); + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC3Config + * + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC3REF. + * TIM_ForcedAction_InActive - Force inactive level on OC3REF. + * + * @return none + */ +void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3M); + tmpccmr2 |= TIM_ForcedAction; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ForcedOC4Config + * + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC4REF. + * TIM_ForcedAction_InActive - Force inactive level on OC4REF. + * + * @return none + */ +void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4M); + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ARRPreloadConfig + * + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * + * @param TIMx - where x can be 1 to 10 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_ARPE; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_ARPE); + } +} + +/********************************************************************* + * @fn TIM_SelectCOM + * + * @brief Selects the TIM peripheral Commutation event. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCUS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCUS); + } +} + +/********************************************************************* + * @fn TIM_SelectCCDMA + * + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCDS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCDS); + } +} + +/********************************************************************* + * @fn TIM_CCPreloadControl + * + * @brief DSets or Resets the TIM peripheral Capture Compare Preload Control bit. + * reset values (Affects also the I2Ss). + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCPC; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCPC); + } +} + +/********************************************************************* + * @fn TIM_OC1PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1PE); + tmpccmr1 |= TIM_OCPreload; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2PE); + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3PE); + tmpccmr2 |= TIM_OCPreload; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4PE); + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1FastConfig + * + * @brief Configures the TIMx Output Compare 1 Fast feature. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1FE); + tmpccmr1 |= TIM_OCFast; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2FastConfig + * + * @brief Configures the TIMx Output Compare 2 Fast feature. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2FE); + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3FastConfig + * + * @brief Configures the TIMx Output Compare 3 Fast feature. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3FE); + tmpccmr2 |= TIM_OCFast; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4FastConfig + * + * @brief Configures the TIMx Output Compare 4 Fast feature. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4FE); + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC1Ref + * + * @brief Clears or safeguards the OCREF1 signal on an external event. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1CE); + tmpccmr1 |= TIM_OCClear; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC2Ref + * + * @brief Clears or safeguards the OCREF2 signal on an external event. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2CE); + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC3Ref + * + * @brief Clears or safeguards the OCREF3 signal on an external event. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3CE); + tmpccmr2 |= TIM_OCClear; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC4Ref + * + * @brief Clears or safeguards the OCREF4 signal on an external event. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4CE); + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1PolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC1 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1P); + tmpccer |= TIM_OCPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC1NPolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be （1 8 9 10） to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1NP); + tmpccer |= TIM_OCNPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2PolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC2 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2NPolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be （1 8 9 10） to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3PolarityConfig + * + * @brief Configures the TIMx Channel 3 polarity. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10）to select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3NPolarityConfig + * + * @brief Configures the TIMx Channel 3N polarity. + * + * @param TIMx - where x can be （1 8 9 10） to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC2N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4PolarityConfig + * + * @brief Configures the TIMx Channel 4 polarity. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10）to select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC4P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_CCxCmd + * + * @brief Enables or disables the TIM Capture Compare Channel x. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_CCx - specifies the TIM Channel CCxE bit new state. + * TIM_CCx_Enable. + * TIM_CCx_Disable. + * + * @return none + */ +void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + tmp = CCER_CCE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_CCxNCmd + * + * @brief Enables or disables the TIM Capture Compare Channel xN. + * + * @param TIMx - where x can be （1 8 9 10） select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_CCxN - specifies the TIM Channel CCxNE bit new state. + * TIM_CCxN_Enable. + * TIM_CCxN_Disable. + * + * @return none + */ +void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + tmp = CCER_CCNE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_SelectOCxM + * + * @brief Selects the TIM Output Compare Mode. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_OCMode - specifies the TIM Output Compare Mode. + * TIM_OCMode_Timing. + * TIM_OCMode_Active. + * TIM_OCMode_Toggle. + * TIM_OCMode_PWM1. + * TIM_OCMode_PWM2. + * TIM_ForcedAction_Active. + * TIM_ForcedAction_InActive. + * + * @return none + */ +void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + tmp = (uint32_t)TIMx; + tmp += CHCTLR_Offset; + tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp1; + + if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel >> 1); + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC1M); + *(__IO uint32_t *)tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4) >> (uint16_t)1; + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC2M); + *(__IO uint32_t *)tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/********************************************************************* + * @fn TIM_UpdateDisableConfig + * + * @brief Enables or Disables the TIMx Update event. + * + * @param TIMx - where x can be 1 to 10 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_UDIS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_UDIS); + } +} + +/********************************************************************* + * @fn TIM_UpdateRequestConfig + * + * @brief Configures the TIMx Update Request Interrupt source. + * + * @param TIMx - where x can be 1 to 10 select the TIM peripheral. + * TIM_UpdateSource - specifies the Update source. + * TIM_UpdateSource_Regular. + * TIM_UpdateSource_Global. + * + * @return none + */ +void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource) +{ + if(TIM_UpdateSource != TIM_UpdateSource_Global) + { + TIMx->CTLR1 |= TIM_URS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_URS); + } +} + +/********************************************************************* + * @fn TIM_SelectHallSensor + * + * @brief Enables or disables the TIMx's Hall sensor interface. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_TI1S; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_TI1S); + } +} + +/********************************************************************* + * @fn TIM_SelectOnePulseMode + * + * @brief Selects the TIMx's One Pulse Mode. + * + * @param TIMx - where x can be 1 to 10 select the TIM peripheral. + * TIM_OPMode - specifies the OPM Mode to be used. + * TIM_OPMode_Single. + * TIM_OPMode_Repetitive. + * + * @return none + */ +void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM); + TIMx->CTLR1 |= TIM_OPMode; +} + +/********************************************************************* + * @fn TIM_SelectOutputTrigger + * + * @brief Selects the TIMx Trigger Output Mode. + * + * @param TIMx - where x can be 1 to 10 select the TIM peripheral. + * TIM_TRGOSource - specifies the Trigger Output source. + * TIM_TRGOSource_Reset - The UG bit in the TIM_EGR register is + * used as the trigger output (TRGO). + * TIM_TRGOSource_Enable - The Counter Enable CEN is used as the + * trigger output (TRGO). + * TIM_TRGOSource_Update - The update event is selected as the + * trigger output (TRGO). + * TIM_TRGOSource_OC1 - The trigger output sends a positive pulse + * when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO). + * TIM_TRGOSource_OC1Ref - OC1REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC2Ref - OC2REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC3Ref - OC3REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC4Ref - OC4REF signal is used as the trigger output (TRGO). + * TIM6/TIM7 only have TIM_TRGOSource_Reset/TIM_TRGOSource_Enable/TIM_TRGOSource_Update + * @return none + */ +void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource) +{ + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_MMS); + TIMx->CTLR2 |= TIM_TRGOSource; +} + +/********************************************************************* + * @fn TIM_SelectSlaveMode + * + * @brief Selects the TIMx Slave Mode. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） select the TIM peripheral. + * TIM_SlaveMode - specifies the Timer Slave Mode. + * TIM_SlaveMode_Reset - Rising edge of the selected trigger + * signal (TRGI) re-initializes. + * TIM_SlaveMode_Gated - The counter clock is enabled when the + * trigger signal (TRGI) is high. + * TIM_SlaveMode_Trigger - The counter starts at a rising edge + * of the trigger TRGI. + * TIM_SlaveMode_External1 - Rising edges of the selected trigger + * (TRGI) clock the counter. + * + * @return none + */ +void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_SMS); + TIMx->SMCFGR |= TIM_SlaveMode; +} + +/********************************************************************* + * @fn TIM_SelectMasterSlaveMode + * + * @brief Sets or Resets the TIMx Master/Slave Mode. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） select the TIM peripheral. + * TIM_MasterSlaveMode - specifies the Timer Master Slave Mode. + * TIM_MasterSlaveMode_Enable - synchronization between the current + * timer and its slaves (through TRGO). + * TIM_MasterSlaveMode_Disable - No action. + * + * @return none + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_MSM); + TIMx->SMCFGR |= TIM_MasterSlaveMode; +} + +/********************************************************************* + * @fn TIM_SetCounter + * + * @brief Sets the TIMx Counter Register value. + * + * @param TIMx - where x can be 1 to 10 select the TIM peripheral. + * Counter - specifies the Counter register new value. + * + * @return none + */ +void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter) +{ + TIMx->CNT = Counter; +} + +/********************************************************************* + * @fn TIM_SetAutoreload + * + * @brief Sets the TIMx Autoreload Register value. + * + * @param TIMx - where x can be 1 to 10 select the TIM peripheral. + * Autoreload - specifies the Autoreload register new value. + * + * @return none + */ +void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload) +{ + TIMx->ATRLR = Autoreload; +} + +/********************************************************************* + * @fn TIM_SetCompare1 + * + * @brief Sets the TIMx Capture Compare1 Register value. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1) +{ + TIMx->CH1CVR = Compare1; +} + +/********************************************************************* + * @fn TIM_SetCompare2 + * + * @brief Sets the TIMx Capture Compare2 Register value. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2) +{ + TIMx->CH2CVR = Compare2; +} + +/********************************************************************* + * @fn TIM_SetCompare3 + * + * @brief Sets the TIMx Capture Compare3 Register value. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3) +{ + TIMx->CH3CVR = Compare3; +} + +/********************************************************************* + * @fn TIM_SetCompare4 + * + * @brief Sets the TIMx Capture Compare4 Register value. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4) +{ + TIMx->CH4CVR = Compare4; +} + +/********************************************************************* + * @fn TIM_SetIC1Prescaler + * + * @brief Sets the TIMx Input Capture 1 prescaler. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC1PSC); + TIMx->CHCTLR1 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC2Prescaler + * + * @brief Sets the TIMx Input Capture 2 prescaler. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC2PSC); + TIMx->CHCTLR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetIC3Prescaler + * + * @brief Sets the TIMx Input Capture 3 prescaler. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC3PSC); + TIMx->CHCTLR2 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC4Prescaler + * + * @brief Sets the TIMx Input Capture 4 prescaler. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC4PSC); + TIMx->CHCTLR2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetClockDivision + * + * @brief Sets the TIMx Clock Division value. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） select the TIM peripheral. + * TIM_CKD - specifies the clock division value. + * TIM_CKD_DIV1 - TDTS = Tck_tim. + * TIM_CKD_DIV2 - TDTS = 2*Tck_tim. + * TIM_CKD_DIV4 - TDTS = 4*Tck_tim. + * + * @return none + */ +void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_CTLR1_CKD); + TIMx->CTLR1 |= TIM_CKD; +} + +/********************************************************************* + * @fn TIM_GetCapture1 + * + * @brief Gets the TIMx Input Capture 1 value. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） select the TIM peripheral. + * + * @return TIMx->CH1CVR - Capture Compare 1 Register value. + */ +uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx) +{ + return TIMx->CH1CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture2 + * + * @brief Gets the TIMx Input Capture 2 value. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） select the TIM peripheral. + * + * @return TIMx->CH2CVR - Capture Compare 2 Register value. + */ +uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx) +{ + return TIMx->CH2CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture3 + * + * @brief Gets the TIMx Input Capture 3 value. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） select the TIM peripheral. + * + * @return TIMx->CH3CVR - Capture Compare 3 Register value. + */ +uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx) +{ + return TIMx->CH3CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture4 + * + * @brief Gets the TIMx Input Capture 4 value. + * + * @param TIMx - where x can be （1 2 3 4 5 8 9 10） select the TIM peripheral. + * + * @return TIMx->CH4CVR - Capture Compare 4 Register value. + */ +uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx) +{ + return TIMx->CH4CVR; +} + +/********************************************************************* + * @fn TIM_GetCounter + * + * @brief Gets the TIMx Counter value. + * + * @param TIMx - where x can be 1 to 10 select the TIM peripheral. + * + * @return TIMx->CNT - Counter Register value. + */ +uint16_t TIM_GetCounter(TIM_TypeDef *TIMx) +{ + return TIMx->CNT; +} + +/********************************************************************* + * @fn TIM_GetPrescaler + * + * @brief Gets the TIMx Prescaler value. + * + * @param TIMx - where x can be 1 to 10 select the TIM peripheral. + * + * @return TIMx->PSC - Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx) +{ + return TIMx->PSC; +} + +/********************************************************************* + * @fn TIM_GetFlagStatus + * + * @brief Checks whether the specified TIM flag is set or not. + * + * @param TIMx - where x can be 1 to 10 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * TIM6/TIM7 only have TIM_FLAG_Update - TIM update Flag. + * + * @return none + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + + if((TIMx->INTFR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearFlag + * + * @brief Clears the TIMx's pending flags. + * + * @param TIMx - where x can be 1 to 10 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * TIM6/TIM7 only have TIM_FLAG_Update - TIM update Flag. + * + * @return none + */ +void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + TIMx->INTFR = (uint16_t)~TIM_FLAG; +} + +/********************************************************************* + * @fn TIM_GetITStatus + * + * @brief Checks whether the TIM interrupt has occurred or not. + * + * @param TIMx - where x can be 1 to 10 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * TIM6/TIM7 only have TIM_IT_Update - TIM update Interrupt source. + * + * @return none + */ +ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + + itstatus = TIMx->INTFR & TIM_IT; + + itenable = TIMx->DMAINTENR & TIM_IT; + if((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearITPendingBit + * + * @brief Clears the TIMx's interrupt pending bits. + * + * @param TIMx - where x can be 1 to 10 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * TIM6/TIM7 only have TIM_IT_Update - TIM update Interrupt source. + * + * @return none + */ +void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + TIMx->INTFR = (uint16_t)~TIM_IT; +} + +/********************************************************************* + * @fn TI1_Config + * + * @brief Configure the TI1 as Input. + * + * @param TIMx - where x can be (1 2 3 4 5 8 9 10) select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC1E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & ((uint16_t) ~((uint16_t)TIM_IC1F))); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI2_Config + * + * @brief Configure the TI2 as Input. + * + * @param TIMx - where x can be (1 2 3 4 5 8 9 10) select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC2E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC2S)) & ((uint16_t) ~((uint16_t)TIM_IC2F))); + tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8); + + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC2E); + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI3_Config + * + * @brief Configure the TI3 as Input. + * + * @param TIMx - where x can be (1 2 3 4 5 8 9 10) select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC3E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC3S)) & ((uint16_t) ~((uint16_t)TIM_IC3F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC3E); + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI4_Config + * + * @brief Configure the TI4 as Input. + * + * @param TIMx - where x can be (1 2 3 4 5 8 9 10) select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC4E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CC4S) & ((uint16_t) ~((uint16_t)TIM_IC4F))); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12); + + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC4P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC4E); + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} diff --git a/Peripheral/src/ch32v30x_usart.c b/Peripheral/src/ch32v30x_usart.c new file mode 100644 index 0000000..2e6513c --- /dev/null +++ b/Peripheral/src/ch32v30x_usart.c @@ -0,0 +1,783 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_usart.c +* Author : WCH +* Version : V1.0.1 +* Date : 2025/04/12 +* Description : This file provides all the USART firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_usart.h" +#include "ch32v30x_rcc.h" + +/* USART_Private_Defines */ +#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ +#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ + +#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ + +#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ +#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ +#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CTLR1 Mask */ +#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ + +#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ +#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ + +#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ +#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CTLR2 STOP Bits Mask */ +#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CTLR2 Clock Mask */ + +#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ +#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ + +#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ +#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ + +#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ +#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ + +#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ +#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CTLR3 Mask */ + +#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ +#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ +#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ +#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ + +/********************************************************************* + * @fn USART_DeInit + * + * @brief Deinitializes the USARTx peripheral registers to their default + * reset values. + * + * @param USARTx - where x can be 1 to 3 to select the USART peripheral. + * UARTx where x can be 4 to 8 to select the UART peripheral. + * + * @return none + */ +void USART_DeInit(USART_TypeDef *USARTx) +{ + if(USARTx == USART1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + } + else if(USARTx == USART2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); + } + else if(USARTx == USART3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); + } + else if(USARTx == UART4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); + } + else if(USARTx == UART5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); + } + else if(USARTx == UART6) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART6, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART6, DISABLE); + } + else if(USARTx == UART7) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART7, DISABLE); + } + else if(USARTx == UART8) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART8, DISABLE); + } +} + +/********************************************************************* + * @fn USART_Init + * + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct. + * + * @param USARTx - where x can be 1 to 3 to select the USART peripheral. + * UARTx where x can be 4 to 8 to select the UART peripheral. + * USART_InitStruct - pointer to a USART_InitTypeDef structure + * that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct) +{ + uint32_t tmpreg = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t usartxbase = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + + if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) + { + } + + usartxbase = (uint32_t)USARTx; + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_STOP_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + USARTx->CTLR2 = (uint16_t)tmpreg; + tmpreg = USARTx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + USARTx->CTLR1 = (uint16_t)tmpreg; + + tmpreg = USARTx->CTLR3; + tmpreg &= CTLR3_CLEAR_Mask; + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + USARTx->CTLR3 = (uint16_t)tmpreg; + + RCC_GetClocksFreq(&RCC_ClocksStatus); + + if(usartxbase == USART1_BASE) + { + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); + tmpreg = (integerdivider / 100) << 4; + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + USARTx->BRR = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_StructInit + * + * @brief Fills each USART_InitStruct member with its default value. + * + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void USART_StructInit(USART_InitTypeDef *USART_InitStruct) +{ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/********************************************************************* + * @fn USART_ClockInit + * + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef + * structure that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + uint32_t tmpreg = 0x00; + + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_CLOCK_CLEAR_Mask; + tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; + USARTx->CTLR2 = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_ClockStructInit + * + * @brief Fills each USART_ClockStructInit member with its default value. + * + * @param USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef + * structure which will be initialized. + * + * @return none + */ +void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/********************************************************************* + * @fn USART_Cmd + * + * @brief Enables or disables the specified USART peripheral. + * reset values (Affects also the I2Ss). + * + * @param USARTx - where x can be 1 to 3 to select the USART peripheral. + * UARTx where x can be 4 to 8 to select the UART peripheral. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_UE_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_UE_Reset; + } +} + +/********************************************************************* + * @fn USART_ITConfig + * + * @brief Enables or disables the specified USART interrupts. + * reset values (Affects also the I2Ss). + * + * @param USARTx - where x can be 1 to 3 to select the USART peripheral. + * UARTx where x can be 4 to 8 to select the UART peripheral. + * USART_IT - specifies the USART interrupt sources to be enabled or disabled. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Transmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_PE - Parity Error interrupt. + * USART_IT_ERR - Error interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + + usartxbase = (uint32_t)USARTx; + usartreg = (((uint8_t)USART_IT) >> 0x05); + itpos = USART_IT & IT_Mask; + itmask = (((uint32_t)0x01) << itpos); + + if(usartreg == 0x01) + { + usartxbase += 0x0C; + } + else if(usartreg == 0x02) + { + usartxbase += 0x10; + } + else + { + usartxbase += 0x14; + } + + if(NewState != DISABLE) + { + *(__IO uint32_t *)usartxbase |= itmask; + } + else + { + *(__IO uint32_t *)usartxbase &= ~itmask; + } +} + +/********************************************************************* + * @fn USART_DMACmd + * + * @brief Enables or disables the USART DMA interface. + * + * @param USARTx - where x can be 1 to 3 to select the USART peripheral. + * UARTx where x can be 4 to 8 to select the UART peripheral. + * USART_DMAReq - specifies the DMA request. + * USART_DMAReq_Tx - USART DMA transmit request. + * USART_DMAReq_Rx - USART DMA receive request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= USART_DMAReq; + } + else + { + USARTx->CTLR3 &= (uint16_t)~USART_DMAReq; + } +} + +/********************************************************************* + * @fn USART_SetAddress + * + * @brief Sets the address of the USART node. + * + * @param USARTx - where x can be 1 to 3 to select the USART peripheral. + * UARTx where x can be 4 to 8 to select the UART peripheral. + * USART_Address - Indicates the address of the USART node. + * + * @return none + */ +void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address) +{ + USARTx->CTLR2 &= CTLR2_Address_Mask; + USARTx->CTLR2 |= USART_Address; +} + +/********************************************************************* + * @fn USART_WakeUpConfig + * + * @brief Selects the USART WakeUp method. + * + * @param USARTx - where x can be 1 to 3 to select the USART peripheral. + * UARTx where x can be 4 to 8 to select the UART peripheral. + * USART_WakeUp - specifies the USART wakeup method. + * USART_WakeUp_IdleLine - WakeUp by an idle line detection. + * USART_WakeUp_AddressMark - WakeUp by an address mark. + * + * @return none + */ +void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp) +{ + USARTx->CTLR1 &= CTLR1_WAKE_Mask; + USARTx->CTLR1 |= USART_WakeUp; +} + +/********************************************************************* + * @fn USART_ReceiverWakeUpCmd + * + * @brief Determines if the USART is in mute mode or not. + * + * @param USARTx - where x can be 1 to 3 to select the USART peripheral. + * UARTx where x can be 4 to 8 to select the UART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_RWU_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_RWU_Reset; + } +} + +/********************************************************************* + * @fn USART_LINBreakDetectLengthConfig + * + * @brief Sets the USART LIN Break detection length. + * + * @param USARTx - where x can be 1 to 3 to select the USART peripheral. + * UARTx where x can be 4 to 8 to select the UART peripheral. + * USART_LINBreakDetectLength - specifies the LIN break detection length. + * USART_LINBreakDetectLength_10b - 10-bit break detection. + * USART_LINBreakDetectLength_11b - 11-bit break detection. + * + * @return none + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength) +{ + USARTx->CTLR2 &= CTLR2_LBDL_Mask; + USARTx->CTLR2 |= USART_LINBreakDetectLength; +} + +/********************************************************************* + * @fn USART_LINCmd + * + * @brief Enables or disables the USART LIN mode. + * + * @param USARTx - where x can be 1 to 3 to select the USART peripheral. + * UARTx where x can be 4 to 8 to select the UART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR2 |= CTLR2_LINEN_Set; + } + else + { + USARTx->CTLR2 &= CTLR2_LINEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SendData + * + * @brief Transmits single data through the USARTx peripheral. + * + * @param USARTx - where x can be 1 to 3 to select the USART peripheral. + * UARTx where x can be 4 to 8 to select the UART peripheral. + * Data - the data to transmit. + * + * @return none + */ +void USART_SendData(USART_TypeDef *USARTx, uint16_t Data) +{ + USARTx->DATAR = (Data & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_ReceiveData + * + * @brief Returns the most recent received data by the USARTx peripheral. + * + * @param USARTx - where x can be 1 to 3 to select the USART peripheral. + * UARTx where x can be 4 to 8 to select the UART peripheral. + * + * @return The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef *USARTx) +{ + return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_SendBreak + * + * @brief Transmits break characters. + * + * @param USARTx - where x can be 1 to 3 to select the USART peripheral. + * UARTx where x can be 4 to 8 to select the UART peripheral. + * + * @return none + */ +void USART_SendBreak(USART_TypeDef *USARTx) +{ + USARTx->CTLR1 |= CTLR1_SBK_Set; +} + +/********************************************************************* + * @fn USART_SetGuardTime + * + * @brief Sets the specified USART guard time. + * + * @param USARTx - where x can be 1 to 3 to select the USART peripheral. + * UARTx where x can be 4 to 8 to select the UART peripheral. + * USART_GuardTime - specifies the guard time. + * + * @return none + */ +void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime) +{ + USARTx->GPR &= GPR_LSB_Mask; + USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/********************************************************************* + * @fn USART_SetPrescaler + * + * @brief Sets the system clock prescaler. + * + * @param USARTx - where x can be 1 to 3 to select the USART peripheral. + * UARTx where x can be 4 to 8 to select the UART peripheral. + * USART_Prescaler - specifies the prescaler clock. + * + * @return none + */ +void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler) +{ + USARTx->GPR &= GPR_MSB_Mask; + USARTx->GPR |= USART_Prescaler; +} + +/********************************************************************* + * @fn USART_SmartCardCmd + * + * @brief Enables or disables the USART Smart Card mode. + * + * @param USARTx - where x can be 1 to 3 to select the USART peripheral. + * UARTx where x can be 4 to 8 to select the UART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_SCEN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_SCEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SmartCardNACKCmd + * + * @brief Enables or disables NACK transmission. + * + * @param USARTx - where x can be 1 to 3 to select the USART peripheral. + * UARTx where x can be 4 to 8 to select the UART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_NACK_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_NACK_Reset; + } +} + +/********************************************************************* + * @fn USART_HalfDuplexCmd + * + * @brief Enables or disables the USART Half Duplex communication. + * + * @param USARTx - where x can be 1 to 3 to select the USART peripheral. + * UARTx where x can be 4 to 8 to select the UART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_HDSEL_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_HDSEL_Reset; + } +} + +/********************************************************************* + * @fn USART_IrDAConfig + * + * @brief Configures the USART's IrDA interface. + * + * @param USARTx - where x can be 1 to 3 to select the USART peripheral. + * UARTx where x can be 4 to 8 to select the UART peripheral. + * USART_IrDAMode - specifies the IrDA mode. + * USART_IrDAMode_LowPower. + * USART_IrDAMode_Normal. + * + * @return none + */ +void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode) +{ + USARTx->CTLR3 &= CTLR3_IRLP_Mask; + USARTx->CTLR3 |= USART_IrDAMode; +} + +/********************************************************************* + * @fn USART_IrDACmd + * + * @brief Enables or disables the USART's IrDA interface. + * + * @param USARTx - where x can be 1 to 3 to select the USART peripheral. + * UARTx where x can be 4 to 8 to select the UART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_IREN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_IREN_Reset; + } +} + +/********************************************************************* + * @fn USART_GetFlagStatus + * + * @brief Checks whether the specified USART flag is set or not. + * + * @param USARTx - where x can be 1 to 3 to select the USART peripheral. + * UARTx where x can be 4 to 8 to select the UART peripheral. + * USART_FLAG - specifies the flag to check. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TXE - Transmit data register empty flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * USART_FLAG_IDLE - Idle Line detection flag. + * USART_FLAG_ORE - OverRun Error flag. + * USART_FLAG_NE - Noise Error flag. + * USART_FLAG_FE - Framing Error flag. + * USART_FLAG_PE - Parity Error flag. + * + * @return bitstatus: SET or RESET + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearFlag + * + * @brief Clears the USARTx's pending flags. + * + * @param USARTx - where x can be 1 to 3 to select the USART peripheral. + * UARTx where x can be 4 to 8 to select the UART peripheral. + * USART_FLAG - specifies the flag to clear. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * Note- + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_STATR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DATAR register (USART_ReceiveData()). + * - RXNE flag can be also cleared by a read to the USART_DATAR register + * (USART_ReceiveData()). + * - TC flag can be also cleared by software sequence: a read operation to + * USART_STATR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DATAR register (USART_SendData()). + * - TXE flag is cleared only by a write to the USART_DATAR register + * (USART_SendData()). + * @return none + */ +void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + + USARTx->STATR = (uint16_t)~USART_FLAG; +} + +/********************************************************************* + * @fn USART_GetITStatus + * + * @brief Checks whether the specified USART interrupt has occurred or not. + * + * @param USARTx - where x can be 1 to 3 to select the USART peripheral. + * UARTx where x can be 4 to 8 to select the UART peripheral. + * USART_IT - specifies the USART interrupt source to check. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Tansmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set. + * USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set. + * USART_IT_NE - Noise Error interrupt. + * USART_IT_FE - Framing Error interrupt. + * USART_IT_PE - Parity Error interrupt. + * + * @return bitstatus: SET or RESET. + */ +ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + + usartreg = (((uint8_t)USART_IT) >> 0x05); + itmask = USART_IT & IT_Mask; + itmask = (uint32_t)0x01 << itmask; + + if(usartreg == 0x01) + { + itmask &= USARTx->CTLR1; + } + else if(usartreg == 0x02) + { + itmask &= USARTx->CTLR2; + } + else + { + itmask &= USARTx->CTLR3; + } + + bitpos = USART_IT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->STATR; + + if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearITPendingBit + * + * @brief Clears the USARTx's interrupt pending bits. + * + * @param USARTx - where x can be 1 to 3 to select the USART peripheral. + * UARTx where x can be 4 to 8 to select the UART peripheral. + * USART_IT - specifies the interrupt pending bit to clear. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * Note- + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_STATR register + * (USART_GetITStatus()) followed by a read operation to USART_DATAR register + * (USART_ReceiveData()). + * - RXNE pending bit can be also cleared by a read to the USART_DATAR register + * (USART_ReceiveData()). + * - TC pending bit can be also cleared by software sequence: a read + * operation to USART_STATR register (USART_GetITStatus()) followed by a write + * operation to USART_DATAR register (USART_SendData()). + * - TXE pending bit is cleared only by a write to the USART_DATAR register + * (USART_SendData()). + * @return none + */ +void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + + bitpos = USART_IT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->STATR = (uint16_t)~itmask; +} diff --git a/Peripheral/src/ch32v30x_wwdg.c b/Peripheral/src/ch32v30x_wwdg.c new file mode 100644 index 0000000..e027893 --- /dev/null +++ b/Peripheral/src/ch32v30x_wwdg.c @@ -0,0 +1,141 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_wwdg.c +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file provides all the WWDG firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_wwdg.h" +#include "ch32v30x_rcc.h" + +/* CTLR register bit mask */ +#define CTLR_WDGA_Set ((uint32_t)0x00000080) + +/* CFGR register bit mask */ +#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F) +#define CFGR_W_Mask ((uint32_t)0xFFFFFF80) +#define BIT_Mask ((uint8_t)0x7F) + +/********************************************************************* + * @fn WWDG_DeInit + * + * @brief Deinitializes the WWDG peripheral registers to their default reset values + * + * @return none + */ +void WWDG_DeInit(void) +{ + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE); +} + +/********************************************************************* + * @fn WWDG_SetPrescaler + * + * @brief Sets the WWDG Prescaler + * + * @param WWDG_Prescaler - specifies the WWDG Prescaler + * WWDG_Prescaler_1 - WWDG counter clock = (PCLK1/4096)/1 + * WWDG_Prescaler_2 - WWDG counter clock = (PCLK1/4096)/2 + * WWDG_Prescaler_4 - WWDG counter clock = (PCLK1/4096)/4 + * WWDG_Prescaler_8 - WWDG counter clock = (PCLK1/4096)/8 + * + * @return none + */ +void WWDG_SetPrescaler(uint32_t WWDG_Prescaler) +{ + uint32_t tmpreg = 0; + tmpreg = WWDG->CFGR & CFGR_WDGTB_Mask; + tmpreg |= WWDG_Prescaler; + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_SetWindowValue + * + * @brief Sets the WWDG window value + * + * @param WindowValue - specifies the window value to be compared to the + * downcounter,which must be lower than 0x80 + * + * @return none + */ +void WWDG_SetWindowValue(uint8_t WindowValue) +{ + __IO uint32_t tmpreg = 0; + + tmpreg = WWDG->CFGR & CFGR_W_Mask; + + tmpreg |= WindowValue & (uint32_t)BIT_Mask; + + WWDG->CFGR = tmpreg; +} + +/********************************************************************* + * @fn WWDG_EnableIT + * + * @brief Enables the WWDG Early Wakeup interrupt(EWI) + * + * @return none + */ +void WWDG_EnableIT(void) +{ + WWDG->CFGR |= (1 << 9); +} + +/********************************************************************* + * @fn WWDG_SetCounter + * + * @brief Sets the WWDG counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * + * @return none + */ +void WWDG_SetCounter(uint8_t Counter) +{ + WWDG->CTLR = Counter & BIT_Mask; +} + +/********************************************************************* + * @fn WWDG_Enable + * + * @brief Enables WWDG and load the counter value + * + * @param Counter - specifies the watchdog counter value,which must be a + * number between 0x40 and 0x7F + * @return none + */ +void WWDG_Enable(uint8_t Counter) +{ + WWDG->CTLR = CTLR_WDGA_Set | Counter; +} + +/********************************************************************* + * @fn WWDG_GetFlagStatus + * + * @brief Checks whether the Early Wakeup interrupt flag is set or not + * + * @return The new state of the Early Wakeup interrupt flag (SET or RESET) + */ +FlagStatus WWDG_GetFlagStatus(void) +{ + return (FlagStatus)(WWDG->STATR); +} + +/********************************************************************* + * @fn WWDG_ClearFlag + * + * @brief Clears Early Wakeup interrupt flag + * + * @return none + */ +void WWDG_ClearFlag(void) +{ + WWDG->STATR = (uint32_t)RESET; +} diff --git a/Startup/startup_ch32v30x_D8.S b/Startup/startup_ch32v30x_D8.S new file mode 100644 index 0000000..f3ec0ab --- /dev/null +++ b/Startup/startup_ch32v30x_D8.S @@ -0,0 +1,356 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : startup_ch32v30x_D8.s +* Author : WCH +* Version : V1.0.2 +* Date : 2025/03/06 +* Description : CH32V303x vector table for eclipse toolchain. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + + .section .init,"ax",@progbits + .global _start + .align 1 +_start: + j handle_reset + + .section .vector,"ax",@progbits + .align 1 +_vector_base: + .option norvc; + .word _start + .word 0 + .word NMI_Handler /* NMI */ + .word HardFault_Handler /* Hard Fault */ + .word 0 + .word Ecall_M_Mode_Handler /* Ecall M Mode */ + .word 0 + .word 0 + .word Ecall_U_Mode_Handler /* Ecall U Mode */ + .word Break_Point_Handler /* Break Point */ + .word 0 + .word 0 + .word SysTick_Handler /* SysTick */ + .word 0 + .word SW_Handler /* SW */ + .word 0 + /* External Interrupts */ + .word WWDG_IRQHandler /* Window Watchdog */ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ + .word TAMPER_IRQHandler /* TAMPER */ + .word RTC_IRQHandler /* RTC */ + .word FLASH_IRQHandler /* Flash */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line 0 */ + .word EXTI1_IRQHandler /* EXTI Line 1 */ + .word EXTI2_IRQHandler /* EXTI Line 2 */ + .word EXTI3_IRQHandler /* EXTI Line 3 */ + .word EXTI4_IRQHandler /* EXTI Line 4 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC1_2_IRQHandler /* ADC1_2 */ + .word USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */ + .word USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ + .word TIM1_UP_IRQHandler /* TIM1 Update */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ + .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ + .word 0 + .word TIM8_BRK_IRQHandler /* TIM8 Break */ + .word TIM8_UP_IRQHandler /* TIM8 Update */ + .word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word RNG_IRQHandler /* RNG */ + .word 0 + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ + .word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ + .word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word USBFS_IRQHandler /* USBFS */ + .word 0 + .word 0 + .word 0 + .word UART6_IRQHandler /* UART6 */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word TIM9_BRK_IRQHandler /* TIM9 Break */ + .word TIM9_UP_IRQHandler /* TIM9 Update */ + .word TIM9_TRG_COM_IRQHandler /* TIM9 Trigger and Commutation */ + .word TIM9_CC_IRQHandler /* TIM9 Capture Compare */ + .word TIM10_BRK_IRQHandler /* TIM10 Break */ + .word TIM10_UP_IRQHandler /* TIM10 Update */ + .word TIM10_TRG_COM_IRQHandler /* TIM10 Trigger and Commutation */ + .word TIM10_CC_IRQHandler /* TIM10 Capture Compare */ + .word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ + .word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ + .word DMA2_Channel8_IRQHandler /* DMA2 Channel 8 */ + .word DMA2_Channel9_IRQHandler /* DMA2 Channel 9 */ + .word DMA2_Channel10_IRQHandler /* DMA2 Channel 10 */ + .word DMA2_Channel11_IRQHandler /* DMA2 Channel 11 */ + + .option rvc; + .section .text.vector_handler, "ax", @progbits + .weak NMI_Handler /* NMI */ + .weak HardFault_Handler /* Hard Fault */ + .weak Ecall_M_Mode_Handler /* Ecall M Mode */ + .weak Ecall_U_Mode_Handler /* Ecall U Mode */ + .weak Break_Point_Handler /* Break Point */ + .weak SysTick_Handler /* SysTick */ + .weak SW_Handler /* SW */ + .weak WWDG_IRQHandler /* Window Watchdog */ + .weak PVD_IRQHandler /* PVD through EXTI Line detect */ + .weak TAMPER_IRQHandler /* TAMPER */ + .weak RTC_IRQHandler /* RTC */ + .weak FLASH_IRQHandler /* Flash */ + .weak RCC_IRQHandler /* RCC */ + .weak EXTI0_IRQHandler /* EXTI Line 0 */ + .weak EXTI1_IRQHandler /* EXTI Line 1 */ + .weak EXTI2_IRQHandler /* EXTI Line 2 */ + .weak EXTI3_IRQHandler /* EXTI Line 3 */ + .weak EXTI4_IRQHandler /* EXTI Line 4 */ + .weak DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .weak DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .weak DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .weak DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .weak DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .weak DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .weak DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .weak ADC1_2_IRQHandler /* ADC1_2 */ + .weak USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */ + .weak USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */ + .weak CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .weak CAN1_SCE_IRQHandler /* CAN1 SCE */ + .weak EXTI9_5_IRQHandler /* EXTI Line 9..5 */ + .weak TIM1_BRK_IRQHandler /* TIM1 Break */ + .weak TIM1_UP_IRQHandler /* TIM1 Update */ + .weak TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .weak TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .weak TIM2_IRQHandler /* TIM2 */ + .weak TIM3_IRQHandler /* TIM3 */ + .weak TIM4_IRQHandler /* TIM4 */ + .weak I2C1_EV_IRQHandler /* I2C1 Event */ + .weak I2C1_ER_IRQHandler /* I2C1 Error */ + .weak I2C2_EV_IRQHandler /* I2C2 Event */ + .weak I2C2_ER_IRQHandler /* I2C2 Error */ + .weak SPI1_IRQHandler /* SPI1 */ + .weak SPI2_IRQHandler /* SPI2 */ + .weak USART1_IRQHandler /* USART1 */ + .weak USART2_IRQHandler /* USART2 */ + .weak USART3_IRQHandler /* USART3 */ + .weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */ + .weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ + .weak TIM8_BRK_IRQHandler /* TIM8 Break */ + .weak TIM8_UP_IRQHandler /* TIM8 Update */ + .weak TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */ + .weak TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .weak RNG_IRQHandler /* RNG */ + .weak SDIO_IRQHandler /* SDIO */ + .weak TIM5_IRQHandler /* TIM5 */ + .weak SPI3_IRQHandler /* SPI3 */ + .weak UART4_IRQHandler /* UART4 */ + .weak UART5_IRQHandler /* UART5 */ + .weak TIM6_IRQHandler /* TIM6 */ + .weak TIM7_IRQHandler /* TIM7 */ + .weak DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ + .weak DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ + .weak DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ + .weak DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ + .weak DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ + .weak USBFS_IRQHandler /* USBFS */ + .weak UART6_IRQHandler /* UART6 */ + .weak UART7_IRQHandler /* UART7 */ + .weak UART8_IRQHandler /* UART8 */ + .weak TIM9_BRK_IRQHandler /* TIM9 Break */ + .weak TIM9_UP_IRQHandler /* TIM9 Update */ + .weak TIM9_TRG_COM_IRQHandler /* TIM9 Trigger and Commutation */ + .weak TIM9_CC_IRQHandler /* TIM9 Capture Compare */ + .weak TIM10_BRK_IRQHandler /* TIM10 Break */ + .weak TIM10_UP_IRQHandler /* TIM10 Update */ + .weak TIM10_TRG_COM_IRQHandler /* TIM10 Trigger and Commutation */ + .weak TIM10_CC_IRQHandler /* TIM10 Capture Compare */ + .weak DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ + .weak DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ + .weak DMA2_Channel8_IRQHandler /* DMA2 Channel 8 */ + .weak DMA2_Channel9_IRQHandler /* DMA2 Channel 9 */ + .weak DMA2_Channel10_IRQHandler /* DMA2 Channel 10 */ + .weak DMA2_Channel11_IRQHandler /* DMA2 Channel 11 */ + +NMI_Handler: +HardFault_Handler: +Ecall_M_Mode_Handler: +Ecall_U_Mode_Handler: +Break_Point_Handler: +SysTick_Handler: +SW_Handler: +WWDG_IRQHandler: +PVD_IRQHandler: +TAMPER_IRQHandler: +RTC_IRQHandler: +FLASH_IRQHandler: +RCC_IRQHandler: +EXTI0_IRQHandler: +EXTI1_IRQHandler: +EXTI2_IRQHandler: +EXTI3_IRQHandler: +EXTI4_IRQHandler: +DMA1_Channel1_IRQHandler: +DMA1_Channel2_IRQHandler: +DMA1_Channel3_IRQHandler: +DMA1_Channel4_IRQHandler: +DMA1_Channel5_IRQHandler: +DMA1_Channel6_IRQHandler: +DMA1_Channel7_IRQHandler: +ADC1_2_IRQHandler: +USB_HP_CAN1_TX_IRQHandler: +USB_LP_CAN1_RX0_IRQHandler: +CAN1_RX1_IRQHandler: +CAN1_SCE_IRQHandler: +EXTI9_5_IRQHandler: +TIM1_BRK_IRQHandler: +TIM1_UP_IRQHandler: +TIM1_TRG_COM_IRQHandler: +TIM1_CC_IRQHandler: +TIM2_IRQHandler: +TIM3_IRQHandler: +TIM4_IRQHandler: +I2C1_EV_IRQHandler: +I2C1_ER_IRQHandler: +I2C2_EV_IRQHandler: +I2C2_ER_IRQHandler: +SPI1_IRQHandler: +SPI2_IRQHandler: +USART1_IRQHandler: +USART2_IRQHandler: +USART3_IRQHandler: +EXTI15_10_IRQHandler: +RTCAlarm_IRQHandler: +TIM8_BRK_IRQHandler: +TIM8_UP_IRQHandler: +TIM8_TRG_COM_IRQHandler: +TIM8_CC_IRQHandler: +RNG_IRQHandler: +SDIO_IRQHandler: +TIM5_IRQHandler: +SPI3_IRQHandler: +UART4_IRQHandler: +UART5_IRQHandler: +TIM6_IRQHandler: +TIM7_IRQHandler: +DMA2_Channel1_IRQHandler: +DMA2_Channel2_IRQHandler: +DMA2_Channel3_IRQHandler: +DMA2_Channel4_IRQHandler: +DMA2_Channel5_IRQHandler: +USBFS_IRQHandler: +UART6_IRQHandler: +UART7_IRQHandler: +UART8_IRQHandler: +TIM9_BRK_IRQHandler: +TIM9_UP_IRQHandler: +TIM9_TRG_COM_IRQHandler: +TIM9_CC_IRQHandler: +TIM10_BRK_IRQHandler: +TIM10_UP_IRQHandler: +TIM10_TRG_COM_IRQHandler: +TIM10_CC_IRQHandler: +DMA2_Channel6_IRQHandler: +DMA2_Channel7_IRQHandler: +DMA2_Channel8_IRQHandler: +DMA2_Channel9_IRQHandler: +DMA2_Channel10_IRQHandler: +DMA2_Channel11_IRQHandler: +1: + j 1b + + .section .text.handle_reset,"ax",@progbits + .weak handle_reset + .align 1 +handle_reset: +.option push +.option norelax + la gp, __global_pointer$ +.option pop + + la sp, _eusrstack + +/* Load data section from flash to RAM */ + la a0, _data_lma + la a1, _data_vma + la a2, _edata + bgeu a1, a2, 2f +1: + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, 1b +2: +/* Clear bss section */ + la a0, _sbss + la a1, _ebss + bgeu a0, a1, 2f +1: + sw zero, (a0) + addi a0, a0, 4 + bltu a0, a1, 1b +2: +/* Configure pipelining and instruction prediction */ + li t0, 0x1f + csrw 0xbc0, t0 +/* Enable interrupt nesting and hardware stack */ + li t0, 0x0b + csrw 0x804, t0 +/* Enable floating point and global interrupt, configure privileged mode */ + li t0, 0x6088 + csrw mstatus, t0 +/* Configure the interrupt vector table recognition mode and entry address mode */ + la t0, _vector_base + ori t0, t0, 3 + csrw mtvec, t0 + + jal SystemInit + la t0, main + csrw mepc, t0 + mret + + + + diff --git a/Startup/startup_ch32v30x_D8C.S b/Startup/startup_ch32v30x_D8C.S new file mode 100644 index 0000000..17c4f8e --- /dev/null +++ b/Startup/startup_ch32v30x_D8C.S @@ -0,0 +1,374 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : startup_ch32v30x_D8C.s +* Author : WCH +* Version : V1.0.1 +* Date : 2025/04/06 +* Description : CH32V307x-CH32V305x vector table for eclipse toolchain. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + + .section .init,"ax",@progbits + .global _start + .align 1 +_start: + j handle_reset + + .section .vector,"ax",@progbits + .align 1 +_vector_base: + .option norvc; + .word _start + .word 0 + .word NMI_Handler /* NMI */ + .word HardFault_Handler /* Hard Fault */ + .word 0 + .word Ecall_M_Mode_Handler /* Ecall M Mode */ + .word 0 + .word 0 + .word Ecall_U_Mode_Handler /* Ecall U Mode */ + .word Break_Point_Handler /* Break Point */ + .word 0 + .word 0 + .word SysTick_Handler /* SysTick */ + .word 0 + .word SW_Handler /* SW */ + .word 0 + /* External Interrupts */ + .word WWDG_IRQHandler /* Window Watchdog */ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ + .word TAMPER_IRQHandler /* TAMPER */ + .word RTC_IRQHandler /* RTC */ + .word FLASH_IRQHandler /* Flash */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line 0 */ + .word EXTI1_IRQHandler /* EXTI Line 1 */ + .word EXTI2_IRQHandler /* EXTI Line 2 */ + .word EXTI3_IRQHandler /* EXTI Line 3 */ + .word EXTI4_IRQHandler /* EXTI Line 4 */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .word ADC1_2_IRQHandler /* ADC1_2 */ + .word USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */ + .word USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */ + .word TIM1_BRK_IRQHandler /* TIM1 Break */ + .word TIM1_UP_IRQHandler /* TIM1 Update */ + .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ + .word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ + .word USBWakeUp_IRQHandler /* USB Wakeup from suspend */ + .word TIM8_BRK_IRQHandler /* TIM8 Break */ + .word TIM8_UP_IRQHandler /* TIM8 Update */ + .word TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word RNG_IRQHandler /* RNG */ + .word 0 + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ + .word DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ + .word DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ + .word DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ + .word DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ + .word ETH_IRQHandler /* ETH */ + .word ETH_WKUP_IRQHandler /* ETH WakeUp */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word USBFS_IRQHandler /* USBFS */ + .word USBHSWakeup_IRQHandler /* USBHS Wakeup */ + .word USBHS_IRQHandler /* USBHS */ + .word DVP_IRQHandler /* DVP */ + .word UART6_IRQHandler /* UART6 */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word TIM9_BRK_IRQHandler /* TIM9 Break */ + .word TIM9_UP_IRQHandler /* TIM9 Update */ + .word TIM9_TRG_COM_IRQHandler /* TIM9 Trigger and Commutation */ + .word TIM9_CC_IRQHandler /* TIM9 Capture Compare */ + .word TIM10_BRK_IRQHandler /* TIM10 Break */ + .word TIM10_UP_IRQHandler /* TIM10 Update */ + .word TIM10_TRG_COM_IRQHandler /* TIM10 Trigger and Commutation */ + .word TIM10_CC_IRQHandler /* TIM10 Capture Compare */ + .word DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ + .word DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ + .word DMA2_Channel8_IRQHandler /* DMA2 Channel 8 */ + .word DMA2_Channel9_IRQHandler /* DMA2 Channel 9 */ + .word DMA2_Channel10_IRQHandler /* DMA2 Channel 10 */ + .word DMA2_Channel11_IRQHandler /* DMA2 Channel 11 */ + + .option rvc; + .section .text.vector_handler, "ax", @progbits + .weak NMI_Handler /* NMI */ + .weak HardFault_Handler /* Hard Fault */ + .weak Ecall_M_Mode_Handler /* Ecall M Mode */ + .weak Ecall_U_Mode_Handler /* Ecall U Mode */ + .weak Break_Point_Handler /* Break Point */ + .weak SysTick_Handler /* SysTick */ + .weak SW_Handler /* SW */ + .weak WWDG_IRQHandler /* Window Watchdog */ + .weak PVD_IRQHandler /* PVD through EXTI Line detect */ + .weak TAMPER_IRQHandler /* TAMPER */ + .weak RTC_IRQHandler /* RTC */ + .weak FLASH_IRQHandler /* Flash */ + .weak RCC_IRQHandler /* RCC */ + .weak EXTI0_IRQHandler /* EXTI Line 0 */ + .weak EXTI1_IRQHandler /* EXTI Line 1 */ + .weak EXTI2_IRQHandler /* EXTI Line 2 */ + .weak EXTI3_IRQHandler /* EXTI Line 3 */ + .weak EXTI4_IRQHandler /* EXTI Line 4 */ + .weak DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .weak DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + .weak DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + .weak DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + .weak DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + .weak DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + .weak DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + .weak ADC1_2_IRQHandler /* ADC1_2 */ + .weak USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */ + .weak USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */ + .weak CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .weak CAN1_SCE_IRQHandler /* CAN1 SCE */ + .weak EXTI9_5_IRQHandler /* EXTI Line 9..5 */ + .weak TIM1_BRK_IRQHandler /* TIM1 Break */ + .weak TIM1_UP_IRQHandler /* TIM1 Update */ + .weak TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + .weak TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .weak TIM2_IRQHandler /* TIM2 */ + .weak TIM3_IRQHandler /* TIM3 */ + .weak TIM4_IRQHandler /* TIM4 */ + .weak I2C1_EV_IRQHandler /* I2C1 Event */ + .weak I2C1_ER_IRQHandler /* I2C1 Error */ + .weak I2C2_EV_IRQHandler /* I2C2 Event */ + .weak I2C2_ER_IRQHandler /* I2C2 Error */ + .weak SPI1_IRQHandler /* SPI1 */ + .weak SPI2_IRQHandler /* SPI2 */ + .weak USART1_IRQHandler /* USART1 */ + .weak USART2_IRQHandler /* USART2 */ + .weak USART3_IRQHandler /* USART3 */ + .weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */ + .weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ + .weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */ + .weak TIM8_BRK_IRQHandler /* TIM8 Break */ + .weak TIM8_UP_IRQHandler /* TIM8 Update */ + .weak TIM8_TRG_COM_IRQHandler /* TIM8 Trigger and Commutation */ + .weak TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .weak RNG_IRQHandler /* RNG */ + .weak SDIO_IRQHandler /* SDIO */ + .weak TIM5_IRQHandler /* TIM5 */ + .weak SPI3_IRQHandler /* SPI3 */ + .weak UART4_IRQHandler /* UART4 */ + .weak UART5_IRQHandler /* UART5 */ + .weak TIM6_IRQHandler /* TIM6 */ + .weak TIM7_IRQHandler /* TIM7 */ + .weak DMA2_Channel1_IRQHandler /* DMA2 Channel 1 */ + .weak DMA2_Channel2_IRQHandler /* DMA2 Channel 2 */ + .weak DMA2_Channel3_IRQHandler /* DMA2 Channel 3 */ + .weak DMA2_Channel4_IRQHandler /* DMA2 Channel 4 */ + .weak DMA2_Channel5_IRQHandler /* DMA2 Channel 5 */ + .weak ETH_IRQHandler /* ETH */ + .weak ETH_WKUP_IRQHandler /* ETH WakeUp */ + .weak CAN2_TX_IRQHandler /* CAN2 TX */ + .weak CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .weak CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .weak CAN2_SCE_IRQHandler /* CAN2 SCE */ + .weak USBFS_IRQHandler /* USBFS */ + .weak USBHSWakeup_IRQHandler /* USBHS Wakeup */ + .weak USBHS_IRQHandler /* USBHS */ + .weak DVP_IRQHandler /* DVP */ + .weak UART6_IRQHandler /* UART6 */ + .weak UART7_IRQHandler /* UART7 */ + .weak UART8_IRQHandler /* UART8 */ + .weak TIM9_BRK_IRQHandler /* TIM9 Break */ + .weak TIM9_UP_IRQHandler /* TIM9 Update */ + .weak TIM9_TRG_COM_IRQHandler /* TIM9 Trigger and Commutation */ + .weak TIM9_CC_IRQHandler /* TIM9 Capture Compare */ + .weak TIM10_BRK_IRQHandler /* TIM10 Break */ + .weak TIM10_UP_IRQHandler /* TIM10 Update */ + .weak TIM10_TRG_COM_IRQHandler /* TIM10 Trigger and Commutation */ + .weak TIM10_CC_IRQHandler /* TIM10 Capture Compare */ + .weak DMA2_Channel6_IRQHandler /* DMA2 Channel 6 */ + .weak DMA2_Channel7_IRQHandler /* DMA2 Channel 7 */ + .weak DMA2_Channel8_IRQHandler /* DMA2 Channel 8 */ + .weak DMA2_Channel9_IRQHandler /* DMA2 Channel 9 */ + .weak DMA2_Channel10_IRQHandler /* DMA2 Channel 10 */ + .weak DMA2_Channel11_IRQHandler /* DMA2 Channel 11 */ + +NMI_Handler: +HardFault_Handler: +Ecall_M_Mode_Handler: +Ecall_U_Mode_Handler: +Break_Point_Handler: +SysTick_Handler: +SW_Handler: +WWDG_IRQHandler: +PVD_IRQHandler: +TAMPER_IRQHandler: +RTC_IRQHandler: +FLASH_IRQHandler: +RCC_IRQHandler: +EXTI0_IRQHandler: +EXTI1_IRQHandler: +EXTI2_IRQHandler: +EXTI3_IRQHandler: +EXTI4_IRQHandler: +DMA1_Channel1_IRQHandler: +DMA1_Channel2_IRQHandler: +DMA1_Channel3_IRQHandler: +DMA1_Channel4_IRQHandler: +DMA1_Channel5_IRQHandler: +DMA1_Channel6_IRQHandler: +DMA1_Channel7_IRQHandler: +ADC1_2_IRQHandler: +USB_HP_CAN1_TX_IRQHandler: +USB_LP_CAN1_RX0_IRQHandler: +CAN1_RX1_IRQHandler: +CAN1_SCE_IRQHandler: +EXTI9_5_IRQHandler: +TIM1_BRK_IRQHandler: +TIM1_UP_IRQHandler: +TIM1_TRG_COM_IRQHandler: +TIM1_CC_IRQHandler: +TIM2_IRQHandler: +TIM3_IRQHandler: +TIM4_IRQHandler: +I2C1_EV_IRQHandler: +I2C1_ER_IRQHandler: +I2C2_EV_IRQHandler: +I2C2_ER_IRQHandler: +SPI1_IRQHandler: +SPI2_IRQHandler: +USART1_IRQHandler: +USART2_IRQHandler: +USART3_IRQHandler: +EXTI15_10_IRQHandler: +RTCAlarm_IRQHandler: +USBWakeUp_IRQHandler: +TIM8_BRK_IRQHandler: +TIM8_UP_IRQHandler: +TIM8_TRG_COM_IRQHandler: +TIM8_CC_IRQHandler: +RNG_IRQHandler: +SDIO_IRQHandler: +TIM5_IRQHandler: +SPI3_IRQHandler: +UART4_IRQHandler: +UART5_IRQHandler: +TIM6_IRQHandler: +TIM7_IRQHandler: +DMA2_Channel1_IRQHandler: +DMA2_Channel2_IRQHandler: +DMA2_Channel3_IRQHandler: +DMA2_Channel4_IRQHandler: +DMA2_Channel5_IRQHandler: +ETH_IRQHandler: +ETH_WKUP_IRQHandler: +CAN2_TX_IRQHandler: +CAN2_RX0_IRQHandler: +CAN2_RX1_IRQHandler: +CAN2_SCE_IRQHandler: +USBFS_IRQHandler: +USBHSWakeup_IRQHandler: +USBHS_IRQHandler: +DVP_IRQHandler: +UART6_IRQHandler: +UART7_IRQHandler: +UART8_IRQHandler: +TIM9_BRK_IRQHandler: +TIM9_UP_IRQHandler: +TIM9_TRG_COM_IRQHandler: +TIM9_CC_IRQHandler: +TIM10_BRK_IRQHandler: +TIM10_UP_IRQHandler: +TIM10_TRG_COM_IRQHandler: +TIM10_CC_IRQHandler: +DMA2_Channel6_IRQHandler: +DMA2_Channel7_IRQHandler: +DMA2_Channel8_IRQHandler: +DMA2_Channel9_IRQHandler: +DMA2_Channel10_IRQHandler: +DMA2_Channel11_IRQHandler: +1: + j 1b + + .section .text.handle_reset,"ax",@progbits + .weak handle_reset + .align 1 +handle_reset: +.option push +.option norelax + la gp, __global_pointer$ +.option pop + + la sp, _eusrstack + +/* Load data section from flash to RAM */ + la a0, _data_lma + la a1, _data_vma + la a2, _edata + bgeu a1, a2, 2f +1: + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, 1b +2: +/* Clear bss section */ + la a0, _sbss + la a1, _ebss + bgeu a0, a1, 2f +1: + sw zero, (a0) + addi a0, a0, 4 + bltu a0, a1, 1b +2: +/* Configure pipelining and instruction prediction */ + li t0, 0x1f + csrw 0xbc0, t0 +/* Enable interrupt nesting and hardware stack */ + li t0, 0x0b + csrw 0x804, t0 +/* Enable floating point and global interrupt, configure privileged mode */ + li t0, 0x6088 + csrw mstatus, t0 +/* Configure the interrupt vector table recognition mode and entry address mode */ + la t0, _vector_base + ori t0, t0, 3 + csrw mtvec, t0 + + jal SystemInit + la t0, main + csrw mepc, t0 + mret + + diff --git a/User/ch32v30x_conf.h b/User/ch32v30x_conf.h new file mode 100644 index 0000000..bfd19b3 --- /dev/null +++ b/User/ch32v30x_conf.h @@ -0,0 +1,45 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_conf.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : Library configuration file. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_CONF_H +#define __CH32V30x_CONF_H + +#include "ch32v30x_adc.h" +#include "ch32v30x_bkp.h" +#include "ch32v30x_can.h" +#include "ch32v30x_crc.h" +#include "ch32v30x_dac.h" +#include "ch32v30x_dbgmcu.h" +#include "ch32v30x_dma.h" +#include "ch32v30x_exti.h" +#include "ch32v30x_flash.h" +#include "ch32v30x_fsmc.h" +#include "ch32v30x_gpio.h" +#include "ch32v30x_i2c.h" +#include "ch32v30x_iwdg.h" +#include "ch32v30x_pwr.h" +#include "ch32v30x_rcc.h" +#include "ch32v30x_rtc.h" +#include "ch32v30x_sdio.h" +#include "ch32v30x_spi.h" +#include "ch32v30x_tim.h" +#include "ch32v30x_usart.h" +#include "ch32v30x_wwdg.h" +#include "ch32v30x_it.h" +#include "ch32v30x_misc.h" + + +#endif /* __CH32V30x_CONF_H */ + + + + + diff --git a/User/ch32v30x_it.c b/User/ch32v30x_it.c new file mode 100644 index 0000000..6f31e0b --- /dev/null +++ b/User/ch32v30x_it.c @@ -0,0 +1,46 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_it.c +* Author : WCH +* Version : V1.0.0 +* Date : 2024/03/06 +* Description : Main Interrupt Service Routines. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x_it.h" + +void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); +void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); + +/********************************************************************* + * @fn NMI_Handler + * + * @brief This function handles NMI exception. + * + * @return none + */ +void NMI_Handler(void) +{ + while (1) + { + } +} + +/********************************************************************* + * @fn HardFault_Handler + * + * @brief This function handles Hard Fault exception. + * + * @return none + */ +void HardFault_Handler(void) +{ + NVIC_SystemReset(); + while (1) + { + } +} + + diff --git a/User/ch32v30x_it.h b/User/ch32v30x_it.h new file mode 100644 index 0000000..d9b111a --- /dev/null +++ b/User/ch32v30x_it.h @@ -0,0 +1,20 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : ch32v30x_it.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : This file contains the headers of the interrupt handlers. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V30x_IT_H +#define __CH32V30x_IT_H + +#include "debug.h" + + +#endif /* __CH32V30x_IT_H */ + + diff --git a/User/lib/adc/temperature.c b/User/lib/adc/temperature.c new file mode 100644 index 0000000..d8026aa --- /dev/null +++ b/User/lib/adc/temperature.c @@ -0,0 +1,253 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : temperature.c +* Author : WCH +* Version : V1.0.0 +* Date : 2023/11/17 +* Description : Temperature program body. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + +/* + *@Note + *Internal temperature sensor routine: + *Through the ADC channel 16, the output voltage value and temperature value of the internal + *temperature sensor are collected. + * + */ + +#include "debug.h" +#include "lib/telemetry/telemetry.h" + +/* Global Variable */ +int16_t Calibrattion_Val = 0; + +/********************************************************************* + * @fn ADC_Function_Init + * + * @brief Initializes ADC collection. + * + * @return none + */ +void ADC_Function_Init(void) +{ + ADC_InitTypeDef ADC_InitStructure={0}; + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE ); + RCC_ADCCLKConfig(RCC_PCLK2_Div8); + + ADC_DeInit(ADC1); + ADC_InitStructure.ADC_Mode = ADC_Mode_Independent; + ADC_InitStructure.ADC_ScanConvMode = DISABLE; + ADC_InitStructure.ADC_ContinuousConvMode = DISABLE; + ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_None; + ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStructure.ADC_NbrOfChannel = 1; + ADC_Init(ADC1, &ADC_InitStructure); + + ADC_Cmd(ADC1, ENABLE); + + ADC_BufferCmd(ADC1, DISABLE); //disable buffer + ADC_ResetCalibration(ADC1); + while(ADC_GetResetCalibrationStatus(ADC1)); + ADC_StartCalibration(ADC1); + while(ADC_GetCalibrationStatus(ADC1)); + Calibrattion_Val = Get_CalibrationValue(ADC1); + + ADC_BufferCmd(ADC1, ENABLE); //enable buffer + + ADC_TempSensorVrefintCmd(ENABLE); +} + +/********************************************************************* + * @fn Get_ADC_Val + * + * @brief Returns ADCx conversion result data. + * + * @param ch - ADC channel. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * + * @return none + */ +uint16_t Get_ADC_Val(uint8_t ch) +{ + uint16_t val; + + ADC_RegularChannelConfig(ADC1, ch, 1, ADC_SampleTime_239Cycles5 ); + ADC_SoftwareStartConvCmd(ADC1, ENABLE); + + while(!ADC_GetFlagStatus(ADC1, ADC_FLAG_EOC )); + + val = ADC_GetConversionValue(ADC1); + + return val; +} + +/********************************************************************* + * @fn Get_ADC_Average + * + * @brief Returns ADCx conversion result average data. + * + * @param ch - ADC channel. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * + * @return val - The Data conversion value. + */ +uint16_t Get_ADC_Average(uint8_t ch,uint8_t times) +{ + u32 temp_val=0; + uint8_t t; + uint16_t val; + + for(t=0;t4095||val==4095) return 4095; + return (val+Calibrattion_Val); +} + +s32 TempSensor_Volt_To_Temper_x10(s32 Value) +{ + s32 Temper_x10; + s32 Refer_Volt, Refer_Temper; + s32 k = 43; // slope in mV/¡ãC + + // Read factory calibration values + Refer_Volt = (s32)((*(u32 *)0x1FFFF720) & 0x0000FFFF); // mV at reference temp + Refer_Temper = (s32)(((*(u32 *)0x1FFFF720) >> 16) & 0x0000FFFF); // ¡ãC + + // Compute temperature in decicelsius + // Formula: T_x10 = Tref*10 - ((V - Vref)*100 + k/2) / k + // Multiply (V - Vref) by 100 to get tenths of ¡ãC + Temper_x10 = Refer_Temper * 10 - ((Value - Refer_Volt) * 100 + (k / 2)) / k; + + return Temper_x10; +} + + +s32 getTemperature(void) +{ + uint16_t ADC_val; + s32 val_mv; + + ADC_val = Get_ADC_Average( ADC_Channel_TempSensor, 10 ); + + ADC_val = Get_ConversionVal(ADC_val); + + val_mv = (ADC_val*3300/4096); + + return TempSensor_Volt_To_Temper(val_mv); +} + +int16_t getDeciTemperature(void) +{ + uint16_t ADC_val; + s32 val_mv; + + ADC_val = Get_ADC_Average( ADC_Channel_TempSensor, 10 ); + + ADC_val = Get_ConversionVal(ADC_val); + + val_mv = (ADC_val*3300/4096); + + s32 temp_x10 = TempSensor_Volt_To_Temper_x10(val_mv); + + int16_t temp16 = (int16_t)temp_x10; // store in 2 bytes + return temp16; +} + +s32 getVoltage(void) +{ + uint16_t ADC_val; + s32 val_mv; + + ADC_val = Get_ADC_Average( ADC_Channel_1, 10 ); + + ADC_val = Get_ConversionVal(ADC_val); + + + val_mv = (ADC_val*3300/4096); + + return val_mv; +} + +// Helper: convert signed 24-bit int to 3 bytes (big-endian) +void int24_to_bytes(int32_t value, uint8_t *bytes) { + if (value < 0) value += 0x1000000; // 2's complement for 24-bit + bytes[0] = (value >> 16) & 0xFF; + bytes[1] = (value >> 8) & 0xFF; + bytes[2] = value & 0xFF; +} + +// Encode GPS into CayenneLPP payload +void encode_gps(uint8_t channel, int32_t lat, int32_t lon, int32_t alt, uint8_t *payload) { + payload[0] = channel; + payload[1] = LPP_GPS; // GPS type + + //int32_t latInt = lat * 10000; + //int32_t lonInt = lon * 10000; + //int32_t altInt = alt * 100; + + int24_to_bytes(lat, &payload[2]); + int24_to_bytes(lon, &payload[5]); + int24_to_bytes(alt, &payload[8]); + //int24_to_bytes(latInt, &payload[2]); + //int24_to_bytes(lonInt, &payload[5]); + //int24_to_bytes(altInt, &payload[8]); +} \ No newline at end of file diff --git a/User/lib/adc/temperature.h b/User/lib/adc/temperature.h new file mode 100644 index 0000000..3ebf256 --- /dev/null +++ b/User/lib/adc/temperature.h @@ -0,0 +1,113 @@ +#ifndef TEMPERATURE_HEADER +#define TEMPERATURE_HEADER + +/********************************** (C) COPYRIGHT ******************************* +* File Name : temperature.c +* Author : WCH +* Version : V1.0.0 +* Date : 2023/11/17 +* Description : Temperature program body. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ + +/* + *@Note + *Internal temperature sensor routine: + *Through the ADC channel 16, the output voltage value and temperature value of the internal + *temperature sensor are collected. + * + */ + +/* Global Variable */ +extern int16_t Calibrattion_Val; + +/********************************************************************* + * @fn ADC_Function_Init + * + * @brief Initializes ADC collection. + * + * @return none + */ +void ADC_Function_Init(void); + +/********************************************************************* + * @fn Get_ADC_Val + * + * @brief Returns ADCx conversion result data. + * + * @param ch - ADC channel. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * + * @return none + */ +uint16_t Get_ADC_Val(uint8_t ch); + +/********************************************************************* + * @fn Get_ADC_Average + * + * @brief Returns ADCx conversion result average data. + * + * @param ch - ADC channel. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * + * @return val - The Data conversion value. + */ +uint16_t Get_ADC_Average(uint8_t ch,uint8_t times); + +/********************************************************************* + * @fn Get_ConversionVal + * + * @brief Get Conversion Value. + * + * @param val - Sampling value + * + * @return val+Calibrattion_Val - Conversion Value. + */ +uint16_t Get_ConversionVal(int16_t val); + +int32_t getTemperature(void); + +int16_t getDeciTemperature(void); + +int32_t getVoltage(void); + +void encode_gps(uint8_t channel, int32_t lat, int32_t lon, int32_t alt, uint8_t *payload); + +#endif \ No newline at end of file diff --git a/User/lib/base64.c b/User/lib/base64.c new file mode 100644 index 0000000..a9a97ef --- /dev/null +++ b/User/lib/base64.c @@ -0,0 +1,23 @@ +#include "base64.h" + +static const char b64_enc_table[] = + "ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz0123456789+/"; + +void base64_encode (const uint8_t *in, size_t ilen, char *out) { + size_t out_len = 0; + for (size_t i = 0; i < ilen; i += 3) { + uint32_t triple = 0; + int remain = ilen - i; + + triple |= in[i] << 16; + if (remain > 1) + triple |= in[i + 1] << 8; + if (remain > 2) + triple |= in[i + 2]; + + out[out_len++] = b64_enc_table[(triple >> 18) & 0x3F]; + out[out_len++] = b64_enc_table[(triple >> 12) & 0x3F]; + out[out_len++] = (remain > 1) ? b64_enc_table[(triple >> 6) & 0x3F] : '='; + out[out_len++] = (remain > 2) ? b64_enc_table[triple & 0x3F] : '='; + } +} diff --git a/User/lib/base64.h b/User/lib/base64.h new file mode 100644 index 0000000..70f79e6 --- /dev/null +++ b/User/lib/base64.h @@ -0,0 +1,8 @@ +#ifndef BASE64_HEADER_FILE +#define BASE64_HEADER_FILE +#include +#include + +void base64_encode (const uint8_t *in, size_t ilen, char *out); + +#endif \ No newline at end of file diff --git a/User/lib/cifra/aes.c b/User/lib/cifra/aes.c new file mode 100644 index 0000000..bbdad88 --- /dev/null +++ b/User/lib/cifra/aes.c @@ -0,0 +1,415 @@ +/* + * cifra - embedded cryptography library + * Written in 2014 by Joseph Birr-Pixton + * + * To the extent possible under law, the author(s) have dedicated all + * copyright and related and neighboring rights to this software to the + * public domain worldwide. This software is distributed without any + * warranty. + * + * You should have received a copy of the CC0 Public Domain Dedication + * along with this software. If not, see + * . + */ + +#include +#include + +#include "cf_config.h" +#include "aes.h" +#include "handy.h" +#include "bitops.h" +#include "tassert.h" + +static const uint8_t S[256] = + { + 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5, 0x30, 0x01, 0x67, 0x2b, 0xfe, + 0xd7, 0xab, 0x76, 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0, 0xad, 0xd4, + 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0, 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, + 0xcc, 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15, 0x04, 0xc7, 0x23, 0xc3, + 0x18, 0x96, 0x05, 0x9a, 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75, 0x09, + 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0, 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, + 0x2f, 0x84, 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b, 0x6a, 0xcb, 0xbe, + 0x39, 0x4a, 0x4c, 0x58, 0xcf, 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85, + 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8, 0x51, 0xa3, 0x40, 0x8f, 0x92, + 0x9d, 0x38, 0xf5, 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2, 0xcd, 0x0c, + 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17, 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, + 0x73, 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88, 0x46, 0xee, 0xb8, 0x14, + 0xde, 0x5e, 0x0b, 0xdb, 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c, 0xc2, + 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79, 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, + 0x4e, 0xa9, 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08, 0xba, 0x78, 0x25, + 0x2e, 0x1c, 0xa6, 0xb4, 0xc6, 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a, + 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e, 0x61, 0x35, 0x57, 0xb9, 0x86, + 0xc1, 0x1d, 0x9e, 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94, 0x9b, 0x1e, + 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf, 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, + 0x68, 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16}; + +static const uint8_t Rcon[11] = + { + 0x8d, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0x1b, 0x36}; + +#ifdef INLINE_FUNCS +static inline uint32_t word4 (uint8_t b0, uint8_t b1, uint8_t b2, uint8_t b3) { + return b0 << 24 | b1 << 16 | b2 << 8 | b3; +} + +static inline uint8_t byte (uint32_t w, unsigned x) { + /* nb. bytes are numbered 0 (leftmost, top) + * to 3 (rightmost). */ + x = 3 - x; + return (w >> (x * 8)) & 0xff; +} + +static uint32_t round_constant (uint32_t i) { + return Rcon[i] << 24; +} + +static uint32_t rot_word (uint32_t w) { + /* Takes + * word [a0,a1,a2,a3] + * returns + * word [a1,a2,a3,a0] + * + */ + return rotl32 (w, 8); +} +#endif + +#define word4(a, b, c, d) (((uint32_t)(a) << 24) | ((uint32_t)(b) << 16) | ((uint32_t)(c) << 8) | (d)) +#define byte(w, x) ((w >> ((3 - (x)) << 3)) & 0xff) +#define round_constant(i) ((uint32_t)(Rcon[i]) << 24) +#define rot_word(w) rotl32 ((w), 8) + +static uint32_t sub_word (uint32_t w, const uint8_t *sbox) { + uint8_t a = byte (w, 0), + b = byte (w, 1), + c = byte (w, 2), + d = byte (w, 3); +#if CF_CACHE_SIDE_CHANNEL_PROTECTION + select_u8x4 (&a, &b, &c, &d, sbox, 256); +#else + a = sbox[a]; + b = sbox[b]; + c = sbox[c]; + d = sbox[d]; +#endif + return word4 (a, b, c, d); +} + +static void aes_schedule (cf_aes_context *ctx, const uint8_t *key, size_t nkey) { + size_t i, + nb = AES_BLOCKSZ / 4, + nk = nkey / 4, + n = nb * (ctx->rounds + 1); + uint32_t *w = ctx->ks; + + /* First words are just the key. */ + for (i = 0; i < nk; i++) { + w[i] = read32_be (key + i * 4); + } + + uint32_t i_div_nk = 1; + uint32_t i_mod_nk = 0; + + for (; i < n; i++, i_mod_nk++) { + uint32_t temp = w[i - 1]; + + if (i_mod_nk == nk) { + i_div_nk++; + i_mod_nk = 0; + } + + if (i_mod_nk == 0) + temp = sub_word (rot_word (temp), S) ^ round_constant (i_div_nk); + else if (nk > 6 && i_mod_nk == 4) + temp = sub_word (temp, S); + + w[i] = w[i - nk] ^ temp; + } +} + +void cf_aes_init (cf_aes_context *ctx, const uint8_t *key, size_t nkey) { + memset (ctx, 0, sizeof *ctx); + + switch (nkey) { +#if CF_AES_MAXROUNDS >= AES128_ROUNDS + case 16: + ctx->rounds = AES128_ROUNDS; + aes_schedule (ctx, key, nkey); + break; +#endif + +#if CF_AES_MAXROUNDS >= AES192_ROUNDS + case 24: + ctx->rounds = AES192_ROUNDS; + aes_schedule (ctx, key, nkey); + break; +#endif + +#if CF_AES_MAXROUNDS >= AES256_ROUNDS + case 32: + ctx->rounds = AES256_ROUNDS; + aes_schedule (ctx, key, nkey); + break; +#endif + + default: + abort(); + } +} + +static void add_round_key (uint32_t state[4], const uint32_t rk[4]) { + state[0] ^= rk[0]; + state[1] ^= rk[1]; + state[2] ^= rk[2]; + state[3] ^= rk[3]; +} + +static void sub_block (uint32_t state[4]) { + state[0] = sub_word (state[0], S); + state[1] = sub_word (state[1], S); + state[2] = sub_word (state[2], S); + state[3] = sub_word (state[3], S); +} + +static void shift_rows (uint32_t state[4]) { + uint32_t u, v, x, y; + + u = word4 (byte (state[0], 0), + byte (state[1], 1), + byte (state[2], 2), + byte (state[3], 3)); + + v = word4 (byte (state[1], 0), + byte (state[2], 1), + byte (state[3], 2), + byte (state[0], 3)); + + x = word4 (byte (state[2], 0), + byte (state[3], 1), + byte (state[0], 2), + byte (state[1], 3)); + + y = word4 (byte (state[3], 0), + byte (state[0], 1), + byte (state[1], 2), + byte (state[2], 3)); + + state[0] = u; + state[1] = v; + state[2] = x; + state[3] = y; +} + +static uint32_t gf_poly_mul2 (uint32_t x) { + return ((x & 0x7f7f7f7f) << 1) ^ + (((x & 0x80808080) >> 7) * 0x1b); +} + +static uint32_t mix_column (uint32_t x) { + uint32_t x2 = gf_poly_mul2 (x); + return x2 ^ rotr32 (x ^ x2, 24) ^ rotr32 (x, 16) ^ rotr32 (x, 8); +} + +static void mix_columns (uint32_t state[4]) { + state[0] = mix_column (state[0]); + state[1] = mix_column (state[1]); + state[2] = mix_column (state[2]); + state[3] = mix_column (state[3]); +} + +void cf_aes_encrypt (const cf_aes_context *ctx, + const uint8_t in[AES_BLOCKSZ], + uint8_t out[AES_BLOCKSZ]) { + assert (ctx->rounds == AES128_ROUNDS || + ctx->rounds == AES192_ROUNDS || + ctx->rounds == AES256_ROUNDS); + + uint32_t state[4] = { + read32_be (in + 0), + read32_be (in + 4), + read32_be (in + 8), + read32_be (in + 12)}; + + const uint32_t *round_keys = ctx->ks; + add_round_key (state, round_keys); + round_keys += 4; + + for (uint32_t round = 1; round < ctx->rounds; round++) { + sub_block (state); + shift_rows (state); + mix_columns (state); + add_round_key (state, round_keys); + round_keys += 4; + } + + sub_block (state); + shift_rows (state); + add_round_key (state, round_keys); + + write32_be (state[0], out + 0); + write32_be (state[1], out + 4); + write32_be (state[2], out + 8); + write32_be (state[3], out + 12); +} + +#if CF_AES_ENCRYPT_ONLY == 0 +static const uint8_t S_inv[256] = + { + 0x52, 0x09, 0x6a, 0xd5, 0x30, 0x36, 0xa5, 0x38, 0xbf, 0x40, 0xa3, 0x9e, 0x81, + 0xf3, 0xd7, 0xfb, 0x7c, 0xe3, 0x39, 0x82, 0x9b, 0x2f, 0xff, 0x87, 0x34, 0x8e, + 0x43, 0x44, 0xc4, 0xde, 0xe9, 0xcb, 0x54, 0x7b, 0x94, 0x32, 0xa6, 0xc2, 0x23, + 0x3d, 0xee, 0x4c, 0x95, 0x0b, 0x42, 0xfa, 0xc3, 0x4e, 0x08, 0x2e, 0xa1, 0x66, + 0x28, 0xd9, 0x24, 0xb2, 0x76, 0x5b, 0xa2, 0x49, 0x6d, 0x8b, 0xd1, 0x25, 0x72, + 0xf8, 0xf6, 0x64, 0x86, 0x68, 0x98, 0x16, 0xd4, 0xa4, 0x5c, 0xcc, 0x5d, 0x65, + 0xb6, 0x92, 0x6c, 0x70, 0x48, 0x50, 0xfd, 0xed, 0xb9, 0xda, 0x5e, 0x15, 0x46, + 0x57, 0xa7, 0x8d, 0x9d, 0x84, 0x90, 0xd8, 0xab, 0x00, 0x8c, 0xbc, 0xd3, 0x0a, + 0xf7, 0xe4, 0x58, 0x05, 0xb8, 0xb3, 0x45, 0x06, 0xd0, 0x2c, 0x1e, 0x8f, 0xca, + 0x3f, 0x0f, 0x02, 0xc1, 0xaf, 0xbd, 0x03, 0x01, 0x13, 0x8a, 0x6b, 0x3a, 0x91, + 0x11, 0x41, 0x4f, 0x67, 0xdc, 0xea, 0x97, 0xf2, 0xcf, 0xce, 0xf0, 0xb4, 0xe6, + 0x73, 0x96, 0xac, 0x74, 0x22, 0xe7, 0xad, 0x35, 0x85, 0xe2, 0xf9, 0x37, 0xe8, + 0x1c, 0x75, 0xdf, 0x6e, 0x47, 0xf1, 0x1a, 0x71, 0x1d, 0x29, 0xc5, 0x89, 0x6f, + 0xb7, 0x62, 0x0e, 0xaa, 0x18, 0xbe, 0x1b, 0xfc, 0x56, 0x3e, 0x4b, 0xc6, 0xd2, + 0x79, 0x20, 0x9a, 0xdb, 0xc0, 0xfe, 0x78, 0xcd, 0x5a, 0xf4, 0x1f, 0xdd, 0xa8, + 0x33, 0x88, 0x07, 0xc7, 0x31, 0xb1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xec, 0x5f, + 0x60, 0x51, 0x7f, 0xa9, 0x19, 0xb5, 0x4a, 0x0d, 0x2d, 0xe5, 0x7a, 0x9f, 0x93, + 0xc9, 0x9c, 0xef, 0xa0, 0xe0, 0x3b, 0x4d, 0xae, 0x2a, 0xf5, 0xb0, 0xc8, 0xeb, + 0xbb, 0x3c, 0x83, 0x53, 0x99, 0x61, 0x17, 0x2b, 0x04, 0x7e, 0xba, 0x77, 0xd6, + 0x26, 0xe1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0c, 0x7d}; + +static void inv_sub_block (uint32_t state[4]) { + state[0] = sub_word (state[0], S_inv); + state[1] = sub_word (state[1], S_inv); + state[2] = sub_word (state[2], S_inv); + state[3] = sub_word (state[3], S_inv); +} + +static void inv_shift_rows (uint32_t state[4]) { + uint32_t u, v, x, y; + + u = word4 (byte (state[0], 0), + byte (state[3], 1), + byte (state[2], 2), + byte (state[1], 3)); + + v = word4 (byte (state[1], 0), + byte (state[0], 1), + byte (state[3], 2), + byte (state[2], 3)); + + x = word4 (byte (state[2], 0), + byte (state[1], 1), + byte (state[0], 2), + byte (state[3], 3)); + + y = word4 (byte (state[3], 0), + byte (state[2], 1), + byte (state[1], 2), + byte (state[0], 3)); + + state[0] = u; + state[1] = v; + state[2] = x; + state[3] = y; +} + +static uint32_t inv_mix_column (uint32_t x) { + uint32_t x2 = gf_poly_mul2 (x), + x4 = gf_poly_mul2 (x2), + x9 = x ^ gf_poly_mul2 (x4), + x11 = x2 ^ x9, + x13 = x4 ^ x9; + + return x ^ x2 ^ x13 ^ rotr32 (x11, 24) ^ rotr32 (x13, 16) ^ rotr32 (x9, 8); +} + +static void inv_mix_columns (uint32_t state[4]) { + state[0] = inv_mix_column (state[0]); + state[1] = inv_mix_column (state[1]); + state[2] = inv_mix_column (state[2]); + state[3] = inv_mix_column (state[3]); +} + +void cf_aes_decrypt (const cf_aes_context *ctx, + const uint8_t in[AES_BLOCKSZ], + uint8_t out[AES_BLOCKSZ]) { + assert (ctx->rounds == AES128_ROUNDS || + ctx->rounds == AES192_ROUNDS || + ctx->rounds == AES256_ROUNDS); + + uint32_t state[4] = { + read32_be (in + 0), + read32_be (in + 4), + read32_be (in + 8), + read32_be (in + 12)}; + + const uint32_t *round_keys = &ctx->ks[ctx->rounds << 2]; + add_round_key (state, round_keys); + round_keys -= 4; + + for (uint32_t round = ctx->rounds - 1; round != 0; round--) { + inv_shift_rows (state); + inv_sub_block (state); + add_round_key (state, round_keys); + inv_mix_columns (state); + round_keys -= 4; + } + + inv_shift_rows (state); + inv_sub_block (state); + add_round_key (state, round_keys); + + write32_be (state[0], out + 0); + write32_be (state[1], out + 4); + write32_be (state[2], out + 8); + write32_be (state[3], out + 12); +} +#else +void cf_aes_decrypt (const cf_aes_context *ctx, + const uint8_t in[AES_BLOCKSZ], + uint8_t out[AES_BLOCKSZ]) { + abort(); +} +#endif + +void cf_aes_finish (cf_aes_context *ctx) { + mem_clean (ctx, sizeof *ctx); +} + +const cf_prp cf_aes = { + .blocksz = AES_BLOCKSZ, + .encrypt = (cf_prp_block)cf_aes_encrypt, + .decrypt = (cf_prp_block)cf_aes_decrypt}; + +int aes_encrypt_ecb (const uint8_t *key, const uint8_t keyLen, const uint8_t *input, size_t ilen, + uint8_t *output) { + if (ilen % 16 != 0) + return -1; + + cf_aes_context ctx; + cf_aes_init (&ctx, key, keyLen); + + for (size_t i = 0; i < ilen; i += 16) { + cf_aes_encrypt (&ctx, input + i, output + i); + } + + cf_aes_finish (&ctx); + return 0; +} + +int aes_decrypt_ecb (const uint8_t *key, const uint8_t keyLen, const uint8_t *input, size_t ilen, + uint8_t *output) { + if (ilen % 16 != 0) + return -1; + + cf_aes_context ctx; + cf_aes_init (&ctx, key, keyLen); + + for (size_t i = 0; i < ilen; i += 16) { + cf_aes_decrypt (&ctx, input + i, output + i); + } + + + cf_aes_finish (&ctx); + return 0; +} diff --git a/User/lib/cifra/aes.h b/User/lib/cifra/aes.h new file mode 100644 index 0000000..c6e9c72 --- /dev/null +++ b/User/lib/cifra/aes.h @@ -0,0 +1,158 @@ +/* + * cifra - embedded cryptography library + * Written in 2014 by Joseph Birr-Pixton + * + * To the extent possible under law, the author(s) have dedicated all + * copyright and related and neighboring rights to this software to the + * public domain worldwide. This software is distributed without any + * warranty. + * + * You should have received a copy of the CC0 Public Domain Dedication + * along with this software. If not, see + * . + */ + +/** + * The AES block cipher + * ==================== + * + * This is a small, simple implementation of AES. Key expansion is done + * first, filling in a :c:type:`cf_aes_context`. Then encryption and + * decryption can be performed as desired. + * + * Usually you don't want to use AES directly; you should use it via + * a :doc:`block cipher mode `. + */ + +#ifndef AES_H +#define AES_H + +#include +#include + +#include "prp.h" + +/* .. c:macro:: AES_BLOCKSZ + * AES has a 128-bit block size. This quantity is in bytes. + */ +#define AES_BLOCKSZ 16 + +/* --- Size configuration --- */ + +/* .. c:macro:: AES128_ROUNDS + * .. c:macro:: AES192_ROUNDS + * .. c:macro:: AES256_ROUNDS + * + * Round counts for different key sizes. + */ +#define AES128_ROUNDS 10 +#define AES192_ROUNDS 12 +#define AES256_ROUNDS 14 + +/* .. c:macro:: CF_AES_MAXROUNDS + * + * You can reduce the maximum number of rounds this implementation + * supports. This reduces the storage needed by :c:type:`cf_aes_context`. + * + * The default is :c:macro:`AES256_ROUNDS` and is good for all key + * sizes. + */ +#ifndef CF_AES_MAXROUNDS +# define CF_AES_MAXROUNDS AES256_ROUNDS +#endif + +/* .. c:macro:: CF_AES_ENCRYPT_ONLY + * + * Define this to 1 if you don't need to decrypt anything. + * This saves space. :c:func:`cf_aes_decrypt` calls `abort(3)`. + */ +#ifndef CF_AES_ENCRYPT_ONLY +# define CF_AES_ENCRYPT_ONLY 0 +#endif + +/* .. c:type:: cf_aes_context + * This type represents an expanded AES key. Create one + * using :c:func:`cf_aes_init`, make use of one using + * :c:func:`cf_aes_encrypt` or :c:func:`cf_aes_decrypt`. + * + * The contents of this structure are equivalent to the + * original key material. You should clean the + * contents of this structure with :c:func:`cf_aes_finish` + * when you're done. + * + * .. c:member:: cf_aes_context.rounds + * + * Number of rounds to use, set by :c:func:`cf_aes_init`. + * + * This depends on the original key size, and will be + * :c:macro:`AES128_ROUNDS`, :c:macro:`AES192_ROUNDS` or + * :c:macro:`AES256_ROUNDS`. + * + * .. c:member:: cf_aes_context.ks + * + * Expanded key material. Filled in by :c:func:`cf_aes_init`. + */ +typedef struct +{ + uint32_t rounds; + uint32_t ks[AES_BLOCKSZ / 4 * (CF_AES_MAXROUNDS + 1)]; +} cf_aes_context; + +/* .. c:function:: $DECL + * This function does AES key expansion. It destroys + * existing contents of :c:data:`ctx`. + * + * :param ctx: expanded key context, filled in by this function. + * :param key: pointer to key material, of :c:data:`nkey` bytes. + * :param nkey: length of key material. Must be `16`, `24` or `32`. + */ +extern void cf_aes_init(cf_aes_context *ctx, + const uint8_t *key, + size_t nkey); + +/* .. c:function:: $DECL + * Encrypts the given block, from :c:data:`in` to :c:data:`out`. + * These may alias. + * + * Fails at runtime if :c:data:`ctx` is invalid. + * + * :param ctx: expanded key context + * :param in: input block (read) + * :param out: output block (written) + */ +extern void cf_aes_encrypt(const cf_aes_context *ctx, + const uint8_t in[AES_BLOCKSZ], + uint8_t out[AES_BLOCKSZ]); + +/* .. c:function:: $DECL + * Decrypts the given block, from :c:data:`in` to :c:data:`out`. + * These may alias. + * + * Fails at runtime if :c:data:`ctx` is invalid. + * + * :param ctx: expanded key context + * :param in: input block (read) + * :param out: output block (written) + */ +extern void cf_aes_decrypt(const cf_aes_context *ctx, + const uint8_t in[AES_BLOCKSZ], + uint8_t out[AES_BLOCKSZ]); + +/* .. c:function:: $DECL + * Erase scheduled key material. + * + * Call this when you're done to erase the round keys. */ +extern void cf_aes_finish(cf_aes_context *ctx); + +/* .. c:var:: const cf_prp cf_aes + * Abstract interface to AES. See :c:type:`cf_prp` for + * more information. */ +extern const cf_prp cf_aes; + +int aes_decrypt_ecb (const uint8_t *key, const uint8_t keyLen, const uint8_t *input, size_t ilen, + uint8_t *output); + +int aes_encrypt_ecb (const uint8_t *key, const uint8_t keyLen, const uint8_t *input, size_t ilen, + uint8_t *output); + +#endif diff --git a/User/lib/cifra/bitops.h b/User/lib/cifra/bitops.h new file mode 100644 index 0000000..d0e6942 --- /dev/null +++ b/User/lib/cifra/bitops.h @@ -0,0 +1,294 @@ +/* + * cifra - embedded cryptography library + * Written in 2014 by Joseph Birr-Pixton + * + * To the extent possible under law, the author(s) have dedicated all + * copyright and related and neighboring rights to this software to the + * public domain worldwide. This software is distributed without any + * warranty. + * + * You should have received a copy of the CC0 Public Domain Dedication + * along with this software. If not, see + * . + */ + +#ifndef BITOPS_H +#define BITOPS_H + +#include +#include + +/* Assorted bitwise and common operations used in ciphers. */ + +/** Circularly rotate right x by n bits. + * 0 > n > 32. */ +static inline uint32_t rotr32(uint32_t x, unsigned n) +{ + return (x >> n) | (x << (32 - n)); +} + +/** Circularly rotate left x by n bits. + * 0 > n > 32. */ +static inline uint32_t rotl32(uint32_t x, unsigned n) +{ + return (x << n) | (x >> (32 - n)); +} + +/** Circularly rotate right x by n bits. + * 0 > n > 64. */ +static inline uint64_t rotr64(uint64_t x, unsigned n) +{ + return (x >> n) | (x << (64 - n)); +} + +/** Circularly rotate left x by n bits. + * 0 > n > 64. */ +static inline uint64_t rotl64(uint64_t x, unsigned n) +{ + return (x << n) | (x >> (64 - n)); +} + +/** Read 4 bytes from buf, as a 32-bit big endian quantity. */ +static inline uint32_t read32_be(const uint8_t buf[4]) +{ + return (buf[0] << 24) | + (buf[1] << 16) | + (buf[2] << 8) | + (buf[3]); +} + +/** Read 4 bytes from buf, as a 32-bit little endian quantity. */ +static inline uint32_t read32_le(const uint8_t buf[4]) +{ + return (buf[3] << 24) | + (buf[2] << 16) | + (buf[1] << 8) | + (buf[0]); +} + +/** Read 8 bytes from buf, as a 64-bit big endian quantity. */ +static inline uint64_t read64_be(const uint8_t buf[8]) +{ + uint32_t hi = read32_be(buf), + lo = read32_be(buf + 4); + return ((uint64_t)hi) << 32 | + lo; +} + +/** Read 8 bytes from buf, as a 64-bit little endian quantity. */ +static inline uint64_t read64_le(const uint8_t buf[8]) +{ + uint32_t hi = read32_le(buf + 4), + lo = read32_le(buf); + return ((uint64_t)hi) << 32 | + lo; +} + +/** Encode v as a 32-bit big endian quantity into buf. */ +static inline void write32_be(uint32_t v, uint8_t buf[4]) +{ + *buf++ = (v >> 24) & 0xff; + *buf++ = (v >> 16) & 0xff; + *buf++ = (v >> 8) & 0xff; + *buf = v & 0xff; +} + +/** Encode v as a 32-bit little endian quantity into buf. */ +static inline void write32_le(uint32_t v, uint8_t buf[4]) +{ + *buf++ = v & 0xff; + *buf++ = (v >> 8) & 0xff; + *buf++ = (v >> 16) & 0xff; + *buf = (v >> 24) & 0xff; +} + +/** Encode v as a 64-bit big endian quantity into buf. */ +static inline void write64_be(uint64_t v, uint8_t buf[8]) +{ + *buf++ = (v >> 56) & 0xff; + *buf++ = (v >> 48) & 0xff; + *buf++ = (v >> 40) & 0xff; + *buf++ = (v >> 32) & 0xff; + *buf++ = (v >> 24) & 0xff; + *buf++ = (v >> 16) & 0xff; + *buf++ = (v >> 8) & 0xff; + *buf = v & 0xff; +} + +/** Encode v as a 64-bit little endian quantity into buf. */ +static inline void write64_le(uint64_t v, uint8_t buf[8]) +{ + *buf++ = v & 0xff; + *buf++ = (v >> 8) & 0xff; + *buf++ = (v >> 16) & 0xff; + *buf++ = (v >> 24) & 0xff; + *buf++ = (v >> 32) & 0xff; + *buf++ = (v >> 40) & 0xff; + *buf++ = (v >> 48) & 0xff; + *buf = (v >> 56) & 0xff; +} + +/** out = in ^ b8. + * out and in may alias. */ +static inline void xor_b8(uint8_t *out, const uint8_t *in, uint8_t b8, size_t len) +{ + for (size_t i = 0; i < len; i++) + out[i] = in[i] ^ b8; +} + +/** out = x ^ y. + * out, x and y may alias. */ +static inline void xor_bb(uint8_t *out, const uint8_t *x, const uint8_t *y, size_t len) +{ + for (size_t i = 0; i < len; i++) + out[i] = x[i] ^ y[i]; +} + +/* out ^= x + * out and x may alias. */ +static inline void xor_words(uint32_t *out, const uint32_t *x, size_t nwords) +{ + for (size_t i = 0; i < nwords; i++) + out[i] ^= x[i]; +} + +/** Produce 0xffffffff if x == y, zero otherwise, without branching. */ +static inline uint32_t mask_u32(uint32_t x, uint32_t y) +{ + uint32_t diff = x ^ y; + uint32_t diff_is_zero = ~diff & (diff - 1); + return - (diff_is_zero >> 31); +} + +/** Product 0xff if x == y, zero otherwise, without branching. */ +static inline uint8_t mask_u8(uint32_t x, uint32_t y) +{ + uint32_t diff = x ^ y; + uint8_t diff_is_zero = ~diff & (diff - 1); + return - (diff_is_zero >> 7); +} + +/** Select the ith entry from the given table of n values, in a side channel-silent + * way. */ +static inline uint32_t select_u32(uint32_t i, volatile const uint32_t *tab, uint32_t n) +{ + uint32_t r = 0; + + for (uint32_t ii = 0; ii < n; ii++) + { + uint32_t mask = mask_u32(i, ii); + r = (r & ~mask) | (tab[ii] & mask); + } + + return r; +} + +/** Select the ith entry from the given table of n values, in a side channel-silent + * way. */ +static inline uint8_t select_u8(uint32_t i, volatile const uint8_t *tab, uint32_t n) +{ + uint8_t r = 0; + + for (uint32_t ii = 0; ii < n; ii++) + { + uint8_t mask = mask_u8(i, ii); + r = (r & ~mask) | (tab[ii] & mask); + } + + return r; +} + +/** Select the ath, bth, cth and dth entries from the given table of n values, + * placing the results into a, b, c and d. */ +static inline void select_u8x4(uint8_t *a, uint8_t *b, uint8_t *c, uint8_t *d, + volatile const uint8_t *tab, uint32_t n) +{ + uint8_t ra = 0, + rb = 0, + rc = 0, + rd = 0; + uint8_t mask; + + for (uint32_t i = 0; i < n; i++) + { + uint8_t item = tab[i]; + + mask = mask_u8(*a, i); ra = (ra & ~mask) | (item & mask); + mask = mask_u8(*b, i); rb = (rb & ~mask) | (item & mask); + mask = mask_u8(*c, i); rc = (rc & ~mask) | (item & mask); + mask = mask_u8(*d, i); rd = (rd & ~mask) | (item & mask); + } + + *a = ra; + *b = rb; + *c = rc; + *d = rd; +} + +/** out ^= if0 or if1, depending on the value of bit. */ +static inline void select_xor128(uint32_t out[4], + const uint32_t if0[4], + const uint32_t if1[4], + uint8_t bit) +{ + uint32_t mask1 = mask_u32(bit, 1); + uint32_t mask0 = ~mask1; + + out[0] ^= (if0[0] & mask0) | (if1[0] & mask1); + out[1] ^= (if0[1] & mask0) | (if1[1] & mask1); + out[2] ^= (if0[2] & mask0) | (if1[2] & mask1); + out[3] ^= (if0[3] & mask0) | (if1[3] & mask1); +} + +/** Increments the integer stored at v (of non-zero length len) + * with the least significant byte first. */ +static inline void incr_le(uint8_t *v, size_t len) +{ + size_t i = 0; + while (1) + { + if (++v[i] != 0) + return; + i++; + if (i == len) + return; + } +} + +/** Increments the integer stored at v (of non-zero length len) + * with the most significant byte last. */ +static inline void incr_be(uint8_t *v, size_t len) +{ + len--; + while (1) + { + if (++v[len] != 0) + return; + if (len == 0) + return; + len--; + } +} + +/** Copies len bytes from in to out, with in shifted left by offset bits + * to the right. */ +static inline void copy_bytes_unaligned(uint8_t *out, const uint8_t *in, size_t len, uint8_t offset) +{ + uint8_t byte_off = offset / 8; + uint8_t bit_off = offset & 7; + uint8_t rmask = (1 << bit_off) - 1; + uint8_t lmask = ~rmask; + + for (size_t i = 0; i < len; i++) + { + out[i] = (in[i + byte_off] << bit_off) & lmask; + out[i] |= (in[i + byte_off + 1] >> (8 - bit_off)) & rmask; + } +} + +static inline uint32_t count_trailing_zeroes(uint32_t x) +{ + return (uint32_t) __builtin_ctzl(x); +} + +#endif diff --git a/User/lib/cifra/blockwise.c b/User/lib/cifra/blockwise.c new file mode 100644 index 0000000..182c8c5 --- /dev/null +++ b/User/lib/cifra/blockwise.c @@ -0,0 +1,195 @@ +/* + * cifra - embedded cryptography library + * Written in 2014 by Joseph Birr-Pixton + * + * To the extent possible under law, the author(s) have dedicated all + * copyright and related and neighboring rights to this software to the + * public domain worldwide. This software is distributed without any + * warranty. + * + * You should have received a copy of the CC0 Public Domain Dedication + * along with this software. If not, see + * . + */ + +#include "blockwise.h" +#include "bitops.h" +#include "handy.h" +#include "tassert.h" + +#include + +void cf_blockwise_accumulate(uint8_t *partial, size_t *npartial, size_t nblock, + const void *inp, size_t nbytes, + cf_blockwise_in_fn process, + void *ctx) +{ + cf_blockwise_accumulate_final(partial, npartial, nblock, + inp, nbytes, + process, process, ctx); +} + +void cf_blockwise_accumulate_final(uint8_t *partial, size_t *npartial, size_t nblock, + const void *inp, size_t nbytes, + cf_blockwise_in_fn process, + cf_blockwise_in_fn process_final, + void *ctx) +{ + const uint8_t *bufin = inp; + assert(partial && *npartial < nblock); + assert(inp || !nbytes); + assert(process && ctx); + + /* If we have partial data, copy in to buffer. */ + if (*npartial && nbytes) + { + size_t space = nblock - *npartial; + size_t taken = MIN(space, nbytes); + + memcpy(partial + *npartial, bufin, taken); + + bufin += taken; + nbytes -= taken; + *npartial += taken; + + /* If that gives us a full block, process it. */ + if (*npartial == nblock) + { + if (nbytes == 0) + process_final(ctx, partial); + else + process(ctx, partial); + *npartial = 0; + } + } + + /* now nbytes < nblock or *npartial == 0. */ + + /* If we have a full block of data, process it directly. */ + while (nbytes >= nblock) + { + /* Partial buffer must be empty, or we're ignoring extant data */ + assert(*npartial == 0); + + if (nbytes == nblock) + process_final(ctx, bufin); + else + process(ctx, bufin); + bufin += nblock; + nbytes -= nblock; + } + + /* Finally, if we have remaining data, buffer it. */ + while (nbytes) + { + size_t space = nblock - *npartial; + size_t taken = MIN(space, nbytes); + + memcpy(partial + *npartial, bufin, taken); + + bufin += taken; + nbytes -= taken; + *npartial += taken; + + /* If we started with *npartial, we must have copied it + * in first. */ + assert(*npartial < nblock); + } +} + +void cf_blockwise_xor(uint8_t *partial, size_t *npartial, size_t nblock, + const void *inp, void *outp, size_t nbytes, + cf_blockwise_out_fn process, void *ctx) +{ + const uint8_t *inb = inp; + uint8_t *outb = outp; + + assert(partial && *npartial < nblock); + assert(inp || !nbytes); + assert(process && ctx); + + while (nbytes) + { + /* If we're out of material, and need more, produce a block. */ + if (*npartial == 0) + { + process(ctx, partial); + *npartial = nblock; + } + + size_t offset = nblock - *npartial; + size_t taken = MIN(*npartial, nbytes); + xor_bb(outb, inb, partial + offset, taken); + *npartial -= taken; + nbytes -= taken; + outb += taken; + inb += taken; + } +} + +void cf_blockwise_acc_byte(uint8_t *partial, size_t *npartial, + size_t nblock, + uint8_t byte, size_t nbytes, + cf_blockwise_in_fn process, + void *ctx) +{ + /* only memset the whole of the block once */ + int filled = 0; + + while (nbytes) + { + size_t start = *npartial; + size_t count = MIN(nbytes, nblock - start); + + if (!filled) + memset(partial + start, byte, count); + + if (start == 0 && count == nblock) + filled = 1; + + if (start + count == nblock) + { + process(ctx, partial); + *npartial = 0; + } else { + *npartial += count; + } + + nbytes -= count; + } +} + +void cf_blockwise_acc_pad(uint8_t *partial, size_t *npartial, + size_t nblock, + uint8_t fbyte, uint8_t mbyte, uint8_t lbyte, + size_t nbytes, + cf_blockwise_in_fn process, + void *ctx) +{ + + switch (nbytes) + { + case 0: break; + case 1: fbyte ^= lbyte; + cf_blockwise_accumulate(partial, npartial, nblock, &fbyte, 1, process, ctx); + break; + case 2: + cf_blockwise_accumulate(partial, npartial, nblock, &fbyte, 1, process, ctx); + cf_blockwise_accumulate(partial, npartial, nblock, &lbyte, 1, process, ctx); + break; + default: + cf_blockwise_accumulate(partial, npartial, nblock, &fbyte, 1, process, ctx); + + /* If the middle and last bytes differ, then process the last byte separately. + * Otherwise, just extend the middle block size. */ + if (lbyte != mbyte) + { + cf_blockwise_acc_byte(partial, npartial, nblock, mbyte, nbytes - 2, process, ctx); + cf_blockwise_accumulate(partial, npartial, nblock, &lbyte, 1, process, ctx); + } else { + cf_blockwise_acc_byte(partial, npartial, nblock, mbyte, nbytes - 1, process, ctx); + } + + break; + } +} diff --git a/User/lib/cifra/blockwise.h b/User/lib/cifra/blockwise.h new file mode 100644 index 0000000..a20ff95 --- /dev/null +++ b/User/lib/cifra/blockwise.h @@ -0,0 +1,147 @@ +/* + * cifra - embedded cryptography library + * Written in 2014 by Joseph Birr-Pixton + * + * To the extent possible under law, the author(s) have dedicated all + * copyright and related and neighboring rights to this software to the + * public domain worldwide. This software is distributed without any + * warranty. + * + * You should have received a copy of the CC0 Public Domain Dedication + * along with this software. If not, see + * . + */ + +#ifndef BLOCKWISE_H +#define BLOCKWISE_H + +#include +#include + +/* Processing function for cf_blockwise_accumulate. */ +typedef void (*cf_blockwise_in_fn)(void *ctx, const uint8_t *data); + +/* Processing function for cf_blockwise_xor. */ +typedef void (*cf_blockwise_out_fn)(void *ctx, uint8_t *data); + +/* This function manages the common abstraction of accumulating input in + * a buffer, and processing it when a full block is available. + * + * partial is the buffer (maintained by the caller) + * on entry, npartial is the currently valid count of used bytes on + * the front of partial. + * on exit, npartial is updated to reflect the status of partial. + * nblock is the blocksize to accumulate -- partial must be at least + * this long! + * input is the new data to process, of length nbytes. + * process is the processing function, passed ctx and a pointer + * to the data to process (always exactly nblock bytes long!) + * which may not neccessarily be the same as partial. + */ +void cf_blockwise_accumulate(uint8_t *partial, size_t *npartial, + size_t nblock, + const void *input, size_t nbytes, + cf_blockwise_in_fn process, + void *ctx); + +/* This function manages the common abstraction of accumulating input in + * a buffer, and processing it when a full block is available. + * This version supports calling a different processing function for + * the last block. + * + * partial is the buffer (maintained by the caller) + * on entry, npartial is the currently valid count of used bytes on + * the front of partial. + * on exit, npartial is updated to reflect the status of partial. + * nblock is the blocksize to accumulate -- partial must be at least + * this long! + * input is the new data to process, of length nbytes. + * process is the processing function, passed ctx and a pointer + * to the data to process (always exactly nblock bytes long!) + * which may not neccessarily be the same as partial. + * process_final is called last (but may not be called at all if + * all input is buffered). + */ +void cf_blockwise_accumulate_final(uint8_t *partial, size_t *npartial, + size_t nblock, + const void *input, size_t nbytes, + cf_blockwise_in_fn process, + cf_blockwise_in_fn process_final, + void *ctx); + +/* This function manages XORing an input stream with a keystream + * to produce an output stream. The keystream is produced in blocks + * (ala a block cipher in counter mode). + * + * partial is the keystream buffer (maintained by the caller) + * on entry, *npartial is the currently valid count of bytes in partial: + * unused bytes are at the *end*. So *npartial = 4 means the last four + * bytes of partial are usable as keystream. + * on exit, npartial is updated to reflect the new state of partial. + * nblock is the blocksize to accumulate -- partial must be at least + * this long! + * input is the new data to process, of length nbytes. + * output is where to write input xored with the keystream -- also length + * nbytes. + * process is the processing function, passed ctx and partial which it + * should fill with fresh key stream. + */ +void cf_blockwise_xor(uint8_t *partial, size_t *npartial, + size_t nblock, + const void *input, void *output, size_t nbytes, + cf_blockwise_out_fn newblock, + void *ctx); + +/* This function processes a single byte a number of times. It's useful + * for padding, and more efficient than calling cf_blockwise_accumulate + * a bunch of times. + * + * partial is the buffer (maintained by the caller) + * on entry, npartial is the currently valid count of used bytes on + * the front of partial. + * on exit, npartial is updated to reflect the status of partial. + * nblock is the blocksize to accumulate -- partial must be at least + * this long! + * process is the processing function, passed ctx and a pointer + * to the data to process (always exactly nblock bytes long!) + * which may not neccessarily be the same as partial. + * byte is the byte to process, nbytes times. + */ +void cf_blockwise_acc_byte(uint8_t *partial, size_t *npartial, + size_t nblock, + uint8_t byte, size_t nbytes, + cf_blockwise_in_fn process, + void *ctx); + +/* This function attempts to process patterns of bytes common in + * block cipher padding. + * + * This takes three bytes: + * - a first byte, fbyte, + * - a middle byte, mbyte, + * - a last byte, lbyte. + * + * If nbytes is zero, nothing happens. + * If nbytes is one, the byte fbyte ^ lbyte is processed. + * If nbytes is two, the fbyte then lbyte are processed. + * If nbytes is three or more, fbyte, then one or more mbytes, then fbyte + * is processed. + * + * partial is the buffer (maintained by the caller) + * on entry, npartial is the currently valid count of used bytes on + * the front of partial. + * on exit, npartial is updated to reflect the status of partial. + * nblock is the blocksize to accumulate -- partial must be at least + * this long! + * process is the processing function, passed ctx and a pointer + * to the data to process (always exactly nblock bytes long!) + * which may not neccessarily be the same as partial. + */ +void cf_blockwise_acc_pad(uint8_t *partial, size_t *npartial, + size_t nblock, + uint8_t fbyte, uint8_t mbyte, uint8_t lbyte, + size_t nbytes, + cf_blockwise_in_fn process, + void *ctx); + +#endif diff --git a/User/lib/cifra/cf_config.h b/User/lib/cifra/cf_config.h new file mode 100644 index 0000000..ceb7e8d --- /dev/null +++ b/User/lib/cifra/cf_config.h @@ -0,0 +1,59 @@ +/* + * cifra - embedded cryptography library + * Written in 2014 by Joseph Birr-Pixton + * + * To the extent possible under law, the author(s) have dedicated all + * copyright and related and neighboring rights to this software to the + * public domain worldwide. This software is distributed without any + * warranty. + * + * You should have received a copy of the CC0 Public Domain Dedication + * along with this software. If not, see + * . + */ + +#ifndef CF_CONFIG_H +#define CF_CONFIG_H + +/** + * Library configuration + * ===================== + */ + +/* .. c:macro:: CF_SIDE_CHANNEL_PROTECTION + * Define this as 1 if you need all available side channel protections. + * **This option may alter the ABI**. + * + * This has a non-trivial performance penalty. Where a + * side-channel free option is cheap or free (like checking + * a MAC) this is always done in a side-channel free way. + * + * The default is **on** for all available protections. + */ +#ifndef CF_SIDE_CHANNEL_PROTECTION +# define CF_SIDE_CHANNEL_PROTECTION 1 +#endif + +/* .. c:macro:: CF_TIME_SIDE_CHANNEL_PROTECTION + * Define this as 1 if you need timing/branch prediction side channel + * protection. + * + * You probably want this. The default is on. */ +#ifndef CF_TIME_SIDE_CHANNEL_PROTECTION +# define CF_TIME_SIDE_CHANNEL_PROTECTION CF_SIDE_CHANNEL_PROTECTION +#endif + +/* .. c:macro:: CF_CACHE_SIDE_CHANNEL_PROTECTION + * Define this as 1 if you need cache side channel protection. + * + * If you have a microcontroller with no cache, you can turn this off + * without negative effects. + * + * The default is on. This will have some performance impact, + * especially on AES. + */ +#ifndef CF_CACHE_SIDE_CHANNEL_PROTECTION +# define CF_CACHE_SIDE_CHANNEL_PROTECTION CF_SIDE_CHANNEL_PROTECTION +#endif + +#endif diff --git a/User/lib/cifra/chash.c b/User/lib/cifra/chash.c new file mode 100644 index 0000000..4ee5d76 --- /dev/null +++ b/User/lib/cifra/chash.c @@ -0,0 +1,28 @@ +/* + * cifra - embedded cryptography library + * Written in 2014 by Joseph Birr-Pixton + * + * To the extent possible under law, the author(s) have dedicated all + * copyright and related and neighboring rights to this software to the + * public domain worldwide. This software is distributed without any + * warranty. + * + * You should have received a copy of the CC0 Public Domain Dedication + * along with this software. If not, see + * . + */ + +#include "chash.h" +#include "handy.h" +#include "tassert.h" + +void cf_hash(const cf_chash *h, const void *m, size_t nm, uint8_t *out) +{ + cf_chash_ctx ctx; + assert(h); + h->init(&ctx); + h->update(&ctx, m, nm); + h->digest(&ctx, out); + mem_clean(&ctx, sizeof ctx); +} + diff --git a/User/lib/cifra/chash.h b/User/lib/cifra/chash.h new file mode 100644 index 0000000..a06209f --- /dev/null +++ b/User/lib/cifra/chash.h @@ -0,0 +1,137 @@ +/* + * cifra - embedded cryptography library + * Written in 2014 by Joseph Birr-Pixton + * + * To the extent possible under law, the author(s) have dedicated all + * copyright and related and neighboring rights to this software to the + * public domain worldwide. This software is distributed without any + * warranty. + * + * You should have received a copy of the CC0 Public Domain Dedication + * along with this software. If not, see + * . + */ + +#ifndef CHASH_H +#define CHASH_H + +#include +#include + +/** + * General hash function description + * ================================= + * This allows us to make use of hash functions without depending + * on a specific one. This is useful in implementing, for example, + * :doc:`HMAC `. + */ + +/* .. c:type:: cf_chash_init + * Hashing initialisation function type. + * + * Functions of this type should initialise the context in preparation + * for hashing a message with `cf_chash_update` functions. + * + * :rtype: void + * :param ctx: hash function-specific context structure. + */ +typedef void (*cf_chash_init)(void *ctx); + +/* .. c:type:: cf_chash_update + * Hashing data processing function type. + * + * Functions of this type hash `count` bytes of data at `data`, + * updating the contents of `ctx`. + * + * :rtype: void + * :param ctx: hash function-specific context structure. + * :param data: input data to hash. + * :param count: number of bytes to hash. + */ +typedef void (*cf_chash_update)(void *ctx, const void *data, size_t count); + +/* .. c:type:: cf_chash_digest + * Hashing completion function type. + * + * Functions of this type complete a hashing operation, + * writing :c:member:`cf_chash.hashsz` bytes to `hash`. + * + * This function does not change `ctx` -- any padding which needs doing + * must be done seperately (in a copy of `ctx`, say). + * + * This means you can interlave `_update` and `_digest` calls to + * learn `H(A)` and `H(A || B)` without hashing `A` twice. + * + * :rtype: void + * :param ctx: hash function-specific context structure. + * :param hash: location to write hash result. + */ +typedef void (*cf_chash_digest)(const void *ctx, uint8_t *hash); + +/* .. c:type:: cf_chash + * This type describes an incremental hash function in an abstract way. + * + * .. c:member:: cf_chash.hashsz + * The hash function's output, in bytes. + * + * .. c:member:: cf_chash.blocksz + * The hash function's internal block size, in bytes. + * + * .. c:member:: cf_chash.init + * Context initialisation function. + * + * .. c:member:: cf_chash:update + * Data processing function. + * + * .. c:member:: cf_chash:digest + * Completion function. + * + */ +typedef struct +{ + size_t hashsz; + size_t blocksz; + + cf_chash_init init; + cf_chash_update update; + cf_chash_digest digest; +} cf_chash; + +/* .. c:macro:: CF_CHASH_MAXCTX + * The maximum size of a :c:type:`cf_chash_ctx`. This allows + * use to put a structure in automatic storage that can + * store working data for any supported hash function. */ +#define CF_CHASH_MAXCTX 390 + +/* .. c:macro:: CF_CHASH_MAXBLK + * Maximum hash function block size (in bytes). */ +#define CF_CHASH_MAXBLK 128 + +/* .. c:macro:: CF_MAXHASH + * Maximum hash function output (in bytes). */ +#define CF_MAXHASH 64 + +/* .. c:type:: cf_chash_ctx + * A type usable with any `cf_chash` as a context. */ +typedef union +{ + uint8_t ctx[CF_CHASH_MAXCTX]; + uint16_t uint16_t; + uint32_t u32; + uint64_t u64; +} cf_chash_ctx; + +/* .. c:function:: $DECL + * One shot hashing: `out = h(m)`. + * + * Using the hash function `h`, `nm` bytes at `m` are hashed and `h->hashsz` bytes + * of result is written to the buffer `out`. + * + * :param h: hash function description. + * :param m: message buffer. + * :param nm: message length. + * :param out: hash result buffer (written). + */ +void cf_hash(const cf_chash *h, const void *m, size_t nm, uint8_t *out); + +#endif diff --git a/User/lib/cifra/handy.h b/User/lib/cifra/handy.h new file mode 100644 index 0000000..a9b2d9d --- /dev/null +++ b/User/lib/cifra/handy.h @@ -0,0 +1,86 @@ +#ifndef HANDY_H +#define HANDY_H + +#include +#include +#include + +/* + * Handy CPP defines and C inline functions. + */ + +/* Evaluates to the number of items in array-type variable arr. */ +#define ARRAYCOUNT(arr) (sizeof arr / sizeof arr[0]) + +/* Normal MIN/MAX macros. Evaluate argument expressions only once. */ +#ifndef MIN + #define MIN(x, y) \ + ({ typeof (x) __x = (x); \ + typeof (y) __y = (y); \ + __x < __y ? __x : __y; }) +#endif +#ifndef MAX + #define MAX(x, y) \ + ({ typeof (x) __x = (x); \ + typeof (y) __y = (y); \ + __x > __y ? __x : __y; }) +#endif + +/* Swap two values. Uses GCC type inference magic. */ +#ifndef SWAP + #define SWAP(x, y) \ + do { \ + typeof (x) __tmp = (x); \ + (x) = (y); \ + (y) = __tmp; \ + } while (0) +#endif + +/** Stringify its argument. */ +#define STRINGIFY(x) STRINGIFY_(x) +#define STRINGIFY_(x) #x + +/* Error handling macros. + * + * These expect a zero = success, non-zero = error convention. + */ + +/** Error: return. + * + * If the expression fails, return the error from this function. */ +#define ER(expr) do { typeof (expr) err_ = (expr); if (err_) return err_; } while (0) + +/** Error: goto. + * + * If the expression fails, goto x_err. Assumes defn of label + * x_err and 'error_type err'. */ +#define EG(expr) do { err = (expr); if (err) goto x_err; } while (0) + +/** Like memset(ptr, 0, len), but not allowed to be removed by + * compilers. */ +static inline void mem_clean(volatile void *v, size_t len) +{ + if (len) + { + memset((void *) v, 0, len); + (void) *((volatile uint8_t *) v); + } +} + +/** Returns 1 if len bytes at va equal len bytes at vb, 0 if they do not. + * Does not leak length of common prefix through timing. */ +static inline unsigned mem_eq(const void *va, const void *vb, size_t len) +{ + const volatile uint8_t *a = va; + const volatile uint8_t *b = vb; + uint8_t diff = 0; + + while (len--) + { + diff |= *a++ ^ *b++; + } + + return !diff; +} + +#endif diff --git a/User/lib/cifra/hmac.c b/User/lib/cifra/hmac.c new file mode 100644 index 0000000..4038acd --- /dev/null +++ b/User/lib/cifra/hmac.c @@ -0,0 +1,117 @@ +/* + * cifra - embedded cryptography library + * Written in 2014 by Joseph Birr-Pixton + * + * To the extent possible under law, the author(s) have dedicated all + * copyright and related and neighboring rights to this software to the + * public domain worldwide. This software is distributed without any + * warranty. + * + * You should have received a copy of the CC0 Public Domain Dedication + * along with this software. If not, see + * . + */ + +#include "hmac.h" +#include "chash.h" +#include "bitops.h" +#include "handy.h" +#include "tassert.h" +#include "sha2.h" + +#include + +void cf_hmac_init(cf_hmac_ctx *ctx, + const cf_chash *hash, + const uint8_t *key, size_t nkey) +{ + assert(ctx); + assert(hash); + + mem_clean(ctx, sizeof *ctx); + ctx->hash = hash; + + /* Prepare key: */ + uint8_t k[CF_CHASH_MAXBLK]; + + /* Shorten long keys. */ + if (nkey > hash->blocksz) + { + /* Standard doesn't cover case where blocksz < hashsz. + * FIPS186-1 seems to want to append a negative number of zero bytes. + * In any case, we only have a k buffer of CF_CHASH_MAXBLK! */ + assert(hash->hashsz <= hash->blocksz); + + cf_hash(hash, key, nkey, k); + key = k; + nkey = hash->hashsz; + } + + /* Right zero-pad short keys. */ + if (k != key) + memcpy(k, key, nkey); + if (hash->blocksz > nkey) + memset(k + nkey, 0, hash->blocksz - nkey); + + /* Start inner hash computation */ + uint8_t blk[CF_CHASH_MAXBLK]; + + xor_b8(blk, k, 0x36, hash->blocksz); + hash->init(&ctx->inner); + hash->update(&ctx->inner, blk, hash->blocksz); + + /* And outer. */ + xor_b8(blk, k, 0x5c, hash->blocksz); + hash->init(&ctx->outer); + hash->update(&ctx->outer, blk, hash->blocksz); + + mem_clean(blk, sizeof blk); + mem_clean(k, sizeof k); +} + +void cf_hmac_update(cf_hmac_ctx *ctx, const void *data, size_t ndata) +{ + assert(ctx && ctx->hash); + + ctx->hash->update(&ctx->inner, data, ndata); +} + +void cf_hmac_finish(cf_hmac_ctx *ctx, uint8_t *out) +{ + assert(ctx && ctx->hash); + assert(out); + + uint8_t innerh[CF_MAXHASH]; + ctx->hash->digest(&ctx->inner, innerh); + + ctx->hash->update(&ctx->outer, innerh, ctx->hash->hashsz); + ctx->hash->digest(&ctx->outer, out); + + mem_clean(ctx, sizeof *ctx); +} + +void cf_hmac(const uint8_t *key, size_t nkey, + const uint8_t *msg, size_t nmsg, + uint8_t *out, + const cf_chash *hash) +{ + cf_hmac_ctx ctx; + + assert(out); + assert(hash); + + cf_hmac_init(&ctx, hash, key, nkey); + cf_hmac_update(&ctx, msg, nmsg); + cf_hmac_finish(&ctx, out); +} + +// HMAC-SHA256 +int hmac_sha256 (const uint8_t *key, size_t keylen, + const uint8_t *input, size_t ilen, + uint8_t *output) { + cf_hmac_ctx ctx; + cf_hmac_init (&ctx, &cf_sha256, key, keylen); + cf_hmac_update (&ctx, input, ilen); + cf_hmac_finish (&ctx, output); + return 0; +} diff --git a/User/lib/cifra/hmac.h b/User/lib/cifra/hmac.h new file mode 100644 index 0000000..863c9d1 --- /dev/null +++ b/User/lib/cifra/hmac.h @@ -0,0 +1,82 @@ +/* + * cifra - embedded cryptography library + * Written in 2014 by Joseph Birr-Pixton + * + * To the extent possible under law, the author(s) have dedicated all + * copyright and related and neighboring rights to this software to the + * public domain worldwide. This software is distributed without any + * warranty. + * + * You should have received a copy of the CC0 Public Domain Dedication + * along with this software. If not, see + * . + */ + +#ifndef HMAC_H +#define HMAC_H + +#include +#include + +#include "chash.h" + +/** + * HMAC + * ==== + * This is a one-shot and incremental interface to computing + * HMAC with any hash function. + * + * (Note: HMAC with SHA3 is possible, but is probably not a + * sensible thing to want.) + */ + +/* .. c:type:: cf_hmac_ctx + * HMAC incremental interface context. + * + * .. c:member:: cf_hmac_ctx.hash + * Hash function description. + * + * .. c:member:: cf_hmac_ctx.inner + * Inner hash computation. + * + * .. c:member:: cf_hmac_ctx.outer + * Outer hash computation. + */ +typedef struct +{ + const cf_chash *hash; + cf_chash_ctx inner; + cf_chash_ctx outer; +} cf_hmac_ctx; + +/* .. c:function:: $DECL + * Set up ctx for computing a HMAC using the given hash and key. */ +void cf_hmac_init(cf_hmac_ctx *ctx, + const cf_chash *hash, + const uint8_t *key, size_t nkey); + +/* .. c:function:: $DECL + * Input data. */ +void cf_hmac_update(cf_hmac_ctx *ctx, + const void *data, size_t ndata); + +/* .. c:function:: $DECL + * Finish and compute HMAC. + * `ctx->hash->hashsz` bytes are written to `out`. */ +void cf_hmac_finish(cf_hmac_ctx *ctx, uint8_t *out); + +/* .. c:function:: $DECL + * One shot interface: compute `HMAC_hash(key, msg)`, writing the + * answer (which is `hash->hashsz` long) to `out`. + * + * This function does not fail. */ +void cf_hmac(const uint8_t *key, size_t nkey, + const uint8_t *msg, size_t nmsg, + uint8_t *out, + const cf_chash *hash); + +int hmac_sha256 (const uint8_t *key, size_t keylen, + const uint8_t *input, size_t ilen, + uint8_t *output); + +#endif diff --git a/User/lib/cifra/prp.h b/User/lib/cifra/prp.h new file mode 100644 index 0000000..1aa7258 --- /dev/null +++ b/User/lib/cifra/prp.h @@ -0,0 +1,64 @@ +/* + * cifra - embedded cryptography library + * Written in 2014 by Joseph Birr-Pixton + * + * To the extent possible under law, the author(s) have dedicated all + * copyright and related and neighboring rights to this software to the + * public domain worldwide. This software is distributed without any + * warranty. + * + * You should have received a copy of the CC0 Public Domain Dedication + * along with this software. If not, see + * . + */ + +#ifndef PRP_H +#define PRP_H + +#include +#include + +/** + * General block cipher description + * ================================ + * This allows us to implement block cipher modes which can work + * with different block ciphers. + */ + +/* .. c:type:: cf_prp_block + * Block processing function type. + * + * The `in` and `out` blocks may alias. + * + * :rtype: void + * :param ctx: block cipher-specific context object. + * :param in: input block. + * :param out: output block. + */ +typedef void (*cf_prp_block)(void *ctx, const uint8_t *in, uint8_t *out); + +/* .. c:type:: cf_prp + * Describes an PRP in a general way. + * + * .. c:member:: cf_prp.blocksz + * Block size in bytes. Must be no more than :c:macro:`CF_MAXBLOCK`. + * + * .. c:member:: cf_prp.encrypt + * Block encryption function. + * + * .. c:member:: cf_prp.decrypt + * Block decryption function. + */ +typedef struct +{ + size_t blocksz; + cf_prp_block encrypt; + cf_prp_block decrypt; +} cf_prp; + +/* .. c:macro:: CF_MAXBLOCK + * The maximum block cipher blocksize we support, in bytes. + */ +#define CF_MAXBLOCK 16 + +#endif diff --git a/User/lib/cifra/sha2.h b/User/lib/cifra/sha2.h new file mode 100644 index 0000000..117a6a1 --- /dev/null +++ b/User/lib/cifra/sha2.h @@ -0,0 +1,89 @@ +/* + * cifra - embedded cryptography library + * Written in 2014 by Joseph Birr-Pixton + * + * To the extent possible under law, the author(s) have dedicated all + * copyright and related and neighboring rights to this software to the + * public domain worldwide. This software is distributed without any + * warranty. + * + * You should have received a copy of the CC0 Public Domain Dedication + * along with this software. If not, see + * . + */ + +#ifndef SHA2_H +#define SHA2_H + +#include +#include + +#include "chash.h" + +/** + * SHA224/SHA256 + * ============= + */ + +/* .. c:macro:: CF_SHA256_HASHSZ + * The output size of SHA256: 32 bytes. */ +#define CF_SHA256_HASHSZ 32 + +/* .. c:macro:: CF_SHA256_BLOCKSZ + * The block size of SHA256: 64 bytes. */ +#define CF_SHA256_BLOCKSZ 64 + +/* .. c:type:: cf_sha256_context + * Incremental SHA256 hashing context. + * + * .. c:member:: cf_sha256_context.H + * Intermediate values. + * + * .. c:member:: cf_sha256_context.partial + * Unprocessed input. + * + * .. c:member:: cf_sha256_context.npartial + * Number of bytes of unprocessed input. + * + * .. c:member:: cf_sha256_context.blocks + * Number of full blocks processed. + */ +typedef struct +{ + uint32_t H[8]; /* State. */ + uint8_t partial[CF_SHA256_BLOCKSZ]; /* Partial block of input. */ + uint32_t blocks; /* Number of full blocks processed into H. */ + size_t npartial; /* Number of bytes in prefix of partial. */ +} cf_sha256_context; + +/* .. c:function:: $DECL + * Sets up `ctx` ready to hash a new message. + */ +extern void cf_sha256_init(cf_sha256_context *ctx); + +/* .. c:function:: $DECL + * Hashes `nbytes` at `data`. Copies the data if there isn't enough to make + * a full block. + */ +extern void cf_sha256_update(cf_sha256_context *ctx, const void *data, size_t nbytes); + +/* .. c:function:: $DECL + * Finishes the hash operation, writing `CF_SHA256_HASHSZ` bytes to `hash`. + * + * This leaves `ctx` unchanged. + */ +extern void cf_sha256_digest(const cf_sha256_context *ctx, uint8_t hash[CF_SHA256_HASHSZ]); + +/* .. c:function:: $DECL + * Finishes the hash operation, writing `CF_SHA256_HASHSZ` bytes to `hash`. + * + * This destroys `ctx`, but uses less stack than :c:func:`cf_sha256_digest`. + */ +extern void cf_sha256_digest_final(cf_sha256_context *ctx, uint8_t hash[CF_SHA256_HASHSZ]); + +/* .. c:var:: cf_sha256 + * Abstract interface to SHA256. See :c:type:`cf_chash` for more information. + */ +extern const cf_chash cf_sha256; + +#endif diff --git a/User/lib/cifra/sha256.c b/User/lib/cifra/sha256.c new file mode 100644 index 0000000..7d77e39 --- /dev/null +++ b/User/lib/cifra/sha256.c @@ -0,0 +1,177 @@ +/* + * cifra - embedded cryptography library + * Written in 2014 by Joseph Birr-Pixton + * + * To the extent possible under law, the author(s) have dedicated all + * copyright and related and neighboring rights to this software to the + * public domain worldwide. This software is distributed without any + * warranty. + * + * You should have received a copy of the CC0 Public Domain Dedication + * along with this software. If not, see + * . + */ + +#include + +#include "sha2.h" +#include "blockwise.h" +#include "bitops.h" +#include "handy.h" +#include "tassert.h" + +static const uint32_t K[64] = { + 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5, + 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5, + 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3, + 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174, + 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc, + 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da, + 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7, + 0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967, + 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13, + 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85, + 0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3, + 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070, + 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5, + 0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3, + 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208, + 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2 +}; + +# define CH(x, y, z) (((x) & (y)) ^ (~(x) & (z))) +# define MAJ(x, y, z) (((x) & (y)) ^ ((x) & (z)) ^ ((y) & (z))) +# define BSIG0(x) (rotr32((x), 2) ^ rotr32((x), 13) ^ rotr32((x), 22)) +# define BSIG1(x) (rotr32((x), 6) ^ rotr32((x), 11) ^ rotr32((x), 25)) +# define SSIG0(x) (rotr32((x), 7) ^ rotr32((x), 18) ^ ((x) >> 3)) +# define SSIG1(x) (rotr32((x), 17) ^ rotr32((x), 19) ^ ((x) >> 10)) + +void cf_sha256_init(cf_sha256_context *ctx) +{ + memset(ctx, 0, sizeof *ctx); + ctx->H[0] = 0x6a09e667; + ctx->H[1] = 0xbb67ae85; + ctx->H[2] = 0x3c6ef372; + ctx->H[3] = 0xa54ff53a; + ctx->H[4] = 0x510e527f; + ctx->H[5] = 0x9b05688c; + ctx->H[6] = 0x1f83d9ab; + ctx->H[7] = 0x5be0cd19; +} + +static void sha256_update_block(void *vctx, const uint8_t *inp) +{ + cf_sha256_context *ctx = vctx; + + /* This is a 16-word window into the whole W array. */ + uint32_t W[16]; + + uint32_t a = ctx->H[0], + b = ctx->H[1], + c = ctx->H[2], + d = ctx->H[3], + e = ctx->H[4], + f = ctx->H[5], + g = ctx->H[6], + h = ctx->H[7], + Wt; + + for (size_t t = 0; t < 64; t++) + { + /* For W[0..16] we process the input into W. + * For W[16..64] we compute the next W value: + * + * W[t] = SSIG1(W[t - 2]) + W[t - 7] + SSIG0(W[t - 15]) + W[t - 16]; + * + * But all W indices are reduced mod 16 into our window. + */ + if (t < 16) + { + W[t] = Wt = read32_be(inp); + inp += 4; + } else { + Wt = SSIG1(W[(t - 2) % 16]) + + W[(t - 7) % 16] + + SSIG0(W[(t - 15) % 16]) + + W[(t - 16) % 16]; + W[t % 16] = Wt; + } + + uint32_t T1 = h + BSIG1(e) + CH(e, f, g) + K[t] + Wt; + uint32_t T2 = BSIG0(a) + MAJ(a, b, c); + h = g; + g = f; + f = e; + e = d + T1; + d = c; + c = b; + b = a; + a = T1 + T2; + } + + ctx->H[0] += a; + ctx->H[1] += b; + ctx->H[2] += c; + ctx->H[3] += d; + ctx->H[4] += e; + ctx->H[5] += f; + ctx->H[6] += g; + ctx->H[7] += h; + + ctx->blocks++; +} + +void cf_sha256_update(cf_sha256_context *ctx, const void *data, size_t nbytes) +{ + cf_blockwise_accumulate(ctx->partial, &ctx->npartial, sizeof ctx->partial, + data, nbytes, + sha256_update_block, ctx); +} + +void cf_sha256_digest(const cf_sha256_context *ctx, uint8_t hash[CF_SHA256_HASHSZ]) +{ + cf_sha256_context ours = *ctx; + cf_sha256_digest_final(&ours, hash); +} + +void cf_sha256_digest_final(cf_sha256_context *ctx, uint8_t hash[CF_SHA256_HASHSZ]) +{ + uint64_t digested_bytes = ctx->blocks; + digested_bytes = digested_bytes * CF_SHA256_BLOCKSZ + ctx->npartial; + uint64_t digested_bits = digested_bytes * 8; + + size_t padbytes = CF_SHA256_BLOCKSZ - ((digested_bytes + 8) % CF_SHA256_BLOCKSZ); + + /* Hash 0x80 00 ... block first. */ + cf_blockwise_acc_pad(ctx->partial, &ctx->npartial, sizeof ctx->partial, + 0x80, 0x00, 0x00, padbytes, + sha256_update_block, ctx); + + /* Now hash length. */ + uint8_t buf[8]; + write64_be(digested_bits, buf); + cf_sha256_update(ctx, buf, 8); + + /* We ought to have got our padding calculation right! */ + assert(ctx->npartial == 0); + + write32_be(ctx->H[0], hash + 0); + write32_be(ctx->H[1], hash + 4); + write32_be(ctx->H[2], hash + 8); + write32_be(ctx->H[3], hash + 12); + write32_be(ctx->H[4], hash + 16); + write32_be(ctx->H[5], hash + 20); + write32_be(ctx->H[6], hash + 24); + write32_be(ctx->H[7], hash + 28); + + memset(ctx, 0, sizeof *ctx); +} + +const cf_chash cf_sha256 = { + .hashsz = CF_SHA256_HASHSZ, + .blocksz = CF_SHA256_BLOCKSZ, + .init = (cf_chash_init) cf_sha256_init, + .update = (cf_chash_update) cf_sha256_update, + .digest = (cf_chash_digest) cf_sha256_digest +}; + diff --git a/User/lib/cifra/tassert.h b/User/lib/cifra/tassert.h new file mode 100644 index 0000000..58ebb4c --- /dev/null +++ b/User/lib/cifra/tassert.h @@ -0,0 +1,32 @@ +/* + * cifra - embedded cryptography library + * Written in 2014 by Joseph Birr-Pixton + * + * To the extent possible under law, the author(s) have dedicated all + * copyright and related and neighboring rights to this software to the + * public domain worldwide. This software is distributed without any + * warranty. + * + * You should have received a copy of the CC0 Public Domain Dedication + * along with this software. If not, see + * . + */ + +#ifndef TASSERT_H +#define TASSERT_H + +/* Tiny assert + * ----------- + * + * This is an assert(3) definition which doesn't include any + * strings, but just branches to abort(3) on failure. + */ + +#ifndef FULL_FAT_ASSERT +# include +# define assert(expr) do { if (!(expr)) abort(); } while (0) +#else +# include +#endif + +#endif diff --git a/User/lib/config.c b/User/lib/config.c new file mode 100644 index 0000000..30a0838 --- /dev/null +++ b/User/lib/config.c @@ -0,0 +1,274 @@ +#include "config.h" +#include "ch32v30x_flash.h" +#include "ch32v30x_rng.h" +#include "lib/cifra/sha2.h" +#include "lib/monocypher/monocypher-ed25519.h" +#include "sx1262.h" +#include "util/hexdump.h" +#include "util/log.h" + +PersistentData_t persistent; + +LoRaSettings currentLoRaSettings; + +#define TAG "Config" + +NodeEntry *getNextNode() { + uint32_t oldest_timestamp = UINT32_MAX; + NodeEntry *selectedNode = &(persistent.contacts[0]); + for (int i = 0; i < CONTACT_COUNT; i++) { + NodeEntry *curNode = &(persistent.contacts[i]); + if (curNode->flags & NODE_ENTRY_FAV_FLAG) { + continue; + } + if (curNode->last_seen_lt == 0) { + selectedNode = curNode; + break; + } + if (curNode->last_seen_lt < oldest_timestamp) { + oldest_timestamp = curNode->last_seen_lt; + selectedNode = curNode; + } + } + return selectedNode; +} + +NodeEntry *getNode (uint8_t hash) { + NodeEntry *selectedNode = NULL; + for (int i = 0; i < CONTACT_COUNT; i++) { + NodeEntry *curNode = &(persistent.contacts[i]); + if (curNode->pubKey[0] == hash) { + selectedNode = curNode; + break; + } + } + return selectedNode; +} + +NodeEntry *getNodePrefix (const uint8_t *hash) { + NodeEntry *selectedNode = NULL; + for (int i = 0; i < CONTACT_COUNT; i++) { + NodeEntry *curNode = &(persistent.contacts[i]); + if (memcmp (curNode->pubKey, hash, 4)) { + selectedNode = curNode; + break; + } + } + return selectedNode; +} + +Channel *getChannel (uint8_t hash, uint8_t ignoreCount) { + Channel *selectedChannel = NULL; + Channel *finalChannel = NULL; + uint8_t matchCount = 0; + for (int i = 0; i < ChannelCount; i++) { + Channel *curChannel = &(persistent.channels[i]); + if (curChannel->hash == hash) { + selectedChannel = curChannel; + if (++matchCount > ignoreCount) { + finalChannel = selectedChannel; + break; + } + } + } + return finalChannel; +} + +void addChannel (char *name, const uint8_t *key) { + + uint32_t oldest_timestamp = UINT32_MAX; + Channel *selectedChannel = &(persistent.channels[0]); + for (int i = 0; i < ChannelCount; i++) { + Channel *curChan = &(persistent.channels[i]); + + if (curChan->timestamp == 0) { + selectedChannel = curChan; + MESH_LOGD (TAG, "Deciding on channel index %d because of timestamp 0, name is %s", i, name); + break; + } + if (strlen (curChan->name) == 0) { + selectedChannel = curChan; + MESH_LOGD (TAG, "Deciding on channel index %d because of name len 0, name is %s", i, name); + break; + } + + if (curChan->timestamp < oldest_timestamp) { + oldest_timestamp = curChan->timestamp; + selectedChannel = curChan; + } + } + + + memset (selectedChannel->name, 0, sizeof (selectedChannel->name)); + strncpy (selectedChannel->name, name, sizeof (selectedChannel->name)); + memcpy (selectedChannel->key, key, sizeof (selectedChannel->key)); + // Buffer for the digest + uint8_t hash[CF_SHA256_HASHSZ]; + + // Context + cf_sha256_context ctx; + + // 1. Initialize + cf_sha256_init (&ctx); + + // 2. Feed in your data + cf_sha256_update (&ctx, selectedChannel->key, sizeof (selectedChannel->key)); + + // 3. Compute digest + cf_sha256_digest (&ctx, hash); + selectedChannel->hash = hash[0]; + selectedChannel->timestamp = RTC_GetCounter(); +} + +void printNodeDB() { + puts ("Node database:"); + for (int i = 0; i < CONTACT_COUNT; i++) { + const NodeEntry *node = &(persistent.contacts[i]); + if (node->last_seen_lt == 0) + continue; // skip inactive nodes + + iprintf ("Node %d:\n", i); + iprintf (" Name: %s\n", node->name); + hexdump ("Pubkey", node->pubKey, sizeof (node->pubKey)); + hexdump ("Secret", node->secret, sizeof (node->secret)); + iprintf ("\n"); + + iprintf (" GPS: lat=%d, lon=%d\n", node->gps_latitude, node->gps_longitude); + iprintf (" Path: ... (not expanded, add if needed)\n"); + iprintf (" Flags: 0x%02X\n", node->flags); + iprintf (" Type: 0x%02X\n", node->type); + iprintf (" Authenticated: %s\n", node->authenticated ? "Yes" : "No"); + iprintf (" Last Seen (remote ts): %d\n", node->last_seen_rt); + iprintf (" Last Seen (local ts): %d\n", node->last_seen_lt); + iprintf (" Sync timestamp: %d\n", node->sync_timestamp); + iprintf ("--------------------------------------\n"); + } +} + +void loadConfig() { + memcpy (&persistent, FLASH_USER_PAGE_ADDR, sizeof (persistent)); + memcpy(¤tLoRaSettings, &(persistent.loraSettings), sizeof(currentLoRaSettings)); + uint32_t crcSum = *((uint32_t *)(((uint8_t *)&persistent) + (sizeof (persistent) - 2))); + memset ((((uint8_t *)&persistent) + (sizeof (persistent) - sizeof (crcSum))), 0, 4); + CRC_ResetDR(); + uint32_t currentSum = CRC_CalcBlockCRC ((uint32_t *)&persistent, sizeof (persistent) - 2); + + if (currentSum != crcSum) { + memset (&persistent, 0, sizeof (persistent)); + } +} + +void saveConfig() { + CRC_ResetDR(); + uint32_t currentSum = CRC_CalcBlockCRC ((uint32_t *)&persistent, sizeof (persistent) - 2); + memcpy ((((uint8_t *)&persistent) + (sizeof (persistent) - sizeof (currentSum))), (uint8_t *)currentSum, 4); + FLASH_Unlock(); + FLASH_ErasePage_Fast (1919); + FLASH_ProgramPage_Fast (1919, (uint32_t *)&persistent); + FLASH_Lock(); +} + +void genSeed (uint8_t *seedOut) { + RCC_AHBPeriphClockCmd (RCC_AHBPeriph_RNG, ENABLE); + RNG_Cmd (ENABLE); + uint32_t random; + for (uint8_t i = 0; i < 8; i++) { + while (RNG_GetFlagStatus (RNG_FLAG_DRDY) == RESET) { + Delay_Ms(10); + } + random = RNG_GetRandomNumber(); + + memcpy (&(seedOut[i * 4]), &random, sizeof (random)); + } + RCC_AHBPeriphClockCmd (RCC_AHBPeriph_RNG, DISABLE); + RNG_Cmd (DISABLE); +} + +const uint8_t publicChannelPSK[16] = {0x8b, 0x33, 0x87, 0xe9, 0xc5, 0xcd, 0xea, 0x6a, 0xc9, 0xe5, 0xed, 0xba, 0xa1, 0x15, 0xcd, 0x72}; +const uint8_t BRNTestChannelPSK[16] = {0x44, 0x81, 0xda, 0x0e, 0x4e, 0x03, 0xc4, 0x9e, 0x84, 0x77, 0x25, 0xd8, 0x3a, 0x93, 0xbf, 0x80}; + +const char *getStringRole (uint8_t role) { + switch (role) { + case NODE_TYPE_CHAT_NODE: + return "Chat node"; + + case NODE_TYPE_REPEATER: + return "Repeater"; + + case NODE_TYPE_ROOM_SERVER: + return "Room server"; + + case NODE_TYPE_SENSOR: + return "Sensor"; + + default: + return "Unknown"; + } +} + +void populateDefaults() { + + uint8_t seed[32]; + //memcpy(seed, "vFt0FRugSOeqnkshImMCVfgHM5vBxz4", 32); //chat node identity + //memcpy (seed, "vFt0FRugSOeqnkshImMCVfgHM5vBxz3", 32); // repeater identity + memcpy (seed, "vFt0FRugSOeqnkshImMCVfgHM5vBxy1", 32); // repeater identity + // genSeed(seed); //random identity + + crypto_ed25519_key_pair(persistent.privkey, persistent.pubkey, seed); + + + persistent.nodeType = NODE_TYPE_CHAT_NODE; + //persistent.nodeType = NODE_TYPE_REPEATER; + memset (persistent.password, 0, sizeof (persistent.password)); + strcpy (persistent.password, "hesielko"); + //strcpy (persistent.nodeName, "BRN WCHNode RISCV"); + strcpy (persistent.nodeName, "BRN WCH Mini"); + + persistent.adcMultiplier = 0; + + persistent.loraSettings.txPowerInDbm = 20; + persistent.loraSettings.frequencyInHz = 869554000; + persistent.loraSettings.spreadingFactor = 8; + persistent.loraSettings.bandwidth = SX126X_LORA_BW_62_5; + persistent.loraSettings.codingRate = SX126X_LORA_CR_4_8; + persistent.loraSettings.preambleLength = 16; + persistent.loraSettings.tcxoVoltage = 2200; // ebyte + // persistent.tcxoVoltage = 1800; // heltec + + memcpy(¤tLoRaSettings, &(persistent.loraSettings), sizeof(currentLoRaSettings)); + + addChannel ("Public", publicChannelPSK); + addChannel ("BRNTest", BRNTestChannelPSK); + + persistent.doRepeat = 1; + persistent.allowReadOnly = 1; + + + persistent.latitude = 48190900; + persistent.longitude = 17030300; + persistent.altitude = 23400; +} + +void LoraApply() { + + MESH_LOGW (TAG, "LoraInit"); + LoRaInit(); + + + char useRegulatorLDO = 0; + + LoRaDebugPrint (0); + uint16_t loraBeginStat = LoRaBegin (currentLoRaSettings.frequencyInHz, currentLoRaSettings.txPowerInDbm, currentLoRaSettings.tcxoVoltage, useRegulatorLDO); + if (loraBeginStat != 0) { + MESH_LOGE (TAG, "Does not recognize the module"); + while (1) { + Delay_Ms(1000); + MESH_LOGE (TAG, "CRITICAL: LoRa not found, halted"); + } + } + + char crcOn = 1; + char invertIrq = 0; + + LoRaConfig (currentLoRaSettings.spreadingFactor, currentLoRaSettings.bandwidth, currentLoRaSettings.codingRate, currentLoRaSettings.preambleLength, 0, crcOn, invertIrq); +} \ No newline at end of file diff --git a/User/lib/config.h b/User/lib/config.h new file mode 100644 index 0000000..3fdefd9 --- /dev/null +++ b/User/lib/config.h @@ -0,0 +1,80 @@ +#ifndef CONFIG_HEADER +#define CONFIG_HEADER +#include "stdint.h" +#include "string.h" +#include "meshcore/packetstructs.h" + +#define FLASH_USER_PAGE_ADDR ((const void *)(0x08077F00)) + +#define ChannelCount 8 +//#define CONTACT_COUNT 100 +#define CONTACT_COUNT 16 + +#define VERSION "v0.0.1 - BRN Systems RISC-V" + +#define BOARD "WCH CH32V307" + +typedef struct LoRaSettings { + int8_t txPowerInDbm; + uint32_t frequencyInHz; + uint8_t spreadingFactor; + uint8_t bandwidth; + uint8_t codingRate; + uint16_t preambleLength; + uint16_t tcxoVoltage; +} LoRaSettings; + +extern LoRaSettings currentLoRaSettings; + +typedef struct { + uint32_t magic; // e.g. 0xDEADBEEF + + uint8_t privkey[32]; // Ed25519 private + uint8_t pubkey[32]; // Ed25519 public + + uint8_t nodeType; + char nodeName[32]; + + int32_t latitude; + int32_t longitude; + int32_t altitude; + + LoRaSettings loraSettings; + + Channel channels[ChannelCount]; + NodeEntry contacts[CONTACT_COUNT]; + + uint8_t password[16]; + uint8_t guestPassword[16]; + + uint8_t doRepeat; + uint8_t allowReadOnly; + uint16_t adcMultiplier; + uint16_t airtimeFactor; + uint32_t crc32; // integrity check +} PersistentData_t; + +extern PersistentData_t persistent; + +void saveConfig(); +void loadConfig(); + +void printNodeDB(); + +NodeEntry *getNextNode(); + +NodeEntry *getNode (uint8_t hash); + +Channel *getChannel (uint8_t hash, uint8_t ignoreCount); + +void addChannel (char *name, const uint8_t *key); + +NodeEntry *getNodePrefix (const uint8_t *hash); + +const char *getStringRole (uint8_t role); + +void populateDefaults(); + +void LoraApply(); + +#endif \ No newline at end of file diff --git a/User/lib/monocypher/monocypher-ed25519.c b/User/lib/monocypher/monocypher-ed25519.c new file mode 100644 index 0000000..8619117 --- /dev/null +++ b/User/lib/monocypher/monocypher-ed25519.c @@ -0,0 +1,503 @@ +// Monocypher version 4.0.3 +// +// This file is dual-licensed. Choose whichever licence you want from +// the two licences listed below. +// +// The first licence is a regular 2-clause BSD licence. The second licence +// is the CC-0 from Creative Commons. It is intended to release Monocypher +// to the public domain. The BSD licence serves as a fallback option. +// +// SPDX-License-Identifier: BSD-2-Clause OR CC0-1.0 +// +// ------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019, Loup Vaillant +// All rights reserved. +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ------------------------------------------------------------------------ +// +// Written in 2017-2019 by Loup Vaillant +// +// To the extent possible under law, the author(s) have dedicated all copyright +// and related neighboring rights to this software to the public domain +// worldwide. This software is distributed without any warranty. +// +// You should have received a copy of the CC0 Public Domain Dedication along +// with this software. If not, see +// + +#include "monocypher-ed25519.h" + +#ifdef MONOCYPHER_CPP_NAMESPACE +namespace MONOCYPHER_CPP_NAMESPACE { +#endif + +///////////////// +/// Utilities /// +///////////////// +#define FOR(i, min, max) for (size_t i = min; i < max; i++) +#define COPY(dst, src, size) FOR(_i_, 0, size) (dst)[_i_] = (src)[_i_] +#define ZERO(buf, size) FOR(_i_, 0, size) (buf)[_i_] = 0 +#define WIPE_CTX(ctx) crypto_wipe(ctx , sizeof(*(ctx))) +#define WIPE_BUFFER(buffer) crypto_wipe(buffer, sizeof(buffer)) +#define MIN(a, b) ((a) <= (b) ? (a) : (b)) +typedef uint8_t u8; +typedef uint64_t u64; + +// Returns the smallest positive integer y such that +// (x + y) % pow_2 == 0 +// Basically, it's how many bytes we need to add to "align" x. +// Only works when pow_2 is a power of 2. +// Note: we use ~x+1 instead of -x to avoid compiler warnings +static size_t align(size_t x, size_t pow_2) +{ + return (~x + 1) & (pow_2 - 1); +} + +static u64 load64_be(const u8 s[8]) +{ + return((u64)s[0] << 56) + | ((u64)s[1] << 48) + | ((u64)s[2] << 40) + | ((u64)s[3] << 32) + | ((u64)s[4] << 24) + | ((u64)s[5] << 16) + | ((u64)s[6] << 8) + | (u64)s[7]; +} + +static void store64_be(u8 out[8], u64 in) +{ + out[0] = (u8)(in >> 56); + out[1] = (u8)(in >> 48); + out[2] = (u8)(in >> 40); + out[3] = (u8)(in >> 32); + out[4] = (u8)(in >> 24); + out[5] = (u8)(in >> 16); + out[6] = (u8)(in >> 8); + out[7] = (u8) in ; +} + +static void load64_be_buf (u64 *dst, const u8 *src, size_t size) { + FOR(i, 0, size) { dst[i] = load64_be(src + i*8); } +} + +/////////////// +/// SHA 512 /// +/////////////// +static u64 rot(u64 x, int c ) { return (x >> c) | (x << (64 - c)); } +static u64 ch (u64 x, u64 y, u64 z) { return (x & y) ^ (~x & z); } +static u64 maj(u64 x, u64 y, u64 z) { return (x & y) ^ ( x & z) ^ (y & z); } +static u64 big_sigma0(u64 x) { return rot(x, 28) ^ rot(x, 34) ^ rot(x, 39); } +static u64 big_sigma1(u64 x) { return rot(x, 14) ^ rot(x, 18) ^ rot(x, 41); } +static u64 lit_sigma0(u64 x) { return rot(x, 1) ^ rot(x, 8) ^ (x >> 7); } +static u64 lit_sigma1(u64 x) { return rot(x, 19) ^ rot(x, 61) ^ (x >> 6); } + +static const u64 K[80] = { + 0x428a2f98d728ae22,0x7137449123ef65cd,0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc, + 0x3956c25bf348b538,0x59f111f1b605d019,0x923f82a4af194f9b,0xab1c5ed5da6d8118, + 0xd807aa98a3030242,0x12835b0145706fbe,0x243185be4ee4b28c,0x550c7dc3d5ffb4e2, + 0x72be5d74f27b896f,0x80deb1fe3b1696b1,0x9bdc06a725c71235,0xc19bf174cf692694, + 0xe49b69c19ef14ad2,0xefbe4786384f25e3,0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65, + 0x2de92c6f592b0275,0x4a7484aa6ea6e483,0x5cb0a9dcbd41fbd4,0x76f988da831153b5, + 0x983e5152ee66dfab,0xa831c66d2db43210,0xb00327c898fb213f,0xbf597fc7beef0ee4, + 0xc6e00bf33da88fc2,0xd5a79147930aa725,0x06ca6351e003826f,0x142929670a0e6e70, + 0x27b70a8546d22ffc,0x2e1b21385c26c926,0x4d2c6dfc5ac42aed,0x53380d139d95b3df, + 0x650a73548baf63de,0x766a0abb3c77b2a8,0x81c2c92e47edaee6,0x92722c851482353b, + 0xa2bfe8a14cf10364,0xa81a664bbc423001,0xc24b8b70d0f89791,0xc76c51a30654be30, + 0xd192e819d6ef5218,0xd69906245565a910,0xf40e35855771202a,0x106aa07032bbd1b8, + 0x19a4c116b8d2d0c8,0x1e376c085141ab53,0x2748774cdf8eeb99,0x34b0bcb5e19b48a8, + 0x391c0cb3c5c95a63,0x4ed8aa4ae3418acb,0x5b9cca4f7763e373,0x682e6ff3d6b2b8a3, + 0x748f82ee5defb2fc,0x78a5636f43172f60,0x84c87814a1f0ab72,0x8cc702081a6439ec, + 0x90befffa23631e28,0xa4506cebde82bde9,0xbef9a3f7b2c67915,0xc67178f2e372532b, + 0xca273eceea26619c,0xd186b8c721c0c207,0xeada7dd6cde0eb1e,0xf57d4f7fee6ed178, + 0x06f067aa72176fba,0x0a637dc5a2c898a6,0x113f9804bef90dae,0x1b710b35131c471b, + 0x28db77f523047d84,0x32caab7b40c72493,0x3c9ebe0a15c9bebc,0x431d67c49c100d4c, + 0x4cc5d4becb3e42b6,0x597f299cfc657e2a,0x5fcb6fab3ad6faec,0x6c44198c4a475817 +}; + +static void sha512_compress(crypto_sha512_ctx *ctx) +{ + u64 a = ctx->hash[0]; u64 b = ctx->hash[1]; + u64 c = ctx->hash[2]; u64 d = ctx->hash[3]; + u64 e = ctx->hash[4]; u64 f = ctx->hash[5]; + u64 g = ctx->hash[6]; u64 h = ctx->hash[7]; + + FOR (j, 0, 16) { + u64 in = K[j] + ctx->input[j]; + u64 t1 = big_sigma1(e) + ch (e, f, g) + h + in; + u64 t2 = big_sigma0(a) + maj(a, b, c); + h = g; g = f; f = e; e = d + t1; + d = c; c = b; b = a; a = t1 + t2; + } + size_t i16 = 0; + FOR(i, 1, 5) { + i16 += 16; + FOR (j, 0, 16) { + ctx->input[j] += lit_sigma1(ctx->input[(j- 2) & 15]); + ctx->input[j] += lit_sigma0(ctx->input[(j-15) & 15]); + ctx->input[j] += ctx->input[(j- 7) & 15]; + u64 in = K[i16 + j] + ctx->input[j]; + u64 t1 = big_sigma1(e) + ch (e, f, g) + h + in; + u64 t2 = big_sigma0(a) + maj(a, b, c); + h = g; g = f; f = e; e = d + t1; + d = c; c = b; b = a; a = t1 + t2; + } + } + + ctx->hash[0] += a; ctx->hash[1] += b; + ctx->hash[2] += c; ctx->hash[3] += d; + ctx->hash[4] += e; ctx->hash[5] += f; + ctx->hash[6] += g; ctx->hash[7] += h; +} + +// Write 1 input byte +static void sha512_set_input(crypto_sha512_ctx *ctx, u8 input) +{ + size_t word = ctx->input_idx >> 3; + size_t byte = ctx->input_idx & 7; + ctx->input[word] |= (u64)input << (8 * (7 - byte)); +} + +// Increment a 128-bit "word". +static void sha512_incr(u64 x[2], u64 y) +{ + x[1] += y; + if (x[1] < y) { + x[0]++; + } +} + +void crypto_sha512_init(crypto_sha512_ctx *ctx) +{ + ctx->hash[0] = 0x6a09e667f3bcc908; + ctx->hash[1] = 0xbb67ae8584caa73b; + ctx->hash[2] = 0x3c6ef372fe94f82b; + ctx->hash[3] = 0xa54ff53a5f1d36f1; + ctx->hash[4] = 0x510e527fade682d1; + ctx->hash[5] = 0x9b05688c2b3e6c1f; + ctx->hash[6] = 0x1f83d9abfb41bd6b; + ctx->hash[7] = 0x5be0cd19137e2179; + ctx->input_size[0] = 0; + ctx->input_size[1] = 0; + ctx->input_idx = 0; + ZERO(ctx->input, 16); +} + +void crypto_sha512_update(crypto_sha512_ctx *ctx, + const u8 *message, size_t message_size) +{ + // Avoid undefined NULL pointer increments with empty messages + if (message_size == 0) { + return; + } + + // Align ourselves with word boundaries + if ((ctx->input_idx & 7) != 0) { + size_t nb_bytes = MIN(align(ctx->input_idx, 8), message_size); + FOR (i, 0, nb_bytes) { + sha512_set_input(ctx, message[i]); + ctx->input_idx++; + } + message += nb_bytes; + message_size -= nb_bytes; + } + + // Align ourselves with block boundaries + if ((ctx->input_idx & 127) != 0) { + size_t nb_words = MIN(align(ctx->input_idx, 128), message_size) >> 3; + load64_be_buf(ctx->input + (ctx->input_idx >> 3), message, nb_words); + ctx->input_idx += nb_words << 3; + message += nb_words << 3; + message_size -= nb_words << 3; + } + + // Compress block if needed + if (ctx->input_idx == 128) { + sha512_incr(ctx->input_size, 1024); // size is in bits + sha512_compress(ctx); + ctx->input_idx = 0; + ZERO(ctx->input, 16); + } + + // Process the message block by block + FOR (i, 0, message_size >> 7) { // number of blocks + load64_be_buf(ctx->input, message, 16); + sha512_incr(ctx->input_size, 1024); // size is in bits + sha512_compress(ctx); + ctx->input_idx = 0; + ZERO(ctx->input, 16); + message += 128; + } + message_size &= 127; + + if (message_size != 0) { + // Remaining words + size_t nb_words = message_size >> 3; + load64_be_buf(ctx->input, message, nb_words); + ctx->input_idx += nb_words << 3; + message += nb_words << 3; + message_size -= nb_words << 3; + + // Remaining bytes + FOR (i, 0, message_size) { + sha512_set_input(ctx, message[i]); + ctx->input_idx++; + } + } +} + +void crypto_sha512_final(crypto_sha512_ctx *ctx, u8 hash[64]) +{ + // Add padding bit + if (ctx->input_idx == 0) { + ZERO(ctx->input, 16); + } + sha512_set_input(ctx, 128); + + // Update size + sha512_incr(ctx->input_size, ctx->input_idx * 8); + + // Compress penultimate block (if any) + if (ctx->input_idx > 111) { + sha512_compress(ctx); + ZERO(ctx->input, 14); + } + // Compress last block + ctx->input[14] = ctx->input_size[0]; + ctx->input[15] = ctx->input_size[1]; + sha512_compress(ctx); + + // Copy hash to output (big endian) + FOR (i, 0, 8) { + store64_be(hash + i*8, ctx->hash[i]); + } + + WIPE_CTX(ctx); +} + +void crypto_sha512(u8 hash[64], const u8 *message, size_t message_size) +{ + crypto_sha512_ctx ctx; + crypto_sha512_init (&ctx); + crypto_sha512_update(&ctx, message, message_size); + crypto_sha512_final (&ctx, hash); +} + +//////////////////// +/// HMAC SHA 512 /// +//////////////////// +void crypto_sha512_hmac_init(crypto_sha512_hmac_ctx *ctx, + const u8 *key, size_t key_size) +{ + // hash key if it is too long + if (key_size > 128) { + crypto_sha512(ctx->key, key, key_size); + key = ctx->key; + key_size = 64; + } + // Compute inner key: padded key XOR 0x36 + FOR (i, 0, key_size) { ctx->key[i] = key[i] ^ 0x36; } + FOR (i, key_size, 128) { ctx->key[i] = 0x36; } + // Start computing inner hash + crypto_sha512_init (&ctx->ctx); + crypto_sha512_update(&ctx->ctx, ctx->key, 128); +} + +void crypto_sha512_hmac_update(crypto_sha512_hmac_ctx *ctx, + const u8 *message, size_t message_size) +{ + crypto_sha512_update(&ctx->ctx, message, message_size); +} + +void crypto_sha512_hmac_final(crypto_sha512_hmac_ctx *ctx, u8 hmac[64]) +{ + // Finish computing inner hash + crypto_sha512_final(&ctx->ctx, hmac); + // Compute outer key: padded key XOR 0x5c + FOR (i, 0, 128) { + ctx->key[i] ^= 0x36 ^ 0x5c; + } + // Compute outer hash + crypto_sha512_init (&ctx->ctx); + crypto_sha512_update(&ctx->ctx, ctx->key , 128); + crypto_sha512_update(&ctx->ctx, hmac, 64); + crypto_sha512_final (&ctx->ctx, hmac); // outer hash + WIPE_CTX(ctx); +} + +void crypto_sha512_hmac(u8 hmac[64], const u8 *key, size_t key_size, + const u8 *message, size_t message_size) +{ + crypto_sha512_hmac_ctx ctx; + crypto_sha512_hmac_init (&ctx, key, key_size); + crypto_sha512_hmac_update(&ctx, message, message_size); + crypto_sha512_hmac_final (&ctx, hmac); +} + +//////////////////// +/// HKDF SHA 512 /// +//////////////////// +void crypto_sha512_hkdf_expand(u8 *okm, size_t okm_size, + const u8 *prk, size_t prk_size, + const u8 *info, size_t info_size) +{ + int not_first = 0; + u8 ctr = 1; + u8 blk[64]; + + while (okm_size > 0) { + size_t out_size = MIN(okm_size, sizeof(blk)); + + crypto_sha512_hmac_ctx ctx; + crypto_sha512_hmac_init(&ctx, prk , prk_size); + if (not_first) { + // For some reason HKDF uses some kind of CBC mode. + // For some reason CTR mode alone wasn't enough. + // Like what, they didn't trust HMAC in 2010? Really?? + crypto_sha512_hmac_update(&ctx, blk , sizeof(blk)); + } + crypto_sha512_hmac_update(&ctx, info, info_size); + crypto_sha512_hmac_update(&ctx, &ctr, 1); + crypto_sha512_hmac_final(&ctx, blk); + + COPY(okm, blk, out_size); + + not_first = 1; + okm += out_size; + okm_size -= out_size; + ctr++; + } + WIPE_BUFFER(blk); +} + +void crypto_sha512_hkdf(u8 *okm , size_t okm_size, + const u8 *ikm , size_t ikm_size, + const u8 *salt, size_t salt_size, + const u8 *info, size_t info_size) +{ + // Extract + u8 prk[64]; + crypto_sha512_hmac(prk, salt, salt_size, ikm, ikm_size); + + // Expand + crypto_sha512_hkdf_expand(okm, okm_size, prk, sizeof(prk), info, info_size); + + WIPE_BUFFER(prk); +} + +/////////////// +/// Ed25519 /// +/////////////// +void crypto_ed25519_key_pair(u8 secret_key[64], u8 public_key[32], u8 seed[32]) +{ + u8 a[64]; + COPY(a, seed, 32); // a[ 0..31] = seed + crypto_wipe(seed, 32); + COPY(secret_key, a, 32); // secret key = seed + crypto_sha512(a, a, 32); // a[ 0..31] = scalar + crypto_eddsa_trim_scalar(a, a); // a[ 0..31] = trimmed scalar + crypto_eddsa_scalarbase(public_key, a); // public key = [trimmed scalar]B + COPY(secret_key + 32, public_key, 32); // secret key includes public half + WIPE_BUFFER(a); +} + +static void hash_reduce(u8 h[32], + const u8 *a, size_t a_size, + const u8 *b, size_t b_size, + const u8 *c, size_t c_size, + const u8 *d, size_t d_size) +{ + u8 hash[64]; + crypto_sha512_ctx ctx; + crypto_sha512_init (&ctx); + crypto_sha512_update(&ctx, a, a_size); + crypto_sha512_update(&ctx, b, b_size); + crypto_sha512_update(&ctx, c, c_size); + crypto_sha512_update(&ctx, d, d_size); + crypto_sha512_final (&ctx, hash); + crypto_eddsa_reduce(h, hash); +} + +static void ed25519_dom_sign(u8 signature[64], const u8 secret_key[64], + const u8 *dom, size_t dom_size, + const u8 *message, size_t message_size) +{ + u8 a[64]; // secret scalar and prefix + u8 r[32]; // secret deterministic "random" nonce + u8 h[32]; // publically verifiable hash of the message (not wiped) + u8 R[32]; // first half of the signature (allows overlapping inputs) + const u8 *pk = secret_key + 32; + + crypto_sha512(a, secret_key, 32); + crypto_eddsa_trim_scalar(a, a); + hash_reduce(r, dom, dom_size, a + 32, 32, message, message_size, 0, 0); + crypto_eddsa_scalarbase(R, r); + hash_reduce(h, dom, dom_size, R, 32, pk, 32, message, message_size); + COPY(signature, R, 32); + crypto_eddsa_mul_add(signature + 32, h, a, r); + + WIPE_BUFFER(a); + WIPE_BUFFER(r); +} + +void crypto_ed25519_sign(u8 signature [64], const u8 secret_key[64], + const u8 *message, size_t message_size) +{ + ed25519_dom_sign(signature, secret_key, 0, 0, message, message_size); +} + +int crypto_ed25519_check(const u8 signature[64], const u8 public_key[32], + const u8 *msg, size_t msg_size) +{ + u8 h_ram[32]; + hash_reduce(h_ram, signature, 32, public_key, 32, msg, msg_size, 0, 0); + return crypto_eddsa_check_equation(signature, public_key, h_ram); +} + +static const u8 domain[34] = "SigEd25519 no Ed25519 collisions\1"; + +void crypto_ed25519_ph_sign(uint8_t signature[64], const uint8_t secret_key[64], + const uint8_t message_hash[64]) +{ + ed25519_dom_sign(signature, secret_key, domain, sizeof(domain), + message_hash, 64); +} + +int crypto_ed25519_ph_check(const uint8_t sig[64], const uint8_t pk[32], + const uint8_t msg_hash[64]) +{ + u8 h_ram[32]; + hash_reduce(h_ram, domain, sizeof(domain), sig, 32, pk, 32, msg_hash, 64); + return crypto_eddsa_check_equation(sig, pk, h_ram); +} + + +#ifdef MONOCYPHER_CPP_NAMESPACE +} +#endif diff --git a/User/lib/monocypher/monocypher-ed25519.h b/User/lib/monocypher/monocypher-ed25519.h new file mode 100644 index 0000000..9ad1c54 --- /dev/null +++ b/User/lib/monocypher/monocypher-ed25519.h @@ -0,0 +1,140 @@ +// Monocypher version 4.0.3 +// +// This file is dual-licensed. Choose whichever licence you want from +// the two licences listed below. +// +// The first licence is a regular 2-clause BSD licence. The second licence +// is the CC-0 from Creative Commons. It is intended to release Monocypher +// to the public domain. The BSD licence serves as a fallback option. +// +// SPDX-License-Identifier: BSD-2-Clause OR CC0-1.0 +// +// ------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019, Loup Vaillant +// All rights reserved. +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ------------------------------------------------------------------------ +// +// Written in 2017-2019 by Loup Vaillant +// +// To the extent possible under law, the author(s) have dedicated all copyright +// and related neighboring rights to this software to the public domain +// worldwide. This software is distributed without any warranty. +// +// You should have received a copy of the CC0 Public Domain Dedication along +// with this software. If not, see +// + +#ifndef ED25519_H +#define ED25519_H + +#include "monocypher.h" + +#ifdef MONOCYPHER_CPP_NAMESPACE +namespace MONOCYPHER_CPP_NAMESPACE { +#elif defined(__cplusplus) +extern "C" { +#endif + +//////////////////////// +/// Type definitions /// +//////////////////////// + +// Do not rely on the size or content on any of those types, +// they may change without notice. +typedef struct { + uint64_t hash[8]; + uint64_t input[16]; + uint64_t input_size[2]; + size_t input_idx; +} crypto_sha512_ctx; + +typedef struct { + uint8_t key[128]; + crypto_sha512_ctx ctx; +} crypto_sha512_hmac_ctx; + + +// SHA 512 +// ------- +void crypto_sha512_init (crypto_sha512_ctx *ctx); +void crypto_sha512_update(crypto_sha512_ctx *ctx, + const uint8_t *message, size_t message_size); +void crypto_sha512_final (crypto_sha512_ctx *ctx, uint8_t hash[64]); +void crypto_sha512(uint8_t hash[64], + const uint8_t *message, size_t message_size); + +// SHA 512 HMAC +// ------------ +void crypto_sha512_hmac_init(crypto_sha512_hmac_ctx *ctx, + const uint8_t *key, size_t key_size); +void crypto_sha512_hmac_update(crypto_sha512_hmac_ctx *ctx, + const uint8_t *message, size_t message_size); +void crypto_sha512_hmac_final(crypto_sha512_hmac_ctx *ctx, uint8_t hmac[64]); +void crypto_sha512_hmac(uint8_t hmac[64], + const uint8_t *key , size_t key_size, + const uint8_t *message, size_t message_size); + +// SHA 512 HKDF +// ------------ +void crypto_sha512_hkdf_expand(uint8_t *okm, size_t okm_size, + const uint8_t *prk, size_t prk_size, + const uint8_t *info, size_t info_size); +void crypto_sha512_hkdf(uint8_t *okm , size_t okm_size, + const uint8_t *ikm , size_t ikm_size, + const uint8_t *salt, size_t salt_size, + const uint8_t *info, size_t info_size); + +// Ed25519 +// ------- +// Signatures (EdDSA with curve25519 + SHA-512) +// -------------------------------------------- +void crypto_ed25519_key_pair(uint8_t secret_key[64], + uint8_t public_key[32], + uint8_t seed[32]); +void crypto_ed25519_sign(uint8_t signature [64], + const uint8_t secret_key[64], + const uint8_t *message, size_t message_size); +int crypto_ed25519_check(const uint8_t signature [64], + const uint8_t public_key[32], + const uint8_t *message, size_t message_size); + +// Pre-hash variants +void crypto_ed25519_ph_sign(uint8_t signature [64], + const uint8_t secret_key [64], + const uint8_t message_hash[64]); +int crypto_ed25519_ph_check(const uint8_t signature [64], + const uint8_t public_key [32], + const uint8_t message_hash[64]); + +#ifdef __cplusplus +} +#endif + +#endif // ED25519_H diff --git a/User/lib/monocypher/monocypher.c b/User/lib/monocypher/monocypher.c new file mode 100644 index 0000000..fe5bbdc --- /dev/null +++ b/User/lib/monocypher/monocypher.c @@ -0,0 +1,2988 @@ +// Monocypher version 4.0.3 +// +// This file is dual-licensed. Choose whichever licence you want from +// the two licences listed below. +// +// The first licence is a regular 2-clause BSD licence. The second licence +// is the CC-0 from Creative Commons. It is intended to release Monocypher +// to the public domain. The BSD licence serves as a fallback option. +// +// SPDX-License-Identifier: BSD-2-Clause OR CC0-1.0 +// +// ------------------------------------------------------------------------ +// +// Copyright (c) 2017-2020, Loup Vaillant +// All rights reserved. +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ------------------------------------------------------------------------ +// +// Written in 2017-2020 by Loup Vaillant +// +// To the extent possible under law, the author(s) have dedicated all copyright +// and related neighboring rights to this software to the public domain +// worldwide. This software is distributed without any warranty. +// +// You should have received a copy of the CC0 Public Domain Dedication along +// with this software. If not, see +// + +#include "monocypher.h" + +#ifdef MONOCYPHER_CPP_NAMESPACE +namespace MONOCYPHER_CPP_NAMESPACE { +#endif + +///////////////// +/// Utilities /// +///////////////// +#define FOR_T(type, i, start, end) for (type i = (start); i < (end); i++) +#define FOR(i, start, end) FOR_T(size_t, i, start, end) +#define COPY(dst, src, size) FOR(_i_, 0, size) (dst)[_i_] = (src)[_i_] +#define ZERO(buf, size) FOR(_i_, 0, size) (buf)[_i_] = 0 +#define WIPE_CTX(ctx) crypto_wipe(ctx , sizeof(*(ctx))) +#define WIPE_BUFFER(buffer) crypto_wipe(buffer, sizeof(buffer)) +#define MIN(a, b) ((a) <= (b) ? (a) : (b)) +#define MAX(a, b) ((a) >= (b) ? (a) : (b)) + +typedef int8_t i8; +typedef uint8_t u8; +typedef int16_t i16; +typedef uint32_t u32; +typedef int32_t i32; +typedef int64_t i64; +typedef uint64_t u64; + +static const u8 zero[128] = {0}; + +// returns the smallest positive integer y such that +// (x + y) % pow_2 == 0 +// Basically, y is the "gap" missing to align x. +// Only works when pow_2 is a power of 2. +// Note: we use ~x+1 instead of -x to avoid compiler warnings +static size_t gap(size_t x, size_t pow_2) +{ + return (~x + 1) & (pow_2 - 1); +} + +static u32 load24_le(const u8 s[3]) +{ + return + ((u32)s[0] << 0) | + ((u32)s[1] << 8) | + ((u32)s[2] << 16); +} + +static u32 load32_le(const u8 s[4]) +{ + return + ((u32)s[0] << 0) | + ((u32)s[1] << 8) | + ((u32)s[2] << 16) | + ((u32)s[3] << 24); +} + +static u64 load64_le(const u8 s[8]) +{ + return load32_le(s) | ((u64)load32_le(s+4) << 32); +} + +static void store32_le(u8 out[4], u32 in) +{ + out[0] = (u8)(in ); + out[1] = (u8)(in >> 8); + out[2] = (u8)(in >> 16); + out[3] = (u8)(in >> 24); +} + +static void store64_le(u8 out[8], u64 in) +{ + store32_le(out , (u32)(in )); + store32_le(out + 4, (u32)(in >> 32)); +} + +static void load32_le_buf (u32 *dst, const u8 *src, size_t size) { + FOR(i, 0, size) { dst[i] = load32_le(src + i*4); } +} +static void load64_le_buf (u64 *dst, const u8 *src, size_t size) { + FOR(i, 0, size) { dst[i] = load64_le(src + i*8); } +} +static void store32_le_buf(u8 *dst, const u32 *src, size_t size) { + FOR(i, 0, size) { store32_le(dst + i*4, src[i]); } +} +static void store64_le_buf(u8 *dst, const u64 *src, size_t size) { + FOR(i, 0, size) { store64_le(dst + i*8, src[i]); } +} + +static u64 rotr64(u64 x, u64 n) { return (x >> n) ^ (x << (64 - n)); } +static u32 rotl32(u32 x, u32 n) { return (x << n) ^ (x >> (32 - n)); } + +static int neq0(u64 diff) +{ + // constant time comparison to zero + // return diff != 0 ? -1 : 0 + u64 half = (diff >> 32) | ((u32)diff); // half < 2^32 + u64 eq0 = 1 & ((half - 1) >> 32); // half == 0 ? 1 : 0 + return (int)eq0 - 1; // half == 0 ? 0 : -1 +} + +static u64 x16(const u8 a[16], const u8 b[16]) +{ + return (load64_le(a + 0) ^ load64_le(b + 0)) + | (load64_le(a + 8) ^ load64_le(b + 8)); +} +static u64 x32(const u8 a[32],const u8 b[32]){return x16(a,b)| x16(a+16, b+16);} +static u64 x64(const u8 a[64],const u8 b[64]){return x32(a,b)| x32(a+32, b+32);} +int crypto_verify16(const u8 a[16], const u8 b[16]){ return neq0(x16(a, b)); } +int crypto_verify32(const u8 a[32], const u8 b[32]){ return neq0(x32(a, b)); } +int crypto_verify64(const u8 a[64], const u8 b[64]){ return neq0(x64(a, b)); } + +void crypto_wipe(void *secret, size_t size) +{ + volatile u8 *v_secret = (u8*)secret; + ZERO(v_secret, size); +} + +///////////////// +/// Chacha 20 /// +///////////////// +#define QUARTERROUND(a, b, c, d) \ + a += b; d = rotl32(d ^ a, 16); \ + c += d; b = rotl32(b ^ c, 12); \ + a += b; d = rotl32(d ^ a, 8); \ + c += d; b = rotl32(b ^ c, 7) + +static void chacha20_rounds(u32 out[16], const u32 in[16]) +{ + // The temporary variables make Chacha20 10% faster. + u32 t0 = in[ 0]; u32 t1 = in[ 1]; u32 t2 = in[ 2]; u32 t3 = in[ 3]; + u32 t4 = in[ 4]; u32 t5 = in[ 5]; u32 t6 = in[ 6]; u32 t7 = in[ 7]; + u32 t8 = in[ 8]; u32 t9 = in[ 9]; u32 t10 = in[10]; u32 t11 = in[11]; + u32 t12 = in[12]; u32 t13 = in[13]; u32 t14 = in[14]; u32 t15 = in[15]; + + FOR (i, 0, 10) { // 20 rounds, 2 rounds per loop. + QUARTERROUND(t0, t4, t8 , t12); // column 0 + QUARTERROUND(t1, t5, t9 , t13); // column 1 + QUARTERROUND(t2, t6, t10, t14); // column 2 + QUARTERROUND(t3, t7, t11, t15); // column 3 + QUARTERROUND(t0, t5, t10, t15); // diagonal 0 + QUARTERROUND(t1, t6, t11, t12); // diagonal 1 + QUARTERROUND(t2, t7, t8 , t13); // diagonal 2 + QUARTERROUND(t3, t4, t9 , t14); // diagonal 3 + } + out[ 0] = t0; out[ 1] = t1; out[ 2] = t2; out[ 3] = t3; + out[ 4] = t4; out[ 5] = t5; out[ 6] = t6; out[ 7] = t7; + out[ 8] = t8; out[ 9] = t9; out[10] = t10; out[11] = t11; + out[12] = t12; out[13] = t13; out[14] = t14; out[15] = t15; +} + +static const u8 *chacha20_constant = (const u8*)"expand 32-byte k"; // 16 bytes + +void crypto_chacha20_h(u8 out[32], const u8 key[32], const u8 in [16]) +{ + u32 block[16]; + load32_le_buf(block , chacha20_constant, 4); + load32_le_buf(block + 4, key , 8); + load32_le_buf(block + 12, in , 4); + + chacha20_rounds(block, block); + + // prevent reversal of the rounds by revealing only half of the buffer. + store32_le_buf(out , block , 4); // constant + store32_le_buf(out+16, block+12, 4); // counter and nonce + WIPE_BUFFER(block); +} + +u64 crypto_chacha20_djb(u8 *cipher_text, const u8 *plain_text, + size_t text_size, const u8 key[32], const u8 nonce[8], + u64 ctr) +{ + u32 input[16]; + load32_le_buf(input , chacha20_constant, 4); + load32_le_buf(input + 4, key , 8); + load32_le_buf(input + 14, nonce , 2); + input[12] = (u32) ctr; + input[13] = (u32)(ctr >> 32); + + // Whole blocks + u32 pool[16]; + size_t nb_blocks = text_size >> 6; + FOR (i, 0, nb_blocks) { + chacha20_rounds(pool, input); + if (plain_text != NULL) { + FOR (j, 0, 16) { + u32 p = pool[j] + input[j]; + store32_le(cipher_text, p ^ load32_le(plain_text)); + cipher_text += 4; + plain_text += 4; + } + } else { + FOR (j, 0, 16) { + u32 p = pool[j] + input[j]; + store32_le(cipher_text, p); + cipher_text += 4; + } + } + input[12]++; + if (input[12] == 0) { + input[13]++; + } + } + text_size &= 63; + + // Last (incomplete) block + if (text_size > 0) { + if (plain_text == NULL) { + plain_text = zero; + } + chacha20_rounds(pool, input); + u8 tmp[64]; + FOR (i, 0, 16) { + store32_le(tmp + i*4, pool[i] + input[i]); + } + FOR (i, 0, text_size) { + cipher_text[i] = tmp[i] ^ plain_text[i]; + } + WIPE_BUFFER(tmp); + } + ctr = input[12] + ((u64)input[13] << 32) + (text_size > 0); + + WIPE_BUFFER(pool); + WIPE_BUFFER(input); + return ctr; +} + +u32 crypto_chacha20_ietf(u8 *cipher_text, const u8 *plain_text, + size_t text_size, + const u8 key[32], const u8 nonce[12], u32 ctr) +{ + u64 big_ctr = ctr + ((u64)load32_le(nonce) << 32); + return (u32)crypto_chacha20_djb(cipher_text, plain_text, text_size, + key, nonce + 4, big_ctr); +} + +u64 crypto_chacha20_x(u8 *cipher_text, const u8 *plain_text, + size_t text_size, + const u8 key[32], const u8 nonce[24], u64 ctr) +{ + u8 sub_key[32]; + crypto_chacha20_h(sub_key, key, nonce); + ctr = crypto_chacha20_djb(cipher_text, plain_text, text_size, + sub_key, nonce + 16, ctr); + WIPE_BUFFER(sub_key); + return ctr; +} + +///////////////// +/// Poly 1305 /// +///////////////// + +// h = (h + c) * r +// preconditions: +// ctx->h <= 4_ffffffff_ffffffff_ffffffff_ffffffff +// ctx->r <= 0ffffffc_0ffffffc_0ffffffc_0fffffff +// end <= 1 +// Postcondition: +// ctx->h <= 4_ffffffff_ffffffff_ffffffff_ffffffff +static void poly_blocks(crypto_poly1305_ctx *ctx, const u8 *in, + size_t nb_blocks, unsigned end) +{ + // Local all the things! + const u32 r0 = ctx->r[0]; + const u32 r1 = ctx->r[1]; + const u32 r2 = ctx->r[2]; + const u32 r3 = ctx->r[3]; + const u32 rr0 = (r0 >> 2) * 5; // lose 2 bits... + const u32 rr1 = (r1 >> 2) + r1; // rr1 == (r1 >> 2) * 5 + const u32 rr2 = (r2 >> 2) + r2; // rr1 == (r2 >> 2) * 5 + const u32 rr3 = (r3 >> 2) + r3; // rr1 == (r3 >> 2) * 5 + const u32 rr4 = r0 & 3; // ...recover 2 bits + u32 h0 = ctx->h[0]; + u32 h1 = ctx->h[1]; + u32 h2 = ctx->h[2]; + u32 h3 = ctx->h[3]; + u32 h4 = ctx->h[4]; + + FOR (i, 0, nb_blocks) { + // h + c, without carry propagation + const u64 s0 = (u64)h0 + load32_le(in); in += 4; + const u64 s1 = (u64)h1 + load32_le(in); in += 4; + const u64 s2 = (u64)h2 + load32_le(in); in += 4; + const u64 s3 = (u64)h3 + load32_le(in); in += 4; + const u32 s4 = h4 + end; + + // (h + c) * r, without carry propagation + const u64 x0 = s0*r0+ s1*rr3+ s2*rr2+ s3*rr1+ s4*rr0; + const u64 x1 = s0*r1+ s1*r0 + s2*rr3+ s3*rr2+ s4*rr1; + const u64 x2 = s0*r2+ s1*r1 + s2*r0 + s3*rr3+ s4*rr2; + const u64 x3 = s0*r3+ s1*r2 + s2*r1 + s3*r0 + s4*rr3; + const u32 x4 = s4*rr4; + + // partial reduction modulo 2^130 - 5 + const u32 u5 = (u32)(x3 >> 32) + x4; // u5 <= 7ffffff5 + const u64 u0 = (u32)(u5 >> 2) * 5 + (x0 & 0xffffffff); + const u64 u1 = (u32)(u0 >> 32) + (x1 & 0xffffffff) + (x0 >> 32); + const u64 u2 = (u32)(u1 >> 32) + (x2 & 0xffffffff) + (x1 >> 32); + const u64 u3 = (u32)(u2 >> 32) + (x3 & 0xffffffff) + (x2 >> 32); + const u32 u4 = (u32)(u3 >> 32) + (u5 & 3); // u4 <= 4 + + // Update the hash + h0 = u0 & 0xffffffff; + h1 = u1 & 0xffffffff; + h2 = u2 & 0xffffffff; + h3 = u3 & 0xffffffff; + h4 = u4; + } + ctx->h[0] = h0; + ctx->h[1] = h1; + ctx->h[2] = h2; + ctx->h[3] = h3; + ctx->h[4] = h4; +} + +void crypto_poly1305_init(crypto_poly1305_ctx *ctx, const u8 key[32]) +{ + ZERO(ctx->h, 5); // Initial hash is zero + ctx->c_idx = 0; + // load r and pad (r has some of its bits cleared) + load32_le_buf(ctx->r , key , 4); + load32_le_buf(ctx->pad, key+16, 4); + FOR (i, 0, 1) { ctx->r[i] &= 0x0fffffff; } + FOR (i, 1, 4) { ctx->r[i] &= 0x0ffffffc; } +} + +void crypto_poly1305_update(crypto_poly1305_ctx *ctx, + const u8 *message, size_t message_size) +{ + // Avoid undefined NULL pointer increments with empty messages + if (message_size == 0) { + return; + } + + // Align ourselves with block boundaries + size_t aligned = MIN(gap(ctx->c_idx, 16), message_size); + FOR (i, 0, aligned) { + ctx->c[ctx->c_idx] = *message; + ctx->c_idx++; + message++; + message_size--; + } + + // If block is complete, process it + if (ctx->c_idx == 16) { + poly_blocks(ctx, ctx->c, 1, 1); + ctx->c_idx = 0; + } + + // Process the message block by block + size_t nb_blocks = message_size >> 4; + poly_blocks(ctx, message, nb_blocks, 1); + message += nb_blocks << 4; + message_size &= 15; + + // remaining bytes (we never complete a block here) + FOR (i, 0, message_size) { + ctx->c[ctx->c_idx] = message[i]; + ctx->c_idx++; + } +} + +void crypto_poly1305_final(crypto_poly1305_ctx *ctx, u8 mac[16]) +{ + // Process the last block (if any) + // We move the final 1 according to remaining input length + // (this will add less than 2^130 to the last input block) + if (ctx->c_idx != 0) { + ZERO(ctx->c + ctx->c_idx, 16 - ctx->c_idx); + ctx->c[ctx->c_idx] = 1; + poly_blocks(ctx, ctx->c, 1, 0); + } + + // check if we should subtract 2^130-5 by performing the + // corresponding carry propagation. + u64 c = 5; + FOR (i, 0, 4) { + c += ctx->h[i]; + c >>= 32; + } + c += ctx->h[4]; + c = (c >> 2) * 5; // shift the carry back to the beginning + // c now indicates how many times we should subtract 2^130-5 (0 or 1) + FOR (i, 0, 4) { + c += (u64)ctx->h[i] + ctx->pad[i]; + store32_le(mac + i*4, (u32)c); + c = c >> 32; + } + WIPE_CTX(ctx); +} + +void crypto_poly1305(u8 mac[16], const u8 *message, + size_t message_size, const u8 key[32]) +{ + crypto_poly1305_ctx ctx; + crypto_poly1305_init (&ctx, key); + crypto_poly1305_update(&ctx, message, message_size); + crypto_poly1305_final (&ctx, mac); +} + +//////////////// +/// BLAKE2 b /// +//////////////// +static const u64 iv[8] = { + 0x6a09e667f3bcc908, 0xbb67ae8584caa73b, + 0x3c6ef372fe94f82b, 0xa54ff53a5f1d36f1, + 0x510e527fade682d1, 0x9b05688c2b3e6c1f, + 0x1f83d9abfb41bd6b, 0x5be0cd19137e2179, +}; + +static void blake2b_compress(crypto_blake2b_ctx *ctx, int is_last_block) +{ + static const u8 sigma[12][16] = { + { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, + { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 }, + { 11, 8, 12, 0, 5, 2, 15, 13, 10, 14, 3, 6, 7, 1, 9, 4 }, + { 7, 9, 3, 1, 13, 12, 11, 14, 2, 6, 5, 10, 4, 0, 15, 8 }, + { 9, 0, 5, 7, 2, 4, 10, 15, 14, 1, 11, 12, 6, 8, 3, 13 }, + { 2, 12, 6, 10, 0, 11, 8, 3, 4, 13, 7, 5, 15, 14, 1, 9 }, + { 12, 5, 1, 15, 14, 13, 4, 10, 0, 7, 6, 3, 9, 2, 8, 11 }, + { 13, 11, 7, 14, 12, 1, 3, 9, 5, 0, 15, 4, 8, 6, 2, 10 }, + { 6, 15, 14, 9, 11, 3, 0, 8, 12, 2, 13, 7, 1, 4, 10, 5 }, + { 10, 2, 8, 4, 7, 6, 1, 5, 15, 11, 9, 14, 3, 12, 13, 0 }, + { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }, + { 14, 10, 4, 8, 9, 15, 13, 6, 1, 12, 0, 2, 11, 7, 5, 3 }, + }; + + // increment input offset + u64 *x = ctx->input_offset; + size_t y = ctx->input_idx; + x[0] += y; + if (x[0] < y) { + x[1]++; + } + + // init work vector + u64 v0 = ctx->hash[0]; u64 v8 = iv[0]; + u64 v1 = ctx->hash[1]; u64 v9 = iv[1]; + u64 v2 = ctx->hash[2]; u64 v10 = iv[2]; + u64 v3 = ctx->hash[3]; u64 v11 = iv[3]; + u64 v4 = ctx->hash[4]; u64 v12 = iv[4] ^ ctx->input_offset[0]; + u64 v5 = ctx->hash[5]; u64 v13 = iv[5] ^ ctx->input_offset[1]; + u64 v6 = ctx->hash[6]; u64 v14 = iv[6] ^ (u64)~(is_last_block - 1); + u64 v7 = ctx->hash[7]; u64 v15 = iv[7]; + + // mangle work vector + u64 *input = ctx->input; +#define BLAKE2_G(a, b, c, d, x, y) \ + a += b + x; d = rotr64(d ^ a, 32); \ + c += d; b = rotr64(b ^ c, 24); \ + a += b + y; d = rotr64(d ^ a, 16); \ + c += d; b = rotr64(b ^ c, 63) +#define BLAKE2_ROUND(i) \ + BLAKE2_G(v0, v4, v8 , v12, input[sigma[i][ 0]], input[sigma[i][ 1]]); \ + BLAKE2_G(v1, v5, v9 , v13, input[sigma[i][ 2]], input[sigma[i][ 3]]); \ + BLAKE2_G(v2, v6, v10, v14, input[sigma[i][ 4]], input[sigma[i][ 5]]); \ + BLAKE2_G(v3, v7, v11, v15, input[sigma[i][ 6]], input[sigma[i][ 7]]); \ + BLAKE2_G(v0, v5, v10, v15, input[sigma[i][ 8]], input[sigma[i][ 9]]); \ + BLAKE2_G(v1, v6, v11, v12, input[sigma[i][10]], input[sigma[i][11]]); \ + BLAKE2_G(v2, v7, v8 , v13, input[sigma[i][12]], input[sigma[i][13]]); \ + BLAKE2_G(v3, v4, v9 , v14, input[sigma[i][14]], input[sigma[i][15]]) + +#ifdef BLAKE2_NO_UNROLLING + FOR (i, 0, 12) { + BLAKE2_ROUND(i); + } +#else + BLAKE2_ROUND(0); BLAKE2_ROUND(1); BLAKE2_ROUND(2); BLAKE2_ROUND(3); + BLAKE2_ROUND(4); BLAKE2_ROUND(5); BLAKE2_ROUND(6); BLAKE2_ROUND(7); + BLAKE2_ROUND(8); BLAKE2_ROUND(9); BLAKE2_ROUND(10); BLAKE2_ROUND(11); +#endif + + // update hash + ctx->hash[0] ^= v0 ^ v8; ctx->hash[1] ^= v1 ^ v9; + ctx->hash[2] ^= v2 ^ v10; ctx->hash[3] ^= v3 ^ v11; + ctx->hash[4] ^= v4 ^ v12; ctx->hash[5] ^= v5 ^ v13; + ctx->hash[6] ^= v6 ^ v14; ctx->hash[7] ^= v7 ^ v15; +} + +void crypto_blake2b_keyed_init(crypto_blake2b_ctx *ctx, size_t hash_size, + const u8 *key, size_t key_size) +{ + // initial hash + COPY(ctx->hash, iv, 8); + ctx->hash[0] ^= 0x01010000 ^ (key_size << 8) ^ hash_size; + + ctx->input_offset[0] = 0; // beginning of the input, no offset + ctx->input_offset[1] = 0; // beginning of the input, no offset + ctx->hash_size = hash_size; + ctx->input_idx = 0; + ZERO(ctx->input, 16); + + // if there is a key, the first block is that key (padded with zeroes) + if (key_size > 0) { + u8 key_block[128] = {0}; + COPY(key_block, key, key_size); + // same as calling crypto_blake2b_update(ctx, key_block , 128) + load64_le_buf(ctx->input, key_block, 16); + ctx->input_idx = 128; + WIPE_BUFFER(key_block); + } +} + +void crypto_blake2b_init(crypto_blake2b_ctx *ctx, size_t hash_size) +{ + crypto_blake2b_keyed_init(ctx, hash_size, 0, 0); +} + +void crypto_blake2b_update(crypto_blake2b_ctx *ctx, + const u8 *message, size_t message_size) +{ + // Avoid undefined NULL pointer increments with empty messages + if (message_size == 0) { + return; + } + + // Align with word boundaries + if ((ctx->input_idx & 7) != 0) { + size_t nb_bytes = MIN(gap(ctx->input_idx, 8), message_size); + size_t word = ctx->input_idx >> 3; + size_t byte = ctx->input_idx & 7; + FOR (i, 0, nb_bytes) { + ctx->input[word] |= (u64)message[i] << ((byte + i) << 3); + } + ctx->input_idx += nb_bytes; + message += nb_bytes; + message_size -= nb_bytes; + } + + // Align with block boundaries (faster than byte by byte) + if ((ctx->input_idx & 127) != 0) { + size_t nb_words = MIN(gap(ctx->input_idx, 128), message_size) >> 3; + load64_le_buf(ctx->input + (ctx->input_idx >> 3), message, nb_words); + ctx->input_idx += nb_words << 3; + message += nb_words << 3; + message_size -= nb_words << 3; + } + + // Process block by block + size_t nb_blocks = message_size >> 7; + FOR (i, 0, nb_blocks) { + if (ctx->input_idx == 128) { + blake2b_compress(ctx, 0); + } + load64_le_buf(ctx->input, message, 16); + message += 128; + ctx->input_idx = 128; + } + message_size &= 127; + + if (message_size != 0) { + // Compress block & flush input buffer as needed + if (ctx->input_idx == 128) { + blake2b_compress(ctx, 0); + ctx->input_idx = 0; + } + if (ctx->input_idx == 0) { + ZERO(ctx->input, 16); + } + // Fill remaining words (faster than byte by byte) + size_t nb_words = message_size >> 3; + load64_le_buf(ctx->input, message, nb_words); + ctx->input_idx += nb_words << 3; + message += nb_words << 3; + message_size -= nb_words << 3; + + // Fill remaining bytes + FOR (i, 0, message_size) { + size_t word = ctx->input_idx >> 3; + size_t byte = ctx->input_idx & 7; + ctx->input[word] |= (u64)message[i] << (byte << 3); + ctx->input_idx++; + } + } +} + +void crypto_blake2b_final(crypto_blake2b_ctx *ctx, u8 *hash) +{ + blake2b_compress(ctx, 1); // compress the last block + size_t hash_size = MIN(ctx->hash_size, 64); + size_t nb_words = hash_size >> 3; + store64_le_buf(hash, ctx->hash, nb_words); + FOR (i, nb_words << 3, hash_size) { + hash[i] = (ctx->hash[i >> 3] >> (8 * (i & 7))) & 0xff; + } + WIPE_CTX(ctx); +} + +void crypto_blake2b_keyed(u8 *hash, size_t hash_size, + const u8 *key, size_t key_size, + const u8 *message, size_t message_size) +{ + crypto_blake2b_ctx ctx; + crypto_blake2b_keyed_init(&ctx, hash_size, key, key_size); + crypto_blake2b_update (&ctx, message, message_size); + crypto_blake2b_final (&ctx, hash); +} + +void crypto_blake2b(u8 *hash, size_t hash_size, const u8 *msg, size_t msg_size) +{ + crypto_blake2b_keyed(hash, hash_size, 0, 0, msg, msg_size); +} + +////////////// +/// Argon2 /// +////////////// +// references to R, Z, Q etc. come from the spec + +// Argon2 operates on 1024 byte blocks. +typedef struct { u64 a[128]; } blk; + +// updates a BLAKE2 hash with a 32 bit word, little endian. +static void blake_update_32(crypto_blake2b_ctx *ctx, u32 input) +{ + u8 buf[4]; + store32_le(buf, input); + crypto_blake2b_update(ctx, buf, 4); + WIPE_BUFFER(buf); +} + +static void blake_update_32_buf(crypto_blake2b_ctx *ctx, + const u8 *buf, u32 size) +{ + blake_update_32(ctx, size); + crypto_blake2b_update(ctx, buf, size); +} + + +static void copy_block(blk *o,const blk*in){FOR(i, 0, 128) o->a[i] = in->a[i];} +static void xor_block(blk *o,const blk*in){FOR(i, 0, 128) o->a[i] ^= in->a[i];} + +// Hash with a virtually unlimited digest size. +// Doesn't extract more entropy than the base hash function. +// Mainly used for filling a whole kilobyte block with pseudo-random bytes. +// (One could use a stream cipher with a seed hash as the key, but +// this would introduce another dependency —and point of failure.) +static void extended_hash(u8 *digest, u32 digest_size, + const u8 *input , u32 input_size) +{ + crypto_blake2b_ctx ctx; + crypto_blake2b_init (&ctx, MIN(digest_size, 64)); + blake_update_32 (&ctx, digest_size); + crypto_blake2b_update(&ctx, input, input_size); + crypto_blake2b_final (&ctx, digest); + + if (digest_size > 64) { + // the conversion to u64 avoids integer overflow on + // ludicrously big hash sizes. + u32 r = (u32)(((u64)digest_size + 31) >> 5) - 2; + u32 i = 1; + u32 in = 0; + u32 out = 32; + while (i < r) { + // Input and output overlap. This is intentional + crypto_blake2b(digest + out, 64, digest + in, 64); + i += 1; + in += 32; + out += 32; + } + crypto_blake2b(digest + out, digest_size - (32 * r), digest + in , 64); + } +} + +#define LSB(x) ((u64)(u32)x) +#define G(a, b, c, d) \ + a += b + ((LSB(a) * LSB(b)) << 1); d ^= a; d = rotr64(d, 32); \ + c += d + ((LSB(c) * LSB(d)) << 1); b ^= c; b = rotr64(b, 24); \ + a += b + ((LSB(a) * LSB(b)) << 1); d ^= a; d = rotr64(d, 16); \ + c += d + ((LSB(c) * LSB(d)) << 1); b ^= c; b = rotr64(b, 63) +#define ROUND(v0, v1, v2, v3, v4, v5, v6, v7, \ + v8, v9, v10, v11, v12, v13, v14, v15) \ + G(v0, v4, v8, v12); G(v1, v5, v9, v13); \ + G(v2, v6, v10, v14); G(v3, v7, v11, v15); \ + G(v0, v5, v10, v15); G(v1, v6, v11, v12); \ + G(v2, v7, v8, v13); G(v3, v4, v9, v14) + +// Core of the compression function G. Computes Z from R in place. +static void g_rounds(blk *b) +{ + // column rounds (work_block = Q) + for (int i = 0; i < 128; i += 16) { + ROUND(b->a[i ], b->a[i+ 1], b->a[i+ 2], b->a[i+ 3], + b->a[i+ 4], b->a[i+ 5], b->a[i+ 6], b->a[i+ 7], + b->a[i+ 8], b->a[i+ 9], b->a[i+10], b->a[i+11], + b->a[i+12], b->a[i+13], b->a[i+14], b->a[i+15]); + } + // row rounds (b = Z) + for (int i = 0; i < 16; i += 2) { + ROUND(b->a[i ], b->a[i+ 1], b->a[i+ 16], b->a[i+ 17], + b->a[i+32], b->a[i+33], b->a[i+ 48], b->a[i+ 49], + b->a[i+64], b->a[i+65], b->a[i+ 80], b->a[i+ 81], + b->a[i+96], b->a[i+97], b->a[i+112], b->a[i+113]); + } +} + +const crypto_argon2_extras crypto_argon2_no_extras = { 0, 0, 0, 0 }; + +void crypto_argon2(u8 *hash, u32 hash_size, void *work_area, + crypto_argon2_config config, + crypto_argon2_inputs inputs, + crypto_argon2_extras extras) +{ + const u32 segment_size = config.nb_blocks / config.nb_lanes / 4; + const u32 lane_size = segment_size * 4; + const u32 nb_blocks = lane_size * config.nb_lanes; // rounding down + + // work area seen as blocks (must be suitably aligned) + blk *blocks = (blk*)work_area; + { + u8 initial_hash[72]; // 64 bytes plus 2 words for future hashes + crypto_blake2b_ctx ctx; + crypto_blake2b_init (&ctx, 64); + blake_update_32 (&ctx, config.nb_lanes ); // p: number of "threads" + blake_update_32 (&ctx, hash_size); + blake_update_32 (&ctx, config.nb_blocks); + blake_update_32 (&ctx, config.nb_passes); + blake_update_32 (&ctx, 0x13); // v: version number + blake_update_32 (&ctx, config.algorithm); // y: Argon2i, Argon2d... + blake_update_32_buf (&ctx, inputs.pass, inputs.pass_size); + blake_update_32_buf (&ctx, inputs.salt, inputs.salt_size); + blake_update_32_buf (&ctx, extras.key, extras.key_size); + blake_update_32_buf (&ctx, extras.ad, extras.ad_size); + crypto_blake2b_final(&ctx, initial_hash); // fill 64 first bytes only + + // fill first 2 blocks of each lane + u8 hash_area[1024]; + FOR_T(u32, l, 0, config.nb_lanes) { + FOR_T(u32, i, 0, 2) { + store32_le(initial_hash + 64, i); // first additional word + store32_le(initial_hash + 68, l); // second additional word + extended_hash(hash_area, 1024, initial_hash, 72); + load64_le_buf(blocks[l * lane_size + i].a, hash_area, 128); + } + } + + WIPE_BUFFER(initial_hash); + WIPE_BUFFER(hash_area); + } + + // Argon2i and Argon2id start with constant time indexing + int constant_time = config.algorithm != CRYPTO_ARGON2_D; + + // Fill (and re-fill) the rest of the blocks + // + // Note: even though each segment within the same slice can be + // computed in parallel, (one thread per lane), we are computing + // them sequentially, because Monocypher doesn't support threads. + // + // Yet optimal performance (and therefore security) requires one + // thread per lane. The only reason Monocypher supports multiple + // lanes is compatibility. + blk tmp; + FOR_T(u32, pass, 0, config.nb_passes) { + FOR_T(u32, slice, 0, 4) { + // On the first slice of the first pass, + // blocks 0 and 1 are already filled, hence pass_offset. + u32 pass_offset = pass == 0 && slice == 0 ? 2 : 0; + u32 slice_offset = slice * segment_size; + + // Argon2id switches back to non-constant time indexing + // after the first two slices of the first pass + if (slice == 2 && config.algorithm == CRYPTO_ARGON2_ID) { + constant_time = 0; + } + + // Each iteration of the following loop may be performed in + // a separate thread. All segments must be fully completed + // before we start filling the next slice. + FOR_T(u32, segment, 0, config.nb_lanes) { + blk index_block; + u32 index_ctr = 1; + FOR_T (u32, block, pass_offset, segment_size) { + // Current and previous blocks + u32 lane_offset = segment * lane_size; + blk *segment_start = blocks + lane_offset + slice_offset; + blk *current = segment_start + block; + blk *previous = + block == 0 && slice_offset == 0 + ? segment_start + lane_size - 1 + : segment_start + block - 1; + + u64 index_seed; + if (constant_time) { + if (block == pass_offset || (block % 128) == 0) { + // Fill or refresh deterministic indices block + + // seed the beginning of the block... + ZERO(index_block.a, 128); + index_block.a[0] = pass; + index_block.a[1] = segment; + index_block.a[2] = slice; + index_block.a[3] = nb_blocks; + index_block.a[4] = config.nb_passes; + index_block.a[5] = config.algorithm; + index_block.a[6] = index_ctr; + index_ctr++; + + // ... then shuffle it + copy_block(&tmp, &index_block); + g_rounds (&index_block); + xor_block (&index_block, &tmp); + copy_block(&tmp, &index_block); + g_rounds (&index_block); + xor_block (&index_block, &tmp); + } + index_seed = index_block.a[block % 128]; + } else { + index_seed = previous->a[0]; + } + + // Establish the reference set. *Approximately* comprises: + // - The last 3 slices (if they exist yet) + // - The already constructed blocks in the current segment + u32 next_slice = ((slice + 1) % 4) * segment_size; + u32 window_start = pass == 0 ? 0 : next_slice; + u32 nb_segments = pass == 0 ? slice : 3; + u32 lane = + pass == 0 && slice == 0 + ? segment + : (u32)(index_seed >> 32) % config.nb_lanes; + u32 window_size = + nb_segments * segment_size + + (lane == segment ? block-1 : + block == 0 ? (u32)-1 : 0); + + // Find reference block + u64 j1 = index_seed & 0xffffffff; // block selector + u64 x = (j1 * j1) >> 32; + u64 y = (window_size * x) >> 32; + u64 z = (window_size - 1) - y; + u32 ref = (u32)((window_start + z) % lane_size); + u32 index = lane * lane_size + ref; + blk *reference = blocks + index; + + // Shuffle the previous & reference block + // into the current block + copy_block(&tmp, previous); + xor_block (&tmp, reference); + if (pass == 0) { copy_block(current, &tmp); } + else { xor_block (current, &tmp); } + g_rounds (&tmp); + xor_block (current, &tmp); + } + } + } + } + + // Wipe temporary block + volatile u64* p = tmp.a; + ZERO(p, 128); + + // XOR last blocks of each lane + blk *last_block = blocks + lane_size - 1; + FOR_T (u32, lane, 1, config.nb_lanes) { + blk *next_block = last_block + lane_size; + xor_block(next_block, last_block); + last_block = next_block; + } + + // Serialize last block + u8 final_block[1024]; + store64_le_buf(final_block, last_block->a, 128); + + // Wipe work area + p = (u64*)work_area; + ZERO(p, 128 * nb_blocks); + + // Hash the very last block with H' into the output hash + extended_hash(hash, hash_size, final_block, 1024); + WIPE_BUFFER(final_block); +} + +//////////////////////////////////// +/// Arithmetic modulo 2^255 - 19 /// +//////////////////////////////////// +// Originally taken from SUPERCOP's ref10 implementation. +// A bit bigger than TweetNaCl, over 4 times faster. + +// field element +typedef i32 fe[10]; + +// field constants +// +// fe_one : 1 +// sqrtm1 : sqrt(-1) +// d : -121665 / 121666 +// D2 : 2 * -121665 / 121666 +// lop_x, lop_y: low order point in Edwards coordinates +// ufactor : -sqrt(-1) * 2 +// A2 : 486662^2 (A squared) +static const fe fe_one = {1}; +static const fe sqrtm1 = { + -32595792, -7943725, 9377950, 3500415, 12389472, + -272473, -25146209, -2005654, 326686, 11406482, +}; +static const fe d = { + -10913610, 13857413, -15372611, 6949391, 114729, + -8787816, -6275908, -3247719, -18696448, -12055116, +}; +static const fe D2 = { + -21827239, -5839606, -30745221, 13898782, 229458, + 15978800, -12551817, -6495438, 29715968, 9444199, +}; +static const fe lop_x = { + 21352778, 5345713, 4660180, -8347857, 24143090, + 14568123, 30185756, -12247770, -33528939, 8345319, +}; +static const fe lop_y = { + -6952922, -1265500, 6862341, -7057498, -4037696, + -5447722, 31680899, -15325402, -19365852, 1569102, +}; +static const fe ufactor = { + -1917299, 15887451, -18755900, -7000830, -24778944, + 544946, -16816446, 4011309, -653372, 10741468, +}; +static const fe A2 = { + 12721188, 3529, 0, 0, 0, 0, 0, 0, 0, 0, +}; + +static void fe_0(fe h) { ZERO(h , 10); } +static void fe_1(fe h) { h[0] = 1; ZERO(h+1, 9); } + +static void fe_copy(fe h,const fe f ){FOR(i,0,10) h[i] = f[i]; } +static void fe_neg (fe h,const fe f ){FOR(i,0,10) h[i] = -f[i]; } +static void fe_add (fe h,const fe f,const fe g){FOR(i,0,10) h[i] = f[i] + g[i];} +static void fe_sub (fe h,const fe f,const fe g){FOR(i,0,10) h[i] = f[i] - g[i];} + +// Some compilers, when inlining fe_cswap() or fe_ccopy(), may introduce +// a timing leak. It happens when it notices `b` has only 2 possible +// values, and either replace the arithmetic by a secret dependent +// branch, or (as has been observed), swap pointers instead of values, +// which intruduces a secret dependent index. +// +// We apply two mitigations here: +// - Add `volatile` in the mask declaration. +// - Unroll the copy loop (costs couple hundred bytes of binary code). +// +// As of June 2026, those mitigation work when applied separately or +// together. Applying them both is currently overkill, but may help +// delay the day compilers grow clever enough to defeat it. (The true +// fix is in the semantics of the language itself: C currently has no +// way to specify constant time code). +// +// Note (Loup): as of June 2026, the problem has yet to surface in +// fe_cswap(), but since this is almost the same code as fe_ccopy() I +// believe it is more prudent to apply the precaution there too. +static void fe_cswap(fe f, fe g, int b) +{ + volatile i32 mask = -b; // -1 = 0xffffffff + i32 x0 = (f[0] ^ g[0]) & mask; f[0] = f[0] ^ x0; g[0] = g[0] ^ x0; + i32 x1 = (f[1] ^ g[1]) & mask; f[1] = f[1] ^ x1; g[1] = g[1] ^ x1; + i32 x2 = (f[2] ^ g[2]) & mask; f[2] = f[2] ^ x2; g[2] = g[2] ^ x2; + i32 x3 = (f[3] ^ g[3]) & mask; f[3] = f[3] ^ x3; g[3] = g[3] ^ x3; + i32 x4 = (f[4] ^ g[4]) & mask; f[4] = f[4] ^ x4; g[4] = g[4] ^ x4; + i32 x5 = (f[5] ^ g[5]) & mask; f[5] = f[5] ^ x5; g[5] = g[5] ^ x5; + i32 x6 = (f[6] ^ g[6]) & mask; f[6] = f[6] ^ x6; g[6] = g[6] ^ x6; + i32 x7 = (f[7] ^ g[7]) & mask; f[7] = f[7] ^ x7; g[7] = g[7] ^ x7; + i32 x8 = (f[8] ^ g[8]) & mask; f[8] = f[8] ^ x8; g[8] = g[8] ^ x8; + i32 x9 = (f[9] ^ g[9]) & mask; f[9] = f[9] ^ x9; g[9] = g[9] ^ x9; +} + +static void fe_ccopy(fe f, const fe g, int b) +{ + volatile i32 mask = -b; // -1 = 0xffffffff + i32 x0 = (f[0] ^ g[0]) & mask; f[0] = f[0] ^ x0; + i32 x1 = (f[1] ^ g[1]) & mask; f[1] = f[1] ^ x1; + i32 x2 = (f[2] ^ g[2]) & mask; f[2] = f[2] ^ x2; + i32 x3 = (f[3] ^ g[3]) & mask; f[3] = f[3] ^ x3; + i32 x4 = (f[4] ^ g[4]) & mask; f[4] = f[4] ^ x4; + i32 x5 = (f[5] ^ g[5]) & mask; f[5] = f[5] ^ x5; + i32 x6 = (f[6] ^ g[6]) & mask; f[6] = f[6] ^ x6; + i32 x7 = (f[7] ^ g[7]) & mask; f[7] = f[7] ^ x7; + i32 x8 = (f[8] ^ g[8]) & mask; f[8] = f[8] ^ x8; + i32 x9 = (f[9] ^ g[9]) & mask; f[9] = f[9] ^ x9; +} + + +// Signed carry propagation +// ------------------------ +// +// Let t be a number. It can be uniquely decomposed thus: +// +// t = h*2^26 + l +// such that -2^25 <= l < 2^25 +// +// Let c = (t + 2^25) / 2^26 (rounded down) +// c = (h*2^26 + l + 2^25) / 2^26 (rounded down) +// c = h + (l + 2^25) / 2^26 (rounded down) +// c = h (exactly) +// Because 0 <= l + 2^25 < 2^26 +// +// Let u = t - c*2^26 +// u = h*2^26 + l - h*2^26 +// u = l +// Therefore, -2^25 <= u < 2^25 +// +// Additionally, if |t| < x, then |h| < x/2^26 (rounded down) +// +// Notations: +// - In C, 1<<25 means 2^25. +// - In C, x>>25 means floor(x / (2^25)). +// - All of the above applies with 25 & 24 as well as 26 & 25. +// +// +// Note on negative right shifts +// ----------------------------- +// +// In C, x >> n, where x is a negative integer, is implementation +// defined. In practice, all platforms do arithmetic shift, which is +// equivalent to division by 2^26, rounded down. Some compilers, like +// GCC, even guarantee it. +// +// If we ever stumble upon a platform that does not propagate the sign +// bit (we won't), visible failures will show at the slightest test, and +// the signed shifts can be replaced by the following: +// +// typedef struct { i64 x:39; } s25; +// typedef struct { i64 x:38; } s26; +// i64 shift25(i64 x) { s25 s; s.x = ((u64)x)>>25; return s.x; } +// i64 shift26(i64 x) { s26 s; s.x = ((u64)x)>>26; return s.x; } +// +// Current compilers cannot optimise this, causing a 30% drop in +// performance. Fairly expensive for something that never happens. +// +// +// Precondition +// ------------ +// +// |t0| < 2^63 +// |t1|..|t9| < 2^62 +// +// Algorithm +// --------- +// c = t0 + 2^25 / 2^26 -- |c| <= 2^36 +// t0 -= c * 2^26 -- |t0| <= 2^25 +// t1 += c -- |t1| <= 2^63 +// +// c = t4 + 2^25 / 2^26 -- |c| <= 2^36 +// t4 -= c * 2^26 -- |t4| <= 2^25 +// t5 += c -- |t5| <= 2^63 +// +// c = t1 + 2^24 / 2^25 -- |c| <= 2^38 +// t1 -= c * 2^25 -- |t1| <= 2^24 +// t2 += c -- |t2| <= 2^63 +// +// c = t5 + 2^24 / 2^25 -- |c| <= 2^38 +// t5 -= c * 2^25 -- |t5| <= 2^24 +// t6 += c -- |t6| <= 2^63 +// +// c = t2 + 2^25 / 2^26 -- |c| <= 2^37 +// t2 -= c * 2^26 -- |t2| <= 2^25 < 1.1 * 2^25 (final t2) +// t3 += c -- |t3| <= 2^63 +// +// c = t6 + 2^25 / 2^26 -- |c| <= 2^37 +// t6 -= c * 2^26 -- |t6| <= 2^25 < 1.1 * 2^25 (final t6) +// t7 += c -- |t7| <= 2^63 +// +// c = t3 + 2^24 / 2^25 -- |c| <= 2^38 +// t3 -= c * 2^25 -- |t3| <= 2^24 < 1.1 * 2^24 (final t3) +// t4 += c -- |t4| <= 2^25 + 2^38 < 2^39 +// +// c = t7 + 2^24 / 2^25 -- |c| <= 2^38 +// t7 -= c * 2^25 -- |t7| <= 2^24 < 1.1 * 2^24 (final t7) +// t8 += c -- |t8| <= 2^63 +// +// c = t4 + 2^25 / 2^26 -- |c| <= 2^13 +// t4 -= c * 2^26 -- |t4| <= 2^25 < 1.1 * 2^25 (final t4) +// t5 += c -- |t5| <= 2^24 + 2^13 < 1.1 * 2^24 (final t5) +// +// c = t8 + 2^25 / 2^26 -- |c| <= 2^37 +// t8 -= c * 2^26 -- |t8| <= 2^25 < 1.1 * 2^25 (final t8) +// t9 += c -- |t9| <= 2^63 +// +// c = t9 + 2^24 / 2^25 -- |c| <= 2^38 +// t9 -= c * 2^25 -- |t9| <= 2^24 < 1.1 * 2^24 (final t9) +// t0 += c * 19 -- |t0| <= 2^25 + 2^38*19 < 2^44 +// +// c = t0 + 2^25 / 2^26 -- |c| <= 2^18 +// t0 -= c * 2^26 -- |t0| <= 2^25 < 1.1 * 2^25 (final t0) +// t1 += c -- |t1| <= 2^24 + 2^18 < 1.1 * 2^24 (final t1) +// +// Postcondition +// ------------- +// |t0|, |t2|, |t4|, |t6|, |t8| < 1.1 * 2^25 +// |t1|, |t3|, |t5|, |t7|, |t9| < 1.1 * 2^24 +#define FE_CARRY \ + i64 c; \ + c = (t0 + ((i64)1<<25)) >> 26; t0 -= c * ((i64)1 << 26); t1 += c; \ + c = (t4 + ((i64)1<<25)) >> 26; t4 -= c * ((i64)1 << 26); t5 += c; \ + c = (t1 + ((i64)1<<24)) >> 25; t1 -= c * ((i64)1 << 25); t2 += c; \ + c = (t5 + ((i64)1<<24)) >> 25; t5 -= c * ((i64)1 << 25); t6 += c; \ + c = (t2 + ((i64)1<<25)) >> 26; t2 -= c * ((i64)1 << 26); t3 += c; \ + c = (t6 + ((i64)1<<25)) >> 26; t6 -= c * ((i64)1 << 26); t7 += c; \ + c = (t3 + ((i64)1<<24)) >> 25; t3 -= c * ((i64)1 << 25); t4 += c; \ + c = (t7 + ((i64)1<<24)) >> 25; t7 -= c * ((i64)1 << 25); t8 += c; \ + c = (t4 + ((i64)1<<25)) >> 26; t4 -= c * ((i64)1 << 26); t5 += c; \ + c = (t8 + ((i64)1<<25)) >> 26; t8 -= c * ((i64)1 << 26); t9 += c; \ + c = (t9 + ((i64)1<<24)) >> 25; t9 -= c * ((i64)1 << 25); t0 += c * 19; \ + c = (t0 + ((i64)1<<25)) >> 26; t0 -= c * ((i64)1 << 26); t1 += c; \ + h[0]=(i32)t0; h[1]=(i32)t1; h[2]=(i32)t2; h[3]=(i32)t3; h[4]=(i32)t4; \ + h[5]=(i32)t5; h[6]=(i32)t6; h[7]=(i32)t7; h[8]=(i32)t8; h[9]=(i32)t9 + +// Decodes a field element from a byte buffer. +// mask specifies how many bits we ignore. +// Traditionally we ignore 1. It's useful for EdDSA, +// which uses that bit to denote the sign of x. +// Elligator however uses positive representatives, +// which means ignoring 2 bits instead. +static void fe_frombytes_mask(fe h, const u8 s[32], unsigned nb_mask) +{ + u32 mask = 0xffffff >> nb_mask; + i64 t0 = load32_le(s); // t0 < 2^32 + i64 t1 = load24_le(s + 4) << 6; // t1 < 2^30 + i64 t2 = load24_le(s + 7) << 5; // t2 < 2^29 + i64 t3 = load24_le(s + 10) << 3; // t3 < 2^27 + i64 t4 = load24_le(s + 13) << 2; // t4 < 2^26 + i64 t5 = load32_le(s + 16); // t5 < 2^32 + i64 t6 = load24_le(s + 20) << 7; // t6 < 2^31 + i64 t7 = load24_le(s + 23) << 5; // t7 < 2^29 + i64 t8 = load24_le(s + 26) << 4; // t8 < 2^28 + i64 t9 = (load24_le(s + 29) & mask) << 2; // t9 < 2^25 + FE_CARRY; // Carry precondition OK +} + +static void fe_frombytes(fe h, const u8 s[32]) +{ + fe_frombytes_mask(h, s, 1); +} + + +// Precondition +// |h[0]|, |h[2]|, |h[4]|, |h[6]|, |h[8]| < 1.1 * 2^25 +// |h[1]|, |h[3]|, |h[5]|, |h[7]|, |h[9]| < 1.1 * 2^24 +// +// Therefore, |h| < 2^255-19 +// There are two possibilities: +// +// - If h is positive, all we need to do is reduce its individual +// limbs down to their tight positive range. +// - If h is negative, we also need to add 2^255-19 to it. +// Or just remove 19 and chop off any excess bit. +static void fe_tobytes(u8 s[32], const fe h) +{ + i32 t[10]; + COPY(t, h, 10); + i32 q = (19 * t[9] + (((i32) 1) << 24)) >> 25; + // |t9| < 1.1 * 2^24 + // -1.1 * 2^24 < t9 < 1.1 * 2^24 + // -21 * 2^24 < 19 * t9 < 21 * 2^24 + // -2^29 < 19 * t9 + 2^24 < 2^29 + // -2^29 / 2^25 < (19 * t9 + 2^24) / 2^25 < 2^29 / 2^25 + // -16 < (19 * t9 + 2^24) / 2^25 < 16 + FOR (i, 0, 5) { + q += t[2*i ]; q >>= 26; // q = 0 or -1 + q += t[2*i+1]; q >>= 25; // q = 0 or -1 + } + // q = 0 iff h >= 0 + // q = -1 iff h < 0 + // Adding q * 19 to h reduces h to its proper range. + q *= 19; // Shift carry back to the beginning + FOR (i, 0, 5) { + t[i*2 ] += q; q = t[i*2 ] >> 26; t[i*2 ] -= q * ((i32)1 << 26); + t[i*2+1] += q; q = t[i*2+1] >> 25; t[i*2+1] -= q * ((i32)1 << 25); + } + // h is now fully reduced, and q represents the excess bit. + + store32_le(s + 0, ((u32)t[0] >> 0) | ((u32)t[1] << 26)); + store32_le(s + 4, ((u32)t[1] >> 6) | ((u32)t[2] << 19)); + store32_le(s + 8, ((u32)t[2] >> 13) | ((u32)t[3] << 13)); + store32_le(s + 12, ((u32)t[3] >> 19) | ((u32)t[4] << 6)); + store32_le(s + 16, ((u32)t[5] >> 0) | ((u32)t[6] << 25)); + store32_le(s + 20, ((u32)t[6] >> 7) | ((u32)t[7] << 19)); + store32_le(s + 24, ((u32)t[7] >> 13) | ((u32)t[8] << 12)); + store32_le(s + 28, ((u32)t[8] >> 20) | ((u32)t[9] << 6)); + + WIPE_BUFFER(t); +} + +// Precondition +// ------------- +// |f0|, |f2|, |f4|, |f6|, |f8| < 1.65 * 2^26 +// |f1|, |f3|, |f5|, |f7|, |f9| < 1.65 * 2^25 +// +// |g0|, |g2|, |g4|, |g6|, |g8| < 1.65 * 2^26 +// |g1|, |g3|, |g5|, |g7|, |g9| < 1.65 * 2^25 +static void fe_mul_small(fe h, const fe f, i32 g) +{ + i64 t0 = f[0] * (i64) g; i64 t1 = f[1] * (i64) g; + i64 t2 = f[2] * (i64) g; i64 t3 = f[3] * (i64) g; + i64 t4 = f[4] * (i64) g; i64 t5 = f[5] * (i64) g; + i64 t6 = f[6] * (i64) g; i64 t7 = f[7] * (i64) g; + i64 t8 = f[8] * (i64) g; i64 t9 = f[9] * (i64) g; + // |t0|, |t2|, |t4|, |t6|, |t8| < 1.65 * 2^26 * 2^31 < 2^58 + // |t1|, |t3|, |t5|, |t7|, |t9| < 1.65 * 2^25 * 2^31 < 2^57 + + FE_CARRY; // Carry precondition OK +} + +// Precondition +// ------------- +// |f0|, |f2|, |f4|, |f6|, |f8| < 1.65 * 2^26 +// |f1|, |f3|, |f5|, |f7|, |f9| < 1.65 * 2^25 +// +// |g0|, |g2|, |g4|, |g6|, |g8| < 1.65 * 2^26 +// |g1|, |g3|, |g5|, |g7|, |g9| < 1.65 * 2^25 +static void fe_mul(fe h, const fe f, const fe g) +{ + // Everything is unrolled and put in temporary variables. + // We could roll the loop, but that would make curve25519 twice as slow. + i32 f0 = f[0]; i32 f1 = f[1]; i32 f2 = f[2]; i32 f3 = f[3]; i32 f4 = f[4]; + i32 f5 = f[5]; i32 f6 = f[6]; i32 f7 = f[7]; i32 f8 = f[8]; i32 f9 = f[9]; + i32 g0 = g[0]; i32 g1 = g[1]; i32 g2 = g[2]; i32 g3 = g[3]; i32 g4 = g[4]; + i32 g5 = g[5]; i32 g6 = g[6]; i32 g7 = g[7]; i32 g8 = g[8]; i32 g9 = g[9]; + i32 F1 = f1*2; i32 F3 = f3*2; i32 F5 = f5*2; i32 F7 = f7*2; i32 F9 = f9*2; + i32 G1 = g1*19; i32 G2 = g2*19; i32 G3 = g3*19; + i32 G4 = g4*19; i32 G5 = g5*19; i32 G6 = g6*19; + i32 G7 = g7*19; i32 G8 = g8*19; i32 G9 = g9*19; + // |F1|, |F3|, |F5|, |F7|, |F9| < 1.65 * 2^26 + // |G0|, |G2|, |G4|, |G6|, |G8| < 2^31 + // |G1|, |G3|, |G5|, |G7|, |G9| < 2^30 + + i64 t0 = f0*(i64)g0 + F1*(i64)G9 + f2*(i64)G8 + F3*(i64)G7 + f4*(i64)G6 + + F5*(i64)G5 + f6*(i64)G4 + F7*(i64)G3 + f8*(i64)G2 + F9*(i64)G1; + i64 t1 = f0*(i64)g1 + f1*(i64)g0 + f2*(i64)G9 + f3*(i64)G8 + f4*(i64)G7 + + f5*(i64)G6 + f6*(i64)G5 + f7*(i64)G4 + f8*(i64)G3 + f9*(i64)G2; + i64 t2 = f0*(i64)g2 + F1*(i64)g1 + f2*(i64)g0 + F3*(i64)G9 + f4*(i64)G8 + + F5*(i64)G7 + f6*(i64)G6 + F7*(i64)G5 + f8*(i64)G4 + F9*(i64)G3; + i64 t3 = f0*(i64)g3 + f1*(i64)g2 + f2*(i64)g1 + f3*(i64)g0 + f4*(i64)G9 + + f5*(i64)G8 + f6*(i64)G7 + f7*(i64)G6 + f8*(i64)G5 + f9*(i64)G4; + i64 t4 = f0*(i64)g4 + F1*(i64)g3 + f2*(i64)g2 + F3*(i64)g1 + f4*(i64)g0 + + F5*(i64)G9 + f6*(i64)G8 + F7*(i64)G7 + f8*(i64)G6 + F9*(i64)G5; + i64 t5 = f0*(i64)g5 + f1*(i64)g4 + f2*(i64)g3 + f3*(i64)g2 + f4*(i64)g1 + + f5*(i64)g0 + f6*(i64)G9 + f7*(i64)G8 + f8*(i64)G7 + f9*(i64)G6; + i64 t6 = f0*(i64)g6 + F1*(i64)g5 + f2*(i64)g4 + F3*(i64)g3 + f4*(i64)g2 + + F5*(i64)g1 + f6*(i64)g0 + F7*(i64)G9 + f8*(i64)G8 + F9*(i64)G7; + i64 t7 = f0*(i64)g7 + f1*(i64)g6 + f2*(i64)g5 + f3*(i64)g4 + f4*(i64)g3 + + f5*(i64)g2 + f6*(i64)g1 + f7*(i64)g0 + f8*(i64)G9 + f9*(i64)G8; + i64 t8 = f0*(i64)g8 + F1*(i64)g7 + f2*(i64)g6 + F3*(i64)g5 + f4*(i64)g4 + + F5*(i64)g3 + f6*(i64)g2 + F7*(i64)g1 + f8*(i64)g0 + F9*(i64)G9; + i64 t9 = f0*(i64)g9 + f1*(i64)g8 + f2*(i64)g7 + f3*(i64)g6 + f4*(i64)g5 + + f5*(i64)g4 + f6*(i64)g3 + f7*(i64)g2 + f8*(i64)g1 + f9*(i64)g0; + // t0 < 0.67 * 2^61 + // t1 < 0.41 * 2^61 + // t2 < 0.52 * 2^61 + // t3 < 0.32 * 2^61 + // t4 < 0.38 * 2^61 + // t5 < 0.22 * 2^61 + // t6 < 0.23 * 2^61 + // t7 < 0.13 * 2^61 + // t8 < 0.09 * 2^61 + // t9 < 0.03 * 2^61 + + FE_CARRY; // Everything below 2^62, Carry precondition OK +} + +// Precondition +// ------------- +// |f0|, |f2|, |f4|, |f6|, |f8| < 1.65 * 2^26 +// |f1|, |f3|, |f5|, |f7|, |f9| < 1.65 * 2^25 +// +// Note: we could use fe_mul() for this, but this is significantly faster +static void fe_sq(fe h, const fe f) +{ + i32 f0 = f[0]; i32 f1 = f[1]; i32 f2 = f[2]; i32 f3 = f[3]; i32 f4 = f[4]; + i32 f5 = f[5]; i32 f6 = f[6]; i32 f7 = f[7]; i32 f8 = f[8]; i32 f9 = f[9]; + i32 f0_2 = f0*2; i32 f1_2 = f1*2; i32 f2_2 = f2*2; i32 f3_2 = f3*2; + i32 f4_2 = f4*2; i32 f5_2 = f5*2; i32 f6_2 = f6*2; i32 f7_2 = f7*2; + i32 f5_38 = f5*38; i32 f6_19 = f6*19; i32 f7_38 = f7*38; + i32 f8_19 = f8*19; i32 f9_38 = f9*38; + // |f0_2| , |f2_2| , |f4_2| , |f6_2| , |f8_2| < 1.65 * 2^27 + // |f1_2| , |f3_2| , |f5_2| , |f7_2| , |f9_2| < 1.65 * 2^26 + // |f5_38|, |f6_19|, |f7_38|, |f8_19|, |f9_38| < 2^31 + + i64 t0 = f0 *(i64)f0 + f1_2*(i64)f9_38 + f2_2*(i64)f8_19 + + f3_2*(i64)f7_38 + f4_2*(i64)f6_19 + f5 *(i64)f5_38; + i64 t1 = f0_2*(i64)f1 + f2 *(i64)f9_38 + f3_2*(i64)f8_19 + + f4 *(i64)f7_38 + f5_2*(i64)f6_19; + i64 t2 = f0_2*(i64)f2 + f1_2*(i64)f1 + f3_2*(i64)f9_38 + + f4_2*(i64)f8_19 + f5_2*(i64)f7_38 + f6 *(i64)f6_19; + i64 t3 = f0_2*(i64)f3 + f1_2*(i64)f2 + f4 *(i64)f9_38 + + f5_2*(i64)f8_19 + f6 *(i64)f7_38; + i64 t4 = f0_2*(i64)f4 + f1_2*(i64)f3_2 + f2 *(i64)f2 + + f5_2*(i64)f9_38 + f6_2*(i64)f8_19 + f7 *(i64)f7_38; + i64 t5 = f0_2*(i64)f5 + f1_2*(i64)f4 + f2_2*(i64)f3 + + f6 *(i64)f9_38 + f7_2*(i64)f8_19; + i64 t6 = f0_2*(i64)f6 + f1_2*(i64)f5_2 + f2_2*(i64)f4 + + f3_2*(i64)f3 + f7_2*(i64)f9_38 + f8 *(i64)f8_19; + i64 t7 = f0_2*(i64)f7 + f1_2*(i64)f6 + f2_2*(i64)f5 + + f3_2*(i64)f4 + f8 *(i64)f9_38; + i64 t8 = f0_2*(i64)f8 + f1_2*(i64)f7_2 + f2_2*(i64)f6 + + f3_2*(i64)f5_2 + f4 *(i64)f4 + f9 *(i64)f9_38; + i64 t9 = f0_2*(i64)f9 + f1_2*(i64)f8 + f2_2*(i64)f7 + + f3_2*(i64)f6 + f4 *(i64)f5_2; + // t0 < 0.67 * 2^61 + // t1 < 0.41 * 2^61 + // t2 < 0.52 * 2^61 + // t3 < 0.32 * 2^61 + // t4 < 0.38 * 2^61 + // t5 < 0.22 * 2^61 + // t6 < 0.23 * 2^61 + // t7 < 0.13 * 2^61 + // t8 < 0.09 * 2^61 + // t9 < 0.03 * 2^61 + + FE_CARRY; +} + +// Parity check. Returns 0 if even, 1 if odd +static int fe_isodd(const fe f) +{ + u8 s[32]; + fe_tobytes(s, f); + u8 isodd = s[0] & 1; + WIPE_BUFFER(s); + return isodd; +} + +// Returns 1 if equal, 0 if not equal +static int fe_isequal(const fe f, const fe g) +{ + u8 fs[32]; + u8 gs[32]; + fe_tobytes(fs, f); + fe_tobytes(gs, g); + int isdifferent = crypto_verify32(fs, gs); + WIPE_BUFFER(fs); + WIPE_BUFFER(gs); + return 1 + isdifferent; +} + +// Inverse square root. +// Returns true if x is a square, false otherwise. +// After the call: +// isr = sqrt(1/x) if x is a non-zero square. +// isr = sqrt(sqrt(-1)/x) if x is not a square. +// isr = 0 if x is zero. +// We do not guarantee the sign of the square root. +// +// Notes: +// Let quartic = x^((p-1)/4) +// +// x^((p-1)/2) = chi(x) +// quartic^2 = chi(x) +// quartic = sqrt(chi(x)) +// quartic = 1 or -1 or sqrt(-1) or -sqrt(-1) +// +// Note that x is a square if quartic is 1 or -1 +// There are 4 cases to consider: +// +// if quartic = 1 (x is a square) +// then x^((p-1)/4) = 1 +// x^((p-5)/4) * x = 1 +// x^((p-5)/4) = 1/x +// x^((p-5)/8) = sqrt(1/x) or -sqrt(1/x) +// +// if quartic = -1 (x is a square) +// then x^((p-1)/4) = -1 +// x^((p-5)/4) * x = -1 +// x^((p-5)/4) = -1/x +// x^((p-5)/8) = sqrt(-1) / sqrt(x) +// x^((p-5)/8) * sqrt(-1) = sqrt(-1)^2 / sqrt(x) +// x^((p-5)/8) * sqrt(-1) = -1/sqrt(x) +// x^((p-5)/8) * sqrt(-1) = -sqrt(1/x) or sqrt(1/x) +// +// if quartic = sqrt(-1) (x is not a square) +// then x^((p-1)/4) = sqrt(-1) +// x^((p-5)/4) * x = sqrt(-1) +// x^((p-5)/4) = sqrt(-1)/x +// x^((p-5)/8) = sqrt(sqrt(-1)/x) or -sqrt(sqrt(-1)/x) +// +// Note that the product of two non-squares is always a square: +// For any non-squares a and b, chi(a) = -1 and chi(b) = -1. +// Since chi(x) = x^((p-1)/2), chi(a)*chi(b) = chi(a*b) = 1. +// Therefore a*b is a square. +// +// Since sqrt(-1) and x are both non-squares, their product is a +// square, and we can compute their square root. +// +// if quartic = -sqrt(-1) (x is not a square) +// then x^((p-1)/4) = -sqrt(-1) +// x^((p-5)/4) * x = -sqrt(-1) +// x^((p-5)/4) = -sqrt(-1)/x +// x^((p-5)/8) = sqrt(-sqrt(-1)/x) +// x^((p-5)/8) = sqrt( sqrt(-1)/x) * sqrt(-1) +// x^((p-5)/8) * sqrt(-1) = sqrt( sqrt(-1)/x) * sqrt(-1)^2 +// x^((p-5)/8) * sqrt(-1) = sqrt( sqrt(-1)/x) * -1 +// x^((p-5)/8) * sqrt(-1) = -sqrt(sqrt(-1)/x) or sqrt(sqrt(-1)/x) +static int invsqrt(fe isr, const fe x) +{ + fe t0, t1, t2; + + // t0 = x^((p-5)/8) + // Can be achieved with a simple double & add ladder, + // but it would be slower. + fe_sq(t0, x); + fe_sq(t1,t0); fe_sq(t1, t1); fe_mul(t1, x, t1); + fe_mul(t0, t0, t1); + fe_sq(t0, t0); fe_mul(t0, t1, t0); + fe_sq(t1, t0); FOR (i, 1, 5) { fe_sq(t1, t1); } fe_mul(t0, t1, t0); + fe_sq(t1, t0); FOR (i, 1, 10) { fe_sq(t1, t1); } fe_mul(t1, t1, t0); + fe_sq(t2, t1); FOR (i, 1, 20) { fe_sq(t2, t2); } fe_mul(t1, t2, t1); + fe_sq(t1, t1); FOR (i, 1, 10) { fe_sq(t1, t1); } fe_mul(t0, t1, t0); + fe_sq(t1, t0); FOR (i, 1, 50) { fe_sq(t1, t1); } fe_mul(t1, t1, t0); + fe_sq(t2, t1); FOR (i, 1, 100) { fe_sq(t2, t2); } fe_mul(t1, t2, t1); + fe_sq(t1, t1); FOR (i, 1, 50) { fe_sq(t1, t1); } fe_mul(t0, t1, t0); + fe_sq(t0, t0); FOR (i, 1, 2) { fe_sq(t0, t0); } fe_mul(t0, t0, x); + + // quartic = x^((p-1)/4) + i32 *quartic = t1; + fe_sq (quartic, t0); + fe_mul(quartic, quartic, x); + + i32 *check = t2; + fe_0 (check); int z0 = fe_isequal(x , check); + fe_1 (check); int p1 = fe_isequal(quartic, check); + fe_neg(check, check ); int m1 = fe_isequal(quartic, check); + fe_neg(check, sqrtm1); int ms = fe_isequal(quartic, check); + + // if quartic == -1 or sqrt(-1) + // then isr = x^((p-1)/4) * sqrt(-1) + // else isr = x^((p-1)/4) + fe_mul(isr, t0, sqrtm1); + fe_ccopy(isr, t0, 1 - (m1 | ms)); + + WIPE_BUFFER(t0); + WIPE_BUFFER(t1); + WIPE_BUFFER(t2); + return p1 | m1 | z0; +} + +// Inverse in terms of inverse square root. +// Requires two additional squarings to get rid of the sign. +// +// 1/x = x * (+invsqrt(x^2))^2 +// = x * (-invsqrt(x^2))^2 +// +// A fully optimised exponentiation by p-1 would save 6 field +// multiplications, but it would require more code. +static void fe_invert(fe out, const fe x) +{ + fe tmp; + fe_sq(tmp, x); + invsqrt(tmp, tmp); + fe_sq(tmp, tmp); + fe_mul(out, tmp, x); + WIPE_BUFFER(tmp); +} + +// trim a scalar for scalar multiplication +void crypto_eddsa_trim_scalar(u8 out[32], const u8 in[32]) +{ + COPY(out, in, 32); + out[ 0] &= 248; + out[31] &= 127; + out[31] |= 64; +} + +// get bit from scalar at position i +static int scalar_bit(const u8 s[32], int i) +{ + if (i < 0) { return 0; } // handle -1 for sliding windows + return (s[i>>3] >> (i&7)) & 1; +} + +/////////////// +/// X-25519 /// Taken from SUPERCOP's ref10 implementation. +/////////////// +static void scalarmult(u8 q[32], const u8 scalar[32], const u8 p[32], + int nb_bits) +{ + // computes the scalar product + fe x1; + fe_frombytes(x1, p); + + // computes the actual scalar product (the result is in x2 and z2) + fe x2, z2, x3, z3, t0, t1; + // Montgomery ladder + // In projective coordinates, to avoid divisions: x = X / Z + // We don't care about the y coordinate, it's only 1 bit of information + fe_1(x2); fe_0(z2); // "zero" point + fe_copy(x3, x1); fe_1(z3); // "one" point + int swap = 0; + for (int pos = nb_bits-1; pos >= 0; --pos) { + // constant time conditional swap before ladder step + int b = scalar_bit(scalar, pos); + swap ^= b; // xor trick avoids swapping at the end of the loop + fe_cswap(x2, x3, swap); + fe_cswap(z2, z3, swap); + swap = b; // anticipates one last swap after the loop + + // Montgomery ladder step: replaces (P2, P3) by (P2*2, P2+P3) + // with differential addition + fe_sub(t0, x3, z3); + fe_sub(t1, x2, z2); + fe_add(x2, x2, z2); + fe_add(z2, x3, z3); + fe_mul(z3, t0, x2); + fe_mul(z2, z2, t1); + fe_sq (t0, t1 ); + fe_sq (t1, x2 ); + fe_add(x3, z3, z2); + fe_sub(z2, z3, z2); + fe_mul(x2, t1, t0); + fe_sub(t1, t1, t0); + fe_sq (z2, z2 ); + fe_mul_small(z3, t1, 121666); + fe_sq (x3, x3 ); + fe_add(t0, t0, z3); + fe_mul(z3, x1, z2); + fe_mul(z2, t1, t0); + } + // last swap is necessary to compensate for the xor trick + // Note: after this swap, P3 == P2 + P1. + fe_cswap(x2, x3, swap); + fe_cswap(z2, z3, swap); + + // normalises the coordinates: x == X / Z + fe_invert(z2, z2); + fe_mul(x2, x2, z2); + fe_tobytes(q, x2); + + WIPE_BUFFER(x1); + WIPE_BUFFER(x2); WIPE_BUFFER(z2); WIPE_BUFFER(t0); + WIPE_BUFFER(x3); WIPE_BUFFER(z3); WIPE_BUFFER(t1); +} + +void crypto_x25519(u8 raw_shared_secret[32], + const u8 your_secret_key [32], + const u8 their_public_key [32]) +{ + // restrict the possible scalar values + u8 e[32]; + crypto_eddsa_trim_scalar(e, your_secret_key); + scalarmult(raw_shared_secret, e, their_public_key, 255); + WIPE_BUFFER(e); +} + +void crypto_x25519_public_key(u8 public_key[32], + const u8 secret_key[32]) +{ + static const u8 base_point[32] = {9}; + crypto_x25519(public_key, secret_key, base_point); +} + +/////////////////////////// +/// Arithmetic modulo L /// +/////////////////////////// +static const u32 L[8] = { + 0x5cf5d3ed, 0x5812631a, 0xa2f79cd6, 0x14def9de, + 0x00000000, 0x00000000, 0x00000000, 0x10000000, +}; + +// p = a*b + p +static void multiply(u32 p[16], const u32 a[8], const u32 b[8]) +{ + FOR (i, 0, 8) { + u64 carry = 0; + FOR (j, 0, 8) { + carry += p[i+j] + (u64)a[i] * b[j]; + p[i+j] = (u32)carry; + carry >>= 32; + } + p[i+8] = (u32)carry; + } +} + +static int is_above_l(const u32 x[8]) +{ + // We work with L directly, in a 2's complement encoding + // (-L == ~L + 1) + u64 carry = 1; + FOR (i, 0, 8) { + carry += (u64)x[i] + (~L[i] & 0xffffffff); + carry >>= 32; + } + return (int)carry; // carry is either 0 or 1 +} + +// Final reduction modulo L, by conditionally removing L. +// if x < l , then r = x +// if l <= x 2*l, then r = x-l +// otherwise the result will be wrong +static void remove_l(u32 r[8], const u32 x[8]) +{ + u64 carry = (u64)is_above_l(x); + u32 mask = ~(u32)carry + 1; // carry == 0 or 1 + FOR (i, 0, 8) { + carry += (u64)x[i] + (~L[i] & mask); + r[i] = (u32)carry; + carry >>= 32; + } +} + +// Full reduction modulo L (Barrett reduction) +static void mod_l(u8 reduced[32], const u32 x[16]) +{ + static const u32 r[9] = { + 0x0a2c131b,0xed9ce5a3,0x086329a7,0x2106215d, + 0xffffffeb,0xffffffff,0xffffffff,0xffffffff,0xf, + }; + // xr = x * r + u32 xr[25] = {0}; + FOR (i, 0, 9) { + u64 carry = 0; + FOR (j, 0, 16) { + carry += xr[i+j] + (u64)r[i] * x[j]; + xr[i+j] = (u32)carry; + carry >>= 32; + } + xr[i+16] = (u32)carry; + } + // xr = floor(xr / 2^512) * L + // Since the result is guaranteed to be below 2*L, + // it is enough to only compute the first 256 bits. + // The division is performed by saying xr[i+16]. (16 * 32 = 512) + ZERO(xr, 8); + FOR (i, 0, 8) { + u64 carry = 0; + FOR (j, 0, 8-i) { + carry += xr[i+j] + (u64)xr[i+16] * L[j]; + xr[i+j] = (u32)carry; + carry >>= 32; + } + } + // xr = x - xr + u64 carry = 1; + FOR (i, 0, 8) { + carry += (u64)x[i] + (~xr[i] & 0xffffffff); + xr[i] = (u32)carry; + carry >>= 32; + } + // Final reduction modulo L (conditional subtraction) + remove_l(xr, xr); + store32_le_buf(reduced, xr, 8); + + WIPE_BUFFER(xr); +} + +void crypto_eddsa_reduce(u8 reduced[32], const u8 expanded[64]) +{ + u32 x[16]; + load32_le_buf(x, expanded, 16); + mod_l(reduced, x); + WIPE_BUFFER(x); +} + +// r = (a * b) + c +void crypto_eddsa_mul_add(u8 r[32], + const u8 a[32], const u8 b[32], const u8 c[32]) +{ + u32 A[8]; load32_le_buf(A, a, 8); + u32 B[8]; load32_le_buf(B, b, 8); + u32 p[16]; load32_le_buf(p, c, 8); ZERO(p + 8, 8); + multiply(p, A, B); + mod_l(r, p); + WIPE_BUFFER(p); + WIPE_BUFFER(A); + WIPE_BUFFER(B); +} + +/////////////// +/// Ed25519 /// +/////////////// + +// Point (group element, ge) in a twisted Edwards curve, +// in extended projective coordinates. +// ge : x = X/Z, y = Y/Z, T = XY/Z +// ge_cached : Yp = X+Y, Ym = X-Y, T2 = T*D2 +// ge_precomp: Z = 1 +typedef struct { fe X; fe Y; fe Z; fe T; } ge; +typedef struct { fe Yp; fe Ym; fe Z; fe T2; } ge_cached; +typedef struct { fe Yp; fe Ym; fe T2; } ge_precomp; + +static void ge_zero(ge *p) +{ + fe_0(p->X); + fe_1(p->Y); + fe_1(p->Z); + fe_0(p->T); +} + +static void ge_tobytes(u8 s[32], const ge *h) +{ + fe recip, x, y; + fe_invert(recip, h->Z); + fe_mul(x, h->X, recip); + fe_mul(y, h->Y, recip); + fe_tobytes(s, y); + s[31] ^= (u8)fe_isodd(x) << 7; + + WIPE_BUFFER(recip); + WIPE_BUFFER(x); + WIPE_BUFFER(y); +} + +// h = -s, where s is a point encoded in 32 bytes +// +// Variable time! Inputs must not be secret! +// => Use only to *check* signatures. +// +// From the specifications: +// The encoding of s contains y and the sign of x +// x = sqrt((y^2 - 1) / (d*y^2 + 1)) +// In extended coordinates: +// X = x, Y = y, Z = 1, T = x*y +// +// Note that num * den is a square iff num / den is a square +// If num * den is not a square, the point was not on the curve. +// From the above: +// Let num = y^2 - 1 +// Let den = d*y^2 + 1 +// x = sqrt((y^2 - 1) / (d*y^2 + 1)) +// x = sqrt(num / den) +// x = sqrt(num^2 / (num * den)) +// x = num * sqrt(1 / (num * den)) +// +// Therefore, we can just compute: +// num = y^2 - 1 +// den = d*y^2 + 1 +// isr = invsqrt(num * den) // abort if not square +// x = num * isr +// Finally, negate x if its sign is not as specified. +static int ge_frombytes_neg_vartime(ge *h, const u8 s[32]) +{ + fe_frombytes(h->Y, s); + fe_1(h->Z); + fe_sq (h->T, h->Y); // t = y^2 + fe_mul(h->X, h->T, d ); // x = d*y^2 + fe_sub(h->T, h->T, h->Z); // t = y^2 - 1 + fe_add(h->X, h->X, h->Z); // x = d*y^2 + 1 + fe_mul(h->X, h->T, h->X); // x = (y^2 - 1) * (d*y^2 + 1) + int is_square = invsqrt(h->X, h->X); + if (!is_square) { + return -1; // Not on the curve, abort + } + fe_mul(h->X, h->T, h->X); // x = sqrt((y^2 - 1) / (d*y^2 + 1)) + if (fe_isodd(h->X) == (s[31] >> 7)) { + fe_neg(h->X, h->X); + } + fe_mul(h->T, h->X, h->Y); + return 0; +} + +static void ge_cache(ge_cached *c, const ge *p) +{ + fe_add (c->Yp, p->Y, p->X); + fe_sub (c->Ym, p->Y, p->X); + fe_copy(c->Z , p->Z ); + fe_mul (c->T2, p->T, D2 ); +} + +// Internal buffers are not wiped! Inputs must not be secret! +// => Use only to *check* signatures. +static void ge_add(ge *s, const ge *p, const ge_cached *q) +{ + fe a, b; + fe_add(a , p->Y, p->X ); + fe_sub(b , p->Y, p->X ); + fe_mul(a , a , q->Yp); + fe_mul(b , b , q->Ym); + fe_add(s->Y, a , b ); + fe_sub(s->X, a , b ); + + fe_add(s->Z, p->Z, p->Z ); + fe_mul(s->Z, s->Z, q->Z ); + fe_mul(s->T, p->T, q->T2); + fe_add(a , s->Z, s->T ); + fe_sub(b , s->Z, s->T ); + + fe_mul(s->T, s->X, s->Y); + fe_mul(s->X, s->X, b ); + fe_mul(s->Y, s->Y, a ); + fe_mul(s->Z, a , b ); +} + +// Internal buffers are not wiped! Inputs must not be secret! +// => Use only to *check* signatures. +static void ge_sub(ge *s, const ge *p, const ge_cached *q) +{ + ge_cached neg; + fe_copy(neg.Ym, q->Yp); + fe_copy(neg.Yp, q->Ym); + fe_copy(neg.Z , q->Z ); + fe_neg (neg.T2, q->T2); + ge_add(s, p, &neg); +} + +static void ge_madd(ge *s, const ge *p, const ge_precomp *q, fe a, fe b) +{ + fe_add(a , p->Y, p->X ); + fe_sub(b , p->Y, p->X ); + fe_mul(a , a , q->Yp); + fe_mul(b , b , q->Ym); + fe_add(s->Y, a , b ); + fe_sub(s->X, a , b ); + + fe_add(s->Z, p->Z, p->Z ); + fe_mul(s->T, p->T, q->T2); + fe_add(a , s->Z, s->T ); + fe_sub(b , s->Z, s->T ); + + fe_mul(s->T, s->X, s->Y); + fe_mul(s->X, s->X, b ); + fe_mul(s->Y, s->Y, a ); + fe_mul(s->Z, a , b ); +} + +// Internal buffers are not wiped! Inputs must not be secret! +// => Use only to *check* signatures. +static void ge_msub(ge *s, const ge *p, const ge_precomp *q, fe a, fe b) +{ + ge_precomp neg; + fe_copy(neg.Ym, q->Yp); + fe_copy(neg.Yp, q->Ym); + fe_neg (neg.T2, q->T2); + ge_madd(s, p, &neg, a, b); +} + +static void ge_double(ge *s, const ge *p, ge *q) +{ + fe_sq (q->X, p->X); + fe_sq (q->Y, p->Y); + fe_sq (q->Z, p->Z); // qZ = pZ^2 + fe_mul_small(q->Z, q->Z, 2); // qZ = pZ^2 * 2 + fe_add(q->T, p->X, p->Y); + fe_sq (s->T, q->T); + fe_add(q->T, q->Y, q->X); + fe_sub(q->Y, q->Y, q->X); + fe_sub(q->X, s->T, q->T); + fe_sub(q->Z, q->Z, q->Y); + + fe_mul(s->X, q->X , q->Z); + fe_mul(s->Y, q->T , q->Y); + fe_mul(s->Z, q->Y , q->Z); + fe_mul(s->T, q->X , q->T); +} + +// 5-bit signed window in cached format (Niels coordinates, Z=1) +static const ge_precomp b_window[8] = { + {{25967493,-14356035,29566456,3660896,-12694345, + 4014787,27544626,-11754271,-6079156,2047605,}, + {-12545711,934262,-2722910,3049990,-727428, + 9406986,12720692,5043384,19500929,-15469378,}, + {-8738181,4489570,9688441,-14785194,10184609, + -12363380,29287919,11864899,-24514362,-4438546,},}, + {{15636291,-9688557,24204773,-7912398,616977, + -16685262,27787600,-14772189,28944400,-1550024,}, + {16568933,4717097,-11556148,-1102322,15682896, + -11807043,16354577,-11775962,7689662,11199574,}, + {30464156,-5976125,-11779434,-15670865,23220365, + 15915852,7512774,10017326,-17749093,-9920357,},}, + {{10861363,11473154,27284546,1981175,-30064349, + 12577861,32867885,14515107,-15438304,10819380,}, + {4708026,6336745,20377586,9066809,-11272109, + 6594696,-25653668,12483688,-12668491,5581306,}, + {19563160,16186464,-29386857,4097519,10237984, + -4348115,28542350,13850243,-23678021,-15815942,},}, + {{5153746,9909285,1723747,-2777874,30523605, + 5516873,19480852,5230134,-23952439,-15175766,}, + {-30269007,-3463509,7665486,10083793,28475525, + 1649722,20654025,16520125,30598449,7715701,}, + {28881845,14381568,9657904,3680757,-20181635, + 7843316,-31400660,1370708,29794553,-1409300,},}, + {{-22518993,-6692182,14201702,-8745502,-23510406, + 8844726,18474211,-1361450,-13062696,13821877,}, + {-6455177,-7839871,3374702,-4740862,-27098617, + -10571707,31655028,-7212327,18853322,-14220951,}, + {4566830,-12963868,-28974889,-12240689,-7602672, + -2830569,-8514358,-10431137,2207753,-3209784,},}, + {{-25154831,-4185821,29681144,7868801,-6854661, + -9423865,-12437364,-663000,-31111463,-16132436,}, + {25576264,-2703214,7349804,-11814844,16472782, + 9300885,3844789,15725684,171356,6466918,}, + {23103977,13316479,9739013,-16149481,817875, + -15038942,8965339,-14088058,-30714912,16193877,},}, + {{-33521811,3180713,-2394130,14003687,-16903474, + -16270840,17238398,4729455,-18074513,9256800,}, + {-25182317,-4174131,32336398,5036987,-21236817, + 11360617,22616405,9761698,-19827198,630305,}, + {-13720693,2639453,-24237460,-7406481,9494427, + -5774029,-6554551,-15960994,-2449256,-14291300,},}, + {{-3151181,-5046075,9282714,6866145,-31907062, + -863023,-18940575,15033784,25105118,-7894876,}, + {-24326370,15950226,-31801215,-14592823,-11662737, + -5090925,1573892,-2625887,2198790,-15804619,}, + {-3099351,10324967,-2241613,7453183,-5446979, + -2735503,-13812022,-16236442,-32461234,-12290683,},}, +}; + +// Incremental sliding windows (left to right) +// Based on Roberto Maria Avanzi[2005] +typedef struct { + i16 next_index; // position of the next signed digit + i8 next_digit; // next signed digit (odd number below 2^window_width) + u8 next_check; // point at which we must check for a new window +} slide_ctx; + +static void slide_init(slide_ctx *ctx, const u8 scalar[32]) +{ + // scalar is guaranteed to be below L, either because we checked (s), + // or because we reduced it modulo L (h_ram). L is under 2^253, so + // so bits 253 to 255 are guaranteed to be zero. No need to test them. + // + // Note however that L is very close to 2^252, so bit 252 is almost + // always zero. If we were to start at bit 251, the tests wouldn't + // catch the off-by-one error (constructing one that does would be + // prohibitively expensive). + // + // We should still check bit 252, though. + int i = 252; + while (i > 0 && scalar_bit(scalar, i) == 0) { + i--; + } + ctx->next_check = (u8)(i + 1); + ctx->next_index = -1; + ctx->next_digit = -1; +} + +static int slide_step(slide_ctx *ctx, int width, int i, const u8 scalar[32]) +{ + if (i == ctx->next_check) { + if (scalar_bit(scalar, i) == scalar_bit(scalar, i - 1)) { + ctx->next_check--; + } else { + // compute digit of next window + int w = MIN(width, i + 1); + int v = -(scalar_bit(scalar, i) << (w-1)); + FOR_T (int, j, 0, w-1) { + v += scalar_bit(scalar, i-(w-1)+j) << j; + } + v += scalar_bit(scalar, i-w); + int lsb = v & (~v + 1); // smallest bit of v + int s = // log2(lsb) + (((lsb & 0xAA) != 0) << 0) | + (((lsb & 0xCC) != 0) << 1) | + (((lsb & 0xF0) != 0) << 2); + ctx->next_index = (i16)(i-(w-1)+s); + ctx->next_digit = (i8) (v >> s ); + ctx->next_check -= (u8) w; + } + } + return i == ctx->next_index ? ctx->next_digit: 0; +} + +#define P_W_WIDTH 3 // Affects the size of the stack +#define B_W_WIDTH 5 // Affects the size of the binary +#define P_W_SIZE (1<<(P_W_WIDTH-2)) + +int crypto_eddsa_check_equation(const u8 signature[64], const u8 public_key[32], + const u8 h[32]) +{ + ge minus_A; // -public_key + ge minus_R; // -first_half_of_signature + const u8 *s = signature + 32; + + // Check that A and R are on the curve + // Check that 0 <= S < L (prevents malleability) + // *Allow* non-cannonical encoding for A and R + { + u32 s32[8]; + load32_le_buf(s32, s, 8); + if (ge_frombytes_neg_vartime(&minus_A, public_key) || + ge_frombytes_neg_vartime(&minus_R, signature) || + is_above_l(s32)) { + return -1; + } + } + + // look-up table for minus_A + ge_cached lutA[P_W_SIZE]; + { + ge minus_A2, tmp; + ge_double(&minus_A2, &minus_A, &tmp); + ge_cache(&lutA[0], &minus_A); + FOR (i, 1, P_W_SIZE) { + ge_add(&tmp, &minus_A2, &lutA[i-1]); + ge_cache(&lutA[i], &tmp); + } + } + + // sum = [s]B - [h]A + // Merged double and add ladder, fused with sliding + slide_ctx h_slide; slide_init(&h_slide, h); + slide_ctx s_slide; slide_init(&s_slide, s); + int i = MAX(h_slide.next_check, s_slide.next_check); + ge *sum = &minus_A; // reuse minus_A for the sum + ge_zero(sum); + while (i >= 0) { + ge tmp; + ge_double(sum, sum, &tmp); + int h_digit = slide_step(&h_slide, P_W_WIDTH, i, h); + int s_digit = slide_step(&s_slide, B_W_WIDTH, i, s); + if (h_digit > 0) { ge_add(sum, sum, &lutA[ h_digit / 2]); } + if (h_digit < 0) { ge_sub(sum, sum, &lutA[-h_digit / 2]); } + fe t1, t2; + if (s_digit > 0) { ge_madd(sum, sum, b_window + s_digit/2, t1, t2); } + if (s_digit < 0) { ge_msub(sum, sum, b_window + -s_digit/2, t1, t2); } + i--; + } + + // Compare [8](sum-R) and the zero point + // The multiplication by 8 eliminates any low-order component + // and ensures consistency with batched verification. + ge_cached cached; + u8 check[32]; + static const u8 zero_point[32] = {1}; // Point of order 1 + ge_cache(&cached, &minus_R); + ge_add(sum, sum, &cached); + ge_double(sum, sum, &minus_R); // reuse minus_R as temporary + ge_double(sum, sum, &minus_R); // reuse minus_R as temporary + ge_double(sum, sum, &minus_R); // reuse minus_R as temporary + ge_tobytes(check, sum); + return crypto_verify32(check, zero_point); +} + +// 5-bit signed comb in cached format (Niels coordinates, Z=1) +static const ge_precomp b_comb_low[8] = { + {{-6816601,-2324159,-22559413,124364,18015490, + 8373481,19993724,1979872,-18549925,9085059,}, + {10306321,403248,14839893,9633706,8463310, + -8354981,-14305673,14668847,26301366,2818560,}, + {-22701500,-3210264,-13831292,-2927732,-16326337, + -14016360,12940910,177905,12165515,-2397893,},}, + {{-12282262,-7022066,9920413,-3064358,-32147467, + 2927790,22392436,-14852487,2719975,16402117,}, + {-7236961,-4729776,2685954,-6525055,-24242706, + -15940211,-6238521,14082855,10047669,12228189,}, + {-30495588,-12893761,-11161261,3539405,-11502464, + 16491580,-27286798,-15030530,-7272871,-15934455,},}, + {{17650926,582297,-860412,-187745,-12072900, + -10683391,-20352381,15557840,-31072141,-5019061,}, + {-6283632,-2259834,-4674247,-4598977,-4089240, + 12435688,-31278303,1060251,6256175,10480726,}, + {-13871026,2026300,-21928428,-2741605,-2406664, + -8034988,7355518,15733500,-23379862,7489131,},}, + {{6883359,695140,23196907,9644202,-33430614, + 11354760,-20134606,6388313,-8263585,-8491918,}, + {-7716174,-13605463,-13646110,14757414,-19430591, + -14967316,10359532,-11059670,-21935259,12082603,}, + {-11253345,-15943946,10046784,5414629,24840771, + 8086951,-6694742,9868723,15842692,-16224787,},}, + {{9639399,11810955,-24007778,-9320054,3912937, + -9856959,996125,-8727907,-8919186,-14097242,}, + {7248867,14468564,25228636,-8795035,14346339, + 8224790,6388427,-7181107,6468218,-8720783,}, + {15513115,15439095,7342322,-10157390,18005294, + -7265713,2186239,4884640,10826567,7135781,},}, + {{-14204238,5297536,-5862318,-6004934,28095835, + 4236101,-14203318,1958636,-16816875,3837147,}, + {-5511166,-13176782,-29588215,12339465,15325758, + -15945770,-8813185,11075932,-19608050,-3776283,}, + {11728032,9603156,-4637821,-5304487,-7827751, + 2724948,31236191,-16760175,-7268616,14799772,},}, + {{-28842672,4840636,-12047946,-9101456,-1445464, + 381905,-30977094,-16523389,1290540,12798615,}, + {27246947,-10320914,14792098,-14518944,5302070, + -8746152,-3403974,-4149637,-27061213,10749585,}, + {25572375,-6270368,-15353037,16037944,1146292, + 32198,23487090,9585613,24714571,-1418265,},}, + {{19844825,282124,-17583147,11004019,-32004269, + -2716035,6105106,-1711007,-21010044,14338445,}, + {8027505,8191102,-18504907,-12335737,25173494, + -5923905,15446145,7483684,-30440441,10009108,}, + {-14134701,-4174411,10246585,-14677495,33553567, + -14012935,23366126,15080531,-7969992,7663473,},}, +}; + +static const ge_precomp b_comb_high[8] = { + {{33055887,-4431773,-521787,6654165,951411, + -6266464,-5158124,6995613,-5397442,-6985227,}, + {4014062,6967095,-11977872,3960002,8001989, + 5130302,-2154812,-1899602,-31954493,-16173976,}, + {16271757,-9212948,23792794,731486,-25808309, + -3546396,6964344,-4767590,10976593,10050757,},}, + {{2533007,-4288439,-24467768,-12387405,-13450051, + 14542280,12876301,13893535,15067764,8594792,}, + {20073501,-11623621,3165391,-13119866,13188608, + -11540496,-10751437,-13482671,29588810,2197295,}, + {-1084082,11831693,6031797,14062724,14748428, + -8159962,-20721760,11742548,31368706,13161200,},}, + {{2050412,-6457589,15321215,5273360,25484180, + 124590,-18187548,-7097255,-6691621,-14604792,}, + {9938196,2162889,-6158074,-1711248,4278932, + -2598531,-22865792,-7168500,-24323168,11746309,}, + {-22691768,-14268164,5965485,9383325,20443693, + 5854192,28250679,-1381811,-10837134,13717818,},}, + {{-8495530,16382250,9548884,-4971523,-4491811, + -3902147,6182256,-12832479,26628081,10395408,}, + {27329048,-15853735,7715764,8717446,-9215518, + -14633480,28982250,-5668414,4227628,242148,}, + {-13279943,-7986904,-7100016,8764468,-27276630, + 3096719,29678419,-9141299,3906709,11265498,},}, + {{11918285,15686328,-17757323,-11217300,-27548967, + 4853165,-27168827,6807359,6871949,-1075745,}, + {-29002610,13984323,-27111812,-2713442,28107359, + -13266203,6155126,15104658,3538727,-7513788,}, + {14103158,11233913,-33165269,9279850,31014152, + 4335090,-1827936,4590951,13960841,12787712,},}, + {{1469134,-16738009,33411928,13942824,8092558, + -8778224,-11165065,1437842,22521552,-2792954,}, + {31352705,-4807352,-25327300,3962447,12541566, + -9399651,-27425693,7964818,-23829869,5541287,}, + {-25732021,-6864887,23848984,3039395,-9147354, + 6022816,-27421653,10590137,25309915,-1584678,},}, + {{-22951376,5048948,31139401,-190316,-19542447, + -626310,-17486305,-16511925,-18851313,-12985140,}, + {-9684890,14681754,30487568,7717771,-10829709, + 9630497,30290549,-10531496,-27798994,-13812825,}, + {5827835,16097107,-24501327,12094619,7413972, + 11447087,28057551,-1793987,-14056981,4359312,},}, + {{26323183,2342588,-21887793,-1623758,-6062284, + 2107090,-28724907,9036464,-19618351,-13055189,}, + {-29697200,14829398,-4596333,14220089,-30022969, + 2955645,12094100,-13693652,-5941445,7047569,}, + {-3201977,14413268,-12058324,-16417589,-9035655, + -7224648,9258160,1399236,30397584,-5684634,},}, +}; + +static void lookup_add(ge *p, ge_precomp *tmp_c, fe tmp_a, fe tmp_b, + const ge_precomp comb[8], const u8 scalar[32], int i) +{ + u8 teeth = (u8)((scalar_bit(scalar, i) ) + + (scalar_bit(scalar, i + 32) << 1) + + (scalar_bit(scalar, i + 64) << 2) + + (scalar_bit(scalar, i + 96) << 3)); + u8 high = teeth >> 3; + u8 index = (teeth ^ (high - 1)) & 7; + FOR (j, 0, 8) { + i32 select = 1 & (((j ^ index) - 1) >> 8); + fe_ccopy(tmp_c->Yp, comb[j].Yp, select); + fe_ccopy(tmp_c->Ym, comb[j].Ym, select); + fe_ccopy(tmp_c->T2, comb[j].T2, select); + } + fe_neg(tmp_a, tmp_c->T2); + fe_cswap(tmp_c->T2, tmp_a , high ^ 1); + fe_cswap(tmp_c->Yp, tmp_c->Ym, high ^ 1); + ge_madd(p, p, tmp_c, tmp_a, tmp_b); +} + +// p = [scalar]B, where B is the base point +static void ge_scalarmult_base(ge *p, const u8 scalar[32]) +{ + // twin 4-bits signed combs, from Mike Hamburg's + // Fast and compact elliptic-curve cryptography (2012) + // 1 / 2 modulo L + static const u8 half_mod_L[32] = { + 247,233,122,46,141,49,9,44,107,206,123,81,239,124,111,10, + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,8, + }; + // (2^256 - 1) / 2 modulo L + static const u8 half_ones[32] = { + 142,74,204,70,186,24,118,107,184,231,190,57,250,173,119,99, + 255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,7, + }; + + // All bits set form: 1 means 1, 0 means -1 + u8 s_scalar[32]; + crypto_eddsa_mul_add(s_scalar, scalar, half_mod_L, half_ones); + + // Double and add ladder + fe tmp_a, tmp_b; // temporaries for addition + ge_precomp tmp_c; // temporary for comb lookup + ge tmp_d; // temporary for doubling + fe_1(tmp_c.Yp); + fe_1(tmp_c.Ym); + fe_0(tmp_c.T2); + + // Save a double on the first iteration + ge_zero(p); + lookup_add(p, &tmp_c, tmp_a, tmp_b, b_comb_low , s_scalar, 31); + lookup_add(p, &tmp_c, tmp_a, tmp_b, b_comb_high, s_scalar, 31+128); + // Regular double & add for the rest + for (int i = 30; i >= 0; i--) { + ge_double(p, p, &tmp_d); + lookup_add(p, &tmp_c, tmp_a, tmp_b, b_comb_low , s_scalar, i); + lookup_add(p, &tmp_c, tmp_a, tmp_b, b_comb_high, s_scalar, i+128); + } + // Note: we could save one addition at the end if we assumed the + // scalar fit in 252 bits. Which it does in practice if it is + // selected at random. However, non-random, non-hashed scalars + // *can* overflow 252 bits in practice. Better account for that + // than leaving that kind of subtle corner case. + + WIPE_BUFFER(tmp_a); WIPE_CTX(&tmp_d); + WIPE_BUFFER(tmp_b); WIPE_CTX(&tmp_c); + WIPE_BUFFER(s_scalar); +} + +void crypto_eddsa_scalarbase(u8 point[32], const u8 scalar[32]) +{ + ge P; + ge_scalarmult_base(&P, scalar); + ge_tobytes(point, &P); + WIPE_CTX(&P); +} + +void crypto_eddsa_key_pair(u8 secret_key[64], u8 public_key[32], u8 seed[32]) +{ + // To allow overlaps, observable writes happen in this order: + // 1. seed + // 2. secret_key + // 3. public_key + u8 a[64]; + COPY(a, seed, 32); + crypto_wipe(seed, 32); + COPY(secret_key, a, 32); + crypto_blake2b(a, 64, a, 32); + crypto_eddsa_trim_scalar(a, a); + crypto_eddsa_scalarbase(secret_key + 32, a); + COPY(public_key, secret_key + 32, 32); + WIPE_BUFFER(a); +} + +static void hash_reduce(u8 h[32], + const u8 *a, size_t a_size, + const u8 *b, size_t b_size, + const u8 *c, size_t c_size) +{ + u8 hash[64]; + crypto_blake2b_ctx ctx; + crypto_blake2b_init (&ctx, 64); + crypto_blake2b_update(&ctx, a, a_size); + crypto_blake2b_update(&ctx, b, b_size); + crypto_blake2b_update(&ctx, c, c_size); + crypto_blake2b_final (&ctx, hash); + crypto_eddsa_reduce(h, hash); +} + +// Digital signature of a message with from a secret key. +// +// The secret key comprises two parts: +// - The seed that generates the key (secret_key[ 0..31]) +// - The public key (secret_key[32..63]) +// +// The seed and the public key are bundled together to make sure users +// don't use mismatched seeds and public keys, which would instantly +// leak the secret scalar and allow forgeries (allowing this to happen +// has resulted in critical vulnerabilities in the wild). +// +// The seed is hashed to derive the secret scalar and a secret prefix. +// The sole purpose of the prefix is to generate a secret random nonce. +// The properties of that nonce must be as follows: +// - Unique: we need a different one for each message. +// - Secret: third parties must not be able to predict it. +// - Random: any detectable bias would break all security. +// +// There are two ways to achieve these properties. The obvious one is +// to simply generate a random number. Here that would be a parameter +// (Monocypher doesn't have an RNG). It works, but then users may reuse +// the nonce by accident, which _also_ leaks the secret scalar and +// allows forgeries. This has happened in the wild too. +// +// This is no good, so instead we generate that nonce deterministically +// by reducing modulo L a hash of the secret prefix and the message. +// The secret prefix makes the nonce unpredictable, the message makes it +// unique, and the hash/reduce removes all bias. +// +// The cost of that safety is hashing the message twice. If that cost +// is unacceptable, there are two alternatives: +// +// - Signing a hash of the message instead of the message itself. This +// is fine as long as the hash is collision resistant. It is not +// compatible with existing "pure" signatures, but at least it's safe. +// +// - Using a random nonce. Please exercise **EXTREME CAUTION** if you +// ever do that. It is absolutely **critical** that the nonce is +// really an unbiased random number between 0 and L-1, never reused, +// and wiped immediately. +// +// To lower the likelihood of complete catastrophe if the RNG is +// either flawed or misused, you can hash the RNG output together with +// the secret prefix and the beginning of the message, and use the +// reduction of that hash instead of the RNG output itself. It's not +// foolproof (you'd need to hash the whole message) but it helps. +// +// Signing a message involves the following operations: +// +// scalar, prefix = HASH(secret_key) +// r = HASH(prefix || message) % L +// R = [r]B +// h = HASH(R || public_key || message) % L +// S = ((h * a) + r) % L +// signature = R || S +void crypto_eddsa_sign(u8 signature [64], const u8 secret_key[64], + const u8 *message, size_t message_size) +{ + u8 a[64]; // secret scalar and prefix + u8 r[32]; // secret deterministic "random" nonce + u8 h[32]; // publically verifiable hash of the message (not wiped) + u8 R[32]; // first half of the signature (allows overlapping inputs) + + crypto_blake2b(a, 64, secret_key, 32); + crypto_eddsa_trim_scalar(a, a); + hash_reduce(r, a + 32, 32, message, message_size, 0, 0); + crypto_eddsa_scalarbase(R, r); + hash_reduce(h, R, 32, secret_key + 32, 32, message, message_size); + COPY(signature, R, 32); + crypto_eddsa_mul_add(signature + 32, h, a, r); + + WIPE_BUFFER(a); + WIPE_BUFFER(r); +} + +// To check the signature R, S of the message M with the public key A, +// there are 3 steps: +// +// compute h = HASH(R || A || message) % L +// check that A is on the curve. +// check that R == [s]B - [h]A +// +// The last two steps are done in crypto_eddsa_check_equation() +int crypto_eddsa_check(const u8 signature[64], const u8 public_key[32], + const u8 *message, size_t message_size) +{ + u8 h[32]; + hash_reduce(h, signature, 32, public_key, 32, message, message_size); + return crypto_eddsa_check_equation(signature, public_key, h); +} + +///////////////////////// +/// EdDSA <--> X25519 /// +///////////////////////// +void crypto_eddsa_to_x25519(u8 x25519[32], const u8 eddsa[32]) +{ + // (u, v) = ((1+y)/(1-y), sqrt(-486664)*u/x) + // Only converting y to u, the sign of x is ignored. + fe t1, t2; + fe_frombytes(t2, eddsa); + fe_add(t1, fe_one, t2); + fe_sub(t2, fe_one, t2); + fe_invert(t2, t2); + fe_mul(t1, t1, t2); + fe_tobytes(x25519, t1); + WIPE_BUFFER(t1); + WIPE_BUFFER(t2); +} + +void crypto_x25519_to_eddsa(u8 eddsa[32], const u8 x25519[32]) +{ + // (x, y) = (sqrt(-486664)*u/v, (u-1)/(u+1)) + // Only converting u to y, x is assumed positive. + fe t1, t2; + fe_frombytes(t2, x25519); + fe_sub(t1, t2, fe_one); + fe_add(t2, t2, fe_one); + fe_invert(t2, t2); + fe_mul(t1, t1, t2); + fe_tobytes(eddsa, t1); + WIPE_BUFFER(t1); + WIPE_BUFFER(t2); +} + +///////////////////////////////////////////// +/// Dirty ephemeral public key generation /// +///////////////////////////////////////////// + +// Those functions generates a public key, *without* clearing the +// cofactor. Sending that key over the network leaks 3 bits of the +// private key. Use only to generate ephemeral keys that will be hidden +// with crypto_curve_to_hidden(). +// +// The public key is otherwise compatible with crypto_x25519(), which +// properly clears the cofactor. +// +// Note that the distribution of the resulting public keys is almost +// uniform. Flipping the sign of the v coordinate (not provided by this +// function), covers the entire key space almost perfectly, where +// "almost" means a 2^-128 bias (undetectable). This uniformity is +// needed to ensure the proper randomness of the resulting +// representatives (once we apply crypto_curve_to_hidden()). +// +// Recall that Curve25519 has order C = 2^255 + e, with e < 2^128 (not +// to be confused with the prime order of the main subgroup, L, which is +// 8 times less than that). +// +// Generating all points would require us to multiply a point of order C +// (the base point plus any point of order 8) by all scalars from 0 to +// C-1. Clamping limits us to scalars between 2^254 and 2^255 - 1. But +// by negating the resulting point at random, we also cover scalars from +// -2^255 + 1 to -2^254 (which modulo C is congruent to e+1 to 2^254 + e). +// +// In practice: +// - Scalars from 0 to e + 1 are never generated +// - Scalars from 2^255 to 2^255 + e are never generated +// - Scalars from 2^254 + 1 to 2^254 + e are generated twice +// +// Since e < 2^128, detecting this bias requires observing over 2^100 +// representatives from a given source (this will never happen), *and* +// recovering enough of the private key to determine that they do, or do +// not, belong to the biased set (this practically requires solving +// discrete logarithm, which is conjecturally intractable). +// +// In practice, this means the bias is impossible to detect. + +// s + (x*L) % 8*L +// Guaranteed to fit in 256 bits iff s fits in 255 bits. +// L < 2^253 +// x%8 < 2^3 +// L * (x%8) < 2^255 +// s < 2^255 +// s + L * (x%8) < 2^256 +static void add_xl(u8 s[32], u8 x) +{ + u64 mod8 = x & 7; + u64 carry = 0; + FOR (i , 0, 8) { + carry = carry + load32_le(s + 4*i) + L[i] * mod8; + store32_le(s + 4*i, (u32)carry); + carry >>= 32; + } +} + +// "Small" dirty ephemeral key. +// Use if you need to shrink the size of the binary, and can afford to +// slow down by a factor of two (compared to the fast version) +// +// This version works by decoupling the cofactor from the main factor. +// +// - The trimmed scalar determines the main factor +// - The clamped bits of the scalar determine the cofactor. +// +// Cofactor and main factor are combined into a single scalar, which is +// then multiplied by a point of order 8*L (unlike the base point, which +// has prime order). That "dirty" base point is the addition of the +// regular base point (9), and a point of order 8. +void crypto_x25519_dirty_small(u8 public_key[32], const u8 secret_key[32]) +{ + // Base point of order 8*L + // Raw scalar multiplication with it does not clear the cofactor, + // and the resulting public key will reveal 3 bits of the scalar. + // + // The low order component of this base point has been chosen + // to yield the same results as crypto_x25519_dirty_fast(). + static const u8 dirty_base_point[32] = { + 0xd8, 0x86, 0x1a, 0xa2, 0x78, 0x7a, 0xd9, 0x26, + 0x8b, 0x74, 0x74, 0xb6, 0x82, 0xe3, 0xbe, 0xc3, + 0xce, 0x36, 0x9a, 0x1e, 0x5e, 0x31, 0x47, 0xa2, + 0x6d, 0x37, 0x7c, 0xfd, 0x20, 0xb5, 0xdf, 0x75, + }; + // separate the main factor & the cofactor of the scalar + u8 scalar[32]; + crypto_eddsa_trim_scalar(scalar, secret_key); + + // Separate the main factor and the cofactor + // + // The scalar is trimmed, so its cofactor is cleared. The three + // least significant bits however still have a main factor. We must + // remove it for X25519 compatibility. + // + // cofactor = lsb * L (modulo 8*L) + // combined = scalar + cofactor (modulo 8*L) + add_xl(scalar, secret_key[0]); + scalarmult(public_key, scalar, dirty_base_point, 256); + WIPE_BUFFER(scalar); +} + +// Select low order point +// We're computing the [cofactor]lop scalar multiplication, where: +// +// cofactor = tweak & 7. +// lop = (lop_x, lop_y) +// lop_x = sqrt((sqrt(d + 1) + 1) / d) +// lop_y = -lop_x * sqrtm1 +// +// The low order point has order 8. There are 4 such points. We've +// chosen the one whose both coordinates are positive (below p/2). +// The 8 low order points are as follows: +// +// [0]lop = ( 0 , 1 ) +// [1]lop = ( lop_x , lop_y) +// [2]lop = ( sqrt(-1), -0 ) +// [3]lop = ( lop_x , -lop_y) +// [4]lop = (-0 , -1 ) +// [5]lop = (-lop_x , -lop_y) +// [6]lop = (-sqrt(-1), 0 ) +// [7]lop = (-lop_x , lop_y) +// +// The x coordinate is either 0, sqrt(-1), lop_x, or their opposite. +// The y coordinate is either 0, -1 , lop_y, or their opposite. +// The pattern for both is the same, except for a rotation of 2 (modulo 8) +// +// This helper function captures the pattern, and we can use it thus: +// +// select_lop(x, lop_x, sqrtm1, cofactor); +// select_lop(y, lop_y, fe_one, cofactor + 2); +// +// This is faster than an actual scalar multiplication, +// and requires less code than naive constant time look up. +static void select_lop(fe out, const fe x, const fe k, u8 cofactor) +{ + fe tmp; + fe_0(out); + fe_ccopy(out, k , (cofactor >> 1) & 1); // bit 1 + fe_ccopy(out, x , (cofactor >> 0) & 1); // bit 0 + fe_neg (tmp, out); + fe_ccopy(out, tmp, (cofactor >> 2) & 1); // bit 2 + WIPE_BUFFER(tmp); +} + +// "Fast" dirty ephemeral key +// We use this one by default. +// +// This version works by performing a regular scalar multiplication, +// then add a low order point. The scalar multiplication is done in +// Edwards space for more speed (*2 compared to the "small" version). +// The cost is a bigger binary for programs that don't also sign messages. +void crypto_x25519_dirty_fast(u8 public_key[32], const u8 secret_key[32]) +{ + // Compute clean scalar multiplication + u8 scalar[32]; + ge pk; + crypto_eddsa_trim_scalar(scalar, secret_key); + ge_scalarmult_base(&pk, scalar); + + // Compute low order point + fe t1, t2; + select_lop(t1, lop_x, sqrtm1, secret_key[0]); + select_lop(t2, lop_y, fe_one, secret_key[0] + 2); + ge_precomp low_order_point; + fe_add(low_order_point.Yp, t2, t1); + fe_sub(low_order_point.Ym, t2, t1); + fe_mul(low_order_point.T2, t2, t1); + fe_mul(low_order_point.T2, low_order_point.T2, D2); + + // Add low order point to the public key + ge_madd(&pk, &pk, &low_order_point, t1, t2); + + // Convert to Montgomery u coordinate (we ignore the sign) + fe_add(t1, pk.Z, pk.Y); + fe_sub(t2, pk.Z, pk.Y); + fe_invert(t2, t2); + fe_mul(t1, t1, t2); + + fe_tobytes(public_key, t1); + + WIPE_BUFFER(t1); WIPE_CTX(&pk); + WIPE_BUFFER(t2); WIPE_CTX(&low_order_point); + WIPE_BUFFER(scalar); +} + +/////////////////// +/// Elligator 2 /// +/////////////////// +static const fe A = {486662}; + +// Elligator direct map +// +// Computes the point corresponding to a representative, encoded in 32 +// bytes (little Endian). Since positive representatives fits in 254 +// bits, The two most significant bits are ignored. +// +// From the paper: +// w = -A / (fe(1) + non_square * r^2) +// e = chi(w^3 + A*w^2 + w) +// u = e*w - (fe(1)-e)*(A//2) +// v = -e * sqrt(u^3 + A*u^2 + u) +// +// We ignore v because we don't need it for X25519 (the Montgomery +// ladder only uses u). +// +// Note that e is either 0, 1 or -1 +// if e = 0 u = 0 and v = 0 +// if e = 1 u = w +// if e = -1 u = -w - A = w * non_square * r^2 +// +// Let r1 = non_square * r^2 +// Let r2 = 1 + r1 +// Note that r2 cannot be zero, -1/non_square is not a square. +// We can (tediously) verify that: +// w^3 + A*w^2 + w = (A^2*r1 - r2^2) * A / r2^3 +// Therefore: +// chi(w^3 + A*w^2 + w) = chi((A^2*r1 - r2^2) * (A / r2^3)) +// chi(w^3 + A*w^2 + w) = chi((A^2*r1 - r2^2) * (A / r2^3)) * 1 +// chi(w^3 + A*w^2 + w) = chi((A^2*r1 - r2^2) * (A / r2^3)) * chi(r2^6) +// chi(w^3 + A*w^2 + w) = chi((A^2*r1 - r2^2) * (A / r2^3) * r2^6) +// chi(w^3 + A*w^2 + w) = chi((A^2*r1 - r2^2) * A * r2^3) +// Corollary: +// e = 1 if (A^2*r1 - r2^2) * A * r2^3) is a non-zero square +// e = -1 if (A^2*r1 - r2^2) * A * r2^3) is not a square +// Note that w^3 + A*w^2 + w (and therefore e) can never be zero: +// w^3 + A*w^2 + w = w * (w^2 + A*w + 1) +// w^3 + A*w^2 + w = w * (w^2 + A*w + A^2/4 - A^2/4 + 1) +// w^3 + A*w^2 + w = w * (w + A/2)^2 - A^2/4 + 1) +// which is zero only if: +// w = 0 (impossible) +// (w + A/2)^2 = A^2/4 - 1 (impossible, because A^2/4-1 is not a square) +// +// Let isr = invsqrt((A^2*r1 - r2^2) * A * r2^3) +// isr = sqrt(1 / ((A^2*r1 - r2^2) * A * r2^3)) if e = 1 +// isr = sqrt(sqrt(-1) / ((A^2*r1 - r2^2) * A * r2^3)) if e = -1 +// +// if e = 1 +// let u1 = -A * (A^2*r1 - r2^2) * A * r2^2 * isr^2 +// u1 = w +// u1 = u +// +// if e = -1 +// let ufactor = -non_square * sqrt(-1) * r^2 +// let vfactor = sqrt(ufactor) +// let u2 = -A * (A^2*r1 - r2^2) * A * r2^2 * isr^2 * ufactor +// u2 = w * -1 * -non_square * r^2 +// u2 = w * non_square * r^2 +// u2 = u +void crypto_elligator_map(u8 curve[32], const u8 hidden[32]) +{ + fe r, u, t1, t2, t3; + fe_frombytes_mask(r, hidden, 2); // r is encoded in 254 bits. + fe_sq(r, r); + fe_add(t1, r, r); + fe_add(u, t1, fe_one); + fe_sq (t2, u); + fe_mul(t3, A2, t1); + fe_sub(t3, t3, t2); + fe_mul(t3, t3, A); + fe_mul(t1, t2, u); + fe_mul(t1, t3, t1); + int is_square = invsqrt(t1, t1); + fe_mul(u, r, ufactor); + fe_ccopy(u, fe_one, is_square); + fe_sq (t1, t1); + fe_mul(u, u, A); + fe_mul(u, u, t3); + fe_mul(u, u, t2); + fe_mul(u, u, t1); + fe_neg(u, u); + fe_tobytes(curve, u); + + WIPE_BUFFER(t1); WIPE_BUFFER(r); + WIPE_BUFFER(t2); WIPE_BUFFER(u); + WIPE_BUFFER(t3); +} + +// Elligator inverse map +// +// Computes the representative of a point, if possible. If not, it does +// nothing and returns -1. Note that the success of the operation +// depends only on the point (more precisely its u coordinate). The +// tweak parameter is used only upon success +// +// The tweak should be a random byte. Beyond that, its contents are an +// implementation detail. Currently, the tweak comprises: +// - Bit 1 : sign of the v coordinate (0 if positive, 1 if negative) +// - Bit 2-5: not used +// - Bits 6-7: random padding +// +// From the paper: +// Let sq = -non_square * u * (u+A) +// if sq is not a square, or u = -A, there is no mapping +// Assuming there is a mapping: +// if v is positive: r = sqrt(-u / (non_square * (u+A))) +// if v is negative: r = sqrt(-(u+A) / (non_square * u )) +// +// We compute isr = invsqrt(-non_square * u * (u+A)) +// if it wasn't a square, abort. +// else, isr = sqrt(-1 / (non_square * u * (u+A)) +// +// If v is positive, we return isr * u: +// isr * u = sqrt(-1 / (non_square * u * (u+A)) * u +// isr * u = sqrt(-u / (non_square * (u+A)) +// +// If v is negative, we return isr * (u+A): +// isr * (u+A) = sqrt(-1 / (non_square * u * (u+A)) * (u+A) +// isr * (u+A) = sqrt(-(u+A) / (non_square * u) +int crypto_elligator_rev(u8 hidden[32], const u8 public_key[32], u8 tweak) +{ + fe t1, t2, t3; + fe_frombytes(t1, public_key); // t1 = u + + fe_add(t2, t1, A); // t2 = u + A + fe_mul(t3, t1, t2); + fe_mul_small(t3, t3, -2); + int is_square = invsqrt(t3, t3); // t3 = sqrt(-1 / non_square * u * (u+A)) + if (is_square) { + // The only variable time bit. This ultimately reveals how many + // tries it took us to find a representable key. + // This does not affect security as long as we try keys at random. + + fe_ccopy (t1, t2, tweak & 1); // multiply by u if v is positive, + fe_mul (t3, t1, t3); // multiply by u+A otherwise + fe_mul_small(t1, t3, 2); + fe_neg (t2, t3); + fe_ccopy (t3, t2, fe_isodd(t1)); + fe_tobytes(hidden, t3); + + // Pad with two random bits + hidden[31] |= tweak & 0xc0; + } + + WIPE_BUFFER(t1); + WIPE_BUFFER(t2); + WIPE_BUFFER(t3); + return is_square - 1; +} + +void crypto_elligator_key_pair(u8 hidden[32], u8 secret_key[32], u8 seed[32]) +{ + u8 pk [32]; // public key + u8 buf[64]; // seed + representative + COPY(buf + 32, seed, 32); + do { + crypto_chacha20_djb(buf, 0, 64, buf+32, zero, 0); + crypto_x25519_dirty_fast(pk, buf); // or the "small" version + } while(crypto_elligator_rev(buf+32, pk, buf[32])); + // Note that the return value of crypto_elligator_rev() is + // independent from its tweak parameter. + // Therefore, buf[32] is not actually reused. Either we loop one + // more time and buf[32] is used for the new seed, or we succeeded, + // and buf[32] becomes the tweak parameter. + + crypto_wipe(seed, 32); + COPY(hidden , buf + 32, 32); + COPY(secret_key, buf , 32); + WIPE_BUFFER(buf); + WIPE_BUFFER(pk); +} + +/////////////////////// +/// Scalar division /// +/////////////////////// + +// Montgomery reduction. +// Divides x by (2^256), and reduces the result modulo L +// +// Precondition: +// x < L * 2^256 +// Constants: +// r = 2^256 (makes division by r trivial) +// k = (r * (1/r) - 1) // L (1/r is computed modulo L ) +// Algorithm: +// s = (x * k) % r +// t = x + s*L (t is always a multiple of r) +// u = (t/r) % L (u is always below 2*L, conditional subtraction is enough) +static void redc(u32 u[8], u32 x[16]) +{ + static const u32 k[8] = { + 0x12547e1b, 0xd2b51da3, 0xfdba84ff, 0xb1a206f2, + 0xffa36bea, 0x14e75438, 0x6fe91836, 0x9db6c6f2, + }; + + // s = x * k (modulo 2^256) + // This is cheaper than the full multiplication. + u32 s[8] = {0}; + FOR (i, 0, 8) { + u64 carry = 0; + FOR (j, 0, 8-i) { + carry += s[i+j] + (u64)x[i] * k[j]; + s[i+j] = (u32)carry; + carry >>= 32; + } + } + u32 t[16] = {0}; + multiply(t, s, L); + + // t = t + x + u64 carry = 0; + FOR (i, 0, 16) { + carry += (u64)t[i] + x[i]; + t[i] = (u32)carry; + carry >>= 32; + } + + // u = (t / 2^256) % L + // Note that t / 2^256 is always below 2*L, + // So a constant time conditional subtraction is enough + remove_l(u, t+8); + + WIPE_BUFFER(s); + WIPE_BUFFER(t); +} + +void crypto_x25519_inverse(u8 blind_salt [32], const u8 private_key[32], + const u8 curve_point[32]) +{ + static const u8 Lm2[32] = { // L - 2 + 0xeb, 0xd3, 0xf5, 0x5c, 0x1a, 0x63, 0x12, 0x58, + 0xd6, 0x9c, 0xf7, 0xa2, 0xde, 0xf9, 0xde, 0x14, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, + }; + // 1 in Montgomery form + u32 m_inv [8] = { + 0x8d98951d, 0xd6ec3174, 0x737dcf70, 0xc6ef5bf4, + 0xfffffffe, 0xffffffff, 0xffffffff, 0x0fffffff, + }; + + u8 scalar[32]; + crypto_eddsa_trim_scalar(scalar, private_key); + + // Convert the scalar in Montgomery form + // m_scl = scalar * 2^256 (modulo L) + u32 m_scl[8]; + { + u32 tmp[16]; + ZERO(tmp, 8); + load32_le_buf(tmp+8, scalar, 8); + mod_l(scalar, tmp); + load32_le_buf(m_scl, scalar, 8); + WIPE_BUFFER(tmp); // Wipe ASAP to save stack space + } + + // Compute the inverse + u32 product[16]; + for (int i = 252; i >= 0; i--) { + ZERO(product, 16); + multiply(product, m_inv, m_inv); + redc(m_inv, product); + if (scalar_bit(Lm2, i)) { + ZERO(product, 16); + multiply(product, m_inv, m_scl); + redc(m_inv, product); + } + } + // Convert the inverse *out* of Montgomery form + // scalar = m_inv / 2^256 (modulo L) + COPY(product, m_inv, 8); + ZERO(product + 8, 8); + redc(m_inv, product); + store32_le_buf(scalar, m_inv, 8); // the *inverse* of the scalar + + // Clear the cofactor of scalar: + // cleared = scalar * (3*L + 1) (modulo 8*L) + // cleared = scalar + scalar * 3 * L (modulo 8*L) + // Note that (scalar * 3) is reduced modulo 8, so we only need the + // first byte. + add_xl(scalar, scalar[0] * 3); + + // Recall that 8*L < 2^256. However it is also very close to + // 2^255. If we spanned the ladder over 255 bits, random tests + // wouldn't catch the off-by-one error. + scalarmult(blind_salt, scalar, curve_point, 256); + + WIPE_BUFFER(scalar); WIPE_BUFFER(m_scl); + WIPE_BUFFER(product); WIPE_BUFFER(m_inv); +} + +//////////////////////////////// +/// Authenticated encryption /// +//////////////////////////////// +static void lock_auth(u8 mac[16], const u8 auth_key[32], + const u8 *ad , size_t ad_size, + const u8 *cipher_text, size_t text_size) +{ + u8 sizes[16]; // Not secret, not wiped + store64_le(sizes + 0, ad_size); + store64_le(sizes + 8, text_size); + crypto_poly1305_ctx poly_ctx; // auto wiped... + crypto_poly1305_init (&poly_ctx, auth_key); + crypto_poly1305_update(&poly_ctx, ad , ad_size); + crypto_poly1305_update(&poly_ctx, zero , gap(ad_size, 16)); + crypto_poly1305_update(&poly_ctx, cipher_text, text_size); + crypto_poly1305_update(&poly_ctx, zero , gap(text_size, 16)); + crypto_poly1305_update(&poly_ctx, sizes , 16); + crypto_poly1305_final (&poly_ctx, mac); // ...here +} + +void crypto_aead_init_x(crypto_aead_ctx *ctx, + u8 const key[32], const u8 nonce[24]) +{ + crypto_chacha20_h(ctx->key, key, nonce); + COPY(ctx->nonce, nonce + 16, 8); + ctx->counter = 0; +} + +void crypto_aead_init_djb(crypto_aead_ctx *ctx, + const u8 key[32], const u8 nonce[8]) +{ + COPY(ctx->key , key , 32); + COPY(ctx->nonce, nonce, 8); + ctx->counter = 0; +} + +void crypto_aead_init_ietf(crypto_aead_ctx *ctx, + const u8 key[32], const u8 nonce[12]) +{ + COPY(ctx->key , key , 32); + COPY(ctx->nonce, nonce + 4, 8); + ctx->counter = (u64)load32_le(nonce) << 32; +} + +void crypto_aead_write(crypto_aead_ctx *ctx, u8 *cipher_text, u8 mac[16], + const u8 *ad, size_t ad_size, + const u8 *plain_text, size_t text_size) +{ + u8 auth_key[64]; // the last 32 bytes are used for rekeying. + crypto_chacha20_djb(auth_key, 0, 64, ctx->key, ctx->nonce, ctx->counter); + crypto_chacha20_djb(cipher_text, plain_text, text_size, + ctx->key, ctx->nonce, ctx->counter + 1); + lock_auth(mac, auth_key, ad, ad_size, cipher_text, text_size); + COPY(ctx->key, auth_key + 32, 32); + WIPE_BUFFER(auth_key); +} + +int crypto_aead_read(crypto_aead_ctx *ctx, u8 *plain_text, const u8 mac[16], + const u8 *ad, size_t ad_size, + const u8 *cipher_text, size_t text_size) +{ + u8 auth_key[64]; // the last 32 bytes are used for rekeying. + u8 real_mac[16]; + crypto_chacha20_djb(auth_key, 0, 64, ctx->key, ctx->nonce, ctx->counter); + lock_auth(real_mac, auth_key, ad, ad_size, cipher_text, text_size); + int mismatch = crypto_verify16(mac, real_mac); + if (!mismatch) { + crypto_chacha20_djb(plain_text, cipher_text, text_size, + ctx->key, ctx->nonce, ctx->counter + 1); + COPY(ctx->key, auth_key + 32, 32); + } + WIPE_BUFFER(auth_key); + WIPE_BUFFER(real_mac); + return mismatch; +} + +void crypto_aead_lock(u8 *cipher_text, u8 mac[16], const u8 key[32], + const u8 nonce[24], const u8 *ad, size_t ad_size, + const u8 *plain_text, size_t text_size) +{ + crypto_aead_ctx ctx; + crypto_aead_init_x(&ctx, key, nonce); + crypto_aead_write(&ctx, cipher_text, mac, ad, ad_size, + plain_text, text_size); + crypto_wipe(&ctx, sizeof(ctx)); +} + +int crypto_aead_unlock(u8 *plain_text, const u8 mac[16], const u8 key[32], + const u8 nonce[24], const u8 *ad, size_t ad_size, + const u8 *cipher_text, size_t text_size) +{ + crypto_aead_ctx ctx; + crypto_aead_init_x(&ctx, key, nonce); + int mismatch = crypto_aead_read(&ctx, plain_text, mac, ad, ad_size, + cipher_text, text_size); + crypto_wipe(&ctx, sizeof(ctx)); + return mismatch; +} + +#ifdef MONOCYPHER_CPP_NAMESPACE +} +#endif diff --git a/User/lib/monocypher/monocypher.h b/User/lib/monocypher/monocypher.h new file mode 100644 index 0000000..291b8b9 --- /dev/null +++ b/User/lib/monocypher/monocypher.h @@ -0,0 +1,321 @@ +// Monocypher version 4.0.3 +// +// This file is dual-licensed. Choose whichever licence you want from +// the two licences listed below. +// +// The first licence is a regular 2-clause BSD licence. The second licence +// is the CC-0 from Creative Commons. It is intended to release Monocypher +// to the public domain. The BSD licence serves as a fallback option. +// +// SPDX-License-Identifier: BSD-2-Clause OR CC0-1.0 +// +// ------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019, Loup Vaillant +// All rights reserved. +// +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are +// met: +// +// 1. Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// 2. Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +// ------------------------------------------------------------------------ +// +// Written in 2017-2019 by Loup Vaillant +// +// To the extent possible under law, the author(s) have dedicated all copyright +// and related neighboring rights to this software to the public domain +// worldwide. This software is distributed without any warranty. +// +// You should have received a copy of the CC0 Public Domain Dedication along +// with this software. If not, see +// + +#ifndef MONOCYPHER_H +#define MONOCYPHER_H + +#include +#include + +#ifdef MONOCYPHER_CPP_NAMESPACE +namespace MONOCYPHER_CPP_NAMESPACE { +#elif defined(__cplusplus) +extern "C" { +#endif + +// Constant time comparisons +// ------------------------- + +// Return 0 if a and b are equal, -1 otherwise +int crypto_verify16(const uint8_t a[16], const uint8_t b[16]); +int crypto_verify32(const uint8_t a[32], const uint8_t b[32]); +int crypto_verify64(const uint8_t a[64], const uint8_t b[64]); + + +// Erase sensitive data +// -------------------- +void crypto_wipe(void *secret, size_t size); + + +// Authenticated encryption +// ------------------------ +void crypto_aead_lock(uint8_t *cipher_text, + uint8_t mac [16], + const uint8_t key [32], + const uint8_t nonce[24], + const uint8_t *ad, size_t ad_size, + const uint8_t *plain_text, size_t text_size); +int crypto_aead_unlock(uint8_t *plain_text, + const uint8_t mac [16], + const uint8_t key [32], + const uint8_t nonce[24], + const uint8_t *ad, size_t ad_size, + const uint8_t *cipher_text, size_t text_size); + +// Authenticated stream +// -------------------- +typedef struct { + uint64_t counter; + uint8_t key[32]; + uint8_t nonce[8]; +} crypto_aead_ctx; + +void crypto_aead_init_x(crypto_aead_ctx *ctx, + const uint8_t key[32], const uint8_t nonce[24]); +void crypto_aead_init_djb(crypto_aead_ctx *ctx, + const uint8_t key[32], const uint8_t nonce[8]); +void crypto_aead_init_ietf(crypto_aead_ctx *ctx, + const uint8_t key[32], const uint8_t nonce[12]); + +void crypto_aead_write(crypto_aead_ctx *ctx, + uint8_t *cipher_text, + uint8_t mac[16], + const uint8_t *ad , size_t ad_size, + const uint8_t *plain_text, size_t text_size); +int crypto_aead_read(crypto_aead_ctx *ctx, + uint8_t *plain_text, + const uint8_t mac[16], + const uint8_t *ad , size_t ad_size, + const uint8_t *cipher_text, size_t text_size); + + +// General purpose hash (BLAKE2b) +// ------------------------------ + +// Direct interface +void crypto_blake2b(uint8_t *hash, size_t hash_size, + const uint8_t *message, size_t message_size); + +void crypto_blake2b_keyed(uint8_t *hash, size_t hash_size, + const uint8_t *key, size_t key_size, + const uint8_t *message, size_t message_size); + +// Incremental interface +typedef struct { + // Do not rely on the size or contents of this type, + // for they may change without notice. + uint64_t hash[8]; + uint64_t input_offset[2]; + uint64_t input[16]; + size_t input_idx; + size_t hash_size; +} crypto_blake2b_ctx; + +void crypto_blake2b_init(crypto_blake2b_ctx *ctx, size_t hash_size); +void crypto_blake2b_keyed_init(crypto_blake2b_ctx *ctx, size_t hash_size, + const uint8_t *key, size_t key_size); +void crypto_blake2b_update(crypto_blake2b_ctx *ctx, + const uint8_t *message, size_t message_size); +void crypto_blake2b_final(crypto_blake2b_ctx *ctx, uint8_t *hash); + + +// Password key derivation (Argon2) +// -------------------------------- +#define CRYPTO_ARGON2_D 0 +#define CRYPTO_ARGON2_I 1 +#define CRYPTO_ARGON2_ID 2 + +typedef struct { + uint32_t algorithm; // Argon2d, Argon2i, Argon2id + uint32_t nb_blocks; // memory hardness, >= 8 * nb_lanes + uint32_t nb_passes; // CPU hardness, >= 1 (>= 3 recommended for Argon2i) + uint32_t nb_lanes; // parallelism level (single threaded anyway) +} crypto_argon2_config; + +typedef struct { + const uint8_t *pass; + const uint8_t *salt; + uint32_t pass_size; + uint32_t salt_size; // 16 bytes recommended +} crypto_argon2_inputs; + +typedef struct { + const uint8_t *key; // may be NULL if no key + const uint8_t *ad; // may be NULL if no additional data + uint32_t key_size; // 0 if no key (32 bytes recommended otherwise) + uint32_t ad_size; // 0 if no additional data +} crypto_argon2_extras; + +extern const crypto_argon2_extras crypto_argon2_no_extras; + +void crypto_argon2(uint8_t *hash, uint32_t hash_size, void *work_area, + crypto_argon2_config config, + crypto_argon2_inputs inputs, + crypto_argon2_extras extras); + + +// Key exchange (X-25519) +// ---------------------- + +// Shared secrets are not quite random. +// Hash them to derive an actual shared key. +void crypto_x25519_public_key(uint8_t public_key[32], + const uint8_t secret_key[32]); +void crypto_x25519(uint8_t raw_shared_secret[32], + const uint8_t your_secret_key [32], + const uint8_t their_public_key [32]); + +// Conversion to EdDSA +void crypto_x25519_to_eddsa(uint8_t eddsa[32], const uint8_t x25519[32]); + +// scalar "division" +// Used for OPRF. Be aware that exponential blinding is less secure +// than Diffie-Hellman key exchange. +void crypto_x25519_inverse(uint8_t blind_salt [32], + const uint8_t private_key[32], + const uint8_t curve_point[32]); + +// "Dirty" versions of x25519_public_key(). +// Use with crypto_elligator_rev(). +// Leaks 3 bits of the private key. +void crypto_x25519_dirty_small(uint8_t pk[32], const uint8_t sk[32]); +void crypto_x25519_dirty_fast (uint8_t pk[32], const uint8_t sk[32]); + + +// Signatures +// ---------- + +// EdDSA with curve25519 + BLAKE2b +void crypto_eddsa_key_pair(uint8_t secret_key[64], + uint8_t public_key[32], + uint8_t seed[32]); +void crypto_eddsa_sign(uint8_t signature [64], + const uint8_t secret_key[64], + const uint8_t *message, size_t message_size); +int crypto_eddsa_check(const uint8_t signature [64], + const uint8_t public_key[32], + const uint8_t *message, size_t message_size); + +// Conversion to X25519 +void crypto_eddsa_to_x25519(uint8_t x25519[32], const uint8_t eddsa[32]); + +// EdDSA building blocks +void crypto_eddsa_trim_scalar(uint8_t out[32], const uint8_t in[32]); +void crypto_eddsa_reduce(uint8_t reduced[32], const uint8_t expanded[64]); +void crypto_eddsa_mul_add(uint8_t r[32], + const uint8_t a[32], + const uint8_t b[32], + const uint8_t c[32]); +void crypto_eddsa_scalarbase(uint8_t point[32], const uint8_t scalar[32]); +int crypto_eddsa_check_equation(const uint8_t signature[64], + const uint8_t public_key[32], + const uint8_t h_ram[32]); + + +// Chacha20 +// -------- + +// Specialised hash. +// Used to hash X25519 shared secrets. +void crypto_chacha20_h(uint8_t out[32], + const uint8_t key[32], + const uint8_t in [16]); + +// Unauthenticated stream cipher. +// Don't forget to add authentication. +uint64_t crypto_chacha20_djb(uint8_t *cipher_text, + const uint8_t *plain_text, + size_t text_size, + const uint8_t key[32], + const uint8_t nonce[8], + uint64_t ctr); +uint32_t crypto_chacha20_ietf(uint8_t *cipher_text, + const uint8_t *plain_text, + size_t text_size, + const uint8_t key[32], + const uint8_t nonce[12], + uint32_t ctr); +uint64_t crypto_chacha20_x(uint8_t *cipher_text, + const uint8_t *plain_text, + size_t text_size, + const uint8_t key[32], + const uint8_t nonce[24], + uint64_t ctr); + + +// Poly 1305 +// --------- + +// This is a *one time* authenticator. +// Disclosing the mac reveals the key. +// See crypto_lock() on how to use it properly. + +// Direct interface +void crypto_poly1305(uint8_t mac[16], + const uint8_t *message, size_t message_size, + const uint8_t key[32]); + +// Incremental interface +typedef struct { + // Do not rely on the size or contents of this type, + // for they may change without notice. + uint8_t c[16]; // chunk of the message + size_t c_idx; // How many bytes are there in the chunk. + uint32_t r [4]; // constant multiplier (from the secret key) + uint32_t pad[4]; // random number added at the end (from the secret key) + uint32_t h [5]; // accumulated hash +} crypto_poly1305_ctx; + +void crypto_poly1305_init (crypto_poly1305_ctx *ctx, const uint8_t key[32]); +void crypto_poly1305_update(crypto_poly1305_ctx *ctx, + const uint8_t *message, size_t message_size); +void crypto_poly1305_final (crypto_poly1305_ctx *ctx, uint8_t mac[16]); + + +// Elligator 2 +// ----------- + +// Elligator mappings proper +void crypto_elligator_map(uint8_t curve [32], const uint8_t hidden[32]); +int crypto_elligator_rev(uint8_t hidden[32], const uint8_t curve [32], + uint8_t tweak); + +// Easy to use key pair generation +void crypto_elligator_key_pair(uint8_t hidden[32], uint8_t secret_key[32], + uint8_t seed[32]); + +#ifdef __cplusplus +} +#endif + +#endif // MONOCYPHER_H diff --git a/User/lib/rtc/rtc.c b/User/lib/rtc/rtc.c new file mode 100644 index 0000000..fa5b8b4 --- /dev/null +++ b/User/lib/rtc/rtc.c @@ -0,0 +1,292 @@ +#include "ch32v30x_misc.h" +#include "stdint.h" +#include "rtc.h" + +_calendar_obj calendar; + + +uint8_t const table_week[12] = {0, 3, 3, 6, 1, 4, 6, 2, 5, 0, 3, 5}; +const uint8_t mon_table[12] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; + +/********************************************************************* + * @fn RTC_NVIC_Config + * + * @brief Initializes RTC Int. + * + * @return none + */ +void RTC_NVIC_Config (void) { + NVIC_InitTypeDef NVIC_InitStructure = {0}; + NVIC_InitStructure.NVIC_IRQChannel = RTC_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init (&NVIC_InitStructure); +} + +/********************************************************************* + * @fn Is_Leap_Year + * + * @brief Judging whether it is a leap year. + * + * @param year + * + * @return 1 - Yes + * 0 - No + */ +uint8_t Is_Leap_Year (uint16_t year) { + if (year % 4 == 0) { + if (year % 100 == 0) { + if (year % 400 == 0) + return 1; + else + return 0; + } else + return 1; + } else + return 0; +} + +static uint8_t month_from_str(const char *m) { + static const char months[] = "JanFebMarAprMayJunJulAugSepOctNovDec"; + for (uint8_t i = 0; i < 12; i++) { + if (m[0] == months[i*3] && + m[1] == months[i*3 + 1] && + m[2] == months[i*3 + 2]) + return i + 1; // 1¨C12 + } + return 0; // should never happen +} + +void RTC_Set_From_BuildTime(void) { + const char *date = __DATE__; + const char *time = __TIME__; + + uint16_t year = + (date[7] - '0') * 1000 + + (date[8] - '0') * 100 + + (date[9] - '0') * 10 + + (date[10] - '0'); + + uint8_t month = month_from_str(date); + uint8_t day = + (date[4] == ' ' ? 0 : (date[4] - '0') * 10) + + (date[5] - '0'); + + uint8_t hour = + (time[0] - '0') * 10 + (time[1] - '0') - 1; + uint8_t min = + (time[3] - '0') * 10 + (time[4] - '0'); + uint8_t sec = + (time[6] - '0') * 10 + (time[7] - '0'); + + RTC_Set(year, month, day, hour, min, sec); +} + + +/********************************************************************* + * @fn RTC_Set + * + * @brief Set Time. + * + * @param Struct of _calendar_obj + * + * @return 1 - error + * 0 - success + */ +uint8_t RTC_Set (uint16_t syear, uint8_t smon, uint8_t sday, uint8_t hour, uint8_t min, uint8_t sec) { + uint16_t t; + u32 seccount = 0; + if (syear < 1970 || syear > 2099) + return 1; + for (t = 1970; t < syear; t++) { + if (Is_Leap_Year (t)) + seccount += 31622400; + else + seccount += 31536000; + } + smon -= 1; + for (t = 0; t < smon; t++) { + seccount += (u32)mon_table[t] * 86400; + if (Is_Leap_Year (syear) && t == 1) + seccount += 86400; + } + seccount += (u32)(sday - 1) * 86400; + seccount += (u32)hour * 3600; + seccount += (u32)min * 60; + seccount += sec; + + RCC_APB1PeriphClockCmd (RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE); + PWR_BackupAccessCmd (ENABLE); + RTC_SetCounter (seccount); + RTC_WaitForLastTask(); + return 0; +} + +/********************************************************************* + * @fn RTC_Alarm_Set + * + * @brief Set Alarm Time. + * + * @param Struct of _calendar_obj + * + * @return 1 - error + * 0 - success + */ +uint8_t RTC_Alarm_Set (uint16_t syear, uint8_t smon, uint8_t sday, uint8_t hour, uint8_t min, uint8_t sec) { + uint16_t t; + u32 seccount = 0; + if (syear < 1970 || syear > 2099) + return 1; + for (t = 1970; t < syear; t++) { + if (Is_Leap_Year (t)) + seccount += 31622400; + else + seccount += 31536000; + } + smon -= 1; + for (t = 0; t < smon; t++) { + seccount += (u32)mon_table[t] * 86400; + if (Is_Leap_Year (syear) && t == 1) + seccount += 86400; + } + seccount += (u32)(sday - 1) * 86400; + seccount += (u32)hour * 3600; + seccount += (u32)min * 60; + seccount += sec; + + RCC_APB1PeriphClockCmd (RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE); + PWR_BackupAccessCmd (ENABLE); + RTC_SetAlarm (seccount); + RTC_WaitForLastTask(); + + return 0; +} + +/********************************************************************* + * @fn RTC_Get_Week + * + * @brief Get the current day of the week. + * + * @param year/month/day + * + * @return week + */ +uint8_t RTC_Get_Week (uint16_t year, uint8_t month, uint8_t day) { + uint16_t temp2; + uint8_t yearH, yearL; + + yearH = year / 100; + yearL = year % 100; + if (yearH > 19) + yearL += 100; + temp2 = yearL + yearL / 4; + temp2 = temp2 % 7; + temp2 = temp2 + day + table_week[month - 1]; + if (yearL % 4 == 0 && month < 3) + temp2--; + return (temp2 % 7); +} + +/********************************************************************* + * @fn RTC_Get + * + * @brief Get current time. + * + * @return 1 - error + * 0 - success + */ +uint8_t RTC_Get (void) { + static uint16_t daycnt = 0; + u32 timecount = 0; + u32 temp = 0; + uint16_t temp1 = 0; + timecount = RTC_GetCounter(); + temp = timecount / 86400; + if (daycnt != temp) { + daycnt = temp; + temp1 = 1970; + while (temp >= 365) { + if (Is_Leap_Year (temp1)) { + if (temp >= 366) + temp -= 366; + else { + break; + } + } else + temp -= 365; + temp1++; + } + calendar.w_year = temp1; + temp1 = 0; + while (temp >= 28) { + if (Is_Leap_Year (calendar.w_year) && temp1 == 1) { + if (temp >= 29) + temp -= 29; + else + break; + } else { + if (temp >= mon_table[temp1]) + temp -= mon_table[temp1]; + else + break; + } + temp1++; + } + calendar.w_month = temp1 + 1; + calendar.w_date = temp + 1; + } + temp = timecount % 86400; + calendar.hour = temp / 3600; + calendar.min = (temp % 3600) / 60; + calendar.sec = (temp % 3600) % 60; + calendar.week = RTC_Get_Week (calendar.w_year, calendar.w_month, calendar.w_date); + return 0; +} + +/********************************************************************* + * @fn RTC_Init + * + * @brief Initializes RTC collection. + * + * @return 1 - Init Fail + * 0 - Init Success + */ +uint8_t RTC_Init (void) { + uint8_t temp = 0; + RCC_APB1PeriphClockCmd (RCC_APB1Periph_PWR | RCC_APB1Periph_BKP, ENABLE); + PWR_BackupAccessCmd (ENABLE); + RTC_ClearITPendingBit (RTC_IT_ALR); + RTC_ClearITPendingBit (RTC_IT_SEC); + + /* Is it the first configuration */ + + BKP_DeInit(); + RCC_LSEConfig (RCC_LSE_ON); + while (RCC_GetFlagStatus (RCC_FLAG_LSERDY) == RESET && temp < 250) { + temp++; + Delay_Ms(20); + } + if (temp >= 250) + return 1; + RCC_RTCCLKConfig (RCC_RTCCLKSource_LSE); + RCC_RTCCLKCmd (ENABLE); + RTC_WaitForLastTask(); + RTC_WaitForSynchro(); + RTC_ITConfig (RTC_IT_SEC, DISABLE); + RTC_ITConfig (RTC_IT_ALR, DISABLE); + RTC_ITConfig (RTC_IT_OW, DISABLE); + RTC_WaitForLastTask(); + RTC_EnterConfigMode(); + RTC_SetPrescaler (32767); + RTC_WaitForLastTask(); + //RTC_Set (2025, 9, 7, 11, 33, 30); /* Setup Time */ + RTC_Set_From_BuildTime(); + RTC_ExitConfigMode(); + BKP_WriteBackupRegister (BKP_DR1, 0XA1A1); + + RTC_NVIC_Config(); + RTC_Get(); + + return 0; +} \ No newline at end of file diff --git a/User/lib/rtc/rtc.h b/User/lib/rtc/rtc.h new file mode 100644 index 0000000..5851172 --- /dev/null +++ b/User/lib/rtc/rtc.h @@ -0,0 +1,95 @@ +#include "stdint.h" + +typedef struct +{ + volatile uint8_t hour; + volatile uint8_t min; + volatile uint8_t sec; + + volatile uint16_t w_year; + volatile uint8_t w_month; + volatile uint8_t w_date; + volatile uint8_t week; +} _calendar_obj; + +extern _calendar_obj calendar; + + +extern uint8_t const table_week[12]; +extern const uint8_t mon_table[12]; + +/********************************************************************* + * @fn RTC_NVIC_Config + * + * @brief Initializes RTC Int. + * + * @return none + */ +void RTC_NVIC_Config (void); +/********************************************************************* + * @fn Is_Leap_Year + * + * @brief Judging whether it is a leap year. + * + * @param year + * + * @return 1 - Yes + * 0 - No + */ +uint8_t Is_Leap_Year (uint16_t year); + +void RTC_Set_From_BuildTime(void); + +/********************************************************************* + * @fn RTC_Set + * + * @brief Set Time. + * + * @param Struct of _calendar_obj + * + * @return 1 - error + * 0 - success + */ +uint8_t RTC_Set (uint16_t syear, uint8_t smon, uint8_t sday, uint8_t hour, uint8_t min, uint8_t sec) ; + +/********************************************************************* + * @fn RTC_Alarm_Set + * + * @brief Set Alarm Time. + * + * @param Struct of _calendar_obj + * + * @return 1 - error + * 0 - success + */ +uint8_t RTC_Alarm_Set (uint16_t syear, uint8_t smon, uint8_t sday, uint8_t hour, uint8_t min, uint8_t sec) ; +/********************************************************************* + * @fn RTC_Get_Week + * + * @brief Get the current day of the week. + * + * @param year/month/day + * + * @return week + */ +uint8_t RTC_Get_Week (uint16_t year, uint8_t month, uint8_t day) ; + +/********************************************************************* + * @fn RTC_Get + * + * @brief Get current time. + * + * @return 1 - error + * 0 - success + */ +uint8_t RTC_Get (void) ; + +/********************************************************************* + * @fn RTC_Init + * + * @brief Initializes RTC collection. + * + * @return 1 - Init Fail + * 0 - Init Success + */ +uint8_t RTC_Init (void); \ No newline at end of file diff --git a/User/lib/telemetry/telemetry.c b/User/lib/telemetry/telemetry.c new file mode 100644 index 0000000..e69de29 diff --git a/User/lib/telemetry/telemetry.h b/User/lib/telemetry/telemetry.h new file mode 100644 index 0000000..447093b --- /dev/null +++ b/User/lib/telemetry/telemetry.h @@ -0,0 +1,93 @@ +#ifndef TELEMETRY_HEADER +#define TELEMETRY_HEADER + +#define TELEM_CHANNEL_SELF 1 // LPP data channel for 'self' device + +#define LPP_DIGITAL_INPUT 0 // 1 byte +#define LPP_DIGITAL_OUTPUT 1 // 1 byte +#define LPP_ANALOG_INPUT 2 // 2 bytes, 0.01 signed +#define LPP_ANALOG_OUTPUT 3 // 2 bytes, 0.01 signed +#define LPP_GENERIC_SENSOR 100 // 4 bytes, unsigned +#define LPP_LUMINOSITY 101 // 2 bytes, 1 lux unsigned +#define LPP_PRESENCE 102 // 1 byte, bool +#define LPP_TEMPERATURE 103 // 2 bytes, 0.1¡ãC signed +#define LPP_RELATIVE_HUMIDITY 104 // 1 byte, 0.5% unsigned +#define LPP_ACCELEROMETER 113 // 2 bytes per axis, 0.001G +#define LPP_BAROMETRIC_PRESSURE 115 // 2 bytes 0.1hPa unsigned +#define LPP_VOLTAGE 116 // 2 bytes 0.01V unsigned +#define LPP_CURRENT 117 // 2 bytes 0.001A unsigned +#define LPP_FREQUENCY 118 // 4 bytes 1Hz unsigned +#define LPP_PERCENTAGE 120 // 1 byte 1-100% unsigned +#define LPP_ALTITUDE 121 // 2 byte 1m signed +#define LPP_CONCENTRATION 125 // 2 bytes, 1 ppm unsigned +#define LPP_POWER 128 // 2 byte, 1W, unsigned +#define LPP_DISTANCE 130 // 4 byte, 0.001m, unsigned +#define LPP_ENERGY 131 // 4 byte, 0.001kWh, unsigned +#define LPP_DIRECTION 132 // 2 bytes, 1deg, unsigned +#define LPP_UNIXTIME 133 // 4 bytes, unsigned +#define LPP_GYROMETER 134 // 2 bytes per axis, 0.01 ¡ã/s +#define LPP_COLOUR 135 // 1 byte per RGB Color +#define LPP_GPS 136 // 3 byte lon/lat 0.0001 ¡ã, 3 bytes alt 0.01 meter +#define LPP_SWITCH 142 // 1 byte, 0/1 +#define LPP_POLYLINE 240 // 1 byte size, 1 byte delta factor, 3 byte lon/lat 0.0001¡ã * factor, n (size-8) bytes deltas + +// Only Data Size +#define LPP_DIGITAL_INPUT_SIZE 1 +#define LPP_DIGITAL_OUTPUT_SIZE 1 +#define LPP_ANALOG_INPUT_SIZE 2 +#define LPP_ANALOG_OUTPUT_SIZE 2 +#define LPP_GENERIC_SENSOR_SIZE 4 +#define LPP_LUMINOSITY_SIZE 2 +#define LPP_PRESENCE_SIZE 1 +#define LPP_TEMPERATURE_SIZE 2 +#define LPP_RELATIVE_HUMIDITY_SIZE 1 +#define LPP_ACCELEROMETER_SIZE 6 +#define LPP_BAROMETRIC_PRESSURE_SIZE 2 +#define LPP_VOLTAGE_SIZE 2 +#define LPP_CURRENT_SIZE 2 +#define LPP_FREQUENCY_SIZE 4 +#define LPP_PERCENTAGE_SIZE 1 +#define LPP_ALTITUDE_SIZE 2 +#define LPP_POWER_SIZE 2 +#define LPP_DISTANCE_SIZE 4 +#define LPP_ENERGY_SIZE 4 +#define LPP_DIRECTION_SIZE 2 +#define LPP_UNIXTIME_SIZE 4 +#define LPP_GYROMETER_SIZE 6 +#define LPP_GPS_SIZE 9 +#define LPP_SWITCH_SIZE 1 +#define LPP_CONCENTRATION_SIZE 2 +#define LPP_COLOUR_SIZE 3 +#define LPP_MIN_POLYLINE_SIZE 8 + + +// Multipliers +#define LPP_DIGITAL_INPUT_MULT 1 +#define LPP_DIGITAL_OUTPUT_MULT 1 +#define LPP_ANALOG_INPUT_MULT 100 +#define LPP_ANALOG_OUTPUT_MULT 100 +#define LPP_GENERIC_SENSOR_MULT 1 +#define LPP_LUMINOSITY_MULT 1 +#define LPP_PRESENCE_MULT 1 +#define LPP_TEMPERATURE_MULT 10 +#define LPP_RELATIVE_HUMIDITY_MULT 2 +#define LPP_ACCELEROMETER_MULT 1000 +#define LPP_BAROMETRIC_PRESSURE_MULT 10 +#define LPP_VOLTAGE_MULT 100 +#define LPP_CURRENT_MULT 1000 +#define LPP_FREQUENCY_MULT 1 +#define LPP_PERCENTAGE_MULT 1 +#define LPP_ALTITUDE_MULT 1 +#define LPP_POWER_MULT 1 +#define LPP_DISTANCE_MULT 1000 +#define LPP_ENERGY_MULT 1000 +#define LPP_DIRECTION_MULT 1 +#define LPP_UNIXTIME_MULT 1 +#define LPP_GYROMETER_MULT 100 +#define LPP_GPS_LAT_LON_MULT 10000 +#define LPP_GPS_ALT_MULT 100 +#define LPP_SWITCH_MULT 1 +#define LPP_CONCENTRATION_MULT 1 +#define LPP_COLOUR_MULT 1 + +#endif \ No newline at end of file diff --git a/User/main.c b/User/main.c new file mode 100644 index 0000000..665fb65 --- /dev/null +++ b/User/main.c @@ -0,0 +1,217 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : main.c + * Author : WCH + * Version : V1.0.0 + * Date : 2021/06/06 + * Description : Main program body. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ + +/* + *@Note + *task1 and task2 alternate printing + */ + +#include "ch32v30x_rng.h" +#include "meshcore/meshframing.h" +#include "meshcore/packets/advert.h" +#include "meshcore/packets/control.h" +#include "meshcore/packets/encrypted.h" +#include "meshcore/packets/group.h" + +#include "meshcore/packetstructs.h" +#include "sx1262.h" +#include "util/hexdump.h" +#include "util/log.h" +#include "string.h" +#include "meshcore/meshcore.h" +#include "lib/config.h" +#include "lib/rtc/rtc.h" +#include "lib/monocypher/monocypher-ed25519.h" +#include "meshcore/stats.h" +#include "lib/adc/temperature.h" + +#define TAG "MeshCore" + + +static TIM_TypeDef *runtimeTIM = TIM2; // use TIM2 for example + +void vConfigureTimerForRunTimeStats (void) { + TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure; + + // Reset the timer + TIM_DeInit (runtimeTIM); + + // Set timer for max period, upcounting + TIM_TimeBaseStructure.TIM_Prescaler = 72 - 1; // Assuming 72 MHz clock -> 1 MHz timer tick (1 ?s) + TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseStructure.TIM_Period = 0xFFFF; // Max 16-bit value + TIM_TimeBaseStructure.TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseStructure.TIM_RepetitionCounter = 0; + + TIM_TimeBaseInit (runtimeTIM, &TIM_TimeBaseStructure); + TIM_Cmd (runtimeTIM, ENABLE); +} + +uint32_t ulGetRunTimeCounterValue (void) { + return TIM_GetCounter (runtimeTIM); +} + +/********************************************************************* + * @fn task1_task + * + * @brief task1 program. + * + * @param *pvParameters - Parameters point of task1 + * + * @return none + */ + +// uint8_t bufIn[260]; + +uint8_t bootedUp = 0; + +/********************************************************************* + * @fn main + * + * @brief ; program. + * + * @return none + */ + +int main (void) { + + NVIC_PriorityGroupConfig (NVIC_PriorityGroup_2); + SystemCoreClockUpdate(); + Delay_Init(); + + + GPIO_InitTypeDef GPIO_InitStructure; + USART_InitTypeDef USART_InitStructure; + + RCC_APB2PeriphClockCmd (RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init (GPIOA, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_Init (GPIOA, &GPIO_InitStructure); + + USART_InitStructure.USART_BaudRate = 115200; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx; + + USART_Init (USART1, &USART_InitStructure); + USART_Cmd (USART1, ENABLE); + + printf("hello there"); + + + + MESH_LOGD (TAG, "SystemClk:%d\r\n", SystemCoreClock); + MESH_LOGD (TAG, "ChipID:%08x\r\n", DBGMCU_GetCHIPID()); + + while (1) { + // loadConfig(); + populateDefaults(); + + LoraApply(); + + ADC_Function_Init(); + RTC_Init(); + startupTime = RTC_GetCounter(); + memset (&stats, 0, sizeof (stats)); + + + /* + DiscoverRequestPayload discReq; + discReq.prefixOnly = 0; + discReq.since = 0; + discReq.tag = RTC_GetCounter(); + discReq.typeFilter = 0xFF; + sendDiscoverRequest (&discReq); + + */ + sendAdvert (0); + bootedUp = 1; + uint64_t ticker = 0; + + while (1) { + if (USART_GetFlagStatus (USART1, USART_FLAG_RXNE) == SET) { + char x; + x = USART_ReceiveData (USART1); + if (x == 'M') { + MESH_LOGI (TAG, "Sending message\n"); + char tempBuf[180]; + sniprintf (tempBuf, 180, "SySTick is %llu", ticker); + makeSendGroupMessage (tempBuf, 1); + } + if (x == '0') { + MESH_LOGI (TAG, "Sending zero hop advert\n"); + sendAdvert (0); + } + if (x == 'F') { + MESH_LOGI (TAG, "Sending flood advert\n"); + sendAdvert (1); + } + if (x == 'N') { + printNodeDB(); + } + if (x == 'D') { + PlainTextMessagePayload plainTextMessage; + plainTextMessage.timestamp = RTC_GetCounter(); + plainTextMessage.textType = 0; + plainTextMessage.attempt = 0; + snprintf (plainTextMessage.message, sizeof (plainTextMessage.message), "Sending message at SySTick is %llu", ticker); + iprintf ("Sending a direct message to the first node\n"); + sendEncryptedTextMessage (&(persistent.contacts[0]), &plainTextMessage); + } + if (x == 'C') { + for (uint8_t i = 0; i < ChannelCount; i++) { + Channel *channel = &(persistent.channels[i]); + if (strlen (channel->name) == 0) { + continue; + } + if (channel->timestamp == 0) { + continue; + } + iprintf ("Channel index %d, named %s, timestamp is %d, hash is %d\n", i, channel->name, channel->timestamp, channel->hash); + hexdump ("Pubkey", channel->key, sizeof (channel->key)); + } + } + } + + int8_t rssi, snr, rawsnr; + FrameStruct frame; + if (ReadFrame (&frame, &rssi, &snr, &rawsnr)) { + hexdump ("Whole frame", frame.payload, frame.payloadLen); + stats.lastSNR = rawsnr; + // stats.lastSNR = snr; //TODO figure out which to use + stats.lastRSSI = rssi; + MESH_LOGI (TAG, "rssi=%d[dBm] snr=%d[dB] rawsnr=%d[quarter dB]", rssi, snr, rawsnr); + // frame = decodeFrame (bufIn, rxLen); + processFrame (&frame); + if (persistent.doRepeat) { + retransmitFrame (&frame); + } + memset (&frame, 0, sizeof (FrameStruct)); // prepare for the next round + } + + int lost = GetPacketLost(); + if (lost != 0) { + MESH_LOGW (TAG, "%d packets lost", lost); + } + ticker++; + } + } +} diff --git a/User/meshcore/meshcore.c b/User/meshcore/meshcore.c new file mode 100644 index 0000000..ae2d643 --- /dev/null +++ b/User/meshcore/meshcore.c @@ -0,0 +1,79 @@ +#include "meshcore.h" +#include "lib/monocypher/monocypher-ed25519.h" +#include "meshcore/packets/advert.h" +#include "meshcore/packets/anonymous.h" +#include "meshcore/packets/control.h" +#include "meshcore/packets/encrypted.h" +#include "meshcore/packets/group.h" +#include "meshcore/stats.h" +#include "lib/base64.h" +#include "lib/cifra/aes.h" +#include "lib/cifra/sha2.h" +#include "lib/cifra/hmac.h" +#include "lib/config.h" +#include "meshframing.h" +#include "meshcore/packetstructs.h" + +#define TAG "MeshCore" + +// requires at least a 256 byte data + + +void processFrame (FrameStruct *frame) { + printframeHeader (frame); + if (frame->header & PAYLOAD_VERSION_3) { // more than the version 0 + MESH_LOGW (TAG, "Frame too new, got version %d instead of 0", (frame->header & PAYLOAD_VERSION_3) >> 6); + } + + unsigned char frameType = frame->header & PAYLOAD_TYPE_MASK; + + unsigned char index = 0; + + stats.packetsReceivedCount++; + + if ((frame->header & ROUTE_TYPE_MASK) == ROUTE_TYPE_FLOOD || + (frame->header & ROUTE_TYPE_MASK) == ROUTE_TYPE_TRANSPORT_FLOOD) { + stats.receivedFloodCount++; + } + + if ((frame->header & ROUTE_TYPE_MASK) == ROUTE_TYPE_DIRECT || + (frame->header & ROUTE_TYPE_MASK) == ROUTE_TYPE_TRANSPORT_DIRECT) { + stats.receivedDirectCount++; + } + + + if (frameType == PAYLOAD_TYPE_ANON_REQ) { + decodeAnonReq (frame); + + } else if (frameType == PAYLOAD_TYPE_PATH || frameType == PAYLOAD_TYPE_REQ || frameType == PAYLOAD_TYPE_RESPONSE || frameType == PAYLOAD_TYPE_TXT_MSG) { + iprintf (" Typexd: 0x%02X\n", frameType); + decodeEncryptedPayload (frame); + + } else if (frameType == PAYLOAD_TYPE_ACK) { + uint32_t checkSum = frame->payload[index++]; + checkSum |= frame->payload[index++] << 8; + checkSum |= frame->payload[index++] << 16; + checkSum |= frame->payload[index++] << 24; + // TODO add checking + + } else if (frameType == PAYLOAD_TYPE_ADVERT) { + decodeAdvertisement (frame); + } else if (frameType == PAYLOAD_TYPE_GRP_TXT || frameType == PAYLOAD_TYPE_GRP_DATA) { + decodeGroupMessage (frame); + } else if (frameType == PAYLOAD_TYPE_TRACE) { + + } else if (frameType == PAYLOAD_TYPE_MULTIPART) { + + } else if (frameType == PAYLOAD_TYPE_CONTROL) { + if (frame->path.pathLen == 0) { + decodeControlFrame (frame); + } + frame->header = 0xFF; + + } else if (frameType == PAYLOAD_TYPE_RAW_CUSTOM) { + // not implemented + } else { + stats.packetsReceivedCount--; + } + MESH_LOGD (TAG, "Processed frame"); +} diff --git a/User/meshcore/meshcore.h b/User/meshcore/meshcore.h new file mode 100644 index 0000000..011118f --- /dev/null +++ b/User/meshcore/meshcore.h @@ -0,0 +1,16 @@ +#ifndef MESHCORE_HEADER +#define MESHCORE_HEADER + +#include "packetstructs.h" +#include "string.h" +#include "sx1262.h" +#include "lib/cifra/aes.h" +#include "lib/cifra/sha2.h" +#include "lib/cifra/hmac.h" +#include "util/log.h" +#include +#include "stdio.h" + +void processFrame (FrameStruct *frame); + +#endif \ No newline at end of file diff --git a/User/meshcore/meshframing.c b/User/meshcore/meshframing.c new file mode 100644 index 0000000..0eec6c9 --- /dev/null +++ b/User/meshcore/meshframing.c @@ -0,0 +1,562 @@ +#include "meshframing.h" +#include "ch32v30x_gpio.h" +#include "lib/config.h" +#include "meshcore/stats.h" +#include "string.h" +#include "stdio.h" +#include "sx1262.h" +#include "util/hexdump.h" +#include "util/log.h" +#include "lib/cifra/sha2.h" + +#define TAG "Meshframing" + +int ReadFrame (FrameStruct *frame, int8_t *rssiPacket, int8_t *snrPacket, int8_t *rawSnr) { + uint16_t irqRegs = GetIrqStatus(); + // uint8_t status = GetStatus(); + + if (irqRegs & SX126X_IRQ_RX_DONE) { + // ClearIrqStatus(SX126X_IRQ_RX_DONE); + ClearIrqStatus (SX126X_IRQ_ALL); + + uint8_t offset = 0; + uint8_t payloadLength = 0; + GetRxBufferStatus (&payloadLength, &offset); + + if (payloadLength == 0) { + return 0; + } + + GetPacketStatus (rssiPacket, snrPacket, rawSnr); + + memset (frame, 0, sizeof (FrameStruct)); + WaitForIdle (BUSY_WAIT, "start ReadBuffer", 1); + + uint8_t cmd[3] = {SX126X_CMD_READ_BUFFER, offset, SX126X_CMD_NOP}; + + GPIO_WriteBit (GPIOA, GPIO_Pin_4, 0); + + uint16_t curPayloadIndex = 0; + uint8_t pathIndex = 0; + uint8_t transportIndex = 0; + uint8_t state = 0; // 0=header, 1=transport, 2=pathLen, 3=path, 4=payload + + for (uint16_t i = 0; i < payloadLength + sizeof (cmd); i++) { + uint8_t out = (i < sizeof (cmd)) ? cmd[i] : 0xFF; + + // Wait TX ready + while (!SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_TXE)); + SPI_I2S_SendData (SPI1, out); + + // Wait RX ready + while (!SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_RXNE)); + uint8_t in = (uint8_t)SPI_I2S_ReceiveData (SPI1); + + // Only process payload bytes + if (i >= sizeof (cmd)) { + switch (state) { + case 0: // header + frame->header = in; + state = ((frame->header & ROUTE_TYPE_MASK) == ROUTE_TYPE_TRANSPORT_DIRECT || + (frame->header & ROUTE_TYPE_MASK) == ROUTE_TYPE_TRANSPORT_FLOOD) + ? 1 + : 2; + break; + + case 1: // transportCodes[4] + frame->transportCodes[transportIndex++] = in; + if (transportIndex >= 4) + state = 2; + break; + + case 2: // pathLen + frame->path.pathLen = in; + if (frame->path.pathLen > 64) { + frame->path.pathLen = 64; + } + pathIndex = 0; + state = (frame->path.pathLen > 0) ? 3 : 4; + break; + + case 3: // path + frame->path.path[pathIndex++] = in; + if (pathIndex >= frame->path.pathLen) + state = 4; + break; + + case 4: // payload + frame->payload[curPayloadIndex++] = in; + break; + } + } + } + + frame->payloadLen = curPayloadIndex; + + GPIO_WriteBit (GPIOA, GPIO_Pin_4, 1); + + WaitForIdle (BUSY_WAIT, "end ReadBuffer", 0); + return payloadLength; + } + return 0; +} + +/* +FrameStruct decodeFrame (unsigned char *data, unsigned char dataLen) { + FrameStruct frame; + memset (&frame, 0, sizeof (frame)); + unsigned char index = 0; + frame.header = data[index++]; + if ((frame.header & ROUTE_TYPE_MASK) == ROUTE_TYPE_TRANSPORT_DIRECT || + (frame.header & ROUTE_TYPE_MASK) == ROUTE_TYPE_TRANSPORT_FLOOD) { + memcpy (frame.transportCodes, data + index, 4); + index += 4; + } + frame.path.pathLen = data[index++]; + + memcpy (frame.path.path, data + index, frame.path.pathLen); + index += frame.path.pathLen; + frame.payloadLen = dataLen - index; + memcpy (frame.payload, data + index, frame.payloadLen); + + return frame; +} +*/ +void printframeHeader (const FrameStruct *frame) { + switch (frame->header & ROUTE_TYPE_MASK) { + case ROUTE_TYPE_TRANSPORT_FLOOD: + iprintf ("transport flood"); + break; + + case ROUTE_TYPE_FLOOD: + iprintf ("flood"); + break; + + case ROUTE_TYPE_DIRECT: + iprintf ("direct"); + break; + + case ROUTE_TYPE_TRANSPORT_DIRECT: + iprintf ("transport direct"); + break; + } + + iprintf (", payload type is "); + + switch (frame->header & PAYLOAD_TYPE_MASK) { + case PAYLOAD_TYPE_REQ: + iprintf ("request"); + break; + + case PAYLOAD_TYPE_RESPONSE: + iprintf ("response"); + break; + + case PAYLOAD_TYPE_TXT_MSG: + iprintf ("text message"); + break; + + case PAYLOAD_TYPE_ACK: + iprintf ("acknowledgement"); + break; + + case PAYLOAD_TYPE_ADVERT: + iprintf ("advert"); + break; + + case PAYLOAD_TYPE_GRP_TXT: + iprintf ("group text"); + break; + + case PAYLOAD_TYPE_GRP_DATA: + iprintf ("group data"); + break; + + case PAYLOAD_TYPE_ANON_REQ: + iprintf ("anon request"); + break; + + case PAYLOAD_TYPE_PATH: + iprintf ("path"); + break; + + case PAYLOAD_TYPE_TRACE: + iprintf ("trace"); + break; + + case PAYLOAD_TYPE_MULTIPART: + iprintf ("multipart"); + break; + + case PAYLOAD_TYPE_CONTROL: + iprintf ("control"); + break; + + case PAYLOAD_TYPE_RAW_CUSTOM: + iprintf ("raw"); + break; + } + char version[2]; + version[0] = (frame->header >> 6) + '0'; + version[1] = 0; + + iprintf (", payload version is %s ", version); + + if ((frame->header & ROUTE_TYPE_MASK) == ROUTE_TYPE_TRANSPORT_DIRECT || + (frame->header & ROUTE_TYPE_MASK) == ROUTE_TYPE_TRANSPORT_FLOOD) { + iprintf ("Transport codes: %d %d\n", *((uint16_t *)frame->transportCodes), + *((uint16_t *)&(frame->transportCodes[2]))); + } + iprintf ("Path is %d nodes long", frame->path.pathLen); + + for (uint8_t pathIndex = 0; pathIndex < frame->path.pathLen; pathIndex++) { + iprintf ("node %d - %02X, ", pathIndex, frame->path.path[pathIndex]); + } + putchar ('\n'); +} + +void LoRaTransmit (const FrameStruct *frame) { + addToNotReTX(frame); + uint16_t len = 2; // header + path_len + + if ( + ((frame->header & ROUTE_TYPE_MASK) == ROUTE_TYPE_TRANSPORT_DIRECT) || + ((frame->header & ROUTE_TYPE_MASK) == ROUTE_TYPE_TRANSPORT_FLOOD) + ) { + len += 4; + } + + len += frame->path.pathLen; + len += frame->payloadLen; + + if (len > 255) { + MESH_LOGE(TAG, "%d is too big for sx1262", len); + } + + uint16_t irqStatus; + char rv = 0; + + size_t outCounter = 0; + + if (txActive == 0) { + txActive = 1; + + if (PacketParams[2] == 0x00) { // explicit header, variable length + PacketParams[3] = len; + } + + WriteCommand (SX126X_CMD_SET_PACKET_PARAMS, PacketParams, 6); + ClearIrqStatus (SX126X_IRQ_ALL); + + WaitForIdle (BUSY_WAIT, "start WriteBuffer", 1); + + uint8_t cmdBuf[2] = {SX126X_CMD_WRITE_BUFFER, 0x00}; + uint8_t cmdLen = sizeof (cmdBuf); + + GPIO_WriteBit (GPIOA, GPIO_Pin_4, 0); + + uint16_t payloadIndex = 0; + uint8_t state = 0; + uint8_t pathIndex = 0; + uint8_t transportIndex = 0; + + for (uint16_t i = 0; i < len + cmdLen; i++) { + uint8_t out = 0xFF; + + if (i < cmdLen) { + out = cmdBuf[i]; + } else { + switch (state) { + case 0: // header + out = frame->header; + outCounter = 0; + state = ((frame->header & ROUTE_TYPE_MASK) == ROUTE_TYPE_TRANSPORT_DIRECT || + (frame->header & ROUTE_TYPE_MASK) == ROUTE_TYPE_TRANSPORT_FLOOD) + ? 1 + : 2; + break; + + case 1: // transport codes + out = frame->transportCodes[transportIndex++]; + if (transportIndex >= 4) + state = 2; + break; + + case 2: // path length + out = frame->path.pathLen; + pathIndex = 0; + state = (frame->path.pathLen > 0) ? 3 : 4; + break; + + case 3: // path + out = frame->path.path[pathIndex++]; + if (pathIndex >= frame->path.pathLen) + state = 4; + break; + + case 4: // payload + out = frame->payload[payloadIndex++]; + break; + } + } + + while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_TXE) == RESET); + outCounter++; + SPI_I2S_SendData (SPI1, out); + + while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_RXNE) == RESET); + (void)SPI_I2S_ReceiveData (SPI1); // discard + } + + GPIO_WriteBit (GPIOA, GPIO_Pin_4, 1); + + WaitForIdle (BUSY_WAIT, "end WriteBuffer", 0); + + MESH_LOGD(TAG, + "TX payloadLen=%u pathLen=%u totalLen=%u header=0x%02X", + frame->payloadLen, + frame->path.pathLen, + len, + frame->header); + + + MESH_LOGD(TAG, "Starting tx mode, sent %d, should %d", outCounter, len); + + SetTx (3000); + + MESH_LOGD(TAG, "SetTx running"); + + irqStatus = GetIrqStatus(); + while (!(irqStatus & (SX126X_IRQ_TX_DONE | SX126X_IRQ_TIMEOUT))) { + Delay_Ms(10); + irqStatus = GetIrqStatus(); + if (debugPrint) { + MESH_LOGD(TAG, "irq: 0x%04X", irqStatus); + } + } + + MESH_LOGD(TAG, "Finished tx"); + txActive = 0; + SetRx (0xFFFFFF); + + if (irqStatus & SX126X_IRQ_TX_DONE) { + rv = 1; + } + } + + if (rv == 0) { + txLost++; + } +} + +/* +void sendFrame (const FrameStruct *frame) { + uint8_t txBuf[256]; + size_t offset = 0; + + txBuf[offset++] = frame->header; + + if ((frame->header & ROUTE_TYPE_MASK) == ROUTE_TYPE_TRANSPORT_DIRECT || + (frame->header & ROUTE_TYPE_MASK) == ROUTE_TYPE_TRANSPORT_FLOOD) { + memcpy (txBuf + offset, frame->transportCodes, 4); + offset += 4; + } + + if ((frame->header & ROUTE_TYPE_MASK) == ROUTE_TYPE_FLOOD || + (frame->header & ROUTE_TYPE_MASK) == ROUTE_TYPE_TRANSPORT_FLOOD) { + stats.sentFloodCount++; + } + + if ((frame->header & ROUTE_TYPE_MASK) == ROUTE_TYPE_DIRECT || + (frame->header & ROUTE_TYPE_MASK) == ROUTE_TYPE_TRANSPORT_DIRECT) { + stats.sentDirectCount++; + } + + stats.packetsSentCount++; + + uint8_t pathLen = frame->path.pathLen; + + + if (pathLen > 64) { + pathLen = 64; + } + + txBuf[offset++] = pathLen; + + memcpy (txBuf + offset, frame->path.path, pathLen); + hexdump ("TxDump Path", frame->path.path, frame->path.pathLen); + offset += pathLen; + + uint16_t maxPayloadLen = 256 - offset; + + uint16_t payloadLen = frame->payloadLen > maxPayloadLen ? maxPayloadLen : frame->payloadLen; + + memcpy (txBuf + offset, frame->payload, payloadLen); + offset += payloadLen; + + + hexdump ("TxDump", txBuf, offset); + hexdump ("TxDumpPayload", frame->payload, frame->payloadLen); + TickType_t start, end; + start = xTaskGetTickCount(); + LoRaSend (txBuf, offset, SX126x_TXMODE_SYNC); + end = xTaskGetTickCount(); + tickAirtime += end - start; +} +*/ + +KnownPacketHistoryType dontReTXHistory[NON_RETX_HISTORY]; +uint8_t dontReTXHistoryIndex = 0; + +void getFrameHash(const FrameStruct *frame, uint8_t *hash) { + cf_sha256_context ctx; + + // 1. Initialize + cf_sha256_init (&ctx); + + // 2. Feed in your data + cf_sha256_update (&ctx, frame->payload, frame->payloadLen); + + // 3. Compute digest + cf_sha256_digest (&ctx, hash); +} + +void addToNotReTX(const FrameStruct *frame) { + KnownPacketHistoryType * knownHist = &(dontReTXHistory[dontReTXHistoryIndex]); + + getFrameHash(frame, knownHist->hash); + knownHist->populated = 1; + + dontReTXHistoryIndex++; + if (dontReTXHistoryIndex >= NON_RETX_HISTORY) { + dontReTXHistoryIndex = 0; + } +} + +void retransmitFrame (FrameStruct *frame) { + + uint8_t hashTmp[CF_SHA256_HASHSZ]; + getFrameHash(frame, hashTmp); + + uint8_t found = 0; + for (uint8_t i = 0; i < NON_RETX_HISTORY; i++) { + KnownPacketHistoryType * knownHist = &(dontReTXHistory[dontReTXHistoryIndex]); + if (knownHist->populated == 0) { + continue; + } + if (memcmp(knownHist->hash, hashTmp, CF_SHA256_HASHSZ) == 0) { + found = 1; + break; + } + } + if (found) { + return; + } + + /* -------- FLOOD -------- */ + if (frame->header & ROUTE_TYPE_FLOOD || + frame->header & ROUTE_TYPE_TRANSPORT_FLOOD) { + + if (frame->header != DONT_RETRANSMIT_HEADER && + frame->path.pathLen + 1 < MAX_FLOOD_TTL) { + + // append self to END of path + frame->path.path[frame->path.pathLen++] = persistent.pubkey[0]; + LoRaTransmit (frame); + } + } + + /* -------- DIRECT -------- */ + if (frame->header & ROUTE_TYPE_DIRECT || + frame->header & ROUTE_TYPE_TRANSPORT_DIRECT) { + + // are we the next hop? + if (frame->path.pathLen > 0 && + frame->path.path[0] == persistent.pubkey[0]) { + + // remove self from START of path + frame->path.pathLen--; + memmove (frame->path.path, + frame->path.path + 1, + frame->path.pathLen); + + // forward only if there's another hop + if (frame->path.pathLen > 0) { + LoRaTransmit (frame); + } + } + } +} + +// Verify MAC + Decrypt + +int encrypt_then_mac (const uint8_t *aes_key, const uint8_t keySize, const uint8_t *plaintext, size_t plen, uint8_t *output, size_t *olen) { + if (plen == 0) + return -1; + + size_t padded_len = ((plen + 15) / 16) * 16; + + // prepare padded buffer + uint8_t padded[padded_len]; + memset (padded, 0, padded_len); // zero padding + memcpy (padded, plaintext, plen); // copy plaintext + + // ciphertext will go right after HMAC + uint8_t *ciphertext = output + HMAC_SIZE; + + // encrypt plaintext + aes_encrypt_ecb (aes_key, 16, padded, padded_len, ciphertext); + + // compute HMAC over ciphertext + uint8_t mac[32]; // full SHA-256 + hmac_sha256 (aes_key, keySize, ciphertext, padded_len, mac); + + // copy only HMAC_SIZE bytes of MAC + memcpy (output, mac, HMAC_SIZE); + + // return total length = HMAC + ciphertext + *olen = HMAC_SIZE + padded_len; + return 0; +} + +int mac_then_decrypt (const uint8_t *aes_key, const uint8_t keySize, const uint8_t *input, size_t ilen, uint8_t *plaintext) { + if (ilen <= HMAC_SIZE) + return -1; + + const uint8_t *mac = input; + const uint8_t *ciphertext = input + HMAC_SIZE; + size_t clen = ilen - HMAC_SIZE; + + if (clen % 16 != 0) + return -2; // must be multiple of block size + + uint8_t calc_mac[32]; // full SHA-256 + hmac_sha256 (aes_key, keySize, ciphertext, clen, calc_mac); + + if (memcmp (mac, calc_mac, HMAC_SIZE) != 0) + return -2; + + return aes_decrypt_ecb (aes_key, 16, ciphertext, clen, plaintext); +} + +uint16_t getTransportCode (const FrameStruct *frame) { + uint16_t code; + /* + // compute HMAC over ciphertext + uint8_t mac[32]; // full SHA-256 + cf_hmac_ctx ctx; + cf_hmac_init (&ctx, &cf_sha256, key, sizeof(key)); + cf_hmac_update (&ctx, &(frame->header), sizeof (frame->header)); + cf_hmac_update (&ctx, frame->payload, frame->payloadLen); + cf_hmac_finish (&ctx, mac); + + // copy only HMAC_SIZE bytes of MAC + memcpy (&code, mac, HMAC_SIZE); + */ + if (code == 0) { // reserve codes 0000 and FFFF + code++; + } else if (code == 0xFFFF) { + code--; + } + return code; +} \ No newline at end of file diff --git a/User/meshcore/meshframing.h b/User/meshcore/meshframing.h new file mode 100644 index 0000000..0b346a3 --- /dev/null +++ b/User/meshcore/meshframing.h @@ -0,0 +1,46 @@ +#ifndef MESHCORE_FRAME_HEADER +#define MESHCORE_FRAME_HEADER + +#include "stddef.h" +#include "stdint.h" +#include "lib/cifra/aes.h" +#include "lib/cifra/hmac.h" +#include "packetstructs.h" + + +#define KEY_SIZE 16 // 128-bit AES +#define HMAC_SIZE 2 // meshcore size +#define MAX_FLOOD_TTL 64 +//#define NON_RETX_HISTORY 64 +#define NON_RETX_HISTORY 8 + +int ReadFrame (FrameStruct *frame, int8_t *rssiPacket, int8_t *snrPacket, int8_t *rawSnr); + +void LoRaTransmit (const FrameStruct *frame); + +/* +FrameStruct decodeFrame (unsigned char *data, unsigned char dataLen); + +void sendFrame (const FrameStruct * frame); +*/ + +void printFrameHeader (const FrameStruct *frame); + +// CALL LAST, PATH GETS MODIFIED +void retransmitFrame (FrameStruct *frame); + +// Verify MAC + Decrypt + +int encrypt_then_mac (const uint8_t *aes_key, const uint8_t keySize, const uint8_t *plaintext, size_t plen, uint8_t *output, size_t *olen); + +int mac_then_decrypt (const uint8_t *aes_key, const uint8_t keySize, const uint8_t *input, size_t ilen, uint8_t *plaintext); + +void addToNotReTX(const FrameStruct *frame); + +typedef struct KnownPacketHistoryType { + uint8_t hash[32]; + uint8_t populated; +} KnownPacketHistoryType; + + +#endif \ No newline at end of file diff --git a/User/meshcore/packets/ack.c b/User/meshcore/packets/ack.c new file mode 100644 index 0000000..2aff951 --- /dev/null +++ b/User/meshcore/packets/ack.c @@ -0,0 +1,43 @@ +#include "ack.h" +#include "lib/cifra/sha2.h" +#include "lib/config.h" +#include "meshcore/meshframing.h" +#include + +#define TAG "Ack" + +void sendDiscreteAck (uint8_t *data, const uint8_t len, uint8_t *senderPubKey) { + FrameStruct frame; + frame.path.pathLen = 0; + memset (&frame, 0, sizeof (frame)); + + // 1. Header + frame.header = + ROUTE_TYPE_FLOOD | // currently flood + PAYLOAD_TYPE_ACK | + PAYLOAD_VERSION_0; + + // Buffer for the digest + uint8_t hash[CF_SHA256_HASHSZ]; + + // Context + cf_sha256_context ctx; + + // 1. Initialize + cf_sha256_init (&ctx); + + // 2. Feed in your data + cf_sha256_update (&ctx, data, len); + + cf_sha256_update (&ctx, senderPubKey, sizeof (persistent.pubkey)); + + // 3. Compute digest + cf_sha256_digest (&ctx, hash); + + memcpy (frame.payload, hash, 4); + // 5. Finalize + frame.payloadLen = 4; + + + LoRaTransmit (&frame); +} \ No newline at end of file diff --git a/User/meshcore/packets/ack.h b/User/meshcore/packets/ack.h new file mode 100644 index 0000000..916d663 --- /dev/null +++ b/User/meshcore/packets/ack.h @@ -0,0 +1,8 @@ +#ifndef ACK_HEADER +#define ACK_HEADER + +#include "meshcore/packetstructs.h" + +void sendDiscreteAck (uint8_t *data, const uint8_t len, uint8_t *senderPubKey); + +#endif \ No newline at end of file diff --git a/User/meshcore/packets/advert.c b/User/meshcore/packets/advert.c new file mode 100644 index 0000000..617f80e --- /dev/null +++ b/User/meshcore/packets/advert.c @@ -0,0 +1,302 @@ +#include "ch32v30x_rtc.h" +#include "lib/config.h" +#include "lib/monocypher/monocypher-ed25519.h" +#include "meshcore/meshframing.h" +#include "meshcore/packetstructs.h" +#include +#include "advert.h" +#include "util/hexdump.h" +#include "lib/base64.h" +#include "util/log.h" + +#define TAG "Advert" + +static void build_ad_message (const FrameStruct *frame, + uint8_t *out, + size_t *out_len) { + size_t idx = 0; + + // pubkey + timestamp (your 36 bytes) + memcpy (out + idx, frame->payload, 36); + idx += 36; + + // rest of payload after signature region + memcpy (out + idx, + &frame->payload[100], + frame->payloadLen - 100); + + idx += (frame->payloadLen - 100); + + *out_len = idx; +} + +void ed25519_sign_ad (FrameStruct *frame) { + uint8_t *signature = &frame->payload[36]; + + uint8_t message[256]; + size_t m = 0; + + // pubkey + timestamp (0..35) + memcpy (message + m, frame->payload, 36); + m += 36; + + // skip signature [36..99] + + // payload after signature + memcpy (message + m, + frame->payload + 100, + frame->payloadLen - 100); + m += frame->payloadLen - 100; + + crypto_ed25519_sign (signature, + persistent.privkey, + message, + m); +} + +int ed25519_verify_ad (const FrameStruct *frame) { + const uint8_t *signature = &frame->payload[36]; + + uint8_t message[256]; + size_t m = 0; + + if (signature[63] & 224) + return 0; + + // pubkey + timestamp + memcpy (message + m, frame->payload, 36); + m += 36; + + // skip signature [36..99] + + // payload after signature + memcpy (message + m, + frame->payload + 100, + frame->payloadLen - 100); + m += frame->payloadLen - 100; + + return crypto_ed25519_check (signature, + frame->payload, // pubkey at start + message, + m) == 0; +} + +void sendAdvert (uint8_t shouldFlood) { + FrameStruct frame; + size_t offset = 0; + + frame.header = (shouldFlood ? ROUTE_TYPE_FLOOD : ROUTE_TYPE_DIRECT) | PAYLOAD_TYPE_ADVERT | PAYLOAD_VERSION_0; + + /* ---- public key ---- */ + memcpy (frame.payload + offset, persistent.pubkey, 32); + offset += 32; + + /* ---- timestamp ---- */ + uint32_t timestamp = RTC_GetCounter(); + memcpy (frame.payload + offset, ×tamp, sizeof (timestamp)); + offset += sizeof (timestamp); + + /* ---- reserve signature ---- */ + uint8_t *signature_pos = frame.payload + offset; + offset += 64; + + /* ---- build app data directly into payload ---- */ + size_t app_start = offset; + + uint8_t dataFlags = ADVERTISEMENT_FLAG_HAS_NAME; + if (persistent.nodeType == NODE_TYPE_CHAT_NODE) + dataFlags |= ADVERTISEMENT_FLAG_IS_CHAT_NODE; + else if (persistent.nodeType == NODE_TYPE_REPEATER) + dataFlags |= ADVERTISEMENT_FLAG_IS_REAPEATER; + else if (persistent.nodeType == NODE_TYPE_ROOM_SERVER) + dataFlags |= ADVERTISEMENT_FLAG_IS_ROOM_SERVER; + else if (persistent.nodeType == NODE_TYPE_SENSOR) + dataFlags |= ADVERTISEMENT_FLAG_IS_SENSOR; + + frame.payload[offset++] = dataFlags; + + if (dataFlags & ADVERTISEMENT_FLAG_HAS_LOCATION) { + memcpy (frame.payload + offset, &persistent.latitude, sizeof (persistent.latitude)); + offset += sizeof (persistent.latitude); + + memcpy (frame.payload + offset, &persistent.longitude, sizeof (persistent.longitude)); + offset += sizeof (persistent.longitude); + } + /* + + if (dataFlags & ADVERTISEMENT_FLAG_RFU1) { + memcpy(frame.payload + offset, &persistent.rfu1, sizeof(persistent.rfu1)); + offset += sizeof(persistent.rfu1); + } + + if (dataFlags & ADVERTISEMENT_FLAG_RFU2) { + memcpy(frame.payload + offset, &persistent.rfu2, sizeof(persistent.rfu2)); + offset += sizeof(persistent.rfu2); + } + */ + + if (dataFlags & ADVERTISEMENT_FLAG_HAS_NAME) { + size_t nameLen = strlen (persistent.nodeName); + memcpy (frame.payload + offset, persistent.nodeName, nameLen); + offset += nameLen; + } + + size_t app_len = offset - app_start; + + frame.payloadLen = offset; + /* ---- sign directly over payload ---- */ + ed25519_sign_ad (&frame); + + /* ---- debug ---- */ + hexdump ("Public key", frame.payload, 32); + hexdump ("Signature", signature_pos, 64); + hexdump ("Appdata", frame.payload + app_start, app_len); + iprintf ("Timestamp is %lu\n", timestamp); + iprintf ("NodeName %s\n", persistent.nodeName); + + /* ---- send ---- */ + frame.payloadLen = offset; + frame.path.pathLen = 0; + LoRaTransmit (&frame); +} + +void decodeAdvertisement (const FrameStruct *frame) { + AdvertisementPayload advert; + memset (&advert, 0, sizeof (advert)); + + advert.valid = 0; + if (frame->payloadLen < 101) { + MESH_LOGW (TAG, "Advertisement frame too short (%d < 101)", frame->payloadLen); + return; + } + + if (!ed25519_verify_ad (frame)) { + MESH_LOGW (TAG, "Incorrect signature"); + return; + } else { + MESH_LOGI (TAG, "Advertisement signature ok."); + } + advert.valid = 1; + + unsigned char index = 0; + + memcpy (advert.pubKey, frame->payload + index, 32); + index += 32; + + memcpy (&advert.timestamp, frame->payload + index, 4); + index += 4; + + memcpy (advert.signature, frame->payload + index, 64); + index += 64; + + advert.dataFlags = frame->payload[index++]; + + uint8_t expectedLen = 101; + + if (advert.dataFlags & ADVERTISEMENT_FLAG_HAS_LOCATION) { + expectedLen += 8; + } + + if (advert.dataFlags & ADVERTISEMENT_FLAG_RFU1) { + expectedLen += 2; + } + if (advert.dataFlags & ADVERTISEMENT_FLAG_RFU2) { + expectedLen += 2; + } + + if (frame->payloadLen < expectedLen) { + MESH_LOGW (TAG, "Advertisement frame with data too short (%d < %d)", frame->payloadLen, expectedLen); + return; + } + + if (advert.dataFlags & ADVERTISEMENT_FLAG_HAS_LOCATION) { + memcpy (&advert.latitude, frame->payload + index, 4); + index += 4; + memcpy (&advert.longitude, frame->payload + index, 4); + index += 4; + } + + if (advert.dataFlags & ADVERTISEMENT_FLAG_RFU1) { + memcpy (&advert.rfu1, frame->payload + index, 2); + index += 2; + } + if (advert.dataFlags & ADVERTISEMENT_FLAG_RFU2) { + memcpy (&advert.rfu2, frame->payload + index, 2); + index += 2; + } + unsigned char nameLen = frame->payloadLen - index; + + if (nameLen > 31) { + nameLen = 31; // leave space for null + } + memcpy (advert.nodeName, frame->payload + index, nameLen); + advert.nodeName[nameLen] = 0; + + + printAdvertisement (&advert); + saveAdvert (&advert); +} + +void saveAdvert (const AdvertisementPayload *advert) { + NodeEntry *node = getNode (advert->pubKey[0]); + + if (node == NULL) { + node = getNextNode(); + memset (node, 0, sizeof (NodeEntry)); + } + + memcpy (node->name, advert->nodeName, sizeof (node->name)); + memcpy (node->pubKey, advert->pubKey, sizeof (node->pubKey)); + + // ------------------------------- + // Ed25519 ¡ú X25519 conversion + // ------------------------------- + uint8_t peer_x[32]; + crypto_eddsa_to_x25519 (peer_x, advert->pubKey); + + // ------------------------------- + // IMPORTANT: derive correct scalar + // (THIS fixes your HMAC mismatch) + // ------------------------------- + uint8_t scalar[64]; + uint8_t scalarOut[32]; + + crypto_sha512 (scalar, persistent.privkey, 32); + crypto_eddsa_trim_scalar (scalarOut, scalar); + + // ------------------------------- + // X25519 Diffie-Hellman + // ------------------------------- + crypto_x25519 (node->secret, + scalarOut, + peer_x); + + + node->gps_latitude = advert->latitude; + node->gps_longitude = advert->longitude; + + // add path + + node->type = advert->dataFlags & 0x0F; + node->last_seen_lt = RTC_GetCounter(); + node->last_seen_rt = advert->timestamp; +} + +void printAdvertisement (const AdvertisementPayload *advert) { + iprintf ( + "%s on %ld with type %s on %s location %ld %ld\n", + advert->dataFlags & ADVERTISEMENT_FLAG_HAS_NAME + ? advert->nodeName + : "nameless node", + advert->timestamp, + (advert->dataFlags & 0x07) == 0x04 ? "sensor" + : (advert->dataFlags & 0x07) == 0x03 ? "room server" + : (advert->dataFlags & 0x07) == 0x02 ? "repeater" + : "chat node", + advert->dataFlags & 0x80 ? "known" : "unknown", + advert->latitude, + advert->longitude); + + hexdump ("Public key", advert->pubKey, 32); + hexdump ("Signature", advert->signature, 64); +} diff --git a/User/meshcore/packets/advert.h b/User/meshcore/packets/advert.h new file mode 100644 index 0000000..263dd1d --- /dev/null +++ b/User/meshcore/packets/advert.h @@ -0,0 +1,14 @@ +#ifndef ADVERT_HEADER +#define ADVERT_HEADER + +#include "meshcore/packetstructs.h" + +void sendAdvert (uint8_t shouldFlood); + +void decodeAdvertisement (const FrameStruct *frame); + +void printAdvertisement (const AdvertisementPayload *advert); + +void saveAdvert (const AdvertisementPayload *advert); + +#endif \ No newline at end of file diff --git a/User/meshcore/packets/anonymous.c b/User/meshcore/packets/anonymous.c new file mode 100644 index 0000000..40fb979 --- /dev/null +++ b/User/meshcore/packets/anonymous.c @@ -0,0 +1,234 @@ +#include "ch32v30x_rtc.h" +#include "lib/config.h" +#include "lib/monocypher/monocypher-ed25519.h" +#include "meshcore/meshframing.h" +#include "meshcore/packets/encrypted.h" +#include "meshcore/packetstructs.h" +#include "anonymous.h" +#include "util/hexdump.h" +#include + +#define TAG "Anonymous" + +void sendAnonymousRequest (const NodeEntry *targetNode, const uint8_t *password, uint32_t sync) { + uint8_t passwordLen = strlen ((const char *)password); + FrameStruct frame; + frame.path.pathLen = 0; + uint8_t offset = 0; + + // 1. Frame header + frame.header = ((targetNode->path.pathLen > 0) ? ROUTE_TYPE_DIRECT : ROUTE_TYPE_FLOOD) | PAYLOAD_TYPE_ANON_REQ | PAYLOAD_VERSION_0; + + // 2. Payload header (unencrypted) + frame.payload[offset++] = targetNode->pubKey[0]; + + memcpy (frame.payload + offset, persistent.pubkey, 32); + offset += 32; + + // 3. Build plaintext payload + uint8_t plaintext[32]; + uint8_t p = 0; + + uint32_t last_seen_rt = RTC_GetCounter(); + plaintext[p++] = (last_seen_rt >> 0) & 0xFF; + plaintext[p++] = (last_seen_rt >> 8) & 0xFF; + plaintext[p++] = (last_seen_rt >> 16) & 0xFF; + plaintext[p++] = (last_seen_rt >> 24) & 0xFF; + + if (targetNode->type == NODE_TYPE_ROOM_SERVER) { + plaintext[p++] = (sync >> 0) & 0xFF; + plaintext[p++] = (sync >> 8) & 0xFF; + plaintext[p++] = (sync >> 16) & 0xFF; + plaintext[p++] = (sync >> 24) & 0xFF; + } + + if (passwordLen > 16) { + passwordLen = 16; + } + memcpy (plaintext + p, password, passwordLen); + p += passwordLen; + + size_t outputLen; + // 4. Encrypt + MAC + encrypt_then_mac ( + targetNode->secret, + 32, + plaintext, + p, + frame.payload + offset, + &outputLen); + + offset += outputLen; + + // 5. Finalize and send + frame.payloadLen = offset; + memcpy (&(frame.path), &(targetNode->path), sizeof (frame.path)); + + hexdump ("Anon payload", frame.payload, frame.payloadLen); + + LoRaTransmit (&frame); +} + +void printAnonRequest (const AnonymousRequestPayload *req, int isRoomServer) { + if (!req) + return; + + iprintf ("AnonymousRequestPayload at %p\n", (void *)req); + iprintf (" destination hash: 0x%02X\n", req->destinationHash); + + iprintf (" sender pubKey: "); + for (int i = 0; i < sizeof (req->pubKey); i++) { + iprintf ("%02X", req->pubKey[i]); + } + iprintf ("\n"); + + iprintf (" cipher MAC: 0x%04X\n", req->cipherMAC); + + iprintf (" decrypted payload (%u bytes):\n", req->payloadLen); + uint8_t index = 0; + + // timestamp (first 4 bytes) + if (req->payloadLen >= 4) { + uint32_t timestamp = req->payload[index++]; + timestamp |= req->payload[index++] << 8; + timestamp |= req->payload[index++] << 16; + timestamp |= req->payload[index++] << 24; + iprintf (" timestamp: %u\n", timestamp); + } + + // room server sync timestamp + if (isRoomServer && req->payloadLen >= index + 4) { + uint32_t syncTimestamp = req->payload[index++]; + syncTimestamp |= req->payload[index++] << 8; + syncTimestamp |= req->payload[index++] << 16; + syncTimestamp |= req->payload[index++] << 24; + iprintf (" sync timestamp: %u\n", syncTimestamp); + } + + + // remaining bytes = password + if (index < req->payloadLen) { + uint8_t passwordLen = req->payloadLen - index; + if (passwordLen > 16) + passwordLen = 16; + passwordLen = strnlen (&(req->payload[index]), passwordLen); + iprintf (" password: "); + for (uint8_t i = 0; i < passwordLen; i++) { + iprintf ("%c", req->payload[i + index]); + } + iprintf ("\n"); + } +} + +size_t strnlen (const char *s, size_t maxLen) { + size_t len = 0; + while (len < maxLen && s[len] != '\0') { + len++; + } + return len; +} + +void decodeAnonReq (const FrameStruct *frame) { + uint8_t index = 0; + AnonymousRequestPayload anonReq; + + anonReq.destinationHash = frame->payload[index++]; + memcpy (anonReq.pubKey, &(frame->payload[index]), sizeof (anonReq.pubKey)); + index += sizeof (anonReq.pubKey); + anonReq.cipherMAC = frame->payload[index]; + anonReq.cipherMAC |= frame->payload[index + 1] << 8; + + NodeEntry *foundNode = getNode (anonReq.pubKey[0]); + + if (foundNode == NULL) { + foundNode = getNextNode(); + memset (foundNode, 0, sizeof (NodeEntry)); + + strcpy (foundNode->name, "Anonymous node"); + foundNode->path.pathLen = 0; + + memcpy (foundNode->pubKey, + anonReq.pubKey, + sizeof (foundNode->pubKey)); + + // --- X25519 conversion + DH --- + uint8_t peer_x[32]; + + crypto_eddsa_to_x25519 (peer_x, anonReq.pubKey); + + crypto_x25519 (foundNode->secret, + persistent.privkey, + peer_x); + + foundNode->gps_latitude = 0; + foundNode->gps_longitude = 0; + foundNode->type = 0; + foundNode->last_seen_lt = RTC_GetCounter(); + + MESH_LOGI (TAG, "New anonymous node created: %s", foundNode->name); + } else { + MESH_LOGD (TAG, + "Existing node found for pubKey[0]=0x%02X", + anonReq.pubKey[0]); + } + + mac_then_decrypt (foundNode->secret, 32, &(frame->payload[index]), frame->payloadLen - index, anonReq.payload); + anonReq.payloadLen = frame->payloadLen - index - 2; + + hexdump ("AnonReq payload", anonReq.payload, anonReq.payloadLen); + + uint8_t index2 = 0; + foundNode->last_seen_rt = anonReq.payload[index2++]; + foundNode->last_seen_rt |= anonReq.payload[index2++] << 8; + foundNode->last_seen_rt |= anonReq.payload[index2++] << 16; + foundNode->last_seen_rt |= anonReq.payload[index2++] << 24; + + if (persistent.nodeType == NODE_TYPE_ROOM_SERVER) { + foundNode->sync_timestamp = anonReq.payload[index2++]; + foundNode->sync_timestamp |= anonReq.payload[index2++] << 8; + foundNode->sync_timestamp |= anonReq.payload[index2++] << 16; + foundNode->sync_timestamp |= anonReq.payload[index2++] << 24; + } + + printAnonRequest (&anonReq, persistent.nodeType == NODE_TYPE_ROOM_SERVER); + + uint8_t passwordLen = anonReq.payloadLen - index2; + if (passwordLen > 16) { + passwordLen = 16; + } + + passwordLen = strnlen (&(anonReq.payload[index2]), passwordLen); + + MESH_LOGI (TAG, "Password len is %d.", passwordLen); + uint8_t passwordBuf[16]; + memcpy (passwordBuf, &(anonReq.payload[index2]), passwordLen); + + if (memcmp (passwordBuf, persistent.password, passwordLen) == 0) { + foundNode->authenticated = 1; + MESH_LOGI (TAG, "Password correct, node %s authenticated.", foundNode->name); + + MESH_LOGI (TAG, "Login response sent to node %s.", foundNode->name); + } else { + MESH_LOGW (TAG, "Password incorrect for node %s.", foundNode->name); + } + + Response resp; + resp.tag = RTC_GetCounter(); + uint8_t index3 = 0; + uint32_t randOut = rand(); + resp.data[index3++] = RESP_SERVER_LOGIN_OK; + resp.data[index3++] = 0; // legacy + resp.data[index3++] = foundNode->authenticated; // isadmin + resp.data[index3++] = foundNode->authenticated ? PERM_ACL_ADMIN : PERM_ACL_GUEST; // permissions + resp.data[index3++] = randOut & 0xFF; + resp.data[index3++] = (randOut >> 8) & 0xFF; + resp.data[index3++] = (randOut >> 16) & 0xFF; + resp.data[index3++] = (randOut >> 24) & 0xFF; + resp.data[index3++] = FIRMWARE_VER_LEVEL; + resp.dataLen = index3; + if ((frame->header & ROUTE_TYPE_MASK) == ROUTE_TYPE_FLOOD || + (frame->header & ROUTE_TYPE_MASK) == ROUTE_TYPE_TRANSPORT_FLOOD) { + sendPathBack (foundNode, &(frame->path)); + } + sendEncryptedResponse (foundNode, &resp); +} diff --git a/User/meshcore/packets/anonymous.h b/User/meshcore/packets/anonymous.h new file mode 100644 index 0000000..b4f95ea --- /dev/null +++ b/User/meshcore/packets/anonymous.h @@ -0,0 +1,11 @@ +#ifndef ANONYMOUS_HEADER +#define ANONYMOUS_HEADER + +#include "meshcore/packetstructs.h" +#include "lib/config.h" + +void decodeAnonReq (const FrameStruct *frame); + +void sendAnonymousRequest (const NodeEntry *targetNode, const uint8_t *password, uint32_t sync); + +#endif \ No newline at end of file diff --git a/User/meshcore/packets/control.c b/User/meshcore/packets/control.c new file mode 100644 index 0000000..259f6e1 --- /dev/null +++ b/User/meshcore/packets/control.c @@ -0,0 +1,148 @@ +#include "lib/config.h" +#include "meshcore/meshframing.h" +#include "meshcore/packetstructs.h" +#include "control.h" +#include "meshcore/stats.h" +#include "string.h" +#include "util/hexdump.h" +#include "util/log.h" +#include + +#define TAG "Control" + +void sendDiscoverRequest (const DiscoverRequestPayload *discReq) { + + FrameStruct frame; + frame.path.pathLen = 0; + uint8_t offset = 0; + + // Build payload + frame.payload[offset++] = (discReq->prefixOnly & 0x01) | CONTROL_DATA_FLAG_TYPE_NODE_DISCOVER_REQ; + + frame.payload[offset++] = discReq->typeFilter; + + frame.payload[offset++] = (discReq->tag >> 0) & 0xFF; + frame.payload[offset++] = (discReq->tag >> 8) & 0xFF; + frame.payload[offset++] = (discReq->tag >> 16) & 0xFF; + frame.payload[offset++] = (discReq->tag >> 24) & 0xFF; + + // optional `since` + if (discReq->since != 0) { // or another condition if you want to always include + frame.payload[offset++] = (discReq->since >> 0) & 0xFF; + frame.payload[offset++] = (discReq->since >> 8) & 0xFF; + frame.payload[offset++] = (discReq->since >> 16) & 0xFF; + frame.payload[offset++] = (discReq->since >> 24) & 0xFF; + } + + frame.payloadLen = offset; + + LoRaTransmit (&frame); +} + +void sendDiscoverResponse (const DiscoverResponsePayload *discResp) { + FrameStruct frame; + frame.header = ROUTE_TYPE_DIRECT | PAYLOAD_TYPE_CONTROL | PAYLOAD_VERSION_0; + frame.path.pathLen = 0; + uint8_t offset = 0; + + /* Control type + node type (lower nibble) */ + frame.payload[offset++] = + (discResp->nodeType & 0x0F) | + CONTROL_DATA_FLAG_DISCOVER_RESP; + + /* SNR */ + frame.payload[offset++] = (uint8_t)discResp->snr; + + /* Tag (LE) */ + frame.payload[offset++] = (discResp->tag >> 0) & 0xFF; + frame.payload[offset++] = (discResp->tag >> 8) & 0xFF; + frame.payload[offset++] = (discResp->tag >> 16) & 0xFF; + frame.payload[offset++] = (discResp->tag >> 24) & 0xFF; + + /* Pubkey */ + if (discResp->pubkeyLen > 0) { + memcpy (&frame.payload[offset], + discResp->pubkey, + discResp->pubkeyLen); + offset += discResp->pubkeyLen; + } + + frame.payloadLen = offset; + + LoRaTransmit (&frame); +} + +void printDiscoverRequest (const DiscoverRequestPayload *p) { + iprintf ("=== Discover Request ===\n"); + iprintf ("prefixOnly : %u\n", p->prefixOnly); + iprintf ("typeFilter : 0x%02X\n", p->typeFilter); + iprintf ("tag : 0x%08lX\n", (unsigned long)p->tag); + iprintf ("since : 0x%08lX\n", (unsigned long)p->since); +} + +void printDiscoverResponse (const DiscoverResponsePayload *p) { + iprintf ("=== Discover Response ===\n"); + iprintf ("nodeType : %u\n", p->nodeType); + iprintf ("snr : %u\n", p->snr); + iprintf ("tag : 0x%08lX\n", (unsigned long)p->tag); + + hexdump ("pubkey : ", p->pubkey, p->pubkeyLen); + iprintf ("\n"); +} + +void decodeControlFrame (const FrameStruct *frame) { + uint8_t index = 0; + uint8_t type = frame->payload[index] & 0xF0; + if (type == CONTROL_DATA_FLAG_TYPE_NODE_DISCOVER_REQ) { + DiscoverRequestPayload discReq; + discReq.prefixOnly = frame->payload[index++] & 0x01; + + discReq.typeFilter = frame->payload[index++]; + + discReq.tag = frame->payload[index++]; + discReq.tag |= frame->payload[index++] << 8; + discReq.tag |= frame->payload[index++] << 16; + discReq.tag |= frame->payload[index++] << 24; + + if (index < frame->payloadLen) { + discReq.since = frame->payload[index++]; + discReq.since |= frame->payload[index++] << 8; + discReq.since |= frame->payload[index++] << 16; + discReq.since |= frame->payload[index++] << 24; + } + printDiscoverRequest (&discReq); + if ((discReq.typeFilter >> 1) & persistent.nodeType) { + DiscoverResponsePayload discResp; + + discResp.tag = discReq.tag; + discResp.nodeType = persistent.nodeType; + discResp.pubkeyLen = sizeof (persistent.pubkey); + memcpy (discResp.pubkey, persistent.pubkey, discResp.pubkeyLen); + discResp.snr = stats.lastSNR; // hopefully the correct one + + + MESH_LOGD (TAG, "Replying to a discover request with tag %d", discResp.tag); + sendDiscoverResponse (&discResp); + printDiscoverResponse (&discResp); + } + + } else if (type == CONTROL_DATA_FLAG_DISCOVER_RESP) { + DiscoverResponsePayload discResp; + discResp.nodeType = frame->payload[index++] & 0x0F; + + discResp.snr = frame->payload[index++]; + + discResp.tag = frame->payload[index++]; + discResp.tag |= frame->payload[index++] << 8; + discResp.tag |= frame->payload[index++] << 16; + discResp.tag |= frame->payload[index++] << 24; + + uint8_t remainingLen = frame->payloadLen - index; + + uint8_t pubKeyLen = (remainingLen > 8) ? sizeof (discResp.pubkey) : 8; + discResp.pubkeyLen = pubKeyLen; + memcpy (discResp.pubkey, &(frame->payload[index]), discResp.pubkeyLen); + index += pubKeyLen; + printDiscoverResponse (&discResp); + } +} \ No newline at end of file diff --git a/User/meshcore/packets/control.h b/User/meshcore/packets/control.h new file mode 100644 index 0000000..fdad2df --- /dev/null +++ b/User/meshcore/packets/control.h @@ -0,0 +1,16 @@ +#ifndef CONTROL_HEADER +#define CONTROL_HEADER + +#include "meshcore/packetstructs.h" + +void sendDiscoverRequest (const DiscoverRequestPayload *discReq); + +void sendDiscoverResponse (const DiscoverResponsePayload *discResp); + +void printDiscoverRequest (const DiscoverRequestPayload *p); + +void printDiscoverResponse (const DiscoverResponsePayload *p); + +void decodeControlFrame (const FrameStruct *frame); + +#endif \ No newline at end of file diff --git a/User/meshcore/packets/custom.c b/User/meshcore/packets/custom.c new file mode 100644 index 0000000..c3a4ac3 --- /dev/null +++ b/User/meshcore/packets/custom.c @@ -0,0 +1,3 @@ +#include "meshcore/packetstructs.h" + +#define TAG "Custom" \ No newline at end of file diff --git a/User/meshcore/packets/custom.h b/User/meshcore/packets/custom.h new file mode 100644 index 0000000..6ef4d48 --- /dev/null +++ b/User/meshcore/packets/custom.h @@ -0,0 +1,5 @@ +#ifndef CUSTOM_HEADER +#define CUSTOM_HEADER + + +#endif \ No newline at end of file diff --git a/User/meshcore/packets/encrypted.c b/User/meshcore/packets/encrypted.c new file mode 100644 index 0000000..9d0cc55 --- /dev/null +++ b/User/meshcore/packets/encrypted.c @@ -0,0 +1,837 @@ +#include "lib/config.h" +#include "ch32v30x.h" +#include "lib/telemetry/telemetry.h" +#include "meshcore/meshframing.h" +#include "meshcore/packets/ack.h" +#include "meshcore/packets/advert.h" +#include "meshcore/packetstructs.h" +#include "meshcore/stats.h" +#include "util/hexdump.h" +#include "util/log.h" +#include +#include +#include +#include "encrypted.h" +#include "lib/adc/temperature.h" +#include "lib/rtc/rtc.h" +#include "sx1262.h" + +#define TAG "EncryptedMessage" + +void sendEncryptedFrame (const NodeEntry *targetNode, uint8_t payloadType, const uint8_t *plain, size_t plainLen) { + FrameStruct frame; + memset(&frame, 0, sizeof(frame)); + size_t offset = 0; + + // 1. Header + frame.header = + (targetNode->path.pathLen > 0 ? ROUTE_TYPE_DIRECT : ROUTE_TYPE_FLOOD) | // currently flood + payloadType | + PAYLOAD_VERSION_0; + + // 2. Destination + source + frame.payload[offset++] = targetNode->pubKey[0]; + frame.payload[offset++] = persistent.pubkey[0]; + + // 4. Encrypt + MAC + size_t encLen; + encrypt_then_mac ( + targetNode->secret, + 32, + plain, + plainLen, + frame.payload + offset, + &encLen); + + MESH_LOGD(TAG, "Plain len: %d, enc len: %d", plainLen, encLen); + + offset += encLen; + + // 5. Finalize + frame.payloadLen = offset; + memcpy (&frame.path, &targetNode->path, sizeof (frame.path)); + + hexdump ("Encrypted frame", frame.payload, frame.payloadLen); + LoRaTransmit (&frame); + MESH_LOGD (TAG, "Encrypted frame tx finish\n"); +} + +void sendEncryptedTextMessage (const NodeEntry *targetNode, const PlainTextMessagePayload *msg) { + if (targetNode == NULL) { + MESH_LOGW (TAG, "Node is null"); + return; + } + if (targetNode->last_seen_lt == 0) { + MESH_LOGW (TAG, "Node is not populated"); + return; + } + uint8_t buf[256]; + uint8_t index = 0; + + uint8_t msgLen = strlen (msg->message) + 1; + buf[index++] = msg->timestamp; + buf[index++] = msg->timestamp >> 8; + buf[index++] = msg->timestamp >> 16; + buf[index++] = msg->timestamp >> 24; + + buf[index++] = (msg->textType << 2) | (msg->attempt & 0x03); + memcpy (&buf[index], msg->message, msgLen); + index += msgLen; + + sendEncryptedFrame ( + targetNode, + PAYLOAD_TYPE_TXT_MSG, + buf, + index); +} + +void sendEncryptedResponse (const NodeEntry *targetNode, const Response *resp) { + uint8_t buf[256]; + uint8_t index = 0; + + buf[index++] = (resp->tag) & 0xFF; + buf[index++] = (resp->tag >> 8) & 0xFF; + buf[index++] = (resp->tag >> 16) & 0xFF; + buf[index++] = (resp->tag >> 24) & 0xFF; + + memcpy (&(buf[index]), resp->data, resp->dataLen); + index += resp->dataLen; + + sendEncryptedFrame ( + targetNode, + PAYLOAD_TYPE_RESPONSE, + buf, + index); +} + +void sendEncryptedRequest (const NodeEntry *targetNode, const Request *req) { + uint8_t buf[256]; + uint8_t index = 0; + + buf[index++] = req->timestamp; + buf[index++] = req->timestamp >> 8; + buf[index++] = req->timestamp >> 16; + buf[index++] = req->timestamp >> 24; + + buf[index++] = req->requestType; + memcpy (&(buf[index]), req->data, req->dataLen); + index += req->dataLen; + + sendEncryptedFrame ( + targetNode, + PAYLOAD_TYPE_REQ, + buf, + index); +} + +void sendEncryptedPathPayload (const NodeEntry *targetNode, const ReturnedPathPayload *path) { + uint8_t buf[256]; + uint8_t index = 0; + + buf[index++] = path->path.pathLen; + memcpy (&buf[index], path->path.path, path->path.pathLen); + index += path->path.pathLen; + + if (path->extra.dataLen > 0) { + buf[index++] = path->extra.type; + memcpy (&buf[index], path->extra.data, path->extra.dataLen); + } else { + buf[index++] = 0xFF; + uint32_t timestamp = RTC_GetCounter(); + buf[index++] = timestamp; + buf[index++] = timestamp >> 8; + buf[index++] = timestamp >> 16; + buf[index++] = timestamp >> 24; + } + + sendEncryptedFrame ( + targetNode, + PAYLOAD_TYPE_PATH, + buf, + index); +} + +void printRequest (const Request *req) { + iprintf ("Request:\n"); + iprintf (" Timestamp: %u\n", req->timestamp); + iprintf (" Type: 0x%02X\n", req->requestType); + iprintf (" Data: "); + hexdump (" Data", req->data, req->dataLen); +} + +void printResponse (const Response *resp) { + iprintf ("Response:\n"); + iprintf (" Tag: %u\n", resp->tag); + iprintf (" Data: "); + hexdump (" Data", resp->data, resp->dataLen); +} + +void printPlainTextMessage (const PlainTextMessagePayload *msg) { + iprintf ("PlainTextMessage:\n"); + iprintf (" Timestamp: %u\n", msg->timestamp); + iprintf (" Attempt: %u\n", msg->attempt); + iprintf (" TextType: %u\n", msg->textType); + iprintf (" Message: %.*s\n", (int)strlen (msg->message), msg->message); +} + +void printReturnedPathPayload (const ReturnedPathPayload *path) { + iprintf ("ReturnedPathPayload:\n"); + iprintf (" Path Length: %u\n", path->path.pathLen); + iprintf (" Path: "); + hexdump (" Path:", path->path.path, path->path.pathLen); + iprintf (" Extra Type: %u\n", path->extra.type); + iprintf (" Extra Data: "); + hexdump (" Extra data:", path->extra.data, path->extra.dataLen); +} + +void printEncryptedPayload (const EncryptedPayloadStruct *enc) { + iprintf ("EncryptedPayload:\n"); + iprintf (" Type: 0x%02X\n", enc->type); + iprintf (" DestinationHash: 0x%02X\n", enc->destinationHash); + iprintf (" SourceHash: 0x%02X\n", enc->sourceHash); + iprintf (" CipherMAC: 0x%04X\n", enc->cipherMAC); + iprintf (" PayloadLen: %zu\n", enc->payloadLen); + iprintf (" Payload: "); + for (size_t i = 0; i < enc->payloadLen; i++) { + iprintf ("%02X ", enc->payload[i]); + } + iprintf ("\n"); +} + +void decodeEncryptedPayload (const FrameStruct *frame) { + EncryptedPayloadStruct enc; + memset (&enc, 0, sizeof (enc)); + enc.path = &(frame->path); + enc.origFrame = frame; + enc.type = frame->header & PAYLOAD_TYPE_MASK; + unsigned char index = 0; + + enc.destinationHash = frame->payload[index++]; + enc.sourceHash = frame->payload[index++]; + enc.cipherMAC = frame->payload[index]; + enc.cipherMAC |= frame->payload[index + 1] << 8; + + if (enc.destinationHash != persistent.pubkey[0]) { + return; + } + + MESH_LOGI (TAG, "Finding remote node, sourceHash is %d", enc.sourceHash); + + NodeEntry *remNode = getNode (enc.sourceHash); + + enc.remNode = remNode; + + if (remNode == NULL) { + MESH_LOGW (TAG, "Node not in DB"); + return; + } + remNode->last_seen_lt = RTC_GetCounter(); + MESH_LOGI (TAG, "Found node with index %d", remNode - persistent.contacts); + + + if (mac_then_decrypt (remNode->secret, 32, &(frame->payload[index]), frame->payloadLen - index, enc.payload) != 0) { + MESH_LOGW (TAG, "HMAC failed on encrypted message %s", remNode->name); + } else { + enc.payloadLen = frame->payloadLen - HMAC_SIZE; + MESH_LOGI (TAG, "HMAC success from %s, %u bytes long", remNode->name, enc.payloadLen); + sendDiscreteAck (enc.payload, 5 + strlen ((char *)&enc.payload[5]), remNode->pubKey); + } + + iprintf (" Typexdd: 0x%02X\n", enc.type); + if (enc.payloadLen > 0) { + parseEncryptedPayload (&enc); + } +} + +void sendPathBack (const NodeEntry *node, const Path *path) { + ReturnedPathPayload retPath; + retPath.extra.dataLen = 0; // redo to send the resp in path + retPath.extra.type = 0xFF; + + retPath.path.pathLen = path->pathLen; + memcpy (retPath.path.path, path->path, path->pathLen); + + sendEncryptedPathPayload (node, &retPath); +} + +void parseEncryptedPayload (const EncryptedPayloadStruct *enc) { + // printEncryptedPayload(&enc); + + iprintf ("EncryptedPayload:\n"); + iprintf (" Type: 0x%02X\n", enc->type); + iprintf (" DestinationHash: 0x%02X\n", enc->destinationHash); + iprintf (" SourceHash: 0x%02X\n", enc->sourceHash); + iprintf (" CipherMAC: 0x%04X\n", enc->cipherMAC); + iprintf (" PayloadLen: %u\n", enc->payloadLen); + hexdump (" Payload: ", enc->payload, enc->payloadLen); + iprintf ("\n"); + + uint8_t index = 0; + if (enc->type == PAYLOAD_TYPE_PATH) { + ReturnedPathPayload retPath; + retPath.path.pathLen = enc->payload[index++]; + if (retPath.path.pathLen > 64) { + MESH_LOGW (TAG, "Path too long\n"); + return; + } + memcpy (retPath.path.path, &(enc->payload[index]), retPath.path.pathLen); + index += retPath.path.pathLen; + retPath.extra.type = enc->payload[index++]; + retPath.extra.dataLen = enc->payloadLen - index; + memcpy (retPath.extra.data, &(enc->payload[index]), retPath.extra.dataLen); + + if ((enc->origFrame->header & ROUTE_TYPE_MASK) == ROUTE_TYPE_FLOOD || + (enc->origFrame->header & ROUTE_TYPE_MASK) == ROUTE_TYPE_TRANSPORT_FLOOD) { + sendPathBack (enc->remNode, enc->path); + } + + } else if (enc->type == PAYLOAD_TYPE_REQ) { + Request req; + req.timestamp = enc->payload[index++]; + req.timestamp |= enc->payload[index++] << 8; + req.timestamp |= enc->payload[index++] << 16; + req.timestamp |= enc->payload[index++] << 24; + enc->remNode->last_seen_rt = req.timestamp; + req.requestType = enc->payload[index++]; + req.dataLen = enc->payloadLen - index; + memcpy (req.data, &(enc->payload[index]), req.dataLen); + printRequest (&req); + if ((enc->origFrame->header & ROUTE_TYPE_MASK) == ROUTE_TYPE_FLOOD || + (enc->origFrame->header & ROUTE_TYPE_MASK) == ROUTE_TYPE_TRANSPORT_FLOOD) { + sendPathBack (enc->remNode, enc->path); + } + switch (req.requestType) { + case REQUEST_GET_STATS: { + Response resp; + resp.tag = RTC_GetCounter(); + stats.totalUpTimeSeconds = RTC_GetCounter() - startupTime; + //stats.totalAirTimeSeconds = TICKS_TO_MS (tickAirtime / 1000); + stats.totalAirTimeSeconds = 0; + memcpy (resp.data, &stats, sizeof (stats)); + resp.dataLen = sizeof (stats); + sendEncryptedResponse (enc->remNode, &resp); + break; + } + case REQUEST_KEEPALIVE: + break; + case REQUEST_GET_TELEMETRY_DATA: { + Response resp; + resp.tag = req.timestamp; + enc->remNode->last_seen_rt = req.timestamp; + resp.dataLen = 0; + resp.data[resp.dataLen++] = TELEM_CHANNEL_SELF; + resp.data[resp.dataLen++] = LPP_TEMPERATURE; + + int16_t dataTemp = getDeciTemperature(); + + resp.data[resp.dataLen++] = (dataTemp >> 8) & 0xFF; + + resp.data[resp.dataLen++] = dataTemp & 0xFF; + + resp.data[resp.dataLen++] = TELEM_CHANNEL_SELF; + resp.data[resp.dataLen++] = LPP_VOLTAGE; + + int16_t dataVolt = stats.millivolts / 10; + + resp.data[resp.dataLen++] = (dataVolt >> 8) & 0xFF; + + resp.data[resp.dataLen++] = dataVolt & 0xFF; + + resp.data[resp.dataLen++] = 2; + resp.data[resp.dataLen++] = LPP_VOLTAGE; + + dataVolt = 1973; + + resp.data[resp.dataLen++] = (dataVolt >> 8) & 0xFF; + + resp.data[resp.dataLen++] = dataVolt & 0xFF; + + if (enc->remNode->authenticated) { + + resp.data[resp.dataLen++] = 2; // channel 2 + resp.data[resp.dataLen++] = LPP_TEMPERATURE; + + int16_t jokeTemp = 6942; + + resp.data[resp.dataLen++] = (jokeTemp >> 8) & 0xFF; + + resp.data[resp.dataLen++] = jokeTemp & 0xFF; + + + encode_gps (TELEM_CHANNEL_SELF, persistent.latitude, persistent.longitude, persistent.altitude, &(resp.data[resp.dataLen])); + // encode_gps(TELEM_CHANNEL_SELF, 48.1909f, 17.0303f, 234.0f, &(resp.data[resp.dataLen])); + + resp.dataLen += LPP_GPS_SIZE + 2; + } + + + sendEncryptedResponse (enc->remNode, &resp); + + iprintf ("Sent response, the temperature is %d decicelsius\n", dataTemp); + + break; + } + case REQUEST_GET_MIN_MAX_AVG: + break; + case REQUEST_GET_ACCESS_LIST: + break; + } + + } else if (enc->type == PAYLOAD_TYPE_RESPONSE) { + Response resp; + resp.tag = enc->payload[index++]; + resp.tag |= enc->payload[index++] << 8; + resp.tag |= enc->payload[index++] << 16; + resp.tag |= enc->payload[index++] << 24; + resp.dataLen = enc->payloadLen - index; + memcpy (resp.data, &(enc->payload[index]), resp.dataLen); + printResponse (&resp); + + } else if (enc->type == PAYLOAD_TYPE_TXT_MSG) { + PlainTextMessagePayload plaintext; + plaintext.timestamp = enc->payload[index++]; + plaintext.timestamp |= enc->payload[index++] << 8; + plaintext.timestamp |= enc->payload[index++] << 16; + plaintext.timestamp |= enc->payload[index++] << 24; + enc->remNode->last_seen_rt = plaintext.timestamp; + plaintext.attempt = enc->payload[index] & 0x03; + plaintext.textType = enc->payload[index++] >> 2; + memcpy (plaintext.message, &(enc->payload[index]), enc->payloadLen - index); + if ((enc->origFrame->header & ROUTE_TYPE_MASK) == ROUTE_TYPE_FLOOD || + (enc->origFrame->header & ROUTE_TYPE_MASK) == ROUTE_TYPE_TRANSPORT_FLOOD) { + sendPathBack (enc->remNode, enc->path); + } + switch (plaintext.textType) { + case TXT_TYPE_PLAIN: + iprintf ("Plaintext message from %s, attempt %d, timestamp %d: %s", enc->remNode->name, plaintext.attempt, plaintext.timestamp, plaintext.message); + break; + + case TXT_TYPE_CLI_DATA: + if (enc->remNode->authenticated) { + processCommand (plaintext.message, enc->remNode); + } + break; + + case TXT_TYPE_SIGNED_PLAIN: { + uint8_t senderPubKeyPrefix[4]; + memcpy (senderPubKeyPrefix, plaintext.message, sizeof (senderPubKeyPrefix)); + NodeEntry *senderNode = getNodePrefix (senderPubKeyPrefix); + iprintf ("Plaintext message from server %s, sender is %s, attempt %d, timestamp %d: %s", enc->remNode->name, senderNode->name, plaintext.attempt, plaintext.timestamp, &(plaintext.message[4])); + break; + } + + default: + MESH_LOGW (TAG, "Unknown text type: %d", plaintext.textType); + break; + } + } +} + +// #define STR_EQ_LIT(s, lit) (memcmp ((s), (lit), sizeof (lit) - 1) == 0) +#define STR_EQ_LIT(s, lit) (strcmp (s, lit) == 0) + +static int32_t parse_coord_micro(const char *s) +{ + int32_t sign = 1; + int32_t int_part = 0; + int32_t frac_part = 0; + int32_t frac_div = 1; + + if (*s == '-') { + sign = -1; + s++; + } + + // integer part + while (*s >= '0' && *s <= '9') { + int_part = int_part * 10 + (*s - '0'); + s++; + } + + if (*s == '.') { + s++; + while (*s >= '0' && *s <= '9' && frac_div < 1000000) { + frac_part = frac_part * 10 + (*s - '0'); + frac_div *= 10; + s++; + } + } + + // scale to microdegrees + while (frac_div < 1000000) { + frac_part *= 10; + frac_div *= 10; + } + + return sign * (int_part * 1000000 + frac_part); +} + +void processCommand (char *cmd, NodeEntry *remNode) { + PlainTextMessagePayload replyPayload; + replyPayload.timestamp = RTC_GetCounter(); + replyPayload.attempt = 0; + replyPayload.textType = TXT_TYPE_CLI_DATA; + + uint8_t *reply = replyPayload.message; + reply[0] = 0; + + while (*cmd == ' ') cmd++; // skip leading spaces + + // Optional CLI prefix (xx|) for companion radio + if (strlen (cmd) > 4 && cmd[2] == '|') { + memcpy (reply, cmd, 3); + reply += 3; + cmd += 3; + } + + /* ---------------- System ---------------- */ + if (STR_EQ_LIT (cmd, "reboot")) { + NVIC_SystemReset(); + } else if (STR_EQ_LIT (cmd, "advert")) { + sendAdvert (1); // 1500ms delay in reference + strcpy ((char *)reply, "OK - Advert sent"); + } else if (STR_EQ_LIT (cmd, "clear stats")) { + memset (&stats, 0, sizeof (stats)); + strcpy ((char *)reply, "(OK - stats reset)"); + } + + else if (STR_EQ_LIT (cmd, "ver")) { + sprintf ((char *)reply, "%s (Build: %s)", VERSION, __DATE__); + } + + else if (STR_EQ_LIT (cmd, "board")) { + sprintf ((char *)reply, "%s", BOARD); + } + + /* ---------------- Clock ---------------- */ + else if (STR_EQ_LIT (cmd, "clock")) { + RTC_Get(); + sprintf ((char *)reply, "%02d:%02d:%02d - %d/%d/%d UTC", + calendar.hour, calendar.min, calendar.sec, + calendar.w_date, calendar.w_month, calendar.w_year); + } else if (STR_EQ_LIT (cmd, "time ")) { + uint32_t secs = atoi (&cmd[5]); + uint32_t curr = RTC_GetCounter(); + if (secs > curr) { + RTC_SetCounter (secs); + RTC_Get(); + sprintf ((char *)reply, "OK - clock set: %02d:%02d:%02d - %d/%d/%d UTC", + calendar.hour, calendar.min, calendar.sec, + calendar.w_date, calendar.w_month, calendar.w_year); + } else { + strcpy ((char *)reply, "(ERR: clock cannot go backwards)"); + } + } else if (STR_EQ_LIT (cmd, "clock sync")) { + uint32_t curr = RTC_GetCounter(); + uint32_t sender = replyPayload.timestamp; + if (sender > curr) { + RTC_SetCounter (sender + 1); + RTC_Get(); + sprintf ((char *)reply, "OK - clock set: %02d:%02d:%02d - %d/%d/%d UTC", + calendar.hour, calendar.min, calendar.sec, + calendar.w_date, calendar.w_month, calendar.w_year); + } else { + strcpy ((char *)reply, "ERR: clock cannot go backwards"); + } + } + + /* + else if (STR_EQ_LIT (cmd, "tempradio ")) { + char tmp[64]; + strcpy (tmp, &cmd[10]); + + const char *parts[5]; + int num = mesh_ParseTextParts (tmp, parts, 5); // assume helper + float freq = num > 0 ? strtof (parts[0], NULL) : 0.0f; + float bw = num > 1 ? strtof (parts[1], NULL) : 0.0f; + uint8_t sf = num > 2 ? atoi (parts[2]) : 0; + uint8_t cr = num > 3 ? atoi (parts[3]) : 0; + int timeout_mins = num > 4 ? atoi (parts[4]) : 0; + if (freq >= 300.0f && freq <= 2500.0f && bw >= 7.0f && bw <= 500.0f && + sf >= 5 && sf <= 12 && cr >= 5 && cr <= 8 && timeout_mins > 0) { + Callbacks_ApplyTempRadioParams (freq, bw, sf, cr, timeout_mins); + + LoraApply(); + sprintf ((char *)reply, "OK - temp params for %d mins", timeout_mins); + } else { + strcpy ((char *)reply, "Error, invalid params"); + } + } + */ + + /* ---------------- Password ---------------- */ + else if (STR_EQ_LIT (cmd, "password ")) { + strncpy (persistent.password, &cmd[9], sizeof (persistent.password)); + // savePrefs(); TODO add this + sprintf ((char *)reply, "password now: %s", persistent.password); + } + + /* ---------------- GET / SET Config ---------------- */ + else if (STR_EQ_LIT (cmd, "get ")) { + const char *config = &cmd[4]; + +/* + if (memcmp (config, "af", 2) == 0) { + sprintf (reply, "> %f", persistent.airtimeFactor); + */ + /* + } else if (memcmp (config, "int.thresh", 10) == 0) { + sprintf (reply, "> %d", (uint32_t)_prefs->interference_threshold); + } else if (memcmp (config, "agc.reset.interval", 18) == 0) { + sprintf (reply, "> %d", ((uint32_t)_prefs->agc_reset_interval) * 4); + } else if (memcmp (config, "multi.acks", 10) == 0) { + sprintf (reply, "> %d", (uint32_t)_prefs->multi_acks); + } else if (memcmp (config, "allow.read.only", 15) == 0) { + sprintf (reply, "> %s", _prefs->allow_read_only ? "on" : "off"); + } else if (memcmp (config, "flood.advert.interval", 21) == 0) { + sprintf (reply, "> %d", (uint32_t)_prefs->flood_advert_interval); + } else if (memcmp (config, "advert.interval", 15) == 0) { + sprintf (reply, "> %d", ((uint32_t)_prefs->advert_interval) * 2);1 + */ + //} else + if (memcmp (config, "guest.password", 14) == 0) { + sprintf (reply, "> %s", persistent.guestPassword); + } else if (memcmp (config, "name", 4) == 0) { + sprintf (reply, "> %s", persistent.nodeName); + } else if (memcmp (config, "repeat", 6) == 0) { + sprintf (reply, "> %s", persistent.doRepeat ? "on" : "off"); + } else if (memcmp (config, "lat", 3) == 0) { + sprintf (reply, "> %d", persistent.latitude); + } else if (memcmp (config, "lon", 3) == 0) { + sprintf (reply, "> %d", persistent.longitude); + /* + } else if (memcmp (config, "radio", 5) == 0) { + char freq[16], bw[16]; + snprintf(freq, sizeof(freq), "%lf", persistent.frequencyInHz / 1000000.0); + snprintf(bw, sizeof(bw), "%lf", loraBwToFloat(persistent.bandwidth)); + sprintf (reply, "> %s,%s,%d,%d", freq, bw, persistent.spreadingFactor, persistent.codingRate + 4); + } else if (memcmp (config, "rxdelay", 7) == 0) { + sprintf (reply, "> %s", StrHelper::ftoa (_prefs->rx_delay_base)); + } else if (memcmp (config, "txdelay", 7) == 0) { + sprintf (reply, "> %s", StrHelper::ftoa (_prefs->tx_delay_factor)); + } else if (memcmp (config, "flood.max", 9) == 0) { + sprintf (reply, "> %d", (uint32_t)_prefs->flood_max); + } else if (memcmp (config, "direct.txdelay", 14) == 0) { + sprintf (reply, "> %s", StrHelper::ftoa (_prefs->direct_tx_delay_factor)); + } else if (memcmp (config, "tx", 2) == 0 && (config[2] == 0 || config[2] == ' ')) { + sprintf (reply, "> %d", (uint32_t)_prefs->tx_power_dbm); + } else if (memcmp (config, "freq", 4) == 0) { + sprintf (reply, "> %s", StrHelper::ftoa (_prefs->freq)); + */ + } else if (memcmp (config, "public.key", 10) == 0) { + strcpy (reply, "> "); + hexdump_compact (persistent.pubkey, sizeof (persistent.pubkey), &(reply[2]), 70); + } else if (memcmp (config, "role", 4) == 0) { + sprintf (reply, "> %s", getStringRole (persistent.nodeType)); + } else if (memcmp (config, "adc.multiplier", 14) == 0) { + sprintf (reply, "> %d.%d", persistent.adcMultiplier / 1000, persistent.adcMultiplier % 1000); + } else { + sprintf (reply, "??: %s", config); + } + + } else if (STR_EQ_LIT (cmd, "set ")) { + const char *config = &cmd[4]; + + +/* + if (memcmp (config, "af ", 3) == 0) { + persistent.airtimeFactor = atof (&config[3]); + // savePrefs(); + strcpy (reply, "OK"); + */ + /* + } else if (memcmp (config, "int.thresh ", 11) == 0) { + _prefs->interference_threshold = atoi (&config[11]); + // savePrefs(); + strcpy (reply, "OK"); + } else if (memcmp (config, "agc.reset.interval ", 19) == 0) { + _prefs->agc_reset_interval = atoi (&config[19]) / 4; + // savePrefs(); + sprintf (reply, "OK - interval rounded to %d", ((uint32_t)_prefs->agc_reset_interval) * 4); + } else if (memcmp (config, "multi.acks ", 11) == 0) { + _prefs->multi_acks = atoi (&config[11]); + // savePrefs(); + strcpy (reply, "OK"); + */ + //} else + if (memcmp (config, "allow.read.only ", 16) == 0) { + if (memcmp (&config[16], "on", 2) == 0) { + persistent.allowReadOnly = 1; + strcpy (reply, "OK"); + } else if (memcmp (&config[16], "off", 3) == 0) { + persistent.allowReadOnly = 0; + strcpy (reply, "OK"); + } + // savePrefs(); + /* + } else if (memcmp (config, "flood.advert.interval ", 22) == 0) { + int hours = _atoi (&config[22]); + if ((hours > 0 && hours < 3) || (hours > 48)) { + strcpy (reply, "Error: interval range is 3-48 hours"); + } else { + _prefs->flood_advert_interval = (uint8_t)hours; + _callbacks->updateFloodAdvertTimer(); + savePrefs(); + strcpy (reply, "OK"); + } + } else if (memcmp (config, "advert.interval ", 16) == 0) { + int mins = _atoi (&config[16]); + if ((mins > 0 && mins < MIN_LOCAL_ADVERT_INTERVAL) || (mins > 240)) { + sprintf (reply, "Error: interval range is %d-240 minutes", MIN_LOCAL_ADVERT_INTERVAL); + } else { + _prefs->advert_interval = (uint8_t)(mins / 2); + _callbacks->updateAdvertTimer(); + savePrefs(); + strcpy (reply, "OK"); + } + */ + } else if (memcmp (config, "guest.password ", 15) == 0) { + strncpy (persistent.guestPassword, &config[15], sizeof (persistent.guestPassword)); + // savePrefs(); + strcpy (reply, "OK"); + } else if (memcmp (config, "name ", 5) == 0) { + strncpy (persistent.nodeName, &config[5], sizeof (persistent.nodeName)); + // savePrefs(); + strcpy (reply, "OK"); + } else if (memcmp (config, "repeat ", 7) == 0) { + if (memcmp (&config[7], "off", 3) == 0) { + persistent.doRepeat = 0; + } else if (memcmp (&config[7], "on", 2) == 0) { + persistent.doRepeat = 1; + } + // savePrefs(); + strcpy (reply, persistent.doRepeat ? "OK - repeat is now ON" : "OK - repeat is now OFF"); + /* + } else if (memcmp (config, "radio ", 6) == 0) { + strcpy (tmp, &config[6]); + const char *parts[4]; + int num = mesh::Utils::parseTextParts (tmp, parts, 4); + float freq = num > 0 ? strtof (parts[0], 0) : 0.0f; + float bw = num > 1 ? strtof (parts[1], 0) : 0.0f; + uint8_t sf = num > 2 ? atoi (parts[2]) : 0; + uint8_t cr = num > 3 ? atoi (parts[3]) : 0; + if (freq >= 300.0f && freq <= 2500.0f && sf >= 5 && sf <= 12 && cr >= 5 && cr <= 8 && bw >= 7.0f && bw <= 500.0f) { + _prefs->sf = sf; + _prefs->cr = cr; + _prefs->freq = freq; + _prefs->bw = bw; + _callbacks->savePrefs(); + strcpy (reply, "OK - reboot to apply"); + } else { + strcpy (reply, "Error, invalid radio params"); + } + */ + } else if (memcmp (config, "lat ", 4) == 0) { + persistent.latitude = parse_coord_micro(&config[4]); + // savePrefs(); + strcpy (reply, "OK"); + } else if (memcmp (config, "lon ", 4) == 0) { + persistent.longitude = parse_coord_micro(&config[4]); + // savePrefs(); + strcpy (reply, "OK"); + /* + } else if (memcmp (config, "rxdelay ", 8) == 0) { + float db = atof (&config[8]); + if (db >= 0) { + _prefs->rx_delay_base = db; + savePrefs(); + strcpy (reply, "OK"); + } else { + strcpy (reply, "Error, cannot be negative"); + } + } else if (memcmp (config, "txdelay ", 8) == 0) { + float f = atof (&config[8]); + if (f >= 0) { + _prefs->tx_delay_factor = f; + savePrefs(); + strcpy (reply, "OK"); + } else { + strcpy (reply, "Error, cannot be negative"); + } + } else if (memcmp (config, "flood.max ", 10) == 0) { + uint8_t m = atoi (&config[10]); + if (m <= 64) { + _prefs->flood_max = m; + savePrefs(); + strcpy (reply, "OK"); + } else { + strcpy (reply, "Error, max 64"); + } + } else if (memcmp (config, "direct.txdelay ", 15) == 0) { + float f = atof (&config[15]); + if (f >= 0) { + _prefs->direct_tx_delay_factor = f; + savePrefs(); + strcpy (reply, "OK"); + } else { + strcpy (reply, "Error, cannot be negative"); + } + } else if (memcmp (config, "tx ", 3) == 0) { + _prefs->tx_power_dbm = atoi (&config[3]); + savePrefs(); + _callbacks->setTxPower (_prefs->tx_power_dbm); + strcpy (reply, "OK"); + */ + /* + } else if (memcmp (config, "freq ", 5) == 0) { + double freq = atof (&config[5]); + uint32_t newFreq = mhzToHzLimited (persistent.loraSettings.frequencyInHz); + if (newFreq != 0) { + persistent.loraSettings.frequencyInHz = newFreq; + } + // savePrefs(); + strcpy (reply, "OK - reboot to apply"); + */ + /* + } else if (memcmp (config, "adc.multiplier ", 15) == 0) { + persistent.adcMultiplier = atof (&config[15]); + if (persistent.adcMultiplier == 0.0f) { + strcpy (reply, "OK - using default board multiplier"); + } else { + sprintf (reply, "OK - multiplier set to %.3f", persistent.adcMultiplier); + } + // savePrefs(); + */ + } else { + sprintf (reply, "unknown config: %s", config); + } + } + + + /* ---------------- Stats ---------------- */ + else if (STR_EQ_LIT (cmd, "stats-packets")) { + sprintf (reply, + "{\"recv\":%u,\"sent\":%u,\"flood_tx\":%u,\"direct_tx\":%u,\"flood_rx\":%u,\"direct_rx\":%u}", + stats.packetsReceivedCount, + stats.packetsSentCount, + stats.sentFloodCount, + stats.sentDirectCount, + stats.receivedFloodCount, + stats.receivedDirectCount); + } else if (STR_EQ_LIT (cmd, "stats-radio")) { + sprintf (reply, + "{\"noise_floor\":%d,\"last_rssi\":%d,\"last_snr\":%d.00,\"tx_air_secs\":%u,\"rx_air_secs\":%u}", + stats.noiseFloor, + stats.lastRSSI, + stats.lastSNR / 4, + stats.totalAirTimeSeconds, + stats.total_rx_air_time_secs); + } else if (STR_EQ_LIT (cmd, "stats-core")) { + stats.totalUpTimeSeconds = RTC_GetCounter() - startupTime; + //stats.totalAirTimeSeconds = TICKS_TO_MS (tickAirtime / 1000); + stats.totalAirTimeSeconds = 0; + sprintf (reply, + "{\"battery_mv\":%u,\"uptime_secs\":%u,\"errors\":%u,\"queue_len\":%u}", + getVoltage(), + stats.totalUpTimeSeconds, + stats.err_events, + stats.txQueueLength); + } + + /* ---------------- Unknown ---------------- */ + else { + strcpy ((char *)reply, "Unknown command"); + } + + sendEncryptedTextMessage (remNode, &replyPayload); +} diff --git a/User/meshcore/packets/encrypted.h b/User/meshcore/packets/encrypted.h new file mode 100644 index 0000000..076d76c --- /dev/null +++ b/User/meshcore/packets/encrypted.h @@ -0,0 +1,30 @@ +#ifndef ENCRYPTED_HEADER +#define ENCRYPTED_HEADER + +#include "lib/config.h" +#include "meshcore/meshframing.h" +#include "meshcore/packetstructs.h" +#include "util/log.h" +#include + +#define MIN_LOCAL_ADVERT_INTERVAL 60 + +void sendEncryptedFrame (const NodeEntry *targetNode, uint8_t payloadType, const uint8_t *plain, size_t plainLen); + +void sendEncryptedTextMessage (const NodeEntry *targetNode, const PlainTextMessagePayload *msg); + +void sendEncryptedResponse (const NodeEntry *targetNode, const Response *resp); + +void sendEncryptedRequest (const NodeEntry *targetNode, const Request *req); + +void sendEncryptedPathPayload (const NodeEntry *targetNode, const ReturnedPathPayload *path); + +void decodeEncryptedPayload (const FrameStruct *frame); + +void parseEncryptedPayload (const EncryptedPayloadStruct *enc); + +void processCommand(char * cmd, NodeEntry * remNode); + +void sendPathBack (const NodeEntry *node, const Path *path); + +#endif \ No newline at end of file diff --git a/User/meshcore/packets/group.c b/User/meshcore/packets/group.c new file mode 100644 index 0000000..f49bea2 --- /dev/null +++ b/User/meshcore/packets/group.c @@ -0,0 +1,107 @@ +#include "ch32v30x_rtc.h" +#include "meshcore/meshframing.h" +#include "meshcore/packetstructs.h" +#include "group.h" +#include "lib/config.h" +#include "util/hexdump.h" +#include "util/log.h" +#include "string.h" + +#define TAG "GroupMessage" + +void sendGroupMessage (const GroupTextMessage *msg) { + // Prepare values locally instead of modifying msg + Channel *channel = &(persistent.channels[msg->keyIndex]); + uint8_t flags = 0; + int32_t timestamp = RTC_GetCounter(); + + FrameStruct frame; + frame.header = ROUTE_TYPE_FLOOD | PAYLOAD_TYPE_GRP_TXT | PAYLOAD_VERSION_0; + frame.path.pathLen = 0; + size_t offset = 0; + frame.payload[offset++] = channel->hash; + + // Build encryption buffer directly on stack (no extra large buffer) + uint8_t buf[180]; // enough for timestamp + flags + text + size_t buf_offset = 0; + + memcpy (buf + buf_offset, ×tamp, sizeof (timestamp)); + buf_offset += sizeof (timestamp); + + buf[buf_offset++] = flags; + + size_t textLen = strlen ((const char *)msg->text); + if (buf_offset + textLen > sizeof (buf)) { + textLen = sizeof (buf) - buf_offset; + } + memcpy (buf + buf_offset, msg->text, textLen); + buf_offset += textLen; + + hexdump ("TxDumpDec", buf, buf_offset); + + // Encrypt and MAC directly into frame payload after channelHash + size_t olen = 0; + + encrypt_then_mac (channel->key, 16, buf, buf_offset, &frame.payload[offset], &olen); + + frame.payloadLen = olen + 1; // +1 for channelHash + + channel->timestamp = timestamp; + + LoRaTransmit (&frame); +} + +void makeSendGroupMessage (char *txt, uint8_t keyIndex) { + GroupTextMessage msg; + strcpy ((char *)msg.text, persistent.nodeName); + strcat ((char *)msg.text, ": "); + strcat ((char *)msg.text, txt); + msg.keyIndex = keyIndex; + sendGroupMessage (&msg); + return; +} + +void decodeGroupMessage (const FrameStruct *frame) { + GroupTextMessage msg; + memset (&msg, 0, sizeof (msg)); + if ((frame->header & PAYLOAD_TYPE_MASK) != PAYLOAD_TYPE_GRP_TXT) { + MESH_LOGW (TAG, "Not a group text"); + return; + } + unsigned char index = 0; + msg.channelHash = frame->payload[index++]; + unsigned char tmp[184]; + + + Channel *channel = NULL; + + uint8_t i = 0; + do { + channel = getChannel (msg.channelHash, i); + if (channel == NULL) { + MESH_LOGW (TAG, "Channel hash %d not found", msg.channelHash); + return; + } + if (mac_then_decrypt (channel->key, 16, frame->payload + index, frame->payloadLen - index, tmp) != 0) { + MESH_LOGW (TAG, "HMAC failed on grouphash key %d", msg.channelHash); + i++; + continue; + } else { + unsigned char plaintextLen = frame->payloadLen - index; + index = 0; + + memcpy (&msg.timestamp, tmp + index, 4); + index += 4; + msg.flags = tmp[index++]; + + memcpy (msg.text, tmp + index, plaintextLen - index); + + channel->timestamp = RTC_GetCounter(); + + iprintf ("Message from channel %s: %s\n", channel->name, msg.text); + break; + } + + + } while (channel != NULL); +} \ No newline at end of file diff --git a/User/meshcore/packets/group.h b/User/meshcore/packets/group.h new file mode 100644 index 0000000..befd673 --- /dev/null +++ b/User/meshcore/packets/group.h @@ -0,0 +1,13 @@ +#ifndef GROUP_HEADER +#define GROUP_HEADER + +#include "stdint.h" +#include "meshcore/packetstructs.h" + +void sendGroupMessage (const GroupTextMessage *msg); + +void makeSendGroupMessage (char *txt, uint8_t keyIndex); + +void decodeGroupMessage (const FrameStruct *frame); + +#endif \ No newline at end of file diff --git a/User/meshcore/packets/multipart.c b/User/meshcore/packets/multipart.c new file mode 100644 index 0000000..a17fc5d --- /dev/null +++ b/User/meshcore/packets/multipart.c @@ -0,0 +1,4 @@ +#include "meshcore/packetstructs.h" +#include "multipart.h" + +#define TAG "Multipart" \ No newline at end of file diff --git a/User/meshcore/packets/multipart.h b/User/meshcore/packets/multipart.h new file mode 100644 index 0000000..21437d4 --- /dev/null +++ b/User/meshcore/packets/multipart.h @@ -0,0 +1,4 @@ +#ifndef MULTIPART_HEADER +#define MULTIPART_HEADER + +#endif \ No newline at end of file diff --git a/User/meshcore/packets/trace.c b/User/meshcore/packets/trace.c new file mode 100644 index 0000000..07c11ee --- /dev/null +++ b/User/meshcore/packets/trace.c @@ -0,0 +1,4 @@ +#include "meshcore/packetstructs.h" +#include "trace.h" + +#define TAG "Trace" \ No newline at end of file diff --git a/User/meshcore/packets/trace.h b/User/meshcore/packets/trace.h new file mode 100644 index 0000000..caccf6a --- /dev/null +++ b/User/meshcore/packets/trace.h @@ -0,0 +1,5 @@ +#ifndef TRACE_HEADER +#define TRACE_HEADER + + +#endif \ No newline at end of file diff --git a/User/meshcore/packetstructs.h b/User/meshcore/packetstructs.h new file mode 100644 index 0000000..4a421be --- /dev/null +++ b/User/meshcore/packetstructs.h @@ -0,0 +1,248 @@ +#ifndef PACKETSTRUCTS_FILE +#define PACKETSTRUCTS_FILE + +#include +#include "stddef.h" +#define ROUTE_TYPE_MASK 0x03 +#define PAYLOAD_TYPE_MASK 0x3C +#define PAYLOAD_VERSION_MASK 0xC0 + +#define DONT_RETRANSMIT_HEADER 0xFF + +#define RESP_SERVER_LOGIN_OK 0 + +#define FIRMWARE_VER_LEVEL 1 + +#define PERM_ACL_ROLE_MASK 3 // lower 2 bits +#define PERM_ACL_GUEST 0 +#define PERM_ACL_READ_ONLY 1 +#define PERM_ACL_READ_WRITE 2 +#define PERM_ACL_ADMIN 3 + +#define NODE_ENTRY_FAV_FLAG (1 << 0) + + +#define MAX_PATH_LEN 64 + + +#define TXT_TYPE_PLAIN 0 // a plain text message +#define TXT_TYPE_CLI_DATA 1 // a CLI command +#define TXT_TYPE_SIGNED_PLAIN 2 // plain text, signed by sender + +typedef enum RouteType { + ROUTE_TYPE_TRANSPORT_FLOOD = 0x00, + ROUTE_TYPE_FLOOD = 0x01, + ROUTE_TYPE_DIRECT = 0x02, + ROUTE_TYPE_TRANSPORT_DIRECT = 0x03, +} RouteType; + +typedef enum PayloadType { + PAYLOAD_TYPE_REQ = 0x00 << 2, + PAYLOAD_TYPE_RESPONSE = 0x01 << 2, + PAYLOAD_TYPE_TXT_MSG = 0x02 << 2, + PAYLOAD_TYPE_ACK = 0x03 << 2, + PAYLOAD_TYPE_ADVERT = 0x04 << 2, + PAYLOAD_TYPE_GRP_TXT = 0x05 << 2, + PAYLOAD_TYPE_GRP_DATA = 0x06 << 2, + PAYLOAD_TYPE_ANON_REQ = 0x07 << 2, + PAYLOAD_TYPE_PATH = 0x08 << 2, + PAYLOAD_TYPE_TRACE = 0x09 << 2, + PAYLOAD_TYPE_MULTIPART = 0x0A << 2, + PAYLOAD_TYPE_CONTROL = 0x0B << 2, + PAYLOAD_TYPE_RAW_CUSTOM = 0x0F << 2, +} PayloadType; + +typedef struct DiscoverRequestPayload { + uint8_t prefixOnly; + uint8_t typeFilter; + uint32_t tag; + uint32_t since; +} DiscoverRequestPayload; + +typedef struct DiscoverResponsePayload { + uint8_t nodeType; + int8_t snr; + uint32_t tag; + uint8_t pubkey[32]; + uint8_t pubkeyLen; +} DiscoverResponsePayload; + +typedef struct AnonymousRequestPayload { + uint8_t destinationHash; + uint8_t pubKey[32]; + uint16_t cipherMAC; + uint8_t payloadLen; + uint8_t payload[149]; +} AnonymousRequestPayload; + +typedef enum PayloadVersion { + PAYLOAD_VERSION_0 = 0 << 6, + PAYLOAD_VERSION_1 = 1 << 6, + PAYLOAD_VERSION_2 = 2 << 6, + PAYLOAD_VERSION_3 = 3 << 6, +} PayloadVersion; + +typedef struct Path { + uint8_t pathLen; + uint8_t path[MAX_PATH_LEN]; +} Path; + +typedef struct FrameStruct { + uint8_t header; + uint8_t transportCodes[4]; + Path path; + size_t payloadLen; + uint8_t payload[184]; +} FrameStruct; + +typedef enum RequestType { + REQUEST_GET_STATS = 0x01, + REQUEST_KEEPALIVE = 0x02, + REQUEST_GET_TELEMETRY_DATA = 0x03, + REQUEST_GET_MIN_MAX_AVG = 0x04, + REQUEST_GET_ACCESS_LIST = 0x05, +} RequestType; + +typedef struct Request { + uint32_t timestamp; + uint8_t requestType; + uint8_t dataLen; + uint8_t data[180]; // hopefully correct len +} Request; + +typedef struct Response { + uint32_t tag; // sender timestamp + uint8_t dataLen; + uint8_t data[180]; // hopefully correct len +} Response; + +typedef struct Node { + uint8_t pubKey[32]; + char name[32]; + int32_t latitude; + int32_t longitude; + int32_t lastSeen; + char flags; +} Node; + +typedef struct { + char name[32]; + unsigned char pubKey[32]; + unsigned char secret[32]; + + int32_t gps_latitude; + int32_t gps_longitude; + + Path path; + + uint8_t flags; + uint8_t type; + + uint8_t authenticated; + + uint32_t last_seen_rt; // remote timestamp + uint32_t last_seen_lt; // local timestamp + + uint32_t sync_timestamp; +} NodeEntry; + +typedef struct EncryptedPayloadStruct { + uint8_t destinationHash; + uint8_t sourceHash; + uint16_t cipherMAC; + uint8_t payloadLen; + uint8_t payload[180]; + uint8_t type; + NodeEntry *remNode; + const Path *path; + const FrameStruct *origFrame; +} EncryptedPayloadStruct; + +typedef enum NodeType { + NODE_TYPE_CHAT_NODE = 1, + NODE_TYPE_REPEATER = 2, + NODE_TYPE_ROOM_SERVER = 3, + NODE_TYPE_SENSOR = 4 +} NodeType; + +typedef enum ControlDataFlags { + CONTROL_DATA_FLAG_TYPE_NODE_DISCOVER_REQ = 0x80, + CONTROL_DATA_FLAG_DISCOVER_RESP = 0x90 +} ControlDataFlags; + +typedef enum AdvertisementPayloadFlags { + ADVERTISEMENT_FLAG_IS_CHAT_NODE = 0x01, + ADVERTISEMENT_FLAG_IS_REAPEATER = 0x02, + ADVERTISEMENT_FLAG_IS_ROOM_SERVER = 0x03, + ADVERTISEMENT_FLAG_IS_SENSOR = 0x04, + ADVERTISEMENT_FLAG_HAS_LOCATION = 0x10, + ADVERTISEMENT_FLAG_RFU1 = 0x20, + ADVERTISEMENT_FLAG_RFU2 = 0x40, + ADVERTISEMENT_FLAG_HAS_NAME = 0x80, +} AdvertisementPayloadFlags; + +typedef struct AdvertisementPayload { + uint8_t pubKey[32]; + int32_t timestamp; + uint8_t signature[64]; + uint8_t valid; + uint8_t dataFlags; + int32_t latitude; + int32_t longitude; + int16_t rfu1; + int16_t rfu2; + char nodeName[32]; + +} AdvertisementPayload; + +typedef struct Extra { + uint8_t type; + uint8_t dataLen; + uint8_t data[180]; // hopefully long enough +} Extra; + +typedef struct ReturnedPathPayload { + Path path; + Extra extra; +} ReturnedPathPayload; + +typedef struct PlainTextMessagePayload { + uint32_t timestamp; + uint8_t textType; + uint8_t attempt; + uint8_t message[180]; // hopefully long enough +} PlainTextMessagePayload; + +typedef struct GroupTextMessage { + uint8_t channelHash; + uint8_t keyIndex; + int32_t timestamp; + uint8_t flags; + uint8_t text[190]; +} GroupTextMessage; + +typedef struct RepeaterStats { + uint16_t millivolts; + uint16_t txQueueLength; + int16_t noiseFloor; + int16_t lastRSSI; + uint32_t packetsReceivedCount; + uint32_t packetsSentCount; + uint32_t totalAirTimeSeconds; + uint32_t totalUpTimeSeconds; + uint32_t sentFloodCount, sentDirectCount; + uint32_t receivedFloodCount, receivedDirectCount; + uint16_t err_events; // was 'n_full_events' + int16_t lastSNR; // x 4 + uint16_t n_direct_dups, n_flood_dups; + uint32_t total_rx_air_time_secs; +} RepeaterStats; + +typedef struct Channel { + char name[32]; + uint8_t key[16]; + uint8_t hash; + int32_t timestamp; +} Channel; + +#endif diff --git a/User/meshcore/stats.c b/User/meshcore/stats.c new file mode 100644 index 0000000..44f0ad5 --- /dev/null +++ b/User/meshcore/stats.c @@ -0,0 +1,6 @@ +#include "stats.h" + +RepeaterStats stats; + +uint32_t startupTime = 0; +uint32_t tickAirtime = 0; \ No newline at end of file diff --git a/User/meshcore/stats.h b/User/meshcore/stats.h new file mode 100644 index 0000000..6d30224 --- /dev/null +++ b/User/meshcore/stats.h @@ -0,0 +1,11 @@ +#ifndef STATS_HEADER +#define STATS_HEADER +#include "meshcore/packetstructs.h" + +extern RepeaterStats stats; + +extern uint32_t startupTime; + +extern uint32_t tickAirtime; + +#endif \ No newline at end of file diff --git a/User/sx1262.c b/User/sx1262.c new file mode 100644 index 0000000..8829bb2 --- /dev/null +++ b/User/sx1262.c @@ -0,0 +1,991 @@ +#include +#include +#include +#include + +#include "sx1262.h" +#include "ch32v30x_gpio.h" +#include "util/log.h" +#define TAG "SX1262" + +// Global Stuff +uint8_t PacketParams[6]; +char txActive; +int txLost = 0; +char debugPrint; + +// Arduino compatible macros +#define delayMicroseconds(us) esp_rom_delay_us (us) +#define delay(ms) esp_rom_delay_us (ms * 1000) + +void LoRaError (int error) { + if (debugPrint) { + MESH_LOGE (TAG, "LoRaErrorDefault=%d", error); + } + while (1) { + iprintf("GONE WRONG\n"); + Delay_Ms(1); + } +} + +/* +// Convert bandwidth constant to float in kHz +float loraBwToFloat(uint8_t bw) { + switch (bw) { + case SX126X_LORA_BW_7_8: return 7.8f; + case SX126X_LORA_BW_10_4: return 10.4f; + case SX126X_LORA_BW_15_6: return 15.6f; + case SX126X_LORA_BW_20_8: return 20.8f; + case SX126X_LORA_BW_31_25: return 31.25f; + case SX126X_LORA_BW_41_7: return 41.7f; + case SX126X_LORA_BW_62_5: return 62.5f; + case SX126X_LORA_BW_125_0: return 125.0f; + case SX126X_LORA_BW_250_0: return 250.0f; + case SX126X_LORA_BW_500_0: return 500.0f; + default: return 0.0f; // unknown + } +} +*/ + +/* +// Convert float bandwidth (kHz) to constant +uint8_t floatToLoraBw(float bw) { + if (bw == 7.8f) return SX126X_LORA_BW_7_8; + if (bw == 10.4f) return SX126X_LORA_BW_10_4; + if (bw == 15.6f) return SX126X_LORA_BW_15_6; + if (bw == 20.8f) return SX126X_LORA_BW_20_8; + if (bw == 31.25f) return SX126X_LORA_BW_31_25; + if (bw == 41.7f) return SX126X_LORA_BW_41_7; + if (bw == 62.5f) return SX126X_LORA_BW_62_5; + if (bw == 125.0f) return SX126X_LORA_BW_125_0; + if (bw == 250.0f) return SX126X_LORA_BW_250_0; + if (bw == 500.0f) return SX126X_LORA_BW_500_0; + return 0xFF; // invalid +} +*/ +/* +// Convert coding rate constant to float +float loraCrToFloat(uint8_t cr) { + switch (cr) { + case SX126X_LORA_CR_4_5: return 4.0f / 5.0f; + case SX126X_LORA_CR_4_6: return 4.0f / 6.0f; + case SX126X_LORA_CR_4_7: return 4.0f / 7.0f; + case SX126X_LORA_CR_4_8: return 4.0f / 8.0f; + default: return 0.0f; + } +} +*/ + +/* + +// Convert float coding rate to constant +uint8_t floatToLoraCr(float cr) { + if (cr == 4.0f / 5.0f) return SX126X_LORA_CR_4_5; + if (cr == 4.0f / 6.0f) return SX126X_LORA_CR_4_6; + if (cr == 4.0f / 7.0f) return SX126X_LORA_CR_4_7; + if (cr == 4.0f / 8.0f) return SX126X_LORA_CR_4_8; + return 0xFF; +} +*/ +/* +// Convert MHz to Hz with limit check +uint32_t mhzToHzLimited(double freqMHz) { + double freqHz = freqMHz * 1000000.0; + if (freqHz > 860000000.0 && freqHz < 880000000.0) { + return (uint32_t)freqHz; + } + return 0; // out of range +} +*/ + +void LoRaInit (void) { + + txActive = 0; + debugPrint = 0; + + GPIO_InitTypeDef GPIO_InitStructure = {0}; + SPI_InitTypeDef SPI_InitStructure = {0}; + + + // RCC_AHBPeriphClockCmd (RCC_AHBPeriph_SDIO, ENABLE); + RCC_APB1PeriphClockCmd (RCC_APB1Periph_USART2 | RCC_APB1Periph_I2C2, ENABLE); + + RCC_APB2PeriphClockCmd (RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOE | RCC_APB2Periph_SPI1, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_4; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init (GPIOA, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init (GPIOA, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_Init (GPIOA, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init (GPIOA, &GPIO_InitStructure); + + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_Init (GPIOE, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_Init (GPIOE, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING; + GPIO_Init (GPIOE, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_Init (GPIOE, &GPIO_InitStructure); + + + SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex; + + SPI_InitStructure.SPI_Mode = SPI_Mode_Master; + + + SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b; + SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low; + SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge; + SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; + SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_16; + SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; + SPI_InitStructure.SPI_CRCPolynomial = 7; + SPI_Init (SPI1, &SPI_InitStructure); + + GPIO_WriteBit (GPIOE, GPIO_Pin_3, 1); + + SPI_Cmd (SPI1, ENABLE); +} + +void spi_write_byte (uint8_t *DataOut, size_t DataLength) { + spi_read_byte (NULL, DataOut, DataLength); +} + +// Full-duplex transfer: TX and RX buffers +void spi_read_byte (uint8_t *rx, const uint8_t *tx, size_t len) { + GPIO_WriteBit (GPIOA, GPIO_Pin_4, 0); + for (size_t i = 0; i < len; i++) { + uint8_t out = tx ? tx[i] : 0xFF; + + // Wait TX ready + while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_TXE) == RESET); + if (debugPrint) { + MESH_LOGV (TAG, "Sent %02X over spi.\n", out); + } + SPI_I2S_SendData (SPI1, out); + // Wait RX ready + + while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_RXNE) == RESET); + + uint8_t in = (uint8_t)SPI_I2S_ReceiveData (SPI1); + if (debugPrint) { + MESH_LOGV (TAG, "Got %02X over spi.\n", in); + } + if (rx) + rx[i] = in; + } + GPIO_WriteBit (GPIOA, GPIO_Pin_4, 1); +} + +// Full-duplex transfer: TX and RX buffers +void spi_read_byte_offs (uint8_t *rx, const uint8_t *tx, size_t len, uint8_t off) { + GPIO_WriteBit (GPIOA, GPIO_Pin_4, 0); + for (size_t i = 0; i < len; i++) { + uint8_t out = 0xFF; + if (i < off) { + out = tx ? tx[i] : 0xFF; + } + + // Wait TX ready + while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_TXE) == RESET); + if (debugPrint) { + MESH_LOGV (TAG, "Sent %02X over spi.\n", out); + } + SPI_I2S_SendData (SPI1, out); + // Wait RX ready + + while (SPI_I2S_GetFlagStatus (SPI1, SPI_I2S_FLAG_RXNE) == RESET); + + uint8_t in = (uint8_t)SPI_I2S_ReceiveData (SPI1); + if (debugPrint) { + MESH_LOGV (TAG, "Got %02X over spi.\n", in); + } + if (rx && i >= off) { + rx[i - off] = in; + } + } + GPIO_WriteBit (GPIOA, GPIO_Pin_4, 1); +} + +int16_t LoRaBegin (uint32_t frequencyInHz, int8_t txPowerInDbm, uint16_t tcxoVoltage, char useRegulatorLDO) { + if (txPowerInDbm > 22) { + txPowerInDbm = 22; + } + if (txPowerInDbm < -3) { + txPowerInDbm = -3; + } + + ResetLora(); + + uint8_t wk[2]; + ReadRegister (SX126X_REG_LORA_SYNC_WORD_MSB, wk, 2); // 0x0740 + uint16_t syncWord = (wk[0] << 8) + wk[1]; + MESH_LOGI (TAG, "syncWord=0x%x", syncWord); + if (syncWord != SX126X_SYNC_WORD_PUBLIC && syncWord != SX126X_SYNC_WORD_PRIVATE) { + MESH_LOGE (TAG, "SX126x error, maybe no SPI connection"); + return ERR_INVALID_MODE; + } + + MESH_LOGI (TAG, "SX126x installed"); + SetStandby (SX126X_STANDBY_RC); + + SetDio2AsRfSwitchCtrl (1); + //MESH_LOGI (TAG, "tcxoVoltage=%f", tcxoVoltage); + // set TCXO control, if requested + if (tcxoVoltage > 0) { + SetDio3AsTcxoCtrl (tcxoVoltage, RADIO_TCXO_SETUP_TIME); // Configure the radio to use a TCXO controlled by DIO3 + } + + Calibrate (SX126X_CALIBRATE_IMAGE_ON | SX126X_CALIBRATE_ADC_BULK_P_ON | SX126X_CALIBRATE_ADC_BULK_N_ON | SX126X_CALIBRATE_ADC_PULSE_ON | SX126X_CALIBRATE_PLL_ON | SX126X_CALIBRATE_RC13M_ON | SX126X_CALIBRATE_RC64K_ON); + + MESH_LOGI (TAG, "useRegulatorLDO=%d", useRegulatorLDO); + if (useRegulatorLDO) { + SetRegulatorMode (SX126X_REGULATOR_LDO); // set regulator mode: LDO + } else { + SetRegulatorMode (SX126X_REGULATOR_DC_DC); // set regulator mode: DC-DC + } + + SetBufferBaseAddress (0, 0); + SetPaConfig (0x04, 0x07, 0x00, 0x01); // PA Optimal Settings +22 dBm + SetOvercurrentProtection (60); // current max 60mA for the whole device + SetPowerConfig (txPowerInDbm, SX126X_PA_RAMP_200U); // 0 fuer Empfaenger + SetRfFrequency (frequencyInHz); + return ERR_NONE; +} + +void FixInvertedIQ (uint8_t iqConfig) { + // fixes IQ configuration for inverted IQ + // see SX1262/SX1268 datasheet, chapter 15 Known Limitations, section 15.4 for details + // When exchanging LoRa packets with inverted IQ polarity, some packet losses may be observed for longer packets. + // Workaround: Bit 2 at address 0x0736 must be set to: + // “0†when using inverted IQ polarity (see the SetPacketParam(...) command) + // “1†when using standard IQ polarity + + // read current IQ configuration + uint8_t iqConfigCurrent = 0; + ReadRegister (SX126X_REG_IQ_POLARITY_SETUP, &iqConfigCurrent, 1); // 0x0736 + + // set correct IQ configuration + // if(iqConfig == SX126X_LORA_IQ_STANDARD) { + if (iqConfig == SX126X_LORA_IQ_INVERTED) { + iqConfigCurrent &= 0xFB; // using inverted IQ polarity + } else { + iqConfigCurrent |= 0x04; // using standard IQ polarity + } + + // update with the new value + WriteRegister (SX126X_REG_IQ_POLARITY_SETUP, &iqConfigCurrent, 1); // 0x0736 +} + +void LoRaConfig (uint8_t spreadingFactor, uint8_t bandwidth, uint8_t codingRate, uint16_t preambleLength, uint8_t payloadLen, char crcOn, char invertIrq) { + SetStopRxTimerOnPreambleDetect (0); + SetLoRaSymbNumTimeout (0); + SetPacketType (SX126X_PACKET_TYPE_LORA); // SX126x.ModulationParams.PacketType : MODEM_LORA + uint8_t ldro = 0; // LowDataRateOptimize OFF + SetModulationParams (spreadingFactor, bandwidth, codingRate, ldro); + + PacketParams[0] = (preambleLength >> 8) & 0xFF; + PacketParams[1] = preambleLength; + if (payloadLen) { + PacketParams[2] = 0x01; // Fixed length packet (implicit header) + PacketParams[3] = payloadLen; + } else { + PacketParams[2] = 0x00; // Variable length packet (explicit header) + PacketParams[3] = 0xFF; + } + + if (crcOn) + PacketParams[4] = SX126X_LORA_CRC_ON; + else + PacketParams[4] = SX126X_LORA_CRC_OFF; + + if (invertIrq) + PacketParams[5] = 0x01; // Inverted LoRa I and Q signals setup + else + PacketParams[5] = 0x00; // Standard LoRa I and Q signals setup + + // fixes IQ configuration for inverted IQ + FixInvertedIQ (PacketParams[5]); + + WriteCommand (SX126X_CMD_SET_PACKET_PARAMS, PacketParams, 6); // 0x8C + + // Do not use DIO interruptst + SetDioIrqParams (SX126X_IRQ_ALL, // all interrupts enabled + SX126X_IRQ_NONE, // interrupts on DIO1 + SX126X_IRQ_NONE, // interrupts on DIO2 + SX126X_IRQ_NONE // interrupts on DIO3 + ); + + + MESH_LOGI (TAG, "Almost done setting LoRa"); + // Receive state no receive timeoout + SetRx (0xFFFFFF); +} + +void LoRaDebugPrint (char enable) { + debugPrint = enable; +} + +uint8_t LoRaReceive (uint8_t *pData, int16_t len) { + uint8_t rxLen = 0; + uint16_t irqRegs = GetIrqStatus(); + // uint8_t status = GetStatus(); + + if (irqRegs & SX126X_IRQ_RX_DONE) { + // ClearIrqStatus(SX126X_IRQ_RX_DONE); + ClearIrqStatus (SX126X_IRQ_ALL); + rxLen = ReadBuffer (pData, len); + } + + return rxLen; +} + +char LoRaSend (uint8_t *pData, int16_t len, uint8_t mode) { + uint16_t irqStatus; + char rv = 0; + + if (txActive == 0) { + txActive = 1; + if (PacketParams[2] == 0x00) { // Variable length packet (explicit header) + PacketParams[3] = len; + } + WriteCommand (SX126X_CMD_SET_PACKET_PARAMS, PacketParams, 6); // 0x8C + + // ClearIrqStatus(SX126X_IRQ_TX_DONE | SX126X_IRQ_TIMEOUT); + ClearIrqStatus (SX126X_IRQ_ALL); + + WriteBuffer (pData, len); + SetTx (5000); + + if (mode & SX126x_TXMODE_SYNC) { + irqStatus = GetIrqStatus(); + while ((!(irqStatus & SX126X_IRQ_TX_DONE)) && (!(irqStatus & SX126X_IRQ_TIMEOUT))) { + Delay_Ms(1); + irqStatus = GetIrqStatus(); + } + if (debugPrint) { + MESH_LOGI (TAG, "irqStatus=0x%x", irqStatus); + if (irqStatus & SX126X_IRQ_TX_DONE) { + MESH_LOGI (TAG, "SX126X_IRQ_TX_DONE"); + } + if (irqStatus & SX126X_IRQ_TIMEOUT) { + MESH_LOGI (TAG, "SX126X_IRQ_TIMEOUT"); + } + } + txActive = 0; + + SetRx (0xFFFFFF); + + if (irqStatus & SX126X_IRQ_TX_DONE) { + rv = 1; + } + } else { + rv = 1; + } + } + if (debugPrint) { + MESH_LOGI (TAG, "Send rv=0x%x", rv); + } + if (rv == 0) + txLost++; + return rv; +} + +char ReceiveMode (void) { + uint16_t irq; + char rv = 0; + + if (txActive == 0) { + rv = 1; + } else { + irq = GetIrqStatus(); + if (irq & (SX126X_IRQ_TX_DONE | SX126X_IRQ_TIMEOUT)) { + SetRx (0xFFFFFF); + txActive = 0; + rv = 1; + } + } + + return rv; +} + +void GetPacketStatus (int8_t *rssiPacket, int8_t *snrPacket, int8_t *rawSnr) { + uint8_t buf[4]; + ReadCommand (SX126X_CMD_GET_PACKET_STATUS, buf, 4); // 0x14 + *rssiPacket = (buf[3] >> 1) * -1; + (buf[2] < 128) ? (*snrPacket = buf[2] >> 2) : (*snrPacket = ((buf[2] - 256) >> 2)); + *rawSnr = buf[2]; +} + +void SetTxPower (int8_t txPowerInDbm) { + SetPowerConfig (txPowerInDbm, SX126X_PA_RAMP_200U); +} + +void ResetLora (void) { + Delay_Ms(10); + GPIO_WriteBit (GPIOE, GPIO_Pin_3, 0); + Delay_Ms(20); + GPIO_WriteBit (GPIOE, GPIO_Pin_3, 1); + MESH_LOGW (TAG, "Waiting for idle"); + Delay_Ms(10); + // ensure BUSY is low (state meachine ready) + WaitForIdle (BUSY_WAIT, "Reset", 1); +} + +void Wakeup (void) { + GetStatus(); +} + +void SetStandby (uint8_t mode) { + uint8_t data = mode; + WriteCommand (SX126X_CMD_SET_STANDBY, &data, 1); // 0x80 +} + +uint8_t GetStatus (void) { + uint8_t rv; + ReadCommand (SX126X_CMD_GET_STATUS, &rv, 1); // 0xC0 + return rv; +} + +static uint8_t voltage_to_tcxo(uint16_t voltage) +{ + if (voltage == 1650) return SX126X_DIO3_OUTPUT_1_6; + if (voltage == 1750) return SX126X_DIO3_OUTPUT_1_7; + if (voltage == 1850) return SX126X_DIO3_OUTPUT_1_8; + if (voltage == 2300) return SX126X_DIO3_OUTPUT_2_2; + if (voltage == 2500) return SX126X_DIO3_OUTPUT_2_4; + if (voltage == 2850) return SX126X_DIO3_OUTPUT_2_7; + if (voltage == 3100) return SX126X_DIO3_OUTPUT_3_0; + return SX126X_DIO3_OUTPUT_3_3; +} + +void SetDio3AsTcxoCtrl (uint16_t voltage, uint32_t delay) { + uint8_t buf[4]; + + // buf[0] = tcxoVoltage & 0x07; + buf[0] = voltage_to_tcxo(voltage); + + uint32_t delayValue = (delay * 1000) / 15625; + + buf[1] = (delayValue >> 16) & 0xFF; + buf[2] = (delayValue >> 8) & 0xFF; + buf[3] = delayValue & 0xFF; + + WriteCommand (SX126X_CMD_SET_DIO3_AS_TCXO_CTRL, buf, 4); // 0x97 +} + +void Calibrate (uint8_t calibParam) { + uint8_t data = calibParam; + WriteCommand (SX126X_CMD_CALIBRATE, &data, 1); // 0x89 +} +void SetDio2AsRfSwitchCtrl (uint8_t enable) { + uint8_t data = enable; + WriteCommand (SX126X_CMD_SET_DIO2_AS_RF_SWITCH_CTRL, &data, 1); // 0x9D +} + +void SetRfFrequency (uint32_t frequency) { + uint8_t buf[4]; + + CalibrateImage (frequency); + + //freq = (uint32_t)((double)frequency / (double)FREQ_STEP); + uint32_t freq = ((uint64_t)frequency << 25) / XTAL_FREQ; + buf[0] = (uint8_t)((freq >> 24) & 0xFF); + buf[1] = (uint8_t)((freq >> 16) & 0xFF); + buf[2] = (uint8_t)((freq >> 8) & 0xFF); + buf[3] = (uint8_t)(freq & 0xFF); + WriteCommand (SX126X_CMD_SET_RF_FREQUENCY, buf, 4); // 0x86 +} + +void CalibrateImage (uint32_t frequency) { + uint8_t calFreq[2]; + + if (frequency > 900000000) { + calFreq[0] = 0xE1; + calFreq[1] = 0xE9; + } else if (frequency > 850000000) { + calFreq[0] = 0xD7; + calFreq[1] = 0xDB; + } else if (frequency > 770000000) { + calFreq[0] = 0xC1; + calFreq[1] = 0xC5; + } else if (frequency > 460000000) { + calFreq[0] = 0x75; + calFreq[1] = 0x81; + } else if (frequency > 425000000) { + calFreq[0] = 0x6B; + calFreq[1] = 0x6F; + } + WriteCommand (SX126X_CMD_CALIBRATE_IMAGE, calFreq, 2); // 0x98 +} + +void SetRegulatorMode (uint8_t mode) { + uint8_t data = mode; + WriteCommand (SX126X_CMD_SET_REGULATOR_MODE, &data, 1); // 0x96 +} + +void SetBufferBaseAddress (uint8_t txBaseAddress, uint8_t rxBaseAddress) { + uint8_t buf[2]; + + buf[0] = txBaseAddress; + buf[1] = rxBaseAddress; + WriteCommand (SX126X_CMD_SET_BUFFER_BASE_ADDRESS, buf, 2); // 0x8F +} + +void SetPowerConfig (int8_t power, uint8_t rampTime) { + uint8_t buf[2]; + + if (power > 22) { + power = 22; + } else if (power < -3) { + power = -3; + } + + buf[0] = power; + buf[1] = (uint8_t)rampTime; + WriteCommand (SX126X_CMD_SET_TX_PARAMS, buf, 2); // 0x8E +} + +void SetPaConfig (uint8_t paDutyCycle, uint8_t hpMax, uint8_t deviceSel, uint8_t paLut) { + uint8_t buf[4]; + + buf[0] = paDutyCycle; + buf[1] = hpMax; + buf[2] = deviceSel; + buf[3] = paLut; + WriteCommand (SX126X_CMD_SET_PA_CONFIG, buf, 4); // 0x95 +} + +void SetOvercurrentProtection(uint16_t current_mA) +{ + if (current_mA <= 140) + { + uint8_t buf = (current_mA * 10) / 25; + WriteRegister(SX126X_REG_OCP_CONFIGURATION, &buf, 1); + } +} + +void SetSyncWord (int16_t sync) { + uint8_t buf[2]; + + buf[0] = (uint8_t)((sync >> 8) & 0x00FF); + buf[1] = (uint8_t)(sync & 0x00FF); + WriteRegister (SX126X_REG_LORA_SYNC_WORD_MSB, buf, 2); // 0x0740 +} + +void SetDioIrqParams (uint16_t irqMask, uint16_t dio1Mask, uint16_t dio2Mask, uint16_t dio3Mask) { + uint8_t buf[8]; + + buf[0] = (uint8_t)((irqMask >> 8) & 0x00FF); + buf[1] = (uint8_t)(irqMask & 0x00FF); + buf[2] = (uint8_t)((dio1Mask >> 8) & 0x00FF); + buf[3] = (uint8_t)(dio1Mask & 0x00FF); + buf[4] = (uint8_t)((dio2Mask >> 8) & 0x00FF); + buf[5] = (uint8_t)(dio2Mask & 0x00FF); + buf[6] = (uint8_t)((dio3Mask >> 8) & 0x00FF); + buf[7] = (uint8_t)(dio3Mask & 0x00FF); + WriteCommand (SX126X_CMD_SET_DIO_IRQ_PARAMS, buf, 8); // 0x08 +} + +void SetStopRxTimerOnPreambleDetect (char enable) { + MESH_LOGI (TAG, "SetStopRxTimerOnPreambleDetect enable=%d", enable); + // uint8_t data = (uint8_t)enable; + uint8_t data = 0; + if (enable) + data = 1; + WriteCommand (SX126X_CMD_STOP_TIMER_ON_PREAMBLE, &data, 1); // 0x9F +} + +void SetLoRaSymbNumTimeout (uint8_t SymbNum) { + uint8_t data = SymbNum; + WriteCommand (SX126X_CMD_SET_LORA_SYMB_NUM_TIMEOUT, &data, 1); // 0xA0 +} + +void SetPacketType (uint8_t packetType) { + uint8_t data = packetType; + WriteCommand (SX126X_CMD_SET_PACKET_TYPE, &data, 1); // 0x01 +} + +void SetModulationParams (uint8_t spreadingFactor, uint8_t bandwidth, uint8_t codingRate, uint8_t lowDataRateOptimize) { + uint8_t data[4]; + // currently only LoRa supported + data[0] = spreadingFactor; + data[1] = bandwidth; + data[2] = codingRate; + data[3] = lowDataRateOptimize; + WriteCommand (SX126X_CMD_SET_MODULATION_PARAMS, data, 4); // 0x8B +} + +void SetCadParams (uint8_t cadSymbolNum, uint8_t cadDetPeak, uint8_t cadDetMin, uint8_t cadExitMode, uint32_t cadTimeout) { + uint8_t data[7]; + data[0] = cadSymbolNum; + data[1] = cadDetPeak; + data[2] = cadDetMin; + data[3] = cadExitMode; + data[4] = (uint8_t)((cadTimeout >> 16) & 0xFF); + data[5] = (uint8_t)((cadTimeout >> 8) & 0xFF); + data[6] = (uint8_t)(cadTimeout & 0xFF); + WriteCommand (SX126X_CMD_SET_CAD_PARAMS, data, 7); // 0x88 +} + +void SetCad() { + uint8_t data = 0; + WriteCommand (SX126X_CMD_SET_CAD, &data, 0); // 0xC5 +} + +uint16_t GetIrqStatus (void) { + uint8_t data[3]; + ReadCommand (SX126X_CMD_GET_IRQ_STATUS, data, 3); // 0x12 + return (data[1] << 8) | data[2]; +} + +void ClearIrqStatus (uint16_t irq) { + uint8_t buf[2]; + + buf[0] = (uint8_t)(((uint16_t)irq >> 8) & 0x00FF); + buf[1] = (uint8_t)((uint16_t)irq & 0x00FF); + WriteCommand (SX126X_CMD_CLEAR_IRQ_STATUS, buf, 2); // 0x02 +} + +void SetRx (uint32_t timeout) { + if (debugPrint) { + MESH_LOGI (TAG, "----- SetRx timeout=%d", timeout); + } + SetStandby (SX126X_STANDBY_RC); + uint8_t buf[3]; + buf[0] = (uint8_t)((timeout >> 16) & 0xFF); + buf[1] = (uint8_t)((timeout >> 8) & 0xFF); + buf[2] = (uint8_t)(timeout & 0xFF); + WriteCommand (SX126X_CMD_SET_RX, buf, 3); // 0x82 + + for (int retry = 0; retry < 10; retry++) { + if ((GetStatus() & 0x70) == 0x50) + break; + Delay_Ms(1); + } + if ((GetStatus() & 0x70) != 0x50) { + MESH_LOGE (TAG, "SetRx Illegal Status"); + LoRaError (ERR_INVALID_SETRX_STATE); + } +} + +void SetTx (uint32_t timeoutInMs) { + if (debugPrint) { + MESH_LOGI (TAG, "----- SetTx timeoutInMs=%d", timeoutInMs); + } + SetStandby (SX126X_STANDBY_RC); + uint8_t buf[3]; + uint32_t tout = timeoutInMs; + if (timeoutInMs != 0) { + uint32_t timeoutInUs = timeoutInMs * 1000; + tout = timeoutInUs * 64; + } + if (debugPrint) { + MESH_LOGI (TAG, "SetTx timeoutInMs=%d" + " tout=%d", + timeoutInMs, tout); + } + buf[0] = (uint8_t)((tout >> 16) & 0xFF); + buf[1] = (uint8_t)((tout >> 8) & 0xFF); + buf[2] = (uint8_t)(tout & 0xFF); + WriteCommand (SX126X_CMD_SET_TX, buf, 3); // 0x83 + + if (debugPrint) { + MESH_LOGD(TAG, "Written command, retrying"); + } + + for (int retry = 0; retry < 20; retry++) { + if ((GetStatus() & 0x70) == 0x60) + break; + Delay_Ms(1); + } + if (debugPrint) { + MESH_LOGI(TAG, "Broke out"); + } + if ((GetStatus() & 0x70) != 0x60) { + MESH_LOGE (TAG, "SetTx Illegal Status"); + LoRaError (ERR_INVALID_SETTX_STATE); + } +} + +int GetPacketLost() { + return txLost; +} + +uint8_t GetRssiInst() { + uint8_t buf[2]; + ReadCommand (SX126X_CMD_GET_RSSI_INST, buf, 2); // 0x15 + return buf[1]; +} + +void GetRxBufferStatus (uint8_t *payloadLength, uint8_t *rxStartBufferPointer) { + uint8_t buf[3]; + ReadCommand (SX126X_CMD_GET_RX_BUFFER_STATUS, buf, 3); // 0x13 + *payloadLength = buf[1]; + *rxStartBufferPointer = buf[2]; +} + +void WaitForIdleBegin (unsigned long timeout, char *text) { + // ensure BUSY is low (state meachine ready) + char stop = 0; + for (int retry = 0; retry < 10; retry++) { + if (retry == 9) + stop = 1; + char ret = WaitForIdle (BUSY_WAIT, text, stop); + if (ret == 1) + break; + MESH_LOGW (TAG, "WaitForIdle fail retry=%d", retry); + Delay_Ms(10); + } +} + +char WaitForIdle (unsigned long timeout, char *text, char stop) { + char ret = 1; + Delay_Ms(1); + for (unsigned long i = 0; i < timeout; i++) { + if (GPIO_ReadInputDataBit (GPIOE, GPIO_Pin_1) == 0) + break; + Delay_Ms(10); + } + + if (GPIO_ReadInputDataBit (GPIOE, GPIO_Pin_1)) { + if (stop) { + MESH_LOGE (TAG, "WaitForIdle Timeout text=%s timeout=%lu", text, timeout); + LoRaError (ERR_IDLE_TIMEOUT); + } else { + MESH_LOGW (TAG, "WaitForIdle Timeout text=%s timeout=%lu", text, timeout); + ret = 0; + } + } + return ret; +} + +/* +uint8_t ReadBuffer (uint8_t *rxData, int16_t rxDataLen) { + uint8_t offset = 0; + uint8_t payloadLength = 0; + GetRxBufferStatus (&payloadLength, &offset); + if (payloadLength > rxDataLen) { + MESH_LOGW (TAG, "ReadBuffer rxDataLen too small. payloadLength=%d rxDataLen=%d", payloadLength, rxDataLen); + return 0; + } + + // ensure BUSY is low (state meachine ready) + WaitForIdle (BUSY_WAIT, "start ReadBuffer", 1); + + // start transfer + uint8_t *buf; + buf = malloc (payloadLength + 3); + if (buf != NULL) { + buf[0] = SX126X_CMD_READ_BUFFER; // 0x1E + buf[1] = offset; // offset in rx fifo + buf[2] = SX126X_CMD_NOP; + memset (&buf[3], SX126X_CMD_NOP, payloadLength); + spi_read_byte (buf, buf, payloadLength + 3); + memcpy (rxData, &buf[3], payloadLength); + free (buf); + } else { + MESH_LOGE (TAG, "ReadBuffer malloc fail"); + payloadLength = 0; + } + + // wait for BUSY to go low + WaitForIdle (BUSY_WAIT, "end ReadBuffer", 0); + + return payloadLength; +}*/ + + +uint8_t ReadBuffer (uint8_t *rxData, int16_t rxDataLen) { + uint8_t offset = 0; + uint8_t payloadLength = 0; + GetRxBufferStatus (&payloadLength, &offset); + + if (payloadLength > rxDataLen) { + MESH_LOGW (TAG, "ReadBuffer rxDataLen too small. payloadLength=%d rxDataLen=%d", payloadLength, rxDataLen); + return 0; + } + + WaitForIdle (BUSY_WAIT, "start ReadBuffer", 1); + + uint8_t cmd[3] = {SX126X_CMD_READ_BUFFER, offset, SX126X_CMD_NOP}; + + spi_read_byte_offs (rxData, cmd, rxDataLen, sizeof (cmd)); + + WaitForIdle (BUSY_WAIT, "end ReadBuffer", 0); + + return payloadLength; +} + +void WriteBuffer (uint8_t *txData, int16_t txDataLen) { + // ensure BUSY is low (state meachine ready) + WaitForIdle (BUSY_WAIT, "start WriteBuffer", 1); + + // start transfer + uint8_t *buf; + buf = malloc (txDataLen + 2); + if (buf != NULL) { + buf[0] = SX126X_CMD_WRITE_BUFFER; // 0x0E + buf[1] = 0; // offset in tx fifo + memcpy (&buf[2], txData, txDataLen); + spi_write_byte (buf, txDataLen + 2); + free (buf); + } else { + MESH_LOGE (TAG, "WriteBuffer malloc fail"); + } + + // wait for BUSY to go low + WaitForIdle (BUSY_WAIT, "end WriteBuffer", 0); +} + +void WriteRegister (uint16_t reg, uint8_t *data, uint8_t numBytes) { + // ensure BUSY is low (state meachine ready) + WaitForIdle (BUSY_WAIT, "start WriteRegister", 1); + + if (debugPrint) { + MESH_LOGI (TAG, "WriteRegister: REG=0x%02x", reg); + for (uint8_t n = 0; n < numBytes; n++) { + MESH_LOGI (TAG, "DataOut:%02x ", data[n]); + } + } + + // start transfer + uint8_t buf[16]; + buf[0] = SX126X_CMD_WRITE_REGISTER; + buf[1] = (reg & 0xFF00) >> 8; + buf[2] = reg & 0xff; + memcpy (&buf[3], data, numBytes); + spi_write_byte (buf, 3 + numBytes); + + // wait for BUSY to go low + WaitForIdle (BUSY_WAIT, "end WriteRegister", 0); +} + +void ReadRegister (uint16_t reg, uint8_t *data, uint8_t numBytes) { + // ensure BUSY is low (state meachine ready) + WaitForIdle (BUSY_WAIT, "start ReadRegister", 1); + + if (debugPrint) { + MESH_LOGI (TAG, "ReadRegister: REG=0x%02x", reg); + } + + // start transfer + uint8_t buf[16]; + uint8_t buf2[16]; + memset (buf, SX126X_CMD_NOP, sizeof (buf)); + memset (buf2, SX126X_CMD_NOP, sizeof (buf2)); + buf[0] = SX126X_CMD_READ_REGISTER; + buf[1] = (reg & 0xFF00) >> 8; + buf[2] = reg & 0xff; + if (debugPrint) { + MESH_LOGI (TAG, "Reading bytes"); + } + + spi_read_byte (buf2, buf, 4 + numBytes); + MESH_LOGI (TAG, "read a byte"); + memcpy (data, &buf2[4], numBytes); + if (debugPrint) { + for (uint8_t n = 0; n < numBytes; n++) { + MESH_LOGI (TAG, "DataIn:%02x ", data[n]); + } + } + + // wait for BUSY to go low + WaitForIdle (BUSY_WAIT, "end ReadRegister", 0); +} + +// WriteCommand with retry +void WriteCommand (uint8_t cmd, uint8_t *data, uint8_t numBytes) { + uint8_t status; + for (int retry = 1; retry < 10; retry++) { + status = WriteCommand2 (cmd, data, numBytes); + if (debugPrint) { + MESH_LOGD (TAG, "status=%02x", status); + } + if (status == 0) + break; + MESH_LOGW (TAG, "WriteCommand2 status=%02x retry=%d", status, retry); + } + if (status != 0) { + MESH_LOGE (TAG, "SPI Transaction error:0x%02x", status); + LoRaError (ERR_SPI_TRANSACTION); + } +} + +uint8_t WriteCommand2 (uint8_t cmd, uint8_t *data, uint8_t numBytes) { + // ensure BUSY is low (state meachine ready) + WaitForIdle (BUSY_WAIT, "start WriteCommand2", 1); + + if (debugPrint) { + MESH_LOGI (TAG, "WriteCommand: CMD=0x%02x", cmd); + } + + // start transfer + uint8_t buf[16]; + buf[0] = cmd; + memcpy (&buf[1], data, numBytes); + spi_read_byte (buf, buf, numBytes + 1); + + uint8_t status = 0; + uint8_t cmd_status = buf[1] & 0xe; + + switch (cmd_status) { + case SX126X_STATUS_CMD_TIMEOUT: + case SX126X_STATUS_CMD_INVALID: + case SX126X_STATUS_CMD_FAILED: + status = cmd_status; + break; + + case 0: + case 7: + status = SX126X_STATUS_SPI_FAILED; + break; + // default: break; // success + } + + // wait for BUSY to go low + WaitForIdle (BUSY_WAIT, "end WriteCommand2", 0); + return status; +} + +void ReadCommand (uint8_t cmd, uint8_t *data, uint8_t numBytes) { + // ensure BUSY is low (state meachine ready) + WaitForIdleBegin (BUSY_WAIT, "start ReadCommand"); + + if (debugPrint) { + MESH_LOGI (TAG, "ReadCommand: CMD=0x%02x", cmd); + } + + // start transfer + uint8_t buf[16]; + memset (buf, SX126X_CMD_NOP, sizeof (buf)); + buf[0] = cmd; + spi_read_byte (buf, buf, 1 + numBytes); + if (data != NULL && numBytes) + memcpy (data, &buf[1], numBytes); + + // wait for BUSY to go low + Delay_Ms(1); + WaitForIdle (BUSY_WAIT, "end ReadCommand", 0); +} \ No newline at end of file diff --git a/User/sx1262.h b/User/sx1262.h new file mode 100644 index 0000000..55aa4f4 --- /dev/null +++ b/User/sx1262.h @@ -0,0 +1,452 @@ +#ifndef _RA01S_H +#define _RA01S_H + +// return values +#define ERR_NONE 0 +#define ERR_PACKET_TOO_LONG 1 +#define ERR_UNKNOWN 2 +#define ERR_TX_TIMEOUT 3 +#define ERR_RX_TIMEOUT 4 +#define ERR_CRC_MISMATCH 5 +#define ERR_WRONG_MODEM 6 +#define ERR_INVALID_BANDWIDTH 7 +#define ERR_INVALID_SPREADING_FACTOR 8 +#define ERR_INVALID_CODING_RATE 9 +#define ERR_INVALID_FREQUENCY_DEVIATION 10 +#define ERR_INVALID_BIT_RATE 11 +#define ERR_INVALID_RX_BANDWIDTH 12 +#define ERR_INVALID_DATA_SHAPING 13 +#define ERR_INVALID_SYNC_WORD 14 +#define ERR_INVALID_OUTPUT_POWER 15 +#define ERR_INVALID_MODE 16 +#define ERR_INVALID_TRANCEIVER 17 +#define ERR_INVALID_SETRX_STATE 18 +#define ERR_INVALID_SETTX_STATE 19 +#define ERR_IDLE_TIMEOUT 20 +#define ERR_SPI_TRANSACTION 21 + +// SX126X physical layer properties +#define XTAL_FREQ 32000000 +#define FREQ_DIV 33554432UL + +#define LOW 0 +#define HIGH 1 +#define BUSY_WAIT 5000 + +// SX126X Model +#define SX1261_TRANCEIVER 0x01 +#define SX1262_TRANCEIVER 0x02 +#define SX1268_TRANCEIVER 0x08 + +// SX126X SPI commands +// operational modes commands +#define SX126X_CMD_NOP 0x00 +#define SX126X_CMD_SET_SLEEP 0x84 +#define SX126X_CMD_SET_STANDBY 0x80 +#define SX126X_CMD_SET_FS 0xC1 +#define SX126X_CMD_SET_TX 0x83 +#define SX126X_CMD_SET_RX 0x82 +#define SX126X_CMD_STOP_TIMER_ON_PREAMBLE 0x9F +#define SX126X_CMD_SET_RX_DUTY_CYCLE 0x94 +#define SX126X_CMD_SET_CAD 0xC5 +#define SX126X_CMD_SET_TX_CONTINUOUS_WAVE 0xD1 +#define SX126X_CMD_SET_TX_INFINITE_PREAMBLE 0xD2 +#define SX126X_CMD_SET_REGULATOR_MODE 0x96 +#define SX126X_CMD_CALIBRATE 0x89 +#define SX126X_CMD_CALIBRATE_IMAGE 0x98 +#define SX126X_CMD_SET_PA_CONFIG 0x95 +#define SX126X_CMD_SET_RX_TX_FALLBACK_MODE 0x93 + +// register and buffer access commands +#define SX126X_CMD_WRITE_REGISTER 0x0D +#define SX126X_CMD_READ_REGISTER 0x1D +#define SX126X_CMD_WRITE_BUFFER 0x0E +#define SX126X_CMD_READ_BUFFER 0x1E + +// DIO and IRQ control +#define SX126X_CMD_SET_DIO_IRQ_PARAMS 0x08 +#define SX126X_CMD_GET_IRQ_STATUS 0x12 +#define SX126X_CMD_CLEAR_IRQ_STATUS 0x02 +#define SX126X_CMD_SET_DIO2_AS_RF_SWITCH_CTRL 0x9D +#define SX126X_CMD_SET_DIO3_AS_TCXO_CTRL 0x97 + +// RF, modulation and packet commands +#define SX126X_CMD_SET_RF_FREQUENCY 0x86 +#define SX126X_CMD_SET_PACKET_TYPE 0x8A +#define SX126X_CMD_GET_PACKET_TYPE 0x11 +#define SX126X_CMD_SET_TX_PARAMS 0x8E +#define SX126X_CMD_SET_MODULATION_PARAMS 0x8B +#define SX126X_CMD_SET_PACKET_PARAMS 0x8C +#define SX126X_CMD_SET_CAD_PARAMS 0x88 +#define SX126X_CMD_SET_BUFFER_BASE_ADDRESS 0x8F +#define SX126X_CMD_SET_LORA_SYMB_NUM_TIMEOUT 0xA0 + +#define SX126X_PA_CONFIG_SX1261 0x01 +#define SX126X_PA_CONFIG_SX1262 0x00 + +// status commands +#define SX126X_CMD_GET_STATUS 0xC0 +#define SX126X_CMD_GET_RSSI_INST 0x15 +#define SX126X_CMD_GET_RX_BUFFER_STATUS 0x13 +#define SX126X_CMD_GET_PACKET_STATUS 0x14 +#define SX126X_CMD_GET_DEVICE_ERRORS 0x17 +#define SX126X_CMD_CLEAR_DEVICE_ERRORS 0x07 +#define SX126X_CMD_GET_STATS 0x10 +#define SX126X_CMD_RESET_STATS 0x00 + + +// SX126X register map +#define SX126X_REG_HOPPING_ENABLE 0x0385 +#define SX126X_REG_PACKECT_LENGTH 0x0386 +#define SX126X_REG_NB_HOPPING_BLOCKS 0x0387 +#define SX126X_REG_NB_SYMBOLS0 0x0388 +#define SX126X_REG_FREQ0 0x038A +#define SX126X_REG_NB_SYMBOLS15 0x03E2 +#define SX126X_REG_FREQ15 0x03E4 +#define SX126X_REG_DIOX_OUTPUT_ENABLE 0x0580 +#define SX126X_REG_DIOX_INPUT_ENABLE 0x0583 +#define SX126X_REG_DIOX_PILL_UP_CONTROL 0x0584 +#define SX126X_REG_DIOX_PULL_DOWN_CONTROL 0x0585 +#define SX126X_REG_WHITENING_INITIAL_MSB 0x06B8 +#define SX126X_REG_WHITENING_INITIAL_LSB 0x06B9 +#define SX126X_REG_CRC_INITIAL_MSB 0x06BC +#define SX126X_REG_CRC_INITIAL_LSB 0x06BD +#define SX126X_REG_CRC_POLYNOMIAL_MSB 0x06BE +#define SX126X_REG_CRC_POLYNOMIAL_LSB 0x06BF +#define SX126X_REG_SYNC_WORD_0 0x06C0 +#define SX126X_REG_SYNC_WORD_1 0x06C1 +#define SX126X_REG_SYNC_WORD_2 0x06C2 +#define SX126X_REG_SYNC_WORD_3 0x06C3 +#define SX126X_REG_SYNC_WORD_4 0x06C4 +#define SX126X_REG_SYNC_WORD_5 0x06C5 +#define SX126X_REG_SYNC_WORD_6 0x06C6 +#define SX126X_REG_SYNC_WORD_7 0x06C7 +#define SX126X_REG_NODE_ADDRESS 0x06CD +#define SX126X_REG_BROADCAST_ADDRESS 0x06CE +#define SX126X_REG_IQ_POLARITY_SETUP 0x0736 +#define SX126X_REG_LORA_SYNC_WORD_MSB 0x0740 +#define SX126X_REG_LORA_SYNC_WORD_LSB 0x0741 +#define SX126X_REG_RANDOM_NUMBER_0 0x0819 +#define SX126X_REG_RANDOM_NUMBER_1 0x081A +#define SX126X_REG_RANDOM_NUMBER_2 0x081B +#define SX126X_REG_RANDOM_NUMBER_3 0x081C +#define SX126X_REG_TX_MODULETION 0x0889 +#define SX126X_REG_RX_GAIN 0x08AC +#define SX126X_REG_TX_CLAMP_CONFIG 0x08D8 +#define SX126X_REG_OCP_CONFIGURATION 0x08E7 +#define SX126X_REG_RTC_CONTROL 0x0902 +#define SX126X_REG_XTA_TRIM 0x0911 +#define SX126X_REG_XTB_TRIM 0x0912 +#define SX126X_REG_DIO3_OUTPUT_VOLTAGE_CONTROL 0x0920 +#define SX126X_REG_EVENT_MASK 0x0944 + + +// SX126X SPI command variables +// SX126X_CMD_SET_SLEEP +#define SX126X_SLEEP_START_COLD 0b00000000 // 2 2 sleep mode: cold start, configuration is lost (default) +#define SX126X_SLEEP_START_WARM 0b00000100 // 2 2 warm start, configuration is retained +#define SX126X_SLEEP_RTC_OFF 0b00000000 // 0 0 wake on RTC timeout: disabled +#define SX126X_SLEEP_RTC_ON 0b00000001 // 0 0 enabled + +// SX126X_CMD_SET_STANDBY +#define SX126X_STANDBY_RC 0x00 // 7 0 standby mode: 13 MHz RC oscillator +#define SX126X_STANDBY_XOSC 0x01 // 7 0 32 MHz crystal oscillator + +// SX126X_CMD_SET_RX +#define SX126X_RX_TIMEOUT_NONE 0x000000 // 23 0 Rx timeout duration: no timeout (Rx single mode) +#define SX126X_RX_TIMEOUT_INF 0xFFFFFF // 23 0 infinite (Rx continuous mode) + +// SX126X_CMD_STOP_TIMER_ON_PREAMBLE +#define SX126X_STOP_ON_PREAMBLE_OFF 0x00 // 7 0 stop timer on: sync word or header (default) +#define SX126X_STOP_ON_PREAMBLE_ON 0x01 // 7 0 preamble detection + +// SX126X_CMD_SET_REGULATOR_MODE +#define SX126X_REGULATOR_LDO 0x00 // 7 0 set regulator mode: LDO (default) +#define SX126X_REGULATOR_DC_DC 0x01 // 7 0 DC-DC + +// SX126X_CMD_CALIBRATE +#define SX126X_CALIBRATE_IMAGE_OFF 0b00000000 // 6 6 image calibration: disabled +#define SX126X_CALIBRATE_IMAGE_ON 0b01000000 // 6 6 enabled +#define SX126X_CALIBRATE_ADC_BULK_P_OFF 0b00000000 // 5 5 ADC bulk P calibration: disabled +#define SX126X_CALIBRATE_ADC_BULK_P_ON 0b00100000 // 5 5 enabled +#define SX126X_CALIBRATE_ADC_BULK_N_OFF 0b00000000 // 4 4 ADC bulk N calibration: disabled +#define SX126X_CALIBRATE_ADC_BULK_N_ON 0b00010000 // 4 4 enabled +#define SX126X_CALIBRATE_ADC_PULSE_OFF 0b00000000 // 3 3 ADC pulse calibration: disabled +#define SX126X_CALIBRATE_ADC_PULSE_ON 0b00001000 // 3 3 enabled +#define SX126X_CALIBRATE_PLL_OFF 0b00000000 // 2 2 PLL calibration: disabled +#define SX126X_CALIBRATE_PLL_ON 0b00000100 // 2 2 enabled +#define SX126X_CALIBRATE_RC13M_OFF 0b00000000 // 1 1 13 MHz RC osc. calibration: disabled +#define SX126X_CALIBRATE_RC13M_ON 0b00000010 // 1 1 enabled +#define SX126X_CALIBRATE_RC64K_OFF 0b00000000 // 0 0 64 kHz RC osc. calibration: disabled +#define SX126X_CALIBRATE_RC64K_ON 0b00000001 // 0 0 enabled + +// SX126X_CMD_CALIBRATE_IMAGE +#define SX126X_CAL_IMG_430_MHZ_1 0x6B +#define SX126X_CAL_IMG_430_MHZ_2 0x6F +#define SX126X_CAL_IMG_470_MHZ_1 0x75 +#define SX126X_CAL_IMG_470_MHZ_2 0x81 +#define SX126X_CAL_IMG_779_MHZ_1 0xC1 +#define SX126X_CAL_IMG_779_MHZ_2 0xC5 +#define SX126X_CAL_IMG_863_MHZ_1 0xD7 +#define SX126X_CAL_IMG_863_MHZ_2 0xDB +#define SX126X_CAL_IMG_902_MHZ_1 0xE1 +#define SX126X_CAL_IMG_902_MHZ_2 0xE9 + +// SX126X_CMD_SET_PA_CONFIG +#define SX126X_PA_CONFIG_HP_MAX 0x07 +#define SX126X_PA_CONFIG_SX1268 0x01 +#define SX126X_PA_CONFIG_PA_LUT 0x01 + +// SX126X_CMD_SET_RX_TX_FALLBACK_MODE +#define SX126X_RX_TX_FALLBACK_MODE_FS 0x40 // 7 0 after Rx/Tx go to: FS mode +#define SX126X_RX_TX_FALLBACK_MODE_STDBY_XOSC 0x30 // 7 0 standby with crystal oscillator +#define SX126X_RX_TX_FALLBACK_MODE_STDBY_RC 0x20 // 7 0 standby with RC oscillator (default) + +// SX126X_CMD_SET_DIO_IRQ_PARAMS +#define SX126X_IRQ_TIMEOUT 0b1000000000 // 9 9 Rx or Tx timeout +#define SX126X_IRQ_CAD_DETECTED 0b0100000000 // 8 8 channel activity detected +#define SX126X_IRQ_CAD_DONE 0b0010000000 // 7 7 channel activity detection finished +#define SX126X_IRQ_CRC_ERR 0b0001000000 // 6 6 wrong CRC received +#define SX126X_IRQ_HEADER_ERR 0b0000100000 // 5 5 LoRa header CRC error +#define SX126X_IRQ_HEADER_VALID 0b0000010000 // 4 4 valid LoRa header received +#define SX126X_IRQ_SYNC_WORD_VALID 0b0000001000 // 3 3 valid sync word detected +#define SX126X_IRQ_PREAMBLE_DETECTED 0b0000000100 // 2 2 preamble detected +#define SX126X_IRQ_RX_DONE 0b0000000010 // 1 1 packet received +#define SX126X_IRQ_TX_DONE 0b0000000001 // 0 0 packet transmission completed +#define SX126X_IRQ_ALL 0b1111111111 // 9 0 all interrupts +#define SX126X_IRQ_NONE 0b0000000000 // 9 0 no interrupts + +// SX126X_CMD_SET_DIO2_AS_RF_SWITCH_CTRL +#define SX126X_DIO2_AS_IRQ 0x00 // 7 0 DIO2 configuration: IRQ +#define SX126X_DIO2_AS_RF_SWITCH 0x01 // 7 0 RF switch control + +// SX126X_CMD_SET_DIO3_AS_TCXO_CTRL +#define SX126X_DIO3_OUTPUT_1_6 0x00 // 7 0 DIO3 voltage output for TCXO: 1.6 V +#define SX126X_DIO3_OUTPUT_1_7 0x01 // 7 0 1.7 V +#define SX126X_DIO3_OUTPUT_1_8 0x02 // 7 0 1.8 V +#define SX126X_DIO3_OUTPUT_2_2 0x03 // 7 0 2.2 V +#define SX126X_DIO3_OUTPUT_2_4 0x04 // 7 0 2.4 V +#define SX126X_DIO3_OUTPUT_2_7 0x05 // 7 0 2.7 V +#define SX126X_DIO3_OUTPUT_3_0 0x06 // 7 0 3.0 V +#define SX126X_DIO3_OUTPUT_3_3 0x07 // 7 0 3.3 V + +// Radio complete Wake-up Time with TCXO stabilisation time +#define RADIO_TCXO_SETUP_TIME 5000 // [us] + +// SX126X_CMD_SET_PACKET_TYPE +#define SX126X_PACKET_TYPE_GFSK 0x00 // 7 0 packet type: GFSK +#define SX126X_PACKET_TYPE_LORA 0x01 // 7 0 LoRa + +// SX126X_CMD_SET_TX_PARAMS +#define SX126X_PA_RAMP_10U 0x00 // 7 0 ramp time: 10 us +#define SX126X_PA_RAMP_20U 0x01 // 7 0 20 us +#define SX126X_PA_RAMP_40U 0x02 // 7 0 40 us +#define SX126X_PA_RAMP_80U 0x03 // 7 0 80 us +#define SX126X_PA_RAMP_200U 0x04 // 7 0 200 us +#define SX126X_PA_RAMP_800U 0x05 // 7 0 800 us +#define SX126X_PA_RAMP_1700U 0x06 // 7 0 1700 us +#define SX126X_PA_RAMP_3400U 0x07 // 7 0 3400 us + +// SX126X_CMD_SET_MODULATION_PARAMS +#define SX126X_GFSK_FILTER_NONE 0x00 // 7 0 GFSK filter: none +#define SX126X_GFSK_FILTER_GAUSS_0_3 0x08 // 7 0 Gaussian, BT = 0.3 +#define SX126X_GFSK_FILTER_GAUSS_0_5 0x09 // 7 0 Gaussian, BT = 0.5 +#define SX126X_GFSK_FILTER_GAUSS_0_7 0x0A // 7 0 Gaussian, BT = 0.7 +#define SX126X_GFSK_FILTER_GAUSS_1 0x0B // 7 0 Gaussian, BT = 1 +#define SX126X_GFSK_RX_BW_4_8 0x1F // 7 0 GFSK Rx bandwidth: 4.8 kHz +#define SX126X_GFSK_RX_BW_5_8 0x17 // 7 0 5.8 kHz +#define SX126X_GFSK_RX_BW_7_3 0x0F // 7 0 7.3 kHz +#define SX126X_GFSK_RX_BW_9_7 0x1E // 7 0 9.7 kHz +#define SX126X_GFSK_RX_BW_11_7 0x16 // 7 0 11.7 kHz +#define SX126X_GFSK_RX_BW_14_6 0x0E // 7 0 14.6 kHz +#define SX126X_GFSK_RX_BW_19_5 0x1D // 7 0 19.5 kHz +#define SX126X_GFSK_RX_BW_23_4 0x15 // 7 0 23.4 kHz +#define SX126X_GFSK_RX_BW_29_3 0x0D // 7 0 29.3 kHz +#define SX126X_GFSK_RX_BW_39_0 0x1C // 7 0 39.0 kHz +#define SX126X_GFSK_RX_BW_46_9 0x14 // 7 0 46.9 kHz +#define SX126X_GFSK_RX_BW_58_6 0x0C // 7 0 58.6 kHz +#define SX126X_GFSK_RX_BW_78_2 0x1B // 7 0 78.2 kHz +#define SX126X_GFSK_RX_BW_93_8 0x13 // 7 0 93.8 kHz +#define SX126X_GFSK_RX_BW_117_3 0x0B // 7 0 117.3 kHz +#define SX126X_GFSK_RX_BW_156_2 0x1A // 7 0 156.2 kHz +#define SX126X_GFSK_RX_BW_187_2 0x12 // 7 0 187.2 kHz +#define SX126X_GFSK_RX_BW_234_3 0x0A // 7 0 234.3 kHz +#define SX126X_GFSK_RX_BW_312_0 0x19 // 7 0 312.0 kHz +#define SX126X_GFSK_RX_BW_373_6 0x11 // 7 0 373.6 kHz +#define SX126X_GFSK_RX_BW_467_0 0x09 // 7 0 467.0 kHz +#define SX126X_LORA_BW_7_8 0x00 // 7 0 LoRa bandwidth: 7.8 kHz +#define SX126X_LORA_BW_10_4 0x08 // 7 0 10.4 kHz +#define SX126X_LORA_BW_15_6 0x01 // 7 0 15.6 kHz +#define SX126X_LORA_BW_20_8 0x09 // 7 0 20.8 kHz +#define SX126X_LORA_BW_31_25 0x02 // 7 0 31.25 kHz +#define SX126X_LORA_BW_41_7 0x0A // 7 0 41.7 kHz +#define SX126X_LORA_BW_62_5 0x03 // 7 0 62.5 kHz +#define SX126X_LORA_BW_125_0 0x04 // 7 0 125.0 kHz +#define SX126X_LORA_BW_250_0 0x05 // 7 0 250.0 kHz +#define SX126X_LORA_BW_500_0 0x06 // 7 0 500.0 kHz +#define SX126X_LORA_CR_4_5 0x01 // 7 0 LoRa coding rate: 4/5 +#define SX126X_LORA_CR_4_6 0x02 // 7 0 4/6 +#define SX126X_LORA_CR_4_7 0x03 // 7 0 4/7 +#define SX126X_LORA_CR_4_8 0x04 // 7 0 4/8 +#define SX126X_LORA_LOW_DATA_RATE_OPTIMIZE_OFF 0x00 // 7 0 LoRa low data rate optimization: disabled +#define SX126X_LORA_LOW_DATA_RATE_OPTIMIZE_ON 0x01 // 7 0 enabled + +// SX126X_CMD_SET_PACKET_PARAMS +#define SX126X_GFSK_PREAMBLE_DETECT_OFF 0x00 // 7 0 GFSK minimum preamble length before reception starts: detector disabled +#define SX126X_GFSK_PREAMBLE_DETECT_8 0x04 // 7 0 8 bits +#define SX126X_GFSK_PREAMBLE_DETECT_16 0x05 // 7 0 16 bits +#define SX126X_GFSK_PREAMBLE_DETECT_24 0x06 // 7 0 24 bits +#define SX126X_GFSK_PREAMBLE_DETECT_32 0x07 // 7 0 32 bits +#define SX126X_GFSK_ADDRESS_FILT_OFF 0x00 // 7 0 GFSK address filtering: disabled +#define SX126X_GFSK_ADDRESS_FILT_NODE 0x01 // 7 0 node only +#define SX126X_GFSK_ADDRESS_FILT_NODE_BROADCAST 0x02 // 7 0 node and broadcast +#define SX126X_GFSK_PACKET_FIXED 0x00 // 7 0 GFSK packet type: fixed (payload length known in advance to both sides) +#define SX126X_GFSK_PACKET_VARIABLE 0x01 // 7 0 variable (payload length added to packet) +#define SX126X_GFSK_CRC_OFF 0x01 // 7 0 GFSK packet CRC: disabled +#define SX126X_GFSK_CRC_1_BYTE 0x00 // 7 0 1 byte +#define SX126X_GFSK_CRC_2_BYTE 0x02 // 7 0 2 byte +#define SX126X_GFSK_CRC_1_BYTE_INV 0x04 // 7 0 1 byte, inverted +#define SX126X_GFSK_CRC_2_BYTE_INV 0x06 // 7 0 2 byte, inverted +#define SX126X_GFSK_WHITENING_OFF 0x00 // 7 0 GFSK data whitening: disabled +#define SX126X_GFSK_WHITENING_ON 0x01 // 7 0 enabled +#define SX126X_LORA_HEADER_EXPLICIT 0x00 // 7 0 LoRa header mode: explicit +#define SX126X_LORA_HEADER_IMPLICIT 0x01 // 7 0 implicit +#define SX126X_LORA_CRC_OFF 0x00 // 7 0 LoRa CRC mode: disabled +#define SX126X_LORA_CRC_ON 0x01 // 7 0 enabled +#define SX126X_LORA_IQ_STANDARD 0x00 // 7 0 LoRa IQ setup: standard +#define SX126X_LORA_IQ_INVERTED 0x01 // 7 0 inverted + +// SX126X_CMD_SET_CAD_PARAMS +#define SX126X_CAD_ON_1_SYMB 0x00 // 7 0 number of symbols used for CAD: 1 +#define SX126X_CAD_ON_2_SYMB 0x01 // 7 0 2 +#define SX126X_CAD_ON_4_SYMB 0x02 // 7 0 4 +#define SX126X_CAD_ON_8_SYMB 0x03 // 7 0 8 +#define SX126X_CAD_ON_16_SYMB 0x04 // 7 0 16 +#define SX126X_CAD_GOTO_STDBY 0x00 // 7 0 after CAD is done, always go to STDBY_RC mode +#define SX126X_CAD_GOTO_RX 0x01 // 7 0 after CAD is done, go to Rx mode if activity is detected + +// SX126X_CMD_GET_STATUS +#define SX126X_STATUS_MODE_STDBY_RC 0b00100000 // 6 4 current chip mode: STDBY_RC +#define SX126X_STATUS_MODE_STDBY_XOSC 0b00110000 // 6 4 STDBY_XOSC +#define SX126X_STATUS_MODE_FS 0b01000000 // 6 4 FS +#define SX126X_STATUS_MODE_RX 0b01010000 // 6 4 RX +#define SX126X_STATUS_MODE_TX 0b01100000 // 6 4 TX +#define SX126X_STATUS_DATA_AVAILABLE 0b00000100 // 3 1 command status: packet received and data can be retrieved +#define SX126X_STATUS_CMD_TIMEOUT 0b00000110 // 3 1 SPI command timed out +#define SX126X_STATUS_CMD_INVALID 0b00001000 // 3 1 invalid SPI command +#define SX126X_STATUS_CMD_FAILED 0b00001010 // 3 1 SPI command failed to execute +#define SX126X_STATUS_TX_DONE 0b00001100 // 3 1 packet transmission done +#define SX126X_STATUS_SPI_FAILED 0b11111111 // 7 0 SPI transaction failed + +// SX126X_CMD_GET_PACKET_STATUS +#define SX126X_GFSK_RX_STATUS_PREAMBLE_ERR 0b10000000 // 7 7 GFSK Rx status: preamble error +#define SX126X_GFSK_RX_STATUS_SYNC_ERR 0b01000000 // 6 6 sync word error +#define SX126X_GFSK_RX_STATUS_ADRS_ERR 0b00100000 // 5 5 address error +#define SX126X_GFSK_RX_STATUS_CRC_ERR 0b00010000 // 4 4 CRC error +#define SX126X_GFSK_RX_STATUS_LENGTH_ERR 0b00001000 // 3 3 length error +#define SX126X_GFSK_RX_STATUS_ABORT_ERR 0b00000100 // 2 2 abort error +#define SX126X_GFSK_RX_STATUS_PACKET_RECEIVED 0b00000010 // 2 2 packet received +#define SX126X_GFSK_RX_STATUS_PACKET_SENT 0b00000001 // 2 2 packet sent + +// SX126X_CMD_GET_DEVICE_ERRORS +#define SX126X_PA_RAMP_ERR 0b100000000 // 8 8 device errors: PA ramping failed +#define SX126X_PLL_LOCK_ERR 0b001000000 // 6 6 PLL failed to lock +#define SX126X_XOSC_START_ERR 0b000100000 // 5 5 crystal oscillator failed to start +#define SX126X_IMG_CALIB_ERR 0b000010000 // 4 4 image calibration failed +#define SX126X_ADC_CALIB_ERR 0b000001000 // 3 3 ADC calibration failed +#define SX126X_PLL_CALIB_ERR 0b000000100 // 2 2 PLL calibration failed +#define SX126X_RC13M_CALIB_ERR 0b000000010 // 1 1 RC13M calibration failed +#define SX126X_RC64K_CALIB_ERR 0b000000001 // 0 0 RC64K calibration failed + + +// SX126X SPI register variables +// SX126X_REG_LORA_SYNC_WORD_MSB + LSB +// #define SX126X_SYNC_WORD_PUBLIC 0x3444 +#define SX126X_SYNC_WORD_PUBLIC 0x24B4 // meshtastic +#define SX126X_SYNC_WORD_PRIVATE 0x1424 + +#define SX126x_TXMODE_ASYNC 0x01 +#define SX126x_TXMODE_SYNC 0x02 +#define SX126x_TXMODE_BACK2RX 0x04 + +// Convert bandwidth constant to float in kHz +//float loraBwToFloat(uint8_t bw); + +// Convert float bandwidth (kHz) to constant +//uint8_t floatToLoraBw(float bw); + +// Convert coding rate constant to float +//float loraCrToFloat(uint8_t cr); + +// Convert float coding rate to constant +//uint8_t floatToLoraCr(float cr); + +// Convert MHz to Hz with limit check +//uint32_t mhzToHzLimited(double freqMHz); + +// Public function +void LoRaInit (void); +int16_t LoRaBegin (uint32_t frequencyInHz, int8_t txPowerInDbm, uint16_t tcxoVoltage, char useRegulatorLDO); +void LoRaConfig (uint8_t spreadingFactor, uint8_t bandwidth, uint8_t codingRate, uint16_t preambleLength, uint8_t payloadLen, char crcOn, char invertIrq); +uint8_t LoRaReceive (uint8_t *pData, int16_t len); +char LoRaSend (uint8_t *pData, int16_t len, uint8_t mode); +void LoRaDebugPrint (char enable); + +// Private function +void spi_write_byte (uint8_t *Dataout, size_t DataLength); +void spi_read_byte (uint8_t *rx, const uint8_t *tx, size_t len); +void spi_read_byte_offs (uint8_t *rx, const uint8_t *tx, size_t len, uint8_t off); +uint8_t spi_transfer (uint8_t address); + +char ReceiveMode (void); +void GetPacketStatus (int8_t *rssiPacket, int8_t *snrPacket, int8_t *rawSnr); +void SetTxPower (int8_t txPowerInDbm); + +void FixInvertedIQ (uint8_t iqConfig); +void SetDio3AsTcxoCtrl (uint16_t voltage, uint32_t delay); +void SetDio2AsRfSwitchCtrl (uint8_t enable); +void ResetLora (void); +void SetStandby (uint8_t mode); +void SetRfFrequency (uint32_t frequency); +void Calibrate (uint8_t calibParam); +void CalibrateImage (uint32_t frequency); +void SetRegulatorMode (uint8_t mode); +void SetBufferBaseAddress (uint8_t txBaseAddress, uint8_t rxBaseAddress); +void SetPowerConfig (int8_t power, uint8_t rampTime); +void SetOvercurrentProtection (uint16_t currentLimit); +void SetSyncWord (int16_t sync); +void SetPaConfig (uint8_t paDutyCycle, uint8_t hpMax, uint8_t deviceSel, uint8_t paLut); +void SetDioIrqParams (uint16_t irqMask, uint16_t dio1Mask, uint16_t dio2Mask, uint16_t dio3Mask); +void SetStopRxTimerOnPreambleDetect (char enable); +void SetLoRaSymbNumTimeout (uint8_t SymbNum); +void SetPacketType (uint8_t packetType); +void SetModulationParams (uint8_t spreadingFactor, uint8_t bandwidth, uint8_t codingRate, uint8_t lowDataRateOptimize); +void SetCadParams (uint8_t cadSymbolNum, uint8_t cadDetPeak, uint8_t cadDetMin, uint8_t cadExitMode, uint32_t cadTimeout); +void SetCad(); +uint8_t GetStatus (void); +uint16_t GetIrqStatus (void); +void ClearIrqStatus (uint16_t irq); +void SetRx (uint32_t timeout); +void SetTx (uint32_t timeoutInMs); +int GetPacketLost(); +uint8_t GetRssiInst(); +void GetRxBufferStatus (uint8_t *payloadLength, uint8_t *rxStartBufferPointer); +void Wakeup (void); +void WaitForIdleBegin (unsigned long timeout, char *text); +char WaitForIdle (unsigned long timeout, char *text, char stop); +uint8_t ReadBuffer (uint8_t *rxData, int16_t rxDataLen); +void WriteBuffer (uint8_t *txData, int16_t txDataLen); +void WriteRegister (uint16_t reg, uint8_t *data, uint8_t numBytes); +void ReadRegister (uint16_t reg, uint8_t *data, uint8_t numBytes); +void WriteCommand (uint8_t cmd, uint8_t *data, uint8_t numBytes); +uint8_t WriteCommand2 (uint8_t cmd, uint8_t *data, uint8_t numBytes); +void ReadCommand (uint8_t cmd, uint8_t *data, uint8_t numBytes); +void SPItransfer (uint8_t cmd, char write, uint8_t *dataOut, uint8_t *dataIn, uint8_t numBytes, char waitForBusy); +void LoRaError (int error); + +extern uint8_t PacketParams[6]; +extern char txActive; +extern int txLost; +extern char debugPrint; + +#endif diff --git a/User/system_ch32v30x.c b/User/system_ch32v30x.c new file mode 100644 index 0000000..53fe111 --- /dev/null +++ b/User/system_ch32v30x.c @@ -0,0 +1,1036 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : system_ch32v30x.c +* Author : WCH +* Version : V1.0.0 +* Date : 2024/03/06 +* Description : CH32V30x Device Peripheral Access Layer System Source File. +* For HSE = 8Mhz +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v30x.h" + +/* +* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after +* reset the HSI is used as SYSCLK source). +* If none of the define below is enabled, the HSI is used as System clock source. +*/ +//#define SYSCLK_FREQ_HSE HSE_VALUE +//#define SYSCLK_FREQ_48MHz_HSE 48000000 +//#define SYSCLK_FREQ_56MHz_HSE 56000000 +//#define SYSCLK_FREQ_72MHz_HSE 72000000 +#define SYSCLK_FREQ_96MHz_HSE 96000000 +//#define SYSCLK_FREQ_120MHz_HSE 120000000 +//#define SYSCLK_FREQ_144MHz_HSE 144000000 +//#define SYSCLK_FREQ_HSI HSI_VALUE +//#define SYSCLK_FREQ_48MHz_HSI 48000000 +//#define SYSCLK_FREQ_56MHz_HSI 56000000 +//#define SYSCLK_FREQ_72MHz_HSI 72000000 +//#define SYSCLK_FREQ_96MHz_HSI 96000000 +//#define SYSCLK_FREQ_120MHz_HSI 120000000 +//#define SYSCLK_FREQ_144MHz_HSI 144000000 + +/* Clock Definitions */ +#ifdef SYSCLK_FREQ_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_96MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_120MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_144MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_96MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_120MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_144MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSI; /* System Clock Frequency (Core Clock) */ +#else +uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */ + +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + + +/* system_private_function_proto_types */ +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE +static void SetSysClockToHSE( void ); +#elif defined SYSCLK_FREQ_48MHz_HSE +static void SetSysClockTo48_HSE( void ); +#elif defined SYSCLK_FREQ_56MHz_HSE +static void SetSysClockTo56_HSE( void ); +#elif defined SYSCLK_FREQ_72MHz_HSE +static void SetSysClockTo72_HSE( void ); +#elif defined SYSCLK_FREQ_96MHz_HSE +static void SetSysClockTo96_HSE( void ); +#elif defined SYSCLK_FREQ_120MHz_HSE +static void SetSysClockTo120_HSE( void ); +#elif defined SYSCLK_FREQ_144MHz_HSE +static void SetSysClockTo144_HSE( void ); +#elif defined SYSCLK_FREQ_48MHz_HSI +static void SetSysClockTo48_HSI( void ); +#elif defined SYSCLK_FREQ_56MHz_HSI +static void SetSysClockTo56_HSI( void ); +#elif defined SYSCLK_FREQ_72MHz_HSI +static void SetSysClockTo72_HSI( void ); +#elif defined SYSCLK_FREQ_96MHz_HSI +static void SetSysClockTo96_HSI( void ); +#elif defined SYSCLK_FREQ_120MHz_HSI +static void SetSysClockTo120_HSI( void ); +#elif defined SYSCLK_FREQ_144MHz_HSI +static void SetSysClockTo144_HSI( void ); + +#endif + + +/********************************************************************* + * @fn SystemInit + * + * @brief Setup the microcontroller system Initialize the Embedded Flash Interface, + * the PLL and update the SystemCoreClock variable. + * + * @return none + */ +void SystemInit (void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + + RCC->CFGR0 &= (uint32_t)0xF0FF0000; + + RCC->CTLR &= (uint32_t)0xFEF6FFFF; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFF00FFFF; + +#ifdef CH32V30x_D8C + RCC->CTLR &= (uint32_t)0xEBFFFFFF; + RCC->INTR = 0x00FF0000; + RCC->CFGR2 = 0x00000000; +#else + RCC->INTR = 0x009F0000; +#endif + SetSysClock(); +} + +/********************************************************************* + * @fn SystemCoreClockUpdate + * + * @brief Update SystemCoreClock variable according to Clock Register Values. + * + * @return none + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + uint8_t Pll_6_5 = 0; + +#ifdef CH32V30x_D8C + uint8_t Pll2mull = 0; + +#endif + + tmp = RCC->CFGR0 & RCC_SWS; + + switch (tmp) + { + case 0x00: + SystemCoreClock = HSI_VALUE; + break; + case 0x04: + SystemCoreClock = HSE_VALUE; + break; + case 0x08: + pllmull = RCC->CFGR0 & RCC_PLLMULL; + pllsource = RCC->CFGR0 & RCC_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + +#ifdef CH32V30x_D8 + if(pllmull == 17) pllmull = 18; +#else + if(pllmull == 2) pllmull = 18; + if(pllmull == 15){ + pllmull = 13; /* *6.5 */ + Pll_6_5 = 1; + } + if(pllmull == 16) pllmull = 15; + if(pllmull == 17) pllmull = 16; +#endif + + if (pllsource == 0x00) + { + if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE) SystemCoreClock = HSI_VALUE * pllmull; + else SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + +#ifdef CH32V30x_D8 + if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET) + { + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + +#else + if(RCC->CFGR2 & (1<<16)){ /* PLL2 */ + SystemCoreClock = HSE_VALUE/(((RCC->CFGR2 & 0xF0)>>4) + 1); /* PREDIV2 */ + + Pll2mull = (uint8_t)((RCC->CFGR2 & 0xF00)>>8); + + if(Pll2mull == 0) SystemCoreClock = (SystemCoreClock * 5)>>1; + else if(Pll2mull == 1) SystemCoreClock = (SystemCoreClock * 25)>>1; + else if(Pll2mull == 15) SystemCoreClock = SystemCoreClock * 20; + else SystemCoreClock = SystemCoreClock * (Pll2mull + 2); + + SystemCoreClock = SystemCoreClock/((RCC->CFGR2 & 0xF) + 1); /* PREDIV1 */ + } + else{/* HSE */ + SystemCoreClock = HSE_VALUE/((RCC->CFGR2 & 0xF) + 1); /* PREDIV1 */ + } + + SystemCoreClock = SystemCoreClock * pllmull; +#endif + } + + + if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2); + + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + + tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; + SystemCoreClock >>= tmp; +} + +/********************************************************************* + * @fn SetSysClock + * + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClock(void) +{ + //GPIO_IPD_Unused(); +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_48MHz_HSE + SetSysClockTo48_HSE(); +#elif defined SYSCLK_FREQ_56MHz_HSE + SetSysClockTo56_HSE(); +#elif defined SYSCLK_FREQ_72MHz_HSE + SetSysClockTo72_HSE(); +#elif defined SYSCLK_FREQ_96MHz_HSE + SetSysClockTo96_HSE(); +#elif defined SYSCLK_FREQ_120MHz_HSE + SetSysClockTo120_HSE(); +#elif defined SYSCLK_FREQ_144MHz_HSE + SetSysClockTo144_HSE(); +#elif defined SYSCLK_FREQ_48MHz_HSI + SetSysClockTo48_HSI(); +#elif defined SYSCLK_FREQ_56MHz_HSI + SetSysClockTo56_HSI(); +#elif defined SYSCLK_FREQ_72MHz_HSI + SetSysClockTo72_HSI(); +#elif defined SYSCLK_FREQ_96MHz_HSI + SetSysClockTo96_HSI(); +#elif defined SYSCLK_FREQ_120MHz_HSI + SetSysClockTo120_HSI(); +#elif defined SYSCLK_FREQ_144MHz_HSI + SetSysClockTo144_HSI(); + +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + * source (default after reset) + */ +} + + +#ifdef SYSCLK_FREQ_HSE + +/********************************************************************* + * @fn SetSysClockToHSE + * + * @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo48_HSE + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_56MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo56_HSE + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_72MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo72_HSE + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_96MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo96_HSE + * + * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo96_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 12 = 96 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_120MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo120_HSE + * + * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo120_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 15 = 120 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_144MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo144_HSE + * + * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo144_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 18 = 144 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo48_HSI + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_56MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo56_HSI + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 7 = 56 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_72MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo72_HSI + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + + +#elif defined SYSCLK_FREQ_96MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo96_HSI + * + * @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo96_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 12 = 96 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + + +#elif defined SYSCLK_FREQ_120MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo120_HSI + * + * @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo120_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 15 = 120 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + + +#elif defined SYSCLK_FREQ_144MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo144_HSI + * + * @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo144_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 18 = 144 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + +#ifdef CH32V30x_D8 + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18); +#else + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18_EXTEN); +#endif + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#endif diff --git a/User/system_ch32v30x.h b/User/system_ch32v30x.h new file mode 100644 index 0000000..056839b --- /dev/null +++ b/User/system_ch32v30x.h @@ -0,0 +1,32 @@ +/********************************** (C) COPYRIGHT ******************************* +* File Name : system_ch32v30x.h +* Author : WCH +* Version : V1.0.0 +* Date : 2021/06/06 +* Description : CH32V30x Device Peripheral Access Layer System Header File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __SYSTEM_CH32V30x_H +#define __SYSTEM_CH32V30x_H + +#ifdef __cplusplus + extern "C" { +#endif + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/* System_Exported_Functions */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V30x_SYSTEM_H */ + + + diff --git a/User/util/hexdump.c b/User/util/hexdump.c new file mode 100644 index 0000000..8082f4e --- /dev/null +++ b/User/util/hexdump.c @@ -0,0 +1,39 @@ +#include "stdio.h" +#include +#include "hexdump.h" + +void hexdump (const char *label, const uint8_t *data, size_t len) { + if (label) + iprintf ("%s (len=%u):\n", label, len); + + for (size_t i = 0; i < len; i += 16) { + iprintf ("%04u ", i); // offset + for (size_t j = 0; j < 16; j++) { + if (i + j < len) + iprintf ("%02X ", data[i + j]); + else + iprintf (" "); // pad spacing + } + iprintf (" "); + for (size_t j = 0; j < 16 && i + j < len; j++) { + uint8_t c = data[i + j]; + iprintf ("%c", isprint (c) ? c : '.'); + } + iprintf ("\n"); + } +} + +void hexdump_compact(const uint8_t* data, size_t len, char* out, size_t out_size) { + size_t pos = 0; + + for (size_t i = 0; i < len; i++) { + if (pos + 2 >= out_size) break; // make sure we don¡¯t overflow + snprintf(out + pos, 3, "%02x", data[i]); // 2 chars + null terminator + pos += 2; + } + + if (pos < out_size) + out[pos] = '\0'; + else + out[out_size - 1] = '\0'; // ensure null termination +} \ No newline at end of file diff --git a/User/util/hexdump.h b/User/util/hexdump.h new file mode 100644 index 0000000..85fa06b --- /dev/null +++ b/User/util/hexdump.h @@ -0,0 +1,11 @@ +#ifndef HEXDUMP_HEADER +#define HEXDUMP_HEADER + + +#include "stddef.h" +#include "stdint.h" +void hexdump (const char *label, const uint8_t *data, size_t len); + +void hexdump_compact(const uint8_t* data, size_t len, char* out, size_t out_size); + +#endif \ No newline at end of file diff --git a/User/util/log.h b/User/util/log.h new file mode 100644 index 0000000..db555b9 --- /dev/null +++ b/User/util/log.h @@ -0,0 +1,33 @@ +#ifndef LOGGER_HEADER +#define LOGGER_HEADER + +#include + +// Log levels as integers for easy comparison +#define LOG_LEVEL_ERROR 0 +#define LOG_LEVEL_WARN 1 +#define LOG_LEVEL_INFO 2 +#define LOG_LEVEL_DEBUG 3 +#define LOG_LEVEL_VERBOSE 4 + +// Current log level (change at runtime or compile-time) +#ifndef CURRENT_LOG_LEVEL +#define CURRENT_LOG_LEVEL LOG_LEVEL_DEBUG +#endif + +// Internal macro to check log level +#define LOG_PRINT_IF(level, levelStr, tag, fmt, ...) \ + do { \ + if ((level) <= CURRENT_LOG_LEVEL) { \ + printf("[%s] %s: " fmt "\r\n", levelStr, tag, ##__VA_ARGS__); \ + } \ + } while(0) + +// ESP-like shortcuts +#define MESH_LOGE(tag, fmt, ...) LOG_PRINT_IF(LOG_LEVEL_ERROR, "E", tag, fmt, ##__VA_ARGS__) +#define MESH_LOGW(tag, fmt, ...) LOG_PRINT_IF(LOG_LEVEL_WARN, "W", tag, fmt, ##__VA_ARGS__) +#define MESH_LOGI(tag, fmt, ...) LOG_PRINT_IF(LOG_LEVEL_INFO, "I", tag, fmt, ##__VA_ARGS__) +#define MESH_LOGD(tag, fmt, ...) LOG_PRINT_IF(LOG_LEVEL_DEBUG, "D", tag, fmt, ##__VA_ARGS__) +#define MESH_LOGV(tag, fmt, ...) LOG_PRINT_IF(LOG_LEVEL_VERBOSE, "V", tag, fmt, ##__VA_ARGS__) + +#endif diff --git a/meshcorenortos.launch b/meshcorenortos.launch new file mode 100644 index 0000000..6ab44c3 --- /dev/null +++ b/meshcorenortos.launch @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/meshcorenortos.wvproj b/meshcorenortos.wvproj new file mode 100644 index 0000000..27819d4 --- /dev/null +++ b/meshcorenortos.wvproj @@ -0,0 +1,421 @@ +{ + "version": "1.0", + "hasAllParsed": true, + "isNormalMRSProject": true, + "basic": { + "chipInfo": { + "vendor": "WCH", + "toolchain": "RISC-V", + "series": "CH32V307", + "rtos": "NoneOS", + "mcu": "CH32V307VCT6", + "description": "Website: http://www.wch.cn/products/CH32V307.html?\\nROM(byte): 256K, SRAM(byte): 64K, CHIP PINS: 100, GPIO PORTS: 80.\\nWCH CH32V3 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.", + "tempratureScope": "CH32V307VCT6{-40℃~85℃}", + "link": "WCH-Link", + "peripheral_version": "2.9", + "calibrateSupport": false + }, + "linkedFolders": [], + "removedResources": [ + { + "parentLogicPath": "", + "type": "file", + "name": "*.wvproj" + }, + { + "name": "FreeRTOSConfig.h", + "parentLogicPath": "User", + "type": "file" + } + ], + "projectName": "meshcorenortos", + "architecture": "RISC-V", + "projectType": "c" + }, + "buildConfig": { + "configurations": [ + { + "buildArtifact": { + "artifact_name": "${ProjName}", + "artifact_extension": "elf", + "output_prefix": "", + "artifact_type": "Executable" + }, + "parallelizationNumber": "optimal", + "stop_on_first_build_error": true, + "pre_script": "", + "pre_script_description": "", + "post_script": "", + "post_script_description": "", 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Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Core/core_riscv.c + +C_DEPS += \ +./Core/core_riscv.d + +OBJS += \ +./Core/core_riscv.o + +DIR_OBJS += \ +./Core/*.o \ + +DIR_DEPS += \ +./Core/*.d \ + +DIR_EXPANDS += \ +./Core/*.234r.expand \ + + +# Each subdirectory must supply rules for building sources it contributes +Core/%.o: ../Core/%.c + @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -fmax-errors=20 -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"/home/bruno/mounriver-studio-projects/meshcorenortos/Debug" -I"/home/bruno/mounriver-studio-projects/meshcorenortos/Core" -I"/home/bruno/mounriver-studio-projects/meshcorenortos/User" -I"/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + diff --git a/obj/Debug/debug.d b/obj/Debug/debug.d new file mode 100644 index 0000000..576c817 --- /dev/null +++ b/obj/Debug/debug.d @@ -0,0 +1,90 @@ +Debug/debug.o: ../Debug/debug.c ../Debug/debug.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Core/core_riscv.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/system_ch32v30x.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_conf.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_adc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_bkp.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_can.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_crc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dac.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dbgmcu.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dma.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_exti.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_flash.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_fsmc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_gpio.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_i2c.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_iwdg.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_pwr.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rcc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rtc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_sdio.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_spi.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_tim.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_usart.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_wwdg.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_it.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Debug/debug.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_misc.h + +../Debug/debug.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Core/core_riscv.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/system_ch32v30x.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_conf.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_adc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_bkp.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_can.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_crc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dac.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dbgmcu.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dma.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_exti.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_flash.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_fsmc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_gpio.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_i2c.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_iwdg.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_pwr.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rcc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rtc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_sdio.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_spi.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_tim.h: + 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/home/bruno/mounriver-studio-projects/meshcorenortos/User/system_ch32v30x.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_conf.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_adc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_bkp.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_can.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_crc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dbgmcu.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dma.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_exti.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_flash.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_fsmc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_gpio.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_i2c.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_iwdg.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_pwr.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rcc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rtc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_sdio.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_spi.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_tim.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_usart.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_wwdg.h \ + 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/home/bruno/mounriver-studio-projects/meshcorenortos/User/system_ch32v30x.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_conf.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_adc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_bkp.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_can.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_crc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dac.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dma.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_exti.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_flash.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_fsmc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_gpio.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_i2c.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_iwdg.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_pwr.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rcc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rtc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_sdio.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_spi.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_tim.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_usart.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_wwdg.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_it.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Debug/debug.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_misc.h + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dbgmcu.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Core/core_riscv.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/system_ch32v30x.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_conf.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_adc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_bkp.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_can.h: + 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/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_bkp.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_can.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_crc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dac.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dbgmcu.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dma.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_exti.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_flash.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_fsmc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_gpio.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_i2c.h \ + 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+ /home/bruno/mounriver-studio-projects/meshcorenortos/User/system_ch32v30x.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_conf.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_adc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_bkp.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_can.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_crc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dac.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dbgmcu.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dma.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_flash.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_fsmc.h \ + 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/home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_conf.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_adc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_bkp.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_can.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_crc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dac.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dbgmcu.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dma.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_exti.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_flash.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_gpio.h \ + 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+Peripheral/src/ch32v30x_misc.o: ../Peripheral/src/ch32v30x_misc.c \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_misc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Core/core_riscv.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/system_ch32v30x.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_conf.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_adc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_bkp.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_can.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_crc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dac.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dbgmcu.h \ + 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index 0000000..239334a --- /dev/null +++ b/obj/Peripheral/src/ch32v30x_rng.d @@ -0,0 +1,91 @@ +Peripheral/src/ch32v30x_rng.o: ../Peripheral/src/ch32v30x_rng.c \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rng.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Core/core_riscv.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/system_ch32v30x.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_conf.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_adc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_bkp.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_can.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_crc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dac.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dbgmcu.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dma.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_exti.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_flash.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_fsmc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_gpio.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_i2c.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_iwdg.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_pwr.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rcc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rtc.h \ + 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Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Peripheral/src/ch32v30x_adc.c \ +../Peripheral/src/ch32v30x_bkp.c \ +../Peripheral/src/ch32v30x_can.c \ +../Peripheral/src/ch32v30x_crc.c \ +../Peripheral/src/ch32v30x_dac.c \ +../Peripheral/src/ch32v30x_dbgmcu.c \ +../Peripheral/src/ch32v30x_dma.c \ +../Peripheral/src/ch32v30x_dvp.c \ +../Peripheral/src/ch32v30x_eth.c \ +../Peripheral/src/ch32v30x_exti.c \ +../Peripheral/src/ch32v30x_flash.c \ +../Peripheral/src/ch32v30x_fsmc.c \ +../Peripheral/src/ch32v30x_gpio.c \ +../Peripheral/src/ch32v30x_i2c.c \ +../Peripheral/src/ch32v30x_iwdg.c \ +../Peripheral/src/ch32v30x_misc.c \ +../Peripheral/src/ch32v30x_opa.c \ +../Peripheral/src/ch32v30x_pwr.c \ +../Peripheral/src/ch32v30x_rcc.c \ +../Peripheral/src/ch32v30x_rng.c \ +../Peripheral/src/ch32v30x_rtc.c \ +../Peripheral/src/ch32v30x_sdio.c \ +../Peripheral/src/ch32v30x_spi.c \ +../Peripheral/src/ch32v30x_tim.c \ +../Peripheral/src/ch32v30x_usart.c \ +../Peripheral/src/ch32v30x_wwdg.c + +C_DEPS += \ +./Peripheral/src/ch32v30x_adc.d \ +./Peripheral/src/ch32v30x_bkp.d \ +./Peripheral/src/ch32v30x_can.d \ +./Peripheral/src/ch32v30x_crc.d \ +./Peripheral/src/ch32v30x_dac.d \ +./Peripheral/src/ch32v30x_dbgmcu.d \ +./Peripheral/src/ch32v30x_dma.d \ +./Peripheral/src/ch32v30x_dvp.d \ +./Peripheral/src/ch32v30x_eth.d \ +./Peripheral/src/ch32v30x_exti.d \ +./Peripheral/src/ch32v30x_flash.d \ +./Peripheral/src/ch32v30x_fsmc.d \ +./Peripheral/src/ch32v30x_gpio.d \ +./Peripheral/src/ch32v30x_i2c.d \ +./Peripheral/src/ch32v30x_iwdg.d \ +./Peripheral/src/ch32v30x_misc.d \ +./Peripheral/src/ch32v30x_opa.d \ +./Peripheral/src/ch32v30x_pwr.d \ +./Peripheral/src/ch32v30x_rcc.d \ +./Peripheral/src/ch32v30x_rng.d \ +./Peripheral/src/ch32v30x_rtc.d \ +./Peripheral/src/ch32v30x_sdio.d \ +./Peripheral/src/ch32v30x_spi.d \ +./Peripheral/src/ch32v30x_tim.d \ +./Peripheral/src/ch32v30x_usart.d \ +./Peripheral/src/ch32v30x_wwdg.d + +OBJS += \ +./Peripheral/src/ch32v30x_adc.o \ +./Peripheral/src/ch32v30x_bkp.o \ +./Peripheral/src/ch32v30x_can.o \ +./Peripheral/src/ch32v30x_crc.o \ +./Peripheral/src/ch32v30x_dac.o \ +./Peripheral/src/ch32v30x_dbgmcu.o \ +./Peripheral/src/ch32v30x_dma.o \ +./Peripheral/src/ch32v30x_dvp.o \ +./Peripheral/src/ch32v30x_eth.o \ +./Peripheral/src/ch32v30x_exti.o \ +./Peripheral/src/ch32v30x_flash.o \ +./Peripheral/src/ch32v30x_fsmc.o \ +./Peripheral/src/ch32v30x_gpio.o \ +./Peripheral/src/ch32v30x_i2c.o \ +./Peripheral/src/ch32v30x_iwdg.o \ +./Peripheral/src/ch32v30x_misc.o \ +./Peripheral/src/ch32v30x_opa.o \ +./Peripheral/src/ch32v30x_pwr.o \ +./Peripheral/src/ch32v30x_rcc.o \ +./Peripheral/src/ch32v30x_rng.o \ +./Peripheral/src/ch32v30x_rtc.o \ +./Peripheral/src/ch32v30x_sdio.o \ +./Peripheral/src/ch32v30x_spi.o \ +./Peripheral/src/ch32v30x_tim.o \ +./Peripheral/src/ch32v30x_usart.o \ +./Peripheral/src/ch32v30x_wwdg.o + +DIR_OBJS += \ +./Peripheral/src/*.o \ + +DIR_DEPS += \ +./Peripheral/src/*.d \ + +DIR_EXPANDS += \ +./Peripheral/src/*.234r.expand \ + + +# Each subdirectory must supply rules for building sources it contributes +Peripheral/src/%.o: ../Peripheral/src/%.c + @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -fmax-errors=20 -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"/home/bruno/mounriver-studio-projects/meshcorenortos/Debug" -I"/home/bruno/mounriver-studio-projects/meshcorenortos/Core" -I"/home/bruno/mounriver-studio-projects/meshcorenortos/User" -I"/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + diff --git a/obj/Startup/startup_ch32v30x_D8C.d b/obj/Startup/startup_ch32v30x_D8C.d new file mode 100644 index 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b/obj/User/lib/monocypher/subdir.mk new file mode 100644 index 0000000..c4f60cb --- /dev/null +++ b/obj/User/lib/monocypher/subdir.mk @@ -0,0 +1,32 @@ +################################################################################ +# MRS Version: 2.4.0 +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../User/lib/monocypher/monocypher-ed25519.c \ +../User/lib/monocypher/monocypher.c + +C_DEPS += \ +./User/lib/monocypher/monocypher-ed25519.d \ +./User/lib/monocypher/monocypher.d + +OBJS += \ +./User/lib/monocypher/monocypher-ed25519.o \ +./User/lib/monocypher/monocypher.o + +DIR_OBJS += \ +./User/lib/monocypher/*.o \ + +DIR_DEPS += \ +./User/lib/monocypher/*.d \ + +DIR_EXPANDS += \ +./User/lib/monocypher/*.234r.expand \ + + +# Each subdirectory must supply rules for building sources it contributes +User/lib/monocypher/%.o: ../User/lib/monocypher/%.c + @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -fmax-errors=20 -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"/home/bruno/mounriver-studio-projects/meshcorenortos/Debug" -I"/home/bruno/mounriver-studio-projects/meshcorenortos/Core" -I"/home/bruno/mounriver-studio-projects/meshcorenortos/User" -I"/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + diff --git a/obj/User/lib/rtc/rtc.d b/obj/User/lib/rtc/rtc.d new file mode 100644 index 0000000..9be4b49 --- /dev/null +++ b/obj/User/lib/rtc/rtc.d @@ -0,0 +1,91 @@ +User/lib/rtc/rtc.o: ../User/lib/rtc/rtc.c \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_misc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Core/core_riscv.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/system_ch32v30x.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_conf.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_adc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_bkp.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_can.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_crc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dac.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dbgmcu.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dma.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_exti.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_flash.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_fsmc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_gpio.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_i2c.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_iwdg.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_pwr.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rcc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rtc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_sdio.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_spi.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_tim.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_usart.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_wwdg.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_it.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Debug/debug.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h \ + ../User/lib/rtc/rtc.h + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_misc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Core/core_riscv.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/system_ch32v30x.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_conf.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_adc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_bkp.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_can.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_crc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dac.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dbgmcu.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dma.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_exti.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_flash.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_fsmc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_gpio.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_i2c.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_iwdg.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_pwr.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rcc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rtc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_sdio.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_spi.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_tim.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_usart.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_wwdg.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_it.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Debug/debug.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h: + +../User/lib/rtc/rtc.h: diff --git a/obj/User/lib/rtc/rtc.o b/obj/User/lib/rtc/rtc.o new file mode 100644 index 0000000000000000000000000000000000000000..5ecadf00a4c3132cb73d8ab7c9a4ecf9717cafc2 GIT binary patch literal 60172 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/home/bruno/mounriver-studio-projects/meshcorenortos/User/system_ch32v30x.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_conf.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_adc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_bkp.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_can.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_crc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dac.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dbgmcu.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dma.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_exti.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_flash.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_fsmc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_gpio.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_i2c.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_iwdg.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_pwr.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rcc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rtc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_sdio.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_spi.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_tim.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_usart.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_wwdg.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_it.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Debug/debug.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_misc.h \ + ../User/meshcore/meshframing.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/aes.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/prp.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/hmac.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/chash.h \ + ../User/meshcore/packetstructs.h ../User/meshcore/packets/advert.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/packetstructs.h \ + ../User/meshcore/packets/control.h ../User/meshcore/packets/encrypted.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/config.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/meshframing.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/util/log.h \ + ../User/meshcore/packets/group.h ../User/meshcore/packetstructs.h \ + ../User/sx1262.h ../User/util/hexdump.h ../User/util/log.h \ + ../User/meshcore/meshcore.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/sx1262.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/sha2.h \ + ../User/lib/config.h ../User/lib/rtc/rtc.h \ + ../User/lib/monocypher/monocypher-ed25519.h \ + ../User/lib/monocypher/monocypher.h ../User/meshcore/stats.h \ + ../User/lib/adc/temperature.h + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rng.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Core/core_riscv.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/system_ch32v30x.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_conf.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_adc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_bkp.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_can.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_crc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dac.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dbgmcu.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dma.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_exti.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_flash.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_fsmc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_gpio.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_i2c.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_iwdg.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_pwr.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rcc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rtc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_sdio.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_spi.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_tim.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_usart.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_wwdg.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_it.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Debug/debug.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_misc.h: + +../User/meshcore/meshframing.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/aes.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/prp.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/hmac.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/chash.h: + +../User/meshcore/packetstructs.h: + +../User/meshcore/packets/advert.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/packetstructs.h: + +../User/meshcore/packets/control.h: + +../User/meshcore/packets/encrypted.h: + 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/home/bruno/mounriver-studio-projects/meshcorenortos/User/system_ch32v30x.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_conf.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_adc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_bkp.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_can.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_crc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dac.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dbgmcu.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dma.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_exti.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_flash.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_fsmc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_i2c.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_iwdg.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_pwr.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rcc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rtc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_sdio.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_spi.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_tim.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_usart.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_wwdg.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_it.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Debug/debug.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_misc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/config.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/packetstructs.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/stats.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/sx1262.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/util/hexdump.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/util/log.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/sha2.h + +../User/meshcore/meshframing.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/aes.h: + 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/home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_conf.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_adc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_bkp.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_can.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_crc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dac.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dbgmcu.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dma.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_exti.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_flash.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_fsmc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_gpio.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_i2c.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_iwdg.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_pwr.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rcc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_sdio.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_spi.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_tim.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_usart.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_wwdg.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_it.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Debug/debug.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_misc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/config.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/packetstructs.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/monocypher/monocypher-ed25519.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/monocypher/monocypher.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/meshframing.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/aes.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/prp.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/hmac.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/chash.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/packetstructs.h \ + ../User/meshcore/packets/advert.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/util/hexdump.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/base64.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/util/log.h + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rtc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Core/core_riscv.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/system_ch32v30x.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_conf.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_adc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_bkp.h: + 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b/obj/User/meshcore/packets/anonymous.d @@ -0,0 +1,130 @@ +User/meshcore/packets/anonymous.o: ../User/meshcore/packets/anonymous.c \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rtc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Core/core_riscv.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/system_ch32v30x.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_conf.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_adc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_bkp.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_can.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_crc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dac.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dbgmcu.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dma.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_exti.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_flash.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_fsmc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_gpio.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_i2c.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_iwdg.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_pwr.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rcc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_sdio.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_spi.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_tim.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_usart.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_wwdg.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_it.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Debug/debug.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_misc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/config.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/packetstructs.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/monocypher/monocypher-ed25519.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/monocypher/monocypher.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/meshframing.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/aes.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/prp.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/hmac.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/chash.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/packetstructs.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/packets/encrypted.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/util/log.h \ + ../User/meshcore/packets/anonymous.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/util/hexdump.h + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rtc.h: + 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b/obj/User/meshcore/packets/control.d @@ -0,0 +1,37 @@ +User/meshcore/packets/control.o: ../User/meshcore/packets/control.c \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/config.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/packetstructs.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/meshframing.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/aes.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/prp.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/hmac.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/chash.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/packetstructs.h \ + ../User/meshcore/packets/control.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/stats.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/util/hexdump.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/util/log.h + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/config.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/packetstructs.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/meshframing.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/aes.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/prp.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/hmac.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/chash.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/packetstructs.h: + +../User/meshcore/packets/control.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/stats.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/util/hexdump.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/util/log.h: diff --git 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/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_bkp.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_can.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_crc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dac.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dbgmcu.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dma.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_exti.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_flash.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_fsmc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_gpio.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_i2c.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_iwdg.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_pwr.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rcc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rtc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_sdio.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_spi.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_tim.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_usart.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_wwdg.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_it.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Debug/debug.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_misc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/telemetry/telemetry.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/meshframing.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/aes.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/prp.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/hmac.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/chash.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/packetstructs.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/packets/ack.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/packets/advert.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/stats.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/util/hexdump.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/util/log.h \ + ../User/meshcore/packets/encrypted.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/adc/temperature.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/rtc/rtc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/sx1262.h + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/config.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/packetstructs.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Core/core_riscv.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/system_ch32v30x.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_conf.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_adc.h: + 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/home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_conf.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_adc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_bkp.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_can.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_crc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dac.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dbgmcu.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dma.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_exti.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_flash.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_fsmc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_gpio.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_i2c.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_iwdg.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_pwr.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rcc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_sdio.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_spi.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_tim.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_usart.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_wwdg.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_it.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Debug/debug.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_misc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/meshframing.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/aes.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/prp.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/hmac.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/chash.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/packetstructs.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/packetstructs.h \ + ../User/meshcore/packets/group.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/config.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/util/hexdump.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/util/log.h + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rtc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Core/core_riscv.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/system_ch32v30x.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_conf.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_adc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_bkp.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_can.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_crc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dac.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dbgmcu.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dma.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_exti.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_flash.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_fsmc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_gpio.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_i2c.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_iwdg.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_pwr.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rcc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_sdio.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_spi.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_tim.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_usart.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_wwdg.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_it.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Debug/debug.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_misc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/meshframing.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/aes.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/prp.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/hmac.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/lib/cifra/chash.h: + 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+################################################################################ +# MRS Version: 2.4.0 +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../User/meshcore/packets/ack.c \ +../User/meshcore/packets/advert.c \ +../User/meshcore/packets/anonymous.c \ +../User/meshcore/packets/control.c \ +../User/meshcore/packets/custom.c \ +../User/meshcore/packets/encrypted.c \ +../User/meshcore/packets/group.c \ +../User/meshcore/packets/multipart.c \ +../User/meshcore/packets/trace.c + +C_DEPS += \ +./User/meshcore/packets/ack.d \ +./User/meshcore/packets/advert.d \ +./User/meshcore/packets/anonymous.d \ +./User/meshcore/packets/control.d \ +./User/meshcore/packets/custom.d \ +./User/meshcore/packets/encrypted.d \ +./User/meshcore/packets/group.d \ +./User/meshcore/packets/multipart.d \ +./User/meshcore/packets/trace.d + +OBJS += \ +./User/meshcore/packets/ack.o \ +./User/meshcore/packets/advert.o \ +./User/meshcore/packets/anonymous.o \ +./User/meshcore/packets/control.o \ +./User/meshcore/packets/custom.o \ +./User/meshcore/packets/encrypted.o \ +./User/meshcore/packets/group.o \ +./User/meshcore/packets/multipart.o \ +./User/meshcore/packets/trace.o + +DIR_OBJS += \ +./User/meshcore/packets/*.o \ + +DIR_DEPS += \ +./User/meshcore/packets/*.d \ + +DIR_EXPANDS += \ +./User/meshcore/packets/*.234r.expand \ + + +# Each subdirectory must supply rules for building sources it contributes +User/meshcore/packets/%.o: ../User/meshcore/packets/%.c + @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -fmax-errors=20 -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"/home/bruno/mounriver-studio-projects/meshcorenortos/Debug" -I"/home/bruno/mounriver-studio-projects/meshcorenortos/Core" -I"/home/bruno/mounriver-studio-projects/meshcorenortos/User" -I"/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + diff --git a/obj/User/meshcore/packets/trace.d b/obj/User/meshcore/packets/trace.d new file mode 100644 index 0000000..eb3cc7b --- /dev/null +++ b/obj/User/meshcore/packets/trace.d @@ -0,0 +1,7 @@ +User/meshcore/packets/trace.o: ../User/meshcore/packets/trace.c \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/packetstructs.h \ + ../User/meshcore/packets/trace.h + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/meshcore/packetstructs.h: + +../User/meshcore/packets/trace.h: diff --git a/obj/User/meshcore/packets/trace.o b/obj/User/meshcore/packets/trace.o new file mode 100644 index 0000000000000000000000000000000000000000..749c8181c0fd7f48c7d8560b52050fcf84a05a87 GIT binary patch literal 2228 zcmb<-^>JflWMqH=MuyJ}2p$7N3>yQOZvs}J!NAYJ$B@pzz`z3Lvw)TIfZ0%jiIEM& zVq)X~Q%tN7iXBX`KzJ+=9tVWS0p>BYux93!Ffc*oAf_-d3Notl33D^^N%IMaGcYiz zFmQ9*aWnHVFfc=zAZtVz7#Ns97C@Z^W->4^NHQ=mFf#}7rUoLZ!xn_8TaoL`ixUyzubomx_? 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Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../User/meshcore/meshcore.c \ +../User/meshcore/meshframing.c \ +../User/meshcore/stats.c + +C_DEPS += \ +./User/meshcore/meshcore.d \ +./User/meshcore/meshframing.d \ +./User/meshcore/stats.d + +OBJS += \ +./User/meshcore/meshcore.o \ +./User/meshcore/meshframing.o \ +./User/meshcore/stats.o + +DIR_OBJS += \ +./User/meshcore/*.o \ + +DIR_DEPS += \ +./User/meshcore/*.d \ + +DIR_EXPANDS += \ +./User/meshcore/*.234r.expand \ + + +# Each subdirectory must supply rules for building sources it contributes +User/meshcore/%.o: ../User/meshcore/%.c + @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -fmax-errors=20 -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"/home/bruno/mounriver-studio-projects/meshcorenortos/Debug" -I"/home/bruno/mounriver-studio-projects/meshcorenortos/Core" -I"/home/bruno/mounriver-studio-projects/meshcorenortos/User" -I"/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + diff --git a/obj/User/subdir.mk b/obj/User/subdir.mk new file mode 100644 index 0000000..719f7fd --- /dev/null +++ b/obj/User/subdir.mk @@ -0,0 +1,38 @@ +################################################################################ +# MRS Version: 2.4.0 +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../User/ch32v30x_it.c \ +../User/main.c \ +../User/sx1262.c \ +../User/system_ch32v30x.c + +C_DEPS += \ +./User/ch32v30x_it.d \ +./User/main.d \ +./User/sx1262.d \ +./User/system_ch32v30x.d + +OBJS += \ +./User/ch32v30x_it.o \ +./User/main.o \ +./User/sx1262.o \ +./User/system_ch32v30x.o + +DIR_OBJS += \ +./User/*.o \ + +DIR_DEPS += \ +./User/*.d \ + +DIR_EXPANDS += \ +./User/*.234r.expand \ + + +# Each subdirectory must supply rules for building sources it contributes +User/%.o: ../User/%.c + @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -fmax-errors=20 -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"/home/bruno/mounriver-studio-projects/meshcorenortos/Debug" -I"/home/bruno/mounriver-studio-projects/meshcorenortos/Core" -I"/home/bruno/mounriver-studio-projects/meshcorenortos/User" -I"/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + diff --git a/obj/User/sx1262.d b/obj/User/sx1262.d new file mode 100644 index 0000000..9c225e3 --- /dev/null +++ b/obj/User/sx1262.d @@ -0,0 +1,93 @@ +User/sx1262.o: ../User/sx1262.c ../User/sx1262.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_gpio.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Core/core_riscv.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/system_ch32v30x.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_conf.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_adc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_bkp.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_can.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_crc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dac.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dbgmcu.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dma.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_exti.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_flash.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_fsmc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_i2c.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_iwdg.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_pwr.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rcc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rtc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_sdio.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_spi.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_tim.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_usart.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_wwdg.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_it.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Debug/debug.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_misc.h \ + ../User/util/log.h + +../User/sx1262.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_gpio.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Core/core_riscv.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/system_ch32v30x.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/User/ch32v30x_conf.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_adc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_bkp.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_can.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_crc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dac.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dbgmcu.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dma.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_exti.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_flash.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_fsmc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_i2c.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_iwdg.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_pwr.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rcc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rtc.h: + +/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_sdio.h: + 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/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dbgmcu.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_dma.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_exti.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_flash.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_fsmc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_gpio.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_i2c.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_iwdg.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_pwr.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rcc.h \ + /home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc/ch32v30x_rtc.h \ + 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z=3Ve&U}#{3gbS#N2a*Gs2O2_y=>ZwAUWkF=97qzxK?(~{S_28g%nR^gU;wSF1Gx{> z1O&-}%mWP%fy{$e#|*XN3=E%<*585TKp50T1JN*b1+vI%yddEMk_QdHfM}?57?#K~ zFo4?hFh0m$5F0cM1Y*P7XAuNhqX%*ysK^A#f!qf&3n@AobU^JqQOFs9pnVr0b)cp( qsJRZylOXeTj2RfRpzVJUA7l=Q28AWEI)PvY252`QBn?jUAO-+KJw77< literal 0 HcmV?d00001 diff --git a/obj/User/util/subdir.mk b/obj/User/util/subdir.mk new file mode 100644 index 0000000..4838da3 --- /dev/null +++ b/obj/User/util/subdir.mk @@ -0,0 +1,29 @@ +################################################################################ +# MRS Version: 2.4.0 +# Automatically-generated file. Do not edit! +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../User/util/hexdump.c + +C_DEPS += \ +./User/util/hexdump.d + +OBJS += \ +./User/util/hexdump.o + +DIR_OBJS += \ +./User/util/*.o \ + +DIR_DEPS += \ +./User/util/*.d \ + +DIR_EXPANDS += \ +./User/util/*.234r.expand \ + + +# Each subdirectory must supply rules for building sources it contributes +User/util/%.o: ../User/util/%.c + @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -fmax-errors=20 -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -I"/home/bruno/mounriver-studio-projects/meshcorenortos/Debug" -I"/home/bruno/mounriver-studio-projects/meshcorenortos/Core" -I"/home/bruno/mounriver-studio-projects/meshcorenortos/User" -I"/home/bruno/mounriver-studio-projects/meshcorenortos/Peripheral/inc" -std=gnu99 -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@)" -c -o "$@" "$<" + diff --git a/obj/makefile b/obj/makefile new file mode 100644 index 0000000..8c38200 --- /dev/null +++ b/obj/makefile @@ -0,0 +1,84 @@ +################################################################################ +# MRS Version: 2.4.0 +# Automatically-generated file. Do not edit! +################################################################################ +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include User/util/subdir.mk +-include User/meshcore/packets/subdir.mk +-include User/meshcore/subdir.mk +-include User/lib/telemetry/subdir.mk +-include User/lib/rtc/subdir.mk +-include User/lib/monocypher/subdir.mk +-include User/lib/cifra/subdir.mk +-include User/lib/adc/subdir.mk +-include User/lib/subdir.mk +-include User/subdir.mk +-include Startup/subdir.mk +-include Peripheral/src/subdir.mk +-include Debug/subdir.mk +-include Core/subdir.mk +-include subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +SECONDARY_FLASH += \ +meshcorenortos.hex \ + +SECONDARY_LIST += \ +meshcorenortos.lst \ + +SECONDARY_SIZE += \ +meshcorenortos.siz \ + + +# All Target +all: + $(MAKE) --no-print-directory main-build + +main-build: meshcorenortos.elf secondary-outputs + +# Tool invocations +meshcorenortos.elf: $(OBJS) $(USER_OBJS_ESCAPE) + @ riscv-none-embed-gcc -march=rv32imacxw -mabi=ilp32 -msmall-data-limit=8 -msave-restore -fmax-errors=20 -Os -fmessage-length=0 -fsigned-char -ffunction-sections -fdata-sections -fno-common -Wunused -Wuninitialized -g -T "/home/bruno/mounriver-studio-projects/meshcorenortos/Ld/Link.ld" -nostartfiles -Xlinker --gc-sections -Wl,-Map,"meshcorenortos.map" --specs=nano.specs --specs=nosys.specs -o "meshcorenortos.elf" $(OBJS) $(LIBS) +meshcorenortos.hex: meshcorenortos.elf + @ riscv-none-embed-objcopy -O ihex "meshcorenortos.elf" "meshcorenortos.hex" +meshcorenortos.lst: meshcorenortos.elf + @ riscv-none-embed-objdump --all-headers --demangle --disassemble -M xw "meshcorenortos.elf" > "meshcorenortos.lst" +meshcorenortos.siz: meshcorenortos.elf + riscv-none-embed-size --format=berkeley "meshcorenortos.elf" + +# Other Targets +clean: + -$(RM) $(DIR_OBJS) $(SECONDARY_FLASH)$(SECONDARY_LIST)$(SECONDARY_SIZE) meshcorenortos.elf + -$(RM) $(DIR_EXPANDS) $(CALLGRAPH_DOT) + -$(RM) $(DIR_DEPS) +secondary-outputs: $(SECONDARY_FLASH) $(SECONDARY_LIST) $(SECONDARY_SIZE) + +.PHONY: all clean dependents + +-include ../makefile.targets \ No newline at end of file diff --git a/obj/meshcorenortos.elf b/obj/meshcorenortos.elf new file mode 100755 index 0000000000000000000000000000000000000000..8081a25dccd039b0f914dc50bdccddc38724c48f GIT binary patch literal 694156 zcmb<-^>JflWMqH=CWg-pFrEnm1H+lgTwuNlg8~CHg9d{HgE*MaAOO?Bz!38Yf>}XA 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a/obj/meshcorenortos.lst b/obj/meshcorenortos.lst new file mode 100644 index 0000000..02742a0 --- /dev/null +++ b/obj/meshcorenortos.lst @@ -0,0 +1,19482 @@ + +meshcorenortos.elf: file format elf32-littleriscv +meshcorenortos.elf +architecture: riscv:rv32, flags 0x00000112: +EXEC_P, HAS_SYMS, D_PAGED +start address 0x00000000 + +Program Header: + LOAD off 0x00001000 vaddr 0x00000000 paddr 0x00000000 align 2**12 + filesz 0x0000e25c memsz 0x0000e25c flags r-x + LOAD off 0x00010000 vaddr 0x20000000 paddr 0x0000e25c align 2**12 + filesz 0x00000208 memsz 0x00001180 flags rw- + LOAD off 0x00010800 vaddr 0x20007800 paddr 0x20007800 align 2**12 + filesz 0x00000000 memsz 0x00000800 flags rw- + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .init 00000004 00000000 00000000 00001000 2**1 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .vector 000001bc 00000004 00000004 00001004 2**1 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .text 0000e09c 000001c0 000001c0 000011c0 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 3 .fini 00000000 0000e25c 0000e25c 00010208 2**0 + CONTENTS, ALLOC, LOAD, CODE + 4 .dalign 00000000 20000000 20000000 00010208 2**0 + CONTENTS + 5 .dlalign 00000000 0000e25c 0000e25c 00010208 2**0 + CONTENTS + 6 .data 00000208 20000000 0000e25c 00010000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 7 .bss 00000f78 20000208 0000e464 00010208 2**2 + ALLOC + 8 .stack 00000800 20007800 20007800 00010800 2**0 + ALLOC + 9 .debug_info 00038f92 00000000 00000000 00010208 2**0 + CONTENTS, READONLY, DEBUGGING + 10 .debug_abbrev 00007410 00000000 00000000 0004919a 2**0 + CONTENTS, READONLY, DEBUGGING + 11 .debug_loc 00018b98 00000000 00000000 000505aa 2**0 + CONTENTS, READONLY, DEBUGGING + 12 .debug_aranges 00001348 00000000 00000000 00069148 2**3 + CONTENTS, READONLY, DEBUGGING + 13 .debug_ranges 00004ea0 00000000 00000000 0006a490 2**3 + CONTENTS, READONLY, DEBUGGING + 14 .debug_line 0002a966 00000000 00000000 0006f330 2**0 + CONTENTS, READONLY, DEBUGGING + 15 .debug_str 00005bf3 00000000 00000000 00099c96 2**0 + CONTENTS, READONLY, DEBUGGING + 16 .comment 00000033 00000000 00000000 0009f889 2**0 + CONTENTS, READONLY + 17 .debug_frame 00004d90 00000000 00000000 0009f8bc 2**2 + CONTENTS, READONLY, DEBUGGING + 18 .stab 000000b4 00000000 00000000 000a464c 2**2 + CONTENTS, READONLY, DEBUGGING + 19 .stabstr 00000183 00000000 00000000 000a4700 2**0 + CONTENTS, READONLY, DEBUGGING +SYMBOL TABLE: +00000000 l d .init 00000000 .init +00000004 l d .vector 00000000 .vector +000001c0 l d .text 00000000 .text +0000e25c l d .fini 00000000 .fini +20000000 l d .dalign 00000000 .dalign +0000e25c l d .dlalign 00000000 .dlalign +20000000 l d .data 00000000 .data +20000208 l d .bss 00000000 .bss +20007800 l d .stack 00000000 .stack +00000000 l d .debug_info 00000000 .debug_info +00000000 l d .debug_abbrev 00000000 .debug_abbrev +00000000 l d .debug_loc 00000000 .debug_loc +00000000 l d .debug_aranges 00000000 .debug_aranges +00000000 l d .debug_ranges 00000000 .debug_ranges +00000000 l d .debug_line 00000000 .debug_line +00000000 l d .debug_str 00000000 .debug_str +00000000 l d .comment 00000000 .comment +00000000 l d .debug_frame 00000000 .debug_frame +00000000 l d .stab 00000000 .stab +00000000 l d .stabstr 00000000 .stabstr +00000000 l df *ABS* 00000000 ./Startup/startup_ch32v30x_D8C.o +00000004 l .vector 00000000 _vector_base +00000000 l df *ABS* 00000000 hexdump.c +00000000 l df *ABS* 00000000 ack.c +00000000 l df *ABS* 00000000 advert.c +00000000 l df *ABS* 00000000 anonymous.c +00000000 l df *ABS* 00000000 control.c +00000000 l df *ABS* 00000000 encrypted.c +00000f5a l F .text 0000009c parse_coord_micro +00000000 l df *ABS* 00000000 group.c +00000000 l df *ABS* 00000000 meshcore.c +00000000 l df *ABS* 00000000 meshframing.c +00000000 l df *ABS* 00000000 rtc.c +0000c3f0 l O .text 00000025 months.5280 +20000210 l O .bss 00000002 daycnt.5339 +00000000 l df *ABS* 00000000 monocypher-ed25519.c +00002c28 l F .text 00000058 load64_be_buf +00002c80 l F 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+00006826 g F .text 00000016 cf_aes_finish +00000970 g F .text 0000016c printAnonRequest +00009f58 g F .text 00000024 strncpy +00002708 g F .text 000000b4 retransmitFrame +000081ca g F .text 0000001c SetBufferBaseAddress +00001eac g F .text 00000040 makeSendGroupMessage +00000adc g F .text 0000026e decodeAnonReq +00008a1c w .text 00000000 TIM7_IRQHandler +0000b2ae g F .text 00000028 _close_r +00008a1c w .text 00000000 CAN2_TX_IRQHandler +20000000 g .dalign 00000000 _data_vma +00008a1c w .text 00000000 TIM5_IRQHandler +00000d4a g F .text 00000062 sendDiscoverResponse +00005fdc g F .text 000001ba crypto_eddsa_check_equation +0000992e g F .text 00000024 memcmp +0000a1ae g F .text 000000fe __swsetup_r +00008a1c w .text 00000000 EXTI9_5_IRQHandler +0000a568 g F .text 000000a0 __sfp +00000ff6 g F .text 000000ba sendEncryptedFrame +000001c8 g F .text 00000028 .hidden __riscv_save_10 +0000b1d6 g F .text 0000002c __sread +00007c46 g F .text 00000066 ResetLora +00008a1c w .text 00000000 ETH_WKUP_IRQHandler +0000a75e g F .text 00000002 __malloc_lock +0000020a g F .text 00000016 .hidden __riscv_restore_4 +0000683c g F .text 00000044 aes_encrypt_ecb +00000200 g F .text 00000020 .hidden __riscv_restore_8 +0000714e g F .text 0000002a Get_ConversionVal +000071f8 g F .text 0000001a int24_to_bytes +0000a3de g F .text 00000066 _fflush_r +000001d6 g F .text 0000001a .hidden __riscv_save_6 +00008a1c w .text 00000000 SPI2_IRQHandler +0000e1e0 g O .text 00000020 __sf_fake_stdin +00000220 g F .text 000000a8 memset +000069f4 g F .text 0000009a cf_blockwise_acc_pad +00000200 g F .text 00000020 .hidden __riscv_restore_9 +0000020a g F .text 00000016 .hidden __riscv_restore_7 +000076f2 g F .text 000002f2 main +00007eda g F .text 000000a6 WriteCommand2 +000034d0 g F .text 00000112 crypto_sha512_final +00008a1c w .text 00000000 TIM10_BRK_IRQHandler +00007a20 g F .text 0000010a LoRaInit +00008a1c w .text 00000000 TIM9_CC_IRQHandler +00003410 g F .text 000000b0 crypto_sha512_init +00007d06 g F .text 000000a6 WriteRegister +0000057e g F .text 00000050 ed25519_verify_ad +0000b27a g F .text 00000006 __sclose +00008a1c w .text 00000000 DMA2_Channel5_IRQHandler +00006ad2 g F .text 000000e8 cf_hmac_init +00009af2 g F .text 000000d4 _malloc_r +0000a190 g F .text 0000001e __ascii_wctomb +00001fe4 g F .text 000000fa processFrame +00006bd2 g F .text 0000004c cf_hmac_finish +00007bc2 g F .text 00000084 WaitForIdle +00008c8c g F .text 00000134 Get_CalibrationValue +000028ea g F .text 000000dc RTC_Set +00008a1c w .text 00000000 DMA1_Channel5_IRQHandler +2000038c g O .bss 00000df0 persistent +00008a1c w .text 00000000 EXTI4_IRQHandler +00009466 g F .text 00000036 Delay_Ms +00008a1c w .text 00000000 USB_LP_CAN1_RX0_IRQHandler +000006b2 g F .text 0000008e saveAdvert +00007250 g F .text 00000042 getNextNode +00008c74 g F .text 00000018 ADC_BufferCmd +00009350 g F .text 0000001a SPI_Cmd +000002c8 g F .text 0000011a strcmp +000087f4 g F .text 000000fa SystemInit +00008a1c w .text 00000000 RNG_IRQHandler +0000823a g F .text 0000012e LoRaBegin +000067d6 g F .text 00000050 cf_aes_init +00009bc6 g F .text 00000042 iprintf +00008a1c w .text 00000000 USB_HP_CAN1_TX_IRQHandler +00009ed2 g F .text 00000046 sprintf +0000dfb0 g O .text 00000100 .hidden __clz_tab +00000000 g .init 00000000 _sinit +0000b280 g F .text 0000002e _write_r +000079e4 g F .text 0000003c LoRaError +00008a1c w .text 00000000 DMA1_Channel3_IRQHandler +00008444 g F .text 00000020 ClearIrqStatus +00008a1c w .text 00000000 ETH_IRQHandler +0000ada4 g F .text 0000010c _printf_common +200001fc g O .data 00000004 _impure_ptr +000070dc g F .text 0000003a Get_ADC_Val +0000702e g F .text 000000ae ADC_Function_Init +00008a1c w .text 00000000 TIM1_UP_IRQHandler +0000a2ac g F .text 00000132 __sflush_r +00007306 g F .text 00000044 getChannel +0000a846 g F .text 0000026a _svfiprintf_r +00008a1c w .text 00000000 WWDG_IRQHandler +00008a1c w .text 00000000 USBHSWakeup_IRQHandler +00008a1c w .text 00000000 DMA2_Channel11_IRQHandler +000098fc g F .text 00000032 __ascii_mbtowc +00008a1c w .text 00000000 Ecall_U_Mode_Handler +00008a1c w .text 00000000 DMA2_Channel6_IRQHandler +00008a1c w .text 00000000 TIM2_IRQHandler +20008000 g .stack 00000000 _eusrstack +0000869c g F .text 00000118 SetTx +000001f0 g F .text 0000000c .hidden __riscv_save_2 +00008a1c w .text 00000000 SW_Handler +00005e6e g F .text 00000028 crypto_eddsa_reduce +00008aa8 g F .text 00000040 ADC_DeInit +0000121e g F .text 00000050 printRequest +2000033c g O .bss 00000034 stats +00008530 g F .text 0000001c GetStatus +00008a1c w .text 00000000 TIM1_BRK_IRQHandler +0000a672 g F .text 00000058 __swhatbuf_r +00008ae8 g F .text 00000056 ADC_Init +00009422 g F .text 00000008 USART_SendData +00008a1c w .text 00000000 DMA2_Channel10_IRQHandler +00007292 g F .text 00000038 getNode +000065da g F .text 000000d8 cf_aes_encrypt +0000755a g F .text 00000100 populateDefaults +00008a1c w .text 00000000 EXTI1_IRQHandler +000092be g F .text 00000010 RTC_WaitForLastTask +20000370 g O .bss 0000000a calendar +000001d6 g F .text 0000001a .hidden __riscv_save_5 +0000949c g F .text 0000003e _write +00008c4a g F .text 00000020 ADC_TempSensorVrefintCmd +20000208 g .data 00000000 _edata +20001180 g .bss 00000000 _end +0000765a g F .text 00000086 LoraApply +00007178 g F .text 00000030 TempSensor_Volt_To_Temper_x10 +00008a1c w .text 00000000 RTCAlarm_IRQHandler +0000e25c g .dlalign 00000000 _data_lma +00008a1c w .text 00000000 TIM10_UP_IRQHandler +00008a1c w .text 00000000 TIM9_TRG_COM_IRQHandler +00008a1c w .text 00000000 UART7_IRQHandler +00008a1c w .text 00000000 USART2_IRQHandler +00008a1c w .text 00000000 UART6_IRQHandler +0000b202 g F .text 00000048 __swrite +000091f2 g F .text 00000018 RTC_ExitConfigMode +2000021e g O .bss 00000001 debugPrint +0000ab1a g F .text 0000028a _vfiprintf_r +0000a608 g F .text 0000006a _fwalk_reent +000088ee g F .text 0000012e SystemCoreClockUpdate +000027bc g F .text 0000009a encrypt_then_mac +0000049e g F .text 0000004e hexdump_compact +00009306 g F .text 0000000c RTC_ClearITPendingBit +0000b434 g F .text 0000000c _kill +00008a1c w .text 00000000 I2C2_ER_IRQHandler +00008a1c w .text 00000000 DMA1_Channel2_IRQHandler +0000e200 g O .text 00000020 __sf_fake_stdout +00009ed2 g F .text 00000046 siprintf +000098cc g F .text 00000008 atoi +000091c6 g F .text 0000001a RTC_ITConfig +000001fc g F .text 00000024 .hidden __riscv_restore_12 +00008a1c w .text 00000000 TIM8_BRK_IRQHandler +0000e0bc g O .text 00000101 _ctype_ +0000b44c g F .text 0000000c _read +00008a1e w .text 00000000 handle_reset +00008a1c w .text 00000000 CAN1_SCE_IRQHandler +00008408 g F .text 0000001c SetPacketType +20000214 g O .bss 00000001 bootedUp +0000700c g F .text 00000022 cf_sha256_digest +00008a1c w .text 00000000 FLASH_IRQHandler +000001f0 g F .text 0000000c .hidden __riscv_save_0 +000087b4 g F .text 0000001e GetIrqStatus +0000370a g F .text 0000008a crypto_ed25519_key_pair +0000b458 g F .text 00000002 _exit +00008160 g F .text 0000004e SetRfFrequency +2000021f g O .bss 00000001 txActive +00008a1c w .text 00000000 USART1_IRQHandler +0000a6ca g F .text 00000094 __smakebuf_r +00009f46 g F .text 00000012 strlen +2000020c g O .bss 00000004 startupTime +0000aeb0 g F .text 000002a2 _printf_i +00008a1c w .text 00000000 SPI3_IRQHandler +000098d4 g F .text 00000006 __locale_ctype_ptr_l +000066ee g F .text 000000e8 cf_aes_decrypt +20000230 g O .bss 00000004 __malloc_sbrk_start +0000915a g F .text 0000001e RCC_APB2PeriphResetCmd +00007116 g F .text 00000038 Get_ADC_Average +00008a1c w .text 00000000 I2C1_ER_IRQHandler +00006f0a g F .text 00000102 cf_sha256_digest_final +00009312 g F .text 0000003e SPI_Init +00008eca g F .text 00000006 NVIC_PriorityGroupConfig +000083a6 g F .text 00000046 SetStopRxTimerOnPreambleDetect +000012dc g F .text 0000058c processCommand +2000022c g O .bss 00000004 __malloc_free_list +000083ec g F .text 0000001c SetLoRaSymbNumTimeout +00000214 g F .text 0000000c .hidden __riscv_restore_1 +0000ab1a g F .text 0000028a _vfprintf_r +00006e7c g F .text 00000068 cf_sha256_init +20000220 g O .bss 00000004 txLost +00001142 g F .text 0000002e sendEncryptedResponse +00000dfa g F .text 00000062 printDiscoverResponse +00008464 g F .text 0000008a ReadCommand +00008eb6 g F .text 0000000a GPIO_ReadInputDataBit +000012b0 g F .text 0000002c sendPathBack +20000020 g O .data 0000016c __global_locale +00008a1c w .text 00000000 USBWakeUp_IRQHandler +0000b404 g F .text 0000000c _close +00009e2a g F .text 0000000c raise +00008a1c w .text 00000000 DMA2_Channel3_IRQHandler + + + +Disassembly of section .init: + +00000000 <_sinit>: + 0: 21f0806f j 8a1e + +Disassembly of section .vector: + +00000004 <_vector_base>: + ... + c: 76e0 flw fs0,108(a3) + e: 0000 unimp + 10: 76e2 flw fa3,56(sp) + 12: 0000 unimp + 14: 0000 unimp + 16: 0000 unimp + 18: 8a1c 0x8a1c + ... + 22: 0000 unimp + 24: 8a1c 0x8a1c + 26: 0000 unimp + 28: 8a1c 0x8a1c + ... + 32: 0000 unimp + 34: 8a1c 0x8a1c + 36: 0000 unimp + 38: 0000 unimp + 3a: 0000 unimp + 3c: 8a1c 0x8a1c + 3e: 0000 unimp + 40: 0000 unimp + 42: 0000 unimp + 44: 8a1c 0x8a1c + 46: 0000 unimp + 48: 8a1c 0x8a1c + 4a: 0000 unimp + 4c: 8a1c 0x8a1c + 4e: 0000 unimp + 50: 8a1c 0x8a1c + 52: 0000 unimp + 54: 8a1c 0x8a1c + 56: 0000 unimp + 58: 8a1c 0x8a1c + 5a: 0000 unimp + 5c: 8a1c 0x8a1c + 5e: 0000 unimp + 60: 8a1c 0x8a1c + 62: 0000 unimp + 64: 8a1c 0x8a1c + 66: 0000 unimp + 68: 8a1c 0x8a1c + 6a: 0000 unimp + 6c: 8a1c 0x8a1c + 6e: 0000 unimp + 70: 8a1c 0x8a1c + 72: 0000 unimp + 74: 8a1c 0x8a1c + 76: 0000 unimp + 78: 8a1c 0x8a1c + 7a: 0000 unimp + 7c: 8a1c 0x8a1c + 7e: 0000 unimp + 80: 8a1c 0x8a1c + 82: 0000 unimp + 84: 8a1c 0x8a1c + 86: 0000 unimp + 88: 8a1c 0x8a1c + 8a: 0000 unimp + 8c: 8a1c 0x8a1c + 8e: 0000 unimp + 90: 8a1c 0x8a1c + 92: 0000 unimp + 94: 8a1c 0x8a1c + 96: 0000 unimp + 98: 8a1c 0x8a1c + 9a: 0000 unimp + 9c: 8a1c 0x8a1c + 9e: 0000 unimp + a0: 8a1c 0x8a1c + a2: 0000 unimp + a4: 8a1c 0x8a1c + a6: 0000 unimp + a8: 8a1c 0x8a1c + aa: 0000 unimp + ac: 8a1c 0x8a1c + ae: 0000 unimp + b0: 8a1c 0x8a1c + b2: 0000 unimp + b4: 8a1c 0x8a1c + b6: 0000 unimp + b8: 8a1c 0x8a1c + ba: 0000 unimp + bc: 8a1c 0x8a1c + be: 0000 unimp + c0: 8a1c 0x8a1c + c2: 0000 unimp + c4: 8a1c 0x8a1c + c6: 0000 unimp + c8: 8a1c 0x8a1c + ca: 0000 unimp + cc: 8a1c 0x8a1c + ce: 0000 unimp + d0: 8a1c 0x8a1c + d2: 0000 unimp + d4: 8a1c 0x8a1c + d6: 0000 unimp + d8: 8a1c 0x8a1c + da: 0000 unimp + dc: 8a1c 0x8a1c + de: 0000 unimp + e0: 8a1c 0x8a1c + e2: 0000 unimp + e4: 8a1c 0x8a1c + e6: 0000 unimp + e8: 8a1c 0x8a1c + ea: 0000 unimp + ec: 8a1c 0x8a1c + ee: 0000 unimp + f0: 8a1c 0x8a1c + f2: 0000 unimp + f4: 8a1c 0x8a1c + f6: 0000 unimp + f8: 8a1c 0x8a1c + fa: 0000 unimp + fc: 8a1c 0x8a1c + fe: 0000 unimp + 100: 8a1c 0x8a1c + 102: 0000 unimp + 104: 0000 unimp + 106: 0000 unimp + 108: 8a1c 0x8a1c + 10a: 0000 unimp + 10c: 8a1c 0x8a1c + 10e: 0000 unimp + 110: 8a1c 0x8a1c + 112: 0000 unimp + 114: 8a1c 0x8a1c + 116: 0000 unimp + 118: 8a1c 0x8a1c + 11a: 0000 unimp + 11c: 8a1c 0x8a1c + 11e: 0000 unimp + 120: 8a1c 0x8a1c + 122: 0000 unimp + 124: 8a1c 0x8a1c + 126: 0000 unimp + 128: 8a1c 0x8a1c + 12a: 0000 unimp + 12c: 8a1c 0x8a1c + 12e: 0000 unimp + 130: 8a1c 0x8a1c + 132: 0000 unimp + 134: 8a1c 0x8a1c + 136: 0000 unimp + 138: 8a1c 0x8a1c + 13a: 0000 unimp + 13c: 8a1c 0x8a1c + 13e: 0000 unimp + 140: 8a1c 0x8a1c + 142: 0000 unimp + 144: 8a1c 0x8a1c + 146: 0000 unimp + 148: 8a1c 0x8a1c + 14a: 0000 unimp + 14c: 8a1c 0x8a1c + 14e: 0000 unimp + 150: 8a1c 0x8a1c + 152: 0000 unimp + 154: 8a1c 0x8a1c + 156: 0000 unimp + 158: 8a1c 0x8a1c + 15a: 0000 unimp + 15c: 8a1c 0x8a1c + 15e: 0000 unimp + 160: 8a1c 0x8a1c + 162: 0000 unimp + 164: 8a1c 0x8a1c + 166: 0000 unimp + 168: 8a1c 0x8a1c + 16a: 0000 unimp + 16c: 8a1c 0x8a1c + 16e: 0000 unimp + 170: 8a1c 0x8a1c + 172: 0000 unimp + 174: 8a1c 0x8a1c + 176: 0000 unimp + 178: 8a1c 0x8a1c + 17a: 0000 unimp + 17c: 8a1c 0x8a1c + 17e: 0000 unimp + 180: 8a1c 0x8a1c + 182: 0000 unimp + 184: 8a1c 0x8a1c + 186: 0000 unimp + 188: 8a1c 0x8a1c + 18a: 0000 unimp + 18c: 8a1c 0x8a1c + 18e: 0000 unimp + 190: 8a1c 0x8a1c + 192: 0000 unimp + 194: 8a1c 0x8a1c + 196: 0000 unimp + 198: 8a1c 0x8a1c + 19a: 0000 unimp + 19c: 8a1c 0x8a1c + 19e: 0000 unimp + 1a0: 8a1c 0x8a1c + ... + +Disassembly of section .text: + +000001c0 <__riscv_save_12>: + 1c0: 7139 addi sp,sp,-64 + 1c2: 4301 li t1,0 + 1c4: c66e sw s11,12(sp) + 1c6: a019 j 1cc <__riscv_save_10+0x4> + +000001c8 <__riscv_save_10>: + 1c8: 7139 addi sp,sp,-64 + 1ca: 5341 li t1,-16 + 1cc: c86a sw s10,16(sp) + 1ce: ca66 sw s9,20(sp) + 1d0: cc62 sw s8,24(sp) + 1d2: ce5e sw s7,28(sp) + 1d4: a019 j 1da <__riscv_save_4+0x4> + +000001d6 <__riscv_save_4>: + 1d6: 7139 addi sp,sp,-64 + 1d8: 5301 li t1,-32 + 1da: d05a sw s6,32(sp) + 1dc: d256 sw s5,36(sp) + 1de: d452 sw s4,40(sp) + 1e0: d64e sw s3,44(sp) + 1e2: d84a sw s2,48(sp) + 1e4: da26 sw s1,52(sp) + 1e6: dc22 sw s0,56(sp) + 1e8: de06 sw ra,60(sp) + 1ea: 40610133 sub sp,sp,t1 + 1ee: 8282 jr t0 + +000001f0 <__riscv_save_0>: + 1f0: 1141 addi sp,sp,-16 + 1f2: c04a sw s2,0(sp) + 1f4: c226 sw s1,4(sp) + 1f6: c422 sw s0,8(sp) + 1f8: c606 sw ra,12(sp) + 1fa: 8282 jr t0 + +000001fc <__riscv_restore_12>: + 1fc: 4db2 lw s11,12(sp) + 1fe: 0141 addi sp,sp,16 + +00000200 <__riscv_restore_10>: + 200: 4d02 lw s10,0(sp) + 202: 4c92 lw s9,4(sp) + 204: 4c22 lw s8,8(sp) + 206: 4bb2 lw s7,12(sp) + 208: 0141 addi sp,sp,16 + +0000020a <__riscv_restore_4>: + 20a: 4b02 lw s6,0(sp) + 20c: 4a92 lw s5,4(sp) + 20e: 4a22 lw s4,8(sp) + 210: 49b2 lw s3,12(sp) + 212: 0141 addi sp,sp,16 + +00000214 <__riscv_restore_0>: + 214: 4902 lw s2,0(sp) + 216: 4492 lw s1,4(sp) + 218: 4422 lw s0,8(sp) + 21a: 40b2 lw ra,12(sp) + 21c: 0141 addi sp,sp,16 + 21e: 8082 ret + +00000220 : + 220: 433d li t1,15 + 222: 872a mv a4,a0 + 224: 02c37363 bgeu t1,a2,24a + 228: 00f77793 andi a5,a4,15 + 22c: efbd bnez a5,2aa + 22e: e5ad bnez a1,298 + 230: ff067693 andi a3,a2,-16 + 234: 8a3d andi a2,a2,15 + 236: 96ba add a3,a3,a4 + 238: c30c sw a1,0(a4) + 23a: c34c sw a1,4(a4) + 23c: c70c sw a1,8(a4) + 23e: c74c sw a1,12(a4) + 240: 0741 addi a4,a4,16 + 242: fed76be3 bltu a4,a3,238 + 246: e211 bnez a2,24a + 248: 8082 ret + 24a: 40c306b3 sub a3,t1,a2 + 24e: 068a slli a3,a3,0x2 + 250: 00000297 auipc t0,0x0 + 254: 9696 add a3,a3,t0 + 256: 00a68067 jr 10(a3) + 25a: 00b70723 sb a1,14(a4) + 25e: 00b706a3 sb a1,13(a4) + 262: 00b70623 sb a1,12(a4) + 266: 00b705a3 sb a1,11(a4) + 26a: 00b70523 sb a1,10(a4) + 26e: 00b704a3 sb a1,9(a4) + 272: 00b70423 sb a1,8(a4) + 276: 00b703a3 sb a1,7(a4) + 27a: 00b70323 sb a1,6(a4) + 27e: 00b702a3 sb a1,5(a4) + 282: 00b70223 sb a1,4(a4) + 286: 00b701a3 sb a1,3(a4) + 28a: 00b70123 sb a1,2(a4) + 28e: 00b700a3 sb a1,1(a4) + 292: 00b70023 sb a1,0(a4) + 296: 8082 ret + 298: 0ff5f593 andi a1,a1,255 + 29c: 00859693 slli a3,a1,0x8 + 2a0: 8dd5 or a1,a1,a3 + 2a2: 01059693 slli a3,a1,0x10 + 2a6: 8dd5 or a1,a1,a3 + 2a8: b761 j 230 + 2aa: 00279693 slli a3,a5,0x2 + 2ae: 00000297 auipc t0,0x0 + 2b2: 9696 add a3,a3,t0 + 2b4: 8286 mv t0,ra + 2b6: fa8680e7 jalr -88(a3) + 2ba: 8096 mv ra,t0 + 2bc: 17c1 addi a5,a5,-16 + 2be: 8f1d sub a4,a4,a5 + 2c0: 963e add a2,a2,a5 + 2c2: f8c374e3 bgeu t1,a2,24a + 2c6: b7a5 j 22e + +000002c8 : + 2c8: 00b56733 or a4,a0,a1 + 2cc: 53fd li t2,-1 + 2ce: 8b0d andi a4,a4,3 + 2d0: e779 bnez a4,39e + 2d2: 7f7f87b7 lui a5,0x7f7f8 + 2d6: f7f78793 addi a5,a5,-129 # 7f7f7f7f <_eusrstack+0x5f7eff7f> + 2da: 4110 lw a2,0(a0) + 2dc: 4194 lw a3,0(a1) + 2de: 00f672b3 and t0,a2,a5 + 2e2: 00f66333 or t1,a2,a5 + 2e6: 92be add t0,t0,a5 + 2e8: 0062e2b3 or t0,t0,t1 + 2ec: 0c729563 bne t0,t2,3b6 + 2f0: 06d61863 bne a2,a3,360 + 2f4: 4150 lw a2,4(a0) + 2f6: 41d4 lw a3,4(a1) + 2f8: 00f672b3 and t0,a2,a5 + 2fc: 00f66333 or t1,a2,a5 + 300: 92be add t0,t0,a5 + 302: 0062e2b3 or t0,t0,t1 + 306: 0a729663 bne t0,t2,3b2 + 30a: 04d61b63 bne a2,a3,360 + 30e: 4510 lw a2,8(a0) + 310: 4594 lw a3,8(a1) + 312: 00f672b3 and t0,a2,a5 + 316: 00f66333 or t1,a2,a5 + 31a: 92be add t0,t0,a5 + 31c: 0062e2b3 or t0,t0,t1 + 320: 08729f63 bne t0,t2,3be + 324: 02d61e63 bne a2,a3,360 + 328: 4550 lw a2,12(a0) + 32a: 45d4 lw a3,12(a1) + 32c: 00f672b3 and t0,a2,a5 + 330: 00f66333 or t1,a2,a5 + 334: 92be add t0,t0,a5 + 336: 0062e2b3 or t0,t0,t1 + 33a: 08729863 bne t0,t2,3ca + 33e: 02d61163 bne a2,a3,360 + 342: 4910 lw a2,16(a0) + 344: 4994 lw a3,16(a1) + 346: 00f672b3 and t0,a2,a5 + 34a: 00f66333 or t1,a2,a5 + 34e: 92be add t0,t0,a5 + 350: 0062e2b3 or t0,t0,t1 + 354: 08729163 bne t0,t2,3d6 + 358: 0551 addi a0,a0,20 + 35a: 05d1 addi a1,a1,20 + 35c: f6d60fe3 beq a2,a3,2da + 360: 01061713 slli a4,a2,0x10 + 364: 01069793 slli a5,a3,0x10 + 368: 00f71c63 bne a4,a5,380 + 36c: 01065713 srli a4,a2,0x10 + 370: 0106d793 srli a5,a3,0x10 + 374: 40f70533 sub a0,a4,a5 + 378: 0ff57593 andi a1,a0,255 + 37c: e991 bnez a1,390 + 37e: 8082 ret + 380: 8341 srli a4,a4,0x10 + 382: 83c1 srli a5,a5,0x10 + 384: 40f70533 sub a0,a4,a5 + 388: 0ff57593 andi a1,a0,255 + 38c: e191 bnez a1,390 + 38e: 8082 ret + 390: 0ff77713 andi a4,a4,255 + 394: 0ff7f793 andi a5,a5,255 + 398: 40f70533 sub a0,a4,a5 + 39c: 8082 ret + 39e: 2110 lbu a2,0(a0) + 3a0: 2194 lbu a3,0(a1) + 3a2: 0505 addi a0,a0,1 + 3a4: 0585 addi a1,a1,1 + 3a6: 00d61363 bne a2,a3,3ac + 3aa: fa75 bnez a2,39e + 3ac: 40d60533 sub a0,a2,a3 + 3b0: 8082 ret + 3b2: 0511 addi a0,a0,4 + 3b4: 0591 addi a1,a1,4 + 3b6: fed614e3 bne a2,a3,39e + 3ba: 4501 li a0,0 + 3bc: 8082 ret + 3be: 0521 addi a0,a0,8 + 3c0: 05a1 addi a1,a1,8 + 3c2: fcd61ee3 bne a2,a3,39e + 3c6: 4501 li a0,0 + 3c8: 8082 ret + 3ca: 0531 addi a0,a0,12 + 3cc: 05b1 addi a1,a1,12 + 3ce: fcd618e3 bne a2,a3,39e + 3d2: 4501 li a0,0 + 3d4: 8082 ret + 3d6: 0541 addi a0,a0,16 + 3d8: 05c1 addi a1,a1,16 + 3da: fcd612e3 bne a2,a3,39e + 3de: 4501 li a0,0 + 3e0: 8082 ret + +000003e2 : + 3e2: ddfff2ef jal t0,1c0 <__riscv_save_12> + 3e6: 1141 addi sp,sp,-16 + 3e8: 8aae mv s5,a1 + 3ea: 8932 mv s2,a2 + 3ec: c901 beqz a0,3fc + 3ee: 85aa mv a1,a0 + 3f0: 0000b537 lui a0,0xb + 3f4: 45c50513 addi a0,a0,1116 # b45c <_exit+0x4> + 3f8: 7ce090ef jal ra,9bc6 + 3fc: 89d6 mv s3,s5 + 3fe: 8a4a mv s4,s2 + 400: 44c1 li s1,16 + 402: 0000bb37 lui s6,0xb + 406: 0000bbb7 lui s7,0xb + 40a: 0000bc37 lui s8,0xb + 40e: 0000ecb7 lui s9,0xe + 412: 0000bd37 lui s10,0xb + 416: ff048413 addi s0,s1,-16 + 41a: 01246463 bltu s0,s2,422 + 41e: 0141 addi sp,sp,16 + 420: bbf1 j 1fc <__riscv_restore_12> + 422: 85a2 mv a1,s0 + 424: 46cb0513 addi a0,s6,1132 # b46c <_exit+0x14> + 428: 79e090ef jal ra,9bc6 + 42c: 07247463 bgeu s0,s2,494 + 430: 008a87b3 add a5,s5,s0 + 434: 238c lbu a1,0(a5) + 436: 474c0513 addi a0,s8,1140 # b474 <_exit+0x1c> + 43a: 78c090ef jal ra,9bc6 + 43e: 0405 addi s0,s0,1 + 440: fe8496e3 bne s1,s0,42c + 444: 224c8513 addi a0,s9,548 # e224 <__sf_fake_stdout+0x24> + 448: 77e090ef jal ra,9bc6 + 44c: 4401 li s0,0 + 44e: 4dc1 li s11,16 + 450: 028a0863 beq s4,s0,480 + 454: 008987b3 add a5,s3,s0 + 458: 238c lbu a1,0(a5) + 45a: c62e sw a1,12(sp) + 45c: 47e090ef jal ra,98da <__locale_ctype_ptr> + 460: 45b2 lw a1,12(sp) + 462: 952e add a0,a0,a1 + 464: 00150783 lb a5,1(a0) + 468: 0977f793 andi a5,a5,151 + 46c: e399 bnez a5,472 + 46e: 02e00593 li a1,46 + 472: 480d0513 addi a0,s10,1152 # b480 <_exit+0x28> + 476: 0405 addi s0,s0,1 + 478: 74e090ef jal ra,9bc6 + 47c: fdb41ae3 bne s0,s11,450 + 480: 0000e537 lui a0,0xe + 484: 99850513 addi a0,a0,-1640 # d998 + 488: 73e090ef jal ra,9bc6 + 48c: 04c1 addi s1,s1,16 + 48e: 1a41 addi s4,s4,-16 + 490: 09c1 addi s3,s3,16 + 492: b751 j 416 + 494: 47cb8513 addi a0,s7,1148 # b47c <_exit+0x24> + 498: 72e090ef jal ra,9bc6 + 49c: b74d j 43e + +0000049e : + 49e: d39ff2ef jal t0,1d6 <__riscv_save_4> + 4a2: 8432 mv s0,a2 + 4a4: 8936 mv s2,a3 + 4a6: 84aa mv s1,a0 + 4a8: 00b50a33 add s4,a0,a1 + 4ac: 4781 li a5,0 + 4ae: ffe60a93 addi s5,a2,-2 + 4b2: 0000bb37 lui s6,0xb + 4b6: 01448663 beq s1,s4,4c2 + 4ba: 00278993 addi s3,a5,2 + 4be: 0129e863 bltu s3,s2,4ce + 4c2: 0327e163 bltu a5,s2,4e4 + 4c6: 944a add s0,s0,s2 + 4c8: fe040fa3 sb zero,-1(s0) + 4cc: a839 j 4ea + 4ce: 2094 lbu a3,0(s1) + 4d0: 484b0613 addi a2,s6,1156 # b484 <_exit+0x2c> + 4d4: 458d li a1,3 + 4d6: 013a8533 add a0,s5,s3 + 4da: 18d090ef jal ra,9e66 + 4de: 0485 addi s1,s1,1 + 4e0: 87ce mv a5,s3 + 4e2: bfd1 j 4b6 + 4e4: 943e add s0,s0,a5 + 4e6: 00040023 sb zero,0(s0) + 4ea: b305 j 20a <__riscv_restore_4> + +000004ec : + 4ec: d05ff2ef jal t0,1f0 <__riscv_save_0> + 4f0: 7165 addi sp,sp,-400 + 4f2: 8432 mv s0,a2 + 4f4: 84aa mv s1,a0 + 4f6: 892e mv s2,a1 + 4f8: 10400613 li a2,260 + 4fc: 4581 li a1,0 + 4fe: 0168 addi a0,sp,140 + 500: 3305 jal 220 + 502: 47b5 li a5,13 + 504: 1048 addi a0,sp,36 + 506: 08f10623 sb a5,140(sp) + 50a: 173060ef jal ra,6e7c + 50e: 864a mv a2,s2 + 510: 85a6 mv a1,s1 + 512: 1048 addi a0,sp,36 + 514: 1d1060ef jal ra,6ee4 + 518: 02000613 li a2,32 + 51c: 85a2 mv a1,s0 + 51e: 1048 addi a0,sp,36 + 520: 1c5060ef jal ra,6ee4 + 524: 004c addi a1,sp,4 + 526: 1048 addi a0,sp,36 + 528: 2e5060ef jal ra,700c + 52c: 4792 lw a5,4(sp) + 52e: 0168 addi a0,sp,140 + 530: cdbe sw a5,216(sp) + 532: 4791 li a5,4 + 534: cbbe sw a5,212(sp) + 536: 765010ef jal ra,249a + 53a: 6159 addi sp,sp,400 + 53c: b9e1 j 214 <__riscv_restore_0> + +0000053e : + 53e: cb3ff2ef jal t0,1f0 <__riscv_save_0> + 542: 7111 addi sp,sp,-256 + 544: 842a mv s0,a0 + 546: 04c50593 addi a1,a0,76 + 54a: 02400613 li a2,36 + 54e: 850a mv a0,sp + 550: 402090ef jal ra,9952 + 554: 4424 lw s1,72(s0) + 556: 0b040593 addi a1,s0,176 + 55a: 1048 addi a0,sp,36 + 55c: f9c48613 addi a2,s1,-100 + 560: 3f2090ef jal ra,9952 + 564: 200005b7 lui a1,0x20000 + 568: 860a mv a2,sp + 56a: fc048693 addi a3,s1,-64 + 56e: 39058593 addi a1,a1,912 # 20000390 + 572: 07040513 addi a0,s0,112 + 576: 21e030ef jal ra,3794 + 57a: 6111 addi sp,sp,256 + 57c: b961 j 214 <__riscv_restore_0> + +0000057e : + 57e: 0af54783 lbu a5,175(a0) + 582: 0e07f793 andi a5,a5,224 + 586: e3b1 bnez a5,5ca + 588: c69ff2ef jal t0,1f0 <__riscv_save_0> + 58c: 7111 addi sp,sp,-256 + 58e: 04c50493 addi s1,a0,76 + 592: 842a mv s0,a0 + 594: 85a6 mv a1,s1 + 596: 02400613 li a2,36 + 59a: 850a mv a0,sp + 59c: 3b6090ef jal ra,9952 + 5a0: 04842903 lw s2,72(s0) + 5a4: 0b040593 addi a1,s0,176 + 5a8: 1048 addi a0,sp,36 + 5aa: f9c90613 addi a2,s2,-100 + 5ae: 3a4090ef jal ra,9952 + 5b2: 860a mv a2,sp + 5b4: fc090693 addi a3,s2,-64 + 5b8: 85a6 mv a1,s1 + 5ba: 07040513 addi a0,s0,112 + 5be: 1ea030ef jal ra,37a8 + 5c2: 00153513 seqz a0,a0 + 5c6: 6111 addi sp,sp,256 + 5c8: b1b1 j 214 <__riscv_restore_0> + 5ca: 4501 li a0,0 + 5cc: 8082 ret + +000005ce : + 5ce: c09ff2ef jal t0,1d6 <__riscv_save_4> + 5d2: 00153513 seqz a0,a0 + 5d6: 20000437 lui s0,0x20000 + 5da: 716d addi sp,sp,-272 + 5dc: 0545 addi a0,a0,17 + 5de: 38c40413 addi s0,s0,908 # 2000038c + 5e2: 8648 sb a0,12(sp) + 5e4: 02000613 li a2,32 + 5e8: 02440593 addi a1,s0,36 + 5ec: 08a8 addi a0,sp,88 + 5ee: 364090ef jal ra,9952 + 5f2: 419080ef jal ra,920a + 5f6: 04444703 lbu a4,68(s0) + 5fa: dcaa sw a0,120(sp) + 5fc: 4685 li a3,1 + 5fe: 89aa mv s3,a0 + 600: 08100793 li a5,129 + 604: 02d70363 beq a4,a3,62a + 608: 4689 li a3,2 + 60a: 08200793 li a5,130 + 60e: 00d70e63 beq a4,a3,62a + 612: 468d li a3,3 + 614: 08300793 li a5,131 + 618: 00d70963 beq a4,a3,62a + 61c: 4691 li a3,4 + 61e: 08000793 li a5,128 + 622: 00d71463 bne a4,a3,62a + 626: 08400793 li a5,132 + 62a: 20000437 lui s0,0x20000 + 62e: 3d140513 addi a0,s0,977 # 200003d1 + 632: 0af10e23 sb a5,188(sp) + 636: 111090ef jal ra,9f46 + 63a: 84aa mv s1,a0 + 63c: 862a mv a2,a0 + 63e: 3d140593 addi a1,s0,977 + 642: 0bd10513 addi a0,sp,189 + 646: 30c090ef jal ra,9952 + 64a: 06548913 addi s2,s1,101 + 64e: 0068 addi a0,sp,12 + 650: caca sw s2,84(sp) + 652: 35f5 jal 53e + 654: 0000b537 lui a0,0xb + 658: 08ac addi a1,sp,88 + 65a: 02000613 li a2,32 + 65e: 5d450513 addi a0,a0,1492 # b5d4 <_exit+0x17c> + 662: 3341 jal 3e2 + 664: 0000b537 lui a0,0xb + 668: 18ec addi a1,sp,124 + 66a: 04000613 li a2,64 + 66e: 5e050513 addi a0,a0,1504 # b5e0 <_exit+0x188> + 672: 3b85 jal 3e2 + 674: 0000b537 lui a0,0xb + 678: 00148613 addi a2,s1,1 + 67c: 196c addi a1,sp,188 + 67e: 5ec50513 addi a0,a0,1516 # b5ec <_exit+0x194> + 682: 3385 jal 3e2 + 684: 0000b537 lui a0,0xb + 688: 85ce mv a1,s3 + 68a: 5f450513 addi a0,a0,1524 # b5f4 <_exit+0x19c> + 68e: 538090ef jal ra,9bc6 + 692: 0000b537 lui a0,0xb + 696: 3d140593 addi a1,s0,977 + 69a: 60850513 addi a0,a0,1544 # b608 <_exit+0x1b0> + 69e: 528090ef jal ra,9bc6 + 6a2: 0068 addi a0,sp,12 + 6a4: caca sw s2,84(sp) + 6a6: 000108a3 sb zero,17(sp) + 6aa: 5f1010ef jal ra,249a + 6ae: 6151 addi sp,sp,272 + 6b0: bea9 j 20a <__riscv_restore_4> + +000006b2 : + 6b2: b3fff2ef jal t0,1f0 <__riscv_save_0> + 6b6: 84aa mv s1,a0 + 6b8: 2108 lbu a0,0(a0) + 6ba: 7119 addi sp,sp,-128 + 6bc: 3d7060ef jal ra,7292 + 6c0: 842a mv s0,a0 + 6c2: e901 bnez a0,6d2 + 6c4: 38d060ef jal ra,7250 + 6c8: 0b800613 li a2,184 + 6cc: 4581 li a1,0 + 6ce: 842a mv s0,a0 + 6d0: 3e81 jal 220 + 6d2: 07448593 addi a1,s1,116 + 6d6: 02000613 li a2,32 + 6da: 8522 mv a0,s0 + 6dc: 276090ef jal ra,9952 + 6e0: 02000613 li a2,32 + 6e4: 85a6 mv a1,s1 + 6e6: 02040513 addi a0,s0,32 + 6ea: 268090ef jal ra,9952 + 6ee: 85a6 mv a1,s1 + 6f0: 850a mv a0,sp + 6f2: 2cb050ef jal ra,61bc + 6f6: 200005b7 lui a1,0x20000 + 6fa: 02000613 li a2,32 + 6fe: 0088 addi a0,sp,64 + 700: 39058593 addi a1,a1,912 # 20000390 + 704: 745020ef jal ra,3648 + 708: 008c addi a1,sp,64 + 70a: 1008 addi a0,sp,32 + 70c: 708050ef jal ra,5e14 + 710: 860a mv a2,sp + 712: 100c addi a1,sp,32 + 714: 04040513 addi a0,s0,64 + 718: 728050ef jal ra,5e40 + 71c: 54bc lw a5,104(s1) + 71e: d03c sw a5,96(s0) + 720: 54fc lw a5,108(s1) + 722: d07c sw a5,100(s0) + 724: 0654c783 lbu a5,101(s1) + 728: 8bbd andi a5,a5,15 + 72a: 0af40523 sb a5,170(s0) + 72e: 2dd080ef jal ra,920a + 732: 509c lw a5,32(s1) + 734: 0aa42823 sw a0,176(s0) + 738: 0af42623 sw a5,172(s0) + 73c: 6109 addi sp,sp,128 + 73e: bcd9 j 214 <__riscv_restore_0> + +00000740 : + 740: ab1ff2ef jal t0,1f0 <__riscv_save_0> + 744: 06554783 lbu a5,101(a0) + 748: 842a mv s0,a0 + 74a: 07450593 addi a1,a0,116 + 74e: 01879713 slli a4,a5,0x18 + 752: 8761 srai a4,a4,0x18 + 754: 00074663 bltz a4,760 + 758: 0000b5b7 lui a1,0xb + 75c: 55858593 addi a1,a1,1368 # b558 <_exit+0x100> + 760: 8b9d andi a5,a5,7 + 762: 4691 li a3,4 + 764: 5010 lw a2,32(s0) + 766: 04d78d63 beq a5,a3,7c0 + 76a: 468d li a3,3 + 76c: 04d78f63 beq a5,a3,7ca + 770: 4689 li a3,2 + 772: 06d78163 beq a5,a3,7d4 + 776: 0000b6b7 lui a3,0xb + 77a: 58868693 addi a3,a3,1416 # b588 <_exit+0x130> + 77e: 06074063 bltz a4,7de + 782: 0000b737 lui a4,0xb + 786: 59c70713 addi a4,a4,1436 # b59c <_exit+0x144> + 78a: 06c42803 lw a6,108(s0) + 78e: 543c lw a5,104(s0) + 790: 0000b537 lui a0,0xb + 794: 5a450513 addi a0,a0,1444 # b5a4 <_exit+0x14c> + 798: 42e090ef jal ra,9bc6 + 79c: 0000b537 lui a0,0xb + 7a0: 85a2 mv a1,s0 + 7a2: 02000613 li a2,32 + 7a6: 5d450513 addi a0,a0,1492 # b5d4 <_exit+0x17c> + 7aa: 3925 jal 3e2 + 7ac: 0000b537 lui a0,0xb + 7b0: 04000613 li a2,64 + 7b4: 02440593 addi a1,s0,36 + 7b8: 5e050513 addi a0,a0,1504 # b5e0 <_exit+0x188> + 7bc: 311d jal 3e2 + 7be: bc99 j 214 <__riscv_restore_0> + 7c0: 0000b6b7 lui a3,0xb + 7c4: 57468693 addi a3,a3,1396 # b574 <_exit+0x11c> + 7c8: bf5d j 77e + 7ca: 0000b6b7 lui a3,0xb + 7ce: 57c68693 addi a3,a3,1404 # b57c <_exit+0x124> + 7d2: b775 j 77e + 7d4: 0000b6b7 lui a3,0xb + 7d8: 56868693 addi a3,a3,1384 # b568 <_exit+0x110> + 7dc: b74d j 77e + 7de: 0000b737 lui a4,0xb + 7e2: 59470713 addi a4,a4,1428 # b594 <_exit+0x13c> + 7e6: b755 j 78a + +000007e8 : + 7e8: 9efff2ef jal t0,1d6 <__riscv_save_4> + 7ec: 7171 addi sp,sp,-176 + 7ee: 842a mv s0,a0 + 7f0: 09400613 li a2,148 + 7f4: 4581 li a1,0 + 7f6: 0868 addi a0,sp,28 + 7f8: 3425 jal 220 + 7fa: 4434 lw a3,72(s0) + 7fc: 06400793 li a5,100 + 800: 0000bab7 lui s5,0xb + 804: 02d7e063 bltu a5,a3,824 <__stack_size+0x24> + 808: 0000b5b7 lui a1,0xb + 80c: 0000b537 lui a0,0xb + 810: 48ca8613 addi a2,s5,1164 # b48c <_exit+0x34> + 814: 49458593 addi a1,a1,1172 # b494 <_exit+0x3c> + 818: 49850513 addi a0,a0,1176 # b498 <_exit+0x40> + 81c: 3aa090ef jal ra,9bc6 + 820: 614d addi sp,sp,176 + 822: b2e5 j 20a <__riscv_restore_4> + 824: 8522 mv a0,s0 + 826: 3ba1 jal 57e + 828: 48ca8613 addi a2,s5,1164 + 82c: ed01 bnez a0,844 <__stack_size+0x44> + 82e: 0000b5b7 lui a1,0xb + 832: 0000b537 lui a0,0xb + 836: 49458593 addi a1,a1,1172 # b494 <_exit+0x3c> + 83a: 4cc50513 addi a0,a0,1228 # b4cc <_exit+0x74> + 83e: 388090ef jal ra,9bc6 + 842: bff9 j 820 <__stack_size+0x20> + 844: 0000b5b7 lui a1,0xb + 848: 0000b537 lui a0,0xb + 84c: 4ec58593 addi a1,a1,1260 # b4ec <_exit+0x94> + 850: 4f050513 addi a0,a0,1264 # b4f0 <_exit+0x98> + 854: 372090ef jal ra,9bc6 + 858: 04c40a13 addi s4,s0,76 + 85c: 4785 li a5,1 + 85e: 02000613 li a2,32 + 862: 85d2 mv a1,s4 + 864: 0868 addi a0,sp,28 + 866: 08f10023 sb a5,128(sp) + 86a: 0e8090ef jal ra,9952 + 86e: 4611 li a2,4 + 870: 06c40593 addi a1,s0,108 + 874: 1868 addi a0,sp,60 + 876: 0dc090ef jal ra,9952 + 87a: 04000613 li a2,64 + 87e: 07040593 addi a1,s0,112 + 882: 0088 addi a0,sp,64 + 884: 0ce090ef jal ra,9952 + 888: 0b044783 lbu a5,176(s0) + 88c: 06500993 li s3,101 + 890: 08f100a3 sb a5,129(sp) + 894: 0107f613 andi a2,a5,16 + 898: c219 beqz a2,89e <__stack_size+0x9e> + 89a: 06d00993 li s3,109 + 89e: 0207fb13 andi s6,a5,32 + 8a2: 84ce mv s1,s3 + 8a4: 000b0463 beqz s6,8ac <__stack_size+0xac> + 8a8: 00298493 addi s1,s3,2 + 8ac: 0407f913 andi s2,a5,64 + 8b0: 8726 mv a4,s1 + 8b2: 00090663 beqz s2,8be <__stack_size+0xbe> + 8b6: 00248713 addi a4,s1,2 + 8ba: 0ff77713 andi a4,a4,255 + 8be: 4434 lw a3,72(s0) + 8c0: 00e6ff63 bgeu a3,a4,8de <__stack_size+0xde> + 8c4: 0000b5b7 lui a1,0xb + 8c8: 0000b537 lui a0,0xb + 8cc: 48ca8613 addi a2,s5,1164 + 8d0: 49458593 addi a1,a1,1172 # b494 <_exit+0x3c> + 8d4: 51850513 addi a0,a0,1304 # b518 <_exit+0xc0> + 8d8: 2ee090ef jal ra,9bc6 + 8dc: b791 j 820 <__stack_size+0x20> + 8de: c20d beqz a2,900 <__stack_size+0x100> + 8e0: 4611 li a2,4 + 8e2: 0b140593 addi a1,s0,177 + 8e6: 0148 addi a0,sp,132 + 8e8: c63a sw a4,12(sp) + 8ea: c436 sw a3,8(sp) + 8ec: 066090ef jal ra,9952 + 8f0: 4611 li a2,4 + 8f2: 0b540593 addi a1,s0,181 + 8f6: 0128 addi a0,sp,136 + 8f8: 05a090ef jal ra,9952 + 8fc: 4732 lw a4,12(sp) + 8fe: 46a2 lw a3,8(sp) + 900: 000b0b63 beqz s6,916 <__stack_size+0x116> + 904: 99d2 add s3,s3,s4 + 906: 0009c783 lbu a5,0(s3) + 90a: 08f10623 sb a5,140(sp) + 90e: 0019c783 lbu a5,1(s3) + 912: 08f106a3 sb a5,141(sp) + 916: 00090963 beqz s2,928 <__stack_size+0x128> + 91a: 94d2 add s1,s1,s4 + 91c: 209c lbu a5,0(s1) + 91e: 08f10723 sb a5,142(sp) + 922: 309c lbu a5,1(s1) + 924: 08f107a3 sb a5,143(sp) + 928: 8e99 sub a3,a3,a4 + 92a: 0ff6f693 andi a3,a3,255 + 92e: 47fd li a5,31 + 930: 0ff6f413 andi s0,a3,255 + 934: 00d7f363 bgeu a5,a3,93a <__stack_size+0x13a> + 938: 447d li s0,31 + 93a: 8622 mv a2,s0 + 93c: 00ea05b3 add a1,s4,a4 + 940: 0908 addi a0,sp,144 + 942: 010090ef jal ra,9952 + 946: 191c addi a5,sp,176 + 948: 943e add s0,s0,a5 + 94a: 0868 addi a0,sp,28 + 94c: fe040023 sb zero,-32(s0) + 950: 3bc5 jal 740 + 952: 0868 addi a0,sp,28 + 954: 3bb9 jal 6b2 + 956: b5e9 j 820 <__stack_size+0x20> + +00000958 : + 958: 4781 li a5,0 + 95a: 00b78763 beq a5,a1,968 + 95e: 00f50733 add a4,a0,a5 + 962: 00070703 lb a4,0(a4) + 966: e319 bnez a4,96c + 968: 853e mv a0,a5 + 96a: 8082 ret + 96c: 0785 addi a5,a5,1 + 96e: b7f5 j 95a + +00000970 : + 970: 16050563 beqz a0,ada + 974: 863ff2ef jal t0,1d6 <__riscv_save_4> + 978: 842a mv s0,a0 + 97a: 89ae mv s3,a1 + 97c: 85aa mv a1,a0 + 97e: 0000b537 lui a0,0xb + 982: 75450513 addi a0,a0,1876 # b754 <_exit+0x2fc> + 986: 240090ef jal ra,9bc6 + 98a: 200c lbu a1,0(s0) + 98c: 0000b537 lui a0,0xb + 990: 77450513 addi a0,a0,1908 # b774 <_exit+0x31c> + 994: 232090ef jal ra,9bc6 + 998: 0000b537 lui a0,0xb + 99c: 79050513 addi a0,a0,1936 # b790 <_exit+0x338> + 9a0: 226090ef jal ra,9bc6 + 9a4: 4485 li s1,1 + 9a6: 0000ba37 lui s4,0xb + 9aa: 02100913 li s2,33 + 9ae: 009407b3 add a5,s0,s1 + 9b2: 238c lbu a1,0(a5) + 9b4: 7a4a0513 addi a0,s4,1956 # b7a4 <_exit+0x34c> + 9b8: 0485 addi s1,s1,1 + 9ba: 20c090ef jal ra,9bc6 + 9be: ff2498e3 bne s1,s2,9ae + 9c2: 0000e937 lui s2,0xe + 9c6: 99890513 addi a0,s2,-1640 # d998 + 9ca: 1fc090ef jal ra,9bc6 + 9ce: 302e lhu a1,34(s0) + 9d0: 0000b537 lui a0,0xb + 9d4: 7ac50513 addi a0,a0,1964 # b7ac <_exit+0x354> + 9d8: 1ee090ef jal ra,9bc6 + 9dc: 02444583 lbu a1,36(s0) + 9e0: 0000b537 lui a0,0xb + 9e4: 7c450513 addi a0,a0,1988 # b7c4 <_exit+0x36c> + 9e8: 1de090ef jal ra,9bc6 + 9ec: 02444703 lbu a4,36(s0) + 9f0: 478d li a5,3 + 9f2: 4481 li s1,0 + 9f4: 02e7f763 bgeu a5,a4,a22 + 9f8: 02644783 lbu a5,38(s0) + 9fc: 02544703 lbu a4,37(s0) + a00: 02844583 lbu a1,40(s0) + a04: 07a2 slli a5,a5,0x8 + a06: 8f5d or a4,a4,a5 + a08: 02744783 lbu a5,39(s0) + a0c: 05e2 slli a1,a1,0x18 + a0e: 0000b537 lui a0,0xb + a12: 07c2 slli a5,a5,0x10 + a14: 8fd9 or a5,a5,a4 + a16: 8ddd or a1,a1,a5 + a18: 7e850513 addi a0,a0,2024 # b7e8 <_exit+0x390> + a1c: 1aa090ef jal ra,9bc6 + a20: 4491 li s1,4 + a22: 04098c63 beqz s3,a7a + a26: 02444783 lbu a5,36(s0) + a2a: 00348693 addi a3,s1,3 + a2e: 04f6d663 bge a3,a5,a7a + a32: 00148713 addi a4,s1,1 + a36: 0ff77713 andi a4,a4,255 + a3a: 009407b3 add a5,s0,s1 + a3e: 9722 add a4,a4,s0 + a40: 0257c603 lbu a2,37(a5) + a44: 02574783 lbu a5,37(a4) + a48: 00248713 addi a4,s1,2 + a4c: 0ff77713 andi a4,a4,255 + a50: 9722 add a4,a4,s0 + a52: 02574583 lbu a1,37(a4) + a56: 07a2 slli a5,a5,0x8 + a58: 96a2 add a3,a3,s0 + a5a: 05c2 slli a1,a1,0x10 + a5c: 8fcd or a5,a5,a1 + a5e: 0256c583 lbu a1,37(a3) + a62: 8fd1 or a5,a5,a2 + a64: 0000b537 lui a0,0xb + a68: 05e2 slli a1,a1,0x18 + a6a: 0491 addi s1,s1,4 + a6c: 8ddd or a1,a1,a5 + a6e: 7fc50513 addi a0,a0,2044 # b7fc <_exit+0x3a4> + a72: 0ff4f493 andi s1,s1,255 + a76: 150090ef jal ra,9bc6 + a7a: 02444783 lbu a5,36(s0) + a7e: 04f4f263 bgeu s1,a5,ac2 + a82: 8f85 sub a5,a5,s1 + a84: 0ff7f793 andi a5,a5,255 + a88: 4741 li a4,16 + a8a: 0ff7f593 andi a1,a5,255 + a8e: 00f77363 bgeu a4,a5,a94 + a92: 45c1 li a1,16 + a94: 02548513 addi a0,s1,37 + a98: 9522 add a0,a0,s0 + a9a: 3d7d jal 958 + a9c: 0ff57993 andi s3,a0,255 + aa0: 0000c537 lui a0,0xc + aa4: 81450513 addi a0,a0,-2028 # b814 <_exit+0x3bc> + aa8: 9426 add s0,s0,s1 + aaa: 11c090ef jal ra,9bc6 + aae: 4481 li s1,0 + ab0: 0000ba37 lui s4,0xb + ab4: 0405 addi s0,s0,1 + ab6: 00999863 bne s3,s1,ac6 + aba: 99890513 addi a0,s2,-1640 + abe: 108090ef jal ra,9bc6 + ac2: f48ff06f j 20a <__riscv_restore_4> + ac6: 02444583 lbu a1,36(s0) + aca: 480a0513 addi a0,s4,1152 # b480 <_exit+0x28> + ace: 0485 addi s1,s1,1 + ad0: 0f6090ef jal ra,9bc6 + ad4: 0ff4f493 andi s1,s1,255 + ad8: bff1 j ab4 + ada: 8082 ret + +00000adc : + adc: efaff2ef jal t0,1d6 <__riscv_save_4> + ae0: 04c54783 lbu a5,76(a0) + ae4: 7165 addi sp,sp,-400 + ae6: 84aa mv s1,a0 + ae8: 04d50593 addi a1,a0,77 + aec: 02000613 li a2,32 + af0: 01910513 addi a0,sp,25 + af4: 00f10c23 sb a5,24(sp) + af8: 65b080ef jal ra,9952 + afc: 06e4c783 lbu a5,110(s1) + b00: 06d4c703 lbu a4,109(s1) + b04: 01914503 lbu a0,25(sp) + b08: 07a2 slli a5,a5,0x8 + b0a: 8fd9 or a5,a5,a4 + b0c: 02f11d23 sh a5,58(sp) + b10: 782060ef jal ra,7292 + b14: 0000b937 lui s2,0xb + b18: 0000ba37 lui s4,0xb + b1c: 1e051d63 bnez a0,d16 + b20: 730060ef jal ra,7250 + b24: 0b800613 li a2,184 + b28: 4581 li a1,0 + b2a: 842a mv s0,a0 + b2c: ef4ff0ef jal ra,220 + b30: 0000b5b7 lui a1,0xb + b34: 61858593 addi a1,a1,1560 # b618 <_exit+0x1c0> + b38: 8522 mv a0,s0 + b3a: 3fc090ef jal ra,9f36 + b3e: 02000613 li a2,32 + b42: 01910593 addi a1,sp,25 + b46: 06040423 sb zero,104(s0) + b4a: 02040513 addi a0,s0,32 + b4e: 605080ef jal ra,9952 + b52: 01910593 addi a1,sp,25 + b56: 09c8 addi a0,sp,212 + b58: 664050ef jal ra,61bc + b5c: 200005b7 lui a1,0x20000 + b60: 09d0 addi a2,sp,212 + b62: 39058593 addi a1,a1,912 # 20000390 + b66: 04040513 addi a0,s0,64 + b6a: 2d6050ef jal ra,5e40 + b6e: 06042023 sw zero,96(s0) + b72: 06042223 sw zero,100(s0) + b76: 0a040523 sb zero,170(s0) + b7a: 690080ef jal ra,920a + b7e: 0aa42823 sw a0,176(s0) + b82: 0000b537 lui a0,0xb + b86: 86a2 mv a3,s0 + b88: 62890613 addi a2,s2,1576 # b628 <_exit+0x1d0> + b8c: 4eca0593 addi a1,s4,1260 # b4ec <_exit+0x94> + b90: 63450513 addi a0,a0,1588 # b634 <_exit+0x1dc> + b94: 032090ef jal ra,9bc6 + b98: 44b4 lw a3,72(s1) + b9a: 03d10713 addi a4,sp,61 + b9e: 06d48613 addi a2,s1,109 + ba2: fdf68693 addi a3,a3,-33 + ba6: 02000593 li a1,32 + baa: 04040513 addi a0,s0,64 + bae: 4a9010ef jal ra,2856 + bb2: 44b0 lw a2,72(s1) + bb4: 0000b537 lui a0,0xb + bb8: 03d10593 addi a1,sp,61 + bbc: fdd60613 addi a2,a2,-35 + bc0: 0ff67613 andi a2,a2,255 + bc4: 69850513 addi a0,a0,1688 # b698 <_exit+0x240> + bc8: 02c10e23 sb a2,60(sp) + bcc: 817ff0ef jal ra,3e2 + bd0: 03e14703 lbu a4,62(sp) + bd4: 03d14783 lbu a5,61(sp) + bd8: 4991 li s3,4 + bda: 0722 slli a4,a4,0x8 + bdc: 8f5d or a4,a4,a5 + bde: 03f14783 lbu a5,63(sp) + be2: 07c2 slli a5,a5,0x10 + be4: 8f5d or a4,a4,a5 + be6: 04014783 lbu a5,64(sp) + bea: 07e2 slli a5,a5,0x18 + bec: 8fd9 or a5,a5,a4 + bee: 0af42623 sw a5,172(s0) + bf2: 200007b7 lui a5,0x20000 + bf6: 3d07c583 lbu a1,976(a5) # 200003d0 + bfa: 478d li a5,3 + bfc: 02f59363 bne a1,a5,c22 + c00: 04214703 lbu a4,66(sp) + c04: 04114783 lbu a5,65(sp) + c08: 49a1 li s3,8 + c0a: 0722 slli a4,a4,0x8 + c0c: 8f5d or a4,a4,a5 + c0e: 04314783 lbu a5,67(sp) + c12: 07c2 slli a5,a5,0x10 + c14: 8f5d or a4,a4,a5 + c16: 04414783 lbu a5,68(sp) + c1a: 07e2 slli a5,a5,0x18 + c1c: 8fd9 or a5,a5,a4 + c1e: 0af42a23 sw a5,180(s0) + c22: 15f5 addi a1,a1,-3 + c24: 0015b593 seqz a1,a1 + c28: 0828 addi a0,sp,24 + c2a: 3399 jal 970 + c2c: 03c14783 lbu a5,60(sp) + c30: 0838 addi a4,sp,24 + c32: 413787b3 sub a5,a5,s3 + c36: 02598993 addi s3,s3,37 + c3a: 0ff7f793 andi a5,a5,255 + c3e: 99ba add s3,s3,a4 + c40: 4741 li a4,16 + c42: 0ff7f593 andi a1,a5,255 + c46: 00f77363 bgeu a4,a5,c4c + c4a: 45c1 li a1,16 + c4c: 854e mv a0,s3 + c4e: 3329 jal 958 + c50: 0ff57a93 andi s5,a0,255 + c54: 0000b537 lui a0,0xb + c58: 86d6 mv a3,s5 + c5a: 62890613 addi a2,s2,1576 + c5e: 4eca0593 addi a1,s4,1260 + c62: 6a850513 addi a0,a0,1704 # b6a8 <_exit+0x250> + c66: 761080ef jal ra,9bc6 + c6a: 8656 mv a2,s5 + c6c: 85ce mv a1,s3 + c6e: 0028 addi a0,sp,8 + c70: 4e3080ef jal ra,9952 + c74: 8656 mv a2,s5 + c76: 76018593 addi a1,gp,1888 # 20001150 <__global_pointer$+0x760> + c7a: 0028 addi a0,sp,8 + c7c: 4b3080ef jal ra,992e + c80: e94d bnez a0,d32 + c82: 4785 li a5,1 + c84: 0000b537 lui a0,0xb + c88: 86a2 mv a3,s0 + c8a: 62890613 addi a2,s2,1576 + c8e: 4eca0593 addi a1,s4,1260 + c92: 0af405a3 sb a5,171(s0) + c96: 6c850513 addi a0,a0,1736 # b6c8 <_exit+0x270> + c9a: 72d080ef jal ra,9bc6 + c9e: 0000b537 lui a0,0xb + ca2: 86a2 mv a3,s0 + ca4: 62890613 addi a2,s2,1576 + ca8: 4eca0593 addi a1,s4,1260 + cac: 6fc50513 addi a0,a0,1788 # b6fc <_exit+0x2a4> + cb0: 717080ef jal ra,9bc6 + cb4: 556080ef jal ra,920a + cb8: cbaa sw a0,212(sp) + cba: 05e090ef jal ra,9d18 + cbe: 0c010ca3 sb zero,217(sp) + cc2: 0c010d23 sb zero,218(sp) + cc6: 0ab44783 lbu a5,171(s0) + cca: 0cf10da3 sb a5,219(sp) + cce: c391 beqz a5,cd2 + cd0: 478d li a5,3 + cd2: 0cf10e23 sb a5,220(sp) + cd6: 00855793 srli a5,a0,0x8 + cda: 0cf10f23 sb a5,222(sp) + cde: 01055793 srli a5,a0,0x10 + ce2: 0cf10fa3 sb a5,223(sp) + ce6: 4785 li a5,1 + ce8: 0ef100a3 sb a5,225(sp) + cec: 47a5 li a5,9 + cee: 0cf10c23 sb a5,216(sp) + cf2: 209c lbu a5,0(s1) + cf4: 0ca10ea3 sb a0,221(sp) + cf8: 8161 srli a0,a0,0x18 + cfa: 0ea10023 sb a0,224(sp) + cfe: 8b89 andi a5,a5,2 + d00: e789 bnez a5,d0a + d02: 00548593 addi a1,s1,5 + d06: 8522 mv a0,s0 + d08: 2365 jal 12b0 + d0a: 09cc addi a1,sp,212 + d0c: 8522 mv a0,s0 + d0e: 2915 jal 1142 + d10: 6159 addi sp,sp,400 + d12: cf8ff06f j 20a <__riscv_restore_4> + d16: 842a mv s0,a0 + d18: 0000b5b7 lui a1,0xb + d1c: 0000b537 lui a0,0xb + d20: 01914683 lbu a3,25(sp) + d24: 62890613 addi a2,s2,1576 + d28: 66058593 addi a1,a1,1632 # b660 <_exit+0x208> + d2c: 66450513 addi a0,a0,1636 # b664 <_exit+0x20c> + d30: b595 j b94 + d32: 0000b5b7 lui a1,0xb + d36: 0000b537 lui a0,0xb + d3a: 86a2 mv a3,s0 + d3c: 62890613 addi a2,s2,1576 + d40: 49458593 addi a1,a1,1172 # b494 <_exit+0x3c> + d44: 72850513 addi a0,a0,1832 # b728 <_exit+0x2d0> + d48: b7a5 j cb0 + +00000d4a : + d4a: ca6ff2ef jal t0,1f0 <__riscv_save_0> + d4e: 716d addi sp,sp,-272 + d50: 02e00793 li a5,46 + d54: 865c sb a5,12(sp) + d56: 211c lbu a5,0(a0) + d58: 215a lhu a4,4(a0) + d5a: 02854403 lbu s0,40(a0) + d5e: 8bbd andi a5,a5,15 + d60: f907e793 ori a5,a5,-112 + d64: 04f10c23 sb a5,88(sp) + d68: 311c lbu a5,1(a0) + d6a: 04e11d23 sh a4,90(sp) + d6e: 000108a3 sb zero,17(sp) + d72: 04f10ca3 sb a5,89(sp) + d76: 415c lw a5,4(a0) + d78: 0107d713 srli a4,a5,0x10 + d7c: 83e1 srli a5,a5,0x18 + d7e: 04f10ea3 sb a5,93(sp) + d82: 04e10e23 sb a4,92(sp) + d86: 4799 li a5,6 + d88: c819 beqz s0,d9e + d8a: 8622 mv a2,s0 + d8c: 00850593 addi a1,a0,8 + d90: 05e10513 addi a0,sp,94 + d94: 3bf080ef jal ra,9952 + d98: 0419 addi s0,s0,6 + d9a: 0ff47793 andi a5,s0,255 + d9e: 0068 addi a0,sp,12 + da0: cabe sw a5,84(sp) + da2: 6f8010ef jal ra,249a + da6: 6151 addi sp,sp,272 + da8: c6cff06f j 214 <__riscv_restore_0> + +00000dac : + dac: c44ff2ef jal t0,1f0 <__riscv_save_0> + db0: 842a mv s0,a0 + db2: 0000c537 lui a0,0xc + db6: 86450513 addi a0,a0,-1948 # b864 <_exit+0x40c> + dba: 60d080ef jal ra,9bc6 + dbe: 200c lbu a1,0(s0) + dc0: 0000c537 lui a0,0xc + dc4: 88050513 addi a0,a0,-1920 # b880 <_exit+0x428> + dc8: 5ff080ef jal ra,9bc6 + dcc: 300c lbu a1,1(s0) + dce: 0000c537 lui a0,0xc + dd2: 89450513 addi a0,a0,-1900 # b894 <_exit+0x43c> + dd6: 5f1080ef jal ra,9bc6 + dda: 404c lw a1,4(s0) + ddc: 0000c537 lui a0,0xc + de0: 8ac50513 addi a0,a0,-1876 # b8ac <_exit+0x454> + de4: 5e3080ef jal ra,9bc6 + de8: 440c lw a1,8(s0) + dea: 0000c537 lui a0,0xc + dee: 8c450513 addi a0,a0,-1852 # b8c4 <_exit+0x46c> + df2: 5d5080ef jal ra,9bc6 + df6: c1eff06f j 214 <__riscv_restore_0> + +00000dfa : + dfa: bf6ff2ef jal t0,1f0 <__riscv_save_0> + dfe: 842a mv s0,a0 + e00: 0000c537 lui a0,0xc + e04: 8dc50513 addi a0,a0,-1828 # b8dc <_exit+0x484> + e08: 5bf080ef jal ra,9bc6 + e0c: 200c lbu a1,0(s0) + e0e: 0000c537 lui a0,0xc + e12: 8f850513 addi a0,a0,-1800 # b8f8 <_exit+0x4a0> + e16: 5b1080ef jal ra,9bc6 + e1a: 00140583 lb a1,1(s0) + e1e: 0000c537 lui a0,0xc + e22: 90850513 addi a0,a0,-1784 # b908 <_exit+0x4b0> + e26: 5a1080ef jal ra,9bc6 + e2a: 404c lw a1,4(s0) + e2c: 0000c537 lui a0,0xc + e30: 91850513 addi a0,a0,-1768 # b918 <_exit+0x4c0> + e34: 593080ef jal ra,9bc6 + e38: 02844603 lbu a2,40(s0) + e3c: 0000c537 lui a0,0xc + e40: 00840593 addi a1,s0,8 + e44: 92c50513 addi a0,a0,-1748 # b92c <_exit+0x4d4> + e48: d9aff0ef jal ra,3e2 + e4c: 0000e537 lui a0,0xe + e50: 99850513 addi a0,a0,-1640 # d998 + e54: 573080ef jal ra,9bc6 + e58: bbcff06f j 214 <__riscv_restore_0> + +00000e5c : + e5c: b94ff2ef jal t0,1f0 <__riscv_save_0> + e60: 04c54783 lbu a5,76(a0) + e64: 08000693 li a3,128 + e68: 715d addi sp,sp,-80 + e6a: 0f07f713 andi a4,a5,240 + e6e: 0ad71263 bne a4,a3,f12 + e72: 8b85 andi a5,a5,1 + e74: 00f10c23 sb a5,24(sp) + e78: 04d54783 lbu a5,77(a0) + e7c: 04e55703 lhu a4,78(a0) + e80: 00f10ca3 sb a5,25(sp) + e84: 05055783 lhu a5,80(a0) + e88: 07c2 slli a5,a5,0x10 + e8a: 8fd9 or a5,a5,a4 + e8c: 4538 lw a4,72(a0) + e8e: ce3e sw a5,28(sp) + e90: 4799 li a5,6 + e92: 00e7f963 bgeu a5,a4,ea4 + e96: 05455783 lhu a5,84(a0) + e9a: 05255703 lhu a4,82(a0) + e9e: 07c2 slli a5,a5,0x10 + ea0: 8fd9 or a5,a5,a4 + ea2: d03e sw a5,32(sp) + ea4: 0828 addi a0,sp,24 + ea6: 3719 jal dac + ea8: 200005b7 lui a1,0x20000 + eac: 38c58593 addi a1,a1,908 # 2000038c + eb0: 01914783 lbu a5,25(sp) + eb4: 0445c703 lbu a4,68(a1) + eb8: 8385 srli a5,a5,0x1 + eba: 8ff9 and a5,a5,a4 + ebc: cba1 beqz a5,f0c + ebe: 46f2 lw a3,28(sp) + ec0: 02000793 li a5,32 + ec4: 02000613 li a2,32 + ec8: 02458593 addi a1,a1,36 + ecc: 1068 addi a0,sp,44 + ece: d436 sw a3,40(sp) + ed0: c636 sw a3,12(sp) + ed2: 02e10223 sb a4,36(sp) + ed6: 04f10623 sb a5,76(sp) + eda: 279080ef jal ra,9952 + ede: 9761d783 lhu a5,-1674(gp) # 20000366 + ee2: 46b2 lw a3,12(sp) + ee4: 0000c637 lui a2,0xc + ee8: 0000b5b7 lui a1,0xb + eec: 0000c537 lui a0,0xc + ef0: 82460613 addi a2,a2,-2012 # b824 <_exit+0x3cc> + ef4: 66058593 addi a1,a1,1632 # b660 <_exit+0x208> + ef8: 82c50513 addi a0,a0,-2004 # b82c <_exit+0x3d4> + efc: 02f102a3 sb a5,37(sp) + f00: 4c7080ef jal ra,9bc6 + f04: 1048 addi a0,sp,36 + f06: 3591 jal d4a + f08: 1048 addi a0,sp,36 + f0a: 3dc5 jal dfa + f0c: 6161 addi sp,sp,80 + f0e: b06ff06f j 214 <__riscv_restore_0> + f12: 09000693 li a3,144 + f16: fed71be3 bne a4,a3,f0c + f1a: 8bbd andi a5,a5,15 + f1c: 02f10223 sb a5,36(sp) + f20: 04d54783 lbu a5,77(a0) + f24: 04e55703 lhu a4,78(a0) + f28: 02000613 li a2,32 + f2c: 02f102a3 sb a5,37(sp) + f30: 05055783 lhu a5,80(a0) + f34: 07c2 slli a5,a5,0x10 + f36: 8fd9 or a5,a5,a4 + f38: d43e sw a5,40(sp) + f3a: 453c lw a5,72(a0) + f3c: 4721 li a4,8 + f3e: 17e9 addi a5,a5,-6 + f40: 0ff7f793 andi a5,a5,255 + f44: 00f76363 bltu a4,a5,f4a + f48: 4621 li a2,8 + f4a: 05250593 addi a1,a0,82 + f4e: 1068 addi a0,sp,44 + f50: 04c10623 sb a2,76(sp) + f54: 1ff080ef jal ra,9952 + f58: bf45 j f08 + +00000f5a : + f5a: 00050703 lb a4,0(a0) + f5e: 02d00793 li a5,45 + f62: 4805 li a6,1 + f64: 00f71463 bne a4,a5,f6c + f68: 0505 addi a0,a0,1 + f6a: 587d li a6,-1 + f6c: 4781 li a5,0 + f6e: 4625 li a2,9 + f70: 48a9 li a7,10 + f72: a029 j f7c + f74: 031787b3 mul a5,a5,a7 + f78: 0505 addi a0,a0,1 + f7a: 97b6 add a5,a5,a3 + f7c: 00050703 lb a4,0(a0) + f80: fd070693 addi a3,a4,-48 + f84: 0ff6f593 andi a1,a3,255 + f88: feb676e3 bgeu a2,a1,f74 + f8c: 02e00693 li a3,46 + f90: 04d71463 bne a4,a3,fd8 + f94: 00150613 addi a2,a0,1 + f98: 4685 li a3,1 + f9a: 051d addi a0,a0,7 + f9c: 4701 li a4,0 + f9e: 4325 li t1,9 + fa0: 48a9 li a7,10 + fa2: 00060583 lb a1,0(a2) + fa6: fd058593 addi a1,a1,-48 + faa: 0ff5fe13 andi t3,a1,255 + fae: 03c37863 bgeu t1,t3,fde + fb2: 000f4637 lui a2,0xf4 + fb6: 23f60613 addi a2,a2,575 # f423f <_data_lma+0xe5fe3> + fba: 45a9 li a1,10 + fbc: 02d64363 blt a2,a3,fe2 + fc0: 02b70733 mul a4,a4,a1 + fc4: 02b686b3 mul a3,a3,a1 + fc8: bfd5 j fbc + fca: 03170733 mul a4,a4,a7 + fce: 0605 addi a2,a2,1 + fd0: 972e add a4,a4,a1 + fd2: 031686b3 mul a3,a3,a7 + fd6: b7f1 j fa2 + fd8: 4685 li a3,1 + fda: 4701 li a4,0 + fdc: bfd9 j fb2 + fde: fea616e3 bne a2,a0,fca + fe2: 000f46b7 lui a3,0xf4 + fe6: 24068693 addi a3,a3,576 # f4240 <_data_lma+0xe5fe4> + fea: 02d787b3 mul a5,a5,a3 + fee: 97ba add a5,a5,a4 + ff0: 03078533 mul a0,a5,a6 + ff4: 8082 ret + +00000ff6 : + ff6: 9e0ff2ef jal t0,1d6 <__riscv_save_4> + ffa: 716d addi sp,sp,-272 + ffc: 84aa mv s1,a0 + ffe: 89ae mv s3,a1 + 1000: 8932 mv s2,a2 + 1002: 4581 li a1,0 + 1004: 10400613 li a2,260 + 1008: 0068 addi a0,sp,12 + 100a: 8436 mv s0,a3 + 100c: a14ff0ef jal ra,220 + 1010: 0204c783 lbu a5,32(s1) + 1014: 0684c583 lbu a1,104(s1) + 1018: 05a10713 addi a4,sp,90 + 101c: 04f10c23 sb a5,88(sp) + 1020: 200007b7 lui a5,0x20000 + 1024: 3b07c783 lbu a5,944(a5) # 200003b0 + 1028: 00b035b3 snez a1,a1 + 102c: 0585 addi a1,a1,1 + 102e: 0135e5b3 or a1,a1,s3 + 1032: 864c sb a1,12(sp) + 1034: 04f10ca3 sb a5,89(sp) + 1038: 86a2 mv a3,s0 + 103a: 003c addi a5,sp,8 + 103c: 864a mv a2,s2 + 103e: 02000593 li a1,32 + 1042: 04048513 addi a0,s1,64 + 1046: 776010ef jal ra,27bc + 104a: 4722 lw a4,8(sp) + 104c: 0000c9b7 lui s3,0xc + 1050: 0000b937 lui s2,0xb + 1054: 0000c537 lui a0,0xc + 1058: 86a2 mv a3,s0 + 105a: f8498613 addi a2,s3,-124 # bf84 <_exit+0xb2c> + 105e: 66090593 addi a1,s2,1632 # b660 <_exit+0x208> + 1062: f9850513 addi a0,a0,-104 # bf98 <_exit+0xb40> + 1066: 361080ef jal ra,9bc6 + 106a: 4422 lw s0,8(sp) + 106c: 06848593 addi a1,s1,104 + 1070: 04100613 li a2,65 + 1074: 0409 addi s0,s0,2 + 1076: 01110513 addi a0,sp,17 + 107a: caa2 sw s0,84(sp) + 107c: 0d7080ef jal ra,9952 + 1080: 0000c537 lui a0,0xc + 1084: 8622 mv a2,s0 + 1086: 08ac addi a1,sp,88 + 1088: fc050513 addi a0,a0,-64 # bfc0 <_exit+0xb68> + 108c: b56ff0ef jal ra,3e2 + 1090: 0068 addi a0,sp,12 + 1092: 408010ef jal ra,249a + 1096: 0000c537 lui a0,0xc + 109a: f8498613 addi a2,s3,-124 + 109e: 66090593 addi a1,s2,1632 + 10a2: fd050513 addi a0,a0,-48 # bfd0 <_exit+0xb78> + 10a6: 321080ef jal ra,9bc6 + 10aa: 6151 addi sp,sp,272 + 10ac: 95eff06f j 20a <__riscv_restore_4> + +000010b0 : + 10b0: 940ff2ef jal t0,1f0 <__riscv_save_0> + 10b4: 716d addi sp,sp,-272 + 10b6: e115 bnez a0,10da + 10b8: 0000c637 lui a2,0xc + 10bc: 0000b5b7 lui a1,0xb + 10c0: 0000c537 lui a0,0xc + 10c4: f8460613 addi a2,a2,-124 # bf84 <_exit+0xb2c> + 10c8: 49458593 addi a1,a1,1172 # b494 <_exit+0x3c> + 10cc: ff850513 addi a0,a0,-8 # bff8 <_exit+0xba0> + 10d0: 2f7080ef jal ra,9bc6 + 10d4: 6151 addi sp,sp,272 + 10d6: 93eff06f j 214 <__riscv_restore_0> + 10da: 0b052783 lw a5,176(a0) + 10de: 892a mv s2,a0 + 10e0: ef91 bnez a5,10fc + 10e2: 0000c637 lui a2,0xc + 10e6: 0000b5b7 lui a1,0xb + 10ea: 0000c537 lui a0,0xc + 10ee: f8460613 addi a2,a2,-124 # bf84 <_exit+0xb2c> + 10f2: 49458593 addi a1,a1,1172 # b494 <_exit+0x3c> + 10f6: 01050513 addi a0,a0,16 # c010 <_exit+0xbb8> + 10fa: bfd9 j 10d0 + 10fc: 84ae mv s1,a1 + 10fe: 0599 addi a1,a1,6 + 1100: 852e mv a0,a1 + 1102: c62e sw a1,12(sp) + 1104: 643080ef jal ra,9f46 + 1108: 409c lw a5,0(s1) + 110a: 30d8 lbu a4,5(s1) + 110c: 0ff57413 andi s0,a0,255 + 1110: c83e sw a5,16(sp) + 1112: 20dc lbu a5,4(s1) + 1114: 45b2 lw a1,12(sp) + 1116: 8b0d andi a4,a4,3 + 1118: 00140613 addi a2,s0,1 + 111c: 078a slli a5,a5,0x2 + 111e: 8fd9 or a5,a5,a4 + 1120: 0ff67613 andi a2,a2,255 + 1124: 01510513 addi a0,sp,21 + 1128: 00f10a23 sb a5,20(sp) + 112c: 027080ef jal ra,9952 + 1130: 00640693 addi a3,s0,6 + 1134: 0ff6f693 andi a3,a3,255 + 1138: 0810 addi a2,sp,16 + 113a: 45a1 li a1,8 + 113c: 854a mv a0,s2 + 113e: 3d65 jal ff6 + 1140: bf51 j 10d4 + +00001142 : + 1142: 8aeff2ef jal t0,1f0 <__riscv_save_0> + 1146: 21c0 lbu s0,4(a1) + 1148: 419c lw a5,0(a1) + 114a: 7111 addi sp,sp,-256 + 114c: 84aa mv s1,a0 + 114e: 8622 mv a2,s0 + 1150: 0595 addi a1,a1,5 + 1152: 0048 addi a0,sp,4 + 1154: c03e sw a5,0(sp) + 1156: 7fc080ef jal ra,9952 + 115a: 00440693 addi a3,s0,4 + 115e: 860a mv a2,sp + 1160: 0ff6f693 andi a3,a3,255 + 1164: 4591 li a1,4 + 1166: 8526 mv a0,s1 + 1168: 3579 jal ff6 + 116a: 6111 addi sp,sp,256 + 116c: 8a8ff06f j 214 <__riscv_restore_0> + +00001170 : + 1170: 866ff2ef jal t0,1d6 <__riscv_save_4> + 1174: 2180 lbu s0,0(a1) + 1176: 7111 addi sp,sp,-256 + 1178: 89ae mv s3,a1 + 117a: 8622 mv a2,s0 + 117c: 892a mv s2,a0 + 117e: 0585 addi a1,a1,1 + 1180: 00110513 addi a0,sp,1 + 1184: 8040 sb s0,0(sp) + 1186: 7cc080ef jal ra,9952 + 118a: 0429c603 lbu a2,66(s3) + 118e: 00140793 addi a5,s0,1 + 1192: 0ff7f793 andi a5,a5,255 + 1196: 00240493 addi s1,s0,2 + 119a: 0218 addi a4,sp,256 + 119c: 0ff4f493 andi s1,s1,255 + 11a0: 97ba add a5,a5,a4 + 11a2: c605 beqz a2,11ca + 11a4: 0419c703 lbu a4,65(s3) + 11a8: 04398593 addi a1,s3,67 + 11ac: 00910533 add a0,sp,s1 + 11b0: f0e78023 sb a4,-256(a5) + 11b4: 79e080ef jal ra,9952 + 11b8: 860a mv a2,sp + 11ba: 86a6 mv a3,s1 + 11bc: 02000593 li a1,32 + 11c0: 854a mv a0,s2 + 11c2: 3d15 jal ff6 + 11c4: 6111 addi sp,sp,256 + 11c6: 844ff06f j 20a <__riscv_restore_4> + 11ca: 577d li a4,-1 + 11cc: f0e78023 sb a4,-256(a5) + 11d0: 03a080ef jal ra,920a + 11d4: 021c addi a5,sp,256 + 11d6: 94be add s1,s1,a5 + 11d8: 00340793 addi a5,s0,3 + 11dc: 0218 addi a4,sp,256 + 11de: 0ff7f793 andi a5,a5,255 + 11e2: f0a48023 sb a0,-256(s1) + 11e6: 97ba add a5,a5,a4 + 11e8: 00855713 srli a4,a0,0x8 + 11ec: f0e78023 sb a4,-256(a5) + 11f0: 00440793 addi a5,s0,4 + 11f4: 0218 addi a4,sp,256 + 11f6: 0ff7f793 andi a5,a5,255 + 11fa: 97ba add a5,a5,a4 + 11fc: 00640493 addi s1,s0,6 + 1200: 01055713 srli a4,a0,0x10 + 1204: 0415 addi s0,s0,5 + 1206: f0e78023 sb a4,-256(a5) + 120a: 0ff47413 andi s0,s0,255 + 120e: 021c addi a5,sp,256 + 1210: 943e add s0,s0,a5 + 1212: 8161 srli a0,a0,0x18 + 1214: 0ff4f493 andi s1,s1,255 + 1218: f0a40023 sb a0,-256(s0) + 121c: bf71 j 11b8 + +0000121e : + 121e: fd3fe2ef jal t0,1f0 <__riscv_save_0> + 1222: 842a mv s0,a0 + 1224: 0000c537 lui a0,0xc + 1228: bb050513 addi a0,a0,-1104 # bbb0 <_exit+0x758> + 122c: 19b080ef jal ra,9bc6 + 1230: 400c lw a1,0(s0) + 1232: 0000c537 lui a0,0xc + 1236: bbc50513 addi a0,a0,-1092 # bbbc <_exit+0x764> + 123a: 18d080ef jal ra,9bc6 + 123e: 204c lbu a1,4(s0) + 1240: 0000c537 lui a0,0xc + 1244: bd050513 addi a0,a0,-1072 # bbd0 <_exit+0x778> + 1248: 17f080ef jal ra,9bc6 + 124c: 0000c537 lui a0,0xc + 1250: be050513 addi a0,a0,-1056 # bbe0 <_exit+0x788> + 1254: 173080ef jal ra,9bc6 + 1258: 3050 lbu a2,5(s0) + 125a: 0000c537 lui a0,0xc + 125e: 00640593 addi a1,s0,6 + 1262: bec50513 addi a0,a0,-1044 # bbec <_exit+0x794> + 1266: 97cff0ef jal ra,3e2 + 126a: fabfe06f j 214 <__riscv_restore_0> + +0000126e : + 126e: f83fe2ef jal t0,1f0 <__riscv_save_0> + 1272: 842a mv s0,a0 + 1274: 0000c537 lui a0,0xc + 1278: bf450513 addi a0,a0,-1036 # bbf4 <_exit+0x79c> + 127c: 14b080ef jal ra,9bc6 + 1280: 400c lw a1,0(s0) + 1282: 0000c537 lui a0,0xc + 1286: c0050513 addi a0,a0,-1024 # bc00 <_exit+0x7a8> + 128a: 13d080ef jal ra,9bc6 + 128e: 0000c537 lui a0,0xc + 1292: be050513 addi a0,a0,-1056 # bbe0 <_exit+0x788> + 1296: 131080ef jal ra,9bc6 + 129a: 2050 lbu a2,4(s0) + 129c: 0000c537 lui a0,0xc + 12a0: 00540593 addi a1,s0,5 + 12a4: bec50513 addi a0,a0,-1044 # bbec <_exit+0x794> + 12a8: 93aff0ef jal ra,3e2 + 12ac: f69fe06f j 214 <__riscv_restore_0> + +000012b0 : + 12b0: f41fe2ef jal t0,1f0 <__riscv_save_0> + 12b4: 2190 lbu a2,0(a1) + 12b6: 7111 addi sp,sp,-256 + 12b8: 842a mv s0,a0 + 12ba: 57fd li a5,-1 + 12bc: 0585 addi a1,a1,1 + 12be: 00910513 addi a0,sp,9 + 12c2: 04f104a3 sb a5,73(sp) + 12c6: 8450 sb a2,8(sp) + 12c8: 04010523 sb zero,74(sp) + 12cc: 686080ef jal ra,9952 + 12d0: 002c addi a1,sp,8 + 12d2: 8522 mv a0,s0 + 12d4: 3d71 jal 1170 + 12d6: 6111 addi sp,sp,256 + 12d8: f3dfe06f j 214 <__riscv_restore_0> + +000012dc : + 12dc: efbfe2ef jal t0,1d6 <__riscv_save_4> + 12e0: 7131 addi sp,sp,-192 + 12e2: 842a mv s0,a0 + 12e4: 892e mv s2,a1 + 12e6: 725070ef jal ra,920a + 12ea: 4785 li a5,1 + 12ec: 847c sh a5,8(sp) + 12ee: c22a sw a0,4(sp) + 12f0: 00010523 sb zero,10(sp) + 12f4: 02000793 li a5,32 + 12f8: 00040703 lb a4,0(s0) + 12fc: 04f70d63 beq a4,a5,1356 + 1300: 8522 mv a0,s0 + 1302: 445080ef jal ra,9f46 + 1306: 4791 li a5,4 + 1308: 00a10493 addi s1,sp,10 + 130c: 02a7f063 bgeu a5,a0,132c + 1310: 00240703 lb a4,2(s0) + 1314: 07c00793 li a5,124 + 1318: 00f71a63 bne a4,a5,132c + 131c: 85a2 mv a1,s0 + 131e: 8526 mv a0,s1 + 1320: 460d li a2,3 + 1322: 630080ef jal ra,9952 + 1326: 040d addi s0,s0,3 + 1328: 00d10493 addi s1,sp,13 + 132c: 0000c5b7 lui a1,0xc + 1330: c4458593 addi a1,a1,-956 # bc44 <_exit+0x7ec> + 1334: 8522 mv a0,s0 + 1336: f93fe0ef jal ra,2c8 + 133a: e105 bnez a0,135a + 133c: beef07b7 lui a5,0xbeef0 + 1340: e000e737 lui a4,0xe000e + 1344: 08078793 addi a5,a5,128 # beef0080 <_eusrstack+0x9eee8080> + 1348: c73c sw a5,72(a4) + 134a: 004c addi a1,sp,4 + 134c: 854a mv a0,s2 + 134e: 338d jal 10b0 + 1350: 6129 addi sp,sp,192 + 1352: eb9fe06f j 20a <__riscv_restore_4> + 1356: 0405 addi s0,s0,1 + 1358: b745 j 12f8 + 135a: 0000c5b7 lui a1,0xc + 135e: c4c58593 addi a1,a1,-948 # bc4c <_exit+0x7f4> + 1362: 8522 mv a0,s0 + 1364: f65fe0ef jal ra,2c8 + 1368: ed01 bnez a0,1380 + 136a: 4505 li a0,1 + 136c: a62ff0ef jal ra,5ce + 1370: 0000c5b7 lui a1,0xc + 1374: c5458593 addi a1,a1,-940 # bc54 <_exit+0x7fc> + 1378: 8526 mv a0,s1 + 137a: 3bd080ef jal ra,9f36 + 137e: b7f1 j 134a + 1380: 0000c5b7 lui a1,0xc + 1384: c6858593 addi a1,a1,-920 # bc68 <_exit+0x810> + 1388: 8522 mv a0,s0 + 138a: f3ffe0ef jal ra,2c8 + 138e: ed09 bnez a0,13a8 + 1390: 4581 li a1,0 + 1392: 03400613 li a2,52 + 1396: 94c18513 addi a0,gp,-1716 # 2000033c + 139a: e87fe0ef jal ra,220 + 139e: 0000c5b7 lui a1,0xc + 13a2: c7458593 addi a1,a1,-908 # bc74 <_exit+0x81c> + 13a6: bfc9 j 1378 + 13a8: 0000e5b7 lui a1,0xe + 13ac: 96858593 addi a1,a1,-1688 # d968 + 13b0: 8522 mv a0,s0 + 13b2: f17fe0ef jal ra,2c8 + 13b6: e10d bnez a0,13d8 + 13b8: 0000c6b7 lui a3,0xc + 13bc: 0000c637 lui a2,0xc + 13c0: 0000c5b7 lui a1,0xc + 13c4: c8868693 addi a3,a3,-888 # bc88 <_exit+0x830> + 13c8: c9460613 addi a2,a2,-876 # bc94 <_exit+0x83c> + 13cc: cb058593 addi a1,a1,-848 # bcb0 <_exit+0x858> + 13d0: 8526 mv a0,s1 + 13d2: 301080ef jal ra,9ed2 + 13d6: bf95 j 134a + 13d8: 0000c5b7 lui a1,0xc + 13dc: cc058593 addi a1,a1,-832 # bcc0 <_exit+0x868> + 13e0: 8522 mv a0,s0 + 13e2: ee7fe0ef jal ra,2c8 + 13e6: e511 bnez a0,13f2 + 13e8: 0000c5b7 lui a1,0xc + 13ec: cc858593 addi a1,a1,-824 # bcc8 <_exit+0x870> + 13f0: b761 j 1378 + 13f2: 0000c5b7 lui a1,0xc + 13f6: cd858593 addi a1,a1,-808 # bcd8 <_exit+0x880> + 13fa: 8522 mv a0,s0 + 13fc: ecdfe0ef jal ra,2c8 + 1400: e515 bnez a0,142c + 1402: 670010ef jal ra,2a72 + 1406: 9801c603 lbu a2,-1664(gp) # 20000370 + 140a: 98018593 addi a1,gp,-1664 # 20000370 + 140e: 3194 lbu a3,1(a1) + 1410: 21b8 lbu a4,2(a1) + 1412: 31fc lbu a5,7(a1) + 1414: 0065c803 lbu a6,6(a1) + 1418: 0045d883 lhu a7,4(a1) + 141c: 0000c5b7 lui a1,0xc + 1420: cf858593 addi a1,a1,-776 # bcf8 <_exit+0x8a0> + 1424: 8526 mv a0,s1 + 1426: 2ad080ef jal ra,9ed2 + 142a: b705 j 134a + 142c: 0000c5b7 lui a1,0xc + 1430: ce058593 addi a1,a1,-800 # bce0 <_exit+0x888> + 1434: 8522 mv a0,s0 + 1436: e93fe0ef jal ra,2c8 + 143a: e521 bnez a0,1482 + 143c: 00540513 addi a0,s0,5 + 1440: 48c080ef jal ra,98cc + 1444: 842a mv s0,a0 + 1446: 5c5070ef jal ra,920a + 144a: 02857763 bgeu a0,s0,1478 + 144e: 8522 mv a0,s0 + 1450: 615070ef jal ra,9264 + 1454: 61e010ef jal ra,2a72 + 1458: 9801c603 lbu a2,-1664(gp) # 20000370 + 145c: 98018593 addi a1,gp,-1664 # 20000370 + 1460: 3194 lbu a3,1(a1) + 1462: 21b8 lbu a4,2(a1) + 1464: 31fc lbu a5,7(a1) + 1466: 0065c803 lbu a6,6(a1) + 146a: 0045d883 lhu a7,4(a1) + 146e: 0000c5b7 lui a1,0xc + 1472: ce858593 addi a1,a1,-792 # bce8 <_exit+0x890> + 1476: b77d j 1424 + 1478: 0000c5b7 lui a1,0xc + 147c: d1858593 addi a1,a1,-744 # bd18 <_exit+0x8c0> + 1480: bde5 j 1378 + 1482: 0000c5b7 lui a1,0xc + 1486: d3c58593 addi a1,a1,-708 # bd3c <_exit+0x8e4> + 148a: 8522 mv a0,s0 + 148c: e3dfe0ef jal ra,2c8 + 1490: ed11 bnez a0,14ac + 1492: 579070ef jal ra,920a + 1496: 4792 lw a5,4(sp) + 1498: 00f57563 bgeu a0,a5,14a2 + 149c: 00178513 addi a0,a5,1 + 14a0: bf45 j 1450 + 14a2: 0000c5b7 lui a1,0xc + 14a6: d4858593 addi a1,a1,-696 # bd48 <_exit+0x8f0> + 14aa: b5f9 j 1378 + 14ac: 0000c5b7 lui a1,0xc + 14b0: d6858593 addi a1,a1,-664 # bd68 <_exit+0x910> + 14b4: 8522 mv a0,s0 + 14b6: e13fe0ef jal ra,2c8 + 14ba: e115 bnez a0,14de + 14bc: 00940593 addi a1,s0,9 + 14c0: 4641 li a2,16 + 14c2: 76018513 addi a0,gp,1888 # 20001150 <__global_pointer$+0x760> + 14c6: 293080ef jal ra,9f58 + 14ca: 0000c5b7 lui a1,0xc + 14ce: 76018613 addi a2,gp,1888 # 20001150 <__global_pointer$+0x760> + 14d2: d7458593 addi a1,a1,-652 # bd74 <_exit+0x91c> + 14d6: 8526 mv a0,s1 + 14d8: 1fb080ef jal ra,9ed2 + 14dc: b5bd j 134a + 14de: 0000c5b7 lui a1,0xc + 14e2: d8858593 addi a1,a1,-632 # bd88 <_exit+0x930> + 14e6: 8522 mv a0,s0 + 14e8: de1fe0ef jal ra,2c8 + 14ec: 14051963 bnez a0,163e + 14f0: 0411 addi s0,s0,4 + 14f2: 0000c5b7 lui a1,0xc + 14f6: 4639 li a2,14 + 14f8: d9058593 addi a1,a1,-624 # bd90 <_exit+0x938> + 14fc: 8522 mv a0,s0 + 14fe: 430080ef jal ra,992e + 1502: e901 bnez a0,1512 + 1504: 77018613 addi a2,gp,1904 # 20001160 <__global_pointer$+0x770> + 1508: 0000c5b7 lui a1,0xc + 150c: da058593 addi a1,a1,-608 # bda0 <_exit+0x948> + 1510: b7d9 j 14d6 + 1512: 0000c5b7 lui a1,0xc + 1516: 4611 li a2,4 + 1518: da858593 addi a1,a1,-600 # bda8 <_exit+0x950> + 151c: 8522 mv a0,s0 + 151e: 410080ef jal ra,992e + 1522: e511 bnez a0,152e + 1524: 20000637 lui a2,0x20000 + 1528: 3d160613 addi a2,a2,977 # 200003d1 + 152c: bff1 j 1508 + 152e: 0000c5b7 lui a1,0xc + 1532: 4619 li a2,6 + 1534: db058593 addi a1,a1,-592 # bdb0 <_exit+0x958> + 1538: 8522 mv a0,s0 + 153a: 3f4080ef jal ra,992e + 153e: e115 bnez a0,1562 + 1540: 200017b7 lui a5,0x20001 + 1544: 38c78793 addi a5,a5,908 # 2000138c <_ebss+0x20c> + 1548: de47c783 lbu a5,-540(a5) + 154c: e791 bnez a5,1558 + 154e: 0000c637 lui a2,0xc + 1552: c1060613 addi a2,a2,-1008 # bc10 <_exit+0x7b8> + 1556: bf4d j 1508 + 1558: 0000c637 lui a2,0xc + 155c: c0c60613 addi a2,a2,-1012 # bc0c <_exit+0x7b4> + 1560: b765 j 1508 + 1562: 0000c5b7 lui a1,0xc + 1566: 460d li a2,3 + 1568: db858593 addi a1,a1,-584 # bdb8 <_exit+0x960> + 156c: 8522 mv a0,s0 + 156e: 3c0080ef jal ra,992e + 1572: e911 bnez a0,1586 + 1574: 200007b7 lui a5,0x20000 + 1578: 3f47a603 lw a2,1012(a5) # 200003f4 + 157c: 0000c5b7 lui a1,0xc + 1580: dbc58593 addi a1,a1,-580 # bdbc <_exit+0x964> + 1584: bf89 j 14d6 + 1586: 0000c5b7 lui a1,0xc + 158a: 460d li a2,3 + 158c: dc458593 addi a1,a1,-572 # bdc4 <_exit+0x96c> + 1590: 8522 mv a0,s0 + 1592: 39c080ef jal ra,992e + 1596: e511 bnez a0,15a2 + 1598: 200007b7 lui a5,0x20000 + 159c: 3f87a603 lw a2,1016(a5) # 200003f8 + 15a0: bff1 j 157c + 15a2: 0000c5b7 lui a1,0xc + 15a6: 4629 li a2,10 + 15a8: dc858593 addi a1,a1,-568 # bdc8 <_exit+0x970> + 15ac: 8522 mv a0,s0 + 15ae: 380080ef jal ra,992e + 15b2: e50d bnez a0,15dc + 15b4: 0000c5b7 lui a1,0xc + 15b8: dd458593 addi a1,a1,-556 # bdd4 <_exit+0x97c> + 15bc: 8526 mv a0,s1 + 15be: 179080ef jal ra,9f36 + 15c2: 20000537 lui a0,0x20000 + 15c6: 04600693 li a3,70 + 15ca: 00248613 addi a2,s1,2 + 15ce: 02000593 li a1,32 + 15d2: 3b050513 addi a0,a0,944 # 200003b0 + 15d6: ec9fe0ef jal ra,49e + 15da: bb85 j 134a + 15dc: 0000c5b7 lui a1,0xc + 15e0: 4611 li a2,4 + 15e2: dd858593 addi a1,a1,-552 # bdd8 <_exit+0x980> + 15e6: 8522 mv a0,s0 + 15e8: 346080ef jal ra,992e + 15ec: e909 bnez a0,15fe + 15ee: 200007b7 lui a5,0x20000 + 15f2: 3d07c503 lbu a0,976(a5) # 200003d0 + 15f6: 741050ef jal ra,7536 + 15fa: 862a mv a2,a0 + 15fc: b731 j 1508 + 15fe: 0000c5b7 lui a1,0xc + 1602: 4639 li a2,14 + 1604: de058593 addi a1,a1,-544 # bde0 <_exit+0x988> + 1608: 8522 mv a0,s0 + 160a: 324080ef jal ra,992e + 160e: e115 bnez a0,1632 + 1610: 200017b7 lui a5,0x20001 + 1614: 38c78793 addi a5,a5,908 # 2000138c <_ebss+0x20c> + 1618: de67d603 lhu a2,-538(a5) + 161c: 0000c5b7 lui a1,0xc + 1620: 3e800793 li a5,1000 + 1624: 02f676b3 remu a3,a2,a5 + 1628: df058593 addi a1,a1,-528 # bdf0 <_exit+0x998> + 162c: 02f65633 divu a2,a2,a5 + 1630: b345 j 13d0 + 1632: 0000c5b7 lui a1,0xc + 1636: 8622 mv a2,s0 + 1638: df858593 addi a1,a1,-520 # bdf8 <_exit+0x9a0> + 163c: bd69 j 14d6 + 163e: 0000c5b7 lui a1,0xc + 1642: e0058593 addi a1,a1,-512 # be00 <_exit+0x9a8> + 1646: 8522 mv a0,s0 + 1648: c81fe0ef jal ra,2c8 + 164c: 16051463 bnez a0,17b4 + 1650: 00440993 addi s3,s0,4 + 1654: 0000c5b7 lui a1,0xc + 1658: 4641 li a2,16 + 165a: e0858593 addi a1,a1,-504 # be08 <_exit+0x9b0> + 165e: 854e mv a0,s3 + 1660: 2ce080ef jal ra,992e + 1664: e921 bnez a0,16b4 + 1666: 0451 addi s0,s0,20 + 1668: 0000c5b7 lui a1,0xc + 166c: 4609 li a2,2 + 166e: c0c58593 addi a1,a1,-1012 # bc0c <_exit+0x7b4> + 1672: 8522 mv a0,s0 + 1674: 2ba080ef jal ra,992e + 1678: ed09 bnez a0,1692 + 167a: 200017b7 lui a5,0x20001 + 167e: 38c78793 addi a5,a5,908 # 2000138c <_ebss+0x20c> + 1682: 4705 li a4,1 + 1684: dee782a3 sb a4,-539(a5) + 1688: 0000c5b7 lui a1,0xc + 168c: e1c58593 addi a1,a1,-484 # be1c <_exit+0x9c4> + 1690: b1e5 j 1378 + 1692: 0000c5b7 lui a1,0xc + 1696: 460d li a2,3 + 1698: c1058593 addi a1,a1,-1008 # bc10 <_exit+0x7b8> + 169c: 8522 mv a0,s0 + 169e: 290080ef jal ra,992e + 16a2: ca0514e3 bnez a0,134a + 16a6: 200017b7 lui a5,0x20001 + 16aa: 38c78793 addi a5,a5,908 # 2000138c <_ebss+0x20c> + 16ae: de0782a3 sb zero,-539(a5) + 16b2: bfd9 j 1688 + 16b4: 0000c5b7 lui a1,0xc + 16b8: 463d li a2,15 + 16ba: e2058593 addi a1,a1,-480 # be20 <_exit+0x9c8> + 16be: 854e mv a0,s3 + 16c0: 26e080ef jal ra,992e + 16c4: e909 bnez a0,16d6 + 16c6: 4641 li a2,16 + 16c8: 01340593 addi a1,s0,19 + 16cc: 77018513 addi a0,gp,1904 # 20001160 <__global_pointer$+0x770> + 16d0: 089080ef jal ra,9f58 + 16d4: bf55 j 1688 + 16d6: 0000c5b7 lui a1,0xc + 16da: 4615 li a2,5 + 16dc: e3058593 addi a1,a1,-464 # be30 <_exit+0x9d8> + 16e0: 854e mv a0,s3 + 16e2: 24c080ef jal ra,992e + 16e6: e911 bnez a0,16fa + 16e8: 20000537 lui a0,0x20000 + 16ec: 02000613 li a2,32 + 16f0: 00940593 addi a1,s0,9 + 16f4: 3d150513 addi a0,a0,977 # 200003d1 + 16f8: bfe1 j 16d0 + 16fa: 0000c5b7 lui a1,0xc + 16fe: 461d li a2,7 + 1700: e3858593 addi a1,a1,-456 # be38 <_exit+0x9e0> + 1704: 854e mv a0,s3 + 1706: 228080ef jal ra,992e + 170a: e939 bnez a0,1760 + 170c: 042d addi s0,s0,11 + 170e: 0000c5b7 lui a1,0xc + 1712: 460d li a2,3 + 1714: c1058593 addi a1,a1,-1008 # bc10 <_exit+0x7b8> + 1718: 8522 mv a0,s0 + 171a: 200019b7 lui s3,0x20001 + 171e: 210080ef jal ra,992e + 1722: 38c98993 addi s3,s3,908 # 2000138c <_ebss+0x20c> + 1726: e901 bnez a0,1736 + 1728: de098223 sb zero,-540(s3) + 172c: 0000c5b7 lui a1,0xc + 1730: c2c58593 addi a1,a1,-980 # bc2c <_exit+0x7d4> + 1734: b191 j 1378 + 1736: 0000c5b7 lui a1,0xc + 173a: 4609 li a2,2 + 173c: c0c58593 addi a1,a1,-1012 # bc0c <_exit+0x7b4> + 1740: 8522 mv a0,s0 + 1742: 1ec080ef jal ra,992e + 1746: e909 bnez a0,1758 + 1748: 4785 li a5,1 + 174a: def98223 sb a5,-540(s3) + 174e: 0000c5b7 lui a1,0xc + 1752: c1458593 addi a1,a1,-1004 # bc14 <_exit+0x7bc> + 1756: b10d j 1378 + 1758: de49c783 lbu a5,-540(s3) + 175c: fbed bnez a5,174e + 175e: b7f9 j 172c + 1760: 0000c5b7 lui a1,0xc + 1764: 4611 li a2,4 + 1766: e4058593 addi a1,a1,-448 # be40 <_exit+0x9e8> + 176a: 854e mv a0,s3 + 176c: 1c2080ef jal ra,992e + 1770: e911 bnez a0,1784 + 1772: 00840513 addi a0,s0,8 + 1776: fe4ff0ef jal ra,f5a + 177a: 200007b7 lui a5,0x20000 + 177e: 3ea7aa23 sw a0,1012(a5) # 200003f4 + 1782: b719 j 1688 + 1784: 0000c5b7 lui a1,0xc + 1788: 4611 li a2,4 + 178a: e4858593 addi a1,a1,-440 # be48 <_exit+0x9f0> + 178e: 854e mv a0,s3 + 1790: 19e080ef jal ra,992e + 1794: e911 bnez a0,17a8 + 1796: 00840513 addi a0,s0,8 + 179a: fc0ff0ef jal ra,f5a + 179e: 200007b7 lui a5,0x20000 + 17a2: 3ea7ac23 sw a0,1016(a5) # 200003f8 + 17a6: b5cd j 1688 + 17a8: 0000c5b7 lui a1,0xc + 17ac: 864e mv a2,s3 + 17ae: e5058593 addi a1,a1,-432 # be50 <_exit+0x9f8> + 17b2: b315 j 14d6 + 17b4: 0000c5b7 lui a1,0xc + 17b8: e6458593 addi a1,a1,-412 # be64 <_exit+0xa0c> + 17bc: 8522 mv a0,s0 + 17be: b0bfe0ef jal ra,2c8 + 17c2: e105 bnez a0,17e2 + 17c4: 94c18613 addi a2,gp,-1716 # 2000033c + 17c8: 0000c5b7 lui a1,0xc + 17cc: 02462883 lw a7,36(a2) + 17d0: 02062803 lw a6,32(a2) + 17d4: 4e5c lw a5,28(a2) + 17d6: 4e18 lw a4,24(a2) + 17d8: 4654 lw a3,12(a2) + 17da: e7458593 addi a1,a1,-396 # be74 <_exit+0xa1c> + 17de: 4610 lw a2,8(a2) + 17e0: b191 j 1424 + 17e2: 0000c5b7 lui a1,0xc + 17e6: ec458593 addi a1,a1,-316 # bec4 <_exit+0xa6c> + 17ea: 8522 mv a0,s0 + 17ec: addfe0ef jal ra,2c8 + 17f0: e51d bnez a0,181e + 17f2: 94c18613 addi a2,gp,-1716 # 2000033c + 17f6: 02a61683 lh a3,42(a2) + 17fa: 4711 li a4,4 + 17fc: 03062803 lw a6,48(a2) + 1800: 02e6c733 div a4,a3,a4 + 1804: 4a1c lw a5,16(a2) + 1806: 00661683 lh a3,6(a2) + 180a: 00461603 lh a2,4(a2) + 180e: 0000c5b7 lui a1,0xc + 1812: ed058593 addi a1,a1,-304 # bed0 <_exit+0xa78> + 1816: 8526 mv a0,s1 + 1818: 6ba080ef jal ra,9ed2 + 181c: b63d j 134a + 181e: 0000c5b7 lui a1,0xc + 1822: f2858593 addi a1,a1,-216 # bf28 <_exit+0xad0> + 1826: 8522 mv a0,s0 + 1828: aa1fe0ef jal ra,2c8 + 182c: e90d bnez a0,185e + 182e: 1dd070ef jal ra,920a + 1832: 81c1a783 lw a5,-2020(gp) # 2000020c + 1836: 94c18413 addi s0,gp,-1716 # 2000033c + 183a: 8d1d sub a0,a0,a5 + 183c: c848 sw a0,20(s0) + 183e: 00042823 sw zero,16(s0) + 1842: 193050ef jal ra,71d4 + 1846: 203e lhu a5,2(s0) + 1848: 341a lhu a4,40(s0) + 184a: 4854 lw a3,20(s0) + 184c: 0000c5b7 lui a1,0xc + 1850: 862a mv a2,a0 + 1852: f3458593 addi a1,a1,-204 # bf34 <_exit+0xadc> + 1856: 8526 mv a0,s1 + 1858: 67a080ef jal ra,9ed2 + 185c: b4fd j 134a + 185e: 0000c5b7 lui a1,0xc + 1862: f7458593 addi a1,a1,-140 # bf74 <_exit+0xb1c> + 1866: be09 j 1378 + +00001868 : + 1868: 96ffe2ef jal t0,1d6 <__riscv_save_4> + 186c: 842a mv s0,a0 + 186e: 0000c537 lui a0,0xc + 1872: 7121 addi sp,sp,-448 + 1874: b3050513 addi a0,a0,-1232 # bb30 <_exit+0x6d8> + 1878: 34e080ef jal ra,9bc6 + 187c: 0b944583 lbu a1,185(s0) + 1880: 0000c537 lui a0,0xc + 1884: bd050513 addi a0,a0,-1072 # bbd0 <_exit+0x778> + 1888: 33e080ef jal ra,9bc6 + 188c: 200c lbu a1,0(s0) + 188e: 0000c537 lui a0,0xc + 1892: b4450513 addi a0,a0,-1212 # bb44 <_exit+0x6ec> + 1896: 330080ef jal ra,9bc6 + 189a: 300c lbu a1,1(s0) + 189c: 0000c537 lui a0,0xc + 18a0: b6050513 addi a0,a0,-1184 # bb60 <_exit+0x708> + 18a4: 322080ef jal ra,9bc6 + 18a8: 202e lhu a1,2(s0) + 18aa: 0000c537 lui a0,0xc + 18ae: b7850513 addi a0,a0,-1160 # bb78 <_exit+0x720> + 18b2: 314080ef jal ra,9bc6 + 18b6: 204c lbu a1,4(s0) + 18b8: 0000c537 lui a0,0xc + 18bc: a2050513 addi a0,a0,-1504 # ba20 <_exit+0x5c8> + 18c0: 306080ef jal ra,9bc6 + 18c4: 2050 lbu a2,4(s0) + 18c6: 0000c537 lui a0,0xc + 18ca: 00540593 addi a1,s0,5 + 18ce: ba450513 addi a0,a0,-1116 # bba4 <_exit+0x74c> + 18d2: b11fe0ef jal ra,3e2 + 18d6: 0000e537 lui a0,0xe + 18da: 99850513 addi a0,a0,-1640 # d998 + 18de: 2e8080ef jal ra,9bc6 + 18e2: 0b944783 lbu a5,185(s0) + 18e6: 02000713 li a4,32 + 18ea: 08e79463 bne a5,a4,1972 + 18ee: 3044 lbu s1,5(s0) + 18f0: 04000793 li a5,64 + 18f4: 0c910423 sb s1,200(sp) + 18f8: 0297f363 bgeu a5,s1,191e + 18fc: 0000c637 lui a2,0xc + 1900: 0000b5b7 lui a1,0xb + 1904: 0000c537 lui a0,0xc + 1908: f8460613 addi a2,a2,-124 # bf84 <_exit+0xb2c> + 190c: 49458593 addi a1,a1,1172 # b494 <_exit+0x3c> + 1910: a3450513 addi a0,a0,-1484 # ba34 <_exit+0x5dc> + 1914: 2b2080ef jal ra,9bc6 + 1918: 6139 addi sp,sp,448 + 191a: 8f1fe06f j 20a <__riscv_restore_4> + 191e: 8626 mv a2,s1 + 1920: 00640593 addi a1,s0,6 + 1924: 0c910513 addi a0,sp,201 + 1928: 02a080ef jal ra,9952 + 192c: 00248593 addi a1,s1,2 + 1930: 0485 addi s1,s1,1 + 1932: 2050 lbu a2,4(s0) + 1934: 0ff4f493 andi s1,s1,255 + 1938: 94a2 add s1,s1,s0 + 193a: 30dc lbu a5,5(s1) + 193c: 0ff5f593 andi a1,a1,255 + 1940: 8e0d sub a2,a2,a1 + 1942: 0595 addi a1,a1,5 + 1944: 0ff67613 andi a2,a2,255 + 1948: 95a2 add a1,a1,s0 + 194a: 10b10513 addi a0,sp,267 + 194e: 10f104a3 sb a5,265(sp) + 1952: 10c10523 sb a2,266(sp) + 1956: 7fd070ef jal ra,9952 + 195a: 0c442783 lw a5,196(s0) + 195e: 239c lbu a5,0(a5) + 1960: 8b89 andi a5,a5,2 + 1962: fbdd bnez a5,1918 + 1964: 0c042583 lw a1,192(s0) + 1968: 0bc42503 lw a0,188(s0) + 196c: 945ff0ef jal ra,12b0 + 1970: b765 j 1918 + 1972: 20079c63 bnez a5,1b8a + 1976: 2078 lbu a4,6(s0) + 1978: 305c lbu a5,5(s0) + 197a: 00a40593 addi a1,s0,10 + 197e: 0722 slli a4,a4,0x8 + 1980: 8f5d or a4,a4,a5 + 1982: 307c lbu a5,7(s0) + 1984: 01210513 addi a0,sp,18 + 1988: 07c2 slli a5,a5,0x10 + 198a: 8f5d or a4,a4,a5 + 198c: 241c lbu a5,8(s0) + 198e: 07e2 slli a5,a5,0x18 + 1990: 8fd9 or a5,a5,a4 + 1992: 0bc42703 lw a4,188(s0) + 1996: c63e sw a5,12(sp) + 1998: 0af72623 sw a5,172(a4) # e000e0ac <_eusrstack+0xc00060ac> + 199c: 2050 lbu a2,4(s0) + 199e: 341c lbu a5,9(s0) + 19a0: 166d addi a2,a2,-5 + 19a2: 0ff67613 andi a2,a2,255 + 19a6: 00f10823 sb a5,16(sp) + 19aa: 00c108a3 sb a2,17(sp) + 19ae: 7a5070ef jal ra,9952 + 19b2: 0068 addi a0,sp,12 + 19b4: 86bff0ef jal ra,121e + 19b8: 0c442783 lw a5,196(s0) + 19bc: 239c lbu a5,0(a5) + 19be: 8b89 andi a5,a5,2 + 19c0: e799 bnez a5,19ce + 19c2: 0c042583 lw a1,192(s0) + 19c6: 0bc42503 lw a0,188(s0) + 19ca: 8e7ff0ef jal ra,12b0 + 19ce: 01014783 lbu a5,16(sp) + 19d2: 4985 li s3,1 + 19d4: 17378c63 beq a5,s3,1b4c + 19d8: 470d li a4,3 + 19da: f2e79fe3 bne a5,a4,1918 + 19de: 47b2 lw a5,12(sp) + 19e0: 0bc42703 lw a4,188(s0) + 19e4: 06700913 li s2,103 + 19e8: c5be sw a5,200(sp) + 19ea: 0af72623 sw a5,172(a4) + 19ee: 10200793 li a5,258 + 19f2: 0cf11623 sh a5,204(sp) + 19f6: 0d210723 sb s2,206(sp) + 19fa: 7ae050ef jal ra,71a8 + 19fe: 0cc14783 lbu a5,204(sp) + 1a02: 0398 addi a4,sp,448 + 1a04: 40855693 srai a3,a0,0x8 + 1a08: 973e add a4,a4,a5 + 1a0a: f0d706a3 sb a3,-243(a4) + 1a0e: 00178713 addi a4,a5,1 + 1a12: 0394 addi a3,sp,448 + 1a14: 0ff77713 andi a4,a4,255 + 1a18: 9736 add a4,a4,a3 + 1a1a: f0a706a3 sb a0,-243(a4) + 1a1e: 00278713 addi a4,a5,2 + 1a22: 0ff77713 andi a4,a4,255 + 1a26: 9736 add a4,a4,a3 + 1a28: f13706a3 sb s3,-243(a4) + 1a2c: 00378713 addi a4,a5,3 + 1a30: 0ff77713 andi a4,a4,255 + 1a34: 9736 add a4,a4,a3 + 1a36: 07400593 li a1,116 + 1a3a: f0b706a3 sb a1,-243(a4) + 1a3e: 94c1d683 lhu a3,-1716(gp) # 2000033c + 1a42: 4729 li a4,10 + 1a44: 0390 addi a2,sp,448 + 1a46: 02e6d6b3 divu a3,a3,a4 + 1a4a: 00478713 addi a4,a5,4 + 1a4e: 0ff77713 andi a4,a4,255 + 1a52: 9732 add a4,a4,a2 + 1a54: 84aa mv s1,a0 + 1a56: 01069613 slli a2,a3,0x10 + 1a5a: 8641 srai a2,a2,0x10 + 1a5c: 8621 srai a2,a2,0x8 + 1a5e: f0c706a3 sb a2,-243(a4) + 1a62: 00578713 addi a4,a5,5 + 1a66: 0390 addi a2,sp,448 + 1a68: 0ff77713 andi a4,a4,255 + 1a6c: 9732 add a4,a4,a2 + 1a6e: f0d706a3 sb a3,-243(a4) + 1a72: 00678713 addi a4,a5,6 + 1a76: 0ff77713 andi a4,a4,255 + 1a7a: 86b2 mv a3,a2 + 1a7c: 9732 add a4,a4,a2 + 1a7e: 4609 li a2,2 + 1a80: f0c706a3 sb a2,-243(a4) + 1a84: 00778713 addi a4,a5,7 + 1a88: 0ff77713 andi a4,a4,255 + 1a8c: 9736 add a4,a4,a3 + 1a8e: f0b706a3 sb a1,-243(a4) + 1a92: 00878713 addi a4,a5,8 + 1a96: 0ff77713 andi a4,a4,255 + 1a9a: 9736 add a4,a4,a3 + 1a9c: 469d li a3,7 + 1a9e: f0d706a3 sb a3,-243(a4) + 1aa2: 00a78713 addi a4,a5,10 + 1aa6: 00978693 addi a3,a5,9 + 1aaa: 038c addi a1,sp,448 + 1aac: 0ff77713 andi a4,a4,255 + 1ab0: 0ff6f693 andi a3,a3,255 + 1ab4: 96ae add a3,a3,a1 + 1ab6: 0ce10623 sb a4,204(sp) + 1aba: fb500593 li a1,-75 + 1abe: f0b686a3 sb a1,-243(a3) + 1ac2: 0bc42683 lw a3,188(s0) + 1ac6: 0ab6c683 lbu a3,171(a3) + 1aca: c6a5 beqz a3,1b32 + 1acc: 0394 addi a3,sp,448 + 1ace: 9736 add a4,a4,a3 + 1ad0: f0c706a3 sb a2,-243(a4) + 1ad4: 00b78713 addi a4,a5,11 + 1ad8: 0ff77713 andi a4,a4,255 + 1adc: 9736 add a4,a4,a3 + 1ade: f12706a3 sb s2,-243(a4) + 1ae2: 00c78713 addi a4,a5,12 + 1ae6: 0ff77713 andi a4,a4,255 + 1aea: 9736 add a4,a4,a3 + 1aec: 46ed li a3,27 + 1aee: f0d706a3 sb a3,-243(a4) + 1af2: 00e78713 addi a4,a5,14 + 1af6: 07b5 addi a5,a5,13 + 1af8: 0ff77713 andi a4,a4,255 + 1afc: 0394 addi a3,sp,448 + 1afe: 0ff7f793 andi a5,a5,255 + 1b02: 0ce10623 sb a4,204(sp) + 1b06: 97b6 add a5,a5,a3 + 1b08: 46f9 li a3,30 + 1b0a: f0d786a3 sb a3,-243(a5) + 1b0e: 200007b7 lui a5,0x20000 + 1b12: 38c78793 addi a5,a5,908 # 2000038c + 1b16: 01b4 addi a3,sp,200 + 1b18: 0715 addi a4,a4,5 + 1b1a: 9736 add a4,a4,a3 + 1b1c: 57f0 lw a2,108(a5) + 1b1e: 5bb4 lw a3,112(a5) + 1b20: 57ac lw a1,104(a5) + 1b22: 4505 li a0,1 + 1b24: 6ee050ef jal ra,7212 + 1b28: 0cc14783 lbu a5,204(sp) + 1b2c: 07ad addi a5,a5,11 + 1b2e: 0cf10623 sb a5,204(sp) + 1b32: 0bc42503 lw a0,188(s0) + 1b36: 01ac addi a1,sp,200 + 1b38: e0aff0ef jal ra,1142 + 1b3c: 0000c537 lui a0,0xc + 1b40: 85a6 mv a1,s1 + 1b42: a5050513 addi a0,a0,-1456 # ba50 <_exit+0x5f8> + 1b46: 080080ef jal ra,9bc6 + 1b4a: b3f9 j 1918 + 1b4c: 6be070ef jal ra,920a + 1b50: c5aa sw a0,200(sp) + 1b52: 6b8070ef jal ra,920a + 1b56: 81c1a783 lw a5,-2020(gp) # 2000020c + 1b5a: 94c18713 addi a4,gp,-1716 # 2000033c + 1b5e: 8d1d sub a0,a0,a5 + 1b60: cb48 sw a0,20(a4) + 1b62: 03400613 li a2,52 + 1b66: 94c18593 addi a1,gp,-1716 # 2000033c + 1b6a: 0cd10513 addi a0,sp,205 + 1b6e: 00072823 sw zero,16(a4) + 1b72: 5e1070ef jal ra,9952 + 1b76: 0bc42503 lw a0,188(s0) + 1b7a: 03400793 li a5,52 + 1b7e: 01ac addi a1,sp,200 + 1b80: 0cf10623 sb a5,204(sp) + 1b84: dbeff0ef jal ra,1142 + 1b88: bb41 j 1918 + 1b8a: 4711 li a4,4 + 1b8c: 02e79d63 bne a5,a4,1bc6 + 1b90: 2078 lbu a4,6(s0) + 1b92: 305c lbu a5,5(s0) + 1b94: 2050 lbu a2,4(s0) + 1b96: 0722 slli a4,a4,0x8 + 1b98: 8f5d or a4,a4,a5 + 1b9a: 307c lbu a5,7(s0) + 1b9c: 1671 addi a2,a2,-4 + 1b9e: 0ff67613 andi a2,a2,255 + 1ba2: 07c2 slli a5,a5,0x10 + 1ba4: 8f5d or a4,a4,a5 + 1ba6: 241c lbu a5,8(s0) + 1ba8: 00940593 addi a1,s0,9 + 1bac: 0cd10513 addi a0,sp,205 + 1bb0: 07e2 slli a5,a5,0x18 + 1bb2: 8fd9 or a5,a5,a4 + 1bb4: c5be sw a5,200(sp) + 1bb6: 0cc10623 sb a2,204(sp) + 1bba: 599070ef jal ra,9952 + 1bbe: 01a8 addi a0,sp,200 + 1bc0: eaeff0ef jal ra,126e + 1bc4: bb91 j 1918 + 1bc6: 4721 li a4,8 + 1bc8: d4e798e3 bne a5,a4,1918 + 1bcc: 2078 lbu a4,6(s0) + 1bce: 305c lbu a5,5(s0) + 1bd0: 0bc42483 lw s1,188(s0) + 1bd4: 0722 slli a4,a4,0x8 + 1bd6: 8f5d or a4,a4,a5 + 1bd8: 307c lbu a5,7(s0) + 1bda: 00a40593 addi a1,s0,10 + 1bde: 0ce10513 addi a0,sp,206 + 1be2: 07c2 slli a5,a5,0x10 + 1be4: 8f5d or a4,a4,a5 + 1be6: 241c lbu a5,8(s0) + 1be8: 07e2 slli a5,a5,0x18 + 1bea: 8fd9 or a5,a5,a4 + 1bec: c5be sw a5,200(sp) + 1bee: 0af4a623 sw a5,172(s1) + 1bf2: 341c lbu a5,9(s0) + 1bf4: 2050 lbu a2,4(s0) + 1bf6: 0037f713 andi a4,a5,3 + 1bfa: 166d addi a2,a2,-5 + 1bfc: 8389 srli a5,a5,0x2 + 1bfe: 0cf10623 sb a5,204(sp) + 1c02: 0ce106a3 sb a4,205(sp) + 1c06: 54d070ef jal ra,9952 + 1c0a: 0c442783 lw a5,196(s0) + 1c0e: 239c lbu a5,0(a5) + 1c10: 8b89 andi a5,a5,2 + 1c12: e791 bnez a5,1c1e + 1c14: 0c042583 lw a1,192(s0) + 1c18: 8526 mv a0,s1 + 1c1a: e96ff0ef jal ra,12b0 + 1c1e: 0cc14683 lbu a3,204(sp) + 1c22: 4785 li a5,1 + 1c24: 04f68363 beq a3,a5,1c6a + 1c28: c29d beqz a3,1c4e + 1c2a: 4789 li a5,2 + 1c2c: 04f68a63 beq a3,a5,1c80 + 1c30: 0000c637 lui a2,0xc + 1c34: 0000b5b7 lui a1,0xb + 1c38: 0000c537 lui a0,0xc + 1c3c: f8460613 addi a2,a2,-124 # bf84 <_exit+0xb2c> + 1c40: 49458593 addi a1,a1,1172 # b494 <_exit+0x3c> + 1c44: b0c50513 addi a0,a0,-1268 # bb0c <_exit+0x6b4> + 1c48: 77f070ef jal ra,9bc6 + 1c4c: b1f1 j 1918 + 1c4e: 46ae lw a3,200(sp) + 1c50: 0cd14603 lbu a2,205(sp) + 1c54: 0bc42583 lw a1,188(s0) + 1c58: 0000c537 lui a0,0xc + 1c5c: 0ce10713 addi a4,sp,206 + 1c60: a8450513 addi a0,a0,-1404 # ba84 <_exit+0x62c> + 1c64: 763070ef jal ra,9bc6 + 1c68: b945 j 1918 + 1c6a: 0bc42583 lw a1,188(s0) + 1c6e: 0ab5c783 lbu a5,171(a1) + 1c72: ca0783e3 beqz a5,1918 + 1c76: 0ce10513 addi a0,sp,206 + 1c7a: e62ff0ef jal ra,12dc + 1c7e: b969 j 1918 + 1c80: 0ce15783 lhu a5,206(sp) + 1c84: 0068 addi a0,sp,12 + 1c86: 867c sh a5,12(sp) + 1c88: 0d015783 lhu a5,208(sp) + 1c8c: 877c sh a5,14(sp) + 1c8e: 63c050ef jal ra,72ca + 1c92: 472e lw a4,200(sp) + 1c94: 0cd14683 lbu a3,205(sp) + 1c98: 0bc42583 lw a1,188(s0) + 1c9c: 862a mv a2,a0 + 1c9e: 0000c537 lui a0,0xc + 1ca2: 0d210793 addi a5,sp,210 + 1ca6: abc50513 addi a0,a0,-1348 # babc <_exit+0x664> + 1caa: 71d070ef jal ra,9bc6 + 1cae: b1ad j 1918 + +00001cb0 : + 1cb0: d26fe2ef jal t0,1d6 <__riscv_save_4> + 1cb4: 7155 addi sp,sp,-208 + 1cb6: 842a mv s0,a0 + 1cb8: 0bc00613 li a2,188 + 1cbc: 4581 li a1,0 + 1cbe: 0068 addi a0,sp,12 + 1cc0: d60fe0ef jal ra,220 + 1cc4: 00540793 addi a5,s0,5 + 1cc8: 4478 lw a4,76(s0) + 1cca: c5be sw a5,200(sp) + 1ccc: 201c lbu a5,0(s0) + 1cce: c43a sw a4,8(sp) + 1cd0: 20000737 lui a4,0x20000 + 1cd4: 03c7f793 andi a5,a5,60 + 1cd8: 0cf100a3 sb a5,193(sp) + 1cdc: 3b074703 lbu a4,944(a4) # 200003b0 + 1ce0: 04c44783 lbu a5,76(s0) + 1ce4: c7a2 sw s0,204(sp) + 1ce6: 04d44683 lbu a3,77(s0) + 1cea: 04f71263 bne a4,a5,1d2e + 1cee: 0000c937 lui s2,0xc + 1cf2: 0000b9b7 lui s3,0xb + 1cf6: 0000c537 lui a0,0xc + 1cfa: f8490613 addi a2,s2,-124 # bf84 <_exit+0xb2c> + 1cfe: 4ec98593 addi a1,s3,1260 # b4ec <_exit+0x94> + 1d02: 93850513 addi a0,a0,-1736 # b938 <_exit+0x4e0> + 1d06: 6c1070ef jal ra,9bc6 + 1d0a: 8488 lbu a0,9(sp) + 1d0c: 586050ef jal ra,7292 + 1d10: c3aa sw a0,196(sp) + 1d12: 84aa mv s1,a0 + 1d14: e105 bnez a0,1d34 + 1d16: 0000b5b7 lui a1,0xb + 1d1a: 0000c537 lui a0,0xc + 1d1e: f8490613 addi a2,s2,-124 + 1d22: 49458593 addi a1,a1,1172 # b494 <_exit+0x3c> + 1d26: 96c50513 addi a0,a0,-1684 # b96c <_exit+0x514> + 1d2a: 69d070ef jal ra,9bc6 + 1d2e: 6169 addi sp,sp,208 + 1d30: cdafe06f j 20a <__riscv_restore_4> + 1d34: 4d6070ef jal ra,920a + 1d38: 200007b7 lui a5,0x20000 + 1d3c: 5d078793 addi a5,a5,1488 # 200005d0 + 1d40: 40f487b3 sub a5,s1,a5 + 1d44: e9bd36b7 lui a3,0xe9bd3 + 1d48: 878d srai a5,a5,0x3 + 1d4a: 7a768693 addi a3,a3,1959 # e9bd37a7 <_eusrstack+0xc9bcb7a7> + 1d4e: 02d786b3 mul a3,a5,a3 + 1d52: 0aa4a823 sw a0,176(s1) + 1d56: 0000c537 lui a0,0xc + 1d5a: f8490613 addi a2,s2,-124 + 1d5e: 4ec98593 addi a1,s3,1260 + 1d62: 98850513 addi a0,a0,-1656 # b988 <_exit+0x530> + 1d66: 661070ef jal ra,9bc6 + 1d6a: 4434 lw a3,72(s0) + 1d6c: 00d10713 addi a4,sp,13 + 1d70: 04e40613 addi a2,s0,78 + 1d74: 16f9 addi a3,a3,-2 + 1d76: 02000593 li a1,32 + 1d7a: 04048513 addi a0,s1,64 + 1d7e: 2d9000ef jal ra,2856 + 1d82: cd05 beqz a0,1dba + 1d84: 0000b5b7 lui a1,0xb + 1d88: 0000c537 lui a0,0xc + 1d8c: 86a6 mv a3,s1 + 1d8e: f8490613 addi a2,s2,-124 + 1d92: 49458593 addi a1,a1,1172 # b494 <_exit+0x3c> + 1d96: 9ac50513 addi a0,a0,-1620 # b9ac <_exit+0x554> + 1d9a: 62d070ef jal ra,9bc6 + 1d9e: 0c114583 lbu a1,193(sp) + 1da2: 0000c537 lui a0,0xc + 1da6: a0c50513 addi a0,a0,-1524 # ba0c <_exit+0x5b4> + 1daa: 61d070ef jal ra,9bc6 + 1dae: 861c lbu a5,12(sp) + 1db0: dfbd beqz a5,1d2e + 1db2: 0028 addi a0,sp,8 + 1db4: ab5ff0ef jal ra,1868 + 1db8: bf9d j 1d2e + 1dba: 4438 lw a4,72(s0) + 1dbc: 0000c537 lui a0,0xc + 1dc0: f8490613 addi a2,s2,-124 + 1dc4: 1779 addi a4,a4,-2 + 1dc6: 0ff77713 andi a4,a4,255 + 1dca: 4ec98593 addi a1,s3,1260 + 1dce: 86a6 mv a3,s1 + 1dd0: 9dc50513 addi a0,a0,-1572 # b9dc <_exit+0x584> + 1dd4: 8658 sb a4,12(sp) + 1dd6: 5f1070ef jal ra,9bc6 + 1dda: 01210513 addi a0,sp,18 + 1dde: 168080ef jal ra,9f46 + 1de2: 00550593 addi a1,a0,5 + 1de6: 02048613 addi a2,s1,32 + 1dea: 0ff5f593 andi a1,a1,255 + 1dee: 00d10513 addi a0,sp,13 + 1df2: efafe0ef jal ra,4ec + 1df6: b765 j 1d9e + +00001df8 : + 1df8: bdefe2ef jal t0,1d6 <__riscv_save_4> + 1dfc: 7145 addi sp,sp,-464 + 1dfe: 00154903 lbu s2,1(a0) + 1e02: 84aa mv s1,a0 + 1e04: 406070ef jal ra,920a + 1e08: 03800713 li a4,56 + 1e0c: 02e90733 mul a4,s2,a4 + 1e10: 47d5 li a5,21 + 1e12: 20000437 lui s0,0x20000 + 1e16: 0cf10623 sb a5,204(sp) + 1e1a: 38c40793 addi a5,s0,908 # 2000038c + 1e1e: 00948593 addi a1,s1,9 + 1e22: cc2a sw a0,24(sp) + 1e24: 89aa mv s3,a0 + 1e26: 852e mv a0,a1 + 1e28: c62e sw a1,12(sp) + 1e2a: 97ba add a5,a5,a4 + 1e2c: 0b47c783 lbu a5,180(a5) + 1e30: 0c0108a3 sb zero,209(sp) + 1e34: 00010e23 sb zero,28(sp) + 1e38: 10f10c23 sb a5,280(sp) + 1e3c: 10a080ef jal ra,9f46 + 1e40: 00550713 addi a4,a0,5 + 1e44: 0b400793 li a5,180 + 1e48: 38c40413 addi s0,s0,908 + 1e4c: 45b2 lw a1,12(sp) + 1e4e: 0af00493 li s1,175 + 1e52: 00e7e363 bltu a5,a4,1e58 + 1e56: 84aa mv s1,a0 + 1e58: 8626 mv a2,s1 + 1e5a: 01d10513 addi a0,sp,29 + 1e5e: 2f5070ef jal ra,9952 + 1e62: 0495 addi s1,s1,5 + 1e64: 0000c537 lui a0,0xc + 1e68: 8626 mv a2,s1 + 1e6a: 082c addi a1,sp,24 + 1e6c: 0d450513 addi a0,a0,212 # c0d4 <_exit+0xc7c> + 1e70: d72fe0ef jal ra,3e2 + 1e74: 03800793 li a5,56 + 1e78: 02f90933 mul s2,s2,a5 + 1e7c: 11910713 addi a4,sp,281 + 1e80: 0830 addi a2,sp,24 + 1e82: 085c addi a5,sp,20 + 1e84: 86a6 mv a3,s1 + 1e86: 45c1 li a1,16 + 1e88: ca02 sw zero,20(sp) + 1e8a: 0a490513 addi a0,s2,164 + 1e8e: 9522 add a0,a0,s0 + 1e90: 12d000ef jal ra,27bc + 1e94: 47d2 lw a5,20(sp) + 1e96: 944a add s0,s0,s2 + 1e98: 01e8 addi a0,sp,204 + 1e9a: 0785 addi a5,a5,1 + 1e9c: 0b342c23 sw s3,184(s0) + 1ea0: 10f12a23 sw a5,276(sp) + 1ea4: 2bdd jal 249a + 1ea6: 6179 addi sp,sp,464 + 1ea8: b62fe06f j 20a <__riscv_restore_4> + +00001eac : + 1eac: b44fe2ef jal t0,1f0 <__riscv_save_0> + 1eb0: 7155 addi sp,sp,-208 + 1eb2: 842e mv s0,a1 + 1eb4: 200005b7 lui a1,0x20000 + 1eb8: 84aa mv s1,a0 + 1eba: 3d158593 addi a1,a1,977 # 200003d1 + 1ebe: 01110513 addi a0,sp,17 + 1ec2: 074080ef jal ra,9f36 + 1ec6: 0000c5b7 lui a1,0xc + 1eca: 82058593 addi a1,a1,-2016 # b820 <_exit+0x3c8> + 1ece: 01110513 addi a0,sp,17 + 1ed2: 046080ef jal ra,9f18 + 1ed6: 85a6 mv a1,s1 + 1ed8: 01110513 addi a0,sp,17 + 1edc: 03c080ef jal ra,9f18 + 1ee0: 0028 addi a0,sp,8 + 1ee2: 84c0 sb s0,9(sp) + 1ee4: 3f11 jal 1df8 + 1ee6: 6169 addi sp,sp,208 + 1ee8: b2cfe06f j 214 <__riscv_restore_0> + +00001eec : + 1eec: aeafe2ef jal t0,1d6 <__riscv_save_4> + 1ef0: 7109 addi sp,sp,-384 + 1ef2: 842a mv s0,a0 + 1ef4: 0c800613 li a2,200 + 1ef8: 4581 li a1,0 + 1efa: 1928 addi a0,sp,184 + 1efc: b24fe0ef jal ra,220 + 1f00: 201c lbu a5,0(s0) + 1f02: 4751 li a4,20 + 1f04: 03c7f793 andi a5,a5,60 + 1f08: 02e78363 beq a5,a4,1f2e + 1f0c: 0000c637 lui a2,0xc + 1f10: 0000b5b7 lui a1,0xb + 1f14: 0000c537 lui a0,0xc + 1f18: 03460613 addi a2,a2,52 # c034 <_exit+0xbdc> + 1f1c: 49458593 addi a1,a1,1172 # b494 <_exit+0x3c> + 1f20: 04450513 addi a0,a0,68 # c044 <_exit+0xbec> + 1f24: 4a3070ef jal ra,9bc6 + 1f28: 6119 addi sp,sp,384 + 1f2a: ae0fe06f j 20a <__riscv_restore_4> + 1f2e: 04c44783 lbu a5,76(s0) + 1f32: 4481 li s1,0 + 1f34: 04d40b13 addi s6,s0,77 + 1f38: 0af10c23 sb a5,184(sp) + 1f3c: 0000cab7 lui s5,0xc + 1f40: 0000ba37 lui s4,0xb + 1f44: 0000c9b7 lui s3,0xc + 1f48: 0b814503 lbu a0,184(sp) + 1f4c: 85a6 mv a1,s1 + 1f4e: 3b8050ef jal ra,7306 + 1f52: 892a mv s2,a0 + 1f54: e115 bnez a0,1f78 + 1f56: 0b814683 lbu a3,184(sp) + 1f5a: 0000c637 lui a2,0xc + 1f5e: 0000b5b7 lui a1,0xb + 1f62: 0000c537 lui a0,0xc + 1f66: 03460613 addi a2,a2,52 # c034 <_exit+0xbdc> + 1f6a: 49458593 addi a1,a1,1172 # b494 <_exit+0x3c> + 1f6e: 06050513 addi a0,a0,96 # c060 <_exit+0xc08> + 1f72: 455070ef jal ra,9bc6 + 1f76: bf4d j 1f28 + 1f78: 4434 lw a3,72(s0) + 1f7a: 870a mv a4,sp + 1f7c: 865a mv a2,s6 + 1f7e: 16fd addi a3,a3,-1 + 1f80: 45c1 li a1,16 + 1f82: 02050513 addi a0,a0,32 + 1f86: 0d1000ef jal ra,2856 + 1f8a: cd19 beqz a0,1fa8 + 1f8c: 0b814683 lbu a3,184(sp) + 1f90: 034a8613 addi a2,s5,52 # c034 <_exit+0xbdc> + 1f94: 494a0593 addi a1,s4,1172 # b494 <_exit+0x3c> + 1f98: 08898513 addi a0,s3,136 # c088 <_exit+0xc30> + 1f9c: 0485 addi s1,s1,1 + 1f9e: 429070ef jal ra,9bc6 + 1fa2: 0ff4f493 andi s1,s1,255 + 1fa6: b74d j 1f48 + 1fa8: 4782 lw a5,0(sp) + 1faa: 4430 lw a2,72(s0) + 1fac: 00510593 addi a1,sp,5 + 1fb0: df3e sw a5,188(sp) + 1fb2: 167d addi a2,a2,-1 + 1fb4: 821c lbu a5,4(sp) + 1fb6: 0ff67613 andi a2,a2,255 + 1fba: 166d addi a2,a2,-5 + 1fbc: 0c110513 addi a0,sp,193 + 1fc0: 0cf10023 sb a5,192(sp) + 1fc4: 18f070ef jal ra,9952 + 1fc8: 242070ef jal ra,920a + 1fcc: 02a92a23 sw a0,52(s2) + 1fd0: 0000c537 lui a0,0xc + 1fd4: 0c110613 addi a2,sp,193 + 1fd8: 85ca mv a1,s2 + 1fda: 0b450513 addi a0,a0,180 # c0b4 <_exit+0xc5c> + 1fde: 3e9070ef jal ra,9bc6 + 1fe2: b799 j 1f28 + +00001fe4 : + 1fe4: a0cfe2ef jal t0,1f0 <__riscv_save_0> + 1fe8: 842a mv s0,a0 + 1fea: 2c41 jal 227a + 1fec: 2014 lbu a3,0(s0) + 1fee: 0000c4b7 lui s1,0xc + 1ff2: 0c06f793 andi a5,a3,192 + 1ff6: cf91 beqz a5,2012 + 1ff8: 0000b5b7 lui a1,0xb + 1ffc: 0000c537 lui a0,0xc + 2000: 8299 srli a3,a3,0x6 + 2002: 0e048613 addi a2,s1,224 # c0e0 <_exit+0xc88> + 2006: 49458593 addi a1,a1,1172 # b494 <_exit+0x3c> + 200a: 0ec50513 addi a0,a0,236 # c0ec <_exit+0xc94> + 200e: 3b9070ef jal ra,9bc6 + 2012: 94c18693 addi a3,gp,-1716 # 2000033c + 2016: 4690 lw a2,8(a3) + 2018: 2018 lbu a4,0(s0) + 201a: 94c18793 addi a5,gp,-1716 # 2000033c + 201e: 00160513 addi a0,a2,1 + 2022: c688 sw a0,8(a3) + 2024: 00277693 andi a3,a4,2 + 2028: 03c77593 andi a1,a4,60 + 202c: e6cd bnez a3,20d6 + 202e: 5394 lw a3,32(a5) + 2030: 0685 addi a3,a3,1 + 2032: d394 sw a3,32(a5) + 2034: 46f1 li a3,28 + 2036: 02d59363 bne a1,a3,205c + 203a: 8522 mv a0,s0 + 203c: aa1fe0ef jal ra,adc + 2040: 0000b5b7 lui a1,0xb + 2044: 0000c537 lui a0,0xc + 2048: 0e048613 addi a2,s1,224 + 204c: 66058593 addi a1,a1,1632 # b660 <_exit+0x208> + 2050: 13850513 addi a0,a0,312 # c138 <_exit+0xce0> + 2054: 373070ef jal ra,9bc6 + 2058: 9bcfe06f j 214 <__riscv_restore_0> + 205c: 02000693 li a3,32 + 2060: 00d58863 beq a1,a3,2070 + 2064: 03877713 andi a4,a4,56 + 2068: c701 beqz a4,2070 + 206a: 4721 li a4,8 + 206c: 00e59c63 bne a1,a4,2084 + 2070: 0000c537 lui a0,0xc + 2074: 12450513 addi a0,a0,292 # c124 <_exit+0xccc> + 2078: 34f070ef jal ra,9bc6 + 207c: 8522 mv a0,s0 + 207e: c33ff0ef jal ra,1cb0 + 2082: bf7d j 2040 + 2084: 4731 li a4,12 + 2086: fae58de3 beq a1,a4,2040 + 208a: 4741 li a4,16 + 208c: 00e59663 bne a1,a4,2098 + 2090: 8522 mv a0,s0 + 2092: f56fe0ef jal ra,7e8 + 2096: b76d j 2040 + 2098: fec58713 addi a4,a1,-20 + 209c: 0f877713 andi a4,a4,248 + 20a0: e701 bnez a4,20a8 + 20a2: 8522 mv a0,s0 + 20a4: 35a1 jal 1eec + 20a6: bf69 j 2040 + 20a8: fdc58713 addi a4,a1,-36 + 20ac: 0f877713 andi a4,a4,248 + 20b0: db41 beqz a4,2040 + 20b2: 02c00713 li a4,44 + 20b6: 00e59a63 bne a1,a4,20ca + 20ba: 305c lbu a5,5(s0) + 20bc: e781 bnez a5,20c4 + 20be: 8522 mv a0,s0 + 20c0: d9dfe0ef jal ra,e5c + 20c4: 57fd li a5,-1 + 20c6: a01c sb a5,0(s0) + 20c8: bfa5 j 2040 + 20ca: 03c00713 li a4,60 + 20ce: f6e589e3 beq a1,a4,2040 + 20d2: c790 sw a2,8(a5) + 20d4: b7b5 j 2040 + 20d6: 53d4 lw a3,36(a5) + 20d8: 0685 addi a3,a3,1 + 20da: d3d4 sw a3,36(a5) + 20dc: bfa1 j 2034 + +000020de : + 20de: 8eafe2ef jal t0,1c8 <__riscv_save_10> + 20e2: 1141 addi sp,sp,-16 + 20e4: 84aa mv s1,a0 + 20e6: 842e mv s0,a1 + 20e8: 8932 mv s2,a2 + 20ea: 89b6 mv s3,a3 + 20ec: 6c8060ef jal ra,87b4 + 20f0: 8909 andi a0,a0,2 + 20f2: 18050263 beqz a0,2276 + 20f6: 3ff00513 li a0,1023 + 20fa: 34a060ef jal ra,8444 + 20fe: 00b10513 addi a0,sp,11 + 2102: 00a10593 addi a1,sp,10 + 2106: 00010523 sb zero,10(sp) + 210a: 000105a3 sb zero,11(sp) + 210e: 6c4060ef jal ra,87d2 + 2112: 859c lbu a5,11(sp) + 2114: 4501 li a0,0 + 2116: 10078163 beqz a5,2218 + 211a: 864e mv a2,s3 + 211c: 85ca mv a1,s2 + 211e: 8522 mv a0,s0 + 2120: 3ce060ef jal ra,84ee + 2124: 10400613 li a2,260 + 2128: 4581 li a1,0 + 212a: 8526 mv a0,s1 + 212c: 8f4fe0ef jal ra,220 + 2130: 0000c5b7 lui a1,0xc + 2134: 6505 lui a0,0x1 + 2136: 4605 li a2,1 + 2138: 29458593 addi a1,a1,660 # c294 <_exit+0xe3c> + 213c: 38850513 addi a0,a0,904 # 1388 + 2140: 283050ef jal ra,7bc2 + 2144: 47f9 li a5,30 + 2146: 865c sb a5,12(sp) + 2148: 851c lbu a5,10(sp) + 214a: 40011537 lui a0,0x40011 + 214e: 4601 li a2,0 + 2150: 45c1 li a1,16 + 2152: 80050513 addi a0,a0,-2048 # 40010800 <_eusrstack+0x20008800> + 2156: 6ab1 lui s5,0xc + 2158: 86dc sb a5,13(sp) + 215a: 00010723 sb zero,14(sp) + 215e: 4901 li s2,0 + 2160: 561060ef jal ra,8ec0 + 2164: 4401 li s0,0 + 2166: 4a01 li s4,0 + 2168: 4c81 li s9,0 + 216a: 4981 li s3,0 + 216c: 4c11 li s8,4 + 216e: 154a8a93 addi s5,s5,340 # c154 <_exit+0xcfc> + 2172: 04000b13 li s6,64 + 2176: 081c addi a5,sp,16 + 2178: 97ca add a5,a5,s2 + 217a: ffc7cd03 lbu s10,-4(a5) + 217e: 4b8d li s7,3 + 2180: a031 j 218c + 2182: 4789 li a5,2 + 2184: 0ff00d13 li s10,255 + 2188: ff27f7e3 bgeu a5,s2,2176 + 218c: 4589 li a1,2 + 218e: 40013537 lui a0,0x40013 + 2192: 1e0070ef jal ra,9372 + 2196: d97d beqz a0,218c + 2198: 85ea mv a1,s10 + 219a: 40013537 lui a0,0x40013 + 219e: 1cc070ef jal ra,936a + 21a2: 4585 li a1,1 + 21a4: 40013537 lui a0,0x40013 + 21a8: 1ca070ef jal ra,9372 + 21ac: d97d beqz a0,21a2 + 21ae: 40013537 lui a0,0x40013 + 21b2: 1bc070ef jal ra,936e + 21b6: 4789 li a5,2 + 21b8: 0327f363 bgeu a5,s2,21de + 21bc: 0ff57513 andi a0,a0,255 + 21c0: 008c6f63 bltu s8,s0,21de + 21c4: 00241793 slli a5,s0,0x2 + 21c8: 97d6 add a5,a5,s5 + 21ca: 439c lw a5,0(a5) + 21cc: 8782 jr a5 + 21ce: a088 sb a0,0(s1) + 21d0: 890d andi a0,a0,3 + 21d2: 4405 li s0,1 + 21d4: 01750563 beq a0,s7,21de + 21d8: 00a03433 snez s0,a0 + 21dc: 0405 addi s0,s0,1 + 21de: 859c lbu a5,11(sp) + 21e0: 0905 addi s2,s2,1 + 21e2: 0942 slli s2,s2,0x10 + 21e4: 01095913 srli s2,s2,0x10 + 21e8: 078d addi a5,a5,3 + 21ea: f8f96ce3 bltu s2,a5,2182 + 21ee: 40011537 lui a0,0x40011 + 21f2: 4605 li a2,1 + 21f4: 45c1 li a1,16 + 21f6: 80050513 addi a0,a0,-2048 # 40010800 <_eusrstack+0x20008800> + 21fa: 0534a423 sw s3,72(s1) + 21fe: 4c3060ef jal ra,8ec0 + 2202: 0000c5b7 lui a1,0xc + 2206: 6505 lui a0,0x1 + 2208: 4601 li a2,0 + 220a: 2a858593 addi a1,a1,680 # c2a8 <_exit+0xe50> + 220e: 38850513 addi a0,a0,904 # 1388 + 2212: 1b1050ef jal ra,7bc2 + 2216: 8588 lbu a0,11(sp) + 2218: 0141 addi sp,sp,16 + 221a: fe7fd06f j 200 <__riscv_restore_10> + 221e: 001a0793 addi a5,s4,1 + 2222: 9a26 add s4,s4,s1 + 2224: 00aa00a3 sb a0,1(s4) + 2228: 0ff7fa13 andi s4,a5,255 + 222c: fb4bf9e3 bgeu s7,s4,21de + 2230: 4409 li s0,2 + 2232: b775 j 21de + 2234: b0c8 sb a0,5(s1) + 2236: 00ab7763 bgeu s6,a0,2244 + 223a: 016482a3 sb s6,5(s1) + 223e: 440d li s0,3 + 2240: 4c81 li s9,0 + 2242: bf71 j 21de + 2244: 4c81 li s9,0 + 2246: fd65 bnez a0,223e + 2248: 4411 li s0,4 + 224a: bf51 j 21de + 224c: 001c8713 addi a4,s9,1 + 2250: 9ca6 add s9,s9,s1 + 2252: 00ac8323 sb a0,6(s9) + 2256: 30dc lbu a5,5(s1) + 2258: 0ff77c93 andi s9,a4,255 + 225c: f8fce1e3 bltu s9,a5,21de + 2260: b7e5 j 2248 + 2262: 00198793 addi a5,s3,1 + 2266: 99a6 add s3,s3,s1 + 2268: 04a98623 sb a0,76(s3) + 226c: 01079993 slli s3,a5,0x10 + 2270: 0109d993 srli s3,s3,0x10 + 2274: b7ad j 21de + 2276: 4501 li a0,0 + 2278: b745 j 2218 + +0000227a : + 227a: f77fd2ef jal t0,1f0 <__riscv_save_0> + 227e: 211c lbu a5,0(a0) + 2280: 4709 li a4,2 + 2282: 1141 addi sp,sp,-16 + 2284: 8b8d andi a5,a5,3 + 2286: 842a mv s0,a0 + 2288: 0ae78b63 beq a5,a4,233e + 228c: 470d li a4,3 + 228e: 0ae78d63 beq a5,a4,2348 + 2292: 4705 li a4,1 + 2294: 0ae78063 beq a5,a4,2334 + 2298: 0000c537 lui a0,0xc + 229c: 2b850513 addi a0,a0,696 # c2b8 <_exit+0xe60> + 22a0: 127070ef jal ra,9bc6 + 22a4: 0000c537 lui a0,0xc + 22a8: 2ec50513 addi a0,a0,748 # c2ec <_exit+0xe94> + 22ac: 11b070ef jal ra,9bc6 + 22b0: 201c lbu a5,0(s0) + 22b2: 4761 li a4,24 + 22b4: 03c7f793 andi a5,a5,60 + 22b8: 12e78963 beq a5,a4,23ea + 22bc: 0af76963 bltu a4,a5,236e + 22c0: 4721 li a4,8 + 22c2: 10e78563 beq a5,a4,23cc + 22c6: 08f76663 bltu a4,a5,2352 + 22ca: c7ed beqz a5,23b4 + 22cc: 4711 li a4,4 + 22ce: 0ee78a63 beq a5,a4,23c2 + 22d2: 201c lbu a5,0(s0) + 22d4: 0000c537 lui a0,0xc + 22d8: 006c addi a1,sp,12 + 22da: 8399 srli a5,a5,0x6 + 22dc: 03078793 addi a5,a5,48 + 22e0: 38450513 addi a0,a0,900 # c384 <_exit+0xf2c> + 22e4: 865c sb a5,12(sp) + 22e6: 000106a3 sb zero,13(sp) + 22ea: 0dd070ef jal ra,9bc6 + 22ee: 201c lbu a5,0(s0) + 22f0: 470d li a4,3 + 22f2: 8b8d andi a5,a5,3 + 22f4: 00e78363 beq a5,a4,22fa + 22f8: eb99 bnez a5,230e + 22fa: 00345603 lhu a2,3(s0) + 22fe: 00145583 lhu a1,1(s0) + 2302: 0000c537 lui a0,0xc + 2306: 3a050513 addi a0,a0,928 # c3a0 <_exit+0xf48> + 230a: 0bd070ef jal ra,9bc6 + 230e: 304c lbu a1,5(s0) + 2310: 0000c537 lui a0,0xc + 2314: 3b850513 addi a0,a0,952 # c3b8 <_exit+0xf60> + 2318: 0af070ef jal ra,9bc6 + 231c: 4481 li s1,0 + 231e: 0000c937 lui s2,0xc + 2322: 305c lbu a5,5(s0) + 2324: 0ef4ec63 bltu s1,a5,241c + 2328: 4529 li a0,10 + 232a: 0df070ef jal ra,9c08 + 232e: 0141 addi sp,sp,16 + 2330: ee5fd06f j 214 <__riscv_restore_0> + 2334: 0000c537 lui a0,0xc + 2338: 2c850513 addi a0,a0,712 # c2c8 <_exit+0xe70> + 233c: b795 j 22a0 + 233e: 0000c537 lui a0,0xc + 2342: 2d050513 addi a0,a0,720 # c2d0 <_exit+0xe78> + 2346: bfa9 j 22a0 + 2348: 0000c537 lui a0,0xc + 234c: 2d850513 addi a0,a0,728 # c2d8 <_exit+0xe80> + 2350: bf81 j 22a0 + 2352: 4741 li a4,16 + 2354: 08e78163 beq a5,a4,23d6 + 2358: 4751 li a4,20 + 235a: 08e78363 beq a5,a4,23e0 + 235e: 4731 li a4,12 + 2360: f6e799e3 bne a5,a4,22d2 + 2364: 0000c537 lui a0,0xc + 2368: 32450513 addi a0,a0,804 # c324 <_exit+0xecc> + 236c: a881 j 23bc + 236e: 02400713 li a4,36 + 2372: 08e78663 beq a5,a4,23fe + 2376: 00f76e63 bltu a4,a5,2392 + 237a: 4771 li a4,28 + 237c: 06e78c63 beq a5,a4,23f4 + 2380: 02000713 li a4,32 + 2384: f4e797e3 bne a5,a4,22d2 + 2388: 0000c537 lui a0,0xc + 238c: 35c50513 addi a0,a0,860 # c35c <_exit+0xf04> + 2390: a035 j 23bc + 2392: 02c00713 li a4,44 + 2396: 06e78963 beq a5,a4,2408 + 239a: 03c00713 li a4,60 + 239e: 06e78a63 beq a5,a4,2412 + 23a2: 02800713 li a4,40 + 23a6: f2e796e3 bne a5,a4,22d2 + 23aa: 0000c537 lui a0,0xc + 23ae: 36c50513 addi a0,a0,876 # c36c <_exit+0xf14> + 23b2: a029 j 23bc + 23b4: 0000c537 lui a0,0xc + 23b8: 30050513 addi a0,a0,768 # c300 <_exit+0xea8> + 23bc: 00b070ef jal ra,9bc6 + 23c0: bf09 j 22d2 + 23c2: 0000c537 lui a0,0xc + 23c6: 30850513 addi a0,a0,776 # c308 <_exit+0xeb0> + 23ca: bfcd j 23bc + 23cc: 0000c537 lui a0,0xc + 23d0: 31450513 addi a0,a0,788 # c314 <_exit+0xebc> + 23d4: b7e5 j 23bc + 23d6: 0000c537 lui a0,0xc + 23da: c4c50513 addi a0,a0,-948 # bc4c <_exit+0x7f4> + 23de: bff9 j 23bc + 23e0: 0000c537 lui a0,0xc + 23e4: 33450513 addi a0,a0,820 # c334 <_exit+0xedc> + 23e8: bfd1 j 23bc + 23ea: 0000c537 lui a0,0xc + 23ee: 34050513 addi a0,a0,832 # c340 <_exit+0xee8> + 23f2: b7e9 j 23bc + 23f4: 0000c537 lui a0,0xc + 23f8: 34c50513 addi a0,a0,844 # c34c <_exit+0xef4> + 23fc: b7c1 j 23bc + 23fe: 0000c537 lui a0,0xc + 2402: 36450513 addi a0,a0,868 # c364 <_exit+0xf0c> + 2406: bf5d j 23bc + 2408: 0000c537 lui a0,0xc + 240c: 37850513 addi a0,a0,888 # c378 <_exit+0xf20> + 2410: b775 j 23bc + 2412: 0000c537 lui a0,0xc + 2416: 38050513 addi a0,a0,896 # c380 <_exit+0xf28> + 241a: b74d j 23bc + 241c: 009407b3 add a5,s0,s1 + 2420: 23f0 lbu a2,6(a5) + 2422: 85a6 mv a1,s1 + 2424: 3d090513 addi a0,s2,976 # c3d0 <_exit+0xf78> + 2428: 0485 addi s1,s1,1 + 242a: 79c070ef jal ra,9bc6 + 242e: 0ff4f493 andi s1,s1,255 + 2432: bdc5 j 2322 + +00002434 : + 2434: dbdfd2ef jal t0,1f0 <__riscv_save_0> + 2438: 7159 addi sp,sp,-112 + 243a: 842a mv s0,a0 + 243c: 0028 addi a0,sp,8 + 243e: 84ae mv s1,a1 + 2440: 23d040ef jal ra,6e7c + 2444: 4430 lw a2,72(s0) + 2446: 04c40593 addi a1,s0,76 + 244a: 0028 addi a0,sp,8 + 244c: 299040ef jal ra,6ee4 + 2450: 0028 addi a0,sp,8 + 2452: 85a6 mv a1,s1 + 2454: 3b9040ef jal ra,700c + 2458: 6165 addi sp,sp,112 + 245a: dbbfd06f j 214 <__riscv_restore_0> + +0000245e : + 245e: d93fd2ef jal t0,1f0 <__riscv_save_0> + 2462: 81818413 addi s0,gp,-2024 # 20000208 <_edata> + 2466: 2004 lbu s1,0(s0) + 2468: 02100793 li a5,33 + 246c: 02f487b3 mul a5,s1,a5 + 2470: 84418493 addi s1,gp,-1980 # 20000234 + 2474: 94be add s1,s1,a5 + 2476: 85a6 mv a1,s1 + 2478: 3f75 jal 2434 + 247a: 4785 li a5,1 + 247c: 02f48023 sb a5,32(s1) + 2480: 201c lbu a5,0(s0) + 2482: 471d li a4,7 + 2484: 0785 addi a5,a5,1 + 2486: 0ff7f793 andi a5,a5,255 + 248a: 00f76563 bltu a4,a5,2494 + 248e: a01c sb a5,0(s0) + 2490: d85fd06f j 214 <__riscv_restore_0> + 2494: 00040023 sb zero,0(s0) + 2498: bfe5 j 2490 + +0000249a : + 249a: d27fd2ef jal t0,1c0 <__riscv_save_12> + 249e: 1101 addi sp,sp,-32 + 24a0: 84aa mv s1,a0 + 24a2: 3f75 jal 245e + 24a4: 209c lbu a5,0(s1) + 24a6: 470d li a4,3 + 24a8: 4419 li s0,6 + 24aa: 8b8d andi a5,a5,3 + 24ac: 00e78463 beq a5,a4,24b4 + 24b0: c391 beqz a5,24b4 + 24b2: 4409 li s0,2 + 24b4: 30d8 lbu a4,5(s1) + 24b6: 44bc lw a5,72(s1) + 24b8: 97ba add a5,a5,a4 + 24ba: 943e add s0,s0,a5 + 24bc: 0442 slli s0,s0,0x10 + 24be: 8041 srli s0,s0,0x10 + 24c0: 0ff00793 li a5,255 + 24c4: 0287f163 bgeu a5,s0,24e6 + 24c8: 0000c637 lui a2,0xc + 24cc: 0000c5b7 lui a1,0xc + 24d0: 0000c537 lui a0,0xc + 24d4: 86a2 mv a3,s0 + 24d6: 17c60613 addi a2,a2,380 # c17c <_exit+0xd24> + 24da: 18858593 addi a1,a1,392 # c188 <_exit+0xd30> + 24de: 18c50513 addi a0,a0,396 # c18c <_exit+0xd34> + 24e2: 6e4070ef jal ra,9bc6 + 24e6: 82f18783 lb a5,-2001(gp) # 2000021f + 24ea: 12079563 bnez a5,2614 + 24ee: 4785 li a5,1 + 24f0: 82f187a3 sb a5,-2001(gp) # 2000021f + 24f4: 82818793 addi a5,gp,-2008 # 20000218 + 24f8: 23b8 lbu a4,2(a5) + 24fa: e311 bnez a4,24fe + 24fc: b3a0 sb s0,3(a5) + 24fe: 4619 li a2,6 + 2500: 82818593 addi a1,gp,-2008 # 20000218 + 2504: 08c00513 li a0,140 + 2508: 279050ef jal ra,7f80 + 250c: 3ff00513 li a0,1023 + 2510: 735050ef jal ra,8444 + 2514: 0000c5b7 lui a1,0xc + 2518: 6505 lui a0,0x1 + 251a: 4605 li a2,1 + 251c: 1b058593 addi a1,a1,432 # c1b0 <_exit+0xd58> + 2520: 38850513 addi a0,a0,904 # 1388 + 2524: 69e050ef jal ra,7bc2 + 2528: 40011537 lui a0,0x40011 + 252c: 47b9 li a5,14 + 252e: 4601 li a2,0 + 2530: 45c1 li a1,16 + 2532: 80050513 addi a0,a0,-2048 # 40010800 <_eusrstack+0x20008800> + 2536: 86fc sh a5,28(sp) + 2538: 189060ef jal ra,8ec0 + 253c: 00240793 addi a5,s0,2 + 2540: 6c31 lui s8,0xc + 2542: 4981 li s3,0 + 2544: 4a81 li s5,0 + 2546: 4901 li s2,0 + 2548: 4d01 li s10,0 + 254a: 4b81 li s7,0 + 254c: 4a01 li s4,0 + 254e: c43e sw a5,8(sp) + 2550: 4d91 li s11,4 + 2552: 168c0c13 addi s8,s8,360 # c168 <_exit+0xd10> + 2556: 4c8d li s9,3 + 2558: 47a2 lw a5,8(sp) + 255a: 0cf9c563 blt s3,a5,2624 + 255e: 40011537 lui a0,0x40011 + 2562: 4605 li a2,1 + 2564: 45c1 li a1,16 + 2566: 80050513 addi a0,a0,-2048 # 40010800 <_eusrstack+0x20008800> + 256a: 157060ef jal ra,8ec0 + 256e: 6985 lui s3,0x1 + 2570: 0000c5b7 lui a1,0xc + 2574: 4601 li a2,0 + 2576: 1c458593 addi a1,a1,452 # c1c4 <_exit+0xd6c> + 257a: 38898513 addi a0,s3,904 # 1388 + 257e: 644050ef jal ra,7bc2 + 2582: 0004c803 lbu a6,0(s1) + 2586: 30d8 lbu a4,5(s1) + 2588: 44b4 lw a3,72(s1) + 258a: 0000c937 lui s2,0xc + 258e: 0000b4b7 lui s1,0xb + 2592: 0000c537 lui a0,0xc + 2596: 87a2 mv a5,s0 + 2598: 17c90613 addi a2,s2,380 # c17c <_exit+0xd24> + 259c: 66048593 addi a1,s1,1632 # b660 <_exit+0x208> + 25a0: 1d450513 addi a0,a0,468 # c1d4 <_exit+0xd7c> + 25a4: 622070ef jal ra,9bc6 + 25a8: 0000c537 lui a0,0xc + 25ac: 8722 mv a4,s0 + 25ae: 86d2 mv a3,s4 + 25b0: 17c90613 addi a2,s2,380 + 25b4: 66048593 addi a1,s1,1632 + 25b8: 21850513 addi a0,a0,536 # c218 <_exit+0xdc0> + 25bc: 60a070ef jal ra,9bc6 + 25c0: bb898513 addi a0,s3,-1096 + 25c4: 0d8060ef jal ra,869c + 25c8: 0000c537 lui a0,0xc + 25cc: 17c90613 addi a2,s2,380 + 25d0: 66048593 addi a1,s1,1632 + 25d4: 24850513 addi a0,a0,584 # c248 <_exit+0xdf0> + 25d8: 5ee070ef jal ra,9bc6 + 25dc: 1d8060ef jal ra,87b4 + 25e0: 842a mv s0,a0 + 25e2: 0000ca37 lui s4,0xc + 25e6: 20147793 andi a5,s0,513 + 25ea: 0e078b63 beqz a5,26e0 + 25ee: 0000c537 lui a0,0xc + 25f2: 17c90613 addi a2,s2,380 + 25f6: 66048593 addi a1,s1,1632 + 25fa: 27c50513 addi a0,a0,636 # c27c <_exit+0xe24> + 25fe: 5c8070ef jal ra,9bc6 + 2602: 01000537 lui a0,0x1000 + 2606: 157d addi a0,a0,-1 + 2608: 8805 andi s0,s0,1 + 260a: 820187a3 sb zero,-2001(gp) # 2000021f + 260e: 73f050ef jal ra,854c + 2612: e411 bnez s0,261e + 2614: 8301a783 lw a5,-2000(gp) # 20000220 + 2618: 0785 addi a5,a5,1 + 261a: 82f1a823 sw a5,-2000(gp) # 20000220 + 261e: 6105 addi sp,sp,32 + 2620: bddfd06f j 1fc <__riscv_restore_12> + 2624: 4785 li a5,1 + 2626: 0537e463 bltu a5,s3,266e + 262a: 101c addi a5,sp,32 + 262c: 01378733 add a4,a5,s3 + 2630: ffc74703 lbu a4,-4(a4) + 2634: 4589 li a1,2 + 2636: 40013537 lui a0,0x40013 + 263a: c63a sw a4,12(sp) + 263c: 537060ef jal ra,9372 + 2640: 4732 lw a4,12(sp) + 2642: d96d beqz a0,2634 + 2644: 85ba mv a1,a4 + 2646: 40013537 lui a0,0x40013 + 264a: 0a05 addi s4,s4,1 + 264c: 51f060ef jal ra,936a + 2650: 4585 li a1,1 + 2652: 40013537 lui a0,0x40013 + 2656: 51d060ef jal ra,9372 + 265a: d97d beqz a0,2650 + 265c: 0985 addi s3,s3,1 + 265e: 40013537 lui a0,0x40013 + 2662: 09c2 slli s3,s3,0x10 + 2664: 50b060ef jal ra,936e + 2668: 0109d993 srli s3,s3,0x10 + 266c: b5f5 j 2558 + 266e: 0ff00713 li a4,255 + 2672: fdade1e3 bltu s11,s10,2634 + 2676: 002d1713 slli a4,s10,0x2 + 267a: 9762 add a4,a4,s8 + 267c: 4318 lw a4,0(a4) + 267e: 8702 jr a4 + 2680: 2098 lbu a4,0(s1) + 2682: 00377793 andi a5,a4,3 + 2686: 01978463 beq a5,s9,268e + 268a: 4d09 li s10,2 + 268c: e391 bnez a5,2690 + 268e: 4d05 li s10,1 + 2690: 4a01 li s4,0 + 2692: b74d j 2634 + 2694: 001a8693 addi a3,s5,1 + 2698: 9aa6 add s5,s5,s1 + 269a: 001ac703 lbu a4,1(s5) + 269e: 0ff6fa93 andi s5,a3,255 + 26a2: f95cf9e3 bgeu s9,s5,2634 + 26a6: 4d09 li s10,2 + 26a8: b771 j 2634 + 26aa: 30d8 lbu a4,5(s1) + 26ac: 4901 li s2,0 + 26ae: 4d0d li s10,3 + 26b0: f351 bnez a4,2634 + 26b2: 4d11 li s10,4 + 26b4: b741 j 2634 + 26b6: 30d4 lbu a3,5(s1) + 26b8: 00190613 addi a2,s2,1 + 26bc: 9926 add s2,s2,s1 + 26be: 00694703 lbu a4,6(s2) + 26c2: 0ff67913 andi s2,a2,255 + 26c6: f6d967e3 bltu s2,a3,2634 + 26ca: b7e5 j 26b2 + 26cc: 001b8693 addi a3,s7,1 + 26d0: 9ba6 add s7,s7,s1 + 26d2: 04cbc703 lbu a4,76(s7) + 26d6: 01069b93 slli s7,a3,0x10 + 26da: 010bdb93 srli s7,s7,0x10 + 26de: bf99 j 2634 + 26e0: 4529 li a0,10 + 26e2: 585060ef jal ra,9466 + 26e6: 0ce060ef jal ra,87b4 + 26ea: 82e18783 lb a5,-2002(gp) # 2000021e + 26ee: 842a mv s0,a0 + 26f0: ee078be3 beqz a5,25e6 + 26f4: 86aa mv a3,a0 + 26f6: 17c90613 addi a2,s2,380 + 26fa: 66048593 addi a1,s1,1632 + 26fe: 264a0513 addi a0,s4,612 # c264 <_exit+0xe0c> + 2702: 4c4070ef jal ra,9bc6 + 2706: b5c5 j 25e6 + +00002708 : + 2708: acffd2ef jal t0,1d6 <__riscv_save_4> + 270c: 1101 addi sp,sp,-32 + 270e: 858a mv a1,sp + 2710: 842a mv s0,a0 + 2712: d23ff0ef jal ra,2434 + 2716: 8181c483 lbu s1,-2024(gp) # 20000208 <_edata> + 271a: 02100793 li a5,33 + 271e: 4921 li s2,8 + 2720: 02f487b3 mul a5,s1,a5 + 2724: 84418493 addi s1,gp,-1980 # 20000234 + 2728: 94be add s1,s1,a5 + 272a: 0204c983 lbu s3,32(s1) + 272e: 00098963 beqz s3,2740 + 2732: 02000613 li a2,32 + 2736: 858a mv a1,sp + 2738: 8526 mv a0,s1 + 273a: 1f4070ef jal ra,992e + 273e: c105 beqz a0,275e + 2740: 197d addi s2,s2,-1 + 2742: 0ff97913 andi s2,s2,255 + 2746: fe0914e3 bnez s2,272e + 274a: 201c lbu a5,0(s0) + 274c: 0017f713 andi a4,a5,1 + 2750: cb1d beqz a4,2786 + 2752: 0ff00713 li a4,255 + 2756: 00e79763 bne a5,a4,2764 + 275a: 3044 lbu s1,5(s0) + 275c: e88d bnez s1,278e + 275e: 6105 addi sp,sp,32 + 2760: aabfd06f j 20a <__riscv_restore_4> + 2764: 305c lbu a5,5(s0) + 2766: 03e00713 li a4,62 + 276a: 00f76e63 bltu a4,a5,2786 + 276e: 00178713 addi a4,a5,1 + 2772: b058 sb a4,5(s0) + 2774: 20000737 lui a4,0x20000 + 2778: 3b074703 lbu a4,944(a4) # 200003b0 + 277c: 97a2 add a5,a5,s0 + 277e: 8522 mv a0,s0 + 2780: a3f8 sb a4,6(a5) + 2782: d19ff0ef jal ra,249a + 2786: 201c lbu a5,0(s0) + 2788: 8b8d andi a5,a5,3 + 278a: dbf1 beqz a5,275e + 278c: b7f9 j 275a + 278e: 200007b7 lui a5,0x20000 + 2792: 2078 lbu a4,6(s0) + 2794: 3b07c783 lbu a5,944(a5) # 200003b0 + 2798: fcf713e3 bne a4,a5,275e + 279c: 14fd addi s1,s1,-1 + 279e: 0ff4f493 andi s1,s1,255 + 27a2: b044 sb s1,5(s0) + 27a4: 8626 mv a2,s1 + 27a6: 00740593 addi a1,s0,7 + 27aa: 00640513 addi a0,s0,6 + 27ae: 256070ef jal ra,9a04 + 27b2: d4d5 beqz s1,275e + 27b4: 8522 mv a0,s0 + 27b6: ce5ff0ef jal ra,249a + 27ba: b755 j 275e + +000027bc : + 27bc: cad9 beqz a3,2852 + 27be: 715d addi sp,sp,-80 + 27c0: c2a6 sw s1,68(sp) + 27c2: 00f68493 addi s1,a3,15 + 27c6: c686 sw ra,76(sp) + 27c8: c4a2 sw s0,72(sp) + 27ca: c0ca sw s2,64(sp) + 27cc: 0880 addi s0,sp,80 + 27ce: de4e sw s3,60(sp) + 27d0: dc52 sw s4,56(sp) + 27d2: da56 sw s5,52(sp) + 27d4: d85a sw s6,48(sp) + 27d6: d65e sw s7,44(sp) + 27d8: 98c1 andi s1,s1,-16 + 27da: 40910133 sub sp,sp,s1 + 27de: 8a2a mv s4,a0 + 27e0: 8bb2 mv s7,a2 + 27e2: 8b2e mv s6,a1 + 27e4: 8626 mv a2,s1 + 27e6: 4581 li a1,0 + 27e8: 850a mv a0,sp + 27ea: 8abe mv s5,a5 + 27ec: 893a mv s2,a4 + 27ee: 89b6 mv s3,a3 + 27f0: a31fd0ef jal ra,220 + 27f4: 864e mv a2,s3 + 27f6: 85de mv a1,s7 + 27f8: 850a mv a0,sp + 27fa: 158070ef jal ra,9952 + 27fe: 00290993 addi s3,s2,2 + 2802: 874e mv a4,s3 + 2804: 86a6 mv a3,s1 + 2806: 860a mv a2,sp + 2808: 45c1 li a1,16 + 280a: 8552 mv a0,s4 + 280c: 030040ef jal ra,683c + 2810: fb040713 addi a4,s0,-80 + 2814: 86a6 mv a3,s1 + 2816: 864e mv a2,s3 + 2818: 85da mv a1,s6 + 281a: 8552 mv a0,s4 + 281c: 402040ef jal ra,6c1e + 2820: fb044783 lbu a5,-80(s0) + 2824: 0489 addi s1,s1,2 + 2826: 4501 li a0,0 + 2828: 00f90023 sb a5,0(s2) + 282c: fb144783 lbu a5,-79(s0) + 2830: 00f900a3 sb a5,1(s2) + 2834: 009aa023 sw s1,0(s5) + 2838: fb040113 addi sp,s0,-80 + 283c: 40b6 lw ra,76(sp) + 283e: 4426 lw s0,72(sp) + 2840: 4496 lw s1,68(sp) + 2842: 4906 lw s2,64(sp) + 2844: 59f2 lw s3,60(sp) + 2846: 5a62 lw s4,56(sp) + 2848: 5ad2 lw s5,52(sp) + 284a: 5b42 lw s6,48(sp) + 284c: 5bb2 lw s7,44(sp) + 284e: 6161 addi sp,sp,80 + 2850: 8082 ret + 2852: 557d li a0,-1 + 2854: 8082 ret + +00002856 : + 2856: 4809 li a6,2 + 2858: 04d87663 bgeu a6,a3,28a4 + 285c: 97bfd2ef jal t0,1d6 <__riscv_save_4> + 2860: ffe68413 addi s0,a3,-2 + 2864: 00f47693 andi a3,s0,15 + 2868: 1101 addi sp,sp,-32 + 286a: 00260a13 addi s4,a2,2 + 286e: c689 beqz a3,2878 + 2870: 5579 li a0,-2 + 2872: 6105 addi sp,sp,32 + 2874: 997fd06f j 20a <__riscv_restore_4> + 2878: 84b2 mv s1,a2 + 287a: 89ba mv s3,a4 + 287c: 8652 mv a2,s4 + 287e: 870a mv a4,sp + 2880: 86a2 mv a3,s0 + 2882: 892a mv s2,a0 + 2884: 39a040ef jal ra,6c1e + 2888: 4609 li a2,2 + 288a: 858a mv a1,sp + 288c: 8526 mv a0,s1 + 288e: 0a0070ef jal ra,992e + 2892: fd79 bnez a0,2870 + 2894: 874e mv a4,s3 + 2896: 86a2 mv a3,s0 + 2898: 8652 mv a2,s4 + 289a: 45c1 li a1,16 + 289c: 854a mv a0,s2 + 289e: 7e3030ef jal ra,6880 + 28a2: bfc1 j 2872 + 28a4: 557d li a0,-1 + 28a6: 8082 ret + +000028a8 : + 28a8: 949fd2ef jal t0,1f0 <__riscv_save_0> + 28ac: 1141 addi sp,sp,-16 + 28ae: c402 sw zero,8(sp) + 28b0: 47cd li a5,19 + 28b2: 845c sb a5,8(sp) + 28b4: 0028 addi a0,sp,8 + 28b6: 4785 li a5,1 + 28b8: c63e sw a5,12(sp) + 28ba: 616060ef jal ra,8ed0 + 28be: 0141 addi sp,sp,16 + 28c0: 955fd06f j 214 <__riscv_restore_0> + +000028c4 : + 28c4: 00357793 andi a5,a0,3 + 28c8: ef99 bnez a5,28e6 + 28ca: 06400713 li a4,100 + 28ce: 02e57733 remu a4,a0,a4 + 28d2: 4785 li a5,1 + 28d4: e719 bnez a4,28e2 + 28d6: 19000793 li a5,400 + 28da: 02f57533 remu a0,a0,a5 + 28de: 00153793 seqz a5,a0 + 28e2: 853e mv a0,a5 + 28e4: 8082 ret + 28e6: 4781 li a5,0 + 28e8: bfed j 28e2 + +000028ea : + 28ea: 84e50813 addi a6,a0,-1970 # 4001284e <_eusrstack+0x2000a84e> + 28ee: 0842 slli a6,a6,0x10 + 28f0: 01085813 srli a6,a6,0x10 + 28f4: 08100893 li a7,129 + 28f8: 0d08e563 bltu a7,a6,29c2 + 28fc: 8c5fd2ef jal t0,1c0 <__riscv_save_12> + 2900: 01e13c37 lui s8,0x1e13 + 2904: 01e28cb7 lui s9,0x1e28 + 2908: 8b3e mv s6,a5 + 290a: 843a mv s0,a4 + 290c: 8ab6 mv s5,a3 + 290e: 8932 mv s2,a2 + 2910: 89ae mv s3,a1 + 2912: 8baa mv s7,a0 + 2914: 4481 li s1,0 + 2916: 7b200a13 li s4,1970 + 291a: 380c0c13 addi s8,s8,896 # 1e13380 <_data_lma+0x1e05124> + 291e: 500c8c93 addi s9,s9,1280 # 1e28500 <_data_lma+0x1e1a2a4> + 2922: 074b9663 bne s7,s4,298e + 2926: 19fd addi s3,s3,-1 + 2928: 6cb1 lui s9,0xc + 292a: 6c55 lui s8,0x15 + 292c: 4a01 li s4,0 + 292e: 0ff9f993 andi s3,s3,255 + 2932: 3e4c8c93 addi s9,s9,996 # c3e4 + 2936: 180c0c13 addi s8,s8,384 # 15180 <_data_lma+0x6f24> + 293a: 4d85 li s11,1 + 293c: 010a1d13 slli s10,s4,0x10 + 2940: 010d5d13 srli s10,s10,0x10 + 2944: 073d6063 bltu s10,s3,29a4 + 2948: 03c00713 li a4,60 + 294c: 6685 lui a3,0x1 + 294e: 02e40433 mul s0,s0,a4 + 2952: e1068693 addi a3,a3,-496 # e10 + 2956: 6655 lui a2,0x15 + 2958: 18060613 addi a2,a2,384 # 15180 <_data_lma+0x6f24> + 295c: 197d addi s2,s2,-1 + 295e: 4585 li a1,1 + 2960: 18000537 lui a0,0x18000 + 2964: 02da8ab3 mul s5,s5,a3 + 2968: 945a add s0,s0,s6 + 296a: 02c90933 mul s2,s2,a2 + 296e: 9456 add s0,s0,s5 + 2970: 7cc060ef jal ra,913c + 2974: 4505 li a0,1 + 2976: 5b6060ef jal ra,8f2c + 297a: 944a add s0,s0,s2 + 297c: 9426 add s0,s0,s1 + 297e: 8522 mv a0,s0 + 2980: 0e5060ef jal ra,9264 + 2984: 13b060ef jal ra,92be + 2988: 4501 li a0,0 + 298a: 873fd06f j 1fc <__riscv_restore_12> + 298e: 8552 mv a0,s4 + 2990: 3f15 jal 28c4 + 2992: c519 beqz a0,29a0 + 2994: 94e6 add s1,s1,s9 + 2996: 0a05 addi s4,s4,1 + 2998: 0a42 slli s4,s4,0x10 + 299a: 010a5a13 srli s4,s4,0x10 + 299e: b751 j 2922 + 29a0: 94e2 add s1,s1,s8 + 29a2: bfd5 j 2996 + 29a4: 014c87b3 add a5,s9,s4 + 29a8: 239c lbu a5,0(a5) + 29aa: 855e mv a0,s7 + 29ac: 038787b3 mul a5,a5,s8 + 29b0: 94be add s1,s1,a5 + 29b2: f13ff0ef jal ra,28c4 + 29b6: c501 beqz a0,29be + 29b8: 01bd1363 bne s10,s11,29be + 29bc: 94e2 add s1,s1,s8 + 29be: 0a05 addi s4,s4,1 + 29c0: bfb5 j 293c + 29c2: 4505 li a0,1 + 29c4: 8082 ret + +000029c6 : + 29c6: 82bfd2ef jal t0,1f0 <__riscv_save_0> + 29ca: 67b1 lui a5,0xc + 29cc: 3f078793 addi a5,a5,1008 # c3f0 + 29d0: 4581 li a1,0 + 29d2: 04a00693 li a3,74 + 29d6: 07500613 li a2,117 + 29da: 06e00513 li a0,110 + 29de: 4731 li a4,12 + 29e0: 00078803 lb a6,0(a5) + 29e4: 0585 addi a1,a1,1 + 29e6: 02d81863 bne a6,a3,2a16 + 29ea: 00178803 lb a6,1(a5) + 29ee: 02c81463 bne a6,a2,2a16 + 29f2: 00278803 lb a6,2(a5) + 29f6: 02a81063 bne a6,a0,2a16 + 29fa: 0ff5f593 andi a1,a1,255 + 29fe: 03800793 li a5,56 + 2a02: 02800713 li a4,40 + 2a06: 46d9 li a3,22 + 2a08: 4665 li a2,25 + 2a0a: 7ea00513 li a0,2026 + 2a0e: eddff0ef jal ra,28ea + 2a12: 803fd06f j 214 <__riscv_restore_0> + 2a16: 0ff5f593 andi a1,a1,255 + 2a1a: 078d addi a5,a5,3 + 2a1c: fce592e3 bne a1,a4,29e0 + 2a20: 4581 li a1,0 + 2a22: bff1 j 29fe + +00002a24 : + 2a24: 06400713 li a4,100 + 2a28: 02e577b3 remu a5,a0,a4 + 2a2c: 02e55533 divu a0,a0,a4 + 2a30: 474d li a4,19 + 2a32: 0ff57513 andi a0,a0,255 + 2a36: 00a77463 bgeu a4,a0,2a3e + 2a3a: 06478793 addi a5,a5,100 + 2a3e: 0027d513 srli a0,a5,0x2 + 2a42: 953e add a0,a0,a5 + 2a44: 471d li a4,7 + 2a46: 02e57533 remu a0,a0,a4 + 2a4a: 6731 lui a4,0xc + 2a4c: 41870713 addi a4,a4,1048 # c418 + 2a50: 972e add a4,a4,a1 + 2a52: fff74703 lbu a4,-1(a4) + 2a56: 8b8d andi a5,a5,3 + 2a58: 963a add a2,a2,a4 + 2a5a: 962a add a2,a2,a0 + 2a5c: e799 bnez a5,2a6a + 2a5e: 4789 li a5,2 + 2a60: 00b7e563 bltu a5,a1,2a6a + 2a64: 167d addi a2,a2,-1 + 2a66: 0642 slli a2,a2,0x10 + 2a68: 8241 srli a2,a2,0x10 + 2a6a: 451d li a0,7 + 2a6c: 02a67533 remu a0,a2,a0 + 2a70: 8082 ret + +00002a72 : + 2a72: f56fd2ef jal t0,1c8 <__riscv_save_10> + 2a76: 6455 lui s0,0x15 + 2a78: 792060ef jal ra,920a + 2a7c: 18040413 addi s0,s0,384 # 15180 <_data_lma+0x6f24> + 2a80: 02855433 divu s0,a0,s0 + 2a84: 82018793 addi a5,gp,-2016 # 20000210 + 2a88: 239a lhu a4,0(a5) + 2a8a: 84aa mv s1,a0 + 2a8c: 04870563 beq a4,s0,2ad6 + 2a90: a382 sh s0,0(a5) + 2a92: 7b200993 li s3,1970 + 2a96: 16c00913 li s2,364 + 2a9a: 16d00a13 li s4,365 + 2a9e: 08896063 bltu s2,s0,2b1e + 2aa2: 98018793 addi a5,gp,-1664 # 20000370 + 2aa6: 6ab1 lui s5,0xc + 2aa8: 01379223 sh s3,4(a5) + 2aac: 98018913 addi s2,gp,-1664 # 20000370 + 2ab0: 4981 li s3,0 + 2ab2: 4b6d li s6,27 + 2ab4: 3e4a8a93 addi s5,s5,996 # c3e4 + 2ab8: 4b85 li s7,1 + 2aba: 4c71 li s8,28 + 2abc: 00198a13 addi s4,s3,1 + 2ac0: 068b6f63 bltu s6,s0,2b3e + 2ac4: 0ffa7a13 andi s4,s4,255 + 2ac8: 0405 addi s0,s0,1 + 2aca: 01490323 sb s4,6(s2) + 2ace: 0ff47413 andi s0,s0,255 + 2ad2: 008903a3 sb s0,7(s2) + 2ad6: 67d5 lui a5,0x15 + 2ad8: 18078793 addi a5,a5,384 # 15180 <_data_lma+0x6f24> + 2adc: 02f4f4b3 remu s1,s1,a5 + 2ae0: 6785 lui a5,0x1 + 2ae2: e1078793 addi a5,a5,-496 # e10 + 2ae6: 98018413 addi s0,gp,-1664 # 20000370 + 2aea: 02f4d733 divu a4,s1,a5 + 2aee: 02f4f4b3 remu s1,s1,a5 + 2af2: 0ff77713 andi a4,a4,255 + 2af6: a018 sb a4,0(s0) + 2af8: 03c00713 li a4,60 + 2afc: 02e4d7b3 divu a5,s1,a4 + 2b00: 02e4f4b3 remu s1,s1,a4 + 2b04: 0ff7f793 andi a5,a5,255 + 2b08: b01c sb a5,1(s0) + 2b0a: a024 sb s1,2(s0) + 2b0c: 204a lhu a0,4(s0) + 2b0e: 206c lbu a1,6(s0) + 2b10: 3070 lbu a2,7(s0) + 2b12: f13ff0ef jal ra,2a24 + 2b16: a408 sb a0,8(s0) + 2b18: 4501 li a0,0 + 2b1a: ee6fd06f j 200 <__riscv_restore_10> + 2b1e: 854e mv a0,s3 + 2b20: da5ff0ef jal ra,28c4 + 2b24: c911 beqz a0,2b38 + 2b26: f7440ee3 beq s0,s4,2aa2 + 2b2a: e9240413 addi s0,s0,-366 + 2b2e: 0985 addi s3,s3,1 + 2b30: 09c2 slli s3,s3,0x10 + 2b32: 0109d993 srli s3,s3,0x10 + 2b36: b7a5 j 2a9e + 2b38: e9340413 addi s0,s0,-365 + 2b3c: bfcd j 2b2e + 2b3e: 00495503 lhu a0,4(s2) + 2b42: d83ff0ef jal ra,28c4 + 2b46: c919 beqz a0,2b5c + 2b48: 01799a63 bne s3,s7,2b5c + 2b4c: f7840ce3 beq s0,s8,2ac4 + 2b50: 140d addi s0,s0,-29 + 2b52: 010a1993 slli s3,s4,0x10 + 2b56: 0109d993 srli s3,s3,0x10 + 2b5a: b78d j 2abc + 2b5c: 99d6 add s3,s3,s5 + 2b5e: 0009c783 lbu a5,0(s3) + 2b62: f6f461e3 bltu s0,a5,2ac4 + 2b66: 8c1d sub s0,s0,a5 + 2b68: b7ed j 2b52 + +00002b6a : + 2b6a: e86fd2ef jal t0,1f0 <__riscv_save_0> + 2b6e: 4585 li a1,1 + 2b70: 18000537 lui a0,0x18000 + 2b74: 5c8060ef jal ra,913c + 2b78: 4505 li a0,1 + 2b7a: 3b2060ef jal ra,8f2c + 2b7e: 4509 li a0,2 + 2b80: 786060ef jal ra,9306 + 2b84: 4505 li a0,1 + 2b86: 780060ef jal ra,9306 + 2b8a: 236060ef jal ra,8dc0 + 2b8e: 4505 li a0,1 + 2b90: 3c4060ef jal ra,8f54 + 2b94: 4401 li s0,0 + 2b96: 0fa00493 li s1,250 + 2b9a: 04100513 li a0,65 + 2b9e: 5fa060ef jal ra,9198 + 2ba2: ed09 bnez a0,2bbc + 2ba4: 00941563 bne s0,s1,2bae + 2ba8: 4505 li a0,1 + 2baa: e6afd06f j 214 <__riscv_restore_0> + 2bae: 0405 addi s0,s0,1 + 2bb0: 4551 li a0,20 + 2bb2: 0ff47413 andi s0,s0,255 + 2bb6: 0b1060ef jal ra,9466 + 2bba: b7c5 j 2b9a + 2bbc: 0fa00793 li a5,250 + 2bc0: 4505 li a0,1 + 2bc2: fef404e3 beq s0,a5,2baa + 2bc6: 10000513 li a0,256 + 2bca: 3b2060ef jal ra,8f7c + 2bce: 4505 li a0,1 + 2bd0: 3b8060ef jal ra,8f88 + 2bd4: 6ea060ef jal ra,92be + 2bd8: 6f6060ef jal ra,92ce + 2bdc: 4581 li a1,0 + 2bde: 4505 li a0,1 + 2be0: 5e6060ef jal ra,91c6 + 2be4: 4581 li a1,0 + 2be6: 4509 li a0,2 + 2be8: 5de060ef jal ra,91c6 + 2bec: 4581 li a1,0 + 2bee: 4511 li a0,4 + 2bf0: 5d6060ef jal ra,91c6 + 2bf4: 6ca060ef jal ra,92be + 2bf8: 5e8060ef jal ra,91e0 + 2bfc: 6521 lui a0,0x8 + 2bfe: 157d addi a0,a0,-1 + 2c00: 690060ef jal ra,9290 + 2c04: 6ba060ef jal ra,92be + 2c08: dbfff0ef jal ra,29c6 + 2c0c: 5e6060ef jal ra,91f2 + 2c10: 65a9 lui a1,0xa + 2c12: 1a158593 addi a1,a1,417 # a1a1 <__ascii_wctomb+0x11> + 2c16: 4511 li a0,4 + 2c18: 1b8060ef jal ra,8dd0 + 2c1c: c8dff0ef jal ra,28a8 + 2c20: e53ff0ef jal ra,2a72 + 2c24: 4501 li a0,0 + 2c26: b751 j 2baa + +00002c28 : + 2c28: 4681 li a3,0 + 2c2a: 00c69363 bne a3,a2,2c30 + 2c2e: 8082 ret + 2c30: 219c lbu a5,0(a1) + 2c32: 3198 lbu a4,1(a1) + 2c34: 0025c883 lbu a7,2(a1) + 2c38: 07e2 slli a5,a5,0x18 + 2c3a: 0742 slli a4,a4,0x10 + 2c3c: 8fd9 or a5,a5,a4 + 2c3e: 08a2 slli a7,a7,0x8 + 2c40: 0117e7b3 or a5,a5,a7 + 2c44: 0045c883 lbu a7,4(a1) + 2c48: 31f8 lbu a4,7(a1) + 2c4a: 0035c303 lbu t1,3(a1) + 2c4e: 08e2 slli a7,a7,0x18 + 2c50: 01176733 or a4,a4,a7 + 2c54: 0055c883 lbu a7,5(a1) + 2c58: 00369813 slli a6,a3,0x3 + 2c5c: 982a add a6,a6,a0 + 2c5e: 08c2 slli a7,a7,0x10 + 2c60: 01176733 or a4,a4,a7 + 2c64: 0065c883 lbu a7,6(a1) + 2c68: 0067e7b3 or a5,a5,t1 + 2c6c: 00f82223 sw a5,4(a6) + 2c70: 08a2 slli a7,a7,0x8 + 2c72: 01176733 or a4,a4,a7 + 2c76: 00e82023 sw a4,0(a6) + 2c7a: 0685 addi a3,a3,1 + 2c7c: 05a1 addi a1,a1,8 + 2c7e: b775 j 2c2a + +00002c80 : + 2c80: 411c lw a5,0(a0) + 2c82: 7119 addi sp,sp,-128 + 2c84: dea2 sw s0,124(sp) + 2c86: c23e sw a5,4(sp) + 2c88: 415c lw a5,4(a0) + 2c8a: dca6 sw s1,120(sp) + 2c8c: daca sw s2,116(sp) + 2c8e: d43e sw a5,40(sp) + 2c90: 451c lw a5,8(a0) + 2c92: d6d2 sw s4,108(sp) + 2c94: cce6 sw s9,88(sp) + 2c96: c43e sw a5,8(sp) + 2c98: 455c lw a5,12(a0) + 2c9a: c8ee sw s11,80(sp) + 2c9c: d8ce sw s3,112(sp) + 2c9e: d63e sw a5,44(sp) + 2ca0: 491c lw a5,16(a0) + 2ca2: d4d6 sw s5,104(sp) + 2ca4: d2da sw s6,100(sp) + 2ca6: c63e sw a5,12(sp) + 2ca8: 495c lw a5,20(a0) + 2caa: d0de sw s7,96(sp) + 2cac: cee2 sw s8,92(sp) + 2cae: d83e sw a5,48(sp) + 2cb0: 4d1c lw a5,24(a0) + 2cb2: caea sw s10,84(sp) + 2cb4: 63b1 lui t2,0xc + 2cb6: c83e sw a5,16(sp) + 2cb8: 4d5c lw a5,28(a0) + 2cba: 04050913 addi s2,a0,64 # 8040 + 2cbe: da3e sw a5,52(sp) + 2cc0: 511c lw a5,32(a0) + 2cc2: ca3e sw a5,20(sp) + 2cc4: 515c lw a5,36(a0) + 2cc6: dc3e sw a5,56(sp) + 2cc8: 551c lw a5,40(a0) + 2cca: 56e2 lw a3,56(sp) + 2ccc: 4dc2 lw s11,16(sp) + 2cce: cc3e sw a5,24(sp) + 2cd0: 555c lw a5,44(a0) + 2cd2: 4f62 lw t5,24(sp) + 2cd4: 5a52 lw s4,52(sp) + 2cd6: de3e sw a5,60(sp) + 2cd8: 591c lw a5,48(a0) + 2cda: 54f2 lw s1,60(sp) + 2cdc: 48b2 lw a7,12(sp) + 2cde: ce3e sw a5,28(sp) + 2ce0: 595c lw a5,52(a0) + 2ce2: 4ef2 lw t4,28(sp) + 2ce4: 5fc2 lw t6,48(sp) + 2ce6: c0be sw a5,64(sp) + 2ce8: 5d1c lw a5,56(a0) + 2cea: 4406 lw s0,64(sp) + 2cec: 4322 lw t1,8(sp) + 2cee: d03e sw a5,32(sp) + 2cf0: 5d5c lw a5,60(a0) + 2cf2: 5e02 lw t3,32(sp) + 2cf4: 52b2 lw t0,44(sp) + 2cf6: c2be sw a5,68(sp) + 2cf8: 42838793 addi a5,t2,1064 # c428 + 2cfc: c03e sw a5,0(sp) + 2cfe: 04050793 addi a5,a0,64 + 2d02: c6be sw a5,76(sp) + 2d04: 0c050793 addi a5,a0,192 + 2d08: c4be sw a5,72(sp) + 2d0a: 4c96 lw s9,68(sp) + 2d0c: 47d2 lw a5,20(sp) + 2d0e: 4712 lw a4,4(sp) + 2d10: 5622 lw a2,40(sp) + 2d12: 42838393 addi t2,t2,1064 + 2d16: 0003aa83 lw s5,0(t2) + 2d1a: 00092583 lw a1,0(s2) + 2d1e: 00492803 lw a6,4(s2) + 2d22: 0043a983 lw s3,4(t2) + 2d26: 95d6 add a1,a1,s5 + 2d28: 0155bab3 sltu s5,a1,s5 + 2d2c: 99c2 add s3,s3,a6 + 2d2e: 9ace add s5,s5,s3 + 2d30: 01269b13 slli s6,a3,0x12 + 2d34: 00e7d993 srli s3,a5,0xe + 2d38: 013b6c33 or s8,s6,s3 + 2d3c: 00e6d813 srli a6,a3,0xe + 2d40: 01279993 slli s3,a5,0x12 + 2d44: 0109ebb3 or s7,s3,a6 + 2d48: 00e69b13 slli s6,a3,0xe + 2d4c: 0127d993 srli s3,a5,0x12 + 2d50: 013b6833 or a6,s6,s3 + 2d54: 0126db13 srli s6,a3,0x12 + 2d58: 00e79993 slli s3,a5,0xe + 2d5c: 0169e9b3 or s3,s3,s6 + 2d60: 013bc9b3 xor s3,s7,s3 + 2d64: 010c4b33 xor s6,s8,a6 + 2d68: 0097db93 srli s7,a5,0x9 + 2d6c: 01769813 slli a6,a3,0x17 + 2d70: 010bebb3 or s7,s7,a6 + 2d74: 01779c13 slli s8,a5,0x17 + 2d78: 0096d813 srli a6,a3,0x9 + 2d7c: 01886833 or a6,a6,s8 + 2d80: 010b4b33 xor s6,s6,a6 + 2d84: 0179c9b3 xor s3,s3,s7 + 2d88: 9b2e add s6,s6,a1 + 2d8a: 00bb35b3 sltu a1,s6,a1 + 2d8e: 9ace add s5,s5,s3 + 2d90: fff7cb93 not s7,a5 + 2d94: 9aae add s5,s5,a1 + 2d96: fff6c993 not s3,a3 + 2d9a: 01e7f5b3 and a1,a5,t5 + 2d9e: 01dbfbb3 and s7,s7,t4 + 2da2: 0096f833 and a6,a3,s1 + 2da6: 00bbcbb3 xor s7,s7,a1 + 2daa: 0089f9b3 and s3,s3,s0 + 2dae: 9bda add s7,s7,s6 + 2db0: 0109c9b3 xor s3,s3,a6 + 2db4: 99d6 add s3,s3,s5 + 2db6: 016bbb33 sltu s6,s7,s6 + 2dba: 9e5e add t3,t3,s7 + 2dbc: 9b4e add s6,s6,s3 + 2dbe: 017e3bb3 sltu s7,t3,s7 + 2dc2: 9cda add s9,s9,s6 + 2dc4: 01e61593 slli a1,a2,0x1e + 2dc8: 00265a93 srli s5,a2,0x2 + 2dcc: 01e71813 slli a6,a4,0x1e + 2dd0: 00275993 srli s3,a4,0x2 + 2dd4: 9cde add s9,s9,s7 + 2dd6: 00b9e9b3 or s3,s3,a1 + 2dda: 010aebb3 or s7,s5,a6 + 2dde: 00461593 slli a1,a2,0x4 + 2de2: 01c75813 srli a6,a4,0x1c + 2de6: 0105e5b3 or a1,a1,a6 + 2dea: 01c65a93 srli s5,a2,0x1c + 2dee: 00471813 slli a6,a4,0x4 + 2df2: 01586833 or a6,a6,s5 + 2df6: 0109c833 xor a6,s3,a6 + 2dfa: 00bbcab3 xor s5,s7,a1 + 2dfe: 00775993 srli s3,a4,0x7 + 2e02: 01961593 slli a1,a2,0x19 + 2e06: 00b9e9b3 or s3,s3,a1 + 2e0a: 01971b13 slli s6,a4,0x19 + 2e0e: 00765593 srli a1,a2,0x7 + 2e12: 0165e5b3 or a1,a1,s6 + 2e16: 01134b33 xor s6,t1,a7 + 2e1a: 00bac5b3 xor a1,s5,a1 + 2e1e: 013849b3 xor s3,a6,s3 + 2e22: 00eb7b33 and s6,s6,a4 + 2e26: 01f2cab3 xor s5,t0,t6 + 2e2a: 01137833 and a6,t1,a7 + 2e2e: 01f2fbb3 and s7,t0,t6 + 2e32: 010b4833 xor a6,s6,a6 + 2e36: 00cafab3 and s5,s5,a2 + 2e3a: 017acab3 xor s5,s5,s7 + 2e3e: 982e add a6,a6,a1 + 2e40: 00b835b3 sltu a1,a6,a1 + 2e44: 9ace add s5,s5,s3 + 2e46: 01558bb3 add s7,a1,s5 + 2e4a: 01be0c33 add s8,t3,s11 + 2e4e: 9872 add a6,a6,t3 + 2e50: 9a66 add s4,s4,s9 + 2e52: 01cc3b33 sltu s6,s8,t3 + 2e56: 9cde add s9,s9,s7 + 2e58: 01c83e33 sltu t3,a6,t3 + 2e5c: 019e05b3 add a1,t3,s9 + 2e60: d22e sw a1,36(sp) + 2e62: 8d2e mv s10,a1 + 2e64: 45a6 lw a1,72(sp) + 2e66: 9b52 add s6,s6,s4 + 2e68: 0921 addi s2,s2,8 + 2e6a: 89e2 mv s3,s8 + 2e6c: 8ada mv s5,s6 + 2e6e: 8bc2 mv s7,a6 + 2e70: 03a1 addi t2,t2,8 + 2e72: 8dc6 mv s11,a7 + 2e74: 8a7e mv s4,t6 + 2e76: 8e76 mv t3,t4 + 2e78: 8ca2 mv s9,s0 + 2e7a: 37259b63 bne a1,s2,31f0 + 2e7e: 4b02 lw s6,0(sp) + 2e80: 43b6 lw t2,76(sp) + 2e82: 8cf6 mv s9,t4 + 2e84: 8c22 mv s8,s0 + 2e86: 8efa mv t4,t5 + 2e88: 8426 mv s0,s1 + 2e8a: 8f3e mv t5,a5 + 2e8c: 84b6 mv s1,a3 + 2e8e: d246 sw a7,36(sp) + 2e90: c4fe sw t6,72(sp) + 2e92: 889a mv a7,t1 + 2e94: 8f96 mv t6,t0 + 2e96: 833a mv t1,a4 + 2e98: 82b2 mv t0,a2 + 2e9a: 87ce mv a5,s3 + 2e9c: 86d6 mv a3,s5 + 2e9e: 875e mv a4,s7 + 2ea0: 866a mv a2,s10 + 2ea2: 5a79 li s4,-2 + 2ea4: 00fa7593 andi a1,s4,15 + 2ea8: 05a1 addi a1,a1,8 + 2eaa: 058e slli a1,a1,0x3 + 2eac: 95aa add a1,a1,a0 + 2eae: 0005a903 lw s2,0(a1) + 2eb2: 41cc lw a1,4(a1) + 2eb4: 03a1 addi t2,t2,8 + 2eb6: 01395813 srli a6,s2,0x13 + 2eba: 00d59b93 slli s7,a1,0xd + 2ebe: 010bebb3 or s7,s7,a6 + 2ec2: 00d91a93 slli s5,s2,0xd + 2ec6: 0135d813 srli a6,a1,0x13 + 2eca: 010aeab3 or s5,s5,a6 + 2ece: 01d95993 srli s3,s2,0x1d + 2ed2: 00359813 slli a6,a1,0x3 + 2ed6: 00391e13 slli t3,s2,0x3 + 2eda: 0109e9b3 or s3,s3,a6 + 2ede: 01d5d813 srli a6,a1,0x1d + 2ee2: 01c86833 or a6,a6,t3 + 2ee6: 013ac9b3 xor s3,s5,s3 + 2eea: 00695913 srli s2,s2,0x6 + 2eee: 01a59a93 slli s5,a1,0x1a + 2ef2: 010bc833 xor a6,s7,a6 + 2ef6: 012ae933 or s2,s5,s2 + 2efa: 01284933 xor s2,a6,s2 + 2efe: ff83a803 lw a6,-8(t2) + 2f02: ffc3ae03 lw t3,-4(t2) + 2f06: 8199 srli a1,a1,0x6 + 2f08: 984a add a6,a6,s2 + 2f0a: 00b9c9b3 xor s3,s3,a1 + 2f0e: 01283933 sltu s2,a6,s2 + 2f12: 99f2 add s3,s3,t3 + 2f14: 01390e33 add t3,s2,s3 + 2f18: ff3a0913 addi s2,s4,-13 + 2f1c: 00f97913 andi s2,s2,15 + 2f20: 0921 addi s2,s2,8 + 2f22: 090e slli s2,s2,0x3 + 2f24: ff03ac23 sw a6,-8(t2) + 2f28: ffc3ae23 sw t3,-4(t2) + 2f2c: 992a add s2,s2,a0 + 2f2e: 00492983 lw s3,4(s2) + 2f32: 00092583 lw a1,0(s2) + 2f36: 0b21 addi s6,s6,8 + 2f38: 01f99d13 slli s10,s3,0x1f + 2f3c: 0015d913 srli s2,a1,0x1 + 2f40: 012d6d33 or s10,s10,s2 + 2f44: 01f59b93 slli s7,a1,0x1f + 2f48: 0019d913 srli s2,s3,0x1 + 2f4c: 012bebb3 or s7,s7,s2 + 2f50: 01899a93 slli s5,s3,0x18 + 2f54: 0085d913 srli s2,a1,0x8 + 2f58: 0089dd93 srli s11,s3,0x8 + 2f5c: 012aeab3 or s5,s5,s2 + 2f60: 01859913 slli s2,a1,0x18 + 2f64: 01b96933 or s2,s2,s11 + 2f68: 012bc933 xor s2,s7,s2 + 2f6c: 819d srli a1,a1,0x7 + 2f6e: 01999b93 slli s7,s3,0x19 + 2f72: 00bbe5b3 or a1,s7,a1 + 2f76: 015d4ab3 xor s5,s10,s5 + 2f7a: 00bacab3 xor s5,s5,a1 + 2f7e: 0079d993 srli s3,s3,0x7 + 2f82: ffba0593 addi a1,s4,-5 + 2f86: 9856 add a6,a6,s5 + 2f88: 01394933 xor s2,s2,s3 + 2f8c: 89bd andi a1,a1,15 + 2f8e: 9972 add s2,s2,t3 + 2f90: 01583ab3 sltu s5,a6,s5 + 2f94: 05a1 addi a1,a1,8 + 2f96: 9aca add s5,s5,s2 + 2f98: 058e slli a1,a1,0x3 + 2f9a: ff03ac23 sw a6,-8(t2) + 2f9e: ff53ae23 sw s5,-4(t2) + 2fa2: 95aa add a1,a1,a0 + 2fa4: 0005a903 lw s2,0(a1) + 2fa8: 41cc lw a1,4(a1) + 2faa: 01279993 slli s3,a5,0x12 + 2fae: 9942 add s2,s2,a6 + 2fb0: 9aae add s5,s5,a1 + 2fb2: 01093833 sltu a6,s2,a6 + 2fb6: 9856 add a6,a6,s5 + 2fb8: 00e7d593 srli a1,a5,0xe + 2fbc: 01269a93 slli s5,a3,0x12 + 2fc0: 00e6de13 srli t3,a3,0xe + 2fc4: 00baed33 or s10,s5,a1 + 2fc8: 01c9ebb3 or s7,s3,t3 + 2fcc: 0127d593 srli a1,a5,0x12 + 2fd0: 00e79993 slli s3,a5,0xe + 2fd4: 0126da93 srli s5,a3,0x12 + 2fd8: 00e69e13 slli t3,a3,0xe + 2fdc: 00be6e33 or t3,t3,a1 + 2fe0: 0159e5b3 or a1,s3,s5 + 2fe4: 00bbc9b3 xor s3,s7,a1 + 2fe8: 01cd4ab3 xor s5,s10,t3 + 2fec: 0097d593 srli a1,a5,0x9 + 2ff0: 01769e13 slli t3,a3,0x17 + 2ff4: 01c5e5b3 or a1,a1,t3 + 2ff8: 01779b93 slli s7,a5,0x17 + 2ffc: 0096de13 srli t3,a3,0x9 + 3000: fff7cd13 not s10,a5 + 3004: 00b9c5b3 xor a1,s3,a1 + 3008: 017e6e33 or t3,t3,s7 + 300c: 01dd7d33 and s10,s10,t4 + 3010: fff6cb93 not s7,a3 + 3014: 01e7f9b3 and s3,a5,t5 + 3018: 01cace33 xor t3,s5,t3 + 301c: 008bfbb3 and s7,s7,s0 + 3020: 013d49b3 xor s3,s10,s3 + 3024: 0096fab3 and s5,a3,s1 + 3028: ff23ac23 sw s2,-8(t2) + 302c: ff03ae23 sw a6,-4(t2) + 3030: 99f2 add s3,s3,t3 + 3032: 015bcab3 xor s5,s7,s5 + 3036: 9aae add s5,s5,a1 + 3038: 01c9be33 sltu t3,s3,t3 + 303c: 078b2d83 lw s11,120(s6) + 3040: 9e56 add t3,t3,s5 + 3042: 07cb2a83 lw s5,124(s6) + 3046: 9dce add s11,s11,s3 + 3048: 013db9b3 sltu s3,s11,s3 + 304c: 9e56 add t3,t3,s5 + 304e: 996e add s2,s2,s11 + 3050: 99f2 add s3,s3,t3 + 3052: 99c2 add s3,s3,a6 + 3054: 01b93db3 sltu s11,s2,s11 + 3058: 9dce add s11,s11,s3 + 305a: 01c75593 srli a1,a4,0x1c + 305e: 00461993 slli s3,a2,0x4 + 3062: 00b9ebb3 or s7,s3,a1 + 3066: 01c65813 srli a6,a2,0x1c + 306a: 00471593 slli a1,a4,0x4 + 306e: 0105eab3 or s5,a1,a6 + 3072: 00265e13 srli t3,a2,0x2 + 3076: 01e61813 slli a6,a2,0x1e + 307a: 01e71d13 slli s10,a4,0x1e + 307e: 00275593 srli a1,a4,0x2 + 3082: 01ae69b3 or s3,t3,s10 + 3086: 0105e5b3 or a1,a1,a6 + 308a: 00775e13 srli t3,a4,0x7 + 308e: 01961813 slli a6,a2,0x19 + 3092: 00bac5b3 xor a1,s5,a1 + 3096: 010e6e33 or t3,t3,a6 + 309a: 01971a93 slli s5,a4,0x19 + 309e: 00765813 srli a6,a2,0x7 + 30a2: 9cca add s9,s9,s2 + 30a4: 013bc9b3 xor s3,s7,s3 + 30a8: 01586833 or a6,a6,s5 + 30ac: 01134ab3 xor s5,t1,a7 + 30b0: 012cb933 sltu s2,s9,s2 + 30b4: 0109c833 xor a6,s3,a6 + 30b8: 01c5ce33 xor t3,a1,t3 + 30bc: 9de2 add s11,s11,s8 + 30be: 00eafab3 and s5,s5,a4 + 30c2: 01f2c9b3 xor s3,t0,t6 + 30c6: 011375b3 and a1,t1,a7 + 30ca: 01b90c33 add s8,s2,s11 + 30ce: 00bac5b3 xor a1,s5,a1 + 30d2: 01f2f933 and s2,t0,t6 + 30d6: 00c9f9b3 and s3,s3,a2 + 30da: 0129c9b3 xor s3,s3,s2 + 30de: 95c2 add a1,a1,a6 + 30e0: 0105b833 sltu a6,a1,a6 + 30e4: 99f2 add s3,s3,t3 + 30e6: 01380933 add s2,a6,s3 + 30ea: 5812 lw a6,36(sp) + 30ec: 95e6 add a1,a1,s9 + 30ee: 0a05 addi s4,s4,1 + 30f0: 010c8e33 add t3,s9,a6 + 30f4: 4826 lw a6,72(sp) + 30f6: 019e3db3 sltu s11,t3,s9 + 30fa: 0195bcb3 sltu s9,a1,s9 + 30fe: 9862 add a6,a6,s8 + 3100: 9c4a add s8,s8,s2 + 3102: 9dc2 add s11,s11,a6 + 3104: d246 sw a7,36(sp) + 3106: 018c8833 add a6,s9,s8 + 310a: c4fe sw t6,72(sp) + 310c: 4939 li s2,14 + 310e: 89f2 mv s3,t3 + 3110: 8aee mv s5,s11 + 3112: 8bae mv s7,a1 + 3114: 8d42 mv s10,a6 + 3116: 8cf6 mv s9,t4 + 3118: 8c22 mv s8,s0 + 311a: 0f2a1863 bne s4,s2,320a + 311e: 4382 lw t2,0(sp) + 3120: 08038393 addi t2,t2,128 + 3124: c01e sw t2,0(sp) + 3126: 4902 lw s2,0(sp) + 3128: 63b1 lui t2,0xc + 312a: 62838393 addi t2,t2,1576 # c628 + 312e: d52398e3 bne t2,s2,2e7e + 3132: 4392 lw t2,4(sp) + 3134: 5922 lw s2,40(sp) + 3136: 959e add a1,a1,t2 + 3138: 0075b3b3 sltu t2,a1,t2 + 313c: 984a add a6,a6,s2 + 313e: 981e add a6,a6,t2 + 3140: c10c sw a1,0(a0) + 3142: 45a2 lw a1,8(sp) + 3144: 01052223 sw a6,4(a0) + 3148: 5832 lw a6,44(sp) + 314a: 972e add a4,a4,a1 + 314c: 00b735b3 sltu a1,a4,a1 + 3150: 9642 add a2,a2,a6 + 3152: 962e add a2,a2,a1 + 3154: c518 sw a4,8(a0) + 3156: 4732 lw a4,12(sp) + 3158: c550 sw a2,12(a0) + 315a: 5642 lw a2,48(sp) + 315c: 933a add t1,t1,a4 + 315e: 00e33733 sltu a4,t1,a4 + 3162: 92b2 add t0,t0,a2 + 3164: 92ba add t0,t0,a4 + 3166: 4742 lw a4,16(sp) + 3168: 5652 lw a2,52(sp) + 316a: 00652823 sw t1,16(a0) + 316e: 98ba add a7,a7,a4 + 3170: 00e8b733 sltu a4,a7,a4 + 3174: 9fb2 add t6,t6,a2 + 3176: 9fba add t6,t6,a4 + 3178: 4752 lw a4,20(sp) + 317a: 5662 lw a2,56(sp) + 317c: 00552a23 sw t0,20(a0) + 3180: 9e3a add t3,t3,a4 + 3182: 00ee3733 sltu a4,t3,a4 + 3186: 9db2 add s11,s11,a2 + 3188: 9dba add s11,s11,a4 + 318a: 4762 lw a4,24(sp) + 318c: 5672 lw a2,60(sp) + 318e: 03b52223 sw s11,36(a0) + 3192: 97ba add a5,a5,a4 + 3194: 00e7b733 sltu a4,a5,a4 + 3198: d51c sw a5,40(a0) + 319a: 96b2 add a3,a3,a2 + 319c: 47f2 lw a5,28(sp) + 319e: 96ba add a3,a3,a4 + 31a0: 4706 lw a4,64(sp) + 31a2: 9f3e add t5,t5,a5 + 31a4: 00ff37b3 sltu a5,t5,a5 + 31a8: 94ba add s1,s1,a4 + 31aa: 94be add s1,s1,a5 + 31ac: 5782 lw a5,32(sp) + 31ae: 4716 lw a4,68(sp) + 31b0: d944 sw s1,52(a0) + 31b2: 9ebe add t4,t4,a5 + 31b4: 00feb7b3 sltu a5,t4,a5 + 31b8: 943a add s0,s0,a4 + 31ba: 943e add s0,s0,a5 + 31bc: 01152c23 sw a7,24(a0) + 31c0: 01f52e23 sw t6,28(a0) + 31c4: 03c52023 sw t3,32(a0) + 31c8: d554 sw a3,44(a0) + 31ca: 03e52823 sw t5,48(a0) + 31ce: 03d52c23 sw t4,56(a0) + 31d2: dd40 sw s0,60(a0) + 31d4: 5476 lw s0,124(sp) + 31d6: 54e6 lw s1,120(sp) + 31d8: 5956 lw s2,116(sp) + 31da: 59c6 lw s3,112(sp) + 31dc: 5a36 lw s4,108(sp) + 31de: 5aa6 lw s5,104(sp) + 31e0: 5b16 lw s6,100(sp) + 31e2: 5b86 lw s7,96(sp) + 31e4: 4c76 lw s8,92(sp) + 31e6: 4ce6 lw s9,88(sp) + 31e8: 4d56 lw s10,84(sp) + 31ea: 4dc6 lw s11,80(sp) + 31ec: 6109 addi sp,sp,128 + 31ee: 8082 ret + 31f0: 8efa mv t4,t5 + 31f2: 8426 mv s0,s1 + 31f4: 8f3e mv t5,a5 + 31f6: 84b6 mv s1,a3 + 31f8: 889a mv a7,t1 + 31fa: 8f96 mv t6,t0 + 31fc: 833a mv t1,a4 + 31fe: 82b2 mv t0,a2 + 3200: 87e2 mv a5,s8 + 3202: 86da mv a3,s6 + 3204: 8742 mv a4,a6 + 3206: 5612 lw a2,36(sp) + 3208: b639 j 2d16 + 320a: 8efa mv t4,t5 + 320c: 8426 mv s0,s1 + 320e: 8f3e mv t5,a5 + 3210: 84b6 mv s1,a3 + 3212: 889a mv a7,t1 + 3214: 8f96 mv t6,t0 + 3216: 833a mv t1,a4 + 3218: 82b2 mv t0,a2 + 321a: 87f2 mv a5,t3 + 321c: 86ee mv a3,s11 + 321e: 872e mv a4,a1 + 3220: 8642 mv a2,a6 + 3222: b149 j 2ea4 + +00003224 : + 3224: fcdfc2ef jal t0,1f0 <__riscv_save_0> + 3228: 0d052603 lw a2,208(a0) + 322c: 57e1 li a5,-8 + 322e: ff867413 andi s0,a2,-8 + 3232: 8a1d andi a2,a2,7 + 3234: 02f60633 mul a2,a2,a5 + 3238: 942a add s0,s0,a0 + 323a: 852e mv a0,a1 + 323c: 4581 li a1,0 + 323e: 03860613 addi a2,a2,56 + 3242: 2be060ef jal ra,9500 <__ashldi3> + 3246: 403c lw a5,64(s0) + 3248: 8d5d or a0,a0,a5 + 324a: 407c lw a5,68(s0) + 324c: c028 sw a0,64(s0) + 324e: 8ddd or a1,a1,a5 + 3250: c06c sw a1,68(s0) + 3252: fc3fc06f j 214 <__riscv_restore_0> + +00003256 : + 3256: f81fc2ef jal t0,1d6 <__riscv_save_4> + 325a: 0d052983 lw s3,208(a0) + 325e: 842a mv s0,a0 + 3260: 892e mv s2,a1 + 3262: 0079f793 andi a5,s3,7 + 3266: 84b2 mv s1,a2 + 3268: c385 beqz a5,3288 + 326a: 413009b3 neg s3,s3 + 326e: 0079f993 andi s3,s3,7 + 3272: 01367363 bgeu a2,s3,3278 + 3276: 89b2 mv s3,a2 + 3278: 4a01 li s4,0 + 327a: 014907b3 add a5,s2,s4 + 327e: 0d3a1463 bne s4,s3,3346 + 3282: 893e mv s2,a5 + 3284: 414484b3 sub s1,s1,s4 + 3288: 0d042783 lw a5,208(s0) + 328c: 07f7f713 andi a4,a5,127 + 3290: cf05 beqz a4,32c8 + 3292: 40f00733 neg a4,a5 + 3296: 07f77713 andi a4,a4,127 + 329a: 0034d993 srli s3,s1,0x3 + 329e: 00e4e463 bltu s1,a4,32a6 + 32a2: 00375993 srli s3,a4,0x3 + 32a6: 9be1 andi a5,a5,-8 + 32a8: 04040513 addi a0,s0,64 + 32ac: 864e mv a2,s3 + 32ae: 85ca mv a1,s2 + 32b0: 953e add a0,a0,a5 + 32b2: 977ff0ef jal ra,2c28 + 32b6: 0d042783 lw a5,208(s0) + 32ba: 098e slli s3,s3,0x3 + 32bc: 994e add s2,s2,s3 + 32be: 97ce add a5,a5,s3 + 32c0: 0cf42823 sw a5,208(s0) + 32c4: 413484b3 sub s1,s1,s3 + 32c8: 0d042703 lw a4,208(s0) + 32cc: 08000793 li a5,128 + 32d0: 06f71163 bne a4,a5,3332 + 32d4: 0c842783 lw a5,200(s0) + 32d8: 0cc42683 lw a3,204(s0) + 32dc: 40078713 addi a4,a5,1024 + 32e0: 00f737b3 sltu a5,a4,a5 + 32e4: 97b6 add a5,a5,a3 + 32e6: 0ce42423 sw a4,200(s0) + 32ea: 0cf42623 sw a5,204(s0) + 32ee: e395 bnez a5,3312 + 32f0: 3ff00793 li a5,1023 + 32f4: 00e7ef63 bltu a5,a4,3312 + 32f8: 0c042783 lw a5,192(s0) + 32fc: 0c442683 lw a3,196(s0) + 3300: 00178713 addi a4,a5,1 + 3304: 00f737b3 sltu a5,a4,a5 + 3308: 97b6 add a5,a5,a3 + 330a: 0ce42023 sw a4,192(s0) + 330e: 0cf42223 sw a5,196(s0) + 3312: 8522 mv a0,s0 + 3314: 96dff0ef jal ra,2c80 + 3318: 04040793 addi a5,s0,64 + 331c: 0c042823 sw zero,208(s0) + 3320: 0c040713 addi a4,s0,192 + 3324: 4601 li a2,0 + 3326: 4681 li a3,0 + 3328: c390 sw a2,0(a5) + 332a: c3d4 sw a3,4(a5) + 332c: 07a1 addi a5,a5,8 + 332e: fef71be3 bne a4,a5,3324 + 3332: f804f993 andi s3,s1,-128 + 3336: 99ca add s3,s3,s2 + 3338: 04040a13 addi s4,s0,64 + 333c: 3ff00a93 li s5,1023 + 3340: 0c040b13 addi s6,s0,192 + 3344: a8ad j 33be + 3346: 238c lbu a1,0(a5) + 3348: 8522 mv a0,s0 + 334a: 0a05 addi s4,s4,1 + 334c: ed9ff0ef jal ra,3224 + 3350: 0d042783 lw a5,208(s0) + 3354: 0785 addi a5,a5,1 + 3356: 0cf42823 sw a5,208(s0) + 335a: b705 j 327a + 335c: 4641 li a2,16 + 335e: 85ca mv a1,s2 + 3360: 8552 mv a0,s4 + 3362: 8c7ff0ef jal ra,2c28 + 3366: 0c842783 lw a5,200(s0) + 336a: 0cc42683 lw a3,204(s0) + 336e: 40078713 addi a4,a5,1024 + 3372: 00f737b3 sltu a5,a4,a5 + 3376: 97b6 add a5,a5,a3 + 3378: 0ce42423 sw a4,200(s0) + 337c: 0cf42623 sw a5,204(s0) + 3380: e385 bnez a5,33a0 + 3382: 00eaef63 bltu s5,a4,33a0 + 3386: 0c042783 lw a5,192(s0) + 338a: 0c442683 lw a3,196(s0) + 338e: 00178713 addi a4,a5,1 + 3392: 00f737b3 sltu a5,a4,a5 + 3396: 97b6 add a5,a5,a3 + 3398: 0ce42023 sw a4,192(s0) + 339c: 0cf42223 sw a5,196(s0) + 33a0: 8522 mv a0,s0 + 33a2: 8dfff0ef jal ra,2c80 + 33a6: 87d2 mv a5,s4 + 33a8: 0c042823 sw zero,208(s0) + 33ac: 4681 li a3,0 + 33ae: 4701 li a4,0 + 33b0: c394 sw a3,0(a5) + 33b2: c3d8 sw a4,4(a5) + 33b4: 07a1 addi a5,a5,8 + 33b6: ff679be3 bne a5,s6,33ac + 33ba: 08090913 addi s2,s2,128 + 33be: f9391fe3 bne s2,s3,335c + 33c2: 07f4f913 andi s2,s1,127 + 33c6: 02090563 beqz s2,33f0 + 33ca: 00395613 srli a2,s2,0x3 + 33ce: 85ce mv a1,s3 + 33d0: 04040513 addi a0,s0,64 + 33d4: 855ff0ef jal ra,2c28 + 33d8: 0d042783 lw a5,208(s0) + 33dc: 0784f493 andi s1,s1,120 + 33e0: 40990933 sub s2,s2,s1 + 33e4: 97a6 add a5,a5,s1 + 33e6: 0cf42823 sw a5,208(s0) + 33ea: 4a01 li s4,0 + 33ec: 01491463 bne s2,s4,33f4 + 33f0: e1bfc06f j 20a <__riscv_restore_4> + 33f4: 014487b3 add a5,s1,s4 + 33f8: 97ce add a5,a5,s3 + 33fa: 238c lbu a1,0(a5) + 33fc: 8522 mv a0,s0 + 33fe: 0a05 addi s4,s4,1 + 3400: e25ff0ef jal ra,3224 + 3404: 0d042783 lw a5,208(s0) + 3408: 0785 addi a5,a5,1 + 340a: 0cf42823 sw a5,208(s0) + 340e: bff9 j 33ec + +00003410 : + 3410: 0000c7b7 lui a5,0xc + 3414: 6a87a703 lw a4,1704(a5) # c6a8 + 3418: 6ac7a783 lw a5,1708(a5) + 341c: 4801 li a6,0 + 341e: c118 sw a4,0(a0) + 3420: c15c sw a5,4(a0) + 3422: 0000c7b7 lui a5,0xc + 3426: 6b07a703 lw a4,1712(a5) # c6b0 + 342a: 6b47a783 lw a5,1716(a5) + 342e: c518 sw a4,8(a0) + 3430: c55c sw a5,12(a0) + 3432: 0000c7b7 lui a5,0xc + 3436: 6b87a703 lw a4,1720(a5) # c6b8 + 343a: 6bc7a783 lw a5,1724(a5) + 343e: c918 sw a4,16(a0) + 3440: c95c sw a5,20(a0) + 3442: 0000c7b7 lui a5,0xc + 3446: 6c07a703 lw a4,1728(a5) # c6c0 + 344a: 6c47a783 lw a5,1732(a5) + 344e: cd18 sw a4,24(a0) + 3450: cd5c sw a5,28(a0) + 3452: 0000c7b7 lui a5,0xc + 3456: 6c87a703 lw a4,1736(a5) # c6c8 + 345a: 6cc7a783 lw a5,1740(a5) + 345e: d118 sw a4,32(a0) + 3460: d15c sw a5,36(a0) + 3462: 0000c7b7 lui a5,0xc + 3466: 6d07a703 lw a4,1744(a5) # c6d0 + 346a: 6d47a783 lw a5,1748(a5) + 346e: d518 sw a4,40(a0) + 3470: d55c sw a5,44(a0) + 3472: 0000c7b7 lui a5,0xc + 3476: 6d87a703 lw a4,1752(a5) # c6d8 + 347a: 6dc7a783 lw a5,1756(a5) + 347e: d918 sw a4,48(a0) + 3480: d95c sw a5,52(a0) + 3482: 0000c7b7 lui a5,0xc + 3486: 6e07a703 lw a4,1760(a5) # c6e0 + 348a: 6e47a783 lw a5,1764(a5) + 348e: dd18 sw a4,56(a0) + 3490: dd5c sw a5,60(a0) + 3492: 4781 li a5,0 + 3494: 0cf52023 sw a5,192(a0) + 3498: 0cf52423 sw a5,200(a0) + 349c: 0d052223 sw a6,196(a0) + 34a0: 0d052623 sw a6,204(a0) + 34a4: 0c052823 sw zero,208(a0) + 34a8: 04050793 addi a5,a0,64 + 34ac: 0c050513 addi a0,a0,192 + 34b0: 4681 li a3,0 + 34b2: 4701 li a4,0 + 34b4: c394 sw a3,0(a5) + 34b6: c3d8 sw a4,4(a5) + 34b8: 07a1 addi a5,a5,8 + 34ba: fea79be3 bne a5,a0,34b0 + 34be: 8082 ret + +000034c0 : + 34c0: c619 beqz a2,34ce + 34c2: d2ffc2ef jal t0,1f0 <__riscv_save_0> + 34c6: d91ff0ef jal ra,3256 + 34ca: d4bfc06f j 214 <__riscv_restore_0> + 34ce: 8082 ret + +000034d0 : + 34d0: d21fc2ef jal t0,1f0 <__riscv_save_0> + 34d4: 0d052783 lw a5,208(a0) + 34d8: 842a mv s0,a0 + 34da: 84ae mv s1,a1 + 34dc: ef81 bnez a5,34f4 + 34de: 04050793 addi a5,a0,64 + 34e2: 0c050713 addi a4,a0,192 + 34e6: 4601 li a2,0 + 34e8: 4681 li a3,0 + 34ea: c390 sw a2,0(a5) + 34ec: c3d4 sw a3,4(a5) + 34ee: 07a1 addi a5,a5,8 + 34f0: fee79be3 bne a5,a4,34e6 + 34f4: 08000593 li a1,128 + 34f8: 8522 mv a0,s0 + 34fa: d2bff0ef jal ra,3224 + 34fe: 0d042603 lw a2,208(s0) + 3502: 0c842783 lw a5,200(s0) + 3506: 0cc42583 lw a1,204(s0) + 350a: 00361693 slli a3,a2,0x3 + 350e: 97b6 add a5,a5,a3 + 3510: 00d7b733 sltu a4,a5,a3 + 3514: 972e add a4,a4,a1 + 3516: 0cf42423 sw a5,200(s0) + 351a: 0ce42623 sw a4,204(s0) + 351e: e305 bnez a4,353e + 3520: 00d7ff63 bgeu a5,a3,353e + 3524: 0c042783 lw a5,192(s0) + 3528: 0c442683 lw a3,196(s0) + 352c: 00178713 addi a4,a5,1 + 3530: 00f737b3 sltu a5,a4,a5 + 3534: 97b6 add a5,a5,a3 + 3536: 0ce42023 sw a4,192(s0) + 353a: 0cf42223 sw a5,196(s0) + 353e: 06f00793 li a5,111 + 3542: 02c7f063 bgeu a5,a2,3562 + 3546: 8522 mv a0,s0 + 3548: f38ff0ef jal ra,2c80 + 354c: 04040793 addi a5,s0,64 + 3550: 0b040713 addi a4,s0,176 + 3554: 4601 li a2,0 + 3556: 4681 li a3,0 + 3558: c390 sw a2,0(a5) + 355a: c3d4 sw a3,4(a5) + 355c: 07a1 addi a5,a5,8 + 355e: fee79be3 bne a5,a4,3554 + 3562: 0c042703 lw a4,192(s0) + 3566: 0c442783 lw a5,196(s0) + 356a: 8522 mv a0,s0 + 356c: 0ae42823 sw a4,176(s0) + 3570: 0af42a23 sw a5,180(s0) + 3574: 0c842703 lw a4,200(s0) + 3578: 0cc42783 lw a5,204(s0) + 357c: 0ae42c23 sw a4,184(s0) + 3580: 0af42e23 sw a5,188(s0) + 3584: efcff0ef jal ra,2c80 + 3588: 87a2 mv a5,s0 + 358a: 85a6 mv a1,s1 + 358c: 04048613 addi a2,s1,64 + 3590: 43d4 lw a3,4(a5) + 3592: 4398 lw a4,0(a5) + 3594: 05a1 addi a1,a1,8 + 3596: 0186d513 srli a0,a3,0x18 + 359a: fea58c23 sb a0,-8(a1) + 359e: 0106d513 srli a0,a3,0x10 + 35a2: fea58ca3 sb a0,-7(a1) + 35a6: fed58da3 sb a3,-5(a1) + 35aa: 0086d513 srli a0,a3,0x8 + 35ae: 01875693 srli a3,a4,0x18 + 35b2: fed58e23 sb a3,-4(a1) + 35b6: 01075693 srli a3,a4,0x10 + 35ba: fed58ea3 sb a3,-3(a1) + 35be: 00875693 srli a3,a4,0x8 + 35c2: fea58d23 sb a0,-6(a1) + 35c6: fed58f23 sb a3,-2(a1) + 35ca: fee58fa3 sb a4,-1(a1) + 35ce: 07a1 addi a5,a5,8 + 35d0: fcc590e3 bne a1,a2,3590 + 35d4: 0d800593 li a1,216 + 35d8: 8522 mv a0,s0 + 35da: 0e2020ef jal ra,56bc + 35de: c37fc06f j 214 <__riscv_restore_0> + +000035e2 : + 35e2: c0ffc2ef jal t0,1f0 <__riscv_save_0> + 35e6: 7129 addi sp,sp,-320 + 35e8: 842a mv s0,a0 + 35ea: 10a8 addi a0,sp,104 + 35ec: c442 sw a6,8(sp) + 35ee: c246 sw a7,4(sp) + 35f0: c83a sw a4,16(sp) + 35f2: c63e sw a5,12(sp) + 35f4: ca36 sw a3,20(sp) + 35f6: ce2e sw a1,28(sp) + 35f8: cc32 sw a2,24(sp) + 35fa: e17ff0ef jal ra,3410 + 35fe: 4662 lw a2,24(sp) + 3600: 45f2 lw a1,28(sp) + 3602: 10a8 addi a0,sp,104 + 3604: ebdff0ef jal ra,34c0 + 3608: 46d2 lw a3,20(sp) + 360a: 10a8 addi a0,sp,104 + 360c: 02000613 li a2,32 + 3610: 85b6 mv a1,a3 + 3612: c45ff0ef jal ra,3256 + 3616: 47b2 lw a5,12(sp) + 3618: 4742 lw a4,16(sp) + 361a: 10a8 addi a0,sp,104 + 361c: 863e mv a2,a5 + 361e: 85ba mv a1,a4 + 3620: ea1ff0ef jal ra,34c0 + 3624: 4892 lw a7,4(sp) + 3626: 4822 lw a6,8(sp) + 3628: 10a8 addi a0,sp,104 + 362a: 8646 mv a2,a7 + 362c: 85c2 mv a1,a6 + 362e: e93ff0ef jal ra,34c0 + 3632: 102c addi a1,sp,40 + 3634: 10a8 addi a0,sp,104 + 3636: e9bff0ef jal ra,34d0 + 363a: 102c addi a1,sp,40 + 363c: 8522 mv a0,s0 + 363e: 031020ef jal ra,5e6e + 3642: 6131 addi sp,sp,320 + 3644: bd1fc06f j 214 <__riscv_restore_0> + +00003648 : + 3648: ba9fc2ef jal t0,1f0 <__riscv_save_0> + 364c: 7151 addi sp,sp,-240 + 364e: 842a mv s0,a0 + 3650: 0828 addi a0,sp,24 + 3652: c62e sw a1,12(sp) + 3654: c432 sw a2,8(sp) + 3656: dbbff0ef jal ra,3410 + 365a: 4622 lw a2,8(sp) + 365c: 45b2 lw a1,12(sp) + 365e: 0828 addi a0,sp,24 + 3660: e61ff0ef jal ra,34c0 + 3664: 0828 addi a0,sp,24 + 3666: 85a2 mv a1,s0 + 3668: e69ff0ef jal ra,34d0 + 366c: 616d addi sp,sp,240 + 366e: ba7fc06f j 214 <__riscv_restore_0> + +00003672 : + 3672: b65fc2ef jal t0,1d6 <__riscv_save_4> + 3676: 7135 addi sp,sp,-160 + 3678: 84b2 mv s1,a2 + 367a: 842a mv s0,a0 + 367c: 02000613 li a2,32 + 3680: 1088 addi a0,sp,96 + 3682: 8936 mv s2,a3 + 3684: 89ba mv s3,a4 + 3686: 8a3e mv s4,a5 + 3688: 8aae mv s5,a1 + 368a: fbfff0ef jal ra,3648 + 368e: 108c addi a1,sp,96 + 3690: 852e mv a0,a1 + 3692: 782020ef jal ra,5e14 + 3696: 4881 li a7,0 + 3698: 4801 li a6,0 + 369a: 87d2 mv a5,s4 + 369c: 874e mv a4,s3 + 369e: 0114 addi a3,sp,128 + 36a0: 864a mv a2,s2 + 36a2: 85a6 mv a1,s1 + 36a4: 850a mv a0,sp + 36a6: f3dff0ef jal ra,35e2 + 36aa: 858a mv a1,sp + 36ac: 0088 addi a0,sp,64 + 36ae: 2e9020ef jal ra,6196 + 36b2: 02000793 li a5,32 + 36b6: 020a8713 addi a4,s5,32 + 36ba: 88d2 mv a7,s4 + 36bc: 884e mv a6,s3 + 36be: 0094 addi a3,sp,64 + 36c0: 864a mv a2,s2 + 36c2: 85a6 mv a1,s1 + 36c4: 1008 addi a0,sp,32 + 36c6: f1dff0ef jal ra,35e2 + 36ca: 4781 li a5,0 + 36cc: 02000713 li a4,32 + 36d0: 0090 addi a2,sp,64 + 36d2: 963e add a2,a2,a5 + 36d4: 2210 lbu a2,0(a2) + 36d6: 00f406b3 add a3,s0,a5 + 36da: 0785 addi a5,a5,1 + 36dc: a290 sb a2,0(a3) + 36de: fee799e3 bne a5,a4,36d0 + 36e2: 868a mv a3,sp + 36e4: 1090 addi a2,sp,96 + 36e6: 100c addi a1,sp,32 + 36e8: 02040513 addi a0,s0,32 + 36ec: 7aa020ef jal ra,5e96 + 36f0: 1088 addi a0,sp,96 + 36f2: 04000593 li a1,64 + 36f6: 7c7010ef jal ra,56bc + 36fa: 850a mv a0,sp + 36fc: 02000593 li a1,32 + 3700: 7bd010ef jal ra,56bc + 3704: 610d addi sp,sp,160 + 3706: b05fc06f j 20a <__riscv_restore_4> + +0000370a : + 370a: ae7fc2ef jal t0,1f0 <__riscv_save_0> + 370e: 7139 addi sp,sp,-64 + 3710: 842a mv s0,a0 + 3712: 84ae mv s1,a1 + 3714: 4781 li a5,0 + 3716: 02000713 li a4,32 + 371a: 00f605b3 add a1,a2,a5 + 371e: 218c lbu a1,0(a1) + 3720: 00f106b3 add a3,sp,a5 + 3724: 0785 addi a5,a5,1 + 3726: a28c sb a1,0(a3) + 3728: fee799e3 bne a5,a4,371a + 372c: 02000593 li a1,32 + 3730: 8532 mv a0,a2 + 3732: 78b010ef jal ra,56bc + 3736: 4781 li a5,0 + 3738: 02000713 li a4,32 + 373c: 00f10633 add a2,sp,a5 + 3740: 2210 lbu a2,0(a2) + 3742: 00f406b3 add a3,s0,a5 + 3746: 0785 addi a5,a5,1 + 3748: a290 sb a2,0(a3) + 374a: fee799e3 bne a5,a4,373c + 374e: 02000613 li a2,32 + 3752: 858a mv a1,sp + 3754: 850a mv a0,sp + 3756: ef3ff0ef jal ra,3648 + 375a: 858a mv a1,sp + 375c: 850a mv a0,sp + 375e: 6b6020ef jal ra,5e14 + 3762: 858a mv a1,sp + 3764: 8526 mv a0,s1 + 3766: 231020ef jal ra,6196 + 376a: 4781 li a5,0 + 376c: 02000713 li a4,32 + 3770: 00f486b3 add a3,s1,a5 + 3774: 2290 lbu a2,0(a3) + 3776: 00f406b3 add a3,s0,a5 + 377a: 0785 addi a5,a5,1 + 377c: 02c68023 sb a2,32(a3) + 3780: fee798e3 bne a5,a4,3770 + 3784: 850a mv a0,sp + 3786: 04000593 li a1,64 + 378a: 733010ef jal ra,56bc + 378e: 6121 addi sp,sp,64 + 3790: a85fc06f j 214 <__riscv_restore_0> + +00003794 : + 3794: a5dfc2ef jal t0,1f0 <__riscv_save_0> + 3798: 87b6 mv a5,a3 + 379a: 8732 mv a4,a2 + 379c: 4681 li a3,0 + 379e: 4601 li a2,0 + 37a0: ed3ff0ef jal ra,3672 + 37a4: a71fc06f j 214 <__riscv_restore_0> + +000037a8 : + 37a8: a49fc2ef jal t0,1f0 <__riscv_save_0> + 37ac: 1101 addi sp,sp,-32 + 37ae: 842a mv s0,a0 + 37b0: 87b6 mv a5,a3 + 37b2: 8732 mv a4,a2 + 37b4: 86ae mv a3,a1 + 37b6: 84ae mv s1,a1 + 37b8: 4881 li a7,0 + 37ba: 4801 li a6,0 + 37bc: 85aa mv a1,a0 + 37be: 02000613 li a2,32 + 37c2: 850a mv a0,sp + 37c4: e1fff0ef jal ra,35e2 + 37c8: 860a mv a2,sp + 37ca: 85a6 mv a1,s1 + 37cc: 8522 mv a0,s0 + 37ce: 00f020ef jal ra,5fdc + 37d2: 6105 addi sp,sp,32 + 37d4: a41fc06f j 214 <__riscv_restore_0> + +000037d8 : + 37d8: 311c lbu a5,1(a0) + 37da: 2138 lbu a4,2(a0) + 37dc: 2108 lbu a0,0(a0) + 37de: 07a2 slli a5,a5,0x8 + 37e0: 0742 slli a4,a4,0x10 + 37e2: 8fd9 or a5,a5,a4 + 37e4: 8d5d or a0,a0,a5 + 37e6: 8082 ret + +000037e8 : + 37e8: 311c lbu a5,1(a0) + 37ea: 2118 lbu a4,0(a0) + 37ec: 07a2 slli a5,a5,0x8 + 37ee: 8f5d or a4,a4,a5 + 37f0: 213c lbu a5,2(a0) + 37f2: 3128 lbu a0,3(a0) + 37f4: 07c2 slli a5,a5,0x10 + 37f6: 8fd9 or a5,a5,a4 + 37f8: 0562 slli a0,a0,0x18 + 37fa: 8d5d or a0,a0,a5 + 37fc: 8082 ret + +000037fe : + 37fe: 9f3fc2ef jal t0,1f0 <__riscv_save_0> + 3802: 84aa mv s1,a0 + 3804: fe5ff0ef jal ra,37e8 + 3808: 842a mv s0,a0 + 380a: 00448513 addi a0,s1,4 + 380e: fdbff0ef jal ra,37e8 + 3812: 85aa mv a1,a0 + 3814: 8522 mv a0,s0 + 3816: 9fffc06f j 214 <__riscv_restore_0> + +0000381a : + 381a: 0085d793 srli a5,a1,0x8 + 381e: a10c sb a1,0(a0) + 3820: b11c sb a5,1(a0) + 3822: 0105d793 srli a5,a1,0x10 + 3826: 81e1 srli a1,a1,0x18 + 3828: a13c sb a5,2(a0) + 382a: b12c sb a1,3(a0) + 382c: 8082 ret + +0000382e : + 382e: 9c3fc2ef jal t0,1f0 <__riscv_save_0> + 3832: 1141 addi sp,sp,-16 + 3834: 892a mv s2,a0 + 3836: 00261493 slli s1,a2,0x2 + 383a: 4401 li s0,0 + 383c: 00858533 add a0,a1,s0 + 3840: c62e sw a1,12(sp) + 3842: fa7ff0ef jal ra,37e8 + 3846: 008907b3 add a5,s2,s0 + 384a: c388 sw a0,0(a5) + 384c: 0411 addi s0,s0,4 + 384e: 45b2 lw a1,12(sp) + 3850: fe9416e3 bne s0,s1,383c + 3854: 0141 addi sp,sp,16 + 3856: 9bffc06f j 214 <__riscv_restore_0> + +0000385a : + 385a: 97dfc2ef jal t0,1d6 <__riscv_save_4> + 385e: 892a mv s2,a0 + 3860: 89ae mv s3,a1 + 3862: 00261493 slli s1,a2,0x2 + 3866: 4401 li s0,0 + 3868: 008987b3 add a5,s3,s0 + 386c: 438c lw a1,0(a5) + 386e: 00890533 add a0,s2,s0 + 3872: 0411 addi s0,s0,4 + 3874: fa7ff0ef jal ra,381a + 3878: fe9418e3 bne s0,s1,3868 + 387c: 98ffc06f j 20a <__riscv_restore_4> + +00003880 : + 3880: 957fc2ef jal t0,1d6 <__riscv_save_4> + 3884: 8a2e mv s4,a1 + 3886: 84aa mv s1,a0 + 3888: f77ff0ef jal ra,37fe + 388c: 892a mv s2,a0 + 388e: 8552 mv a0,s4 + 3890: 842e mv s0,a1 + 3892: f6dff0ef jal ra,37fe + 3896: 00a94933 xor s2,s2,a0 + 389a: 00848513 addi a0,s1,8 + 389e: 8c2d xor s0,s0,a1 + 38a0: f5fff0ef jal ra,37fe + 38a4: 89aa mv s3,a0 + 38a6: 008a0513 addi a0,s4,8 + 38aa: 84ae mv s1,a1 + 38ac: f53ff0ef jal ra,37fe + 38b0: 00a9c533 xor a0,s3,a0 + 38b4: 8da5 xor a1,a1,s1 + 38b6: 01256533 or a0,a0,s2 + 38ba: 8dc1 or a1,a1,s0 + 38bc: 94ffc06f j 20a <__riscv_restore_4> + +000038c0 : + 38c0: 917fc2ef jal t0,1d6 <__riscv_save_4> + 38c4: 892a mv s2,a0 + 38c6: 89ae mv s3,a1 + 38c8: fb9ff0ef jal ra,3880 + 38cc: 842e mv s0,a1 + 38ce: 84aa mv s1,a0 + 38d0: 01098593 addi a1,s3,16 + 38d4: 01090513 addi a0,s2,16 + 38d8: fa9ff0ef jal ra,3880 + 38dc: 8d45 or a0,a0,s1 + 38de: 8dc1 or a1,a1,s0 + 38e0: 92bfc06f j 20a <__riscv_restore_4> + +000038e4 : + 38e4: 02850793 addi a5,a0,40 + 38e8: 00052023 sw zero,0(a0) + 38ec: 0511 addi a0,a0,4 + 38ee: fef51de3 bne a0,a5,38e8 + 38f2: 8082 ret + +000038f4 : + 38f4: 4785 li a5,1 + 38f6: c11c sw a5,0(a0) + 38f8: 00450793 addi a5,a0,4 + 38fc: 02850513 addi a0,a0,40 + 3900: 0007a023 sw zero,0(a5) + 3904: 0791 addi a5,a5,4 + 3906: fea79de3 bne a5,a0,3900 + 390a: 8082 ret + +0000390c : + 390c: 4781 li a5,0 + 390e: 02800713 li a4,40 + 3912: 00f586b3 add a3,a1,a5 + 3916: 4290 lw a2,0(a3) + 3918: 00f506b3 add a3,a0,a5 + 391c: 0791 addi a5,a5,4 + 391e: c290 sw a2,0(a3) + 3920: fee799e3 bne a5,a4,3912 + 3924: 8082 ret + +00003926 : + 3926: 4781 li a5,0 + 3928: 02800693 li a3,40 + 392c: 00f58733 add a4,a1,a5 + 3930: 4318 lw a4,0(a4) + 3932: 00f50633 add a2,a0,a5 + 3936: 0791 addi a5,a5,4 + 3938: 40e00733 neg a4,a4 + 393c: c218 sw a4,0(a2) + 393e: fed797e3 bne a5,a3,392c + 3942: 8082 ret + +00003944 : + 3944: 4781 li a5,0 + 3946: 02800693 li a3,40 + 394a: 00f58733 add a4,a1,a5 + 394e: 00f608b3 add a7,a2,a5 + 3952: 4318 lw a4,0(a4) + 3954: 0008a883 lw a7,0(a7) + 3958: 00f50833 add a6,a0,a5 + 395c: 0791 addi a5,a5,4 + 395e: 9746 add a4,a4,a7 + 3960: 00e82023 sw a4,0(a6) + 3964: fed793e3 bne a5,a3,394a + 3968: 8082 ret + +0000396a : + 396a: 4781 li a5,0 + 396c: 02800693 li a3,40 + 3970: 00f58733 add a4,a1,a5 + 3974: 00f608b3 add a7,a2,a5 + 3978: 4318 lw a4,0(a4) + 397a: 0008a883 lw a7,0(a7) + 397e: 00f50833 add a6,a0,a5 + 3982: 0791 addi a5,a5,4 + 3984: 41170733 sub a4,a4,a7 + 3988: 00e82023 sw a4,0(a6) + 398c: fed792e3 bne a5,a3,3970 + 3990: 8082 ret + +00003992 : + 3992: 1141 addi sp,sp,-16 + 3994: 40c00633 neg a2,a2 + 3998: 4118 lw a4,0(a0) + 399a: 419c lw a5,0(a1) + 399c: c632 sw a2,12(sp) + 399e: 46b2 lw a3,12(sp) + 39a0: 8fb9 xor a5,a5,a4 + 39a2: 8ff5 and a5,a5,a3 + 39a4: 8f3d xor a4,a4,a5 + 39a6: c118 sw a4,0(a0) + 39a8: 4198 lw a4,0(a1) + 39aa: 46b2 lw a3,12(sp) + 39ac: 8fb9 xor a5,a5,a4 + 39ae: c19c sw a5,0(a1) + 39b0: 4158 lw a4,4(a0) + 39b2: 41dc lw a5,4(a1) + 39b4: 8fb9 xor a5,a5,a4 + 39b6: 8ff5 and a5,a5,a3 + 39b8: 8f3d xor a4,a4,a5 + 39ba: c158 sw a4,4(a0) + 39bc: 41d8 lw a4,4(a1) + 39be: 46b2 lw a3,12(sp) + 39c0: 8fb9 xor a5,a5,a4 + 39c2: c1dc sw a5,4(a1) + 39c4: 4518 lw a4,8(a0) + 39c6: 459c lw a5,8(a1) + 39c8: 8fb9 xor a5,a5,a4 + 39ca: 8ff5 and a5,a5,a3 + 39cc: 8f3d xor a4,a4,a5 + 39ce: c518 sw a4,8(a0) + 39d0: 4598 lw a4,8(a1) + 39d2: 46b2 lw a3,12(sp) + 39d4: 8fb9 xor a5,a5,a4 + 39d6: c59c sw a5,8(a1) + 39d8: 4558 lw a4,12(a0) + 39da: 45dc lw a5,12(a1) + 39dc: 8fb9 xor a5,a5,a4 + 39de: 8ff5 and a5,a5,a3 + 39e0: 8f3d xor a4,a4,a5 + 39e2: c558 sw a4,12(a0) + 39e4: 45d8 lw a4,12(a1) + 39e6: 46b2 lw a3,12(sp) + 39e8: 8fb9 xor a5,a5,a4 + 39ea: c5dc sw a5,12(a1) + 39ec: 4918 lw a4,16(a0) + 39ee: 499c lw a5,16(a1) + 39f0: 8fb9 xor a5,a5,a4 + 39f2: 8ff5 and a5,a5,a3 + 39f4: 8f3d xor a4,a4,a5 + 39f6: c918 sw a4,16(a0) + 39f8: 4998 lw a4,16(a1) + 39fa: 8fb9 xor a5,a5,a4 + 39fc: c99c sw a5,16(a1) + 39fe: 4958 lw a4,20(a0) + 3a00: 46b2 lw a3,12(sp) + 3a02: 49dc lw a5,20(a1) + 3a04: 8fb9 xor a5,a5,a4 + 3a06: 8ff5 and a5,a5,a3 + 3a08: 8f3d xor a4,a4,a5 + 3a0a: c958 sw a4,20(a0) + 3a0c: 49d8 lw a4,20(a1) + 3a0e: 46b2 lw a3,12(sp) + 3a10: 8fb9 xor a5,a5,a4 + 3a12: c9dc sw a5,20(a1) + 3a14: 4d18 lw a4,24(a0) + 3a16: 4d9c lw a5,24(a1) + 3a18: 8fb9 xor a5,a5,a4 + 3a1a: 8ff5 and a5,a5,a3 + 3a1c: 8f3d xor a4,a4,a5 + 3a1e: cd18 sw a4,24(a0) + 3a20: 4d98 lw a4,24(a1) + 3a22: 46b2 lw a3,12(sp) + 3a24: 8fb9 xor a5,a5,a4 + 3a26: cd9c sw a5,24(a1) + 3a28: 4d58 lw a4,28(a0) + 3a2a: 4ddc lw a5,28(a1) + 3a2c: 8fb9 xor a5,a5,a4 + 3a2e: 8ff5 and a5,a5,a3 + 3a30: 8f3d xor a4,a4,a5 + 3a32: cd58 sw a4,28(a0) + 3a34: 4dd8 lw a4,28(a1) + 3a36: 46b2 lw a3,12(sp) + 3a38: 8fb9 xor a5,a5,a4 + 3a3a: cddc sw a5,28(a1) + 3a3c: 5118 lw a4,32(a0) + 3a3e: 519c lw a5,32(a1) + 3a40: 8fb9 xor a5,a5,a4 + 3a42: 8ff5 and a5,a5,a3 + 3a44: 8f3d xor a4,a4,a5 + 3a46: d118 sw a4,32(a0) + 3a48: 5198 lw a4,32(a1) + 3a4a: 46b2 lw a3,12(sp) + 3a4c: 8fb9 xor a5,a5,a4 + 3a4e: d19c sw a5,32(a1) + 3a50: 5158 lw a4,36(a0) + 3a52: 51dc lw a5,36(a1) + 3a54: 8fb9 xor a5,a5,a4 + 3a56: 8ff5 and a5,a5,a3 + 3a58: 8f3d xor a4,a4,a5 + 3a5a: d158 sw a4,36(a0) + 3a5c: 51d8 lw a4,36(a1) + 3a5e: 8fb9 xor a5,a5,a4 + 3a60: d1dc sw a5,36(a1) + 3a62: 0141 addi sp,sp,16 + 3a64: 8082 ret + +00003a66 : + 3a66: 1141 addi sp,sp,-16 + 3a68: 40c00633 neg a2,a2 + 3a6c: c632 sw a2,12(sp) + 3a6e: 419c lw a5,0(a1) + 3a70: 4118 lw a4,0(a0) + 3a72: 46b2 lw a3,12(sp) + 3a74: 8fb9 xor a5,a5,a4 + 3a76: 8ff5 and a5,a5,a3 + 3a78: 8fb9 xor a5,a5,a4 + 3a7a: c11c sw a5,0(a0) + 3a7c: 41dc lw a5,4(a1) + 3a7e: 4158 lw a4,4(a0) + 3a80: 46b2 lw a3,12(sp) + 3a82: 8fb9 xor a5,a5,a4 + 3a84: 8ff5 and a5,a5,a3 + 3a86: 8fb9 xor a5,a5,a4 + 3a88: c15c sw a5,4(a0) + 3a8a: 459c lw a5,8(a1) + 3a8c: 4518 lw a4,8(a0) + 3a8e: 46b2 lw a3,12(sp) + 3a90: 8fb9 xor a5,a5,a4 + 3a92: 8ff5 and a5,a5,a3 + 3a94: 8fb9 xor a5,a5,a4 + 3a96: c51c sw a5,8(a0) + 3a98: 45dc lw a5,12(a1) + 3a9a: 4558 lw a4,12(a0) + 3a9c: 46b2 lw a3,12(sp) + 3a9e: 8fb9 xor a5,a5,a4 + 3aa0: 8ff5 and a5,a5,a3 + 3aa2: 8fb9 xor a5,a5,a4 + 3aa4: c55c sw a5,12(a0) + 3aa6: 4918 lw a4,16(a0) + 3aa8: 499c lw a5,16(a1) + 3aaa: 46b2 lw a3,12(sp) + 3aac: 8fb9 xor a5,a5,a4 + 3aae: 8ff5 and a5,a5,a3 + 3ab0: 8fb9 xor a5,a5,a4 + 3ab2: c91c sw a5,16(a0) + 3ab4: 4958 lw a4,20(a0) + 3ab6: 49dc lw a5,20(a1) + 3ab8: 46b2 lw a3,12(sp) + 3aba: 8fb9 xor a5,a5,a4 + 3abc: 8ff5 and a5,a5,a3 + 3abe: 8fb9 xor a5,a5,a4 + 3ac0: c95c sw a5,20(a0) + 3ac2: 4d18 lw a4,24(a0) + 3ac4: 4d9c lw a5,24(a1) + 3ac6: 46b2 lw a3,12(sp) + 3ac8: 8fb9 xor a5,a5,a4 + 3aca: 8ff5 and a5,a5,a3 + 3acc: 8fb9 xor a5,a5,a4 + 3ace: cd1c sw a5,24(a0) + 3ad0: 4d58 lw a4,28(a0) + 3ad2: 4ddc lw a5,28(a1) + 3ad4: 46b2 lw a3,12(sp) + 3ad6: 8fb9 xor a5,a5,a4 + 3ad8: 8ff5 and a5,a5,a3 + 3ada: 8fb9 xor a5,a5,a4 + 3adc: cd5c sw a5,28(a0) + 3ade: 5118 lw a4,32(a0) + 3ae0: 519c lw a5,32(a1) + 3ae2: 46b2 lw a3,12(sp) + 3ae4: 8fb9 xor a5,a5,a4 + 3ae6: 8ff5 and a5,a5,a3 + 3ae8: 8fb9 xor a5,a5,a4 + 3aea: d11c sw a5,32(a0) + 3aec: 5158 lw a4,36(a0) + 3aee: 51dc lw a5,36(a1) + 3af0: 46b2 lw a3,12(sp) + 3af2: 8fb9 xor a5,a5,a4 + 3af4: 8ff5 and a5,a5,a3 + 3af6: 8fb9 xor a5,a5,a4 + 3af8: d15c sw a5,36(a0) + 3afa: 0141 addi sp,sp,16 + 3afc: 8082 ret + +00003afe : + 3afe: ecafc2ef jal t0,1c8 <__riscv_save_10> + 3b02: 1141 addi sp,sp,-16 + 3b04: 84aa mv s1,a0 + 3b06: 852e mv a0,a1 + 3b08: 842e mv s0,a1 + 3b0a: c632 sw a2,12(sp) + 3b0c: cddff0ef jal ra,37e8 + 3b10: 8b2a mv s6,a0 + 3b12: 00440513 addi a0,s0,4 + 3b16: cc3ff0ef jal ra,37d8 + 3b1a: 00651d13 slli s10,a0,0x6 + 3b1e: 00740513 addi a0,s0,7 + 3b22: cb7ff0ef jal ra,37d8 + 3b26: 00551c13 slli s8,a0,0x5 + 3b2a: 00a40513 addi a0,s0,10 + 3b2e: cabff0ef jal ra,37d8 + 3b32: 00351b93 slli s7,a0,0x3 + 3b36: 00d40513 addi a0,s0,13 + 3b3a: c9fff0ef jal ra,37d8 + 3b3e: 00251a93 slli s5,a0,0x2 + 3b42: 01040513 addi a0,s0,16 + 3b46: ca3ff0ef jal ra,37e8 + 3b4a: 8caa mv s9,a0 + 3b4c: 01440513 addi a0,s0,20 + 3b50: c89ff0ef jal ra,37d8 + 3b54: 00751a13 slli s4,a0,0x7 + 3b58: 01740513 addi a0,s0,23 + 3b5c: c7dff0ef jal ra,37d8 + 3b60: 00551993 slli s3,a0,0x5 + 3b64: 01a40513 addi a0,s0,26 + 3b68: c71ff0ef jal ra,37d8 + 3b6c: 00451913 slli s2,a0,0x4 + 3b70: 01d40513 addi a0,s0,29 + 3b74: c65ff0ef jal ra,37d8 + 3b78: 4632 lw a2,12(sp) + 3b7a: 010007b7 lui a5,0x1000 + 3b7e: 02000737 lui a4,0x2000 + 3b82: fff78e93 addi t4,a5,-1 # ffffff <_data_lma+0xff1da3> + 3b86: 40cedeb3 sra t4,t4,a2 + 3b8a: 00eb0633 add a2,s6,a4 + 3b8e: 016636b3 sltu a3,a2,s6 + 3b92: 069a slli a3,a3,0x6 + 3b94: 8269 srli a2,a2,0x1a + 3b96: 8e55 or a2,a2,a3 + 3b98: 00cd05b3 add a1,s10,a2 + 3b9c: 00665393 srli t2,a2,0x6 + 3ba0: 01a61e13 slli t3,a2,0x1a + 3ba4: 00ea8633 add a2,s5,a4 + 3ba8: 015636b3 sltu a3,a2,s5 + 3bac: 00f58333 add t1,a1,a5 + 3bb0: 069a slli a3,a3,0x6 + 3bb2: 8269 srli a2,a2,0x1a + 3bb4: 8e55 or a2,a2,a3 + 3bb6: 01a5bd33 sltu s10,a1,s10 + 3bba: 00b336b3 sltu a3,t1,a1 + 3bbe: 41cb0e33 sub t3,s6,t3 + 3bc2: 96ea add a3,a3,s10 + 3bc4: 01cb3b33 sltu s6,s6,t3 + 3bc8: 069e slli a3,a3,0x7 + 3bca: 407003b3 neg t2,t2 + 3bce: 01935313 srli t1,t1,0x19 + 3bd2: 416383b3 sub t2,t2,s6 + 3bd6: 01a61893 slli a7,a2,0x1a + 3bda: 00665b13 srli s6,a2,0x6 + 3bde: 0066e333 or t1,a3,t1 + 3be2: 9666 add a2,a2,s9 + 3be4: 00f60833 add a6,a2,a5 + 3be8: 01931693 slli a3,t1,0x19 + 3bec: 9362 add t1,t1,s8 + 3bee: 00e302b3 add t0,t1,a4 + 3bf2: 01963cb3 sltu s9,a2,s9 + 3bf6: 00aefeb3 and t4,t4,a0 + 3bfa: 00c83533 sltu a0,a6,a2 + 3bfe: 8d95 sub a1,a1,a3 + 3c00: 9566 add a0,a0,s9 + 3c02: 018336b3 sltu a3,t1,s8 + 3c06: 0062bc33 sltu s8,t0,t1 + 3c0a: 051e slli a0,a0,0x7 + 3c0c: 9c36 add s8,s8,a3 + 3c0e: 01985813 srli a6,a6,0x19 + 3c12: 01056833 or a6,a0,a6 + 3c16: 0c1a slli s8,s8,0x6 + 3c18: 01a2d293 srli t0,t0,0x1a + 3c1c: 01981513 slli a0,a6,0x19 + 3c20: 005c62b3 or t0,s8,t0 + 3c24: 9852 add a6,a6,s4 + 3c26: 00e80f33 add t5,a6,a4 + 3c2a: 8e09 sub a2,a2,a0 + 3c2c: 01483533 sltu a0,a6,s4 + 3c30: 005b8a33 add s4,s7,t0 + 3c34: 00fa0fb3 add t6,s4,a5 + 3c38: 010f36b3 sltu a3,t5,a6 + 3c3c: 017a3cb3 sltu s9,s4,s7 + 3c40: 96aa add a3,a3,a0 + 3c42: 014fbbb3 sltu s7,t6,s4 + 3c46: 069a slli a3,a3,0x6 + 3c48: 9be6 add s7,s7,s9 + 3c4a: 01af5f13 srli t5,t5,0x1a + 3c4e: 01e6ef33 or t5,a3,t5 + 3c52: 0b9e slli s7,s7,0x7 + 3c54: 019fdf93 srli t6,t6,0x19 + 3c58: 01e98433 add s0,s3,t5 + 3c5c: 411a88b3 sub a7,s5,a7 + 3c60: 01fbefb3 or t6,s7,t6 + 3c64: 01343c33 sltu s8,s0,s3 + 3c68: 01f889b3 add s3,a7,t6 + 3c6c: 011abab3 sltu s5,s5,a7 + 3c70: 0119b6b3 sltu a3,s3,a7 + 3c74: 415686b3 sub a3,a3,s5 + 3c78: 416686b3 sub a3,a3,s6 + 3c7c: 00f40b33 add s6,s0,a5 + 3c80: 008b3533 sltu a0,s6,s0 + 3c84: 9562 add a0,a0,s8 + 3c86: 00e988b3 add a7,s3,a4 + 3c8a: 051e slli a0,a0,0x7 + 3c8c: 019b5b13 srli s6,s6,0x19 + 3c90: 01656b33 or s6,a0,s6 + 3c94: 0138b533 sltu a0,a7,s3 + 3c98: 96aa add a3,a3,a0 + 3c9a: 01690ab3 add s5,s2,s6 + 3c9e: 069a slli a3,a3,0x6 + 3ca0: 01a8d893 srli a7,a7,0x1a + 3ca4: 0116e8b3 or a7,a3,a7 + 3ca8: 00ea86b3 add a3,s5,a4 + 3cac: 012abbb3 sltu s7,s5,s2 + 3cb0: 0156b933 sltu s2,a3,s5 + 3cb4: 995e add s2,s2,s7 + 3cb6: 091a slli s2,s2,0x6 + 3cb8: 82e9 srli a3,a3,0x1a + 3cba: 0e8a slli t4,t4,0x2 + 3cbc: 00d966b3 or a3,s2,a3 + 3cc0: 00de8933 add s2,t4,a3 + 3cc4: 97ca add a5,a5,s2 + 3cc6: 01d93533 sltu a0,s2,t4 + 3cca: 0127beb3 sltu t4,a5,s2 + 3cce: 9eaa add t4,t4,a0 + 3cd0: 0e9e slli t4,t4,0x7 + 3cd2: 83e5 srli a5,a5,0x19 + 3cd4: 00fee7b3 or a5,t4,a5 + 3cd8: 4ecd li t4,19 + 3cda: 02fe8533 mul a0,t4,a5 + 3cde: 02ea slli t0,t0,0x1a + 3ce0: 0fe6 slli t6,t6,0x19 + 3ce2: 0f6a slli t5,t5,0x1a + 3ce4: 0b66 slli s6,s6,0x19 + 3ce6: 06ea slli a3,a3,0x1a + 3ce8: 41640433 sub s0,s0,s6 + 3cec: 40530333 sub t1,t1,t0 + 3cf0: 41fa0a33 sub s4,s4,t6 + 3cf4: 9646 add a2,a2,a7 + 3cf6: 02febeb3 mulhu t4,t4,a5 + 3cfa: 9e2a add t3,t3,a0 + 3cfc: 9772 add a4,a4,t3 + 3cfe: 00ae3533 sltu a0,t3,a0 + 3d02: 07e6 slli a5,a5,0x19 + 3d04: 41e80833 sub a6,a6,t5 + 3d08: 40da86b3 sub a3,s5,a3 + 3d0c: 40f907b3 sub a5,s2,a5 + 3d10: 0064a423 sw t1,8(s1) + 3d14: 0144a623 sw s4,12(s1) + 3d18: 93f6 add t2,t2,t4 + 3d1a: 951e add a0,a0,t2 + 3d1c: 01c733b3 sltu t2,a4,t3 + 3d20: 951e add a0,a0,t2 + 3d22: 051a slli a0,a0,0x6 + 3d24: 8369 srli a4,a4,0x1a + 3d26: 8f49 or a4,a4,a0 + 3d28: 01a71513 slli a0,a4,0x1a + 3d2c: 95ba add a1,a1,a4 + 3d2e: 01a89713 slli a4,a7,0x1a + 3d32: 40ae0e33 sub t3,t3,a0 + 3d36: 40e989b3 sub s3,s3,a4 + 3d3a: 01c4a023 sw t3,0(s1) + 3d3e: c0cc sw a1,4(s1) + 3d40: 0134a823 sw s3,16(s1) + 3d44: c8d0 sw a2,20(s1) + 3d46: 0104ac23 sw a6,24(s1) + 3d4a: ccc0 sw s0,28(s1) + 3d4c: d094 sw a3,32(s1) + 3d4e: d0dc sw a5,36(s1) + 3d50: 0141 addi sp,sp,16 + 3d52: caefc06f j 200 <__riscv_restore_10> + +00003d56 : + 3d56: 7179 addi sp,sp,-48 + 3d58: c06e sw s11,0(sp) + 3d5a: 0005ad83 lw s11,0(a1) + 3d5e: cc56 sw s5,24(sp) + 3d60: 0045a383 lw t2,4(a1) + 3d64: 03b60ab3 mul s5,a2,s11 + 3d68: 4994 lw a3,16(a1) + 3d6a: c26a sw s10,4(sp) + 3d6c: c466 sw s9,8(sp) + 3d6e: d622 sw s0,44(sp) + 3d70: d426 sw s1,40(sp) + 3d72: d24a sw s2,36(sp) + 3d74: d04e sw s3,32(sp) + 3d76: c85e sw s7,16(sp) + 3d78: 51dc lw a5,36(a1) + 3d7a: 03b61db3 mulh s11,a2,s11 + 3d7e: 0085a983 lw s3,8(a1) + 3d82: 45c4 lw s1,12(a1) + 3d84: 0145ab83 lw s7,20(a1) + 3d88: 0185a903 lw s2,24(a1) + 3d8c: 4dc0 lw s0,28(a1) + 3d8e: 0205a283 lw t0,32(a1) + 3d92: 020005b7 lui a1,0x2000 + 3d96: 00ba8733 add a4,s5,a1 + 3d9a: ca5a sw s6,20(sp) + 3d9c: 02760d33 mul s10,a2,t2 + 3da0: ce52 sw s4,28(sp) + 3da2: c662 sw s8,12(sp) + 3da4: 02d60cb3 mul s9,a2,a3 + 3da8: 027613b3 mulh t2,a2,t2 + 3dac: 02d616b3 mulh a3,a2,a3 + 3db0: 03360833 mul a6,a2,s3 + 3db4: 02960eb3 mul t4,a2,s1 + 3db8: 037608b3 mul a7,a2,s7 + 3dbc: 03260fb3 mul t6,a2,s2 + 3dc0: 02860f33 mul t5,a2,s0 + 3dc4: 02560333 mul t1,a2,t0 + 3dc8: 02f60b33 mul s6,a2,a5 + 3dcc: 03261933 mulh s2,a2,s2 + 3dd0: 033619b3 mulh s3,a2,s3 + 3dd4: 029614b3 mulh s1,a2,s1 + 3dd8: 03761bb3 mulh s7,a2,s7 + 3ddc: 02861433 mulh s0,a2,s0 + 3de0: 025612b3 mulh t0,a2,t0 + 3de4: 02f61633 mulh a2,a2,a5 + 3de8: 015737b3 sltu a5,a4,s5 + 3dec: 97ee add a5,a5,s11 + 3dee: 00679e13 slli t3,a5,0x6 + 3df2: 8369 srli a4,a4,0x1a + 3df4: 00ee6733 or a4,t3,a4 + 3df8: 87e9 srai a5,a5,0x1a + 3dfa: 00675e13 srli t3,a4,0x6 + 3dfe: 01a79c13 slli s8,a5,0x1a + 3e02: 01a71a13 slli s4,a4,0x1a + 3e06: 018e6c33 or s8,t3,s8 + 3e0a: 976a add a4,a4,s10 + 3e0c: 414a8a33 sub s4,s5,s4 + 3e10: 014abe33 sltu t3,s5,s4 + 3e14: 01a73d33 sltu s10,a4,s10 + 3e18: 418d8ab3 sub s5,s11,s8 + 3e1c: 00f38c33 add s8,t2,a5 + 3e20: 00bc87b3 add a5,s9,a1 + 3e24: 9c6a add s8,s8,s10 + 3e26: 0197bd33 sltu s10,a5,s9 + 3e2a: 9d36 add s10,s10,a3 + 3e2c: 41ca8ab3 sub s5,s5,t3 + 3e30: 83e9 srli a5,a5,0x1a + 3e32: 006d1e13 slli t3,s10,0x6 + 3e36: 00fe67b3 or a5,t3,a5 + 3e3a: 41ad5d13 srai s10,s10,0x1a + 3e3e: 0067d393 srli t2,a5,0x6 + 3e42: 01ad1e13 slli t3,s10,0x1a + 3e46: 01c3ee33 or t3,t2,t3 + 3e4a: 01a79393 slli t2,a5,0x1a + 3e4e: 97c6 add a5,a5,a7 + 3e50: 407c83b3 sub t2,s9,t2 + 3e54: 0117b8b3 sltu a7,a5,a7 + 3e58: 41c68e33 sub t3,a3,t3 + 3e5c: 9bea add s7,s7,s10 + 3e5e: 010006b7 lui a3,0x1000 + 3e62: 007cbcb3 sltu s9,s9,t2 + 3e66: 9bc6 add s7,s7,a7 + 3e68: 00d708b3 add a7,a4,a3 + 3e6c: 419e0e33 sub t3,t3,s9 + 3e70: 00e8bcb3 sltu s9,a7,a4 + 3e74: 9c66 add s8,s8,s9 + 3e76: 007c1c93 slli s9,s8,0x7 + 3e7a: 0198d893 srli a7,a7,0x19 + 3e7e: 011ce8b3 or a7,s9,a7 + 3e82: 01989c93 slli s9,a7,0x19 + 3e86: 419c5c13 srai s8,s8,0x19 + 3e8a: 98c2 add a7,a7,a6 + 3e8c: 0108b833 sltu a6,a7,a6 + 3e90: 99e2 add s3,s3,s8 + 3e92: 99c2 add s3,s3,a6 + 3e94: 00d78833 add a6,a5,a3 + 3e98: 00f83d33 sltu s10,a6,a5 + 3e9c: 9bea add s7,s7,s10 + 3e9e: 007b9c13 slli s8,s7,0x7 + 3ea2: 01985813 srli a6,a6,0x19 + 3ea6: 010c6833 or a6,s8,a6 + 3eaa: 01981c13 slli s8,a6,0x19 + 3eae: 419bdb93 srai s7,s7,0x19 + 3eb2: 987e add a6,a6,t6 + 3eb4: 01f83fb3 sltu t6,a6,t6 + 3eb8: 9bca add s7,s7,s2 + 3eba: 9bfe add s7,s7,t6 + 3ebc: 00b88fb3 add t6,a7,a1 + 3ec0: 418787b3 sub a5,a5,s8 + 3ec4: 011fbc33 sltu s8,t6,a7 + 3ec8: 99e2 add s3,s3,s8 + 3eca: 00699913 slli s2,s3,0x6 + 3ece: 01afdf93 srli t6,t6,0x1a + 3ed2: 01f96fb3 or t6,s2,t6 + 3ed6: 41a9d913 srai s2,s3,0x1a + 3eda: 01fe89b3 add s3,t4,t6 + 3ede: 01d9beb3 sltu t4,s3,t4 + 3ee2: 94ca add s1,s1,s2 + 3ee4: 009e8c33 add s8,t4,s1 + 3ee8: 00b80eb3 add t4,a6,a1 + 3eec: 010eb933 sltu s2,t4,a6 + 3ef0: 995e add s2,s2,s7 + 3ef2: 00691493 slli s1,s2,0x6 + 3ef6: 01aede93 srli t4,t4,0x1a + 3efa: 01d4eeb3 or t4,s1,t4 + 3efe: 01df04b3 add s1,t5,t4 + 3f02: 41a95913 srai s2,s2,0x1a + 3f06: 01e4bf33 sltu t5,s1,t5 + 3f0a: 944a add s0,s0,s2 + 3f0c: 008f0bb3 add s7,t5,s0 + 3f10: 00d98f33 add t5,s3,a3 + 3f14: 013f3433 sltu s0,t5,s3 + 3f18: 9462 add s0,s0,s8 + 3f1a: 00741913 slli s2,s0,0x7 + 3f1e: 019f5f13 srli t5,t5,0x19 + 3f22: 01e96f33 or t5,s2,t5 + 3f26: 01e38933 add s2,t2,t5 + 3f2a: 8465 srai s0,s0,0x19 + 3f2c: 9472 add s0,s0,t3 + 3f2e: 007933b3 sltu t2,s2,t2 + 3f32: 00d48e33 add t3,s1,a3 + 3f36: 93a2 add t2,t2,s0 + 3f38: 009e3433 sltu s0,t3,s1 + 3f3c: 945e add s0,s0,s7 + 3f3e: 00741b93 slli s7,s0,0x7 + 3f42: 019e5e13 srli t3,t3,0x19 + 3f46: 01cbee33 or t3,s7,t3 + 3f4a: 41945c13 srai s8,s0,0x19 + 3f4e: 01c30433 add s0,t1,t3 + 3f52: 00643333 sltu t1,s0,t1 + 3f56: 92e2 add t0,t0,s8 + 3f58: 00530bb3 add s7,t1,t0 + 3f5c: 00b902b3 add t0,s2,a1 + 3f60: 0122b333 sltu t1,t0,s2 + 3f64: 939a add t2,t2,t1 + 3f66: 039a slli t2,t2,0x6 + 3f68: 00b40333 add t1,s0,a1 + 3f6c: 01a2d293 srli t0,t0,0x1a + 3f70: 0053e2b3 or t0,t2,t0 + 3f74: 008333b3 sltu t2,t1,s0 + 3f78: 93de add t2,t2,s7 + 3f7a: 00639b93 slli s7,t2,0x6 + 3f7e: 01a35313 srli t1,t1,0x1a + 3f82: 006be333 or t1,s7,t1 + 3f86: 41a3db93 srai s7,t2,0x1a + 3f8a: 006b03b3 add t2,s6,t1 + 3f8e: 965e add a2,a2,s7 + 3f90: 969e add a3,a3,t2 + 3f92: 0163bb33 sltu s6,t2,s6 + 3f96: 9b32 add s6,s6,a2 + 3f98: 0076b633 sltu a2,a3,t2 + 3f9c: 965a add a2,a2,s6 + 3f9e: 00761b13 slli s6,a2,0x7 + 3fa2: 82e5 srli a3,a3,0x19 + 3fa4: 00db66b3 or a3,s6,a3 + 3fa8: 4bcd li s7,19 + 3faa: 8665 srai a2,a2,0x19 + 3fac: 02db8b33 mul s6,s7,a3 + 3fb0: 41970733 sub a4,a4,s9 + 3fb4: 0fea slli t6,t6,0x1a + 3fb6: 0f66 slli t5,t5,0x19 + 3fb8: 0eea slli t4,t4,0x1a + 3fba: 0e66 slli t3,t3,0x19 + 3fbc: 036a slli t1,t1,0x1a + 3fbe: 41e989b3 sub s3,s3,t5 + 3fc2: 41c484b3 sub s1,s1,t3 + 3fc6: 40640433 sub s0,s0,t1 + 3fca: 02cb8633 mul a2,s7,a2 + 3fce: 9a5a add s4,s4,s6 + 3fd0: 016a3b33 sltu s6,s4,s6 + 3fd4: 95d2 add a1,a1,s4 + 3fd6: 41f888b3 sub a7,a7,t6 + 3fda: 9796 add a5,a5,t0 + 3fdc: 41d80833 sub a6,a6,t4 + 3fe0: 01352623 sw s3,12(a0) + 3fe4: cd44 sw s1,28(a0) + 3fe6: 01152423 sw a7,8(a0) + 3fea: 02dbbbb3 mulhu s7,s7,a3 + 3fee: 06e6 slli a3,a3,0x19 + 3ff0: 40d386b3 sub a3,t2,a3 + 3ff4: c95c sw a5,20(a0) + 3ff6: 01052c23 sw a6,24(a0) + 3ffa: d100 sw s0,32(a0) + 3ffc: d154 sw a3,36(a0) + 3ffe: 965e add a2,a2,s7 + 4000: 9656 add a2,a2,s5 + 4002: 965a add a2,a2,s6 + 4004: 0145bb33 sltu s6,a1,s4 + 4008: 965a add a2,a2,s6 + 400a: 061a slli a2,a2,0x6 + 400c: 81e9 srli a1,a1,0x1a + 400e: 8dd1 or a1,a1,a2 + 4010: 01a59613 slli a2,a1,0x1a + 4014: 95ba add a1,a1,a4 + 4016: 01a29713 slli a4,t0,0x1a + 401a: 40ca0a33 sub s4,s4,a2 + 401e: 40e90933 sub s2,s2,a4 + 4022: 01452023 sw s4,0(a0) + 4026: 01252823 sw s2,16(a0) + 402a: c14c sw a1,4(a0) + 402c: 5432 lw s0,44(sp) + 402e: 54a2 lw s1,40(sp) + 4030: 5912 lw s2,36(sp) + 4032: 5982 lw s3,32(sp) + 4034: 4a72 lw s4,28(sp) + 4036: 4ae2 lw s5,24(sp) + 4038: 4b52 lw s6,20(sp) + 403a: 4bc2 lw s7,16(sp) + 403c: 4c32 lw s8,12(sp) + 403e: 4ca2 lw s9,8(sp) + 4040: 4d12 lw s10,4(sp) + 4042: 4d82 lw s11,0(sp) + 4044: 6145 addi sp,sp,48 + 4046: 8082 ret + +00004048 : + 4048: 45d8 lw a4,12(a1) + 404a: 7175 addi sp,sp,-144 + 404c: c722 sw s0,140(sp) + 404e: c43a sw a4,8(sp) + 4050: 49d8 lw a4,20(a1) + 4052: 4a40 lw s0,20(a2) + 4054: c526 sw s1,136(sp) + 4056: c63a sw a4,12(sp) + 4058: 4dd8 lw a4,28(a1) + 405a: c34a sw s2,132(sp) + 405c: c14e sw s3,128(sp) + 405e: c83a sw a4,16(sp) + 4060: 51d8 lw a4,36(a1) + 4062: ded2 sw s4,124(sp) + 4064: dcd6 sw s5,120(sp) + 4066: dada sw s6,116(sp) + 4068: d8de sw s7,112(sp) + 406a: d6e2 sw s8,108(sp) + 406c: d4e6 sw s9,104(sp) + 406e: d2ea sw s10,100(sp) + 4070: d0ee sw s11,96(sp) + 4072: ca3a sw a4,20(sp) + 4074: 0205a883 lw a7,32(a1) # 2000020 <_data_lma+0x1ff1dc4> + 4078: 419c lw a5,0(a1) + 407a: 0085a803 lw a6,8(a1) + 407e: 4994 lw a3,16(a1) + 4080: 0185a303 lw t1,24(a1) + 4084: 4218 lw a4,0(a2) + 4086: 00862e03 lw t3,8(a2) + 408a: 00c62f03 lw t5,12(a2) + 408e: 01062283 lw t0,16(a2) + 4092: 0045a903 lw s2,4(a1) + 4096: 424c lw a1,4(a2) + 4098: cc22 sw s0,24(sp) + 409a: 4e00 lw s0,24(a2) + 409c: 00191a13 slli s4,s2,0x1 + 40a0: 02e783b3 mul t2,a5,a4 + 40a4: d422 sw s0,40(sp) + 40a6: 4e40 lw s0,28(a2) + 40a8: d622 sw s0,44(sp) + 40aa: 5200 lw s0,32(a2) + 40ac: 5250 lw a2,36(a2) + 40ae: d822 sw s0,48(sp) + 40b0: dc32 sw a2,56(sp) + 40b2: 4622 lw a2,8(sp) + 40b4: 444d li s0,19 + 40b6: 02e79db3 mulh s11,a5,a4 + 40ba: 00161993 slli s3,a2,0x1 + 40be: 4632 lw a2,12(sp) + 40c0: 0606 slli a2,a2,0x1 + 40c2: ce32 sw a2,28(sp) + 40c4: 4642 lw a2,16(sp) + 40c6: 0606 slli a2,a2,0x1 + 40c8: d032 sw a2,32(sp) + 40ca: 4652 lw a2,20(sp) + 40cc: 02828bb3 mul s7,t0,s0 + 40d0: 0606 slli a2,a2,0x1 + 40d2: d232 sw a2,36(sp) + 40d4: 4662 lw a2,24(sp) + 40d6: 02860ab3 mul s5,a2,s0 + 40da: 5622 lw a2,40(sp) + 40dc: 028604b3 mul s1,a2,s0 + 40e0: 5632 lw a2,44(sp) + 40e2: 02860fb3 mul t6,a2,s0 + 40e6: 5642 lw a2,48(sp) + 40e8: 02860eb3 mul t4,a2,s0 + 40ec: 5662 lw a2,56(sp) + 40ee: 02860633 mul a2,a2,s0 + 40f2: 02ca0b33 mul s6,s4,a2 + 40f6: 02ca1d33 mulh s10,s4,a2 + 40fa: 9b1e add s6,s6,t2 + 40fc: 007b33b3 sltu t2,s6,t2 + 4100: 9d6e add s10,s10,s11 + 4102: 9d1e add s10,s10,t2 + 4104: 03d803b3 mul t2,a6,t4 + 4108: 03d81db3 mulh s11,a6,t4 + 410c: 93da add t2,t2,s6 + 410e: 0163bb33 sltu s6,t2,s6 + 4112: 9d6e add s10,s10,s11 + 4114: 9b6a add s6,s6,s10 + 4116: 03f98d33 mul s10,s3,t6 + 411a: 03f99db3 mulh s11,s3,t6 + 411e: 9d1e add s10,s10,t2 + 4120: 007d33b3 sltu t2,s10,t2 + 4124: 9b6e add s6,s6,s11 + 4126: 93da add t2,t2,s6 + 4128: 02968b33 mul s6,a3,s1 + 412c: 02969db3 mulh s11,a3,s1 + 4130: 9b6a add s6,s6,s10 + 4132: 01ab3d33 sltu s10,s6,s10 + 4136: 93ee add t2,t2,s11 + 4138: 9d1e add s10,s10,t2 + 413a: 43f2 lw t2,28(sp) + 413c: 4df2 lw s11,28(sp) + 413e: 028f0c33 mul s8,t5,s0 + 4142: 035383b3 mul t2,t2,s5 + 4146: 035d9db3 mulh s11,s11,s5 + 414a: 93da add t2,t2,s6 + 414c: 0163bb33 sltu s6,t2,s6 + 4150: 9d6e add s10,s10,s11 + 4152: 03730db3 mul s11,t1,s7 + 4156: 9b6a add s6,s6,s10 + 4158: 03731d33 mulh s10,t1,s7 + 415c: 9d9e add s11,s11,t2 + 415e: 007db3b3 sltu t2,s11,t2 + 4162: 9d5a add s10,s10,s6 + 4164: 9d1e add s10,s10,t2 + 4166: 5382 lw t2,32(sp) + 4168: 5b02 lw s6,32(sp) + 416a: 028e0cb3 mul s9,t3,s0 + 416e: 038383b3 mul t2,t2,s8 + 4172: 038b1b33 mulh s6,s6,s8 + 4176: 93ee add t2,t2,s11 + 4178: 01b3bdb3 sltu s11,t2,s11 + 417c: 9b6a add s6,s6,s10 + 417e: 03988d33 mul s10,a7,s9 + 4182: 9b6e add s6,s6,s11 + 4184: 03989db3 mulh s11,a7,s9 + 4188: 9d1e add s10,s10,t2 + 418a: 007d33b3 sltu t2,s10,t2 + 418e: 9b6e add s6,s6,s11 + 4190: 93da add t2,t2,s6 + 4192: 02858b33 mul s6,a1,s0 + 4196: 5d92 lw s11,36(sp) + 4198: de1e sw t2,60(sp) + 419a: 5392 lw t2,36(sp) + 419c: 03bb0db3 mul s11,s6,s11 + 41a0: 027b1b33 mulh s6,s6,t2 + 41a4: 01bd03b3 add t2,s10,s11 + 41a8: da1e sw t2,52(sp) + 41aa: 01a3bd33 sltu s10,t2,s10 + 41ae: 53f2 lw t2,60(sp) + 41b0: 9b1e add s6,s6,t2 + 41b2: 016d03b3 add t2,s10,s6 + 41b6: c29e sw t2,68(sp) + 41b8: 02b78b33 mul s6,a5,a1 + 41bc: 032703b3 mul t2,a4,s2 + 41c0: 02b79db3 mulh s11,a5,a1 + 41c4: 93da add t2,t2,s6 + 41c6: 0163bb33 sltu s6,t2,s6 + 41ca: 03271d33 mulh s10,a4,s2 + 41ce: 9d6e add s10,s10,s11 + 41d0: 9d5a add s10,s10,s6 + 41d2: 03060b33 mul s6,a2,a6 + 41d6: 03061db3 mulh s11,a2,a6 + 41da: 9b1e add s6,s6,t2 + 41dc: 007b33b3 sltu t2,s6,t2 + 41e0: 9d6e add s10,s10,s11 + 41e2: 93ea add t2,t2,s10 + 41e4: 4d22 lw s10,8(sp) + 41e6: 4da2 lw s11,8(sp) + 41e8: 03ae8d33 mul s10,t4,s10 + 41ec: 03be9db3 mulh s11,t4,s11 + 41f0: 9d5a add s10,s10,s6 + 41f2: 016d3b33 sltu s6,s10,s6 + 41f6: 93ee add t2,t2,s11 + 41f8: 02df8db3 mul s11,t6,a3 + 41fc: 93da add t2,t2,s6 + 41fe: 02df9b33 mulh s6,t6,a3 + 4202: 9dea add s11,s11,s10 + 4204: 01adbd33 sltu s10,s11,s10 + 4208: 93da add t2,t2,s6 + 420a: 9d1e add s10,s10,t2 + 420c: 43b2 lw t2,12(sp) + 420e: 02748b33 mul s6,s1,t2 + 4212: 027493b3 mulh t2,s1,t2 + 4216: 9b6e add s6,s6,s11 + 4218: 01bb3db3 sltu s11,s6,s11 + 421c: 9d1e add s10,s10,t2 + 421e: 026a83b3 mul t2,s5,t1 + 4222: 9dea add s11,s11,s10 + 4224: 026a9d33 mulh s10,s5,t1 + 4228: 93da add t2,t2,s6 + 422a: 0163bb33 sltu s6,t2,s6 + 422e: 9dea add s11,s11,s10 + 4230: 4d42 lw s10,16(sp) + 4232: 9b6e add s6,s6,s11 + 4234: 4dc2 lw s11,16(sp) + 4236: 03ab8d33 mul s10,s7,s10 + 423a: 03bb9db3 mulh s11,s7,s11 + 423e: 9d1e add s10,s10,t2 + 4240: 007d33b3 sltu t2,s10,t2 + 4244: 9b6e add s6,s6,s11 + 4246: 93da add t2,t2,s6 + 4248: 031c0b33 mul s6,s8,a7 + 424c: 031c1db3 mulh s11,s8,a7 + 4250: 9b6a add s6,s6,s10 + 4252: 01ab3d33 sltu s10,s6,s10 + 4256: 93ee add t2,t2,s11 + 4258: 9d1e add s10,s10,t2 + 425a: 43d2 lw t2,20(sp) + 425c: 4dd2 lw s11,20(sp) + 425e: 027c83b3 mul t2,s9,t2 + 4262: 03bc9cb3 mulh s9,s9,s11 + 4266: 93da add t2,t2,s6 + 4268: 0163bb33 sltu s6,t2,s6 + 426c: de1e sw t2,60(sp) + 426e: 9d66 add s10,s10,s9 + 4270: 01ab03b3 add t2,s6,s10 + 4274: 03c78cb3 mul s9,a5,t3 + 4278: c69e sw t2,76(sp) + 427a: 02ba0b33 mul s6,s4,a1 + 427e: 03c79d33 mulh s10,a5,t3 + 4282: 9b66 add s6,s6,s9 + 4284: 019b3cb3 sltu s9,s6,s9 + 4288: 02ba1db3 mulh s11,s4,a1 + 428c: 01bd03b3 add t2,s10,s11 + 4290: 03070d33 mul s10,a4,a6 + 4294: 93e6 add t2,t2,s9 + 4296: 03071cb3 mulh s9,a4,a6 + 429a: 9d5a add s10,s10,s6 + 429c: 016d3b33 sltu s6,s10,s6 + 42a0: 03360db3 mul s11,a2,s3 + 42a4: 93e6 add t2,t2,s9 + 42a6: 93da add t2,t2,s6 + 42a8: 03361b33 mulh s6,a2,s3 + 42ac: 9dea add s11,s11,s10 + 42ae: 01adbd33 sltu s10,s11,s10 + 42b2: 02de8cb3 mul s9,t4,a3 + 42b6: 93da add t2,t2,s6 + 42b8: 93ea add t2,t2,s10 + 42ba: 02de9d33 mulh s10,t4,a3 + 42be: 9cee add s9,s9,s11 + 42c0: 01bcbdb3 sltu s11,s9,s11 + 42c4: 93ea add t2,t2,s10 + 42c6: 9d9e add s11,s11,t2 + 42c8: 43f2 lw t2,28(sp) + 42ca: 027f9d33 mulh s10,t6,t2 + 42ce: 027f8b33 mul s6,t6,t2 + 42d2: 9dea add s11,s11,s10 + 42d4: 026483b3 mul t2,s1,t1 + 42d8: 9b66 add s6,s6,s9 + 42da: 019b3cb3 sltu s9,s6,s9 + 42de: 9cee add s9,s9,s11 + 42e0: 02649d33 mulh s10,s1,t1 + 42e4: 93da add t2,t2,s6 + 42e6: 0163bb33 sltu s6,t2,s6 + 42ea: 9cea add s9,s9,s10 + 42ec: 9b66 add s6,s6,s9 + 42ee: 5c82 lw s9,32(sp) + 42f0: 039a8d33 mul s10,s5,s9 + 42f4: 039a9cb3 mulh s9,s5,s9 + 42f8: 9d1e add s10,s10,t2 + 42fa: 007d33b3 sltu t2,s10,t2 + 42fe: 9b66 add s6,s6,s9 + 4300: 93da add t2,t2,s6 + 4302: 031b8b33 mul s6,s7,a7 + 4306: 031b9cb3 mulh s9,s7,a7 + 430a: 9b6a add s6,s6,s10 + 430c: 01ab3d33 sltu s10,s6,s10 + 4310: 93e6 add t2,t2,s9 + 4312: 9d1e add s10,s10,t2 + 4314: 5392 lw t2,36(sp) + 4316: 03e79cb3 mulh s9,a5,t5 + 431a: 027c0db3 mul s11,s8,t2 + 431e: 027c1c33 mulh s8,s8,t2 + 4322: 9dda add s11,s11,s6 + 4324: 016dbb33 sltu s6,s11,s6 + 4328: 9d62 add s10,s10,s8 + 432a: 01ab03b3 add t2,s6,s10 + 432e: 03e78c33 mul s8,a5,t5 + 4332: c89e sw t2,80(sp) + 4334: 03c90b33 mul s6,s2,t3 + 4338: 03c91d33 mulh s10,s2,t3 + 433c: 9b62 add s6,s6,s8 + 433e: 018b3c33 sltu s8,s6,s8 + 4342: 01ac83b3 add t2,s9,s10 + 4346: 02b80cb3 mul s9,a6,a1 + 434a: 93e2 add t2,t2,s8 + 434c: 02b81c33 mulh s8,a6,a1 + 4350: 9cda add s9,s9,s6 + 4352: 016cbb33 sltu s6,s9,s6 + 4356: 93e2 add t2,t2,s8 + 4358: 93da add t2,t2,s6 + 435a: 4b22 lw s6,8(sp) + 435c: 02d60c33 mul s8,a2,a3 + 4360: 03670d33 mul s10,a4,s6 + 4364: 03671b33 mulh s6,a4,s6 + 4368: 9d66 add s10,s10,s9 + 436a: 019d3cb3 sltu s9,s10,s9 + 436e: 9c6a add s8,s8,s10 + 4370: 01ac3d33 sltu s10,s8,s10 + 4374: 93da add t2,t2,s6 + 4376: 93e6 add t2,t2,s9 + 4378: 02d61cb3 mulh s9,a2,a3 + 437c: 93e6 add t2,t2,s9 + 437e: 9d1e add s10,s10,t2 + 4380: 43b2 lw t2,12(sp) + 4382: 027e9cb3 mulh s9,t4,t2 + 4386: 027e8b33 mul s6,t4,t2 + 438a: 9d66 add s10,s10,s9 + 438c: 026f83b3 mul t2,t6,t1 + 4390: 9b62 add s6,s6,s8 + 4392: 018b3c33 sltu s8,s6,s8 + 4396: 9c6a add s8,s8,s10 + 4398: 026f9cb3 mulh s9,t6,t1 + 439c: 93da add t2,t2,s6 + 439e: 0163bb33 sltu s6,t2,s6 + 43a2: 9c66 add s8,s8,s9 + 43a4: 9b62 add s6,s6,s8 + 43a6: 4c42 lw s8,16(sp) + 43a8: 03848cb3 mul s9,s1,s8 + 43ac: 03849c33 mulh s8,s1,s8 + 43b0: 9c9e add s9,s9,t2 + 43b2: 007cb3b3 sltu t2,s9,t2 + 43b6: 9b62 add s6,s6,s8 + 43b8: 93da add t2,t2,s6 + 43ba: 031a8b33 mul s6,s5,a7 + 43be: 031a9c33 mulh s8,s5,a7 + 43c2: 9b66 add s6,s6,s9 + 43c4: 019b3cb3 sltu s9,s6,s9 + 43c8: 93e2 add t2,t2,s8 + 43ca: 9c9e add s9,s9,t2 + 43cc: 43d2 lw t2,20(sp) + 43ce: 02579c33 mulh s8,a5,t0 + 43d2: 027b8d33 mul s10,s7,t2 + 43d6: 027b9bb3 mulh s7,s7,t2 + 43da: 01ab03b3 add t2,s6,s10 + 43de: 0163bb33 sltu s6,t2,s6 + 43e2: c09e sw t2,64(sp) + 43e4: 9cde add s9,s9,s7 + 43e6: 019b03b3 add t2,s6,s9 + 43ea: 02578bb3 mul s7,a5,t0 + 43ee: ca9e sw t2,84(sp) + 43f0: 03ea0b33 mul s6,s4,t5 + 43f4: 03ea1cb3 mulh s9,s4,t5 + 43f8: 9b5e add s6,s6,s7 + 43fa: 017b3bb3 sltu s7,s6,s7 + 43fe: 019c03b3 add t2,s8,s9 + 4402: 03c80c33 mul s8,a6,t3 + 4406: 93de add t2,t2,s7 + 4408: 03c81bb3 mulh s7,a6,t3 + 440c: 9c5a add s8,s8,s6 + 440e: 016c3b33 sltu s6,s8,s6 + 4412: 02b98cb3 mul s9,s3,a1 + 4416: 93de add t2,t2,s7 + 4418: 93da add t2,t2,s6 + 441a: 02b99b33 mulh s6,s3,a1 + 441e: 9ce2 add s9,s9,s8 + 4420: 018cbc33 sltu s8,s9,s8 + 4424: 02d70bb3 mul s7,a4,a3 + 4428: 93da add t2,t2,s6 + 442a: 93e2 add t2,t2,s8 + 442c: 02d71c33 mulh s8,a4,a3 + 4430: 9be6 add s7,s7,s9 + 4432: 019bbcb3 sltu s9,s7,s9 + 4436: 93e2 add t2,t2,s8 + 4438: 9c9e add s9,s9,t2 + 443a: 43f2 lw t2,28(sp) + 443c: 02761c33 mulh s8,a2,t2 + 4440: 02760b33 mul s6,a2,t2 + 4444: 9ce2 add s9,s9,s8 + 4446: 026e83b3 mul t2,t4,t1 + 444a: 9b5e add s6,s6,s7 + 444c: 017b3bb3 sltu s7,s6,s7 + 4450: 9be6 add s7,s7,s9 + 4452: 026e9c33 mulh s8,t4,t1 + 4456: 93da add t2,t2,s6 + 4458: 0163bb33 sltu s6,t2,s6 + 445c: 9be2 add s7,s7,s8 + 445e: 9b5e add s6,s6,s7 + 4460: 5b82 lw s7,32(sp) + 4462: 037f8c33 mul s8,t6,s7 + 4466: 037f9bb3 mulh s7,t6,s7 + 446a: 9c1e add s8,s8,t2 + 446c: 007c33b3 sltu t2,s8,t2 + 4470: 9b5e add s6,s6,s7 + 4472: 93da add t2,t2,s6 + 4474: 03148b33 mul s6,s1,a7 + 4478: 03149bb3 mulh s7,s1,a7 + 447c: 9b62 add s6,s6,s8 + 447e: 018b3c33 sltu s8,s6,s8 + 4482: 93de add t2,t2,s7 + 4484: 9c1e add s8,s8,t2 + 4486: 5392 lw t2,36(sp) + 4488: 027a8cb3 mul s9,s5,t2 + 448c: 027a9ab3 mulh s5,s5,t2 + 4490: 9cda add s9,s9,s6 + 4492: 016cbb33 sltu s6,s9,s6 + 4496: 9c56 add s8,s8,s5 + 4498: 018b03b3 add t2,s6,s8 + 449c: c49e sw t2,72(sp) + 449e: 43e2 lw t2,24(sp) + 44a0: 02590ab3 mul s5,s2,t0 + 44a4: 02778b33 mul s6,a5,t2 + 44a8: 02591c33 mulh s8,s2,t0 + 44ac: 9ada add s5,s5,s6 + 44ae: 016abb33 sltu s6,s5,s6 + 44b2: 02779bb3 mulh s7,a5,t2 + 44b6: 018b83b3 add t2,s7,s8 + 44ba: 03e80bb3 mul s7,a6,t5 + 44be: 93da add t2,t2,s6 + 44c0: 03e81b33 mulh s6,a6,t5 + 44c4: 9bd6 add s7,s7,s5 + 44c6: 015bbab3 sltu s5,s7,s5 + 44ca: 93da add t2,t2,s6 + 44cc: 93d6 add t2,t2,s5 + 44ce: 4aa2 lw s5,8(sp) + 44d0: 02b68b33 mul s6,a3,a1 + 44d4: 03ca8c33 mul s8,s5,t3 + 44d8: 03ca9ab3 mulh s5,s5,t3 + 44dc: 9c5e add s8,s8,s7 + 44de: 017c3bb3 sltu s7,s8,s7 + 44e2: 9b62 add s6,s6,s8 + 44e4: 018b3c33 sltu s8,s6,s8 + 44e8: 93d6 add t2,t2,s5 + 44ea: 93de add t2,t2,s7 + 44ec: 02b69bb3 mulh s7,a3,a1 + 44f0: 93de add t2,t2,s7 + 44f2: 9c1e add s8,s8,t2 + 44f4: 43b2 lw t2,12(sp) + 44f6: 02771bb3 mulh s7,a4,t2 + 44fa: 02770ab3 mul s5,a4,t2 + 44fe: 9c5e add s8,s8,s7 + 4500: 026603b3 mul t2,a2,t1 + 4504: 9ada add s5,s5,s6 + 4506: 016abb33 sltu s6,s5,s6 + 450a: 9b62 add s6,s6,s8 + 450c: 02661bb3 mulh s7,a2,t1 + 4510: 93d6 add t2,t2,s5 + 4512: 0153bab3 sltu s5,t2,s5 + 4516: 9b5e add s6,s6,s7 + 4518: 9ada add s5,s5,s6 + 451a: 4b42 lw s6,16(sp) + 451c: 036e8bb3 mul s7,t4,s6 + 4520: 036e9b33 mulh s6,t4,s6 + 4524: 9b9e add s7,s7,t2 + 4526: 007bb3b3 sltu t2,s7,t2 + 452a: 9ada add s5,s5,s6 + 452c: 93d6 add t2,t2,s5 + 452e: 031f8ab3 mul s5,t6,a7 + 4532: 031f9b33 mulh s6,t6,a7 + 4536: 9ade add s5,s5,s7 + 4538: 017abbb3 sltu s7,s5,s7 + 453c: 93da add t2,t2,s6 + 453e: 9b9e add s7,s7,t2 + 4540: 43d2 lw t2,20(sp) + 4542: 02748c33 mul s8,s1,t2 + 4546: 027494b3 mulh s1,s1,t2 + 454a: 018a8d33 add s10,s5,s8 + 454e: 015d3ab3 sltu s5,s10,s5 + 4552: 43e2 lw t2,24(sp) + 4554: 9ba6 add s7,s7,s1 + 4556: 017a84b3 add s1,s5,s7 + 455a: cca6 sw s1,88(sp) + 455c: 54a2 lw s1,40(sp) + 455e: 027a1bb3 mulh s7,s4,t2 + 4562: 02978ab3 mul s5,a5,s1 + 4566: 02979b33 mulh s6,a5,s1 + 456a: 44e2 lw s1,24(sp) + 456c: 029a04b3 mul s1,s4,s1 + 4570: 017b03b3 add t2,s6,s7 + 4574: 94d6 add s1,s1,s5 + 4576: 0154bab3 sltu s5,s1,s5 + 457a: 93d6 add t2,t2,s5 + 457c: 02580ab3 mul s5,a6,t0 + 4580: 02581b33 mulh s6,a6,t0 + 4584: 9aa6 add s5,s5,s1 + 4586: 009ab4b3 sltu s1,s5,s1 + 458a: 93da add t2,t2,s6 + 458c: 93a6 add t2,t2,s1 + 458e: 03e994b3 mulh s1,s3,t5 + 4592: 03e98b33 mul s6,s3,t5 + 4596: 93a6 add t2,t2,s1 + 4598: 03c684b3 mul s1,a3,t3 + 459c: 9b56 add s6,s6,s5 + 459e: 015b3ab3 sltu s5,s6,s5 + 45a2: 93d6 add t2,t2,s5 + 45a4: 4af2 lw s5,28(sp) + 45a6: 03c69c33 mulh s8,a3,t3 + 45aa: 94da add s1,s1,s6 + 45ac: 0164bb33 sltu s6,s1,s6 + 45b0: 93e2 add t2,t2,s8 + 45b2: 9b1e add s6,s6,t2 + 45b4: 43f2 lw t2,28(sp) + 45b6: 02ba9c33 mulh s8,s5,a1 + 45ba: 02b383b3 mul t2,t2,a1 + 45be: 9b62 add s6,s6,s8 + 45c0: 93a6 add t2,t2,s1 + 45c2: 0093b4b3 sltu s1,t2,s1 + 45c6: 01648bb3 add s7,s1,s6 + 45ca: 02670b33 mul s6,a4,t1 + 45ce: 5482 lw s1,32(sp) + 45d0: 02671c33 mulh s8,a4,t1 + 45d4: 9b1e add s6,s6,t2 + 45d6: 007b33b3 sltu t2,s6,t2 + 45da: 018b8ab3 add s5,s7,s8 + 45de: 9a9e add s5,s5,t2 + 45e0: 029603b3 mul t2,a2,s1 + 45e4: 02961bb3 mulh s7,a2,s1 + 45e8: 93da add t2,t2,s6 + 45ea: 0163bb33 sltu s6,t2,s6 + 45ee: 017a84b3 add s1,s5,s7 + 45f2: 031e8ab3 mul s5,t4,a7 + 45f6: 94da add s1,s1,s6 + 45f8: 031e9b33 mulh s6,t4,a7 + 45fc: 9a9e add s5,s5,t2 + 45fe: 007ab3b3 sltu t2,s5,t2 + 4602: 94da add s1,s1,s6 + 4604: 93a6 add t2,t2,s1 + 4606: 5492 lw s1,36(sp) + 4608: 5b12 lw s6,36(sp) + 460a: 029f84b3 mul s1,t6,s1 + 460e: 036f9fb3 mulh t6,t6,s6 + 4612: 94d6 add s1,s1,s5 + 4614: 0154bab3 sltu s5,s1,s5 + 4618: 9f9e add t6,t6,t2 + 461a: 01fa8c33 add s8,s5,t6 + 461e: 5fb2 lw t6,44(sp) + 4620: 5aa2 lw s5,40(sp) + 4622: 03f783b3 mul t2,a5,t6 + 4626: 03f79b33 mulh s6,a5,t6 + 462a: 5fa2 lw t6,40(sp) + 462c: 03f90fb3 mul t6,s2,t6 + 4630: 03591bb3 mulh s7,s2,s5 + 4634: 9f9e add t6,t6,t2 + 4636: 007fb3b3 sltu t2,t6,t2 + 463a: 017b0ab3 add s5,s6,s7 + 463e: 9a9e add s5,s5,t2 + 4640: 43e2 lw t2,24(sp) + 4642: 4b62 lw s6,24(sp) + 4644: 027803b3 mul t2,a6,t2 + 4648: 03681b33 mulh s6,a6,s6 + 464c: 93fe add t2,t2,t6 + 464e: 01f3bfb3 sltu t6,t2,t6 + 4652: 9ada add s5,s5,s6 + 4654: 9fd6 add t6,t6,s5 + 4656: 4aa2 lw s5,8(sp) + 4658: 4b22 lw s6,8(sp) + 465a: 025a8ab3 mul s5,s5,t0 + 465e: 025b1b33 mulh s6,s6,t0 + 4662: 9a9e add s5,s5,t2 + 4664: 007ab3b3 sltu t2,s5,t2 + 4668: 9fda add t6,t6,s6 + 466a: 03e68b33 mul s6,a3,t5 + 466e: 9f9e add t6,t6,t2 + 4670: 03e693b3 mulh t2,a3,t5 + 4674: 9b56 add s6,s6,s5 + 4676: 015b3ab3 sltu s5,s6,s5 + 467a: 9f9e add t6,t6,t2 + 467c: 9afe add s5,s5,t6 + 467e: 4fb2 lw t6,12(sp) + 4680: 03cf83b3 mul t2,t6,t3 + 4684: 03cf9bb3 mulh s7,t6,t3 + 4688: 93da add t2,t2,s6 + 468a: 0163bb33 sltu s6,t2,s6 + 468e: 9ade add s5,s5,s7 + 4690: 02b30fb3 mul t6,t1,a1 + 4694: 9b56 add s6,s6,s5 + 4696: 02b31ab3 mulh s5,t1,a1 + 469a: 9f9e add t6,t6,t2 + 469c: 007fb3b3 sltu t2,t6,t2 + 46a0: 9b56 add s6,s6,s5 + 46a2: 4ac2 lw s5,16(sp) + 46a4: 93da add t2,t2,s6 + 46a6: 4b42 lw s6,16(sp) + 46a8: 03570ab3 mul s5,a4,s5 + 46ac: 03671b33 mulh s6,a4,s6 + 46b0: 9afe add s5,s5,t6 + 46b2: 01fabfb3 sltu t6,s5,t6 + 46b6: 93da add t2,t2,s6 + 46b8: 9f9e add t6,t6,t2 + 46ba: 031603b3 mul t2,a2,a7 + 46be: 03161b33 mulh s6,a2,a7 + 46c2: 93d6 add t2,t2,s5 + 46c4: 0153bab3 sltu s5,t2,s5 + 46c8: 9fda add t6,t6,s6 + 46ca: 9afe add s5,s5,t6 + 46cc: 4fd2 lw t6,20(sp) + 46ce: 03fe8bb3 mul s7,t4,t6 + 46d2: 03fe9eb3 mulh t4,t4,t6 + 46d6: 9b9e add s7,s7,t2 + 46d8: 5fc2 lw t6,48(sp) + 46da: 007bb3b3 sltu t2,s7,t2 + 46de: 9af6 add s5,s5,t4 + 46e0: 01538eb3 add t4,t2,s5 + 46e4: cef6 sw t4,92(sp) + 46e6: 03f793b3 mulh t2,a5,t6 + 46ea: 5ec2 lw t4,48(sp) + 46ec: 5fb2 lw t6,44(sp) + 46ee: 5ab2 lw s5,44(sp) + 46f0: 03d78eb3 mul t4,a5,t4 + 46f4: 03fa0fb3 mul t6,s4,t6 + 46f8: 035a1a33 mulh s4,s4,s5 + 46fc: 9ff6 add t6,t6,t4 + 46fe: 01dfbeb3 sltu t4,t6,t4 + 4702: 9a1e add s4,s4,t2 + 4704: 014e83b3 add t2,t4,s4 + 4708: 5ea2 lw t4,40(sp) + 470a: 02568a33 mul s4,a3,t0 + 470e: 03d80ab3 mul s5,a6,t4 + 4712: 03d81eb3 mulh t4,a6,t4 + 4716: 9afe add s5,s5,t6 + 4718: 01fabfb3 sltu t6,s5,t6 + 471c: 93f6 add t2,t2,t4 + 471e: 4ee2 lw t4,24(sp) + 4720: 9f9e add t6,t6,t2 + 4722: 03c303b3 mul t2,t1,t3 + 4726: 03d98b33 mul s6,s3,t4 + 472a: 03d999b3 mulh s3,s3,t4 + 472e: 9b56 add s6,s6,s5 + 4730: 015b3ab3 sltu s5,s6,s5 + 4734: 9a5a add s4,s4,s6 + 4736: 016a3b33 sltu s6,s4,s6 + 473a: 4ef2 lw t4,28(sp) + 473c: 9fce add t6,t6,s3 + 473e: 025699b3 mulh s3,a3,t0 + 4742: 9fd6 add t6,t6,s5 + 4744: 9fce add t6,t6,s3 + 4746: 9b7e add s6,s6,t6 + 4748: 4ff2 lw t6,28(sp) + 474a: 03ee8eb3 mul t4,t4,t5 + 474e: 03ef9fb3 mulh t6,t6,t5 + 4752: 9ed2 add t4,t4,s4 + 4754: 014eba33 sltu s4,t4,s4 + 4758: 93f6 add t2,t2,t4 + 475a: 01d3beb3 sltu t4,t2,t4 + 475e: 9b7e add s6,s6,t6 + 4760: 03c31fb3 mulh t6,t1,t3 + 4764: 9b52 add s6,s6,s4 + 4766: 9b7e add s6,s6,t6 + 4768: 5f82 lw t6,32(sp) + 476a: 03170a33 mul s4,a4,a7 + 476e: 9eda add t4,t4,s6 + 4770: 02bf89b3 mul s3,t6,a1 + 4774: 02bf9fb3 mulh t6,t6,a1 + 4778: 999e add s3,s3,t2 + 477a: 0079b3b3 sltu t2,s3,t2 + 477e: 9a4e add s4,s4,s3 + 4780: 013a39b3 sltu s3,s4,s3 + 4784: 9efe add t4,t4,t6 + 4786: 03171fb3 mulh t6,a4,a7 + 478a: 9e9e add t4,t4,t2 + 478c: 53c2 lw t2,48(sp) + 478e: 9efe add t4,t4,t6 + 4790: 99f6 add s3,s3,t4 + 4792: 5e92 lw t4,36(sp) + 4794: 5fe2 lw t6,56(sp) + 4796: 03d60ab3 mul s5,a2,t4 + 479a: 03d61633 mulh a2,a2,t4 + 479e: 015a0eb3 add t4,s4,s5 + 47a2: 014eba33 sltu s4,t4,s4 + 47a6: 99b2 add s3,s3,a2 + 47a8: 5662 lw a2,56(sp) + 47aa: 99d2 add s3,s3,s4 + 47ac: 02c78633 mul a2,a5,a2 + 47b0: 03f797b3 mulh a5,a5,t6 + 47b4: 5fc2 lw t6,48(sp) + 47b6: 03f90fb3 mul t6,s2,t6 + 47ba: 02791933 mulh s2,s2,t2 + 47be: 9fb2 add t6,t6,a2 + 47c0: 00cfb633 sltu a2,t6,a2 + 47c4: 97ca add a5,a5,s2 + 47c6: 963e add a2,a2,a5 + 47c8: 57b2 lw a5,44(sp) + 47ca: 02f803b3 mul t2,a6,a5 + 47ce: 02f81833 mulh a6,a6,a5 + 47d2: 93fe add t2,t2,t6 + 47d4: 01f3bfb3 sltu t6,t2,t6 + 47d8: 47a2 lw a5,8(sp) + 47da: 9642 add a2,a2,a6 + 47dc: 9fb2 add t6,t6,a2 + 47de: 5622 lw a2,40(sp) + 47e0: 02c787b3 mul a5,a5,a2 + 47e4: 4622 lw a2,8(sp) + 47e6: 5822 lw a6,40(sp) + 47e8: 03061633 mulh a2,a2,a6 + 47ec: 979e add a5,a5,t2 + 47ee: 0077b3b3 sltu t2,a5,t2 + 47f2: 9fb2 add t6,t6,a2 + 47f4: 4662 lw a2,24(sp) + 47f6: 93fe add t2,t2,t6 + 47f8: 02c68833 mul a6,a3,a2 + 47fc: 02c696b3 mulh a3,a3,a2 + 4800: 983e add a6,a6,a5 + 4802: 00f837b3 sltu a5,a6,a5 + 4806: 93b6 add t2,t2,a3 + 4808: 46b2 lw a3,12(sp) + 480a: 979e add a5,a5,t2 + 480c: 02568633 mul a2,a3,t0 + 4810: 025692b3 mulh t0,a3,t0 + 4814: 9642 add a2,a2,a6 + 4816: 01063833 sltu a6,a2,a6 + 481a: 9796 add a5,a5,t0 + 481c: 983e add a6,a6,a5 + 481e: 47c2 lw a5,16(sp) + 4820: 03e306b3 mul a3,t1,t5 + 4824: 03e31333 mulh t1,t1,t5 + 4828: 96b2 add a3,a3,a2 + 482a: 00c6b633 sltu a2,a3,a2 + 482e: 03c78fb3 mul t6,a5,t3 + 4832: 981a add a6,a6,t1 + 4834: 9642 add a2,a2,a6 + 4836: 03c79e33 mulh t3,a5,t3 + 483a: 9fb6 add t6,t6,a3 + 483c: 00dfb6b3 sltu a3,t6,a3 + 4840: 02b887b3 mul a5,a7,a1 + 4844: 9672 add a2,a2,t3 + 4846: 96b2 add a3,a3,a2 + 4848: 4616 lw a2,68(sp) + 484a: 4e26 lw t3,72(sp) + 484c: 02b895b3 mulh a1,a7,a1 + 4850: 97fe add a5,a5,t6 + 4852: 01f7bfb3 sltu t6,a5,t6 + 4856: 4896 lw a7,68(sp) + 4858: 96ae add a3,a3,a1 + 485a: 9fb6 add t6,t6,a3 + 485c: 46d2 lw a3,20(sp) + 485e: 02d70333 mul t1,a4,a3 + 4862: 02d71733 mulh a4,a4,a3 + 4866: 933e add t1,t1,a5 + 4868: 00f337b3 sltu a5,t1,a5 + 486c: 977e add a4,a4,t6 + 486e: 00e78833 add a6,a5,a4 + 4872: 57d2 lw a5,52(sp) + 4874: 02000737 lui a4,0x2000 + 4878: 00e786b3 add a3,a5,a4 + 487c: 00f6b7b3 sltu a5,a3,a5 + 4880: 97b2 add a5,a5,a2 + 4882: 00679613 slli a2,a5,0x6 + 4886: 82e9 srli a3,a3,0x1a + 4888: 8ed1 or a3,a3,a2 + 488a: 87e9 srai a5,a5,0x1a + 488c: 0066d613 srli a2,a3,0x6 + 4890: 01a79b13 slli s6,a5,0x1a + 4894: 01666b33 or s6,a2,s6 + 4898: 5652 lw a2,52(sp) + 489a: 01a69593 slli a1,a3,0x1a + 489e: 41688b33 sub s6,a7,s6 + 48a2: 40b605b3 sub a1,a2,a1 + 48a6: 00b63633 sltu a2,a2,a1 + 48aa: 40cb08b3 sub a7,s6,a2 + 48ae: 5672 lw a2,60(sp) + 48b0: 96b2 add a3,a3,a2 + 48b2: 00c6b3b3 sltu t2,a3,a2 + 48b6: 4636 lw a2,76(sp) + 48b8: 00f60b33 add s6,a2,a5 + 48bc: 00ec8633 add a2,s9,a4 + 48c0: 019637b3 sltu a5,a2,s9 + 48c4: 97f2 add a5,a5,t3 + 48c6: 00679e13 slli t3,a5,0x6 + 48ca: 8269 srli a2,a2,0x1a + 48cc: 00ce6633 or a2,t3,a2 + 48d0: 87e9 srai a5,a5,0x1a + 48d2: 00665e13 srli t3,a2,0x6 + 48d6: 93da add t2,t2,s6 + 48d8: 01a79b13 slli s6,a5,0x1a + 48dc: 016e6b33 or s6,t3,s6 + 48e0: 4e26 lw t3,72(sp) + 48e2: 01a61f13 slli t5,a2,0x1a + 48e6: 41ec8f33 sub t5,s9,t5 + 48ea: 416e0b33 sub s6,t3,s6 + 48ee: 4e66 lw t3,88(sp) + 48f0: 01ecbcb3 sltu s9,s9,t5 + 48f4: 419b0933 sub s2,s6,s9 + 48f8: 00fe0ab3 add s5,t3,a5 + 48fc: 010007b7 lui a5,0x1000 + 4900: 00f68e33 add t3,a3,a5 + 4904: 00de3b33 sltu s6,t3,a3 + 4908: 93da add t2,t2,s6 + 490a: 00739f93 slli t6,t2,0x7 + 490e: 019e5e13 srli t3,t3,0x19 + 4912: 01cfee33 or t3,t6,t3 + 4916: 019e1293 slli t0,t3,0x19 + 491a: 405682b3 sub t0,a3,t0 + 491e: 46c6 lw a3,80(sp) + 4920: 966a add a2,a2,s10 + 4922: 4193db13 srai s6,t2,0x19 + 4926: 01a63d33 sltu s10,a2,s10 + 492a: 9b36 add s6,s6,a3 + 492c: 00f606b3 add a3,a2,a5 + 4930: 9aea add s5,s5,s10 + 4932: 00c6bd33 sltu s10,a3,a2 + 4936: 9aea add s5,s5,s10 + 4938: 007a9f93 slli t6,s5,0x7 + 493c: 82e5 srli a3,a3,0x19 + 493e: 00dfe6b3 or a3,t6,a3 + 4942: 9e6e add t3,t3,s11 + 4944: 01969f93 slli t6,a3,0x19 + 4948: 01be3cb3 sltu s9,t3,s11 + 494c: 96a6 add a3,a3,s1 + 494e: 41f60633 sub a2,a2,t6 + 4952: 419ada93 srai s5,s5,0x19 + 4956: 00ee0fb3 add t6,t3,a4 + 495a: 9b66 add s6,s6,s9 + 495c: 0096b4b3 sltu s1,a3,s1 + 4960: 01cfbcb3 sltu s9,t6,t3 + 4964: 9ae2 add s5,s5,s8 + 4966: 9cda add s9,s9,s6 + 4968: 9aa6 add s5,s5,s1 + 496a: 4486 lw s1,64(sp) + 496c: 006c9393 slli t2,s9,0x6 + 4970: 01afdf93 srli t6,t6,0x1a + 4974: 01f3efb3 or t6,t2,t6 + 4978: 01f48c33 add s8,s1,t6 + 497c: 009c3d33 sltu s10,s8,s1 + 4980: 44d6 lw s1,84(sp) + 4982: 41acdc93 srai s9,s9,0x1a + 4986: 0fea slli t6,t6,0x1a + 4988: 9ca6 add s9,s9,s1 + 498a: 00e684b3 add s1,a3,a4 + 498e: 00d4b3b3 sltu t2,s1,a3 + 4992: 9a9e add s5,s5,t2 + 4994: 006a9393 slli t2,s5,0x6 + 4998: 80e9 srli s1,s1,0x1a + 499a: 0093e4b3 or s1,t2,s1 + 499e: 43f6 lw t2,92(sp) + 49a0: 41aada93 srai s5,s5,0x1a + 49a4: 9cea add s9,s9,s10 + 49a6: 9a9e add s5,s5,t2 + 49a8: 00fc03b3 add t2,s8,a5 + 49ac: 0183bd33 sltu s10,t2,s8 + 49b0: 9cea add s9,s9,s10 + 49b2: 007c9a13 slli s4,s9,0x7 + 49b6: 0193d393 srli t2,t2,0x19 + 49ba: 007a63b3 or t2,s4,t2 + 49be: 007f0d33 add s10,t5,t2 + 49c2: 419cdc93 srai s9,s9,0x19 + 49c6: 009b8b33 add s6,s7,s1 + 49ca: 9cca add s9,s9,s2 + 49cc: 01ed3f33 sltu t5,s10,t5 + 49d0: 017b3bb3 sltu s7,s6,s7 + 49d4: 9f66 add t5,t5,s9 + 49d6: 00fb0cb3 add s9,s6,a5 + 49da: 016cbdb3 sltu s11,s9,s6 + 49de: 9bd6 add s7,s7,s5 + 49e0: 9bee add s7,s7,s11 + 49e2: 00ed0a33 add s4,s10,a4 + 49e6: 007b9913 slli s2,s7,0x7 + 49ea: 019cdc93 srli s9,s9,0x19 + 49ee: 01996cb3 or s9,s2,s9 + 49f2: 01aa3933 sltu s2,s4,s10 + 49f6: 9f4a add t5,t5,s2 + 49f8: 419bdd93 srai s11,s7,0x19 + 49fc: 0f1a slli t5,t5,0x6 + 49fe: 019e8bb3 add s7,t4,s9 + 4a02: 01aa5a13 srli s4,s4,0x1a + 4a06: 01dbbab3 sltu s5,s7,t4 + 4a0a: 014f6a33 or s4,t5,s4 + 4a0e: 99ee add s3,s3,s11 + 4a10: 00eb8f33 add t5,s7,a4 + 4a14: 99d6 add s3,s3,s5 + 4a16: 017f3ab3 sltu s5,t5,s7 + 4a1a: 9ace add s5,s5,s3 + 4a1c: 006a9e93 slli t4,s5,0x6 + 4a20: 01af5f13 srli t5,t5,0x1a + 4a24: 01eeef33 or t5,t4,t5 + 4a28: 01e30933 add s2,t1,t5 + 4a2c: 41aada93 srai s5,s5,0x1a + 4a30: 9856 add a6,a6,s5 + 4a32: 97ca add a5,a5,s2 + 4a34: 00693333 sltu t1,s2,t1 + 4a38: 9342 add t1,t1,a6 + 4a3a: 0127b833 sltu a6,a5,s2 + 4a3e: 981a add a6,a6,t1 + 4a40: 00781313 slli t1,a6,0x7 + 4a44: 83e5 srli a5,a5,0x19 + 4a46: 00f367b3 or a5,t1,a5 + 4a4a: 41985813 srai a6,a6,0x19 + 4a4e: 02f40333 mul t1,s0,a5 + 4a52: 04ea slli s1,s1,0x1a + 4a54: 0ce6 slli s9,s9,0x19 + 4a56: 03e6 slli t2,t2,0x19 + 4a58: 0f6a slli t5,t5,0x1a + 4a5a: 419b0b33 sub s6,s6,s9 + 4a5e: 407c0c33 sub s8,s8,t2 + 4a62: 9652 add a2,a2,s4 + 4a64: 8e85 sub a3,a3,s1 + 4a66: 41eb8bb3 sub s7,s7,t5 + 4a6a: 03040833 mul a6,s0,a6 + 4a6e: 959a add a1,a1,t1 + 4a70: 0065b333 sltu t1,a1,t1 + 4a74: 972e add a4,a4,a1 + 4a76: 41fe0e33 sub t3,t3,t6 + 4a7a: 01852623 sw s8,12(a0) + 4a7e: 01652e23 sw s6,28(a0) + 4a82: 03752023 sw s7,32(a0) + 4a86: 44aa lw s1,136(sp) + 4a88: 01c52423 sw t3,8(a0) + 4a8c: 02f43433 mulhu s0,s0,a5 + 4a90: 07e6 slli a5,a5,0x19 + 4a92: 40f907b3 sub a5,s2,a5 + 4a96: c950 sw a2,20(a0) + 4a98: 491a lw s2,132(sp) + 4a9a: cd14 sw a3,24(a0) + 4a9c: d15c sw a5,36(a0) + 4a9e: 9442 add s0,s0,a6 + 4aa0: 98a2 add a7,a7,s0 + 4aa2: 989a add a7,a7,t1 + 4aa4: 00b73333 sltu t1,a4,a1 + 4aa8: 989a add a7,a7,t1 + 4aaa: 089a slli a7,a7,0x6 + 4aac: 8369 srli a4,a4,0x1a + 4aae: 00e8e733 or a4,a7,a4 + 4ab2: 443a lw s0,140(sp) + 4ab4: 01a71813 slli a6,a4,0x1a + 4ab8: 9716 add a4,a4,t0 + 4aba: c158 sw a4,4(a0) + 4abc: 01aa1713 slli a4,s4,0x1a + 4ac0: 40ed0d33 sub s10,s10,a4 + 4ac4: 410585b3 sub a1,a1,a6 + 4ac8: 01a52823 sw s10,16(a0) + 4acc: c10c sw a1,0(a0) + 4ace: 498a lw s3,128(sp) + 4ad0: 5a76 lw s4,124(sp) + 4ad2: 5ae6 lw s5,120(sp) + 4ad4: 5b56 lw s6,116(sp) + 4ad6: 5bc6 lw s7,112(sp) + 4ad8: 5c36 lw s8,108(sp) + 4ada: 5ca6 lw s9,104(sp) + 4adc: 5d16 lw s10,100(sp) + 4ade: 5d86 lw s11,96(sp) + 4ae0: 6149 addi sp,sp,144 + 4ae2: 8082 ret + +00004ae4 : + 4ae4: 715d addi sp,sp,-80 + 4ae6: d466 sw s9,40(sp) + 4ae8: 0245ac83 lw s9,36(a1) + 4aec: dc56 sw s5,56(sp) + 4aee: 02600a93 li s5,38 + 4af2: 035c8633 mul a2,s9,s5 + 4af6: c6a2 sw s0,76(sp) + 4af8: 41c0 lw s0,4(a1) + 4afa: 0005a883 lw a7,0(a1) + 4afe: da5a sw s6,52(sp) + 4b00: 00141693 slli a3,s0,0x1 + 4b04: 0205ab03 lw s6,32(a1) + 4b08: c2ca sw s2,68(sp) + 4b0a: de52 sw s4,60(sp) + 4b0c: 00189793 slli a5,a7,0x1 + 4b10: 03188933 mul s2,a7,a7 + 4b14: d662 sw s8,44(sp) + 4b16: d06e sw s11,32(sp) + 4b18: 4c4d li s8,19 + 4b1a: 4998 lw a4,16(a1) + 4b1c: 0185a303 lw t1,24(a1) + 4b20: d85e sw s7,48(sp) + 4b22: 0085af03 lw t5,8(a1) + 4b26: 01c5ab83 lw s7,28(a1) + 4b2a: 0145a383 lw t2,20(a1) + 4b2e: 02c68a33 mul s4,a3,a2 + 4b32: 00c5af83 lw t6,12(a1) + 4b36: 001f1e93 slli t4,t5,0x1 + 4b3a: c4a6 sw s1,72(sp) + 4b3c: 001f9813 slli a6,t6,0x1 + 4b40: c0ce sw s3,64(sp) + 4b42: 00171993 slli s3,a4,0x1 + 4b46: 00139e13 slli t3,t2,0x1 + 4b4a: d26a sw s10,36(sp) + 4b4c: 001b9d13 slli s10,s7,0x1 + 4b50: 02c69db3 mulh s11,a3,a2 + 4b54: 9a4a add s4,s4,s2 + 4b56: 012a3933 sltu s2,s4,s2 + 4b5a: 031898b3 mulh a7,a7,a7 + 4b5e: 038b05b3 mul a1,s6,s8 + 4b62: 98ee add a7,a7,s11 + 4b64: 98ca add a7,a7,s2 + 4b66: 02be8933 mul s2,t4,a1 + 4b6a: 035b82b3 mul t0,s7,s5 + 4b6e: 9952 add s2,s2,s4 + 4b70: 01493a33 sltu s4,s2,s4 + 4b74: 02be9db3 mulh s11,t4,a1 + 4b78: 98ee add a7,a7,s11 + 4b7a: 02580db3 mul s11,a6,t0 + 4b7e: 9a46 add s4,s4,a7 + 4b80: 025818b3 mulh a7,a6,t0 + 4b84: 9dca add s11,s11,s2 + 4b86: 012db933 sltu s2,s11,s2 + 4b8a: 038304b3 mul s1,t1,s8 + 4b8e: 98d2 add a7,a7,s4 + 4b90: 9946 add s2,s2,a7 + 4b92: 029998b3 mulh a7,s3,s1 + 4b96: 98ca add a7,a7,s2 + 4b98: 03538933 mul s2,t2,s5 + 4b9c: 02998a33 mul s4,s3,s1 + 4ba0: 02790ab3 mul s5,s2,t2 + 4ba4: 9a6e add s4,s4,s11 + 4ba6: 01ba3db3 sltu s11,s4,s11 + 4baa: 98ee add a7,a7,s11 + 4bac: 02791933 mulh s2,s2,t2 + 4bb0: 9ad2 add s5,s5,s4 + 4bb2: 014aba33 sltu s4,s5,s4 + 4bb6: 9946 add s2,s2,a7 + 4bb8: 012a08b3 add a7,s4,s2 + 4bbc: 02878a33 mul s4,a5,s0 + 4bc0: c646 sw a7,12(sp) + 4bc2: 03e60933 mul s2,a2,t5 + 4bc6: 02879db3 mulh s11,a5,s0 + 4bca: 9952 add s2,s2,s4 + 4bcc: 01493a33 sltu s4,s2,s4 + 4bd0: 03e618b3 mulh a7,a2,t5 + 4bd4: 98ee add a7,a7,s11 + 4bd6: 98d2 add a7,a7,s4 + 4bd8: 03058a33 mul s4,a1,a6 + 4bdc: 03059db3 mulh s11,a1,a6 + 4be0: 9a4a add s4,s4,s2 + 4be2: 012a3933 sltu s2,s4,s2 + 4be6: 98ee add a7,a7,s11 + 4be8: 02e28db3 mul s11,t0,a4 + 4bec: 98ca add a7,a7,s2 + 4bee: 02e29933 mulh s2,t0,a4 + 4bf2: 9dd2 add s11,s11,s4 + 4bf4: 014dba33 sltu s4,s11,s4 + 4bf8: 98ca add a7,a7,s2 + 4bfa: 03c48933 mul s2,s1,t3 + 4bfe: 98d2 add a7,a7,s4 + 4c00: 03c49a33 mulh s4,s1,t3 + 4c04: 996e add s2,s2,s11 + 4c06: 01b93db3 sltu s11,s2,s11 + 4c0a: c44a sw s2,8(sp) + 4c0c: 98d2 add a7,a7,s4 + 4c0e: 98ee add a7,a7,s11 + 4c10: c846 sw a7,16(sp) + 4c12: 02868933 mul s2,a3,s0 + 4c16: 03e788b3 mul a7,a5,t5 + 4c1a: 03e79a33 mulh s4,a5,t5 + 4c1e: 9946 add s2,s2,a7 + 4c20: 011938b3 sltu a7,s2,a7 + 4c24: 02869433 mulh s0,a3,s0 + 4c28: 9452 add s0,s0,s4 + 4c2a: 98a2 add a7,a7,s0 + 4c2c: 03060433 mul s0,a2,a6 + 4c30: 03061a33 mulh s4,a2,a6 + 4c34: 944a add s0,s0,s2 + 4c36: 01243933 sltu s2,s0,s2 + 4c3a: 03358db3 mul s11,a1,s3 + 4c3e: 98d2 add a7,a7,s4 + 4c40: 9946 add s2,s2,a7 + 4c42: 033599b3 mulh s3,a1,s3 + 4c46: 9da2 add s11,s11,s0 + 4c48: 008db433 sltu s0,s11,s0 + 4c4c: 03c288b3 mul a7,t0,t3 + 4c50: 994e add s2,s2,s3 + 4c52: 9922 add s2,s2,s0 + 4c54: 03c29433 mulh s0,t0,t3 + 4c58: 98ee add a7,a7,s11 + 4c5a: 01b8bdb3 sltu s11,a7,s11 + 4c5e: 9922 add s2,s2,s0 + 4c60: 9dca add s11,s11,s2 + 4c62: 02648933 mul s2,s1,t1 + 4c66: 026494b3 mulh s1,s1,t1 + 4c6a: 9946 add s2,s2,a7 + 4c6c: 011938b3 sltu a7,s2,a7 + 4c70: 94ee add s1,s1,s11 + 4c72: 00988433 add s0,a7,s1 + 4c76: 03f788b3 mul a7,a5,t6 + 4c7a: ca22 sw s0,20(sp) + 4c7c: 03e684b3 mul s1,a3,t5 + 4c80: 03f799b3 mulh s3,a5,t6 + 4c84: 94c6 add s1,s1,a7 + 4c86: 0114b8b3 sltu a7,s1,a7 + 4c8a: 03e69a33 mulh s4,a3,t5 + 4c8e: 01498433 add s0,s3,s4 + 4c92: 9446 add s0,s0,a7 + 4c94: 02e608b3 mul a7,a2,a4 + 4c98: 02e619b3 mulh s3,a2,a4 + 4c9c: 98a6 add a7,a7,s1 + 4c9e: 0098b4b3 sltu s1,a7,s1 + 4ca2: 944e add s0,s0,s3 + 4ca4: 03c589b3 mul s3,a1,t3 + 4ca8: 9426 add s0,s0,s1 + 4caa: 03c594b3 mulh s1,a1,t3 + 4cae: 99c6 add s3,s3,a7 + 4cb0: 0119b8b3 sltu a7,s3,a7 + 4cb4: 9426 add s0,s0,s1 + 4cb6: 98a2 add a7,a7,s0 + 4cb8: 02628433 mul s0,t0,t1 + 4cbc: 026294b3 mulh s1,t0,t1 + 4cc0: 944e add s0,s0,s3 + 4cc2: 013439b3 sltu s3,s0,s3 + 4cc6: 98a6 add a7,a7,s1 + 4cc8: 011984b3 add s1,s3,a7 + 4ccc: 02e789b3 mul s3,a5,a4 + 4cd0: cc26 sw s1,24(sp) + 4cd2: 030688b3 mul a7,a3,a6 + 4cd6: 03069a33 mulh s4,a3,a6 + 4cda: 98ce add a7,a7,s3 + 4cdc: 0138b9b3 sltu s3,a7,s3 + 4ce0: 02e794b3 mulh s1,a5,a4 + 4ce4: 03ef0db3 mul s11,t5,t5 + 4ce8: 94d2 add s1,s1,s4 + 4cea: 99a6 add s3,s3,s1 + 4cec: 03ef1f33 mulh t5,t5,t5 + 4cf0: 9dc6 add s11,s11,a7 + 4cf2: 011db8b3 sltu a7,s11,a7 + 4cf6: 03c604b3 mul s1,a2,t3 + 4cfa: 99fa add s3,s3,t5 + 4cfc: 99c6 add s3,s3,a7 + 4cfe: 03c61f33 mulh t5,a2,t3 + 4d02: 94ee add s1,s1,s11 + 4d04: 01b4bdb3 sltu s11,s1,s11 + 4d08: 99fa add s3,s3,t5 + 4d0a: 9dce add s11,s11,s3 + 4d0c: 00131993 slli s3,t1,0x1 + 4d10: 02b98f33 mul t5,s3,a1 + 4d14: 02b999b3 mulh s3,s3,a1 + 4d18: 9f26 add t5,t5,s1 + 4d1a: 009f34b3 sltu s1,t5,s1 + 4d1e: 03728a33 mul s4,t0,s7 + 4d22: 9dce add s11,s11,s3 + 4d24: 94ee add s1,s1,s11 + 4d26: 037292b3 mulh t0,t0,s7 + 4d2a: 9a7a add s4,s4,t5 + 4d2c: 01ea3f33 sltu t5,s4,t5 + 4d30: 92a6 add t0,t0,s1 + 4d32: 005f08b3 add a7,t5,t0 + 4d36: 02f38f33 mul t5,t2,a5 + 4d3a: 02e682b3 mul t0,a3,a4 + 4d3e: 02f399b3 mulh s3,t2,a5 + 4d42: 92fa add t0,t0,t5 + 4d44: 01e2bf33 sltu t5,t0,t5 + 4d48: 02e69db3 mulh s11,a3,a4 + 4d4c: 01b984b3 add s1,s3,s11 + 4d50: 94fa add s1,s1,t5 + 4d52: 03fe8f33 mul t5,t4,t6 + 4d56: 03fe99b3 mulh s3,t4,t6 + 4d5a: 9f16 add t5,t5,t0 + 4d5c: 005f32b3 sltu t0,t5,t0 + 4d60: 94ce add s1,s1,s3 + 4d62: 92a6 add t0,t0,s1 + 4d64: 026604b3 mul s1,a2,t1 + 4d68: 026619b3 mulh s3,a2,t1 + 4d6c: 94fa add s1,s1,t5 + 4d6e: 01e4bf33 sltu t5,s1,t5 + 4d72: 92ce add t0,t0,s3 + 4d74: 92fa add t0,t0,t5 + 4d76: 03a59f33 mulh t5,a1,s10 + 4d7a: 03a589b3 mul s3,a1,s10 + 4d7e: 92fa add t0,t0,t5 + 4d80: 02679db3 mulh s11,a5,t1 + 4d84: 99a6 add s3,s3,s1 + 4d86: 0099b4b3 sltu s1,s3,s1 + 4d8a: 9496 add s1,s1,t0 + 4d8c: ce26 sw s1,28(sp) + 4d8e: 03c69f33 mulh t5,a3,t3 + 4d92: 026782b3 mul t0,a5,t1 + 4d96: 9f6e add t5,t5,s11 + 4d98: 03c684b3 mul s1,a3,t3 + 4d9c: 02ee9db3 mulh s11,t4,a4 + 4da0: 9496 add s1,s1,t0 + 4da2: 0054b2b3 sltu t0,s1,t0 + 4da6: 9f16 add t5,t5,t0 + 4da8: 02ee82b3 mul t0,t4,a4 + 4dac: 9f6e add t5,t5,s11 + 4dae: 03f80db3 mul s11,a6,t6 + 4db2: 92a6 add t0,t0,s1 + 4db4: 0092b4b3 sltu s1,t0,s1 + 4db8: 94fa add s1,s1,t5 + 4dba: 03f81fb3 mulh t6,a6,t6 + 4dbe: 9d96 add s11,s11,t0 + 4dc0: 005db2b3 sltu t0,s11,t0 + 4dc4: 03a60f33 mul t5,a2,s10 + 4dc8: 94fe add s1,s1,t6 + 4dca: 9496 add s1,s1,t0 + 4dcc: 03a612b3 mulh t0,a2,s10 + 4dd0: 9f6e add t5,t5,s11 + 4dd2: 01bf3db3 sltu s11,t5,s11 + 4dd6: 9496 add s1,s1,t0 + 4dd8: 9da6 add s11,s11,s1 + 4dda: 036584b3 mul s1,a1,s6 + 4dde: 036595b3 mulh a1,a1,s6 + 4de2: 94fa add s1,s1,t5 + 4de4: 01e4bf33 sltu t5,s1,t5 + 4de8: 95ee add a1,a1,s11 + 4dea: 00bf0fb3 add t6,t5,a1 + 4dee: 02669db3 mulh s11,a3,t1 + 4df2: 03779f33 mulh t5,a5,s7 + 4df6: 037782b3 mul t0,a5,s7 + 4dfa: 9f6e add t5,t5,s11 + 4dfc: 026685b3 mul a1,a3,t1 + 4e00: 027e8db3 mul s11,t4,t2 + 4e04: 9596 add a1,a1,t0 + 4e06: 0055b2b3 sltu t0,a1,t0 + 4e0a: 92fa add t0,t0,t5 + 4e0c: 027e93b3 mulh t2,t4,t2 + 4e10: 9dae add s11,s11,a1 + 4e12: 00bdb5b3 sltu a1,s11,a1 + 4e16: 929e add t0,t0,t2 + 4e18: 92ae add t0,t0,a1 + 4e1a: 02e815b3 mulh a1,a6,a4 + 4e1e: 02e80f33 mul t5,a6,a4 + 4e22: 92ae add t0,t0,a1 + 4e24: 036603b3 mul t2,a2,s6 + 4e28: 9f6e add t5,t5,s11 + 4e2a: 01bf3db3 sltu s11,t5,s11 + 4e2e: 9d96 add s11,s11,t0 + 4e30: 036615b3 mulh a1,a2,s6 + 4e34: 93fa add t2,t2,t5 + 4e36: 01e3bf33 sltu t5,t2,t5 + 4e3a: 9dae add s11,s11,a1 + 4e3c: 03a682b3 mul t0,a3,s10 + 4e40: 9f6e add t5,t5,s11 + 4e42: 036785b3 mul a1,a5,s6 + 4e46: 03679db3 mulh s11,a5,s6 + 4e4a: 92ae add t0,t0,a1 + 4e4c: 00b2b5b3 sltu a1,t0,a1 + 4e50: 03a69d33 mulh s10,a3,s10 + 4e54: 9d6e add s10,s10,s11 + 4e56: 9d2e add s10,s10,a1 + 4e58: 026e85b3 mul a1,t4,t1 + 4e5c: 026e9db3 mulh s11,t4,t1 + 4e60: 9596 add a1,a1,t0 + 4e62: 0055b2b3 sltu t0,a1,t0 + 4e66: 9d6e add s10,s10,s11 + 4e68: 92ea add t0,t0,s10 + 4e6a: 03c80d33 mul s10,a6,t3 + 4e6e: 03c81db3 mulh s11,a6,t3 + 4e72: 9d2e add s10,s10,a1 + 4e74: 00bd35b3 sltu a1,s10,a1 + 4e78: 92ee add t0,t0,s11 + 4e7a: 9596 add a1,a1,t0 + 4e7c: 02e702b3 mul t0,a4,a4 + 4e80: 02e71db3 mulh s11,a4,a4 + 4e84: 92ea add t0,t0,s10 + 4e86: 01a2bd33 sltu s10,t0,s10 + 4e8a: 95ee add a1,a1,s11 + 4e8c: 9d2e add s10,s10,a1 + 4e8e: 039605b3 mul a1,a2,s9 + 4e92: 03961633 mulh a2,a2,s9 + 4e96: 9596 add a1,a1,t0 + 4e98: 0055b2b3 sltu t0,a1,t0 + 4e9c: 9d32 add s10,s10,a2 + 4e9e: 92ea add t0,t0,s10 + 4ea0: 03978633 mul a2,a5,s9 + 4ea4: 03668d33 mul s10,a3,s6 + 4ea8: 039797b3 mulh a5,a5,s9 + 4eac: 9d32 add s10,s10,a2 + 4eae: 00cd3633 sltu a2,s10,a2 + 4eb2: 036696b3 mulh a3,a3,s6 + 4eb6: 037e8db3 mul s11,t4,s7 + 4eba: 97b6 add a5,a5,a3 + 4ebc: 963e add a2,a2,a5 + 4ebe: 037e9eb3 mulh t4,t4,s7 + 4ec2: 9dea add s11,s11,s10 + 4ec4: 01adbd33 sltu s10,s11,s10 + 4ec8: 02680b33 mul s6,a6,t1 + 4ecc: 9676 add a2,a2,t4 + 4ece: 9d32 add s10,s10,a2 + 4ed0: 4632 lw a2,12(sp) + 4ed2: 02681833 mulh a6,a6,t1 + 4ed6: 9b6e add s6,s6,s11 + 4ed8: 01bb3db3 sltu s11,s6,s11 + 4edc: 4332 lw t1,12(sp) + 4ede: 03c70eb3 mul t4,a4,t3 + 4ee2: 9d42 add s10,s10,a6 + 4ee4: 9dea add s11,s11,s10 + 4ee6: 03c71733 mulh a4,a4,t3 + 4eea: 9eda add t4,t4,s6 + 4eec: 016ebb33 sltu s6,t4,s6 + 4ef0: 976e add a4,a4,s11 + 4ef2: 00eb0e33 add t3,s6,a4 + 4ef6: 02000737 lui a4,0x2000 + 4efa: 00ea86b3 add a3,s5,a4 + 4efe: 0156b7b3 sltu a5,a3,s5 + 4f02: 97b2 add a5,a5,a2 + 4f04: 00679613 slli a2,a5,0x6 + 4f08: 82e9 srli a3,a3,0x1a + 4f0a: 8ed1 or a3,a3,a2 + 4f0c: 87e9 srai a5,a5,0x1a + 4f0e: 0066d813 srli a6,a3,0x6 + 4f12: 01a79613 slli a2,a5,0x1a + 4f16: 00c86633 or a2,a6,a2 + 4f1a: 01a69813 slli a6,a3,0x1a + 4f1e: 410a8833 sub a6,s5,a6 + 4f22: 40c30633 sub a2,t1,a2 + 4f26: 010abab3 sltu s5,s5,a6 + 4f2a: 41560ab3 sub s5,a2,s5 + 4f2e: 4622 lw a2,8(sp) + 4f30: 4342 lw t1,16(sp) + 4f32: 96b2 add a3,a3,a2 + 4f34: 00c6b633 sltu a2,a3,a2 + 4f38: 00f30db3 add s11,t1,a5 + 4f3c: 9db2 add s11,s11,a2 + 4f3e: 00ea0633 add a2,s4,a4 + 4f42: 014637b3 sltu a5,a2,s4 + 4f46: 97c6 add a5,a5,a7 + 4f48: 00679313 slli t1,a5,0x6 + 4f4c: 8269 srli a2,a2,0x1a + 4f4e: 00c36633 or a2,t1,a2 + 4f52: 87e9 srai a5,a5,0x1a + 4f54: 00665b13 srli s6,a2,0x6 + 4f58: 01a79313 slli t1,a5,0x1a + 4f5c: 006b6333 or t1,s6,t1 + 4f60: 406888b3 sub a7,a7,t1 + 4f64: 4372 lw t1,28(sp) + 4f66: 01a61b13 slli s6,a2,0x1a + 4f6a: 964e add a2,a2,s3 + 4f6c: 979a add a5,a5,t1 + 4f6e: 013639b3 sltu s3,a2,s3 + 4f72: 416a0b33 sub s6,s4,s6 + 4f76: 99be add s3,s3,a5 + 4f78: 010007b7 lui a5,0x1000 + 4f7c: 00f68333 add t1,a3,a5 + 4f80: 016a3a33 sltu s4,s4,s6 + 4f84: 414888b3 sub a7,a7,s4 + 4f88: 00d33a33 sltu s4,t1,a3 + 4f8c: 9dd2 add s11,s11,s4 + 4f8e: 007d9a13 slli s4,s11,0x7 + 4f92: 01935313 srli t1,t1,0x19 + 4f96: 006a6333 or t1,s4,t1 + 4f9a: 01931b93 slli s7,t1,0x19 + 4f9e: 41768bb3 sub s7,a3,s7 + 4fa2: 46d2 lw a3,20(sp) + 4fa4: 934a add t1,t1,s2 + 4fa6: 419ddd93 srai s11,s11,0x19 + 4faa: 01233933 sltu s2,t1,s2 + 4fae: 01b68a33 add s4,a3,s11 + 4fb2: 00f606b3 add a3,a2,a5 + 4fb6: 9a4a add s4,s4,s2 + 4fb8: 00c6b933 sltu s2,a3,a2 + 4fbc: 99ca add s3,s3,s2 + 4fbe: 00799913 slli s2,s3,0x7 + 4fc2: 82e5 srli a3,a3,0x19 + 4fc4: 00d966b3 or a3,s2,a3 + 4fc8: 4199d993 srai s3,s3,0x19 + 4fcc: 01969913 slli s2,a3,0x19 + 4fd0: 9fce add t6,t6,s3 + 4fd2: 00e309b3 add s3,t1,a4 + 4fd6: 96a6 add a3,a3,s1 + 4fd8: 41260633 sub a2,a2,s2 + 4fdc: 0069b933 sltu s2,s3,t1 + 4fe0: 0096b4b3 sltu s1,a3,s1 + 4fe4: 9952 add s2,s2,s4 + 4fe6: 9fa6 add t6,t6,s1 + 4fe8: 01a9d993 srli s3,s3,0x1a + 4fec: 00691493 slli s1,s2,0x6 + 4ff0: 0134e9b3 or s3,s1,s3 + 4ff4: 44e2 lw s1,24(sp) + 4ff6: 01340cb3 add s9,s0,s3 + 4ffa: 41a95913 srai s2,s2,0x1a + 4ffe: 9926 add s2,s2,s1 + 5000: 008cb433 sltu s0,s9,s0 + 5004: 944a add s0,s0,s2 + 5006: 00e68933 add s2,a3,a4 + 500a: 00d934b3 sltu s1,s2,a3 + 500e: 9fa6 add t6,t6,s1 + 5010: 006f9493 slli s1,t6,0x6 + 5014: 01a95913 srli s2,s2,0x1a + 5018: 0124e933 or s2,s1,s2 + 501c: 41afd493 srai s1,t6,0x1a + 5020: 01238fb3 add t6,t2,s2 + 5024: 007fb3b3 sltu t2,t6,t2 + 5028: 9f26 add t5,t5,s1 + 502a: 00fc84b3 add s1,s9,a5 + 502e: 9f1e add t5,t5,t2 + 5030: 0194b3b3 sltu t2,s1,s9 + 5034: 941e add s0,s0,t2 + 5036: 41945a13 srai s4,s0,0x19 + 503a: 00741393 slli t2,s0,0x7 + 503e: 98d2 add a7,a7,s4 + 5040: 80e5 srli s1,s1,0x19 + 5042: 00ff8a33 add s4,t6,a5 + 5046: 0093e4b3 or s1,t2,s1 + 504a: 01fa33b3 sltu t2,s4,t6 + 504e: 9f1e add t5,t5,t2 + 5050: 007f1393 slli t2,t5,0x7 + 5054: 019a5a13 srli s4,s4,0x19 + 5058: 009b0433 add s0,s6,s1 + 505c: 0143ea33 or s4,t2,s4 + 5060: 419f5393 srai t2,t5,0x19 + 5064: 01643b33 sltu s6,s0,s6 + 5068: 929e add t0,t0,t2 + 506a: 00e403b3 add t2,s0,a4 + 506e: 98da add a7,a7,s6 + 5070: 0083bb33 sltu s6,t2,s0 + 5074: 98da add a7,a7,s6 + 5076: 01458f33 add t5,a1,s4 + 507a: 089a slli a7,a7,0x6 + 507c: 01a3d393 srli t2,t2,0x1a + 5080: 00bf35b3 sltu a1,t5,a1 + 5084: 0078e3b3 or t2,a7,t2 + 5088: 00ef08b3 add a7,t5,a4 + 508c: 92ae add t0,t0,a1 + 508e: 01e8b5b3 sltu a1,a7,t5 + 5092: 9596 add a1,a1,t0 + 5094: 00659293 slli t0,a1,0x6 + 5098: 01a8d893 srli a7,a7,0x1a + 509c: 0112e8b3 or a7,t0,a7 + 50a0: 011e8b33 add s6,t4,a7 + 50a4: 85e9 srai a1,a1,0x1a + 50a6: 9e2e add t3,t3,a1 + 50a8: 97da add a5,a5,s6 + 50aa: 01db3eb3 sltu t4,s6,t4 + 50ae: 9ef2 add t4,t4,t3 + 50b0: 0167be33 sltu t3,a5,s6 + 50b4: 9e76 add t3,t3,t4 + 50b6: 007e1593 slli a1,t3,0x7 + 50ba: 83e5 srli a5,a5,0x19 + 50bc: 8fcd or a5,a5,a1 + 50be: 419e5e13 srai t3,t3,0x19 + 50c2: 02fc05b3 mul a1,s8,a5 + 50c6: 09ea slli s3,s3,0x1a + 50c8: 04e6 slli s1,s1,0x19 + 50ca: 096a slli s2,s2,0x1a + 50cc: 0a66 slli s4,s4,0x19 + 50ce: 08ea slli a7,a7,0x1a + 50d0: 409c8cb3 sub s9,s9,s1 + 50d4: 41330333 sub t1,t1,s3 + 50d8: 412686b3 sub a3,a3,s2 + 50dc: 414f8fb3 sub t6,t6,s4 + 50e0: 03cc0e33 mul t3,s8,t3 + 50e4: 982e add a6,a6,a1 + 50e6: 00b835b3 sltu a1,a6,a1 + 50ea: 9742 add a4,a4,a6 + 50ec: 961e add a2,a2,t2 + 50ee: 411f0f33 sub t5,t5,a7 + 50f2: 01952623 sw s9,12(a0) + 50f6: 00652423 sw t1,8(a0) + 50fa: c950 sw a2,20(a0) + 50fc: cd14 sw a3,24(a0) + 50fe: 02fc3c33 mulhu s8,s8,a5 + 5102: 07e6 slli a5,a5,0x19 + 5104: 40fb07b3 sub a5,s6,a5 + 5108: 01f52e23 sw t6,28(a0) + 510c: 03e52023 sw t5,32(a0) + 5110: d15c sw a5,36(a0) + 5112: 44a6 lw s1,72(sp) + 5114: 4916 lw s2,68(sp) + 5116: 4986 lw s3,64(sp) + 5118: 5a72 lw s4,60(sp) + 511a: 9c72 add s8,s8,t3 + 511c: 9ae2 add s5,s5,s8 + 511e: 9aae add s5,s5,a1 + 5120: 010735b3 sltu a1,a4,a6 + 5124: 9aae add s5,s5,a1 + 5126: 0a9a slli s5,s5,0x6 + 5128: 8369 srli a4,a4,0x1a + 512a: 00eae733 or a4,s5,a4 + 512e: 01a71593 slli a1,a4,0x1a + 5132: 975e add a4,a4,s7 + 5134: c158 sw a4,4(a0) + 5136: 01a39713 slli a4,t2,0x1a + 513a: 8c19 sub s0,s0,a4 + 513c: c900 sw s0,16(a0) + 513e: 4436 lw s0,76(sp) + 5140: 40b80833 sub a6,a6,a1 + 5144: 01052023 sw a6,0(a0) + 5148: 5ae2 lw s5,56(sp) + 514a: 5b52 lw s6,52(sp) + 514c: 5bc2 lw s7,48(sp) + 514e: 5c32 lw s8,44(sp) + 5150: 5ca2 lw s9,40(sp) + 5152: 5d12 lw s10,36(sp) + 5154: 5d82 lw s11,32(sp) + 5156: 6161 addi sp,sp,80 + 5158: 8082 ret + +0000515a : + 515a: 0005cb63 bltz a1,5170 + 515e: 4035d793 srai a5,a1,0x3 + 5162: 953e add a0,a0,a5 + 5164: 2108 lbu a0,0(a0) + 5166: 899d andi a1,a1,7 + 5168: 40b55533 sra a0,a0,a1 + 516c: 8905 andi a0,a0,1 + 516e: 8082 ret + 5170: 4501 li a0,0 + 5172: 8082 ret + +00005174 : + 5174: 02058e13 addi t3,a1,32 + 5178: 02060e93 addi t4,a2,32 + 517c: 88b2 mv a7,a2 + 517e: 882a mv a6,a0 + 5180: 4701 li a4,0 + 5182: 419c lw a5,0(a1) + 5184: 0008a303 lw t1,0(a7) + 5188: 0891 addi a7,a7,4 + 518a: 0811 addi a6,a6,4 + 518c: 026786b3 mul a3,a5,t1 + 5190: 0267b333 mulhu t1,a5,t1 + 5194: ffc82783 lw a5,-4(a6) + 5198: 97b6 add a5,a5,a3 + 519a: 973e add a4,a4,a5 + 519c: 00d7b6b3 sltu a3,a5,a3 + 51a0: fee82e23 sw a4,-4(a6) + 51a4: 00f737b3 sltu a5,a4,a5 + 51a8: 969a add a3,a3,t1 + 51aa: 00d78733 add a4,a5,a3 + 51ae: fd1e9ae3 bne t4,a7,5182 + 51b2: d118 sw a4,32(a0) + 51b4: 0591 addi a1,a1,4 + 51b6: 0511 addi a0,a0,4 + 51b8: fcbe12e3 bne t3,a1,517c + 51bc: 8082 ret + +000051be : + 51be: 65b1 lui a1,0xc + 51c0: 4681 li a3,0 + 51c2: 4785 li a5,1 + 51c4: 71058593 addi a1,a1,1808 # c710 + 51c8: 02000813 li a6,32 + 51cc: 00d58733 add a4,a1,a3 + 51d0: 00d50633 add a2,a0,a3 + 51d4: 4318 lw a4,0(a4) + 51d6: 4210 lw a2,0(a2) + 51d8: 0691 addi a3,a3,4 + 51da: fff74713 not a4,a4 + 51de: 963a add a2,a2,a4 + 51e0: 97b2 add a5,a5,a2 + 51e2: 00e63733 sltu a4,a2,a4 + 51e6: 00c7b7b3 sltu a5,a5,a2 + 51ea: 97ba add a5,a5,a4 + 51ec: ff0690e3 bne a3,a6,51cc + 51f0: 853e mv a0,a5 + 51f2: 8082 ret + +000051f4 : + 51f4: ffdfa2ef jal t0,1f0 <__riscv_save_0> + 51f8: 1141 addi sp,sp,-16 + 51fa: 842a mv s0,a0 + 51fc: 852e mv a0,a1 + 51fe: c62e sw a1,12(sp) + 5200: fbfff0ef jal ra,51be + 5204: 45b2 lw a1,12(sp) + 5206: 6631 lui a2,0xc + 5208: 41f55813 srai a6,a0,0x1f + 520c: 40a00333 neg t1,a0 + 5210: 4681 li a3,0 + 5212: 71060613 addi a2,a2,1808 # c710 + 5216: 02000893 li a7,32 + 521a: 00d607b3 add a5,a2,a3 + 521e: 439c lw a5,0(a5) + 5220: 00d58733 add a4,a1,a3 + 5224: 4318 lw a4,0(a4) + 5226: fff7c793 not a5,a5 + 522a: 0067f7b3 and a5,a5,t1 + 522e: 973e add a4,a4,a5 + 5230: 00f737b3 sltu a5,a4,a5 + 5234: 953a add a0,a0,a4 + 5236: 97c2 add a5,a5,a6 + 5238: 00d40833 add a6,s0,a3 + 523c: 00a82023 sw a0,0(a6) + 5240: 00e53733 sltu a4,a0,a4 + 5244: 0691 addi a3,a3,4 + 5246: 00f70533 add a0,a4,a5 + 524a: 4801 li a6,0 + 524c: fd1697e3 bne a3,a7,521a + 5250: 0141 addi sp,sp,16 + 5252: fc3fa06f j 214 <__riscv_restore_0> + +00005256 : + 5256: f9bfa2ef jal t0,1f0 <__riscv_save_0> + 525a: 842a mv s0,a0 + 525c: e88fe0ef jal ra,38e4 + 5260: 02840513 addi a0,s0,40 + 5264: e90fe0ef jal ra,38f4 + 5268: 05040513 addi a0,s0,80 + 526c: e88fe0ef jal ra,38f4 + 5270: 07840513 addi a0,s0,120 + 5274: e70fe0ef jal ra,38e4 + 5278: f9dfa06f j 214 <__riscv_restore_0> + +0000527c : + 527c: f75fa2ef jal t0,1f0 <__riscv_save_0> + 5280: 02858913 addi s2,a1,40 + 5284: 842e mv s0,a1 + 5286: 862e mv a2,a1 + 5288: 85ca mv a1,s2 + 528a: 84aa mv s1,a0 + 528c: eb8fe0ef jal ra,3944 + 5290: 8622 mv a2,s0 + 5292: 85ca mv a1,s2 + 5294: 02848513 addi a0,s1,40 + 5298: ed2fe0ef jal ra,396a + 529c: 05040593 addi a1,s0,80 + 52a0: 05048513 addi a0,s1,80 + 52a4: e68fe0ef jal ra,390c + 52a8: 6631 lui a2,0xc + 52aa: 6e860613 addi a2,a2,1768 # c6e8 + 52ae: 07840593 addi a1,s0,120 + 52b2: 07848513 addi a0,s1,120 + 52b6: d93fe0ef jal ra,4048 + 52ba: f5bfa06f j 214 <__riscv_restore_0> + +000052be : + 52be: f19fa2ef jal t0,1d6 <__riscv_save_4> + 52c2: 715d addi sp,sp,-80 + 52c4: 02858413 addi s0,a1,40 + 52c8: 84aa mv s1,a0 + 52ca: 8a32 mv s4,a2 + 52cc: 892e mv s2,a1 + 52ce: 862e mv a2,a1 + 52d0: 850a mv a0,sp + 52d2: 85a2 mv a1,s0 + 52d4: e70fe0ef jal ra,3944 + 52d8: 864a mv a2,s2 + 52da: 85a2 mv a1,s0 + 52dc: 1028 addi a0,sp,40 + 52de: e8cfe0ef jal ra,396a + 52e2: 8652 mv a2,s4 + 52e4: 858a mv a1,sp + 52e6: 850a mv a0,sp + 52e8: d61fe0ef jal ra,4048 + 52ec: 102c addi a1,sp,40 + 52ee: 028a0613 addi a2,s4,40 + 52f2: 852e mv a0,a1 + 52f4: d55fe0ef jal ra,4048 + 52f8: 02848a93 addi s5,s1,40 + 52fc: 1030 addi a2,sp,40 + 52fe: 858a mv a1,sp + 5300: 8556 mv a0,s5 + 5302: e42fe0ef jal ra,3944 + 5306: 1030 addi a2,sp,40 + 5308: 858a mv a1,sp + 530a: 8526 mv a0,s1 + 530c: e5efe0ef jal ra,396a + 5310: 05048413 addi s0,s1,80 + 5314: 05090613 addi a2,s2,80 + 5318: 85b2 mv a1,a2 + 531a: 8522 mv a0,s0 + 531c: e28fe0ef jal ra,3944 + 5320: 050a0613 addi a2,s4,80 + 5324: 85a2 mv a1,s0 + 5326: 8522 mv a0,s0 + 5328: d21fe0ef jal ra,4048 + 532c: 07848993 addi s3,s1,120 + 5330: 078a0613 addi a2,s4,120 + 5334: 07890593 addi a1,s2,120 + 5338: 854e mv a0,s3 + 533a: d0ffe0ef jal ra,4048 + 533e: 864e mv a2,s3 + 5340: 85a2 mv a1,s0 + 5342: 850a mv a0,sp + 5344: e00fe0ef jal ra,3944 + 5348: 864e mv a2,s3 + 534a: 85a2 mv a1,s0 + 534c: 1028 addi a0,sp,40 + 534e: e1cfe0ef jal ra,396a + 5352: 8656 mv a2,s5 + 5354: 85a6 mv a1,s1 + 5356: 854e mv a0,s3 + 5358: cf1fe0ef jal ra,4048 + 535c: 1030 addi a2,sp,40 + 535e: 85a6 mv a1,s1 + 5360: 8526 mv a0,s1 + 5362: ce7fe0ef jal ra,4048 + 5366: 860a mv a2,sp + 5368: 85d6 mv a1,s5 + 536a: 8556 mv a0,s5 + 536c: cddfe0ef jal ra,4048 + 5370: 1030 addi a2,sp,40 + 5372: 858a mv a1,sp + 5374: 8522 mv a0,s0 + 5376: cd3fe0ef jal ra,4048 + 537a: 6161 addi sp,sp,80 + 537c: e8ffa06f j 20a <__riscv_restore_4> + +00005380 : + 5380: e49fa2ef jal t0,1c8 <__riscv_save_10> + 5384: 02858a13 addi s4,a1,40 + 5388: 892a mv s2,a0 + 538a: 89ae mv s3,a1 + 538c: 8536 mv a0,a3 + 538e: 8bb2 mv s7,a2 + 5390: 862e mv a2,a1 + 5392: 85d2 mv a1,s4 + 5394: 8436 mv s0,a3 + 5396: 84ba mv s1,a4 + 5398: dacfe0ef jal ra,3944 + 539c: 864e mv a2,s3 + 539e: 85d2 mv a1,s4 + 53a0: 8526 mv a0,s1 + 53a2: dc8fe0ef jal ra,396a + 53a6: 865e mv a2,s7 + 53a8: 85a2 mv a1,s0 + 53aa: 8522 mv a0,s0 + 53ac: c9dfe0ef jal ra,4048 + 53b0: 028b8613 addi a2,s7,40 + 53b4: 85a6 mv a1,s1 + 53b6: 8526 mv a0,s1 + 53b8: c91fe0ef jal ra,4048 + 53bc: 02890b13 addi s6,s2,40 + 53c0: 8626 mv a2,s1 + 53c2: 85a2 mv a1,s0 + 53c4: 855a mv a0,s6 + 53c6: d7efe0ef jal ra,3944 + 53ca: 8626 mv a2,s1 + 53cc: 85a2 mv a1,s0 + 53ce: 854a mv a0,s2 + 53d0: d9afe0ef jal ra,396a + 53d4: 05090a13 addi s4,s2,80 + 53d8: 05098613 addi a2,s3,80 + 53dc: 85b2 mv a1,a2 + 53de: 8552 mv a0,s4 + 53e0: d64fe0ef jal ra,3944 + 53e4: 07890a93 addi s5,s2,120 + 53e8: 050b8613 addi a2,s7,80 + 53ec: 07898593 addi a1,s3,120 + 53f0: 8556 mv a0,s5 + 53f2: c57fe0ef jal ra,4048 + 53f6: 8656 mv a2,s5 + 53f8: 85d2 mv a1,s4 + 53fa: 8522 mv a0,s0 + 53fc: d48fe0ef jal ra,3944 + 5400: 8656 mv a2,s5 + 5402: 85d2 mv a1,s4 + 5404: 8526 mv a0,s1 + 5406: d64fe0ef jal ra,396a + 540a: 865a mv a2,s6 + 540c: 85ca mv a1,s2 + 540e: 8556 mv a0,s5 + 5410: c39fe0ef jal ra,4048 + 5414: 8626 mv a2,s1 + 5416: 85ca mv a1,s2 + 5418: 854a mv a0,s2 + 541a: c2ffe0ef jal ra,4048 + 541e: 8622 mv a2,s0 + 5420: 85da mv a1,s6 + 5422: 855a mv a0,s6 + 5424: c25fe0ef jal ra,4048 + 5428: 8626 mv a2,s1 + 542a: 85a2 mv a1,s0 + 542c: 8552 mv a0,s4 + 542e: c1bfe0ef jal ra,4048 + 5432: dcffa06f j 200 <__riscv_restore_10> + +00005436 : + 5436: da1fa2ef jal t0,1d6 <__riscv_save_4> + 543a: 8432 mv s0,a2 + 543c: 8a2a mv s4,a0 + 543e: 8aae mv s5,a1 + 5440: 8532 mv a0,a2 + 5442: 02840493 addi s1,s0,40 + 5446: e9eff0ef jal ra,4ae4 + 544a: 028a8b13 addi s6,s5,40 + 544e: 85da mv a1,s6 + 5450: 8526 mv a0,s1 + 5452: 05040913 addi s2,s0,80 + 5456: e8eff0ef jal ra,4ae4 + 545a: 050a8593 addi a1,s5,80 + 545e: 854a mv a0,s2 + 5460: e84ff0ef jal ra,4ae4 + 5464: 85ca mv a1,s2 + 5466: 854a mv a0,s2 + 5468: 4609 li a2,2 + 546a: 07840993 addi s3,s0,120 + 546e: 8e9fe0ef jal ra,3d56 + 5472: 865a mv a2,s6 + 5474: 85d6 mv a1,s5 + 5476: 854e mv a0,s3 + 5478: cccfe0ef jal ra,3944 + 547c: 078a0a93 addi s5,s4,120 + 5480: 85ce mv a1,s3 + 5482: 8556 mv a0,s5 + 5484: e60ff0ef jal ra,4ae4 + 5488: 8622 mv a2,s0 + 548a: 85a6 mv a1,s1 + 548c: 854e mv a0,s3 + 548e: cb6fe0ef jal ra,3944 + 5492: 8622 mv a2,s0 + 5494: 85a6 mv a1,s1 + 5496: 8526 mv a0,s1 + 5498: cd2fe0ef jal ra,396a + 549c: 864e mv a2,s3 + 549e: 85d6 mv a1,s5 + 54a0: 8522 mv a0,s0 + 54a2: cc8fe0ef jal ra,396a + 54a6: 8626 mv a2,s1 + 54a8: 85ca mv a1,s2 + 54aa: 854a mv a0,s2 + 54ac: cbefe0ef jal ra,396a + 54b0: 864a mv a2,s2 + 54b2: 85a2 mv a1,s0 + 54b4: 8552 mv a0,s4 + 54b6: b93fe0ef jal ra,4048 + 54ba: 8626 mv a2,s1 + 54bc: 85ce mv a1,s3 + 54be: 028a0513 addi a0,s4,40 + 54c2: b87fe0ef jal ra,4048 + 54c6: 864a mv a2,s2 + 54c8: 85a6 mv a1,s1 + 54ca: 050a0513 addi a0,s4,80 + 54ce: b7bfe0ef jal ra,4048 + 54d2: 864e mv a2,s3 + 54d4: 85a2 mv a1,s0 + 54d6: 8556 mv a0,s5 + 54d8: b71fe0ef jal ra,4048 + 54dc: d2ffa06f j 20a <__riscv_restore_4> + +000054e0 : + 54e0: d11fa2ef jal t0,1f0 <__riscv_save_0> + 54e4: 84aa mv s1,a0 + 54e6: 892e mv s2,a1 + 54e8: 0fc00413 li s0,252 + 54ec: 85a2 mv a1,s0 + 54ee: 854a mv a0,s2 + 54f0: c6bff0ef jal ra,515a + 54f4: e119 bnez a0,54fa + 54f6: 147d addi s0,s0,-1 + 54f8: f875 bnez s0,54ec + 54fa: 0405 addi s0,s0,1 + 54fc: 57fd li a5,-1 + 54fe: b0a0 sb s0,3(s1) + 5500: a09e sh a5,0(s1) + 5502: a0bc sb a5,2(s1) + 5504: d11fa06f j 214 <__riscv_restore_0> + +00005508 : + 5508: cc1fa2ef jal t0,1c8 <__riscv_save_10> + 550c: 3124 lbu s1,3(a0) + 550e: 89aa mv s3,a0 + 5510: 8932 mv s2,a2 + 5512: 02c49363 bne s1,a2,5538 + 5516: 8aae mv s5,a1 + 5518: 8536 mv a0,a3 + 551a: 85b2 mv a1,a2 + 551c: 8b36 mv s6,a3 + 551e: fff90a13 addi s4,s2,-1 + 5522: c39ff0ef jal ra,515a + 5526: 842a mv s0,a0 + 5528: 85d2 mv a1,s4 + 552a: 855a mv a0,s6 + 552c: c2fff0ef jal ra,515a + 5530: 00a41d63 bne s0,a0,554a + 5534: 014981a3 sb s4,3(s3) + 5538: 00099783 lh a5,0(s3) + 553c: 4501 li a0,0 + 553e: 01279463 bne a5,s2,5546 + 5542: 00298503 lb a0,2(s3) + 5546: cbbfa06f j 200 <__riscv_restore_10> + 554a: 00148a13 addi s4,s1,1 + 554e: 014ad363 bge s5,s4,5554 + 5552: 8a56 mv s4,s5 + 5554: fffa0513 addi a0,s4,-1 + 5558: 00a41433 sll s0,s0,a0 + 555c: 40800433 neg s0,s0 + 5560: 4a81 li s5,0 + 5562: 41490c33 sub s8,s2,s4 + 5566: 8bd6 mv s7,s5 + 5568: 0a85 addi s5,s5,1 + 556a: 055a1863 bne s4,s5,55ba + 556e: 85e2 mv a1,s8 + 5570: 855a mv a0,s6 + 5572: be9ff0ef jal ra,515a + 5576: 9522 add a0,a0,s0 + 5578: 40a007b3 neg a5,a0 + 557c: 8fe9 and a5,a5,a0 + 557e: 0aa7f413 andi s0,a5,170 + 5582: 0cc7f713 andi a4,a5,204 + 5586: 00803433 snez s0,s0 + 558a: c311 beqz a4,558e + 558c: 4709 li a4,2 + 558e: 0f07f793 andi a5,a5,240 + 5592: 8c59 or s0,s0,a4 + 5594: c391 beqz a5,5598 + 5596: 4791 li a5,4 + 5598: 00190713 addi a4,s2,1 + 559c: 8fc1 or a5,a5,s0 + 559e: 41470733 sub a4,a4,s4 + 55a2: 973e add a4,a4,a5 + 55a4: 40f55533 sra a0,a0,a5 + 55a8: 414484b3 sub s1,s1,s4 + 55ac: 00e99023 sh a4,0(s3) + 55b0: 00a98123 sb a0,2(s3) + 55b4: 009981a3 sb s1,3(s3) + 55b8: b741 j 5538 + 55ba: 015c05b3 add a1,s8,s5 + 55be: 855a mv a0,s6 + 55c0: b9bff0ef jal ra,515a + 55c4: 01751533 sll a0,a0,s7 + 55c8: 942a add s0,s0,a0 + 55ca: bf71 j 5566 + +000055cc : + 55cc: bf5fa2ef jal t0,1c0 <__riscv_save_12> + 55d0: 1141 addi sp,sp,-16 + 55d2: 892e mv s2,a1 + 55d4: 8a2a mv s4,a0 + 55d6: 85c2 mv a1,a6 + 55d8: 853e mv a0,a5 + 55da: 8b3e mv s6,a5 + 55dc: 8bc2 mv s7,a6 + 55de: c63a sw a4,12(sp) + 55e0: 89b2 mv s3,a2 + 55e2: 8ab6 mv s5,a3 + 55e4: b77ff0ef jal ra,515a + 55e8: 020b8593 addi a1,s7,32 + 55ec: 842a mv s0,a0 + 55ee: 855a mv a0,s6 + 55f0: b6bff0ef jal ra,515a + 55f4: 040b8593 addi a1,s7,64 + 55f8: 84aa mv s1,a0 + 55fa: 855a mv a0,s6 + 55fc: b5fff0ef jal ra,515a + 5600: 050a slli a0,a0,0x2 + 5602: 0486 slli s1,s1,0x1 + 5604: 94aa add s1,s1,a0 + 5606: 060b8593 addi a1,s7,96 + 560a: 855a mv a0,s6 + 560c: 9426 add s0,s0,s1 + 560e: b4dff0ef jal ra,515a + 5612: 0ff47413 andi s0,s0,255 + 5616: 050e slli a0,a0,0x3 + 5618: 9522 add a0,a0,s0 + 561a: 0ff57513 andi a0,a0,255 + 561e: 00355b13 srli s6,a0,0x3 + 5622: 4732 lw a4,12(sp) + 5624: fffb0c93 addi s9,s6,-1 + 5628: 00acc533 xor a0,s9,a0 + 562c: 00757c93 andi s9,a0,7 + 5630: 84ba mv s1,a4 + 5632: 4d01 li s10,0 + 5634: 02890c13 addi s8,s2,40 + 5638: 05090b93 addi s7,s2,80 + 563c: 4da1 li s11,8 + 563e: 01acc433 xor s0,s9,s10 + 5642: 147d addi s0,s0,-1 + 5644: 8021 srli s0,s0,0x8 + 5646: 8805 andi s0,s0,1 + 5648: 85a6 mv a1,s1 + 564a: 8622 mv a2,s0 + 564c: 854a mv a0,s2 + 564e: c18fe0ef jal ra,3a66 + 5652: 02848593 addi a1,s1,40 + 5656: 8622 mv a2,s0 + 5658: 8562 mv a0,s8 + 565a: c0cfe0ef jal ra,3a66 + 565e: 05048593 addi a1,s1,80 + 5662: 8622 mv a2,s0 + 5664: 855e mv a0,s7 + 5666: 0d05 addi s10,s10,1 + 5668: bfefe0ef jal ra,3a66 + 566c: 07848493 addi s1,s1,120 + 5670: fdbd17e3 bne s10,s11,563e + 5674: 85de mv a1,s7 + 5676: 854e mv a0,s3 + 5678: aaefe0ef jal ra,3926 + 567c: 001b4b13 xori s6,s6,1 + 5680: 865a mv a2,s6 + 5682: 85ce mv a1,s3 + 5684: 855e mv a0,s7 + 5686: b0cfe0ef jal ra,3992 + 568a: 865a mv a2,s6 + 568c: 85e2 mv a1,s8 + 568e: 854a mv a0,s2 + 5690: b02fe0ef jal ra,3992 + 5694: 8756 mv a4,s5 + 5696: 86ce mv a3,s3 + 5698: 864a mv a2,s2 + 569a: 85d2 mv a1,s4 + 569c: 8552 mv a0,s4 + 569e: ce3ff0ef jal ra,5380 + 56a2: 0141 addi sp,sp,16 + 56a4: b59fa06f j 1fc <__riscv_restore_12> + +000056a8 : + 56a8: b49fa2ef jal t0,1f0 <__riscv_save_0> + 56ac: a14fe0ef jal ra,38c0 + 56b0: 8d4d or a0,a0,a1 + 56b2: 00153513 seqz a0,a0 + 56b6: 157d addi a0,a0,-1 + 56b8: b5dfa06f j 214 <__riscv_restore_0> + +000056bc : + 56bc: 4781 li a5,0 + 56be: 00b79363 bne a5,a1,56c4 + 56c2: 8082 ret + 56c4: 00f50733 add a4,a0,a5 + 56c8: 00070023 sb zero,0(a4) # 2000000 <_data_lma+0x1ff1da4> + 56cc: 0785 addi a5,a5,1 + 56ce: bfc5 j 56be + +000056d0 : + 56d0: b21fa2ef jal t0,1f0 <__riscv_save_0> + 56d4: 7179 addi sp,sp,-48 + 56d6: 842a mv s0,a0 + 56d8: 4781 li a5,0 + 56da: 02800713 li a4,40 + 56de: 00f58633 add a2,a1,a5 + 56e2: 4210 lw a2,0(a2) + 56e4: 0034 addi a3,sp,8 + 56e6: 96be add a3,a3,a5 + 56e8: c290 sw a2,0(a3) + 56ea: 0791 addi a5,a5,4 + 56ec: fee799e3 bne a5,a4,56de + 56f0: 5732 lw a4,44(sp) + 56f2: 47cd li a5,19 + 56f4: 1810 addi a2,sp,48 + 56f6: 02e787b3 mul a5,a5,a4 + 56fa: 01000737 lui a4,0x1000 + 56fe: 97ba add a5,a5,a4 + 5700: 0038 addi a4,sp,8 + 5702: 87e5 srai a5,a5,0x19 + 5704: 86ba mv a3,a4 + 5706: 428c lw a1,0(a3) + 5708: 06a1 addi a3,a3,8 + 570a: 97ae add a5,a5,a1 + 570c: ffc6a583 lw a1,-4(a3) # fffffc <_data_lma+0xff1da0> + 5710: 87e9 srai a5,a5,0x1a + 5712: 97ae add a5,a5,a1 + 5714: 87e5 srai a5,a5,0x19 + 5716: fed618e3 bne a2,a3,5706 + 571a: 46cd li a3,19 + 571c: 02d787b3 mul a5,a5,a3 + 5720: 4314 lw a3,0(a4) + 5722: 0721 addi a4,a4,8 + 5724: 97b6 add a5,a5,a3 + 5726: 41a7d693 srai a3,a5,0x1a + 572a: 01a69593 slli a1,a3,0x1a + 572e: 8f8d sub a5,a5,a1 + 5730: fef72c23 sw a5,-8(a4) # fffff8 <_data_lma+0xff1d9c> + 5734: ffc72783 lw a5,-4(a4) + 5738: 96be add a3,a3,a5 + 573a: 4196d793 srai a5,a3,0x19 + 573e: 01979593 slli a1,a5,0x19 + 5742: 8e8d sub a3,a3,a1 + 5744: fed72e23 sw a3,-4(a4) + 5748: fce61ce3 bne a2,a4,5720 + 574c: 47b2 lw a5,12(sp) + 574e: 45a2 lw a1,8(sp) + 5750: 8522 mv a0,s0 + 5752: 07ea slli a5,a5,0x1a + 5754: 8ddd or a1,a1,a5 + 5756: 8c4fe0ef jal ra,381a + 575a: 45b2 lw a1,12(sp) + 575c: 47c2 lw a5,16(sp) + 575e: 00440513 addi a0,s0,4 + 5762: 8199 srli a1,a1,0x6 + 5764: 07ce slli a5,a5,0x13 + 5766: 8ddd or a1,a1,a5 + 5768: 8b2fe0ef jal ra,381a + 576c: 45c2 lw a1,16(sp) + 576e: 47d2 lw a5,20(sp) + 5770: 00840513 addi a0,s0,8 + 5774: 81b5 srli a1,a1,0xd + 5776: 07b6 slli a5,a5,0xd + 5778: 8ddd or a1,a1,a5 + 577a: 8a0fe0ef jal ra,381a + 577e: 45d2 lw a1,20(sp) + 5780: 47e2 lw a5,24(sp) + 5782: 00c40513 addi a0,s0,12 + 5786: 81cd srli a1,a1,0x13 + 5788: 079a slli a5,a5,0x6 + 578a: 8ddd or a1,a1,a5 + 578c: 88efe0ef jal ra,381a + 5790: 5782 lw a5,32(sp) + 5792: 45f2 lw a1,28(sp) + 5794: 01040513 addi a0,s0,16 + 5798: 07e6 slli a5,a5,0x19 + 579a: 8ddd or a1,a1,a5 + 579c: 87efe0ef jal ra,381a + 57a0: 5582 lw a1,32(sp) + 57a2: 5792 lw a5,36(sp) + 57a4: 01440513 addi a0,s0,20 + 57a8: 819d srli a1,a1,0x7 + 57aa: 07ce slli a5,a5,0x13 + 57ac: 8ddd or a1,a1,a5 + 57ae: 86cfe0ef jal ra,381a + 57b2: 5592 lw a1,36(sp) + 57b4: 57a2 lw a5,40(sp) + 57b6: 01840513 addi a0,s0,24 + 57ba: 81b5 srli a1,a1,0xd + 57bc: 07b2 slli a5,a5,0xc + 57be: 8ddd or a1,a1,a5 + 57c0: 85afe0ef jal ra,381a + 57c4: 55a2 lw a1,40(sp) + 57c6: 57b2 lw a5,44(sp) + 57c8: 01c40513 addi a0,s0,28 + 57cc: 81d1 srli a1,a1,0x14 + 57ce: 079a slli a5,a5,0x6 + 57d0: 8ddd or a1,a1,a5 + 57d2: 848fe0ef jal ra,381a + 57d6: 0028 addi a0,sp,8 + 57d8: 02800593 li a1,40 + 57dc: ee1ff0ef jal ra,56bc + 57e0: 6145 addi sp,sp,48 + 57e2: a33fa06f j 214 <__riscv_restore_0> + +000057e6 : + 57e6: a0bfa2ef jal t0,1f0 <__riscv_save_0> + 57ea: 7139 addi sp,sp,-64 + 57ec: 842e mv s0,a1 + 57ee: 85aa mv a1,a0 + 57f0: 850a mv a0,sp + 57f2: edfff0ef jal ra,56d0 + 57f6: 85a2 mv a1,s0 + 57f8: 1008 addi a0,sp,32 + 57fa: ed7ff0ef jal ra,56d0 + 57fe: 100c addi a1,sp,32 + 5800: 850a mv a0,sp + 5802: ea7ff0ef jal ra,56a8 + 5806: 842a mv s0,a0 + 5808: 02000593 li a1,32 + 580c: 850a mv a0,sp + 580e: eafff0ef jal ra,56bc + 5812: 1008 addi a0,sp,32 + 5814: 02000593 li a1,32 + 5818: ea5ff0ef jal ra,56bc + 581c: 00140513 addi a0,s0,1 + 5820: 6121 addi sp,sp,64 + 5822: 9f3fa06f j 214 <__riscv_restore_0> + +00005826 : + 5826: 9b1fa2ef jal t0,1d6 <__riscv_save_4> + 582a: 7119 addi sp,sp,-128 + 582c: 892a mv s2,a0 + 582e: 0028 addi a0,sp,8 + 5830: 842e mv s0,a1 + 5832: ab2ff0ef jal ra,4ae4 + 5836: 002c addi a1,sp,8 + 5838: 1808 addi a0,sp,48 + 583a: aaaff0ef jal ra,4ae4 + 583e: 180c addi a1,sp,48 + 5840: 852e mv a0,a1 + 5842: aa2ff0ef jal ra,4ae4 + 5846: 1810 addi a2,sp,48 + 5848: 8532 mv a0,a2 + 584a: 85a2 mv a1,s0 + 584c: ffcfe0ef jal ra,4048 + 5850: 002c addi a1,sp,8 + 5852: 1810 addi a2,sp,48 + 5854: 852e mv a0,a1 + 5856: ff2fe0ef jal ra,4048 + 585a: 002c addi a1,sp,8 + 585c: 852e mv a0,a1 + 585e: a86ff0ef jal ra,4ae4 + 5862: 0030 addi a2,sp,8 + 5864: 8532 mv a0,a2 + 5866: 180c addi a1,sp,48 + 5868: fe0fe0ef jal ra,4048 + 586c: 002c addi a1,sp,8 + 586e: 1808 addi a0,sp,48 + 5870: a74ff0ef jal ra,4ae4 + 5874: 4491 li s1,4 + 5876: 180c addi a1,sp,48 + 5878: 852e mv a0,a1 + 587a: 14fd addi s1,s1,-1 + 587c: a68ff0ef jal ra,4ae4 + 5880: f8fd bnez s1,5876 + 5882: 0030 addi a2,sp,8 + 5884: 8532 mv a0,a2 + 5886: 180c addi a1,sp,48 + 5888: fc0fe0ef jal ra,4048 + 588c: 002c addi a1,sp,8 + 588e: 1808 addi a0,sp,48 + 5890: a54ff0ef jal ra,4ae4 + 5894: 44a5 li s1,9 + 5896: 180c addi a1,sp,48 + 5898: 852e mv a0,a1 + 589a: 14fd addi s1,s1,-1 + 589c: a48ff0ef jal ra,4ae4 + 58a0: f8fd bnez s1,5896 + 58a2: 180c addi a1,sp,48 + 58a4: 852e mv a0,a1 + 58a6: 0030 addi a2,sp,8 + 58a8: fa0fe0ef jal ra,4048 + 58ac: 180c addi a1,sp,48 + 58ae: 08a8 addi a0,sp,88 + 58b0: a34ff0ef jal ra,4ae4 + 58b4: 44cd li s1,19 + 58b6: 08ac addi a1,sp,88 + 58b8: 852e mv a0,a1 + 58ba: 14fd addi s1,s1,-1 + 58bc: a28ff0ef jal ra,4ae4 + 58c0: f8fd bnez s1,58b6 + 58c2: 1810 addi a2,sp,48 + 58c4: 8532 mv a0,a2 + 58c6: 08ac addi a1,sp,88 + 58c8: f80fe0ef jal ra,4048 + 58cc: 180c addi a1,sp,48 + 58ce: 852e mv a0,a1 + 58d0: a14ff0ef jal ra,4ae4 + 58d4: 44a5 li s1,9 + 58d6: 180c addi a1,sp,48 + 58d8: 852e mv a0,a1 + 58da: 14fd addi s1,s1,-1 + 58dc: a08ff0ef jal ra,4ae4 + 58e0: f8fd bnez s1,58d6 + 58e2: 0030 addi a2,sp,8 + 58e4: 8532 mv a0,a2 + 58e6: 180c addi a1,sp,48 + 58e8: f60fe0ef jal ra,4048 + 58ec: 002c addi a1,sp,8 + 58ee: 1808 addi a0,sp,48 + 58f0: 9f4ff0ef jal ra,4ae4 + 58f4: 03100493 li s1,49 + 58f8: 180c addi a1,sp,48 + 58fa: 852e mv a0,a1 + 58fc: 14fd addi s1,s1,-1 + 58fe: 9e6ff0ef jal ra,4ae4 + 5902: f8fd bnez s1,58f8 + 5904: 180c addi a1,sp,48 + 5906: 852e mv a0,a1 + 5908: 0030 addi a2,sp,8 + 590a: f3efe0ef jal ra,4048 + 590e: 180c addi a1,sp,48 + 5910: 08a8 addi a0,sp,88 + 5912: 9d2ff0ef jal ra,4ae4 + 5916: 06300493 li s1,99 + 591a: 08ac addi a1,sp,88 + 591c: 852e mv a0,a1 + 591e: 14fd addi s1,s1,-1 + 5920: 9c4ff0ef jal ra,4ae4 + 5924: f8fd bnez s1,591a + 5926: 1810 addi a2,sp,48 + 5928: 8532 mv a0,a2 + 592a: 08ac addi a1,sp,88 + 592c: f1cfe0ef jal ra,4048 + 5930: 180c addi a1,sp,48 + 5932: 852e mv a0,a1 + 5934: 9b0ff0ef jal ra,4ae4 + 5938: 03100493 li s1,49 + 593c: 180c addi a1,sp,48 + 593e: 852e mv a0,a1 + 5940: 14fd addi s1,s1,-1 + 5942: 9a2ff0ef jal ra,4ae4 + 5946: f8fd bnez s1,593c + 5948: 0030 addi a2,sp,8 + 594a: 8532 mv a0,a2 + 594c: 180c addi a1,sp,48 + 594e: efafe0ef jal ra,4048 + 5952: 002c addi a1,sp,8 + 5954: 852e mv a0,a1 + 5956: 98eff0ef jal ra,4ae4 + 595a: 002c addi a1,sp,8 + 595c: 852e mv a0,a1 + 595e: 986ff0ef jal ra,4ae4 + 5962: 002c addi a1,sp,8 + 5964: 8622 mv a2,s0 + 5966: 852e mv a0,a1 + 5968: ee0fe0ef jal ra,4048 + 596c: 002c addi a1,sp,8 + 596e: 1808 addi a0,sp,48 + 5970: 974ff0ef jal ra,4ae4 + 5974: 180c addi a1,sp,48 + 5976: 8622 mv a2,s0 + 5978: 852e mv a0,a1 + 597a: ecefe0ef jal ra,4048 + 597e: 08a8 addi a0,sp,88 + 5980: f65fd0ef jal ra,38e4 + 5984: 08ac addi a1,sp,88 + 5986: 8522 mv a0,s0 + 5988: e5fff0ef jal ra,57e6 + 598c: 842a mv s0,a0 + 598e: 08a8 addi a0,sp,88 + 5990: f65fd0ef jal ra,38f4 + 5994: 08ac addi a1,sp,88 + 5996: 1808 addi a0,sp,48 + 5998: e4fff0ef jal ra,57e6 + 599c: 08ac addi a1,sp,88 + 599e: 8aaa mv s5,a0 + 59a0: 852e mv a0,a1 + 59a2: f85fd0ef jal ra,3926 + 59a6: 08ac addi a1,sp,88 + 59a8: 1808 addi a0,sp,48 + 59aa: e3dff0ef jal ra,57e6 + 59ae: 6a35 lui s4,0xd + 59b0: 89aa mv s3,a0 + 59b2: 324a0593 addi a1,s4,804 # d324 + 59b6: 08a8 addi a0,sp,88 + 59b8: f6ffd0ef jal ra,3926 + 59bc: 08ac addi a1,sp,88 + 59be: 1808 addi a0,sp,48 + 59c0: e27ff0ef jal ra,57e6 + 59c4: 324a0613 addi a2,s4,804 + 59c8: 002c addi a1,sp,8 + 59ca: 84aa mv s1,a0 + 59cc: 854a mv a0,s2 + 59ce: e7afe0ef jal ra,4048 + 59d2: 0099e4b3 or s1,s3,s1 + 59d6: 4605 li a2,1 + 59d8: 8e05 sub a2,a2,s1 + 59da: 002c addi a1,sp,8 + 59dc: 854a mv a0,s2 + 59de: 888fe0ef jal ra,3a66 + 59e2: 0028 addi a0,sp,8 + 59e4: 02800593 li a1,40 + 59e8: cd5ff0ef jal ra,56bc + 59ec: 1808 addi a0,sp,48 + 59ee: 02800593 li a1,40 + 59f2: ccbff0ef jal ra,56bc + 59f6: 08a8 addi a0,sp,88 + 59f8: 02800593 li a1,40 + 59fc: cc1ff0ef jal ra,56bc + 5a00: 01546533 or a0,s0,s5 + 5a04: 01356533 or a0,a0,s3 + 5a08: 6109 addi sp,sp,128 + 5a0a: 801fa06f j 20a <__riscv_restore_4> + +00005a0e : + 5a0e: fe2fa2ef jal t0,1f0 <__riscv_save_0> + 5a12: 7139 addi sp,sp,-64 + 5a14: 842a mv s0,a0 + 5a16: 0828 addi a0,sp,24 + 5a18: c62e sw a1,12(sp) + 5a1a: 8caff0ef jal ra,4ae4 + 5a1e: 082c addi a1,sp,24 + 5a20: 852e mv a0,a1 + 5a22: e05ff0ef jal ra,5826 + 5a26: 082c addi a1,sp,24 + 5a28: 852e mv a0,a1 + 5a2a: 8baff0ef jal ra,4ae4 + 5a2e: 4632 lw a2,12(sp) + 5a30: 082c addi a1,sp,24 + 5a32: 8522 mv a0,s0 + 5a34: e14fe0ef jal ra,4048 + 5a38: 0828 addi a0,sp,24 + 5a3a: 02800593 li a1,40 + 5a3e: c7fff0ef jal ra,56bc + 5a42: 6121 addi sp,sp,64 + 5a44: fd0fa06f j 214 <__riscv_restore_0> + +00005a48 : + 5a48: f8efa2ef jal t0,1d6 <__riscv_save_4> + 5a4c: 712d addi sp,sp,-288 + 5a4e: 8a2a mv s4,a0 + 5a50: 8b2e mv s6,a1 + 5a52: 0028 addi a0,sp,8 + 5a54: 85b2 mv a1,a2 + 5a56: 4605 li a2,1 + 5a58: 84b6 mv s1,a3 + 5a5a: 8a4fe0ef jal ra,3afe + 5a5e: 1808 addi a0,sp,48 + 5a60: e95fd0ef jal ra,38f4 + 5a64: 08a8 addi a0,sp,88 + 5a66: e7ffd0ef jal ra,38e4 + 5a6a: 002c addi a1,sp,8 + 5a6c: 0108 addi a0,sp,128 + 5a6e: e9ffd0ef jal ra,390c + 5a72: 1128 addi a0,sp,168 + 5a74: 6979 lui s2,0x1e + 5a76: e7ffd0ef jal ra,38f4 + 5a7a: 14fd addi s1,s1,-1 + 5a7c: 4401 li s0,0 + 5a7e: b4290913 addi s2,s2,-1214 # 1db42 <_data_lma+0xf8e6> + 5a82: 5afd li s5,-1 + 5a84: 85a6 mv a1,s1 + 5a86: 855a mv a0,s6 + 5a88: ed2ff0ef jal ra,515a + 5a8c: 8c29 xor s0,s0,a0 + 5a8e: 8622 mv a2,s0 + 5a90: 89aa mv s3,a0 + 5a92: 010c addi a1,sp,128 + 5a94: 1808 addi a0,sp,48 + 5a96: efdfd0ef jal ra,3992 + 5a9a: 8622 mv a2,s0 + 5a9c: 112c addi a1,sp,168 + 5a9e: 08a8 addi a0,sp,88 + 5aa0: ef3fd0ef jal ra,3992 + 5aa4: 1130 addi a2,sp,168 + 5aa6: 010c addi a1,sp,128 + 5aa8: 0988 addi a0,sp,208 + 5aaa: ec1fd0ef jal ra,396a + 5aae: 08b0 addi a2,sp,88 + 5ab0: 180c addi a1,sp,48 + 5ab2: 19a8 addi a0,sp,248 + 5ab4: eb7fd0ef jal ra,396a + 5ab8: 180c addi a1,sp,48 + 5aba: 852e mv a0,a1 + 5abc: 08b0 addi a2,sp,88 + 5abe: e87fd0ef jal ra,3944 + 5ac2: 1130 addi a2,sp,168 + 5ac4: 010c addi a1,sp,128 + 5ac6: 08a8 addi a0,sp,88 + 5ac8: e7dfd0ef jal ra,3944 + 5acc: 1810 addi a2,sp,48 + 5ace: 098c addi a1,sp,208 + 5ad0: 1128 addi a0,sp,168 + 5ad2: d76fe0ef jal ra,4048 + 5ad6: 08ac addi a1,sp,88 + 5ad8: 19b0 addi a2,sp,248 + 5ada: 852e mv a0,a1 + 5adc: d6cfe0ef jal ra,4048 + 5ae0: 19ac addi a1,sp,248 + 5ae2: 0988 addi a0,sp,208 + 5ae4: 800ff0ef jal ra,4ae4 + 5ae8: 180c addi a1,sp,48 + 5aea: 19a8 addi a0,sp,248 + 5aec: ff9fe0ef jal ra,4ae4 + 5af0: 08b0 addi a2,sp,88 + 5af2: 112c addi a1,sp,168 + 5af4: 0108 addi a0,sp,128 + 5af6: e4ffd0ef jal ra,3944 + 5afa: 08b0 addi a2,sp,88 + 5afc: 8532 mv a0,a2 + 5afe: 112c addi a1,sp,168 + 5b00: e6bfd0ef jal ra,396a + 5b04: 0990 addi a2,sp,208 + 5b06: 19ac addi a1,sp,248 + 5b08: 1808 addi a0,sp,48 + 5b0a: d3efe0ef jal ra,4048 + 5b0e: 19ac addi a1,sp,248 + 5b10: 0990 addi a2,sp,208 + 5b12: 852e mv a0,a1 + 5b14: e57fd0ef jal ra,396a + 5b18: 08ac addi a1,sp,88 + 5b1a: 852e mv a0,a1 + 5b1c: fc9fe0ef jal ra,4ae4 + 5b20: 864a mv a2,s2 + 5b22: 19ac addi a1,sp,248 + 5b24: 1128 addi a0,sp,168 + 5b26: a30fe0ef jal ra,3d56 + 5b2a: 010c addi a1,sp,128 + 5b2c: 852e mv a0,a1 + 5b2e: fb7fe0ef jal ra,4ae4 + 5b32: 098c addi a1,sp,208 + 5b34: 852e mv a0,a1 + 5b36: 1130 addi a2,sp,168 + 5b38: e0dfd0ef jal ra,3944 + 5b3c: 08b0 addi a2,sp,88 + 5b3e: 002c addi a1,sp,8 + 5b40: 1128 addi a0,sp,168 + 5b42: d06fe0ef jal ra,4048 + 5b46: 0990 addi a2,sp,208 + 5b48: 19ac addi a1,sp,248 + 5b4a: 08a8 addi a0,sp,88 + 5b4c: 14fd addi s1,s1,-1 + 5b4e: cfafe0ef jal ra,4048 + 5b52: 844e mv s0,s3 + 5b54: f35498e3 bne s1,s5,5a84 + 5b58: 864e mv a2,s3 + 5b5a: 010c addi a1,sp,128 + 5b5c: 1808 addi a0,sp,48 + 5b5e: e35fd0ef jal ra,3992 + 5b62: 864e mv a2,s3 + 5b64: 112c addi a1,sp,168 + 5b66: 08a8 addi a0,sp,88 + 5b68: e2bfd0ef jal ra,3992 + 5b6c: 08ac addi a1,sp,88 + 5b6e: 852e mv a0,a1 + 5b70: e9fff0ef jal ra,5a0e + 5b74: 180c addi a1,sp,48 + 5b76: 08b0 addi a2,sp,88 + 5b78: 852e mv a0,a1 + 5b7a: ccefe0ef jal ra,4048 + 5b7e: 180c addi a1,sp,48 + 5b80: 8552 mv a0,s4 + 5b82: b4fff0ef jal ra,56d0 + 5b86: 0028 addi a0,sp,8 + 5b88: 02800593 li a1,40 + 5b8c: b31ff0ef jal ra,56bc + 5b90: 1808 addi a0,sp,48 + 5b92: 02800593 li a1,40 + 5b96: b27ff0ef jal ra,56bc + 5b9a: 08a8 addi a0,sp,88 + 5b9c: 02800593 li a1,40 + 5ba0: b1dff0ef jal ra,56bc + 5ba4: 0988 addi a0,sp,208 + 5ba6: 02800593 li a1,40 + 5baa: b13ff0ef jal ra,56bc + 5bae: 0108 addi a0,sp,128 + 5bb0: 02800593 li a1,40 + 5bb4: b09ff0ef jal ra,56bc + 5bb8: 1128 addi a0,sp,168 + 5bba: 02800593 li a1,40 + 5bbe: affff0ef jal ra,56bc + 5bc2: 19a8 addi a0,sp,248 + 5bc4: 02800593 li a1,40 + 5bc8: af5ff0ef jal ra,56bc + 5bcc: 6115 addi sp,sp,288 + 5bce: e3cfa06f j 20a <__riscv_restore_4> + +00005bd2 : + 5bd2: e1efa2ef jal t0,1f0 <__riscv_save_0> + 5bd6: 7159 addi sp,sp,-112 + 5bd8: 842e mv s0,a1 + 5bda: 84aa mv s1,a0 + 5bdc: 4581 li a1,0 + 5bde: 06400613 li a2,100 + 5be2: 0068 addi a0,sp,12 + 5be4: e3cfa0ef jal ra,220 + 5be8: 006c addi a1,sp,12 + 5bea: 6eb5 lui t4,0xd + 5bec: 882e mv a6,a1 + 5bee: 4301 li t1,0 + 5bf0: 300e8e93 addi t4,t4,768 # d300 + 5bf4: 04040f93 addi t6,s0,64 + 5bf8: 02400293 li t0,36 + 5bfc: 006e87b3 add a5,t4,t1 + 5c00: 0007af03 lw t5,0(a5) # 1000000 <_data_lma+0xff1da4> + 5c04: 8622 mv a2,s0 + 5c06: 88a2 mv a7,s0 + 5c08: 8542 mv a0,a6 + 5c0a: 4701 li a4,0 + 5c0c: 0008a783 lw a5,0(a7) + 5c10: 0891 addi a7,a7,4 + 5c12: 0511 addi a0,a0,4 + 5c14: 02ff06b3 mul a3,t5,a5 + 5c18: 02ff3e33 mulhu t3,t5,a5 + 5c1c: ffc52783 lw a5,-4(a0) + 5c20: 97b6 add a5,a5,a3 + 5c22: 973e add a4,a4,a5 + 5c24: 00d7b6b3 sltu a3,a5,a3 + 5c28: fee52e23 sw a4,-4(a0) + 5c2c: 00f737b3 sltu a5,a4,a5 + 5c30: 96f2 add a3,a3,t3 + 5c32: 00d78733 add a4,a5,a3 + 5c36: fdf89be3 bne a7,t6,5c0c + 5c3a: 04e82023 sw a4,64(a6) + 5c3e: 0311 addi t1,t1,4 + 5c40: 0811 addi a6,a6,4 + 5c42: fa531de3 bne t1,t0,5bfc + 5c46: c602 sw zero,12(sp) + 5c48: c802 sw zero,16(sp) + 5c4a: ca02 sw zero,20(sp) + 5c4c: cc02 sw zero,24(sp) + 5c4e: ce02 sw zero,28(sp) + 5c50: d002 sw zero,32(sp) + 5c52: d202 sw zero,36(sp) + 5c54: d402 sw zero,40(sp) + 5c56: 00c10813 addi a6,sp,12 + 5c5a: 48a1 li a7,8 + 5c5c: 6f31 lui t5,0xc + 5c5e: 710f0e93 addi t4,t5,1808 # c710 + 5c62: 8542 mv a0,a6 + 5c64: 4e01 li t3,0 + 5c66: 4681 li a3,0 + 5c68: 04082783 lw a5,64(a6) + 5c6c: 000ea303 lw t1,0(t4) + 5c70: 0e05 addi t3,t3,1 + 5c72: 0511 addi a0,a0,4 + 5c74: 02678733 mul a4,a5,t1 + 5c78: 0e91 addi t4,t4,4 + 5c7a: 0267b333 mulhu t1,a5,t1 + 5c7e: ffc52783 lw a5,-4(a0) + 5c82: 97ba add a5,a5,a4 + 5c84: 96be add a3,a3,a5 + 5c86: 00e7b733 sltu a4,a5,a4 + 5c8a: fed52e23 sw a3,-4(a0) + 5c8e: 00f6b7b3 sltu a5,a3,a5 + 5c92: 971a add a4,a4,t1 + 5c94: 00e786b3 add a3,a5,a4 + 5c98: fd1e68e3 bltu t3,a7,5c68 + 5c9c: 18fd addi a7,a7,-1 + 5c9e: 0811 addi a6,a6,4 + 5ca0: fa089fe3 bnez a7,5c5e + 5ca4: 02040413 addi s0,s0,32 + 5ca8: 4685 li a3,1 + 5caa: 4198 lw a4,0(a1) + 5cac: 421c lw a5,0(a2) + 5cae: 0611 addi a2,a2,4 + 5cb0: fff74713 not a4,a4 + 5cb4: 97ba add a5,a5,a4 + 5cb6: 96be add a3,a3,a5 + 5cb8: 00e7b733 sltu a4,a5,a4 + 5cbc: c194 sw a3,0(a1) + 5cbe: 00f6b7b3 sltu a5,a3,a5 + 5cc2: 00e786b3 add a3,a5,a4 + 5cc6: 0591 addi a1,a1,4 + 5cc8: fe8611e3 bne a2,s0,5caa + 5ccc: 006c addi a1,sp,12 + 5cce: 852e mv a0,a1 + 5cd0: d24ff0ef jal ra,51f4 + 5cd4: 4621 li a2,8 + 5cd6: 006c addi a1,sp,12 + 5cd8: 8526 mv a0,s1 + 5cda: b81fd0ef jal ra,385a + 5cde: 0068 addi a0,sp,12 + 5ce0: 06400593 li a1,100 + 5ce4: 9d9ff0ef jal ra,56bc + 5ce8: 6165 addi sp,sp,112 + 5cea: d2afa06f j 214 <__riscv_restore_0> + +00005cee : + 5cee: d02fa2ef jal t0,1f0 <__riscv_save_0> + 5cf2: 1101 addi sp,sp,-32 + 5cf4: 85aa mv a1,a0 + 5cf6: 850a mv a0,sp + 5cf8: 9d9ff0ef jal ra,56d0 + 5cfc: 8000 lbu s0,0(sp) + 5cfe: 850a mv a0,sp + 5d00: 02000593 li a1,32 + 5d04: 9b9ff0ef jal ra,56bc + 5d08: 8805 andi s0,s0,1 + 5d0a: 8522 mv a0,s0 + 5d0c: 6105 addi sp,sp,32 + 5d0e: d06fa06f j 214 <__riscv_restore_0> + +00005d12 : + 5d12: cc4fa2ef jal t0,1d6 <__riscv_save_4> + 5d16: 02850913 addi s2,a0,40 + 5d1a: 842a mv s0,a0 + 5d1c: 4605 li a2,1 + 5d1e: 854a mv a0,s2 + 5d20: 8a2e mv s4,a1 + 5d22: 05040993 addi s3,s0,80 + 5d26: dd9fd0ef jal ra,3afe + 5d2a: 854e mv a0,s3 + 5d2c: 07840493 addi s1,s0,120 + 5d30: bc5fd0ef jal ra,38f4 + 5d34: 85ca mv a1,s2 + 5d36: 8526 mv a0,s1 + 5d38: dadfe0ef jal ra,4ae4 + 5d3c: 6635 lui a2,0xd + 5d3e: 27060613 addi a2,a2,624 # d270 + 5d42: 85a6 mv a1,s1 + 5d44: 8522 mv a0,s0 + 5d46: b02fe0ef jal ra,4048 + 5d4a: 864e mv a2,s3 + 5d4c: 85a6 mv a1,s1 + 5d4e: 8526 mv a0,s1 + 5d50: c1bfd0ef jal ra,396a + 5d54: 864e mv a2,s3 + 5d56: 85a2 mv a1,s0 + 5d58: 8522 mv a0,s0 + 5d5a: bebfd0ef jal ra,3944 + 5d5e: 85a6 mv a1,s1 + 5d60: 8522 mv a0,s0 + 5d62: 8622 mv a2,s0 + 5d64: ae4fe0ef jal ra,4048 + 5d68: 85a2 mv a1,s0 + 5d6a: 8522 mv a0,s0 + 5d6c: abbff0ef jal ra,5826 + 5d70: c915 beqz a0,5da4 + 5d72: 8622 mv a2,s0 + 5d74: 85a6 mv a1,s1 + 5d76: 8522 mv a0,s0 + 5d78: ad0fe0ef jal ra,4048 + 5d7c: 8522 mv a0,s0 + 5d7e: f71ff0ef jal ra,5cee + 5d82: 01fa4783 lbu a5,31(s4) + 5d86: 839d srli a5,a5,0x7 + 5d88: 00f51663 bne a0,a5,5d94 + 5d8c: 85a2 mv a1,s0 + 5d8e: 8522 mv a0,s0 + 5d90: b97fd0ef jal ra,3926 + 5d94: 8526 mv a0,s1 + 5d96: 864a mv a2,s2 + 5d98: 85a2 mv a1,s0 + 5d9a: aaefe0ef jal ra,4048 + 5d9e: 4501 li a0,0 + 5da0: c6afa06f j 20a <__riscv_restore_4> + 5da4: 557d li a0,-1 + 5da6: bfed j 5da0 + +00005da8 : + 5da8: c48fa2ef jal t0,1f0 <__riscv_save_0> + 5dac: 7119 addi sp,sp,-128 + 5dae: 842a mv s0,a0 + 5db0: 84ae mv s1,a1 + 5db2: 0028 addi a0,sp,8 + 5db4: 05058593 addi a1,a1,80 + 5db8: c57ff0ef jal ra,5a0e + 5dbc: 0030 addi a2,sp,8 + 5dbe: 85a6 mv a1,s1 + 5dc0: 1808 addi a0,sp,48 + 5dc2: a86fe0ef jal ra,4048 + 5dc6: 0030 addi a2,sp,8 + 5dc8: 02848593 addi a1,s1,40 + 5dcc: 08a8 addi a0,sp,88 + 5dce: a7afe0ef jal ra,4048 + 5dd2: 08ac addi a1,sp,88 + 5dd4: 8522 mv a0,s0 + 5dd6: 8fbff0ef jal ra,56d0 + 5dda: 1808 addi a0,sp,48 + 5ddc: f13ff0ef jal ra,5cee + 5de0: 67a1 lui a5,0x8 + 5de2: f8078793 addi a5,a5,-128 # 7f80 + 5de6: 051e slli a0,a0,0x7 + 5de8: 8d7d and a0,a0,a5 + 5dea: 3c7c lbu a5,31(s0) + 5dec: 02800593 li a1,40 + 5df0: 8d3d xor a0,a0,a5 + 5df2: bc68 sb a0,31(s0) + 5df4: 0028 addi a0,sp,8 + 5df6: 8c7ff0ef jal ra,56bc + 5dfa: 1808 addi a0,sp,48 + 5dfc: 02800593 li a1,40 + 5e00: 8bdff0ef jal ra,56bc + 5e04: 08a8 addi a0,sp,88 + 5e06: 02800593 li a1,40 + 5e0a: 8b3ff0ef jal ra,56bc + 5e0e: 6109 addi sp,sp,128 + 5e10: c04fa06f j 214 <__riscv_restore_0> + +00005e14 : + 5e14: 4781 li a5,0 + 5e16: 02000713 li a4,32 + 5e1a: 00f586b3 add a3,a1,a5 + 5e1e: 2290 lbu a2,0(a3) + 5e20: 00f506b3 add a3,a0,a5 + 5e24: 0785 addi a5,a5,1 + 5e26: a290 sb a2,0(a3) + 5e28: fee799e3 bne a5,a4,5e1a + 5e2c: 211c lbu a5,0(a0) + 5e2e: 9be1 andi a5,a5,-8 + 5e30: a11c sb a5,0(a0) + 5e32: 3d7c lbu a5,31(a0) + 5e34: 07f7f793 andi a5,a5,127 + 5e38: 0407e793 ori a5,a5,64 + 5e3c: bd7c sb a5,31(a0) + 5e3e: 8082 ret + +00005e40 : + 5e40: bb0fa2ef jal t0,1f0 <__riscv_save_0> + 5e44: 7179 addi sp,sp,-48 + 5e46: 842a mv s0,a0 + 5e48: 0808 addi a0,sp,16 + 5e4a: c632 sw a2,12(sp) + 5e4c: fc9ff0ef jal ra,5e14 + 5e50: 4632 lw a2,12(sp) + 5e52: 0ff00693 li a3,255 + 5e56: 080c addi a1,sp,16 + 5e58: 8522 mv a0,s0 + 5e5a: befff0ef jal ra,5a48 + 5e5e: 0808 addi a0,sp,16 + 5e60: 02000593 li a1,32 + 5e64: 859ff0ef jal ra,56bc + 5e68: 6145 addi sp,sp,48 + 5e6a: baafa06f j 214 <__riscv_restore_0> + +00005e6e : + 5e6e: b82fa2ef jal t0,1f0 <__riscv_save_0> + 5e72: 7139 addi sp,sp,-64 + 5e74: 842a mv s0,a0 + 5e76: 4641 li a2,16 + 5e78: 850a mv a0,sp + 5e7a: 9b5fd0ef jal ra,382e + 5e7e: 858a mv a1,sp + 5e80: 8522 mv a0,s0 + 5e82: d51ff0ef jal ra,5bd2 + 5e86: 850a mv a0,sp + 5e88: 04000593 li a1,64 + 5e8c: 831ff0ef jal ra,56bc + 5e90: 6121 addi sp,sp,64 + 5e92: b82fa06f j 214 <__riscv_restore_0> + +00005e96 : + 5e96: b5afa2ef jal t0,1f0 <__riscv_save_0> + 5e9a: 7175 addi sp,sp,-144 + 5e9c: 842a mv s0,a0 + 5e9e: 84b2 mv s1,a2 + 5ea0: 0808 addi a0,sp,16 + 5ea2: 4621 li a2,8 + 5ea4: c636 sw a3,12(sp) + 5ea6: 989fd0ef jal ra,382e + 5eaa: 85a6 mv a1,s1 + 5eac: 1808 addi a0,sp,48 + 5eae: 4621 li a2,8 + 5eb0: 97ffd0ef jal ra,382e + 5eb4: 46b2 lw a3,12(sp) + 5eb6: 0888 addi a0,sp,80 + 5eb8: 4621 li a2,8 + 5eba: 85b6 mv a1,a3 + 5ebc: 973fd0ef jal ra,382e + 5ec0: 1810 addi a2,sp,48 + 5ec2: 080c addi a1,sp,16 + 5ec4: 0888 addi a0,sp,80 + 5ec6: d882 sw zero,112(sp) + 5ec8: da82 sw zero,116(sp) + 5eca: dc82 sw zero,120(sp) + 5ecc: de82 sw zero,124(sp) + 5ece: c102 sw zero,128(sp) + 5ed0: c302 sw zero,132(sp) + 5ed2: c502 sw zero,136(sp) + 5ed4: c702 sw zero,140(sp) + 5ed6: a9eff0ef jal ra,5174 + 5eda: 088c addi a1,sp,80 + 5edc: 8522 mv a0,s0 + 5ede: cf5ff0ef jal ra,5bd2 + 5ee2: 0888 addi a0,sp,80 + 5ee4: 04000593 li a1,64 + 5ee8: fd4ff0ef jal ra,56bc + 5eec: 0808 addi a0,sp,16 + 5eee: 02000593 li a1,32 + 5ef2: fcaff0ef jal ra,56bc + 5ef6: 1808 addi a0,sp,48 + 5ef8: 02000593 li a1,32 + 5efc: fc0ff0ef jal ra,56bc + 5f00: 6149 addi sp,sp,144 + 5f02: b12fa06f j 214 <__riscv_restore_0> + +00005f06 : + 5f06: ad0fa2ef jal t0,1d6 <__riscv_save_4> + 5f0a: 7165 addi sp,sp,-400 + 5f0c: 66b5 lui a3,0xd + 5f0e: 6635 lui a2,0xd + 5f10: 2e068693 addi a3,a3,736 # d2e0 + 5f14: 2c060613 addi a2,a2,704 # d2c0 + 5f18: 842a mv s0,a0 + 5f1a: 0028 addi a0,sp,8 + 5f1c: f7bff0ef jal ra,5e96 + 5f20: 18a8 addi a0,sp,120 + 5f22: 9d3fd0ef jal ra,38f4 + 5f26: 1108 addi a0,sp,160 + 5f28: 9cdfd0ef jal ra,38f4 + 5f2c: 01a8 addi a0,sp,200 + 5f2e: 9b7fd0ef jal ra,38e4 + 5f32: 8522 mv a0,s0 + 5f34: b22ff0ef jal ra,5256 + 5f38: 69b5 lui s3,0xd + 5f3a: 487d li a6,31 + 5f3c: 003c addi a5,sp,8 + 5f3e: af098713 addi a4,s3,-1296 # caf0 + 5f42: 0894 addi a3,sp,80 + 5f44: 1030 addi a2,sp,40 + 5f46: 18ac addi a1,sp,120 + 5f48: 8522 mv a0,s0 + 5f4a: e82ff0ef jal ra,55cc + 5f4e: 6931 lui s2,0xc + 5f50: 09f00813 li a6,159 + 5f54: 003c addi a5,sp,8 + 5f56: 73090713 addi a4,s2,1840 # c730 + 5f5a: 0894 addi a3,sp,80 + 5f5c: 1030 addi a2,sp,40 + 5f5e: 18ac addi a1,sp,120 + 5f60: 8522 mv a0,s0 + 5f62: e6aff0ef jal ra,55cc + 5f66: 44f9 li s1,30 + 5f68: 5a7d li s4,-1 + 5f6a: 1990 addi a2,sp,240 + 5f6c: 85a2 mv a1,s0 + 5f6e: 8522 mv a0,s0 + 5f70: cc6ff0ef jal ra,5436 + 5f74: 8826 mv a6,s1 + 5f76: 003c addi a5,sp,8 + 5f78: af098713 addi a4,s3,-1296 + 5f7c: 0894 addi a3,sp,80 + 5f7e: 1030 addi a2,sp,40 + 5f80: 18ac addi a1,sp,120 + 5f82: 8522 mv a0,s0 + 5f84: e48ff0ef jal ra,55cc + 5f88: 08048813 addi a6,s1,128 + 5f8c: 003c addi a5,sp,8 + 5f8e: 73090713 addi a4,s2,1840 + 5f92: 0894 addi a3,sp,80 + 5f94: 1030 addi a2,sp,40 + 5f96: 18ac addi a1,sp,120 + 5f98: 8522 mv a0,s0 + 5f9a: 14fd addi s1,s1,-1 + 5f9c: e30ff0ef jal ra,55cc + 5fa0: fd4495e3 bne s1,s4,5f6a + 5fa4: 1028 addi a0,sp,40 + 5fa6: 02800593 li a1,40 + 5faa: f12ff0ef jal ra,56bc + 5fae: 1988 addi a0,sp,240 + 5fb0: 0a000593 li a1,160 + 5fb4: f08ff0ef jal ra,56bc + 5fb8: 0888 addi a0,sp,80 + 5fba: 02800593 li a1,40 + 5fbe: efeff0ef jal ra,56bc + 5fc2: 18a8 addi a0,sp,120 + 5fc4: 07800593 li a1,120 + 5fc8: ef4ff0ef jal ra,56bc + 5fcc: 0028 addi a0,sp,8 + 5fce: 02000593 li a1,32 + 5fd2: eeaff0ef jal ra,56bc + 5fd6: 6159 addi sp,sp,400 + 5fd8: a32fa06f j 20a <__riscv_restore_4> + +00005fdc : + 5fdc: 9fafa2ef jal t0,1d6 <__riscv_save_4> + 5fe0: be010113 addi sp,sp,-1056 + 5fe4: 02050a13 addi s4,a0,32 + 5fe8: 84ae mv s1,a1 + 5fea: 842a mv s0,a0 + 5fec: 85d2 mv a1,s4 + 5fee: 1588 addi a0,sp,736 + 5ff0: 8ab2 mv s5,a2 + 5ff2: 4621 li a2,8 + 5ff4: 83bfd0ef jal ra,382e + 5ff8: 85a6 mv a1,s1 + 5ffa: 1088 addi a0,sp,96 + 5ffc: d17ff0ef jal ra,5d12 + 6000: c511 beqz a0,600c + 6002: 557d li a0,-1 + 6004: 42010113 addi sp,sp,1056 + 6008: a02fa06f j 20a <__riscv_restore_4> + 600c: 85a2 mv a1,s0 + 600e: 0208 addi a0,sp,256 + 6010: d03ff0ef jal ra,5d12 + 6014: f57d bnez a0,6002 + 6016: 1588 addi a0,sp,736 + 6018: 9a6ff0ef jal ra,51be + 601c: f17d bnez a0,6002 + 601e: 0490 addi a2,sp,576 + 6020: 108c addi a1,sp,96 + 6022: 1308 addi a0,sp,416 + 6024: c12ff0ef jal ra,5436 + 6028: 108c addi a1,sp,96 + 602a: 1588 addi a0,sp,736 + 602c: a50ff0ef jal ra,527c + 6030: 1590 addi a2,sp,736 + 6032: 130c addi a1,sp,416 + 6034: 0488 addi a0,sp,576 + 6036: a88ff0ef jal ra,52be + 603a: 048c addi a1,sp,576 + 603c: 0708 addi a0,sp,896 + 603e: a3eff0ef jal ra,527c + 6042: 85d6 mv a1,s5 + 6044: 0028 addi a0,sp,8 + 6046: c9aff0ef jal ra,54e0 + 604a: 85d2 mv a1,s4 + 604c: 0068 addi a0,sp,12 + 604e: c92ff0ef jal ra,54e0 + 6052: 879c lbu a5,15(sp) + 6054: 00b14903 lbu s2,11(sp) + 6058: 00f97363 bgeu s2,a5,605e + 605c: 893e mv s2,a5 + 605e: 1088 addi a0,sp,96 + 6060: 69b5 lui s3,0xd + 6062: 0ff97913 andi s2,s2,255 + 6066: 9f0ff0ef jal ra,5256 + 606a: 4b09 li s6,2 + 606c: eb098993 addi s3,s3,-336 # ceb0 + 6070: 108c addi a1,sp,96 + 6072: 852e mv a0,a1 + 6074: 1310 addi a2,sp,416 + 6076: bc0ff0ef jal ra,5436 + 607a: 86d6 mv a3,s5 + 607c: 864a mv a2,s2 + 607e: 458d li a1,3 + 6080: 0028 addi a0,sp,8 + 6082: c86ff0ef jal ra,5508 + 6086: 842a mv s0,a0 + 6088: 86d2 mv a3,s4 + 608a: 864a mv a2,s2 + 608c: 4595 li a1,5 + 608e: 0068 addi a0,sp,12 + 6090: c78ff0ef jal ra,5508 + 6094: 84aa mv s1,a0 + 6096: 08805263 blez s0,611a + 609a: 8405 srai s0,s0,0x1 + 609c: 0a000613 li a2,160 + 60a0: 02c40633 mul a2,s0,a2 + 60a4: 159c addi a5,sp,736 + 60a6: 963e add a2,a2,a5 + 60a8: 108c addi a1,sp,96 + 60aa: 852e mv a0,a1 + 60ac: a12ff0ef jal ra,52be + 60b0: 0a905963 blez s1,6162 + 60b4: 8485 srai s1,s1,0x1 + 60b6: 07800613 li a2,120 + 60ba: 02c48633 mul a2,s1,a2 + 60be: 1838 addi a4,sp,56 + 60c0: 0814 addi a3,sp,16 + 60c2: 964e add a2,a2,s3 + 60c4: 108c addi a1,sp,96 + 60c6: 852e mv a0,a1 + 60c8: ab8ff0ef jal ra,5380 + 60cc: 197d addi s2,s2,-1 + 60ce: 57fd li a5,-1 + 60d0: faf910e3 bne s2,a5,6070 + 60d4: 020c addi a1,sp,256 + 60d6: 0488 addi a0,sp,576 + 60d8: 9a4ff0ef jal ra,527c + 60dc: 108c addi a1,sp,96 + 60de: 0490 addi a2,sp,576 + 60e0: 852e mv a0,a1 + 60e2: 9dcff0ef jal ra,52be + 60e6: 108c addi a1,sp,96 + 60e8: 0210 addi a2,sp,256 + 60ea: 852e mv a0,a1 + 60ec: b4aff0ef jal ra,5436 + 60f0: 108c addi a1,sp,96 + 60f2: 0210 addi a2,sp,256 + 60f4: 852e mv a0,a1 + 60f6: b40ff0ef jal ra,5436 + 60fa: 108c addi a1,sp,96 + 60fc: 0210 addi a2,sp,256 + 60fe: 852e mv a0,a1 + 6100: b36ff0ef jal ra,5436 + 6104: 108c addi a1,sp,96 + 6106: 1308 addi a0,sp,416 + 6108: ca1ff0ef jal ra,5da8 + 610c: 65b5 lui a1,0xd + 610e: 34c58593 addi a1,a1,844 # d34c + 6112: 1308 addi a0,sp,416 + 6114: d94ff0ef jal ra,56a8 + 6118: b5f5 j 6004 + 611a: d859 beqz s0,60b0 + 611c: 03644433 div s0,s0,s6 + 6120: f6000593 li a1,-160 + 6124: 159c addi a5,sp,736 + 6126: 14a8 addi a0,sp,616 + 6128: 02b40433 mul s0,s0,a1 + 612c: 008785b3 add a1,a5,s0 + 6130: fdcfd0ef jal ra,390c + 6134: 159c addi a5,sp,736 + 6136: 02840593 addi a1,s0,40 + 613a: 95be add a1,a1,a5 + 613c: 0488 addi a0,sp,576 + 613e: fcefd0ef jal ra,390c + 6142: 159c addi a5,sp,736 + 6144: 05040593 addi a1,s0,80 + 6148: 95be add a1,a1,a5 + 614a: 0d08 addi a0,sp,656 + 614c: fc0fd0ef jal ra,390c + 6150: 159c addi a5,sp,736 + 6152: 07840593 addi a1,s0,120 + 6156: 95be add a1,a1,a5 + 6158: 1d28 addi a0,sp,696 + 615a: fccfd0ef jal ra,3926 + 615e: 0490 addi a2,sp,576 + 6160: b7a1 j 60a8 + 6162: d4ad beqz s1,60cc + 6164: 0364c4b3 div s1,s1,s6 + 6168: f8800793 li a5,-120 + 616c: 14a8 addi a0,sp,616 + 616e: 02f484b3 mul s1,s1,a5 + 6172: 94ce add s1,s1,s3 + 6174: 85a6 mv a1,s1 + 6176: f96fd0ef jal ra,390c + 617a: 02848593 addi a1,s1,40 + 617e: 0488 addi a0,sp,576 + 6180: f8cfd0ef jal ra,390c + 6184: 05048593 addi a1,s1,80 + 6188: 0d08 addi a0,sp,656 + 618a: f9cfd0ef jal ra,3926 + 618e: 1838 addi a4,sp,56 + 6190: 0814 addi a3,sp,16 + 6192: 0490 addi a2,sp,576 + 6194: bf05 j 60c4 + +00006196 : + 6196: 85afa2ef jal t0,1f0 <__riscv_save_0> + 619a: 7135 addi sp,sp,-160 + 619c: 842a mv s0,a0 + 619e: 850a mv a0,sp + 61a0: d67ff0ef jal ra,5f06 + 61a4: 858a mv a1,sp + 61a6: 8522 mv a0,s0 + 61a8: c01ff0ef jal ra,5da8 + 61ac: 850a mv a0,sp + 61ae: 0a000593 li a1,160 + 61b2: d0aff0ef jal ra,56bc + 61b6: 610d addi sp,sp,160 + 61b8: 85cfa06f j 214 <__riscv_restore_0> + +000061bc : + 61bc: 834fa2ef jal t0,1f0 <__riscv_save_0> + 61c0: 715d addi sp,sp,-80 + 61c2: 84aa mv s1,a0 + 61c4: 4605 li a2,1 + 61c6: 1028 addi a0,sp,40 + 61c8: 937fd0ef jal ra,3afe + 61cc: 6435 lui s0,0xd + 61ce: 1030 addi a2,sp,40 + 61d0: 29840593 addi a1,s0,664 # d298 + 61d4: 850a mv a0,sp + 61d6: f6efd0ef jal ra,3944 + 61da: 1030 addi a2,sp,40 + 61dc: 8532 mv a0,a2 + 61de: 29840593 addi a1,s0,664 + 61e2: f88fd0ef jal ra,396a + 61e6: 102c addi a1,sp,40 + 61e8: 852e mv a0,a1 + 61ea: 825ff0ef jal ra,5a0e + 61ee: 1030 addi a2,sp,40 + 61f0: 858a mv a1,sp + 61f2: 850a mv a0,sp + 61f4: e55fd0ef jal ra,4048 + 61f8: 858a mv a1,sp + 61fa: 8526 mv a0,s1 + 61fc: cd4ff0ef jal ra,56d0 + 6200: 850a mv a0,sp + 6202: 02800593 li a1,40 + 6206: cb6ff0ef jal ra,56bc + 620a: 1028 addi a0,sp,40 + 620c: 02800593 li a1,40 + 6210: cacff0ef jal ra,56bc + 6214: 6161 addi sp,sp,80 + 6216: ffff906f j 214 <__riscv_restore_0> + +0000621a : + 621a: 211c lbu a5,0(a0) + 621c: 3118 lbu a4,1(a0) + 621e: 07e2 slli a5,a5,0x18 + 6220: 0742 slli a4,a4,0x10 + 6222: 8fd9 or a5,a5,a4 + 6224: 3138 lbu a4,3(a0) + 6226: 2128 lbu a0,2(a0) + 6228: 8fd9 or a5,a5,a4 + 622a: 0522 slli a0,a0,0x8 + 622c: 8d5d or a0,a0,a5 + 622e: 8082 ret + +00006230 : + 6230: 01855793 srli a5,a0,0x18 + 6234: a19c sb a5,0(a1) + 6236: 01055793 srli a5,a0,0x10 + 623a: b19c sb a5,1(a1) + 623c: 00855793 srli a5,a0,0x8 + 6240: a1bc sb a5,2(a1) + 6242: b1a8 sb a0,3(a1) + 6244: 8082 ret + +00006246 : + 6246: 4198 lw a4,0(a1) + 6248: 411c lw a5,0(a0) + 624a: 8fb9 xor a5,a5,a4 + 624c: c11c sw a5,0(a0) + 624e: 41d8 lw a4,4(a1) + 6250: 415c lw a5,4(a0) + 6252: 8fb9 xor a5,a5,a4 + 6254: c15c sw a5,4(a0) + 6256: 4598 lw a4,8(a1) + 6258: 451c lw a5,8(a0) + 625a: 8fb9 xor a5,a5,a4 + 625c: c51c sw a5,8(a0) + 625e: 45d8 lw a4,12(a1) + 6260: 455c lw a5,12(a0) + 6262: 8fb9 xor a5,a5,a4 + 6264: c55c sw a5,12(a0) + 6266: 8082 ret + +00006268 : + 6268: 00052803 lw a6,0(a0) + 626c: 4150 lw a2,4(a0) + 626e: ff000337 lui t1,0xff000 + 6272: 00ff08b7 lui a7,0xff0 + 6276: 4514 lw a3,8(a0) + 6278: 011675b3 and a1,a2,a7 + 627c: 00687733 and a4,a6,t1 + 6280: 455c lw a5,12(a0) + 6282: 8f4d or a4,a4,a1 + 6284: 65c1 lui a1,0x10 + 6286: f0058593 addi a1,a1,-256 # ff00 <_data_lma+0x1ca4> + 628a: 00b6fe33 and t3,a3,a1 + 628e: 01c76733 or a4,a4,t3 + 6292: 0ff7fe13 andi t3,a5,255 + 6296: 01c76733 or a4,a4,t3 + 629a: c118 sw a4,0(a0) + 629c: 0116fe33 and t3,a3,a7 + 62a0: 00667733 and a4,a2,t1 + 62a4: 01c76733 or a4,a4,t3 + 62a8: 00b7fe33 and t3,a5,a1 + 62ac: 01c76733 or a4,a4,t3 + 62b0: 0ff87e13 andi t3,a6,255 + 62b4: 01c76733 or a4,a4,t3 + 62b8: c158 sw a4,4(a0) + 62ba: 0117fe33 and t3,a5,a7 + 62be: 0066f733 and a4,a3,t1 + 62c2: 01c76733 or a4,a4,t3 + 62c6: 0067f7b3 and a5,a5,t1 + 62ca: 00b87e33 and t3,a6,a1 + 62ce: 01187833 and a6,a6,a7 + 62d2: 01c76733 or a4,a4,t3 + 62d6: 0107e7b3 or a5,a5,a6 + 62da: 0ff67e13 andi t3,a2,255 + 62de: 8e6d and a2,a2,a1 + 62e0: 8fd1 or a5,a5,a2 + 62e2: 0ff6f693 andi a3,a3,255 + 62e6: 01c76733 or a4,a4,t3 + 62ea: 8fd5 or a5,a5,a3 + 62ec: c518 sw a4,8(a0) + 62ee: c55c sw a5,12(a0) + 62f0: 8082 ret + +000062f2 : + 62f2: 01010737 lui a4,0x1010 + 62f6: 00755793 srli a5,a0,0x7 + 62fa: 10170713 addi a4,a4,257 # 1010101 <_data_lma+0x1001ea5> + 62fe: 8ff9 and a5,a5,a4 + 6300: 476d li a4,27 + 6302: 02e787b3 mul a5,a5,a4 + 6306: feff0737 lui a4,0xfeff0 + 630a: efe70713 addi a4,a4,-258 # fefefefe <_eusrstack+0xdefe7efe> + 630e: 0506 slli a0,a0,0x1 + 6310: 8d79 and a0,a0,a4 + 6312: 8d3d xor a0,a0,a5 + 6314: 8082 ret + +00006316 : + 6316: edbf92ef jal t0,1f0 <__riscv_save_0> + 631a: 842a mv s0,a0 + 631c: fd7ff0ef jal ra,62f2 + 6320: 01045713 srli a4,s0,0x10 + 6324: 01041793 slli a5,s0,0x10 + 6328: 01841693 slli a3,s0,0x18 + 632c: 8fd9 or a5,a5,a4 + 632e: 00845713 srli a4,s0,0x8 + 6332: 8f55 or a4,a4,a3 + 6334: 8fb9 xor a5,a5,a4 + 6336: 8c29 xor s0,s0,a0 + 6338: 8fa9 xor a5,a5,a0 + 633a: 00841513 slli a0,s0,0x8 + 633e: 8061 srli s0,s0,0x18 + 6340: 8d41 or a0,a0,s0 + 6342: 8d3d xor a0,a0,a5 + 6344: ed1f906f j 214 <__riscv_restore_0> + +00006348 : + 6348: 4114 lw a3,0(a0) + 634a: 455c lw a5,12(a0) + 634c: ff000337 lui t1,0xff000 + 6350: 00ff08b7 lui a7,0xff0 + 6354: 00852803 lw a6,8(a0) + 6358: 0117f5b3 and a1,a5,a7 + 635c: 0066f733 and a4,a3,t1 + 6360: 4150 lw a2,4(a0) + 6362: 8f4d or a4,a4,a1 + 6364: 65c1 lui a1,0x10 + 6366: f0058593 addi a1,a1,-256 # ff00 <_data_lma+0x1ca4> + 636a: 00b87e33 and t3,a6,a1 + 636e: 01c76733 or a4,a4,t3 + 6372: 0ff67e13 andi t3,a2,255 + 6376: 01c76733 or a4,a4,t3 + 637a: c118 sw a4,0(a0) + 637c: 0116fe33 and t3,a3,a7 + 6380: 00667733 and a4,a2,t1 + 6384: 01c76733 or a4,a4,t3 + 6388: 00b7fe33 and t3,a5,a1 + 638c: 01c76733 or a4,a4,t3 + 6390: 0ff87e13 andi t3,a6,255 + 6394: 01c76733 or a4,a4,t3 + 6398: c158 sw a4,4(a0) + 639a: 01167e33 and t3,a2,a7 + 639e: 00687733 and a4,a6,t1 + 63a2: 01c76733 or a4,a4,t3 + 63a6: 00b6fe33 and t3,a3,a1 + 63aa: 01c76733 or a4,a4,t3 + 63ae: 01187833 and a6,a6,a7 + 63b2: 0ff7fe13 andi t3,a5,255 + 63b6: 0067f7b3 and a5,a5,t1 + 63ba: 0107e7b3 or a5,a5,a6 + 63be: 8e6d and a2,a2,a1 + 63c0: 8fd1 or a5,a5,a2 + 63c2: 0ff6f693 andi a3,a3,255 + 63c6: 01c76733 or a4,a4,t3 + 63ca: 8fd5 or a5,a5,a3 + 63cc: c518 sw a4,8(a0) + 63ce: c55c sw a5,12(a0) + 63d0: 8082 ret + +000063d2 : + 63d2: e1ff92ef jal t0,1f0 <__riscv_save_0> + 63d6: 842a mv s0,a0 + 63d8: f1bff0ef jal ra,62f2 + 63dc: 892a mv s2,a0 + 63de: f15ff0ef jal ra,62f2 + 63e2: 84aa mv s1,a0 + 63e4: f0fff0ef jal ra,62f2 + 63e8: 8d21 xor a0,a0,s0 + 63ea: 00a4c7b3 xor a5,s1,a0 + 63ee: 01851693 slli a3,a0,0x18 + 63f2: 01244433 xor s0,s0,s2 + 63f6: 00855713 srli a4,a0,0x8 + 63fa: 00a94933 xor s2,s2,a0 + 63fe: 00891513 slli a0,s2,0x8 + 6402: 8c3d xor s0,s0,a5 + 6404: 8f55 or a4,a4,a3 + 6406: 01895913 srli s2,s2,0x18 + 640a: 01256933 or s2,a0,s2 + 640e: 8c39 xor s0,s0,a4 + 6410: 01079513 slli a0,a5,0x10 + 6414: 83c1 srli a5,a5,0x10 + 6416: 01244433 xor s0,s0,s2 + 641a: 8d5d or a0,a0,a5 + 641c: 8d21 xor a0,a0,s0 + 641e: df7f906f j 214 <__riscv_restore_0> + +00006422 : + 6422: 01055f93 srli t6,a0,0x10 + 6426: 00855f13 srli t5,a0,0x8 + 642a: 01855393 srli t2,a0,0x18 + 642e: 4e81 li t4,0 + 6430: 4301 li t1,0 + 6432: 4e01 li t3,0 + 6434: 4601 li a2,0 + 6436: 4801 li a6,0 + 6438: 0fffff93 andi t6,t6,255 + 643c: 0fff7f13 andi t5,t5,255 + 6440: 0ff57513 andi a0,a0,255 + 6444: 10000293 li t0,256 + 6448: 010587b3 add a5,a1,a6 + 644c: 0007c883 lbu a7,0(a5) + 6450: 0103c7b3 xor a5,t2,a6 + 6454: 0ff7f793 andi a5,a5,255 + 6458: fff7c693 not a3,a5 + 645c: 17fd addi a5,a5,-1 + 645e: 8efd and a3,a3,a5 + 6460: 06e2 slli a3,a3,0x18 + 6462: 86fd srai a3,a3,0x1f + 6464: fff6c793 not a5,a3 + 6468: 8e7d and a2,a2,a5 + 646a: 010fc7b3 xor a5,t6,a6 + 646e: 0ff7f793 andi a5,a5,255 + 6472: fff7c713 not a4,a5 + 6476: 17fd addi a5,a5,-1 + 6478: 8f7d and a4,a4,a5 + 647a: 0ff8f893 andi a7,a7,255 + 647e: 0762 slli a4,a4,0x18 + 6480: 00d8f6b3 and a3,a7,a3 + 6484: 877d srai a4,a4,0x1f + 6486: 8e55 or a2,a2,a3 + 6488: fff74693 not a3,a4 + 648c: 01c6fe33 and t3,a3,t3 + 6490: 00e8f733 and a4,a7,a4 + 6494: 00ee6e33 or t3,t3,a4 + 6498: 010f4733 xor a4,t5,a6 + 649c: 0ff77713 andi a4,a4,255 + 64a0: fff74793 not a5,a4 + 64a4: 177d addi a4,a4,-1 + 64a6: 8ff9 and a5,a5,a4 + 64a8: 07e2 slli a5,a5,0x18 + 64aa: 87fd srai a5,a5,0x1f + 64ac: fff7c713 not a4,a5 + 64b0: 00677333 and t1,a4,t1 + 64b4: 01054733 xor a4,a0,a6 + 64b8: 00f8f7b3 and a5,a7,a5 + 64bc: 0ff77713 andi a4,a4,255 + 64c0: 00f36333 or t1,t1,a5 + 64c4: fff74793 not a5,a4 + 64c8: 177d addi a4,a4,-1 + 64ca: 8ff9 and a5,a5,a4 + 64cc: 07e2 slli a5,a5,0x18 + 64ce: 87fd srai a5,a5,0x1f + 64d0: fff7c693 not a3,a5 + 64d4: 01d6f6b3 and a3,a3,t4 + 64d8: 00f8f8b3 and a7,a7,a5 + 64dc: 0805 addi a6,a6,1 + 64de: 0116eeb3 or t4,a3,a7 + 64e2: f65813e3 bne a6,t0,6448 + 64e6: 01861693 slli a3,a2,0x18 + 64ea: 010e1713 slli a4,t3,0x10 + 64ee: 8ed9 or a3,a3,a4 + 64f0: 01d6e6b3 or a3,a3,t4 + 64f4: 00831513 slli a0,t1,0x8 + 64f8: 8d55 or a0,a0,a3 + 64fa: 8082 ret + +000064fc : + 64fc: cc5f92ef jal t0,1c0 <__riscv_save_12> + 6500: 4104 lw s1,0(a0) + 6502: 00265913 srli s2,a2,0x2 + 6506: 1141 addi sp,sp,-16 + 6508: 0485 addi s1,s1,1 + 650a: 842a mv s0,a0 + 650c: 8a32 mv s4,a2 + 650e: 048a slli s1,s1,0x2 + 6510: 00291a93 slli s5,s2,0x2 + 6514: 4981 li s3,0 + 6516: 033a9363 bne s5,s3,653c + 651a: 69b5 lui s3,0xd + 651c: 00440d93 addi s11,s0,4 + 6520: 8cca mv s9,s2 + 6522: 9456 add s0,s0,s5 + 6524: 4c01 li s8,0 + 6526: 4d05 li s10,1 + 6528: 6ab5 lui s5,0xd + 652a: 36c98993 addi s3,s3,876 # d36c + 652e: 4b6d li s6,27 + 6530: 4b91 li s7,4 + 6532: 029ce063 bltu s9,s1,6552 + 6536: 0141 addi sp,sp,16 + 6538: cc5f906f j 1fc <__riscv_restore_12> + 653c: 01358533 add a0,a1,s3 + 6540: c62e sw a1,12(sp) + 6542: cd9ff0ef jal ra,621a + 6546: 013407b3 add a5,s0,s3 + 654a: c3c8 sw a0,4(a5) + 654c: 0991 addi s3,s3,4 + 654e: 45b2 lw a1,12(sp) + 6550: b7d9 j 6516 + 6552: 4008 lw a0,0(s0) + 6554: 032c1a63 bne s8,s2,6588 + 6558: 0d05 addi s10,s10,1 + 655a: 00851793 slli a5,a0,0x8 + 655e: 8161 srli a0,a0,0x18 + 6560: 8d5d or a0,a0,a5 + 6562: 378a8593 addi a1,s5,888 # d378 + 6566: ebdff0ef jal ra,6422 + 656a: 01a987b3 add a5,s3,s10 + 656e: 239c lbu a5,0(a5) + 6570: 4c01 li s8,0 + 6572: 07e2 slli a5,a5,0x18 + 6574: 8d3d xor a0,a0,a5 + 6576: 000da783 lw a5,0(s11) + 657a: 0c85 addi s9,s9,1 + 657c: 0c05 addi s8,s8,1 + 657e: 8d3d xor a0,a0,a5 + 6580: c048 sw a0,4(s0) + 6582: 0d91 addi s11,s11,4 + 6584: 0411 addi s0,s0,4 + 6586: b775 j 6532 + 6588: fc0c09e3 beqz s8,655a + 658c: ff4b75e3 bgeu s6,s4,6576 + 6590: ff7c13e3 bne s8,s7,6576 + 6594: 378a8593 addi a1,s5,888 + 6598: e8bff0ef jal ra,6422 + 659c: bfe9 j 6576 + +0000659e : + 659e: c53f92ef jal t0,1f0 <__riscv_save_0> + 65a2: 842a mv s0,a0 + 65a4: 4108 lw a0,0(a0) + 65a6: 64b5 lui s1,0xd + 65a8: 37848593 addi a1,s1,888 # d378 + 65ac: e77ff0ef jal ra,6422 + 65b0: c008 sw a0,0(s0) + 65b2: 4048 lw a0,4(s0) + 65b4: 37848593 addi a1,s1,888 + 65b8: e6bff0ef jal ra,6422 + 65bc: c048 sw a0,4(s0) + 65be: 4408 lw a0,8(s0) + 65c0: 37848593 addi a1,s1,888 + 65c4: e5fff0ef jal ra,6422 + 65c8: c408 sw a0,8(s0) + 65ca: 4448 lw a0,12(s0) + 65cc: 37848593 addi a1,s1,888 + 65d0: e53ff0ef jal ra,6422 + 65d4: c448 sw a0,12(s0) + 65d6: c3ff906f j 214 <__riscv_restore_0> + +000065da : + 65da: bfdf92ef jal t0,1d6 <__riscv_save_4> + 65de: 411c lw a5,0(a0) + 65e0: 4729 li a4,10 + 65e2: 1141 addi sp,sp,-16 + 65e4: ffb7f693 andi a3,a5,-5 + 65e8: 892a mv s2,a0 + 65ea: 84ae mv s1,a1 + 65ec: 8432 mv s0,a2 + 65ee: 00e68763 beq a3,a4,65fc + 65f2: 4731 li a4,12 + 65f4: 00e78463 beq a5,a4,65fc + 65f8: 2c6030ef jal ra,98be + 65fc: 8526 mv a0,s1 + 65fe: c1dff0ef jal ra,621a + 6602: c02a sw a0,0(sp) + 6604: 00448513 addi a0,s1,4 + 6608: c13ff0ef jal ra,621a + 660c: c22a sw a0,4(sp) + 660e: 00848513 addi a0,s1,8 + 6612: c09ff0ef jal ra,621a + 6616: c42a sw a0,8(sp) + 6618: 00c48513 addi a0,s1,12 + 661c: bffff0ef jal ra,621a + 6620: c62a sw a0,12(sp) + 6622: 00490593 addi a1,s2,4 + 6626: 850a mv a0,sp + 6628: c1fff0ef jal ra,6246 + 662c: 01490493 addi s1,s2,20 + 6630: 4985 li s3,1 + 6632: 00092783 lw a5,0(s2) + 6636: 850a mv a0,sp + 6638: 04f9e163 bltu s3,a5,667a + 663c: f63ff0ef jal ra,659e + 6640: 850a mv a0,sp + 6642: c27ff0ef jal ra,6268 + 6646: 85a6 mv a1,s1 + 6648: 850a mv a0,sp + 664a: bfdff0ef jal ra,6246 + 664e: 4502 lw a0,0(sp) + 6650: 85a2 mv a1,s0 + 6652: bdfff0ef jal ra,6230 + 6656: 4512 lw a0,4(sp) + 6658: 00440593 addi a1,s0,4 + 665c: bd5ff0ef jal ra,6230 + 6660: 4522 lw a0,8(sp) + 6662: 00840593 addi a1,s0,8 + 6666: bcbff0ef jal ra,6230 + 666a: 4532 lw a0,12(sp) + 666c: 00c40593 addi a1,s0,12 + 6670: bc1ff0ef jal ra,6230 + 6674: 0141 addi sp,sp,16 + 6676: b95f906f j 20a <__riscv_restore_4> + 667a: f25ff0ef jal ra,659e + 667e: 850a mv a0,sp + 6680: be9ff0ef jal ra,6268 + 6684: 4502 lw a0,0(sp) + 6686: 0985 addi s3,s3,1 + 6688: c8fff0ef jal ra,6316 + 668c: c02a sw a0,0(sp) + 668e: 4512 lw a0,4(sp) + 6690: c87ff0ef jal ra,6316 + 6694: c22a sw a0,4(sp) + 6696: 4522 lw a0,8(sp) + 6698: c7fff0ef jal ra,6316 + 669c: c42a sw a0,8(sp) + 669e: 4532 lw a0,12(sp) + 66a0: c77ff0ef jal ra,6316 + 66a4: c62a sw a0,12(sp) + 66a6: 85a6 mv a1,s1 + 66a8: 850a mv a0,sp + 66aa: b9dff0ef jal ra,6246 + 66ae: 04c1 addi s1,s1,16 + 66b0: b749 j 6632 + +000066b2 : + 66b2: b3ff92ef jal t0,1f0 <__riscv_save_0> + 66b6: 842a mv s0,a0 + 66b8: 4108 lw a0,0(a0) + 66ba: 64b5 lui s1,0xd + 66bc: 47848593 addi a1,s1,1144 # d478 + 66c0: d63ff0ef jal ra,6422 + 66c4: c008 sw a0,0(s0) + 66c6: 4048 lw a0,4(s0) + 66c8: 47848593 addi a1,s1,1144 + 66cc: d57ff0ef jal ra,6422 + 66d0: c048 sw a0,4(s0) + 66d2: 4408 lw a0,8(s0) + 66d4: 47848593 addi a1,s1,1144 + 66d8: d4bff0ef jal ra,6422 + 66dc: c408 sw a0,8(s0) + 66de: 4448 lw a0,12(s0) + 66e0: 47848593 addi a1,s1,1144 + 66e4: d3fff0ef jal ra,6422 + 66e8: c448 sw a0,12(s0) + 66ea: b2bf906f j 214 <__riscv_restore_0> + +000066ee : + 66ee: ae9f92ef jal t0,1d6 <__riscv_save_4> + 66f2: 4100 lw s0,0(a0) + 66f4: 47a9 li a5,10 + 66f6: 1141 addi sp,sp,-16 + 66f8: ffb47713 andi a4,s0,-5 + 66fc: 89aa mv s3,a0 + 66fe: 892e mv s2,a1 + 6700: 84b2 mv s1,a2 + 6702: 00f70763 beq a4,a5,6710 + 6706: 47b1 li a5,12 + 6708: 00f40463 beq s0,a5,6710 + 670c: 1b2030ef jal ra,98be + 6710: 854a mv a0,s2 + 6712: b09ff0ef jal ra,621a + 6716: c02a sw a0,0(sp) + 6718: 00490513 addi a0,s2,4 + 671c: affff0ef jal ra,621a + 6720: c22a sw a0,4(sp) + 6722: 00890513 addi a0,s2,8 + 6726: af5ff0ef jal ra,621a + 672a: 0412 slli s0,s0,0x4 + 672c: c42a sw a0,8(sp) + 672e: 0411 addi s0,s0,4 + 6730: 00c90513 addi a0,s2,12 + 6734: ae7ff0ef jal ra,621a + 6738: 944e add s0,s0,s3 + 673a: c62a sw a0,12(sp) + 673c: 85a2 mv a1,s0 + 673e: 850a mv a0,sp + 6740: b07ff0ef jal ra,6246 + 6744: 0009a903 lw s2,0(s3) + 6748: ff040a13 addi s4,s0,-16 + 674c: fff90993 addi s3,s2,-1 + 6750: 04099663 bnez s3,679c + 6754: 55c1 li a1,-16 + 6756: 02b90933 mul s2,s2,a1 + 675a: 850a mv a0,sp + 675c: bedff0ef jal ra,6348 + 6760: 850a mv a0,sp + 6762: f51ff0ef jal ra,66b2 + 6766: 850a mv a0,sp + 6768: 944a add s0,s0,s2 + 676a: 85a2 mv a1,s0 + 676c: adbff0ef jal ra,6246 + 6770: 4502 lw a0,0(sp) + 6772: 85a6 mv a1,s1 + 6774: abdff0ef jal ra,6230 + 6778: 4512 lw a0,4(sp) + 677a: 00448593 addi a1,s1,4 + 677e: ab3ff0ef jal ra,6230 + 6782: 4522 lw a0,8(sp) + 6784: 00848593 addi a1,s1,8 + 6788: aa9ff0ef jal ra,6230 + 678c: 4532 lw a0,12(sp) + 678e: 00c48593 addi a1,s1,12 + 6792: a9fff0ef jal ra,6230 + 6796: 0141 addi sp,sp,16 + 6798: a73f906f j 20a <__riscv_restore_4> + 679c: 850a mv a0,sp + 679e: babff0ef jal ra,6348 + 67a2: 850a mv a0,sp + 67a4: f0fff0ef jal ra,66b2 + 67a8: 85d2 mv a1,s4 + 67aa: 850a mv a0,sp + 67ac: a9bff0ef jal ra,6246 + 67b0: 4502 lw a0,0(sp) + 67b2: 1a41 addi s4,s4,-16 + 67b4: 19fd addi s3,s3,-1 + 67b6: c1dff0ef jal ra,63d2 + 67ba: c02a sw a0,0(sp) + 67bc: 4512 lw a0,4(sp) + 67be: c15ff0ef jal ra,63d2 + 67c2: c22a sw a0,4(sp) + 67c4: 4522 lw a0,8(sp) + 67c6: c0dff0ef jal ra,63d2 + 67ca: c42a sw a0,8(sp) + 67cc: 4532 lw a0,12(sp) + 67ce: c05ff0ef jal ra,63d2 + 67d2: c62a sw a0,12(sp) + 67d4: bfb5 j 6750 + +000067d6 : + 67d6: a1bf92ef jal t0,1f0 <__riscv_save_0> + 67da: 842e mv s0,a1 + 67dc: 84b2 mv s1,a2 + 67de: 4581 li a1,0 + 67e0: 0f400613 li a2,244 + 67e4: a3df90ef jal ra,220 + 67e8: 4761 li a4,24 + 67ea: 87aa mv a5,a0 + 67ec: 02e48263 beq s1,a4,6810 + 67f0: 02000713 li a4,32 + 67f4: 02e48263 beq s1,a4,6818 + 67f8: 4741 li a4,16 + 67fa: 02e49463 bne s1,a4,6822 + 67fe: 4729 li a4,10 + 6800: c118 sw a4,0(a0) + 6802: 4641 li a2,16 + 6804: 85a2 mv a1,s0 + 6806: 853e mv a0,a5 + 6808: cf5ff0ef jal ra,64fc + 680c: a09f906f j 214 <__riscv_restore_0> + 6810: 4731 li a4,12 + 6812: c118 sw a4,0(a0) + 6814: 4661 li a2,24 + 6816: b7fd j 6804 + 6818: 4739 li a4,14 + 681a: c118 sw a4,0(a0) + 681c: 02000613 li a2,32 + 6820: b7d5 j 6804 + 6822: 09c030ef jal ra,98be + +00006826 : + 6826: 9cbf92ef jal t0,1f0 <__riscv_save_0> + 682a: 0f400613 li a2,244 + 682e: 4581 li a1,0 + 6830: 9f1f90ef jal ra,220 + 6834: 87aa mv a5,a0 + 6836: 239c lbu a5,0(a5) + 6838: 9ddf906f j 214 <__riscv_restore_0> + +0000683c : + 683c: 99bf92ef jal t0,1d6 <__riscv_save_4> + 6840: 00f6f413 andi s0,a3,15 + 6844: 7111 addi sp,sp,-256 + 6846: e81d bnez s0,687c + 6848: 8932 mv s2,a2 + 684a: 862e mv a2,a1 + 684c: 85aa mv a1,a0 + 684e: 0068 addi a0,sp,12 + 6850: 89ba mv s3,a4 + 6852: 84b6 mv s1,a3 + 6854: f83ff0ef jal ra,67d6 + 6858: 00946963 bltu s0,s1,686a + 685c: 0068 addi a0,sp,12 + 685e: fc9ff0ef jal ra,6826 + 6862: 4501 li a0,0 + 6864: 6111 addi sp,sp,256 + 6866: 9a5f906f j 20a <__riscv_restore_4> + 686a: 00898633 add a2,s3,s0 + 686e: 008905b3 add a1,s2,s0 + 6872: 0068 addi a0,sp,12 + 6874: d67ff0ef jal ra,65da + 6878: 0441 addi s0,s0,16 + 687a: bff9 j 6858 + 687c: 557d li a0,-1 + 687e: b7dd j 6864 + +00006880 : + 6880: 957f92ef jal t0,1d6 <__riscv_save_4> + 6884: 00f6f413 andi s0,a3,15 + 6888: 7111 addi sp,sp,-256 + 688a: e81d bnez s0,68c0 + 688c: 8932 mv s2,a2 + 688e: 862e mv a2,a1 + 6890: 85aa mv a1,a0 + 6892: 0068 addi a0,sp,12 + 6894: 89ba mv s3,a4 + 6896: 84b6 mv s1,a3 + 6898: f3fff0ef jal ra,67d6 + 689c: 00946963 bltu s0,s1,68ae + 68a0: 0068 addi a0,sp,12 + 68a2: f85ff0ef jal ra,6826 + 68a6: 4501 li a0,0 + 68a8: 6111 addi sp,sp,256 + 68aa: 961f906f j 20a <__riscv_restore_4> + 68ae: 00898633 add a2,s3,s0 + 68b2: 008905b3 add a1,s2,s0 + 68b6: 0068 addi a0,sp,12 + 68b8: e37ff0ef jal ra,66ee + 68bc: 0441 addi s0,s0,16 + 68be: bff9 j 689c + 68c0: 557d li a0,-1 + 68c2: b7dd j 68a8 + +000068c4 : + 68c4: 905f92ef jal t0,1c8 <__riscv_save_10> + 68c8: c519 beqz a0,68d6 + 68ca: 8aaa mv s5,a0 + 68cc: 4188 lw a0,0(a1) + 68ce: 8a2e mv s4,a1 + 68d0: 8932 mv s2,a2 + 68d2: 00c56463 bltu a0,a2,68da + 68d6: 7e9020ef jal ra,98be + 68da: 84b6 mv s1,a3 + 68dc: 843a mv s0,a4 + 68de: 8bbe mv s7,a5 + 68e0: 8c42 mv s8,a6 + 68e2: 8b46 mv s6,a7 + 68e4: e291 bnez a3,68e8 + 68e6: fb65 bnez a4,68d6 + 68e8: fe0b87e3 beqz s7,68d6 + 68ec: fe0b05e3 beqz s6,68d6 + 68f0: cd05 beqz a0,6928 + 68f2: c81d beqz s0,6928 + 68f4: 40a909b3 sub s3,s2,a0 + 68f8: 01347363 bgeu s0,s3,68fe + 68fc: 89a2 mv s3,s0 + 68fe: 864e mv a2,s3 + 6900: 85a6 mv a1,s1 + 6902: 9556 add a0,a0,s5 + 6904: 04e030ef jal ra,9952 + 6908: 000a2783 lw a5,0(s4) + 690c: 94ce add s1,s1,s3 + 690e: 41340433 sub s0,s0,s3 + 6912: 99be add s3,s3,a5 + 6914: 013a2023 sw s3,0(s4) + 6918: 01299863 bne s3,s2,6928 + 691c: 85d6 mv a1,s5 + 691e: 855a mv a0,s6 + 6920: e809 bnez s0,6932 + 6922: 9c02 jalr s8 + 6924: 000a2023 sw zero,0(s4) + 6928: 01247763 bgeu s0,s2,6936 + 692c: e01d bnez s0,6952 + 692e: 8d3f906f j 200 <__riscv_restore_10> + 6932: 9b82 jalr s7 + 6934: bfc5 j 6924 + 6936: 000a2783 lw a5,0(s4) + 693a: ffd1 bnez a5,68d6 + 693c: 85a6 mv a1,s1 + 693e: 855a mv a0,s6 + 6940: 01241763 bne s0,s2,694e + 6944: 9c02 jalr s8 + 6946: 94ca add s1,s1,s2 + 6948: 41240433 sub s0,s0,s2 + 694c: bff1 j 6928 + 694e: 9b82 jalr s7 + 6950: bfdd j 6946 + 6952: 000a2503 lw a0,0(s4) + 6956: 40a909b3 sub s3,s2,a0 + 695a: 01347363 bgeu s0,s3,6960 + 695e: 89a2 mv s3,s0 + 6960: 864e mv a2,s3 + 6962: 85a6 mv a1,s1 + 6964: 9556 add a0,a0,s5 + 6966: 7ed020ef jal ra,9952 + 696a: 000a2783 lw a5,0(s4) + 696e: 94ce add s1,s1,s3 + 6970: 41340433 sub s0,s0,s3 + 6974: 99be add s3,s3,a5 + 6976: 013a2023 sw s3,0(s4) + 697a: fb29e9e3 bltu s3,s2,692c + 697e: bfa1 j 68d6 + +00006980 : + 6980: 871f92ef jal t0,1f0 <__riscv_save_0> + 6984: 88c2 mv a7,a6 + 6986: 883e mv a6,a5 + 6988: f3dff0ef jal ra,68c4 + 698c: 889f906f j 214 <__riscv_restore_0> + +00006990 : + 6990: 839f92ef jal t0,1c8 <__riscv_save_10> + 6994: 8b2a mv s6,a0 + 6996: 89ae mv s3,a1 + 6998: 8a32 mv s4,a2 + 699a: 8bb6 mv s7,a3 + 699c: 893a mv s2,a4 + 699e: 8c3e mv s8,a5 + 69a0: 8cc2 mv s9,a6 + 69a2: 4a81 li s5,0 + 69a4: 00091463 bnez s2,69ac + 69a8: 859f906f j 200 <__riscv_restore_10> + 69ac: 0009a483 lw s1,0(s3) + 69b0: 409a0433 sub s0,s4,s1 + 69b4: 00897363 bgeu s2,s0,69ba + 69b8: 844a mv s0,s2 + 69ba: 000a9863 bnez s5,69ca + 69be: 8622 mv a2,s0 + 69c0: 85de mv a1,s7 + 69c2: 009b0533 add a0,s6,s1 + 69c6: 85bf90ef jal ra,220 + 69ca: e481 bnez s1,69d2 + 69cc: 008a1363 bne s4,s0,69d2 + 69d0: 4a85 li s5,1 + 69d2: 94a2 add s1,s1,s0 + 69d4: 01449a63 bne s1,s4,69e8 + 69d8: 85da mv a1,s6 + 69da: 8566 mv a0,s9 + 69dc: 9c02 jalr s8 + 69de: 0009a023 sw zero,0(s3) + 69e2: 40890933 sub s2,s2,s0 + 69e6: bf7d j 69a4 + 69e8: 0009a703 lw a4,0(s3) + 69ec: 9722 add a4,a4,s0 + 69ee: 00e9a023 sw a4,0(s3) + 69f2: bfc5 j 69e2 + +000069f4 : + 69f4: fe2f92ef jal t0,1d6 <__riscv_save_4> + 69f8: 1141 addi sp,sp,-16 + 69fa: 8b3a mv s6,a4 + 69fc: 87d4 sb a3,15(sp) + 69fe: 875c sb a5,14(sp) + 6a00: 4705 li a4,1 + 6a02: 8446 mv s0,a7 + 6a04: 54c2 lw s1,48(sp) + 6a06: 04e80063 beq a6,a4,6a46 + 6a0a: 8942 mv s2,a6 + 6a0c: 04080663 beqz a6,6a58 + 6a10: 4789 li a5,2 + 6a12: 89aa mv s3,a0 + 6a14: 8a2e mv s4,a1 + 6a16: 8ab2 mv s5,a2 + 6a18: 04f80363 beq a6,a5,6a5e + 6a1c: 8826 mv a6,s1 + 6a1e: 87c6 mv a5,a7 + 6a20: 00f10693 addi a3,sp,15 + 6a24: 4705 li a4,1 + 6a26: f5bff0ef jal ra,6980 + 6a2a: 8714 lbu a3,14(sp) + 6a2c: 8826 mv a6,s1 + 6a2e: 87a2 mv a5,s0 + 6a30: 05668763 beq a3,s6,6a7e + 6a34: ffe90713 addi a4,s2,-2 + 6a38: 86da mv a3,s6 + 6a3a: 8656 mv a2,s5 + 6a3c: 85d2 mv a1,s4 + 6a3e: 854e mv a0,s3 + 6a40: f51ff0ef jal ra,6990 + 6a44: a025 j 6a6c + 6a46: 8ebd xor a3,a3,a5 + 6a48: 87d4 sb a3,15(sp) + 6a4a: 8826 mv a6,s1 + 6a4c: 87c6 mv a5,a7 + 6a4e: 4705 li a4,1 + 6a50: 00f10693 addi a3,sp,15 + 6a54: f2dff0ef jal ra,6980 + 6a58: 0141 addi sp,sp,16 + 6a5a: fb0f906f j 20a <__riscv_restore_4> + 6a5e: 8826 mv a6,s1 + 6a60: 87c6 mv a5,a7 + 6a62: 4705 li a4,1 + 6a64: 00f10693 addi a3,sp,15 + 6a68: f19ff0ef jal ra,6980 + 6a6c: 8826 mv a6,s1 + 6a6e: 87a2 mv a5,s0 + 6a70: 4705 li a4,1 + 6a72: 00e10693 addi a3,sp,14 + 6a76: 8656 mv a2,s5 + 6a78: 85d2 mv a1,s4 + 6a7a: 854e mv a0,s3 + 6a7c: bfe1 j 6a54 + 6a7e: fff90713 addi a4,s2,-1 + 6a82: 8656 mv a2,s5 + 6a84: 85d2 mv a1,s4 + 6a86: 854e mv a0,s3 + 6a88: f09ff0ef jal ra,6990 + 6a8c: b7f1 j 6a58 + +00006a8e : + 6a8e: f62f92ef jal t0,1f0 <__riscv_save_0> + 6a92: 7125 addi sp,sp,-416 + 6a94: e119 bnez a0,6a9a + 6a96: 629020ef jal ra,98be + 6a9a: 451c lw a5,8(a0) + 6a9c: 842a mv s0,a0 + 6a9e: 0828 addi a0,sp,24 + 6aa0: c636 sw a3,12(sp) + 6aa2: c432 sw a2,8(sp) + 6aa4: c22e sw a1,4(sp) + 6aa6: 9782 jalr a5 + 6aa8: 4622 lw a2,8(sp) + 6aaa: 445c lw a5,12(s0) + 6aac: 4592 lw a1,4(sp) + 6aae: 0828 addi a0,sp,24 + 6ab0: 9782 jalr a5 + 6ab2: 46b2 lw a3,12(sp) + 6ab4: 481c lw a5,16(s0) + 6ab6: 0828 addi a0,sp,24 + 6ab8: 85b6 mv a1,a3 + 6aba: 9782 jalr a5 + 6abc: 18800613 li a2,392 + 6ac0: 4581 li a1,0 + 6ac2: 0828 addi a0,sp,24 + 6ac4: f5cf90ef jal ra,220 + 6ac8: 01814783 lbu a5,24(sp) + 6acc: 611d addi sp,sp,416 + 6ace: f46f906f j 214 <__riscv_restore_0> + +00006ad2 : + 6ad2: f04f92ef jal t0,1d6 <__riscv_save_4> + 6ad6: 7111 addi sp,sp,-256 + 6ad8: e119 bnez a0,6ade + 6ada: 5e5020ef jal ra,98be + 6ade: 842e mv s0,a1 + 6ae0: dded beqz a1,6ada + 6ae2: 89b2 mv s3,a2 + 6ae4: 4581 li a1,0 + 6ae6: 31800613 li a2,792 + 6aea: 84aa mv s1,a0 + 6aec: 8936 mv s2,a3 + 6aee: f32f90ef jal ra,220 + 6af2: 209c lbu a5,0(s1) + 6af4: 405c lw a5,4(s0) + 6af6: c080 sw s0,0(s1) + 6af8: 0b27fb63 bgeu a5,s2,6bae + 6afc: 4018 lw a4,0(s0) + 6afe: fce7eee3 bltu a5,a4,6ada + 6b02: 864a mv a2,s2 + 6b04: 868a mv a3,sp + 6b06: 85ce mv a1,s3 + 6b08: 8522 mv a0,s0 + 6b0a: f85ff0ef jal ra,6a8e + 6b0e: 00042903 lw s2,0(s0) + 6b12: 00442983 lw s3,4(s0) + 6b16: 01397963 bgeu s2,s3,6b28 + 6b1a: 41298633 sub a2,s3,s2 + 6b1e: 4581 li a1,0 + 6b20: 01210533 add a0,sp,s2 + 6b24: efcf90ef jal ra,220 + 6b28: 4781 li a5,0 + 6b2a: 04f99c63 bne s3,a5,6b82 + 6b2e: 441c lw a5,8(s0) + 6b30: 00848913 addi s2,s1,8 + 6b34: 854a mv a0,s2 + 6b36: 9782 jalr a5 + 6b38: 445c lw a5,12(s0) + 6b3a: 4050 lw a2,4(s0) + 6b3c: 010c addi a1,sp,128 + 6b3e: 854a mv a0,s2 + 6b40: 9782 jalr a5 + 6b42: 4054 lw a3,4(s0) + 6b44: 4781 li a5,0 + 6b46: 04f69963 bne a3,a5,6b98 + 6b4a: 441c lw a5,8(s0) + 6b4c: 19048493 addi s1,s1,400 + 6b50: 8526 mv a0,s1 + 6b52: 9782 jalr a5 + 6b54: 445c lw a5,12(s0) + 6b56: 4050 lw a2,4(s0) + 6b58: 010c addi a1,sp,128 + 6b5a: 8526 mv a0,s1 + 6b5c: 9782 jalr a5 + 6b5e: 08000613 li a2,128 + 6b62: 4581 li a1,0 + 6b64: 0108 addi a0,sp,128 + 6b66: ebaf90ef jal ra,220 + 6b6a: 08014783 lbu a5,128(sp) + 6b6e: 08000613 li a2,128 + 6b72: 4581 li a1,0 + 6b74: 850a mv a0,sp + 6b76: eaaf90ef jal ra,220 + 6b7a: 801c lbu a5,0(sp) + 6b7c: 6111 addi sp,sp,256 + 6b7e: e8cf906f j 20a <__riscv_restore_4> + 6b82: 0118 addi a4,sp,128 + 6b84: 00f706b3 add a3,a4,a5 + 6b88: 00f10733 add a4,sp,a5 + 6b8c: 2318 lbu a4,0(a4) + 6b8e: 0785 addi a5,a5,1 + 6b90: 03674713 xori a4,a4,54 + 6b94: a298 sb a4,0(a3) + 6b96: bf51 j 6b2a + 6b98: 0118 addi a4,sp,128 + 6b9a: 00f70633 add a2,a4,a5 + 6b9e: 00f10733 add a4,sp,a5 + 6ba2: 2318 lbu a4,0(a4) + 6ba4: 0785 addi a5,a5,1 + 6ba6: 05c74713 xori a4,a4,92 + 6baa: a218 sb a4,0(a2) + 6bac: bf69 j 6b46 + 6bae: 864a mv a2,s2 + 6bb0: 85ce mv a1,s3 + 6bb2: 850a mv a0,sp + 6bb4: 59f020ef jal ra,9952 + 6bb8: bfa9 j 6b12 + +00006bba : + 6bba: e36f92ef jal t0,1f0 <__riscv_save_0> + 6bbe: c119 beqz a0,6bc4 + 6bc0: 411c lw a5,0(a0) + 6bc2: e399 bnez a5,6bc8 + 6bc4: 4fb020ef jal ra,98be + 6bc8: 47dc lw a5,12(a5) + 6bca: 0521 addi a0,a0,8 + 6bcc: 9782 jalr a5 + 6bce: e46f906f j 214 <__riscv_restore_0> + +00006bd2 : + 6bd2: e1ef92ef jal t0,1f0 <__riscv_save_0> + 6bd6: 7139 addi sp,sp,-64 + 6bd8: c501 beqz a0,6be0 + 6bda: 411c lw a5,0(a0) + 6bdc: 842a mv s0,a0 + 6bde: e399 bnez a5,6be4 + 6be0: 4df020ef jal ra,98be + 6be4: 892e mv s2,a1 + 6be6: dded beqz a1,6be0 + 6be8: 4b9c lw a5,16(a5) + 6bea: 858a mv a1,sp + 6bec: 0521 addi a0,a0,8 + 6bee: 9782 jalr a5 + 6bf0: 401c lw a5,0(s0) + 6bf2: 19040493 addi s1,s0,400 + 6bf6: 858a mv a1,sp + 6bf8: 47d8 lw a4,12(a5) + 6bfa: 4390 lw a2,0(a5) + 6bfc: 8526 mv a0,s1 + 6bfe: 9702 jalr a4 + 6c00: 401c lw a5,0(s0) + 6c02: 85ca mv a1,s2 + 6c04: 8526 mv a0,s1 + 6c06: 4b9c lw a5,16(a5) + 6c08: 9782 jalr a5 + 6c0a: 31800613 li a2,792 + 6c0e: 4581 li a1,0 + 6c10: 8522 mv a0,s0 + 6c12: e0ef90ef jal ra,220 + 6c16: 201c lbu a5,0(s0) + 6c18: 6121 addi sp,sp,64 + 6c1a: dfaf906f j 214 <__riscv_restore_0> + +00006c1e : + 6c1e: dd2f92ef jal t0,1f0 <__riscv_save_0> + 6c22: cd010113 addi sp,sp,-816 + 6c26: 84b6 mv s1,a3 + 6c28: 86ae mv a3,a1 + 6c2a: 65b5 lui a1,0xd + 6c2c: 8432 mv s0,a2 + 6c2e: 67858593 addi a1,a1,1656 # d678 + 6c32: 862a mv a2,a0 + 6c34: 0828 addi a0,sp,24 + 6c36: c63a sw a4,12(sp) + 6c38: e9bff0ef jal ra,6ad2 + 6c3c: 8626 mv a2,s1 + 6c3e: 85a2 mv a1,s0 + 6c40: 0828 addi a0,sp,24 + 6c42: f79ff0ef jal ra,6bba + 6c46: 4732 lw a4,12(sp) + 6c48: 0828 addi a0,sp,24 + 6c4a: 85ba mv a1,a4 + 6c4c: f87ff0ef jal ra,6bd2 + 6c50: 4501 li a0,0 + 6c52: 33010113 addi sp,sp,816 + 6c56: dbef906f j 214 <__riscv_restore_0> + +00006c5a : + 6c5a: 01855793 srli a5,a0,0x18 + 6c5e: a19c sb a5,0(a1) + 6c60: 01055793 srli a5,a0,0x10 + 6c64: b19c sb a5,1(a1) + 6c66: 00855793 srli a5,a0,0x8 + 6c6a: a1bc sb a5,2(a1) + 6c6c: b1a8 sb a0,3(a1) + 6c6e: 8082 ret + +00006c70 : + 6c70: 7119 addi sp,sp,-128 + 6c72: d4d6 sw s5,104(sp) + 6c74: d2da sw s6,100(sp) + 6c76: 4118 lw a4,0(a0) + 6c78: 00452e83 lw t4,4(a0) + 6c7c: 00852e03 lw t3,8(a0) + 6c80: 00c52b03 lw s6,12(a0) + 6c84: 491c lw a5,16(a0) + 6c86: 01452f83 lw t6,20(a0) + 6c8a: 01852f03 lw t5,24(a0) + 6c8e: 01c52a83 lw s5,28(a0) + 6c92: 62b5 lui t0,0xd + 6c94: dea2 sw s0,124(sp) + 6c96: dca6 sw s1,120(sp) + 6c98: daca sw s2,116(sp) + 6c9a: d8ce sw s3,112(sp) + 6c9c: d6d2 sw s4,108(sp) + 6c9e: cce6 sw s9,88(sp) + 6ca0: caea sw s10,84(sp) + 6ca2: d0de sw s7,96(sp) + 6ca4: cee2 sw s8,92(sp) + 6ca6: c8ee sw s11,80(sp) + 6ca8: 57828293 addi t0,t0,1400 # d578 + 6cac: 4681 li a3,0 + 6cae: 8a3a mv s4,a4 + 6cb0: 89f6 mv s3,t4 + 6cb2: 8972 mv s2,t3 + 6cb4: 84da mv s1,s6 + 6cb6: 843e mv s0,a5 + 6cb8: 83fe mv t2,t6 + 6cba: c47a sw t5,8(sp) + 6cbc: c656 sw s5,12(sp) + 6cbe: 4d3d li s10,15 + 6cc0: 04000c93 li s9,64 + 6cc4: 12dd6363 bltu s10,a3,6dea + 6cc8: 0005cb83 lbu s7,0(a1) + 6ccc: 3190 lbu a2,1(a1) + 6cce: 01010813 addi a6,sp,16 + 6cd2: 0be2 slli s7,s7,0x18 + 6cd4: 0642 slli a2,a2,0x10 + 6cd6: 00cbebb3 or s7,s7,a2 + 6cda: 31b0 lbu a2,3(a1) + 6cdc: 0591 addi a1,a1,4 + 6cde: 00cbebb3 or s7,s7,a2 + 6ce2: ffe5c603 lbu a2,-2(a1) + 6ce6: 0622 slli a2,a2,0x8 + 6ce8: 00cbebb3 or s7,s7,a2 + 6cec: 00269613 slli a2,a3,0x2 + 6cf0: 9642 add a2,a2,a6 + 6cf2: 01762023 sw s7,0(a2) + 6cf6: 0067d813 srli a6,a5,0x6 + 6cfa: 01a79893 slli a7,a5,0x1a + 6cfe: 011868b3 or a7,a6,a7 + 6d02: 01579613 slli a2,a5,0x15 + 6d06: 00b7d813 srli a6,a5,0xb + 6d0a: 00c86633 or a2,a6,a2 + 6d0e: 00c8c833 xor a6,a7,a2 + 6d12: 0197d893 srli a7,a5,0x19 + 6d16: 00779613 slli a2,a5,0x7 + 6d1a: 01166633 or a2,a2,a7 + 6d1e: 00c84633 xor a2,a6,a2 + 6d22: fff7c813 not a6,a5 + 6d26: 01e87833 and a6,a6,t5 + 6d2a: 01f7f8b3 and a7,a5,t6 + 6d2e: 01184833 xor a6,a6,a7 + 6d32: 9642 add a2,a2,a6 + 6d34: 0002a803 lw a6,0(t0) + 6d38: 0685 addi a3,a3,1 + 6d3a: 0291 addi t0,t0,4 + 6d3c: 9642 add a2,a2,a6 + 6d3e: 9bb2 add s7,s7,a2 + 6d40: 01e71813 slli a6,a4,0x1e + 6d44: 00275613 srli a2,a4,0x2 + 6d48: 9ade add s5,s5,s7 + 6d4a: 01066833 or a6,a2,a6 + 6d4e: 00d75b93 srli s7,a4,0xd + 6d52: 01371613 slli a2,a4,0x13 + 6d56: 00cbebb3 or s7,s7,a2 + 6d5a: 01784633 xor a2,a6,s7 + 6d5e: 01675813 srli a6,a4,0x16 + 6d62: 00a71b93 slli s7,a4,0xa + 6d66: 010bebb3 or s7,s7,a6 + 6d6a: 01764bb3 xor s7,a2,s7 + 6d6e: 01cec633 xor a2,t4,t3 + 6d72: 8e79 and a2,a2,a4 + 6d74: 01cef833 and a6,t4,t3 + 6d78: 01064633 xor a2,a2,a6 + 6d7c: 9bb2 add s7,s7,a2 + 6d7e: 9bd6 add s7,s7,s5 + 6d80: 016a8633 add a2,s5,s6 + 6d84: 8b72 mv s6,t3 + 6d86: 8afa mv s5,t5 + 6d88: 05969a63 bne a3,s9,6ddc + 6d8c: 979e add a5,a5,t2 + 6d8e: c95c sw a5,20(a0) + 6d90: 47a2 lw a5,8(sp) + 6d92: 9432 add s0,s0,a2 + 6d94: c900 sw s0,16(a0) + 6d96: 9fbe add t6,t6,a5 + 6d98: 47b2 lw a5,12(sp) + 6d9a: 5476 lw s0,124(sp) + 6d9c: 9bd2 add s7,s7,s4 + 6d9e: 9f3e add t5,t5,a5 + 6da0: 513c lw a5,96(a0) + 6da2: 974e add a4,a4,s3 + 6da4: 9eca add t4,t4,s2 + 6da6: 9e26 add t3,t3,s1 + 6da8: 0785 addi a5,a5,1 + 6daa: 01752023 sw s7,0(a0) + 6dae: c158 sw a4,4(a0) + 6db0: 01d52423 sw t4,8(a0) + 6db4: 01c52623 sw t3,12(a0) + 6db8: 01f52c23 sw t6,24(a0) + 6dbc: 01e52e23 sw t5,28(a0) + 6dc0: d13c sw a5,96(a0) + 6dc2: 54e6 lw s1,120(sp) + 6dc4: 5956 lw s2,116(sp) + 6dc6: 59c6 lw s3,112(sp) + 6dc8: 5a36 lw s4,108(sp) + 6dca: 5aa6 lw s5,104(sp) + 6dcc: 5b16 lw s6,100(sp) + 6dce: 5b86 lw s7,96(sp) + 6dd0: 4c76 lw s8,92(sp) + 6dd2: 4ce6 lw s9,88(sp) + 6dd4: 4d56 lw s10,84(sp) + 6dd6: 4dc6 lw s11,80(sp) + 6dd8: 6109 addi sp,sp,128 + 6dda: 8082 ret + 6ddc: 8f7e mv t5,t6 + 6dde: 8e76 mv t3,t4 + 6de0: 8fbe mv t6,a5 + 6de2: 8eba mv t4,a4 + 6de4: 87b2 mv a5,a2 + 6de6: 875e mv a4,s7 + 6de8: bdf1 j 6cc4 + 6dea: ffe68613 addi a2,a3,-2 + 6dee: 8a3d andi a2,a2,15 + 6df0: 05010813 addi a6,sp,80 + 6df4: 060a slli a2,a2,0x2 + 6df6: 9642 add a2,a2,a6 + 6df8: fc062303 lw t1,-64(a2) + 6dfc: ff168613 addi a2,a3,-15 + 6e00: 8a3d andi a2,a2,15 + 6e02: 060a slli a2,a2,0x2 + 6e04: 9642 add a2,a2,a6 + 6e06: fc062883 lw a7,-64(a2) + 6e0a: ff968613 addi a2,a3,-7 + 6e0e: 00f6f813 andi a6,a3,15 + 6e12: 8a3d andi a2,a2,15 + 6e14: 05010b93 addi s7,sp,80 + 6e18: 060a slli a2,a2,0x2 + 6e1a: 080a slli a6,a6,0x2 + 6e1c: 985e add a6,a6,s7 + 6e1e: 965e add a2,a2,s7 + 6e20: fc062b83 lw s7,-64(a2) + 6e24: fc082603 lw a2,-64(a6) + 6e28: 00f31c13 slli s8,t1,0xf + 6e2c: 01335d93 srli s11,t1,0x13 + 6e30: 9bb2 add s7,s7,a2 + 6e32: 01135613 srli a2,t1,0x11 + 6e36: 00cc6c33 or s8,s8,a2 + 6e3a: 00d31613 slli a2,t1,0xd + 6e3e: 01b66633 or a2,a2,s11 + 6e42: 00cc4633 xor a2,s8,a2 + 6e46: 00a35313 srli t1,t1,0xa + 6e4a: 00664633 xor a2,a2,t1 + 6e4e: 9bb2 add s7,s7,a2 + 6e50: 0078d313 srli t1,a7,0x7 + 6e54: 01989613 slli a2,a7,0x19 + 6e58: 00c36633 or a2,t1,a2 + 6e5c: 0128dc13 srli s8,a7,0x12 + 6e60: 00e89313 slli t1,a7,0xe + 6e64: 01836333 or t1,t1,s8 + 6e68: 00664633 xor a2,a2,t1 + 6e6c: 0038d893 srli a7,a7,0x3 + 6e70: 011648b3 xor a7,a2,a7 + 6e74: 9bc6 add s7,s7,a7 + 6e76: fd782023 sw s7,-64(a6) + 6e7a: bdb5 j 6cf6 + +00006e7c : + 6e7c: b74f92ef jal t0,1f0 <__riscv_save_0> + 6e80: 842a mv s0,a0 + 6e82: 04800613 li a2,72 + 6e86: 4581 li a1,0 + 6e88: 02050513 addi a0,a0,32 + 6e8c: b94f90ef jal ra,220 + 6e90: 6a09e7b7 lui a5,0x6a09e + 6e94: 66778793 addi a5,a5,1639 # 6a09e667 <_eusrstack+0x4a096667> + 6e98: c01c sw a5,0(s0) + 6e9a: bb67b7b7 lui a5,0xbb67b + 6e9e: e8578793 addi a5,a5,-379 # bb67ae85 <_eusrstack+0x9b672e85> + 6ea2: c05c sw a5,4(s0) + 6ea4: 3c6ef7b7 lui a5,0x3c6ef + 6ea8: 37278793 addi a5,a5,882 # 3c6ef372 <_eusrstack+0x1c6e7372> + 6eac: c41c sw a5,8(s0) + 6eae: a54ff7b7 lui a5,0xa54ff + 6eb2: 53a78793 addi a5,a5,1338 # a54ff53a <_eusrstack+0x854f753a> + 6eb6: c45c sw a5,12(s0) + 6eb8: 510e57b7 lui a5,0x510e5 + 6ebc: 27f78793 addi a5,a5,639 # 510e527f <_eusrstack+0x310dd27f> + 6ec0: c81c sw a5,16(s0) + 6ec2: 9b0577b7 lui a5,0x9b057 + 6ec6: 88c78793 addi a5,a5,-1908 # 9b05688c <_eusrstack+0x7b04e88c> + 6eca: c85c sw a5,20(s0) + 6ecc: 1f83e7b7 lui a5,0x1f83e + 6ed0: 9ab78793 addi a5,a5,-1621 # 1f83d9ab <_data_lma+0x1f82f74f> + 6ed4: cc1c sw a5,24(s0) + 6ed6: 5be0d7b7 lui a5,0x5be0d + 6eda: d1978793 addi a5,a5,-743 # 5be0cd19 <_eusrstack+0x3be04d19> + 6ede: cc5c sw a5,28(s0) + 6ee0: b34f906f j 214 <__riscv_restore_0> + +00006ee4 : + 6ee4: b0cf92ef jal t0,1f0 <__riscv_save_0> + 6ee8: 000077b7 lui a5,0x7 + 6eec: 882a mv a6,a0 + 6eee: 8732 mv a4,a2 + 6ef0: 86ae mv a3,a1 + 6ef2: c7078793 addi a5,a5,-912 # 6c70 + 6ef6: 06450593 addi a1,a0,100 + 6efa: 04000613 li a2,64 + 6efe: 02050513 addi a0,a0,32 + 6f02: a7fff0ef jal ra,6980 + 6f06: b0ef906f j 214 <__riscv_restore_0> + +00006f0a : + 6f0a: accf92ef jal t0,1d6 <__riscv_save_4> + 6f0e: 513c lw a5,96(a0) + 6f10: 06452903 lw s2,100(a0) + 6f14: 1101 addi sp,sp,-32 + 6f16: 01a7d713 srli a4,a5,0x1a + 6f1a: 079a slli a5,a5,0x6 + 6f1c: 993e add s2,s2,a5 + 6f1e: 00f934b3 sltu s1,s2,a5 + 6f22: 94ba add s1,s1,a4 + 6f24: 01d95793 srli a5,s2,0x1d + 6f28: 048e slli s1,s1,0x3 + 6f2a: 8cdd or s1,s1,a5 + 6f2c: 00890793 addi a5,s2,8 + 6f30: 03f7f793 andi a5,a5,63 + 6f34: 000078b7 lui a7,0x7 + 6f38: 04000813 li a6,64 + 6f3c: 842a mv s0,a0 + 6f3e: 40f80833 sub a6,a6,a5 + 6f42: c02a sw a0,0(sp) + 6f44: c7088893 addi a7,a7,-912 # 6c70 + 6f48: 4781 li a5,0 + 6f4a: 4701 li a4,0 + 6f4c: 08000693 li a3,128 + 6f50: 04000613 li a2,64 + 6f54: 89ae mv s3,a1 + 6f56: 06450593 addi a1,a0,100 + 6f5a: 02050513 addi a0,a0,32 + 6f5e: a97ff0ef jal ra,69f4 + 6f62: 00391a13 slli s4,s2,0x3 + 6f66: 0084d793 srli a5,s1,0x8 + 6f6a: 00f10d23 sb a5,26(sp) + 6f6e: 018a5793 srli a5,s4,0x18 + 6f72: 00f10e23 sb a5,28(sp) + 6f76: 010a5793 srli a5,s4,0x10 + 6f7a: 0a42 slli s4,s4,0x10 + 6f7c: 010a5a13 srli s4,s4,0x10 + 6f80: 092e slli s2,s2,0xb + 6f82: 008a5a13 srli s4,s4,0x8 + 6f86: 01496933 or s2,s2,s4 + 6f8a: 4621 li a2,8 + 6f8c: 082c addi a1,sp,24 + 6f8e: 8522 mv a0,s0 + 6f90: 00f10ea3 sb a5,29(sp) + 6f94: 00011c23 sh zero,24(sp) + 6f98: 00910da3 sb s1,27(sp) + 6f9c: 01211f23 sh s2,30(sp) + 6fa0: f45ff0ef jal ra,6ee4 + 6fa4: 507c lw a5,100(s0) + 6fa6: c399 beqz a5,6fac + 6fa8: 117020ef jal ra,98be + 6fac: 4008 lw a0,0(s0) + 6fae: 85ce mv a1,s3 + 6fb0: cabff0ef jal ra,6c5a + 6fb4: 4048 lw a0,4(s0) + 6fb6: 00498593 addi a1,s3,4 + 6fba: ca1ff0ef jal ra,6c5a + 6fbe: 4408 lw a0,8(s0) + 6fc0: 00898593 addi a1,s3,8 + 6fc4: c97ff0ef jal ra,6c5a + 6fc8: 4448 lw a0,12(s0) + 6fca: 00c98593 addi a1,s3,12 + 6fce: c8dff0ef jal ra,6c5a + 6fd2: 4808 lw a0,16(s0) + 6fd4: 01098593 addi a1,s3,16 + 6fd8: c83ff0ef jal ra,6c5a + 6fdc: 4848 lw a0,20(s0) + 6fde: 01498593 addi a1,s3,20 + 6fe2: c79ff0ef jal ra,6c5a + 6fe6: 4c08 lw a0,24(s0) + 6fe8: 01898593 addi a1,s3,24 + 6fec: c6fff0ef jal ra,6c5a + 6ff0: 4c48 lw a0,28(s0) + 6ff2: 01c98593 addi a1,s3,28 + 6ff6: c65ff0ef jal ra,6c5a + 6ffa: 06800613 li a2,104 + 6ffe: 4581 li a1,0 + 7000: 8522 mv a0,s0 + 7002: a1ef90ef jal ra,220 + 7006: 6105 addi sp,sp,32 + 7008: a02f906f j 20a <__riscv_restore_4> + +0000700c : + 700c: 9e4f92ef jal t0,1f0 <__riscv_save_0> + 7010: 7159 addi sp,sp,-112 + 7012: 842e mv s0,a1 + 7014: 06800613 li a2,104 + 7018: 85aa mv a1,a0 + 701a: 0028 addi a0,sp,8 + 701c: 137020ef jal ra,9952 + 7020: 0028 addi a0,sp,8 + 7022: 85a2 mv a1,s0 + 7024: ee7ff0ef jal ra,6f0a + 7028: 6165 addi sp,sp,112 + 702a: 9eaf906f j 214 <__riscv_restore_0> + +0000702e : + 702e: 9c2f92ef jal t0,1f0 <__riscv_save_0> + 7032: 1101 addi sp,sp,-32 + 7034: 02000613 li a2,32 + 7038: 4581 li a1,0 + 703a: 850a mv a0,sp + 703c: 9e4f90ef jal ra,220 + 7040: 4585 li a1,1 + 7042: 20000513 li a0,512 + 7046: 0d8020ef jal ra,911e + 704a: 6531 lui a0,0xc + 704c: 40012437 lui s0,0x40012 + 7050: 6f3010ef jal ra,8f42 + 7054: 40040513 addi a0,s0,1024 # 40012400 <_eusrstack+0x2000a400> + 7058: 251010ef jal ra,8aa8 + 705c: 000e07b7 lui a5,0xe0 + 7060: c63e sw a5,12(sp) + 7062: 858a mv a1,sp + 7064: 4785 li a5,1 + 7066: 40040513 addi a0,s0,1024 + 706a: 00f10a23 sb a5,20(sp) + 706e: c002 sw zero,0(sp) + 7070: c202 sw zero,4(sp) + 7072: c402 sw zero,8(sp) + 7074: c802 sw zero,16(sp) + 7076: 273010ef jal ra,8ae8 + 707a: 4585 li a1,1 + 707c: 40040513 addi a0,s0,1024 + 7080: 2bf010ef jal ra,8b3e + 7084: 4581 li a1,0 + 7086: 40040513 addi a0,s0,1024 + 708a: 3eb010ef jal ra,8c74 + 708e: 40040513 addi a0,s0,1024 + 7092: 2bd010ef jal ra,8b4e + 7096: 40040493 addi s1,s0,1024 + 709a: 8526 mv a0,s1 + 709c: 2bd010ef jal ra,8b58 + 70a0: fd6d bnez a0,709a + 70a2: 40040513 addi a0,s0,1024 + 70a6: 40012437 lui s0,0x40012 + 70aa: 2b7010ef jal ra,8b60 + 70ae: 40040493 addi s1,s0,1024 # 40012400 <_eusrstack+0x2000a400> + 70b2: 8526 mv a0,s1 + 70b4: 2b7010ef jal ra,8b6a + 70b8: fd6d bnez a0,70b2 + 70ba: 40040513 addi a0,s0,1024 + 70be: 3cf010ef jal ra,8c8c + 70c2: 82a19123 sh a0,-2014(gp) # 20000212 + 70c6: 4585 li a1,1 + 70c8: 40040513 addi a0,s0,1024 + 70cc: 3a9010ef jal ra,8c74 + 70d0: 4505 li a0,1 + 70d2: 379010ef jal ra,8c4a + 70d6: 6105 addi sp,sp,32 + 70d8: 93cf906f j 214 <__riscv_restore_0> + +000070dc : + 70dc: 914f92ef jal t0,1f0 <__riscv_save_0> + 70e0: 40012437 lui s0,0x40012 + 70e4: 85aa mv a1,a0 + 70e6: 469d li a3,7 + 70e8: 4605 li a2,1 + 70ea: 40040513 addi a0,s0,1024 # 40012400 <_eusrstack+0x2000a400> + 70ee: 29d010ef jal ra,8b8a + 70f2: 4585 li a1,1 + 70f4: 40040513 addi a0,s0,1024 + 70f8: 27b010ef jal ra,8b72 + 70fc: 40040493 addi s1,s0,1024 + 7100: 4589 li a1,2 + 7102: 8526 mv a0,s1 + 7104: 367010ef jal ra,8c6a + 7108: dd65 beqz a0,7100 + 710a: 40040513 addi a0,s0,1024 + 710e: 335010ef jal ra,8c42 + 7112: 902f906f j 214 <__riscv_restore_0> + +00007116 : + 7116: 8daf92ef jal t0,1f0 <__riscv_save_0> + 711a: 1141 addi sp,sp,-16 + 711c: 892a mv s2,a0 + 711e: 4401 li s0,0 + 7120: 4481 li s1,0 + 7122: 00b41963 bne s0,a1,7134 + 7126: 0284d533 divu a0,s1,s0 + 712a: 0141 addi sp,sp,16 + 712c: 0542 slli a0,a0,0x10 + 712e: 8141 srli a0,a0,0x10 + 7130: 8e4f906f j 214 <__riscv_restore_0> + 7134: 854a mv a0,s2 + 7136: c62e sw a1,12(sp) + 7138: fa5ff0ef jal ra,70dc + 713c: 94aa add s1,s1,a0 + 713e: 4515 li a0,5 + 7140: 326020ef jal ra,9466 + 7144: 0405 addi s0,s0,1 + 7146: 0ff47413 andi s0,s0,255 + 714a: 45b2 lw a1,12(sp) + 714c: bfd9 j 7122 + +0000714e : + 714e: 82219703 lh a4,-2014(gp) # 20000212 + 7152: 4781 li a5,0 + 7154: 972a add a4,a4,a0 + 7156: 00074f63 bltz a4,7174 + 715a: cd09 beqz a0,7174 + 715c: 6605 lui a2,0x1 + 715e: fff60693 addi a3,a2,-1 # fff + 7162: 87b6 mv a5,a3 + 7164: 00c75863 bge a4,a2,7174 + 7168: 87aa mv a5,a0 + 716a: 00d50563 beq a0,a3,7174 + 716e: 01071793 slli a5,a4,0x10 + 7172: 83c1 srli a5,a5,0x10 + 7174: 853e mv a0,a5 + 7176: 8082 ret + +00007178 : + 7178: 1ffff7b7 lui a5,0x1ffff + 717c: 7207a783 lw a5,1824(a5) # 1ffff720 <_data_lma+0x1fff14c4> + 7180: 46a9 li a3,10 + 7182: 0107d713 srli a4,a5,0x10 + 7186: 07c2 slli a5,a5,0x10 + 7188: 83c1 srli a5,a5,0x10 + 718a: 8d1d sub a0,a0,a5 + 718c: 06400793 li a5,100 + 7190: 02f50533 mul a0,a0,a5 + 7194: 02b00793 li a5,43 + 7198: 0555 addi a0,a0,21 + 719a: 02f54533 div a0,a0,a5 + 719e: 02d70733 mul a4,a4,a3 + 71a2: 40a70533 sub a0,a4,a0 + 71a6: 8082 ret + +000071a8 : + 71a8: 848f92ef jal t0,1f0 <__riscv_save_0> + 71ac: 45a9 li a1,10 + 71ae: 4541 li a0,16 + 71b0: f67ff0ef jal ra,7116 + 71b4: 0542 slli a0,a0,0x10 + 71b6: 8541 srai a0,a0,0x10 + 71b8: f97ff0ef jal ra,714e + 71bc: 6785 lui a5,0x1 + 71be: ce478793 addi a5,a5,-796 # ce4 + 71c2: 02f50533 mul a0,a0,a5 + 71c6: 8531 srai a0,a0,0xc + 71c8: fb1ff0ef jal ra,7178 + 71cc: 0542 slli a0,a0,0x10 + 71ce: 8541 srai a0,a0,0x10 + 71d0: 844f906f j 214 <__riscv_restore_0> + +000071d4 : + 71d4: 81cf92ef jal t0,1f0 <__riscv_save_0> + 71d8: 45a9 li a1,10 + 71da: 4505 li a0,1 + 71dc: f3bff0ef jal ra,7116 + 71e0: 0542 slli a0,a0,0x10 + 71e2: 8541 srai a0,a0,0x10 + 71e4: f6bff0ef jal ra,714e + 71e8: 6785 lui a5,0x1 + 71ea: ce478793 addi a5,a5,-796 # ce4 + 71ee: 02f50533 mul a0,a0,a5 + 71f2: 8531 srai a0,a0,0xc + 71f4: 820f906f j 214 <__riscv_restore_0> + +000071f8 : + 71f8: 00055563 bgez a0,7202 + 71fc: 010007b7 lui a5,0x1000 + 7200: 953e add a0,a0,a5 + 7202: 41055793 srai a5,a0,0x10 + 7206: a19c sb a5,0(a1) + 7208: 40855793 srai a5,a0,0x8 + 720c: b19c sb a5,1(a1) + 720e: a1a8 sb a0,2(a1) + 7210: 8082 ret + +00007212 : + 7212: fdff82ef jal t0,1f0 <__riscv_save_0> + 7216: 843a mv s0,a4 + 7218: 87ae mv a5,a1 + 721a: a308 sb a0,0(a4) + 721c: f8800713 li a4,-120 + 7220: 1141 addi sp,sp,-16 + 7222: 853e mv a0,a5 + 7224: b018 sb a4,1(s0) + 7226: 00240593 addi a1,s0,2 + 722a: c436 sw a3,8(sp) + 722c: c632 sw a2,12(sp) + 722e: fcbff0ef jal ra,71f8 + 7232: 4632 lw a2,12(sp) + 7234: 00540593 addi a1,s0,5 + 7238: 8532 mv a0,a2 + 723a: fbfff0ef jal ra,71f8 + 723e: 46a2 lw a3,8(sp) + 7240: 00840593 addi a1,s0,8 + 7244: 8536 mv a0,a3 + 7246: fb3ff0ef jal ra,71f8 + 724a: 0141 addi sp,sp,16 + 724c: fc9f806f j 214 <__riscv_restore_0> + +00007250 : + 7250: 200007b7 lui a5,0x20000 + 7254: 6705 lui a4,0x1 + 7256: 38c78793 addi a5,a5,908 # 2000038c + 725a: b8070713 addi a4,a4,-1152 # b80 + 725e: 20000537 lui a0,0x20000 + 7262: 973e add a4,a4,a5 + 7264: 5d050513 addi a0,a0,1488 # 200005d0 + 7268: 55fd li a1,-1 + 726a: 2ed7c683 lbu a3,749(a5) + 726e: 8a85 andi a3,a3,1 + 7270: ea91 bnez a3,7284 + 7272: 2f47a683 lw a3,756(a5) + 7276: 24478613 addi a2,a5,580 + 727a: ca91 beqz a3,728e + 727c: 00b6f463 bgeu a3,a1,7284 + 7280: 8532 mv a0,a2 + 7282: 85b6 mv a1,a3 + 7284: 0b878793 addi a5,a5,184 + 7288: fee791e3 bne a5,a4,726a + 728c: 8082 ret + 728e: 8532 mv a0,a2 + 7290: 8082 ret + +00007292 : + 7292: 20000737 lui a4,0x20000 + 7296: 38c70693 addi a3,a4,908 # 2000038c + 729a: 4781 li a5,0 + 729c: 38c70713 addi a4,a4,908 + 72a0: 4641 li a2,16 + 72a2: 2646c583 lbu a1,612(a3) + 72a6: 00a58963 beq a1,a0,72b8 + 72aa: 0785 addi a5,a5,1 + 72ac: 0b868693 addi a3,a3,184 + 72b0: fec799e3 bne a5,a2,72a2 + 72b4: 4501 li a0,0 + 72b6: 8082 ret + 72b8: 0b800513 li a0,184 + 72bc: 02a787b3 mul a5,a5,a0 + 72c0: 24478793 addi a5,a5,580 + 72c4: 00f70533 add a0,a4,a5 + 72c8: 8082 ret + +000072ca : + 72ca: f0df82ef jal t0,1d6 <__riscv_save_4> + 72ce: 89aa mv s3,a0 + 72d0: 20000537 lui a0,0x20000 + 72d4: 38c50493 addi s1,a0,908 # 2000038c + 72d8: 6905 lui s2,0x1 + 72da: 4401 li s0,0 + 72dc: 26448a13 addi s4,s1,612 + 72e0: b8090913 addi s2,s2,-1152 # b80 + 72e4: 4611 li a2,4 + 72e6: 85ce mv a1,s3 + 72e8: 008a0533 add a0,s4,s0 + 72ec: 642020ef jal ra,992e + 72f0: e519 bnez a0,72fe + 72f2: 0b840413 addi s0,s0,184 + 72f6: ff2417e3 bne s0,s2,72e4 + 72fa: f11f806f j 20a <__riscv_restore_4> + 72fe: 24440513 addi a0,s0,580 + 7302: 9526 add a0,a0,s1 + 7304: bfdd j 72fa + +00007306 : + 7306: 20000737 lui a4,0x20000 + 730a: 38c70613 addi a2,a4,908 # 2000038c + 730e: 4781 li a5,0 + 7310: 4681 li a3,0 + 7312: 38c70713 addi a4,a4,908 + 7316: 4821 li a6,8 + 7318: 0b464883 lbu a7,180(a2) + 731c: 00a89763 bne a7,a0,732a + 7320: 0685 addi a3,a3,1 + 7322: 0ff6f693 andi a3,a3,255 + 7326: 00d5e963 bltu a1,a3,7338 + 732a: 0785 addi a5,a5,1 + 732c: 03860613 addi a2,a2,56 + 7330: ff0794e3 bne a5,a6,7318 + 7334: 4501 li a0,0 + 7336: 8082 ret + 7338: 03800513 li a0,56 + 733c: 02a787b3 mul a5,a5,a0 + 7340: 08478793 addi a5,a5,132 + 7344: 00f70533 add a0,a4,a5 + 7348: 8082 ret + +0000734a : + 734a: e8df82ef jal t0,1d6 <__riscv_save_4> + 734e: 20000437 lui s0,0x20000 + 7352: 41040493 addi s1,s0,1040 # 20000410 + 7356: 7175 addi sp,sp,-144 + 7358: 892a mv s2,a0 + 735a: 89ae mv s3,a1 + 735c: 4681 li a3,0 + 735e: 41040413 addi s0,s0,1040 + 7362: 577d li a4,-1 + 7364: 4621 li a2,8 + 7366: 58dc lw a5,52(s1) + 7368: ebad bnez a5,73da + 736a: 0000d637 lui a2,0xd + 736e: 0000b5b7 lui a1,0xb + 7372: 0000d537 lui a0,0xd + 7376: 874a mv a4,s2 + 7378: 71860613 addi a2,a2,1816 # d718 + 737c: 66058593 addi a1,a1,1632 # b660 <_exit+0x208> + 7380: 72050513 addi a0,a0,1824 # d720 + 7384: 043020ef jal ra,9bc6 + 7388: 8426 mv s0,s1 + 738a: 02000613 li a2,32 + 738e: 4581 li a1,0 + 7390: 8522 mv a0,s0 + 7392: e8ff80ef jal ra,220 + 7396: 85ca mv a1,s2 + 7398: 02000613 li a2,32 + 739c: 8522 mv a0,s0 + 739e: 3bb020ef jal ra,9f58 + 73a2: 02040493 addi s1,s0,32 + 73a6: 85ce mv a1,s3 + 73a8: 4641 li a2,16 + 73aa: 8526 mv a0,s1 + 73ac: 5a6020ef jal ra,9952 + 73b0: 1028 addi a0,sp,40 + 73b2: acbff0ef jal ra,6e7c + 73b6: 4641 li a2,16 + 73b8: 85a6 mv a1,s1 + 73ba: 1028 addi a0,sp,40 + 73bc: b29ff0ef jal ra,6ee4 + 73c0: 002c addi a1,sp,8 + 73c2: 1028 addi a0,sp,40 + 73c4: c49ff0ef jal ra,700c + 73c8: 841c lbu a5,8(sp) + 73ca: 02f40823 sb a5,48(s0) + 73ce: 63d010ef jal ra,920a + 73d2: d848 sw a0,52(s0) + 73d4: 6149 addi sp,sp,144 + 73d6: e35f806f j 20a <__riscv_restore_4> + 73da: 00048583 lb a1,0(s1) + 73de: ed99 bnez a1,73fc + 73e0: 0000d637 lui a2,0xd + 73e4: 0000b5b7 lui a1,0xb + 73e8: 0000d537 lui a0,0xd + 73ec: 874a mv a4,s2 + 73ee: 71860613 addi a2,a2,1816 # d718 + 73f2: 66058593 addi a1,a1,1632 # b660 <_exit+0x208> + 73f6: 76c50513 addi a0,a0,1900 # d76c + 73fa: b769 j 7384 + 73fc: 00e7f463 bgeu a5,a4,7404 + 7400: 8426 mv s0,s1 + 7402: 873e mv a4,a5 + 7404: 0685 addi a3,a3,1 + 7406: 03848493 addi s1,s1,56 + 740a: f4c69ee3 bne a3,a2,7366 + 740e: bfb5 j 738a + +00007410 : + 7410: db9f82ef jal t0,1c8 <__riscv_save_10> + 7414: 0000e537 lui a0,0xe + 7418: 81450513 addi a0,a0,-2028 # d814 + 741c: 20000437 lui s0,0x20000 + 7420: 0000e937 lui s2,0xe + 7424: 0000e9b7 lui s3,0xe + 7428: 0e5020ef jal ra,9d0c + 742c: 38c40413 addi s0,s0,908 # 2000038c + 7430: 4481 li s1,0 + 7432: 0000ea37 lui s4,0xe + 7436: 0000eab7 lui s5,0xe + 743a: 0000eb37 lui s6,0xe + 743e: 0000ebb7 lui s7,0xe + 7442: 80c90913 addi s2,s2,-2036 # d80c + 7446: 81098993 addi s3,s3,-2032 # d810 + 744a: 2f442783 lw a5,756(s0) + 744e: 0c078c63 beqz a5,7526 + 7452: 85a6 mv a1,s1 + 7454: 824a0513 addi a0,s4,-2012 # d824 + 7458: 76e020ef jal ra,9bc6 + 745c: 24440593 addi a1,s0,580 + 7460: 830a8513 addi a0,s5,-2000 # d830 + 7464: 762020ef jal ra,9bc6 + 7468: 02000613 li a2,32 + 746c: 26440593 addi a1,s0,612 + 7470: 83cb0513 addi a0,s6,-1988 # d83c + 7474: f6ff80ef jal ra,3e2 + 7478: 02000613 li a2,32 + 747c: 28440593 addi a1,s0,644 + 7480: 844b8513 addi a0,s7,-1980 # d844 + 7484: f5ff80ef jal ra,3e2 + 7488: 0000e537 lui a0,0xe + 748c: 99850513 addi a0,a0,-1640 # d998 + 7490: 736020ef jal ra,9bc6 + 7494: 2a842603 lw a2,680(s0) + 7498: 2a442583 lw a1,676(s0) + 749c: 0000e537 lui a0,0xe + 74a0: 84c50513 addi a0,a0,-1972 # d84c + 74a4: 722020ef jal ra,9bc6 + 74a8: 0000e537 lui a0,0xe + 74ac: 86450513 addi a0,a0,-1948 # d864 + 74b0: 716020ef jal ra,9bc6 + 74b4: 2ed44583 lbu a1,749(s0) + 74b8: 0000e537 lui a0,0xe + 74bc: 89050513 addi a0,a0,-1904 # d890 + 74c0: 706020ef jal ra,9bc6 + 74c4: 2ee44583 lbu a1,750(s0) + 74c8: 0000c537 lui a0,0xc + 74cc: bd050513 addi a0,a0,-1072 # bbd0 <_exit+0x778> + 74d0: 6f6020ef jal ra,9bc6 + 74d4: 2ef44783 lbu a5,751(s0) + 74d8: 85ca mv a1,s2 + 74da: e391 bnez a5,74de + 74dc: 85ce mv a1,s3 + 74de: 0000e537 lui a0,0xe + 74e2: 8a450513 addi a0,a0,-1884 # d8a4 + 74e6: 6e0020ef jal ra,9bc6 + 74ea: 2f042583 lw a1,752(s0) + 74ee: 0000e537 lui a0,0xe + 74f2: 8bc50513 addi a0,a0,-1860 # d8bc + 74f6: 6d0020ef jal ra,9bc6 + 74fa: 2f442583 lw a1,756(s0) + 74fe: 0000e537 lui a0,0xe + 7502: 8dc50513 addi a0,a0,-1828 # d8dc + 7506: 6c0020ef jal ra,9bc6 + 750a: 2f842583 lw a1,760(s0) + 750e: 0000e537 lui a0,0xe + 7512: 8f850513 addi a0,a0,-1800 # d8f8 + 7516: 6b0020ef jal ra,9bc6 + 751a: 0000e537 lui a0,0xe + 751e: 91050513 addi a0,a0,-1776 # d910 + 7522: 6a4020ef jal ra,9bc6 + 7526: 0485 addi s1,s1,1 + 7528: 47c1 li a5,16 + 752a: 0b840413 addi s0,s0,184 + 752e: f0f49ee3 bne s1,a5,744a + 7532: ccff806f j 200 <__riscv_restore_10> + +00007536 : + 7536: 157d addi a0,a0,-1 + 7538: 0ff57513 andi a0,a0,255 + 753c: 478d li a5,3 + 753e: 00a7e963 bltu a5,a0,7550 + 7542: 67b5 lui a5,0xd + 7544: 69c78793 addi a5,a5,1692 # d69c + 7548: 050a slli a0,a0,0x2 + 754a: 953e add a0,a0,a5 + 754c: 4108 lw a0,0(a0) + 754e: 8082 ret + 7550: 0000d537 lui a0,0xd + 7554: 7b850513 addi a0,a0,1976 # d7b8 + 7558: 8082 ret + +0000755a : + 755a: c97f82ef jal t0,1f0 <__riscv_save_0> + 755e: 1101 addi sp,sp,-32 + 7560: 0000d5b7 lui a1,0xd + 7564: 02000613 li a2,32 + 7568: 7c058593 addi a1,a1,1984 # d7c0 + 756c: 850a mv a0,sp + 756e: 3e4020ef jal ra,9952 + 7572: 200005b7 lui a1,0x20000 + 7576: 20000537 lui a0,0x20000 + 757a: 860a mv a2,sp + 757c: 3b058593 addi a1,a1,944 # 200003b0 + 7580: 39050513 addi a0,a0,912 # 20000390 + 7584: 986fc0ef jal ra,370a + 7588: 20000437 lui s0,0x20000 + 758c: 38c40413 addi s0,s0,908 # 2000038c + 7590: 4785 li a5,1 + 7592: 7601a023 sw zero,1888(gp) # 20001150 <__global_pointer$+0x760> + 7596: 04f40223 sb a5,68(s0) + 759a: 0000d5b7 lui a1,0xd + 759e: 76018793 addi a5,gp,1888 # 20001150 <__global_pointer$+0x760> + 75a2: 0007a223 sw zero,4(a5) + 75a6: 0007a423 sw zero,8(a5) + 75aa: 0007a623 sw zero,12(a5) + 75ae: 7e058593 addi a1,a1,2016 # d7e0 + 75b2: 76018513 addi a0,gp,1888 # 20001150 <__global_pointer$+0x760> + 75b6: 181020ef jal ra,9f36 + 75ba: 0000d5b7 lui a1,0xd + 75be: 20000537 lui a0,0x20000 + 75c2: 7ec58593 addi a1,a1,2028 # d7ec + 75c6: 3d150513 addi a0,a0,977 # 200003d1 + 75ca: 16d020ef jal ra,9f36 + 75ce: 47d1 li a5,20 + 75d0: 06f40a23 sb a5,116(s0) + 75d4: 33d457b7 lui a5,0x33d45 + 75d8: 75078793 addi a5,a5,1872 # 33d45750 <_eusrstack+0x13d3d750> + 75dc: dc3c sw a5,120(s0) + 75de: 30800793 li a5,776 + 75e2: 06f41e23 sh a5,124(s0) + 75e6: 4791 li a5,4 + 75e8: 06f40f23 sb a5,126(s0) + 75ec: 6485 lui s1,0x1 + 75ee: 089807b7 lui a5,0x8980 + 75f2: 07c1 addi a5,a5,16 + 75f4: 4641 li a2,16 + 75f6: 94a2 add s1,s1,s0 + 75f8: 07440593 addi a1,s0,116 + 75fc: 98c18513 addi a0,gp,-1652 # 2000037c + 7600: 08f42023 sw a5,128(s0) + 7604: de049323 sh zero,-538(s1) # de6 + 7608: 34a020ef jal ra,9952 + 760c: 65b9 lui a1,0xe + 760e: 0000d537 lui a0,0xd + 7612: 93858593 addi a1,a1,-1736 # d938 + 7616: 7fc50513 addi a0,a0,2044 # d7fc + 761a: d31ff0ef jal ra,734a + 761e: 65b5 lui a1,0xd + 7620: 0000e537 lui a0,0xe + 7624: 68c58593 addi a1,a1,1676 # d68c + 7628: 80450513 addi a0,a0,-2044 # d804 + 762c: d1fff0ef jal ra,734a + 7630: 10100793 li a5,257 + 7634: def49223 sh a5,-540(s1) + 7638: 02df57b7 lui a5,0x2df5 + 763c: 5b478793 addi a5,a5,1460 # 2df55b4 <_data_lma+0x2de7358> + 7640: d43c sw a5,104(s0) + 7642: 0103e7b7 lui a5,0x103e + 7646: c9c78793 addi a5,a5,-868 # 103dc9c <_data_lma+0x102fa40> + 764a: d47c sw a5,108(s0) + 764c: 6799 lui a5,0x6 + 764e: b6878793 addi a5,a5,-1176 # 5b68 + 7652: d83c sw a5,112(s0) + 7654: 6105 addi sp,sp,32 + 7656: bbff806f j 214 <__riscv_restore_0> + +0000765a : + 765a: b97f82ef jal t0,1f0 <__riscv_save_0> + 765e: 0000d4b7 lui s1,0xd + 7662: 0000b5b7 lui a1,0xb + 7666: 0000d537 lui a0,0xd + 766a: 71848613 addi a2,s1,1816 # d718 + 766e: 49458593 addi a1,a1,1172 # b494 <_exit+0x3c> + 7672: 6ac50513 addi a0,a0,1708 # d6ac + 7676: 550020ef jal ra,9bc6 + 767a: 265d jal 7a20 + 767c: 4501 li a0,0 + 767e: 2b25 jal 7bb6 + 7680: 98c18413 addi s0,gp,-1652 # 2000037c + 7684: 2472 lhu a2,14(s0) + 7686: 00040583 lb a1,0(s0) + 768a: 4048 lw a0,4(s0) + 768c: 4681 li a3,0 + 768e: 3ad000ef jal ra,823a + 7692: cd05 beqz a0,76ca + 7694: 0000c437 lui s0,0xc + 7698: 0000d537 lui a0,0xd + 769c: 71848613 addi a2,s1,1816 + 76a0: 18840593 addi a1,s0,392 # c188 <_exit+0xd30> + 76a4: 6c050513 addi a0,a0,1728 # d6c0 + 76a8: 51e020ef jal ra,9bc6 + 76ac: 0000d937 lui s2,0xd + 76b0: 3e800513 li a0,1000 + 76b4: 5b3010ef jal ra,9466 + 76b8: 71848613 addi a2,s1,1816 + 76bc: 18840593 addi a1,s0,392 + 76c0: 6ec90513 addi a0,s2,1772 # d6ec + 76c4: 502020ef jal ra,9bc6 + 76c8: b7e5 j 76b0 + 76ca: 2456 lhu a3,12(s0) + 76cc: 2430 lbu a2,10(s0) + 76ce: 340c lbu a1,9(s0) + 76d0: 2408 lbu a0,8(s0) + 76d2: 4801 li a6,0 + 76d4: 4785 li a5,1 + 76d6: 4701 li a4,0 + 76d8: 715000ef jal ra,85ec + 76dc: b39f806f j 214 <__riscv_restore_0> + +000076e0 : + 76e0: a001 j 76e0 + +000076e2 : + 76e2: beef07b7 lui a5,0xbeef0 + 76e6: e000e737 lui a4,0xe000e + 76ea: 08078793 addi a5,a5,128 # beef0080 <_eusrstack+0x9eee8080> + 76ee: c73c sw a5,72(a4) + 76f0: a001 j 76f0 + +000076f2

: + 76f2: ad7f82ef jal t0,1c8 <__riscv_save_10> + 76f6: 7169 addi sp,sp,-304 + 76f8: 4509 li a0,2 + 76fa: 7d0010ef jal ra,8eca + 76fe: 1f0010ef jal ra,88ee + 7702: 53b010ef jal ra,943c + 7706: 6511 lui a0,0x4 + 7708: 4585 li a1,1 + 770a: 0511 addi a0,a0,4 + 770c: 213010ef jal ra,911e + 7710: 40011437 lui s0,0x40011 + 7714: 20000793 li a5,512 + 7718: 448d li s1,3 + 771a: 80040513 addi a0,s0,-2048 # 40010800 <_eusrstack+0x20008800> + 771e: 80fc sh a5,16(sp) + 7720: 080c addi a1,sp,16 + 7722: 47e1 li a5,24 + 7724: ca26 sw s1,20(sp) + 7726: cc3e sw a5,24(sp) + 7728: 6ce010ef jal ra,8df6 + 772c: 40000793 li a5,1024 + 7730: 80040513 addi a0,s0,-2048 + 7734: 80fc sh a5,16(sp) + 7736: 080c addi a1,sp,16 + 7738: 4791 li a5,4 + 773a: ca26 sw s1,20(sp) + 773c: cc3e sw a5,24(sp) + 773e: 6b8010ef jal ra,8df6 + 7742: 67f1 lui a5,0x1c + 7744: 40014437 lui s0,0x40014 + 7748: 20078793 addi a5,a5,512 # 1c200 <_data_lma+0xdfa4> + 774c: 80040513 addi a0,s0,-2048 # 40013800 <_eusrstack+0x2000b800> + 7750: ce3e sw a5,28(sp) + 7752: 086c addi a1,sp,28 + 7754: 000c07b7 lui a5,0xc0 + 7758: d23e sw a5,36(sp) + 775a: d002 sw zero,32(sp) + 775c: 02011423 sh zero,40(sp) + 7760: 41d010ef jal ra,937c + 7764: 4585 li a1,1 + 7766: 80040513 addi a0,s0,-2048 + 776a: 4a3010ef jal ra,940c + 776e: 0000e537 lui a0,0xe + 7772: 97450513 addi a0,a0,-1676 # d974 + 7776: 450020ef jal ra,9bc6 + 777a: 200007b7 lui a5,0x20000 + 777e: 1f07a683 lw a3,496(a5) # 200001f0 + 7782: 0000c437 lui s0,0xc + 7786: 0000b4b7 lui s1,0xb + 778a: 0000e537 lui a0,0xe + 778e: 0e040613 addi a2,s0,224 # c0e0 <_exit+0xc88> + 7792: 66048593 addi a1,s1,1632 # b660 <_exit+0x208> + 7796: 98050513 addi a0,a0,-1664 # d980 + 779a: 42c020ef jal ra,9bc6 + 779e: 64e010ef jal ra,8dec + 77a2: 86aa mv a3,a0 + 77a4: 0000e537 lui a0,0xe + 77a8: 0e040613 addi a2,s0,224 + 77ac: 66048593 addi a1,s1,1632 + 77b0: 99c50513 addi a0,a0,-1636 # d99c + 77b4: 412020ef jal ra,9bc6 + 77b8: da3ff0ef jal ra,755a + 77bc: e9fff0ef jal ra,765a + 77c0: 86fff0ef jal ra,702e + 77c4: ba6fb0ef jal ra,2b6a + 77c8: 243010ef jal ra,920a + 77cc: 80a1ae23 sw a0,-2020(gp) # 2000020c + 77d0: 03400613 li a2,52 + 77d4: 4581 li a1,0 + 77d6: 94c18513 addi a0,gp,-1716 # 2000033c + 77da: a47f80ef jal ra,220 + 77de: 4501 li a0,0 + 77e0: deff80ef jal ra,5ce + 77e4: 4705 li a4,1 + 77e6: 20001a37 lui s4,0x20001 + 77ea: 82e18223 sb a4,-2012(gp) # 20000214 + 77ee: 4a81 li s5,0 + 77f0: 4b01 li s6,0 + 77f2: 0000ebb7 lui s7,0xe + 77f6: 0000ec37 lui s8,0xe + 77fa: 38ca0a13 addi s4,s4,908 # 2000138c <_ebss+0x20c> + 77fe: 400144b7 lui s1,0x40014 + 7802: 02000593 li a1,32 + 7806: 80048513 addi a0,s1,-2048 # 40013800 <_eusrstack+0x2000b800> + 780a: 429010ef jal ra,9432 + 780e: 4785 li a5,1 + 7810: 0ef51363 bne a0,a5,78f6 + 7814: 80048513 addi a0,s1,-2048 + 7818: 413010ef jal ra,942a + 781c: 01851493 slli s1,a0,0x18 + 7820: 84e1 srai s1,s1,0x18 + 7822: 04d00793 li a5,77 + 7826: 08f49163 bne s1,a5,78a8 + 782a: 0000b5b7 lui a1,0xb + 782e: 0000e537 lui a0,0xe + 7832: 0e040613 addi a2,s0,224 + 7836: 4ec58593 addi a1,a1,1260 # b4ec <_exit+0x94> + 783a: 9b850513 addi a0,a0,-1608 # d9b8 + 783e: 388020ef jal ra,9bc6 + 7842: 0000e637 lui a2,0xe + 7846: 0b400593 li a1,180 + 784a: 8756 mv a4,s5 + 784c: 87da mv a5,s6 + 784e: 9d460613 addi a2,a2,-1580 # d9d4 + 7852: 1068 addi a0,sp,44 + 7854: 612020ef jal ra,9e66 + 7858: 4585 li a1,1 + 785a: 1068 addi a0,sp,44 + 785c: e50fa0ef jal ra,1eac + 7860: 04300793 li a5,67 + 7864: 08f49963 bne s1,a5,78f6 + 7868: 200004b7 lui s1,0x20000 + 786c: 41048493 addi s1,s1,1040 # 20000410 + 7870: 4981 li s3,0 + 7872: 4ca1 li s9,8 + 7874: 00048783 lb a5,0(s1) + 7878: c395 beqz a5,789c + 787a: 58d4 lw a3,52(s1) + 787c: c285 beqz a3,789c + 787e: 0304c703 lbu a4,48(s1) + 7882: 8626 mv a2,s1 + 7884: 85ce mv a1,s3 + 7886: a7cb8513 addi a0,s7,-1412 # da7c + 788a: 33c020ef jal ra,9bc6 + 788e: 4641 li a2,16 + 7890: 02048593 addi a1,s1,32 + 7894: 83cc0513 addi a0,s8,-1988 # d83c + 7898: b4bf80ef jal ra,3e2 + 789c: 0985 addi s3,s3,1 + 789e: 03848493 addi s1,s1,56 + 78a2: fd9999e3 bne s3,s9,7874 + 78a6: a881 j 78f6 + 78a8: 03000793 li a5,48 + 78ac: 02f49263 bne s1,a5,78d0 + 78b0: 0000b5b7 lui a1,0xb + 78b4: 0000e537 lui a0,0xe + 78b8: 0e040613 addi a2,s0,224 + 78bc: 4ec58593 addi a1,a1,1260 # b4ec <_exit+0x94> + 78c0: 9e450513 addi a0,a0,-1564 # d9e4 + 78c4: 302020ef jal ra,9bc6 + 78c8: 4501 li a0,0 + 78ca: d05f80ef jal ra,5ce + 78ce: bf49 j 7860 + 78d0: 04600793 li a5,70 + 78d4: 0af49e63 bne s1,a5,7990 + 78d8: 0000b5b7 lui a1,0xb + 78dc: 0000e537 lui a0,0xe + 78e0: 0e040613 addi a2,s0,224 + 78e4: 4ec58593 addi a1,a1,1260 # b4ec <_exit+0x94> + 78e8: a0850513 addi a0,a0,-1528 # da08 + 78ec: 2da020ef jal ra,9bc6 + 78f0: 4505 li a0,1 + 78f2: cddf80ef jal ra,5ce + 78f6: 00f10693 addi a3,sp,15 + 78fa: 00e10613 addi a2,sp,14 + 78fe: 00d10593 addi a1,sp,13 + 7902: 1068 addi a0,sp,44 + 7904: fdafa0ef jal ra,20de + 7908: cd31 beqz a0,7964 + 790a: 5656 lw a2,116(sp) + 790c: 0000e537 lui a0,0xe + 7910: 18ac addi a1,sp,120 + 7912: ab850513 addi a0,a0,-1352 # dab8 + 7916: acdf80ef jal ra,3e2 + 791a: 00f10783 lb a5,15(sp) + 791e: 00d10683 lb a3,13(sp) + 7922: 94c18713 addi a4,gp,-1716 # 2000033c + 7926: b73e sh a5,42(a4) + 7928: a376 sh a3,6(a4) + 792a: 00e10703 lb a4,14(sp) + 792e: 0000b5b7 lui a1,0xb + 7932: 0000e537 lui a0,0xe + 7936: 0e040613 addi a2,s0,224 + 793a: 4ec58593 addi a1,a1,1260 # b4ec <_exit+0x94> + 793e: ac450513 addi a0,a0,-1340 # dac4 + 7942: 284020ef jal ra,9bc6 + 7946: 1068 addi a0,sp,44 + 7948: e9cfa0ef jal ra,1fe4 + 794c: de4a4783 lbu a5,-540(s4) + 7950: c781 beqz a5,7958 + 7952: 1068 addi a0,sp,44 + 7954: db5fa0ef jal ra,2708 + 7958: 10400613 li a2,260 + 795c: 4581 li a1,0 + 795e: 1068 addi a0,sp,44 + 7960: 8c1f80ef jal ra,220 + 7964: 2ca1 jal 7bbc + 7966: 86aa mv a3,a0 + 7968: cd09 beqz a0,7982 + 796a: 0000b5b7 lui a1,0xb + 796e: 0000e537 lui a0,0xe + 7972: 0e040613 addi a2,s0,224 + 7976: 49458593 addi a1,a1,1172 # b494 <_exit+0x3c> + 797a: b0050513 addi a0,a0,-1280 # db00 + 797e: 248020ef jal ra,9bc6 + 7982: 001a8793 addi a5,s5,1 + 7986: 0157b733 sltu a4,a5,s5 + 798a: 9b3a add s6,s6,a4 + 798c: 8abe mv s5,a5 + 798e: bd85 j 77fe + 7990: 04e00793 li a5,78 + 7994: 00f49563 bne s1,a5,799e + 7998: a79ff0ef jal ra,7410 + 799c: bfa9 j 78f6 + 799e: 04400793 li a5,68 + 79a2: eaf49fe3 bne s1,a5,7860 + 79a6: 065010ef jal ra,920a + 79aa: 0000e637 lui a2,0xe + 79ae: d62a sw a0,44(sp) + 79b0: 8756 mv a4,s5 + 79b2: 87da mv a5,s6 + 79b4: a2c60613 addi a2,a2,-1492 # da2c + 79b8: 0b400593 li a1,180 + 79bc: 03210513 addi a0,sp,50 + 79c0: 02011823 sh zero,48(sp) + 79c4: 4a2020ef jal ra,9e66 + 79c8: 0000e537 lui a0,0xe + 79cc: a5050513 addi a0,a0,-1456 # da50 + 79d0: 1f6020ef jal ra,9bc6 + 79d4: 20000537 lui a0,0x20000 + 79d8: 106c addi a1,sp,44 + 79da: 5d050513 addi a0,a0,1488 # 200005d0 + 79de: ed2f90ef jal ra,10b0 + 79e2: bf11 j 78f6 + +000079e4 : + 79e4: 80df82ef jal t0,1f0 <__riscv_save_0> + 79e8: 82e18783 lb a5,-2002(gp) # 2000021e + 79ec: c385 beqz a5,7a0c + 79ee: 86aa mv a3,a0 + 79f0: 0000e637 lui a2,0xe + 79f4: 0000c5b7 lui a1,0xc + 79f8: 0000e537 lui a0,0xe + 79fc: bcc60613 addi a2,a2,-1076 # dbcc + 7a00: 18858593 addi a1,a1,392 # c188 <_exit+0xd30> + 7a04: bd450513 addi a0,a0,-1068 # dbd4 + 7a08: 1be020ef jal ra,9bc6 + 7a0c: 0000e437 lui s0,0xe + 7a10: bf440513 addi a0,s0,-1036 # dbf4 + 7a14: 1b2020ef jal ra,9bc6 + 7a18: 4505 li a0,1 + 7a1a: 24d010ef jal ra,9466 + 7a1e: bfcd j 7a10 + +00007a20 : + 7a20: fb6f82ef jal t0,1d6 <__riscv_save_4> + 7a24: 1101 addi sp,sp,-32 + 7a26: 820187a3 sb zero,-2001(gp) # 2000021f + 7a2a: 4585 li a1,1 + 7a2c: 00420537 lui a0,0x420 + 7a30: 82018723 sb zero,-2002(gp) # 2000021e + 7a34: c002 sw zero,0(sp) + 7a36: c202 sw zero,4(sp) + 7a38: c402 sw zero,8(sp) + 7a3a: c602 sw zero,12(sp) + 7a3c: c802 sw zero,16(sp) + 7a3e: ca02 sw zero,20(sp) + 7a40: cc02 sw zero,24(sp) + 7a42: 00011e23 sh zero,28(sp) + 7a46: 6f6010ef jal ra,913c + 7a4a: 6505 lui a0,0x1 + 7a4c: 4585 li a1,1 + 7a4e: 05c50513 addi a0,a0,92 # 105c + 7a52: 6cc010ef jal ra,911e + 7a56: 40011437 lui s0,0x40011 + 7a5a: 49c1 li s3,16 + 7a5c: 4a0d li s4,3 + 7a5e: 47c1 li a5,16 + 7a60: 858a mv a1,sp + 7a62: 80040513 addi a0,s0,-2048 # 40010800 <_eusrstack+0x20008800> + 7a66: 807c sh a5,0(sp) + 7a68: c44e sw s3,8(sp) + 7a6a: c252 sw s4,4(sp) + 7a6c: 38a010ef jal ra,8df6 + 7a70: 4961 li s2,24 + 7a72: 02000793 li a5,32 + 7a76: 858a mv a1,sp + 7a78: 80040513 addi a0,s0,-2048 + 7a7c: 807c sh a5,0(sp) + 7a7e: c44a sw s2,8(sp) + 7a80: c252 sw s4,4(sp) + 7a82: 374010ef jal ra,8df6 + 7a86: 4491 li s1,4 + 7a88: 04000793 li a5,64 + 7a8c: 858a mv a1,sp + 7a8e: 80040513 addi a0,s0,-2048 + 7a92: 807c sh a5,0(sp) + 7a94: c426 sw s1,8(sp) + 7a96: 360010ef jal ra,8df6 + 7a9a: 08000793 li a5,128 + 7a9e: 858a mv a1,sp + 7aa0: 80040513 addi a0,s0,-2048 + 7aa4: 807c sh a5,0(sp) + 7aa6: 40012437 lui s0,0x40012 + 7aaa: c44a sw s2,8(sp) + 7aac: c252 sw s4,4(sp) + 7aae: 348010ef jal ra,8df6 + 7ab2: 4785 li a5,1 + 7ab4: 858a mv a1,sp + 7ab6: 80040513 addi a0,s0,-2048 # 40011800 <_eusrstack+0x20009800> + 7aba: 807c sh a5,0(sp) + 7abc: c44e sw s3,8(sp) + 7abe: 338010ef jal ra,8df6 + 7ac2: 4789 li a5,2 + 7ac4: 858a mv a1,sp + 7ac6: 80040513 addi a0,s0,-2048 + 7aca: 807c sh a5,0(sp) + 7acc: c426 sw s1,8(sp) + 7ace: 328010ef jal ra,8df6 + 7ad2: 858a mv a1,sp + 7ad4: 80040513 addi a0,s0,-2048 + 7ad8: 8064 sh s1,0(sp) + 7ada: c426 sw s1,8(sp) + 7adc: 31a010ef jal ra,8df6 + 7ae0: 47a1 li a5,8 + 7ae2: 858a mv a1,sp + 7ae4: 80040513 addi a0,s0,-2048 + 7ae8: 807c sh a5,0(sp) + 7aea: c44e sw s3,8(sp) + 7aec: 30a010ef jal ra,8df6 + 7af0: 010407b7 lui a5,0x1040 + 7af4: c63e sw a5,12(sp) + 7af6: 020007b7 lui a5,0x2000 + 7afa: ca3e sw a5,20(sp) + 7afc: 006c addi a1,sp,12 + 7afe: 479d li a5,7 + 7b00: 40013537 lui a0,0x40013 + 7b04: 86fc sh a5,28(sp) + 7b06: cc4a sw s2,24(sp) + 7b08: c802 sw zero,16(sp) + 7b0a: 009010ef jal ra,9312 + 7b0e: 4605 li a2,1 + 7b10: 80040513 addi a0,s0,-2048 + 7b14: 45a1 li a1,8 + 7b16: 3aa010ef jal ra,8ec0 + 7b1a: 4585 li a1,1 + 7b1c: 40013537 lui a0,0x40013 + 7b20: 031010ef jal ra,9350 + 7b24: 6105 addi sp,sp,32 + 7b26: ee4f806f j 20a <__riscv_restore_4> + +00007b2a : + 7b2a: eacf82ef jal t0,1d6 <__riscv_save_4> + 7b2e: 84aa mv s1,a0 + 7b30: 40011537 lui a0,0x40011 + 7b34: 892e mv s2,a1 + 7b36: 8a32 mv s4,a2 + 7b38: 45c1 li a1,16 + 7b3a: 4601 li a2,0 + 7b3c: 80050513 addi a0,a0,-2048 # 40010800 <_eusrstack+0x20008800> + 7b40: 380010ef jal ra,8ec0 + 7b44: 4401 li s0,0 + 7b46: 01441c63 bne s0,s4,7b5e + 7b4a: 40011537 lui a0,0x40011 + 7b4e: 4605 li a2,1 + 7b50: 45c1 li a1,16 + 7b52: 80050513 addi a0,a0,-2048 # 40010800 <_eusrstack+0x20008800> + 7b56: 36a010ef jal ra,8ec0 + 7b5a: eb0f806f j 20a <__riscv_restore_4> + 7b5e: 0ff00993 li s3,255 + 7b62: 00090663 beqz s2,7b6e + 7b66: 008907b3 add a5,s2,s0 + 7b6a: 0007c983 lbu s3,0(a5) # 2000000 <_data_lma+0x1ff1da4> + 7b6e: 4589 li a1,2 + 7b70: 40013537 lui a0,0x40013 + 7b74: 7fe010ef jal ra,9372 + 7b78: d97d beqz a0,7b6e + 7b7a: 85ce mv a1,s3 + 7b7c: 40013537 lui a0,0x40013 + 7b80: 7ea010ef jal ra,936a + 7b84: 4585 li a1,1 + 7b86: 40013537 lui a0,0x40013 + 7b8a: 7e8010ef jal ra,9372 + 7b8e: d97d beqz a0,7b84 + 7b90: 40013537 lui a0,0x40013 + 7b94: 7da010ef jal ra,936e + 7b98: c481 beqz s1,7ba0 + 7b9a: 008487b3 add a5,s1,s0 + 7b9e: a388 sb a0,0(a5) + 7ba0: 0405 addi s0,s0,1 + 7ba2: b755 j 7b46 + +00007ba4 : + 7ba4: e4cf82ef jal t0,1f0 <__riscv_save_0> + 7ba8: 862e mv a2,a1 + 7baa: 85aa mv a1,a0 + 7bac: 4501 li a0,0 + 7bae: f7dff0ef jal ra,7b2a + 7bb2: e62f806f j 214 <__riscv_restore_0> + +00007bb6 : + 7bb6: 82a18723 sb a0,-2002(gp) # 2000021e + 7bba: 8082 ret + +00007bbc : + 7bbc: 8301a503 lw a0,-2000(gp) # 20000220 + 7bc0: 8082 ret + +00007bc2 : + 7bc2: e14f82ef jal t0,1d6 <__riscv_save_4> + 7bc6: 84aa mv s1,a0 + 7bc8: 400129b7 lui s3,0x40012 + 7bcc: 4505 li a0,1 + 7bce: 8a2e mv s4,a1 + 7bd0: 8432 mv s0,a2 + 7bd2: 4901 li s2,0 + 7bd4: 093010ef jal ra,9466 + 7bd8: 80098993 addi s3,s3,-2048 # 40011800 <_eusrstack+0x20009800> + 7bdc: 00990763 beq s2,s1,7bea + 7be0: 4589 li a1,2 + 7be2: 854e mv a0,s3 + 7be4: 2d2010ef jal ra,8eb6 + 7be8: ed09 bnez a0,7c02 + 7bea: 40012537 lui a0,0x40012 + 7bee: 4589 li a1,2 + 7bf0: 80050513 addi a0,a0,-2048 # 40011800 <_eusrstack+0x20009800> + 7bf4: 2c2010ef jal ra,8eb6 + 7bf8: e911 bnez a0,7c0c + 7bfa: 4405 li s0,1 + 7bfc: 8522 mv a0,s0 + 7bfe: e0cf806f j 20a <__riscv_restore_4> + 7c02: 4529 li a0,10 + 7c04: 063010ef jal ra,9466 + 7c08: 0905 addi s2,s2,1 + 7c0a: bfc9 j 7bdc + 7c0c: 0000e637 lui a2,0xe + 7c10: 0000e537 lui a0,0xe + 7c14: 8726 mv a4,s1 + 7c16: 86d2 mv a3,s4 + 7c18: bcc60613 addi a2,a2,-1076 # dbcc + 7c1c: cc01 beqz s0,7c34 + 7c1e: 0000c5b7 lui a1,0xc + 7c22: 18858593 addi a1,a1,392 # c188 <_exit+0xd30> + 7c26: e2c50513 addi a0,a0,-468 # de2c + 7c2a: 79d010ef jal ra,9bc6 + 7c2e: 4551 li a0,20 + 7c30: db5ff0ef jal ra,79e4 + 7c34: 0000b5b7 lui a1,0xb + 7c38: 49458593 addi a1,a1,1172 # b494 <_exit+0x3c> + 7c3c: e2c50513 addi a0,a0,-468 + 7c40: 787010ef jal ra,9bc6 + 7c44: bf65 j 7bfc + +00007c46 : + 7c46: daaf82ef jal t0,1f0 <__riscv_save_0> + 7c4a: 4529 li a0,10 + 7c4c: 01b010ef jal ra,9466 + 7c50: 40012437 lui s0,0x40012 + 7c54: 4601 li a2,0 + 7c56: 45a1 li a1,8 + 7c58: 80040513 addi a0,s0,-2048 # 40011800 <_eusrstack+0x20009800> + 7c5c: 264010ef jal ra,8ec0 + 7c60: 4551 li a0,20 + 7c62: 005010ef jal ra,9466 + 7c66: 80040513 addi a0,s0,-2048 + 7c6a: 4605 li a2,1 + 7c6c: 45a1 li a1,8 + 7c6e: 252010ef jal ra,8ec0 + 7c72: 0000e637 lui a2,0xe + 7c76: 0000b5b7 lui a1,0xb + 7c7a: 0000e537 lui a0,0xe + 7c7e: bcc60613 addi a2,a2,-1076 # dbcc + 7c82: 49458593 addi a1,a1,1172 # b494 <_exit+0x3c> + 7c86: ce050513 addi a0,a0,-800 # dce0 + 7c8a: 73d010ef jal ra,9bc6 + 7c8e: 4529 li a0,10 + 7c90: 7d6010ef jal ra,9466 + 7c94: 0000e5b7 lui a1,0xe + 7c98: 6505 lui a0,0x1 + 7c9a: 4605 li a2,1 + 7c9c: cfc58593 addi a1,a1,-772 # dcfc + 7ca0: 38850513 addi a0,a0,904 # 1388 + 7ca4: f1fff0ef jal ra,7bc2 + 7ca8: d6cf806f j 214 <__riscv_restore_0> + +00007cac : + 7cac: d1cf82ef jal t0,1c8 <__riscv_save_10> + 7cb0: 6485 lui s1,0x1 + 7cb2: 8b2e mv s6,a1 + 7cb4: 4401 li s0,0 + 7cb6: 4901 li s2,0 + 7cb8: 38848493 addi s1,s1,904 # 1388 + 7cbc: 4b85 li s7,1 + 7cbe: 0000eab7 lui s5,0xe + 7cc2: 0000ba37 lui s4,0xb + 7cc6: 0000e9b7 lui s3,0xe + 7cca: 4c25 li s8,9 + 7ccc: 864a mv a2,s2 + 7cce: 85da mv a1,s6 + 7cd0: 8526 mv a0,s1 + 7cd2: ef1ff0ef jal ra,7bc2 + 7cd6: 03750263 beq a0,s7,7cfa + 7cda: 86a2 mv a3,s0 + 7cdc: bcca8613 addi a2,s5,-1076 # dbcc + 7ce0: 494a0593 addi a1,s4,1172 # b494 <_exit+0x3c> + 7ce4: e6098513 addi a0,s3,-416 # de60 + 7ce8: 6df010ef jal ra,9bc6 + 7cec: 4529 li a0,10 + 7cee: 778010ef jal ra,9466 + 7cf2: 0405 addi s0,s0,1 + 7cf4: 47a9 li a5,10 + 7cf6: 00f41463 bne s0,a5,7cfe + 7cfa: d06f806f j 200 <__riscv_restore_10> + 7cfe: fd8417e3 bne s0,s8,7ccc + 7d02: 4905 li s2,1 + 7d04: b7e1 j 7ccc + +00007d06 : + 7d06: cc2f82ef jal t0,1c8 <__riscv_save_10> + 7d0a: 89aa mv s3,a0 + 7d0c: 8a2e mv s4,a1 + 7d0e: 6505 lui a0,0x1 + 7d10: 0000e5b7 lui a1,0xe + 7d14: 1141 addi sp,sp,-16 + 7d16: 8ab2 mv s5,a2 + 7d18: f4458593 addi a1,a1,-188 # df44 + 7d1c: 4605 li a2,1 + 7d1e: 38850513 addi a0,a0,904 # 1388 + 7d22: ea1ff0ef jal ra,7bc2 + 7d26: 82e18783 lb a5,-2002(gp) # 2000021e + 7d2a: e3a1 bnez a5,7d6a + 7d2c: 47b5 li a5,13 + 7d2e: 8656 mv a2,s5 + 7d30: 805c sb a5,0(sp) + 7d32: 85d2 mv a1,s4 + 7d34: 0089d793 srli a5,s3,0x8 + 7d38: 00310513 addi a0,sp,3 + 7d3c: 80dc sb a5,1(sp) + 7d3e: 01310123 sb s3,2(sp) + 7d42: 411010ef jal ra,9952 + 7d46: 003a8593 addi a1,s5,3 + 7d4a: 850a mv a0,sp + 7d4c: e59ff0ef jal ra,7ba4 + 7d50: 0000e5b7 lui a1,0xe + 7d54: 6505 lui a0,0x1 + 7d56: 4601 li a2,0 + 7d58: f5858593 addi a1,a1,-168 # df58 + 7d5c: 38850513 addi a0,a0,904 # 1388 + 7d60: e63ff0ef jal ra,7bc2 + 7d64: 0141 addi sp,sp,16 + 7d66: c9af806f j 200 <__riscv_restore_10> + 7d6a: 0000e4b7 lui s1,0xe + 7d6e: 0000b937 lui s2,0xb + 7d72: 0000e537 lui a0,0xe + 7d76: 86ce mv a3,s3 + 7d78: bcc48613 addi a2,s1,-1076 # dbcc + 7d7c: 4ec90593 addi a1,s2,1260 # b4ec <_exit+0x94> + 7d80: f6c50513 addi a0,a0,-148 # df6c + 7d84: 643010ef jal ra,9bc6 + 7d88: 8452 mv s0,s4 + 7d8a: 014a8b33 add s6,s5,s4 + 7d8e: 0000ebb7 lui s7,0xe + 7d92: f9640de3 beq s0,s6,7d2c + 7d96: 2014 lbu a3,0(s0) + 7d98: bcc48613 addi a2,s1,-1076 + 7d9c: 4ec90593 addi a1,s2,1260 + 7da0: f94b8513 addi a0,s7,-108 # df94 + 7da4: 623010ef jal ra,9bc6 + 7da8: 0405 addi s0,s0,1 + 7daa: b7e5 j 7d92 + +00007dac : + 7dac: c2af82ef jal t0,1d6 <__riscv_save_4> + 7db0: 89aa mv s3,a0 + 7db2: 842e mv s0,a1 + 7db4: 6505 lui a0,0x1 + 7db6: 0000e5b7 lui a1,0xe + 7dba: 1101 addi sp,sp,-32 + 7dbc: 84b2 mv s1,a2 + 7dbe: c4858593 addi a1,a1,-952 # dc48 + 7dc2: 4605 li a2,1 + 7dc4: 38850513 addi a0,a0,904 # 1388 + 7dc8: dfbff0ef jal ra,7bc2 + 7dcc: 82e18783 lb a5,-2002(gp) # 2000021e + 7dd0: 0000ea37 lui s4,0xe + 7dd4: 82e18913 addi s2,gp,-2002 # 2000021e + 7dd8: 0000bab7 lui s5,0xb + 7ddc: cf81 beqz a5,7df4 + 7dde: 0000e537 lui a0,0xe + 7de2: 86ce mv a3,s3 + 7de4: bcca0613 addi a2,s4,-1076 # dbcc + 7de8: 4eca8593 addi a1,s5,1260 # b4ec <_exit+0x94> + 7dec: c5c50513 addi a0,a0,-932 # dc5c + 7df0: 5d7010ef jal ra,9bc6 + 7df4: 4639 li a2,14 + 7df6: 4581 li a1,0 + 7df8: 00210513 addi a0,sp,2 + 7dfc: c24f80ef jal ra,220 + 7e00: 47f5 li a5,29 + 7e02: 805c sb a5,0(sp) + 7e04: 0089d793 srli a5,s3,0x8 + 7e08: 80dc sb a5,1(sp) + 7e0a: 00090783 lb a5,0(s2) + 7e0e: c802 sw zero,16(sp) + 7e10: ca02 sw zero,20(sp) + 7e12: cc02 sw zero,24(sp) + 7e14: ce02 sw zero,28(sp) + 7e16: 01310123 sb s3,2(sp) + 7e1a: cb99 beqz a5,7e30 + 7e1c: 0000e537 lui a0,0xe + 7e20: bcca0613 addi a2,s4,-1076 + 7e24: 4eca8593 addi a1,s5,1260 + 7e28: c8050513 addi a0,a0,-896 # dc80 + 7e2c: 59b010ef jal ra,9bc6 + 7e30: 00448613 addi a2,s1,4 + 7e34: 858a mv a1,sp + 7e36: 0808 addi a0,sp,16 + 7e38: cf3ff0ef jal ra,7b2a + 7e3c: 0000e537 lui a0,0xe + 7e40: bcca0613 addi a2,s4,-1076 + 7e44: 4eca8593 addi a1,s5,1260 + 7e48: c9c50513 addi a0,a0,-868 # dc9c + 7e4c: 57b010ef jal ra,9bc6 + 7e50: 8626 mv a2,s1 + 7e52: 084c addi a1,sp,20 + 7e54: 8522 mv a0,s0 + 7e56: 2fd010ef jal ra,9952 + 7e5a: 00090783 lb a5,0(s2) + 7e5e: c791 beqz a5,7e6a + 7e60: 94a2 add s1,s1,s0 + 7e62: 0000e937 lui s2,0xe + 7e66: 00941f63 bne s0,s1,7e84 + 7e6a: 0000e5b7 lui a1,0xe + 7e6e: 6505 lui a0,0x1 + 7e70: 4601 li a2,0 + 7e72: cb458593 addi a1,a1,-844 # dcb4 + 7e76: 38850513 addi a0,a0,904 # 1388 + 7e7a: d49ff0ef jal ra,7bc2 + 7e7e: 6105 addi sp,sp,32 + 7e80: b8af806f j 20a <__riscv_restore_4> + 7e84: 2014 lbu a3,0(s0) + 7e86: bcca0613 addi a2,s4,-1076 + 7e8a: 4eca8593 addi a1,s5,1260 + 7e8e: cc890513 addi a0,s2,-824 # dcc8 + 7e92: 535010ef jal ra,9bc6 + 7e96: 0405 addi s0,s0,1 + 7e98: b7f9 j 7e66 + +00007e9a : + 7e9a: b56f82ef jal t0,1f0 <__riscv_save_0> + 7e9e: 1141 addi sp,sp,-16 + 7ea0: 842a mv s0,a0 + 7ea2: 4605 li a2,1 + 7ea4: 00f10593 addi a1,sp,15 + 7ea8: 73600513 li a0,1846 + 7eac: 000107a3 sb zero,15(sp) + 7eb0: efdff0ef jal ra,7dac + 7eb4: 8798 lbu a4,15(sp) + 7eb6: 4685 li a3,1 + 7eb8: 0fb77793 andi a5,a4,251 + 7ebc: 00d40463 beq s0,a3,7ec4 + 7ec0: 00476793 ori a5,a4,4 + 7ec4: 00f10593 addi a1,sp,15 + 7ec8: 4605 li a2,1 + 7eca: 73600513 li a0,1846 + 7ece: 87dc sb a5,15(sp) + 7ed0: e37ff0ef jal ra,7d06 + 7ed4: 0141 addi sp,sp,16 + 7ed6: b3ef806f j 214 <__riscv_restore_0> + +00007eda : + 7eda: b16f82ef jal t0,1f0 <__riscv_save_0> + 7ede: 84aa mv s1,a0 + 7ee0: 892e mv s2,a1 + 7ee2: 6505 lui a0,0x1 + 7ee4: 0000e5b7 lui a1,0xe + 7ee8: 1141 addi sp,sp,-16 + 7eea: 8432 mv s0,a2 + 7eec: ef858593 addi a1,a1,-264 # def8 + 7ef0: 4605 li a2,1 + 7ef2: 38850513 addi a0,a0,904 # 1388 + 7ef6: ccdff0ef jal ra,7bc2 + 7efa: 82e18783 lb a5,-2002(gp) # 2000021e + 7efe: c385 beqz a5,7f1e + 7f00: 0000e637 lui a2,0xe + 7f04: 0000b5b7 lui a1,0xb + 7f08: 0000e537 lui a0,0xe + 7f0c: 86a6 mv a3,s1 + 7f0e: bcc60613 addi a2,a2,-1076 # dbcc + 7f12: 4ec58593 addi a1,a1,1260 # b4ec <_exit+0x94> + 7f16: f0c50513 addi a0,a0,-244 # df0c + 7f1a: 4ad010ef jal ra,9bc6 + 7f1e: 8622 mv a2,s0 + 7f20: 85ca mv a1,s2 + 7f22: 00110513 addi a0,sp,1 + 7f26: 8044 sb s1,0(sp) + 7f28: 22b010ef jal ra,9952 + 7f2c: 858a mv a1,sp + 7f2e: 00140613 addi a2,s0,1 + 7f32: 852e mv a0,a1 + 7f34: bf7ff0ef jal ra,7b2a + 7f38: 8088 lbu a0,1(sp) + 7f3a: 47a9 li a5,10 + 7f3c: 00e57413 andi s0,a0,14 + 7f40: 0287ee63 bltu a5,s0,7f7c + 7f44: 4785 li a5,1 + 7f46: 008797b3 sll a5,a5,s0 + 7f4a: 5407f713 andi a4,a5,1344 + 7f4e: eb09 bnez a4,7f60 + 7f50: 0817f513 andi a0,a5,129 + 7f54: 00a03533 snez a0,a0 + 7f58: 40a00533 neg a0,a0 + 7f5c: 0ff57413 andi s0,a0,255 + 7f60: 0000e5b7 lui a1,0xe + 7f64: 6505 lui a0,0x1 + 7f66: 4601 li a2,0 + 7f68: f3058593 addi a1,a1,-208 # df30 + 7f6c: 38850513 addi a0,a0,904 # 1388 + 7f70: c53ff0ef jal ra,7bc2 + 7f74: 8522 mv a0,s0 + 7f76: 0141 addi sp,sp,16 + 7f78: a9cf806f j 214 <__riscv_restore_0> + 7f7c: 4401 li s0,0 + 7f7e: b7cd j 7f60 + +00007f80 : + 7f80: a40f82ef jal t0,1c0 <__riscv_save_12> + 7f84: 8b2a mv s6,a0 + 7f86: 8bae mv s7,a1 + 7f88: 8c32 mv s8,a2 + 7f8a: 4485 li s1,1 + 7f8c: 0000e937 lui s2,0xe + 7f90: 0000bd37 lui s10,0xb + 7f94: 0000edb7 lui s11,0xe + 7f98: 0000bab7 lui s5,0xb + 7f9c: 0000ea37 lui s4,0xe + 7fa0: 49a9 li s3,10 + 7fa2: 8662 mv a2,s8 + 7fa4: 85de mv a1,s7 + 7fa6: 855a mv a0,s6 + 7fa8: f33ff0ef jal ra,7eda + 7fac: 82e18783 lb a5,-2002(gp) # 2000021e + 7fb0: 842a mv s0,a0 + 7fb2: cb91 beqz a5,7fc6 + 7fb4: 86aa mv a3,a0 + 7fb6: bcc90613 addi a2,s2,-1076 # dbcc + 7fba: 660d0593 addi a1,s10,1632 # b660 <_exit+0x208> + 7fbe: e88d8513 addi a0,s11,-376 # de88 + 7fc2: 405010ef jal ra,9bc6 + 7fc6: cc15 beqz s0,8002 + 7fc8: 8726 mv a4,s1 + 7fca: 86a2 mv a3,s0 + 7fcc: bcc90613 addi a2,s2,-1076 + 7fd0: 494a8593 addi a1,s5,1172 # b494 <_exit+0x3c> + 7fd4: ea0a0513 addi a0,s4,-352 # dea0 + 7fd8: 0485 addi s1,s1,1 + 7fda: 3ed010ef jal ra,9bc6 + 7fde: fd3492e3 bne s1,s3,7fa2 + 7fe2: 0000c5b7 lui a1,0xc + 7fe6: 0000e537 lui a0,0xe + 7fea: 86a2 mv a3,s0 + 7fec: bcc90613 addi a2,s2,-1076 + 7ff0: 18858593 addi a1,a1,392 # c188 <_exit+0xd30> + 7ff4: ed050513 addi a0,a0,-304 # ded0 + 7ff8: 3cf010ef jal ra,9bc6 + 7ffc: 4555 li a0,21 + 7ffe: 9e7ff0ef jal ra,79e4 + 8002: 9faf806f j 1fc <__riscv_restore_12> + +00008006 : + 8006: 9eaf82ef jal t0,1f0 <__riscv_save_0> + 800a: 1141 addi sp,sp,-16 + 800c: 87c8 sb a0,15(sp) + 800e: 00f10593 addi a1,sp,15 + 8012: 4605 li a2,1 + 8014: 08000513 li a0,128 + 8018: f69ff0ef jal ra,7f80 + 801c: 0141 addi sp,sp,16 + 801e: 9f6f806f j 214 <__riscv_restore_0> + +00008022 : + 8022: 9cef82ef jal t0,1f0 <__riscv_save_0> + 8026: 67200713 li a4,1650 + 802a: 1141 addi sp,sp,-16 + 802c: 4781 li a5,0 + 802e: 04e50263 beq a0,a4,8072 + 8032: 6d600713 li a4,1750 + 8036: 4785 li a5,1 + 8038: 02e50d63 beq a0,a4,8072 + 803c: 73a00713 li a4,1850 + 8040: 4789 li a5,2 + 8042: 02e50863 beq a0,a4,8072 + 8046: 6705 lui a4,0x1 + 8048: 8fc70693 addi a3,a4,-1796 # 8fc <__stack_size+0xfc> + 804c: 478d li a5,3 + 804e: 02d50263 beq a0,a3,8072 + 8052: 9c470693 addi a3,a4,-1596 + 8056: 4791 li a5,4 + 8058: 00d50d63 beq a0,a3,8072 + 805c: b2270693 addi a3,a4,-1246 + 8060: 4795 li a5,5 + 8062: 00d50863 beq a0,a3,8072 + 8066: c1c70713 addi a4,a4,-996 + 806a: 479d li a5,7 + 806c: 00e51363 bne a0,a4,8072 + 8070: 4799 li a5,6 + 8072: 865c sb a5,12(sp) + 8074: 3e800793 li a5,1000 + 8078: 02f585b3 mul a1,a1,a5 + 807c: 6791 lui a5,0x4 + 807e: d0978793 addi a5,a5,-759 # 3d09 + 8082: 4611 li a2,4 + 8084: 09700513 li a0,151 + 8088: 02f5d5b3 divu a1,a1,a5 + 808c: 0105d793 srli a5,a1,0x10 + 8090: 86dc sb a5,13(sp) + 8092: 00859793 slli a5,a1,0x8 + 8096: 05c2 slli a1,a1,0x10 + 8098: 81c1 srli a1,a1,0x10 + 809a: 81a1 srli a1,a1,0x8 + 809c: 8ddd or a1,a1,a5 + 809e: 876c sh a1,14(sp) + 80a0: 006c addi a1,sp,12 + 80a2: edfff0ef jal ra,7f80 + 80a6: 0141 addi sp,sp,16 + 80a8: 96cf806f j 214 <__riscv_restore_0> + +000080ac : + 80ac: 944f82ef jal t0,1f0 <__riscv_save_0> + 80b0: 1141 addi sp,sp,-16 + 80b2: 87c8 sb a0,15(sp) + 80b4: 00f10593 addi a1,sp,15 + 80b8: 4605 li a2,1 + 80ba: 08900513 li a0,137 + 80be: ec3ff0ef jal ra,7f80 + 80c2: 0141 addi sp,sp,16 + 80c4: 950f806f j 214 <__riscv_restore_0> + +000080c8 : + 80c8: 928f82ef jal t0,1f0 <__riscv_save_0> + 80cc: 1141 addi sp,sp,-16 + 80ce: 87c8 sb a0,15(sp) + 80d0: 00f10593 addi a1,sp,15 + 80d4: 4605 li a2,1 + 80d6: 09d00513 li a0,157 + 80da: ea7ff0ef jal ra,7f80 + 80de: 0141 addi sp,sp,16 + 80e0: 934f806f j 214 <__riscv_restore_0> + +000080e4 : + 80e4: 90cf82ef jal t0,1f0 <__riscv_save_0> + 80e8: 35a4f7b7 lui a5,0x35a4f + 80ec: 90078793 addi a5,a5,-1792 # 35a4e900 <_eusrstack+0x15a46900> + 80f0: 1141 addi sp,sp,-16 + 80f2: 00a7ff63 bgeu a5,a0,8110 + 80f6: 77fd lui a5,0xfffff + 80f8: 9e178793 addi a5,a5,-1567 # ffffe9e1 <_eusrstack+0xdfff69e1> + 80fc: 867c sh a5,12(sp) + 80fe: 006c addi a1,sp,12 + 8100: 4609 li a2,2 + 8102: 09800513 li a0,152 + 8106: e7bff0ef jal ra,7f80 + 810a: 0141 addi sp,sp,16 + 810c: 908f806f j 214 <__riscv_restore_0> + 8110: 32aa07b7 lui a5,0x32aa0 + 8114: 88078793 addi a5,a5,-1920 # 32a9f880 <_eusrstack+0x12a97880> + 8118: 00a7f663 bgeu a5,a0,8124 + 811c: 77f9 lui a5,0xffffe + 811e: bd778793 addi a5,a5,-1065 # ffffdbd7 <_eusrstack+0xdfff5bd7> + 8122: bfe9 j 80fc + 8124: 2de547b7 lui a5,0x2de54 + 8128: 48078793 addi a5,a5,1152 # 2de54480 <_eusrstack+0xde4c480> + 812c: 00a7f663 bgeu a5,a0,8138 + 8130: 77f1 lui a5,0xffffc + 8132: 5c178793 addi a5,a5,1473 # ffffc5c1 <_eusrstack+0xdfff45c1> + 8136: b7d9 j 80fc + 8138: 1b6b17b7 lui a5,0x1b6b1 + 813c: b0078793 addi a5,a5,-1280 # 1b6b0b00 <_data_lma+0x1b6a28a4> + 8140: 00a7f663 bgeu a5,a0,814c + 8144: 77e1 lui a5,0xffff8 + 8146: 17578793 addi a5,a5,373 # ffff8175 <_eusrstack+0xdfff0175> + 814a: bf4d j 80fc + 814c: 195507b7 lui a5,0x19550 + 8150: c4078793 addi a5,a5,-960 # 1954fc40 <_data_lma+0x195419e4> + 8154: faa7f5e3 bgeu a5,a0,80fe + 8158: 679d lui a5,0x7 + 815a: f6b78793 addi a5,a5,-149 # 6f6b + 815e: bf79 j 80fc + +00008160 : + 8160: 890f82ef jal t0,1f0 <__riscv_save_0> + 8164: 1141 addi sp,sp,-16 + 8166: 842a mv s0,a0 + 8168: f7dff0ef jal ra,80e4 + 816c: 01e85637 lui a2,0x1e85 + 8170: 4681 li a3,0 + 8172: 80060613 addi a2,a2,-2048 # 1e84800 <_data_lma+0x1e765a4> + 8176: 01941513 slli a0,s0,0x19 + 817a: 00745593 srli a1,s0,0x7 + 817e: 3ae010ef jal ra,952c <__udivdi3> + 8182: 01855793 srli a5,a0,0x18 + 8186: 865c sb a5,12(sp) + 8188: 01055793 srli a5,a0,0x10 + 818c: 86dc sb a5,13(sp) + 818e: 00851793 slli a5,a0,0x8 + 8192: 0542 slli a0,a0,0x10 + 8194: 8141 srli a0,a0,0x10 + 8196: 8121 srli a0,a0,0x8 + 8198: 8d5d or a0,a0,a5 + 819a: 8768 sh a0,14(sp) + 819c: 006c addi a1,sp,12 + 819e: 4611 li a2,4 + 81a0: 08600513 li a0,134 + 81a4: dddff0ef jal ra,7f80 + 81a8: 0141 addi sp,sp,16 + 81aa: 86af806f j 214 <__riscv_restore_0> + +000081ae : + 81ae: 842f82ef jal t0,1f0 <__riscv_save_0> + 81b2: 1141 addi sp,sp,-16 + 81b4: 87c8 sb a0,15(sp) + 81b6: 00f10593 addi a1,sp,15 + 81ba: 4605 li a2,1 + 81bc: 09600513 li a0,150 + 81c0: dc1ff0ef jal ra,7f80 + 81c4: 0141 addi sp,sp,16 + 81c6: 84ef806f j 214 <__riscv_restore_0> + +000081ca : + 81ca: 826f82ef jal t0,1f0 <__riscv_save_0> + 81ce: 1141 addi sp,sp,-16 + 81d0: 8648 sb a0,12(sp) + 81d2: 86cc sb a1,13(sp) + 81d4: 4609 li a2,2 + 81d6: 006c addi a1,sp,12 + 81d8: 08f00513 li a0,143 + 81dc: da5ff0ef jal ra,7f80 + 81e0: 0141 addi sp,sp,16 + 81e2: 832f806f j 214 <__riscv_restore_0> + +000081e6 : + 81e6: 80af82ef jal t0,1f0 <__riscv_save_0> + 81ea: 5775 li a4,-3 + 81ec: 1141 addi sp,sp,-16 + 81ee: 57f5 li a5,-3 + 81f0: 00e54363 blt a0,a4,81f6 + 81f4: 87aa mv a5,a0 + 81f6: 01879693 slli a3,a5,0x18 + 81fa: 86e1 srai a3,a3,0x18 + 81fc: 4759 li a4,22 + 81fe: 00d75363 bge a4,a3,8204 + 8202: 47d9 li a5,22 + 8204: 86cc sb a1,13(sp) + 8206: 4609 li a2,2 + 8208: 006c addi a1,sp,12 + 820a: 08e00513 li a0,142 + 820e: 865c sb a5,12(sp) + 8210: d71ff0ef jal ra,7f80 + 8214: 0141 addi sp,sp,16 + 8216: ffff706f j 214 <__riscv_restore_0> + +0000821a : + 821a: fd7f72ef jal t0,1f0 <__riscv_save_0> + 821e: 1141 addi sp,sp,-16 + 8220: 8648 sb a0,12(sp) + 8222: 86cc sb a1,13(sp) + 8224: 8750 sb a2,14(sp) + 8226: 006c addi a1,sp,12 + 8228: 4611 li a2,4 + 822a: 09500513 li a0,149 + 822e: 87d4 sb a3,15(sp) + 8230: d51ff0ef jal ra,7f80 + 8234: 0141 addi sp,sp,16 + 8236: fdff706f j 214 <__riscv_restore_0> + +0000823a : + 823a: f8ff72ef jal t0,1c8 <__riscv_save_10> + 823e: 57f5 li a5,-3 + 8240: 8b2a mv s6,a0 + 8242: 1141 addi sp,sp,-16 + 8244: 8ab2 mv s5,a2 + 8246: 8a36 mv s4,a3 + 8248: 5575 li a0,-3 + 824a: 00f5c363 blt a1,a5,8250 + 824e: 852e mv a0,a1 + 8250: 01851713 slli a4,a0,0x18 + 8254: 8761 srai a4,a4,0x18 + 8256: 47d9 li a5,22 + 8258: 00e7d363 bge a5,a4,825e + 825c: 4559 li a0,22 + 825e: 01851493 slli s1,a0,0x18 + 8262: 9e5ff0ef jal ra,7c46 + 8266: 4609 li a2,2 + 8268: 006c addi a1,sp,12 + 826a: 74000513 li a0,1856 + 826e: b3fff0ef jal ra,7dac + 8272: 8600 lbu s0,12(sp) + 8274: 869c lbu a5,13(sp) + 8276: 0000e9b7 lui s3,0xe + 827a: 0422 slli s0,s0,0x8 + 827c: 943e add s0,s0,a5 + 827e: 0442 slli s0,s0,0x10 + 8280: 8041 srli s0,s0,0x10 + 8282: 0000b937 lui s2,0xb + 8286: 0000e537 lui a0,0xe + 828a: 86a2 mv a3,s0 + 828c: bcc98613 addi a2,s3,-1076 # dbcc + 8290: 4ec90593 addi a1,s2,1260 # b4ec <_exit+0x94> + 8294: b1c50513 addi a0,a0,-1252 # db1c + 8298: 12f010ef jal ra,9bc6 + 829c: 6789 lui a5,0x2 + 829e: 4b478793 addi a5,a5,1204 # 24b4 + 82a2: 84e1 srai s1,s1,0x18 + 82a4: 8bce mv s7,s3 + 82a6: 02f40763 beq s0,a5,82d4 + 82aa: 6785 lui a5,0x1 + 82ac: 42478793 addi a5,a5,1060 # 1424 + 82b0: 02f40263 beq s0,a5,82d4 + 82b4: 0000c5b7 lui a1,0xc + 82b8: 0000e537 lui a0,0xe + 82bc: bcc98613 addi a2,s3,-1076 + 82c0: 18858593 addi a1,a1,392 # c188 <_exit+0xd30> + 82c4: b3850513 addi a0,a0,-1224 # db38 + 82c8: 0ff010ef jal ra,9bc6 + 82cc: 4541 li a0,16 + 82ce: 0141 addi sp,sp,16 + 82d0: f31f706f j 200 <__riscv_restore_10> + 82d4: 0000e537 lui a0,0xe + 82d8: bccb8613 addi a2,s7,-1076 + 82dc: 4ec90593 addi a1,s2,1260 + 82e0: b6c50513 addi a0,a0,-1172 # db6c + 82e4: 0e3010ef jal ra,9bc6 + 82e8: 4501 li a0,0 + 82ea: d1dff0ef jal ra,8006 + 82ee: 4505 li a0,1 + 82f0: dd9ff0ef jal ra,80c8 + 82f4: 000a8863 beqz s5,8304 + 82f8: 6585 lui a1,0x1 + 82fa: 38858593 addi a1,a1,904 # 1388 + 82fe: 8556 mv a0,s5 + 8300: d23ff0ef jal ra,8022 + 8304: 07f00513 li a0,127 + 8308: da5ff0ef jal ra,80ac + 830c: 0000e537 lui a0,0xe + 8310: 86d2 mv a3,s4 + 8312: bccb8613 addi a2,s7,-1076 + 8316: 4ec90593 addi a1,s2,1260 + 831a: b8850513 addi a0,a0,-1144 # db88 + 831e: 0a9010ef jal ra,9bc6 + 8322: 4501 li a0,0 + 8324: 000a1363 bnez s4,832a + 8328: 4505 li a0,1 + 832a: e85ff0ef jal ra,81ae + 832e: 4581 li a1,0 + 8330: 4501 li a0,0 + 8332: e99ff0ef jal ra,81ca + 8336: 4685 li a3,1 + 8338: 4601 li a2,0 + 833a: 459d li a1,7 + 833c: 4511 li a0,4 + 833e: eddff0ef jal ra,821a + 8342: 6505 lui a0,0x1 + 8344: 47e1 li a5,24 + 8346: 4605 li a2,1 + 8348: 00b10593 addi a1,sp,11 + 834c: 8e750513 addi a0,a0,-1817 # 8e7 <__stack_size+0xe7> + 8350: 85dc sb a5,11(sp) + 8352: 9b5ff0ef jal ra,7d06 + 8356: 4591 li a1,4 + 8358: 8526 mv a0,s1 + 835a: e8dff0ef jal ra,81e6 + 835e: 855a mv a0,s6 + 8360: e01ff0ef jal ra,8160 + 8364: 4501 li a0,0 + 8366: b7a5 j 82ce + +00008368 : + 8368: e89f72ef jal t0,1f0 <__riscv_save_0> + 836c: 00851793 slli a5,a0,0x8 + 8370: 8121 srli a0,a0,0x8 + 8372: 8d5d or a0,a0,a5 + 8374: 00859793 slli a5,a1,0x8 + 8378: 81a1 srli a1,a1,0x8 + 837a: 8ddd or a1,a1,a5 + 837c: 00861793 slli a5,a2,0x8 + 8380: 8221 srli a2,a2,0x8 + 8382: 1141 addi sp,sp,-16 + 8384: 8e5d or a2,a2,a5 + 8386: 00869793 slli a5,a3,0x8 + 838a: 82a1 srli a3,a3,0x8 + 838c: 8468 sh a0,8(sp) + 838e: 856c sh a1,10(sp) + 8390: 8670 sh a2,12(sp) + 8392: 8edd or a3,a3,a5 + 8394: 002c addi a1,sp,8 + 8396: 4621 li a2,8 + 8398: 4521 li a0,8 + 839a: 8774 sh a3,14(sp) + 839c: be5ff0ef jal ra,7f80 + 83a0: 0141 addi sp,sp,16 + 83a2: e73f706f j 214 <__riscv_restore_0> + +000083a6 : + 83a6: e4bf72ef jal t0,1f0 <__riscv_save_0> + 83aa: 842a mv s0,a0 + 83ac: 86aa mv a3,a0 + 83ae: 0000e637 lui a2,0xe + 83b2: 0000b5b7 lui a1,0xb + 83b6: 0000e537 lui a0,0xe + 83ba: 1141 addi sp,sp,-16 + 83bc: bcc60613 addi a2,a2,-1076 # dbcc + 83c0: 4ec58593 addi a1,a1,1260 # b4ec <_exit+0x94> + 83c4: d4850513 addi a0,a0,-696 # dd48 + 83c8: 7fe010ef jal ra,9bc6 + 83cc: ec09 bnez s0,83e6 + 83ce: 000107a3 sb zero,15(sp) + 83d2: 00f10593 addi a1,sp,15 + 83d6: 4605 li a2,1 + 83d8: 09f00513 li a0,159 + 83dc: ba5ff0ef jal ra,7f80 + 83e0: 0141 addi sp,sp,16 + 83e2: e33f706f j 214 <__riscv_restore_0> + 83e6: 4785 li a5,1 + 83e8: 87dc sb a5,15(sp) + 83ea: b7e5 j 83d2 + +000083ec : + 83ec: e05f72ef jal t0,1f0 <__riscv_save_0> + 83f0: 1141 addi sp,sp,-16 + 83f2: 87c8 sb a0,15(sp) + 83f4: 00f10593 addi a1,sp,15 + 83f8: 4605 li a2,1 + 83fa: 0a000513 li a0,160 + 83fe: b83ff0ef jal ra,7f80 + 8402: 0141 addi sp,sp,16 + 8404: e11f706f j 214 <__riscv_restore_0> + +00008408 : + 8408: de9f72ef jal t0,1f0 <__riscv_save_0> + 840c: 1141 addi sp,sp,-16 + 840e: 87c8 sb a0,15(sp) + 8410: 00f10593 addi a1,sp,15 + 8414: 4605 li a2,1 + 8416: 08a00513 li a0,138 + 841a: b67ff0ef jal ra,7f80 + 841e: 0141 addi sp,sp,16 + 8420: df5f706f j 214 <__riscv_restore_0> + +00008424 : + 8424: dcdf72ef jal t0,1f0 <__riscv_save_0> + 8428: 1141 addi sp,sp,-16 + 842a: 8648 sb a0,12(sp) + 842c: 86cc sb a1,13(sp) + 842e: 8750 sb a2,14(sp) + 8430: 006c addi a1,sp,12 + 8432: 4611 li a2,4 + 8434: 08b00513 li a0,139 + 8438: 87d4 sb a3,15(sp) + 843a: b47ff0ef jal ra,7f80 + 843e: 0141 addi sp,sp,16 + 8440: dd5f706f j 214 <__riscv_restore_0> + +00008444 : + 8444: dadf72ef jal t0,1f0 <__riscv_save_0> + 8448: 00851793 slli a5,a0,0x8 + 844c: 8121 srli a0,a0,0x8 + 844e: 1141 addi sp,sp,-16 + 8450: 8d5d or a0,a0,a5 + 8452: 8668 sh a0,12(sp) + 8454: 006c addi a1,sp,12 + 8456: 4609 li a2,2 + 8458: 4509 li a0,2 + 845a: b27ff0ef jal ra,7f80 + 845e: 0141 addi sp,sp,16 + 8460: db5f706f j 214 <__riscv_restore_0> + +00008464 : + 8464: d8df72ef jal t0,1f0 <__riscv_save_0> + 8468: 892a mv s2,a0 + 846a: 84ae mv s1,a1 + 846c: 6505 lui a0,0x1 + 846e: 0000e5b7 lui a1,0xe + 8472: 1141 addi sp,sp,-16 + 8474: c0058593 addi a1,a1,-1024 # dc00 + 8478: 38850513 addi a0,a0,904 # 1388 + 847c: 8432 mv s0,a2 + 847e: 82fff0ef jal ra,7cac + 8482: 82e18783 lb a5,-2002(gp) # 2000021e + 8486: c385 beqz a5,84a6 + 8488: 0000e637 lui a2,0xe + 848c: 0000b5b7 lui a1,0xb + 8490: 0000e537 lui a0,0xe + 8494: 86ca mv a3,s2 + 8496: bcc60613 addi a2,a2,-1076 # dbcc + 849a: 4ec58593 addi a1,a1,1260 # b4ec <_exit+0x94> + 849e: c1450513 addi a0,a0,-1004 # dc14 + 84a2: 724010ef jal ra,9bc6 + 84a6: 858a mv a1,sp + 84a8: c002 sw zero,0(sp) + 84aa: 00140613 addi a2,s0,1 + 84ae: 852e mv a0,a1 + 84b0: c202 sw zero,4(sp) + 84b2: c402 sw zero,8(sp) + 84b4: c602 sw zero,12(sp) + 84b6: 01210023 sb s2,0(sp) + 84ba: e70ff0ef jal ra,7b2a + 84be: c881 beqz s1,84ce + 84c0: c419 beqz s0,84ce + 84c2: 8622 mv a2,s0 + 84c4: 00110593 addi a1,sp,1 + 84c8: 8526 mv a0,s1 + 84ca: 488010ef jal ra,9952 + 84ce: 4505 li a0,1 + 84d0: 797000ef jal ra,9466 + 84d4: 0000e5b7 lui a1,0xe + 84d8: 6505 lui a0,0x1 + 84da: 4601 li a2,0 + 84dc: c3858593 addi a1,a1,-968 # dc38 + 84e0: 38850513 addi a0,a0,904 # 1388 + 84e4: edeff0ef jal ra,7bc2 + 84e8: 0141 addi sp,sp,16 + 84ea: d2bf706f j 214 <__riscv_restore_0> + +000084ee : + 84ee: d03f72ef jal t0,1f0 <__riscv_save_0> + 84f2: 1141 addi sp,sp,-16 + 84f4: 892a mv s2,a0 + 84f6: 84ae mv s1,a1 + 84f8: 8432 mv s0,a2 + 84fa: 006c addi a1,sp,12 + 84fc: 4611 li a2,4 + 84fe: 4551 li a0,20 + 8500: f65ff0ef jal ra,8464 + 8504: 879c lbu a5,15(sp) + 8506: 8385 srli a5,a5,0x1 + 8508: 40f007b3 neg a5,a5 + 850c: 00f90023 sb a5,0(s2) + 8510: 871c lbu a5,14(sp) + 8512: 01879713 slli a4,a5,0x18 + 8516: 8761 srai a4,a4,0x18 + 8518: 00074863 bltz a4,8528 + 851c: 8389 srli a5,a5,0x2 + 851e: a09c sb a5,0(s1) + 8520: a018 sb a4,0(s0) + 8522: 0141 addi sp,sp,16 + 8524: cf1f706f j 214 <__riscv_restore_0> + 8528: f0078793 addi a5,a5,-256 + 852c: 8789 srai a5,a5,0x2 + 852e: bfc5 j 851e + +00008530 : + 8530: cc1f72ef jal t0,1f0 <__riscv_save_0> + 8534: 1141 addi sp,sp,-16 + 8536: 00f10593 addi a1,sp,15 + 853a: 4605 li a2,1 + 853c: 0c000513 li a0,192 + 8540: f25ff0ef jal ra,8464 + 8544: 8788 lbu a0,15(sp) + 8546: 0141 addi sp,sp,16 + 8548: ccdf706f j 214 <__riscv_restore_0> + +0000854c : + 854c: ca5f72ef jal t0,1f0 <__riscv_save_0> + 8550: 82e18783 lb a5,-2002(gp) # 2000021e + 8554: 1141 addi sp,sp,-16 + 8556: 842a mv s0,a0 + 8558: c385 beqz a5,8578 + 855a: 86aa mv a3,a0 + 855c: 0000e637 lui a2,0xe + 8560: 0000b5b7 lui a1,0xb + 8564: 0000e537 lui a0,0xe + 8568: bcc60613 addi a2,a2,-1076 # dbcc + 856c: 4ec58593 addi a1,a1,1260 # b4ec <_exit+0x94> + 8570: d0450513 addi a0,a0,-764 # dd04 + 8574: 652010ef jal ra,9bc6 + 8578: 4501 li a0,0 + 857a: a8dff0ef jal ra,8006 + 857e: 01045793 srli a5,s0,0x10 + 8582: 865c sb a5,12(sp) + 8584: 460d li a2,3 + 8586: 00845793 srli a5,s0,0x8 + 858a: 006c addi a1,sp,12 + 858c: 08200513 li a0,130 + 8590: 8740 sb s0,14(sp) + 8592: 86dc sb a5,13(sp) + 8594: 4429 li s0,10 + 8596: 9ebff0ef jal ra,7f80 + 859a: 05000493 li s1,80 + 859e: f93ff0ef jal ra,8530 + 85a2: 07057513 andi a0,a0,112 + 85a6: 00950763 beq a0,s1,85b4 + 85aa: 4505 li a0,1 + 85ac: 147d addi s0,s0,-1 + 85ae: 6b9000ef jal ra,9466 + 85b2: f475 bnez s0,859e + 85b4: f7dff0ef jal ra,8530 + 85b8: 07057513 andi a0,a0,112 + 85bc: 05000793 li a5,80 + 85c0: 02f50363 beq a0,a5,85e6 + 85c4: 0000e637 lui a2,0xe + 85c8: 0000c5b7 lui a1,0xc + 85cc: 0000e537 lui a0,0xe + 85d0: bcc60613 addi a2,a2,-1076 # dbcc + 85d4: 18858593 addi a1,a1,392 # c188 <_exit+0xd30> + 85d8: d2850513 addi a0,a0,-728 # dd28 + 85dc: 5ea010ef jal ra,9bc6 + 85e0: 4549 li a0,18 + 85e2: c02ff0ef jal ra,79e4 + 85e6: 0141 addi sp,sp,16 + 85e8: c2df706f j 214 <__riscv_restore_0> + +000085ec : + 85ec: c05f72ef jal t0,1f0 <__riscv_save_0> + 85f0: 1101 addi sp,sp,-32 + 85f2: 842a mv s0,a0 + 85f4: 4501 li a0,0 + 85f6: 84b6 mv s1,a3 + 85f8: ca3a sw a4,20(sp) + 85fa: c83e sw a5,16(sp) + 85fc: c642 sw a6,12(sp) + 85fe: ce2e sw a1,28(sp) + 8600: cc32 sw a2,24(sp) + 8602: da5ff0ef jal ra,83a6 + 8606: 4501 li a0,0 + 8608: de5ff0ef jal ra,83ec + 860c: 4505 li a0,1 + 860e: dfbff0ef jal ra,8408 + 8612: 4662 lw a2,24(sp) + 8614: 45f2 lw a1,28(sp) + 8616: 4681 li a3,0 + 8618: 8522 mv a0,s0 + 861a: e0bff0ef jal ra,8424 + 861e: 00849693 slli a3,s1,0x8 + 8622: 4752 lw a4,20(sp) + 8624: 80a1 srli s1,s1,0x8 + 8626: 8cd5 or s1,s1,a3 + 8628: 82919423 sh s1,-2008(gp) # 20000218 + 862c: 82818693 addi a3,gp,-2008 # 20000218 + 8630: 4832 lw a6,12(sp) + 8632: 47c2 lw a5,16(sp) + 8634: c325 beqz a4,8694 + 8636: 4605 li a2,1 + 8638: a2b0 sb a2,2(a3) + 863a: b2b8 sb a4,3(a3) + 863c: 01003533 snez a0,a6 + 8640: 00f037b3 snez a5,a5 + 8644: a2dc sb a5,4(a3) + 8646: b2c8 sb a0,5(a3) + 8648: 853ff0ef jal ra,7e9a + 864c: 82818593 addi a1,gp,-2008 # 20000218 + 8650: 4619 li a2,6 + 8652: 08c00513 li a0,140 + 8656: 92bff0ef jal ra,7f80 + 865a: 4681 li a3,0 + 865c: 4601 li a2,0 + 865e: 4581 li a1,0 + 8660: 3ff00513 li a0,1023 + 8664: d05ff0ef jal ra,8368 + 8668: 0000e637 lui a2,0xe + 866c: 0000b5b7 lui a1,0xb + 8670: 0000e537 lui a0,0xe + 8674: bcc60613 addi a2,a2,-1076 # dbcc + 8678: 4ec58593 addi a1,a1,1260 # b4ec <_exit+0x94> + 867c: ba850513 addi a0,a0,-1112 # dba8 + 8680: 546010ef jal ra,9bc6 + 8684: 01000537 lui a0,0x1000 + 8688: 157d addi a0,a0,-1 + 868a: ec3ff0ef jal ra,854c + 868e: 6105 addi sp,sp,32 + 8690: b85f706f j 214 <__riscv_restore_0> + 8694: f0000713 li a4,-256 + 8698: a2ba sh a4,2(a3) + 869a: b74d j 863c + +0000869c : + 869c: b55f72ef jal t0,1f0 <__riscv_save_0> + 86a0: 82e18783 lb a5,-2002(gp) # 2000021e + 86a4: 1141 addi sp,sp,-16 + 86a6: 892a mv s2,a0 + 86a8: 82e18493 addi s1,gp,-2002 # 2000021e + 86ac: c385 beqz a5,86cc + 86ae: 86aa mv a3,a0 + 86b0: 0000e637 lui a2,0xe + 86b4: 0000b5b7 lui a1,0xb + 86b8: 0000e537 lui a0,0xe + 86bc: bcc60613 addi a2,a2,-1076 # dbcc + 86c0: 4ec58593 addi a1,a1,1260 # b4ec <_exit+0x94> + 86c4: d7c50513 addi a0,a0,-644 # dd7c + 86c8: 4fe010ef jal ra,9bc6 + 86cc: 4501 li a0,0 + 86ce: 939ff0ef jal ra,8006 + 86d2: 00048783 lb a5,0(s1) + 86d6: 6441 lui s0,0x10 + 86d8: a0040413 addi s0,s0,-1536 # fa00 <_data_lma+0x17a4> + 86dc: 02890433 mul s0,s2,s0 + 86e0: c38d beqz a5,8702 + 86e2: 0000e637 lui a2,0xe + 86e6: 0000b5b7 lui a1,0xb + 86ea: 0000e537 lui a0,0xe + 86ee: 8722 mv a4,s0 + 86f0: 86ca mv a3,s2 + 86f2: bcc60613 addi a2,a2,-1076 # dbcc + 86f6: 4ec58593 addi a1,a1,1260 # b4ec <_exit+0x94> + 86fa: da450513 addi a0,a0,-604 # dda4 + 86fe: 4c8010ef jal ra,9bc6 + 8702: 01045793 srli a5,s0,0x10 + 8706: 460d li a2,3 + 8708: 8021 srli s0,s0,0x8 + 870a: 006c addi a1,sp,12 + 870c: 08300513 li a0,131 + 8710: 865c sb a5,12(sp) + 8712: 86c0 sb s0,13(sp) + 8714: 00010723 sb zero,14(sp) + 8718: 869ff0ef jal ra,7f80 + 871c: 00048783 lb a5,0(s1) + 8720: cf99 beqz a5,873e + 8722: 0000e637 lui a2,0xe + 8726: 0000b5b7 lui a1,0xb + 872a: 0000e537 lui a0,0xe + 872e: bcc60613 addi a2,a2,-1076 # dbcc + 8732: 66058593 addi a1,a1,1632 # b660 <_exit+0x208> + 8736: dcc50513 addi a0,a0,-564 # ddcc + 873a: 48c010ef jal ra,9bc6 + 873e: 4451 li s0,20 + 8740: 06000913 li s2,96 + 8744: dedff0ef jal ra,8530 + 8748: 07057513 andi a0,a0,112 + 874c: 01250763 beq a0,s2,875a + 8750: 4505 li a0,1 + 8752: 147d addi s0,s0,-1 + 8754: 513000ef jal ra,9466 + 8758: f475 bnez s0,8744 + 875a: 00048783 lb a5,0(s1) + 875e: cf99 beqz a5,877c + 8760: 0000e637 lui a2,0xe + 8764: 0000b5b7 lui a1,0xb + 8768: 0000e537 lui a0,0xe + 876c: bcc60613 addi a2,a2,-1076 # dbcc + 8770: 4ec58593 addi a1,a1,1260 # b4ec <_exit+0x94> + 8774: df450513 addi a0,a0,-524 # ddf4 + 8778: 44e010ef jal ra,9bc6 + 877c: db5ff0ef jal ra,8530 + 8780: 07057513 andi a0,a0,112 + 8784: 06000793 li a5,96 + 8788: 02f50363 beq a0,a5,87ae + 878c: 0000e637 lui a2,0xe + 8790: 0000c5b7 lui a1,0xc + 8794: 0000e537 lui a0,0xe + 8798: bcc60613 addi a2,a2,-1076 # dbcc + 879c: 18858593 addi a1,a1,392 # c188 <_exit+0xd30> + 87a0: e0c50513 addi a0,a0,-500 # de0c + 87a4: 422010ef jal ra,9bc6 + 87a8: 454d li a0,19 + 87aa: a3aff0ef jal ra,79e4 + 87ae: 0141 addi sp,sp,16 + 87b0: a65f706f j 214 <__riscv_restore_0> + +000087b4 : + 87b4: a3df72ef jal t0,1f0 <__riscv_save_0> + 87b8: 1141 addi sp,sp,-16 + 87ba: 006c addi a1,sp,12 + 87bc: 460d li a2,3 + 87be: 4549 li a0,18 + 87c0: ca5ff0ef jal ra,8464 + 87c4: 869c lbu a5,13(sp) + 87c6: 8708 lbu a0,14(sp) + 87c8: 07a2 slli a5,a5,0x8 + 87ca: 8d5d or a0,a0,a5 + 87cc: 0141 addi sp,sp,16 + 87ce: a47f706f j 214 <__riscv_restore_0> + +000087d2 : + 87d2: a1ff72ef jal t0,1f0 <__riscv_save_0> + 87d6: 1141 addi sp,sp,-16 + 87d8: 842e mv s0,a1 + 87da: 84aa mv s1,a0 + 87dc: 006c addi a1,sp,12 + 87de: 460d li a2,3 + 87e0: 454d li a0,19 + 87e2: c83ff0ef jal ra,8464 + 87e6: 869c lbu a5,13(sp) + 87e8: a09c sb a5,0(s1) + 87ea: 871c lbu a5,14(sp) + 87ec: a01c sb a5,0(s0) + 87ee: 0141 addi sp,sp,16 + 87f0: a25f706f j 214 <__riscv_restore_0> + +000087f4 : + 87f4: 400217b7 lui a5,0x40021 + 87f8: 4398 lw a4,0(a5) + 87fa: f0ff06b7 lui a3,0xf0ff0 + 87fe: 1141 addi sp,sp,-16 + 8800: 00176713 ori a4,a4,1 + 8804: c398 sw a4,0(a5) + 8806: 43d8 lw a4,4(a5) + 8808: 00020637 lui a2,0x20 + 880c: 8f75 and a4,a4,a3 + 880e: c3d8 sw a4,4(a5) + 8810: 4398 lw a4,0(a5) + 8812: fef706b7 lui a3,0xfef70 + 8816: 16fd addi a3,a3,-1 + 8818: 8f75 and a4,a4,a3 + 881a: c398 sw a4,0(a5) + 881c: 4398 lw a4,0(a5) + 881e: fffc06b7 lui a3,0xfffc0 + 8822: 16fd addi a3,a3,-1 + 8824: 8f75 and a4,a4,a3 + 8826: c398 sw a4,0(a5) + 8828: 43d8 lw a4,4(a5) + 882a: ff0106b7 lui a3,0xff010 + 882e: 16fd addi a3,a3,-1 + 8830: 8f75 and a4,a4,a3 + 8832: c3d8 sw a4,4(a5) + 8834: 4398 lw a4,0(a5) + 8836: ec0006b7 lui a3,0xec000 + 883a: 16fd addi a3,a3,-1 + 883c: 8f75 and a4,a4,a3 + 883e: c398 sw a4,0(a5) + 8840: 00ff0737 lui a4,0xff0 + 8844: c798 sw a4,8(a5) + 8846: 0207a623 sw zero,44(a5) # 4002102c <_eusrstack+0x2001902c> + 884a: c402 sw zero,8(sp) + 884c: c602 sw zero,12(sp) + 884e: 4398 lw a4,0(a5) + 8850: 66c1 lui a3,0x10 + 8852: 8f55 or a4,a4,a3 + 8854: c398 sw a4,0(a5) + 8856: 400216b7 lui a3,0x40021 + 885a: 6705 lui a4,0x1 + 885c: 429c lw a5,0(a3) + 885e: 8ff1 and a5,a5,a2 + 8860: c63e sw a5,12(sp) + 8862: 47a2 lw a5,8(sp) + 8864: 0785 addi a5,a5,1 + 8866: c43e sw a5,8(sp) + 8868: 47b2 lw a5,12(sp) + 886a: e781 bnez a5,8872 + 886c: 47a2 lw a5,8(sp) + 886e: fee797e3 bne a5,a4,885c + 8872: 400217b7 lui a5,0x40021 + 8876: 439c lw a5,0(a5) + 8878: 00e79713 slli a4,a5,0xe + 887c: 06075763 bgez a4,88ea + 8880: 4785 li a5,1 + 8882: c63e sw a5,12(sp) + 8884: 4732 lw a4,12(sp) + 8886: 4785 li a5,1 + 8888: 04f71f63 bne a4,a5,88e6 + 888c: 400217b7 lui a5,0x40021 + 8890: 43d8 lw a4,4(a5) + 8892: ffc106b7 lui a3,0xffc10 + 8896: 16fd addi a3,a3,-1 + 8898: c3d8 sw a4,4(a5) + 889a: 43d8 lw a4,4(a5) + 889c: c3d8 sw a4,4(a5) + 889e: 43d8 lw a4,4(a5) + 88a0: 40076713 ori a4,a4,1024 + 88a4: c3d8 sw a4,4(a5) + 88a6: 43d8 lw a4,4(a5) + 88a8: 8f75 and a4,a4,a3 + 88aa: c3d8 sw a4,4(a5) + 88ac: 43d8 lw a4,4(a5) + 88ae: 002906b7 lui a3,0x290 + 88b2: 8f55 or a4,a4,a3 + 88b4: c3d8 sw a4,4(a5) + 88b6: 4398 lw a4,0(a5) + 88b8: 010006b7 lui a3,0x1000 + 88bc: 8f55 or a4,a4,a3 + 88be: c398 sw a4,0(a5) + 88c0: 4398 lw a4,0(a5) + 88c2: 00671693 slli a3,a4,0x6 + 88c6: fe06dde3 bgez a3,88c0 + 88ca: 43d8 lw a4,4(a5) + 88cc: 400216b7 lui a3,0x40021 + 88d0: 9b71 andi a4,a4,-4 + 88d2: c3d8 sw a4,4(a5) + 88d4: 43d8 lw a4,4(a5) + 88d6: 00276713 ori a4,a4,2 + 88da: c3d8 sw a4,4(a5) + 88dc: 4721 li a4,8 + 88de: 42dc lw a5,4(a3) + 88e0: 8bb1 andi a5,a5,12 + 88e2: fee79ee3 bne a5,a4,88de + 88e6: 0141 addi sp,sp,16 + 88e8: 8082 ret + 88ea: c602 sw zero,12(sp) + 88ec: bf61 j 8884 + +000088ee : + 88ee: 400216b7 lui a3,0x40021 + 88f2: 42d8 lw a4,4(a3) + 88f4: 200007b7 lui a5,0x20000 + 88f8: 4611 li a2,4 + 88fa: 8b31 andi a4,a4,12 + 88fc: 1f078793 addi a5,a5,496 # 200001f0 + 8900: 00c70563 beq a4,a2,890a + 8904: 4621 li a2,8 + 8906: 02c70863 beq a4,a2,8936 + 890a: 007a1737 lui a4,0x7a1 + 890e: 20070713 addi a4,a4,512 # 7a1200 <_data_lma+0x792fa4> + 8912: c398 sw a4,0(a5) + 8914: 40021737 lui a4,0x40021 + 8918: 4358 lw a4,4(a4) + 891a: 8311 srli a4,a4,0x4 + 891c: 00f77693 andi a3,a4,15 + 8920: 20000737 lui a4,0x20000 + 8924: 00070713 mv a4,a4 + 8928: 9736 add a4,a4,a3 + 892a: 2314 lbu a3,0(a4) + 892c: 4398 lw a4,0(a5) + 892e: 00d75733 srl a4,a4,a3 + 8932: c398 sw a4,0(a5) + 8934: 8082 ret + 8936: 42d8 lw a4,4(a3) + 8938: 42d4 lw a3,4(a3) + 893a: 6641 lui a2,0x10 + 893c: 8349 srli a4,a4,0x12 + 893e: 8b3d andi a4,a4,15 + 8940: 8ef1 and a3,a3,a2 + 8942: 00270613 addi a2,a4,2 # 20000002 <_data_vma+0x2> + 8946: cf15 beqz a4,8982 + 8948: 473d li a4,15 + 894a: 02e60f63 beq a2,a4,8988 + 894e: 4741 li a4,16 + 8950: 02e60f63 beq a2,a4,898e + 8954: 4745 li a4,17 + 8956: 4581 li a1,0 + 8958: 00e61363 bne a2,a4,895e + 895c: 4641 li a2,16 + 895e: e2a1 bnez a3,899e + 8960: 40024737 lui a4,0x40024 + 8964: 80072703 lw a4,-2048(a4) # 40023800 <_eusrstack+0x2001b800> + 8968: 8b41 andi a4,a4,16 + 896a: c70d beqz a4,8994 + 896c: 007a1737 lui a4,0x7a1 + 8970: 20070713 addi a4,a4,512 # 7a1200 <_data_lma+0x792fa4> + 8974: 02c70633 mul a2,a4,a2 + 8978: c390 sw a2,0(a5) + 897a: ddc9 beqz a1,8914 + 897c: 4398 lw a4,0(a5) + 897e: 8305 srli a4,a4,0x1 + 8980: bf49 j 8912 + 8982: 4581 li a1,0 + 8984: 4649 li a2,18 + 8986: bfe1 j 895e + 8988: 4585 li a1,1 + 898a: 4635 li a2,13 + 898c: bfc9 j 895e + 898e: 4581 li a1,0 + 8990: 463d li a2,15 + 8992: b7f1 j 895e + 8994: 003d1737 lui a4,0x3d1 + 8998: 90070713 addi a4,a4,-1792 # 3d0900 <_data_lma+0x3c26a4> + 899c: bfe1 j 8974 + 899e: 40021537 lui a0,0x40021 + 89a2: 5558 lw a4,44(a0) + 89a4: 00f71693 slli a3,a4,0xf + 89a8: 5558 lw a4,44(a0) + 89aa: 0406df63 bgez a3,8a08 + 89ae: 8311 srli a4,a4,0x4 + 89b0: 8b3d andi a4,a4,15 + 89b2: 00170693 addi a3,a4,1 + 89b6: 007a1737 lui a4,0x7a1 + 89ba: 20070713 addi a4,a4,512 # 7a1200 <_data_lma+0x792fa4> + 89be: 02d75733 divu a4,a4,a3 + 89c2: c398 sw a4,0(a5) + 89c4: 5554 lw a3,44(a0) + 89c6: 82a1 srli a3,a3,0x8 + 89c8: 8abd andi a3,a3,15 + 89ca: e28d bnez a3,89ec + 89cc: 4695 li a3,5 + 89ce: 02d70733 mul a4,a4,a3 + 89d2: 8305 srli a4,a4,0x1 + 89d4: c398 sw a4,0(a5) + 89d6: 40021737 lui a4,0x40021 + 89da: 5758 lw a4,44(a4) + 89dc: 4394 lw a3,0(a5) + 89de: 8b3d andi a4,a4,15 + 89e0: 0705 addi a4,a4,1 + 89e2: 02e6d733 divu a4,a3,a4 + 89e6: c398 sw a4,0(a5) + 89e8: 4398 lw a4,0(a5) + 89ea: b769 j 8974 + 89ec: 4505 li a0,1 + 89ee: 00a69463 bne a3,a0,89f6 + 89f2: 46e5 li a3,25 + 89f4: bfe9 j 89ce + 89f6: 453d li a0,15 + 89f8: 00a69663 bne a3,a0,8a04 + 89fc: 46d1 li a3,20 + 89fe: 02e68733 mul a4,a3,a4 + 8a02: bfc9 j 89d4 + 8a04: 0689 addi a3,a3,2 + 8a06: bfe5 j 89fe + 8a08: 8b3d andi a4,a4,15 + 8a0a: 00170693 addi a3,a4,1 # 40021001 <_eusrstack+0x20019001> + 8a0e: 007a1737 lui a4,0x7a1 + 8a12: 20070713 addi a4,a4,512 # 7a1200 <_data_lma+0x792fa4> + 8a16: 02d75733 divu a4,a4,a3 + 8a1a: b7f1 j 89e6 + +00008a1c : + 8a1c: a001 j 8a1c + +00008a1e : + 8a1e: 1fff8197 auipc gp,0x1fff8 + 8a22: fd218193 addi gp,gp,-46 # 200009f0 <__global_pointer$> + 8a26: 1ffff117 auipc sp,0x1ffff + 8a2a: 5da10113 addi sp,sp,1498 # 20008000 <_eusrstack> + 8a2e: 00006517 auipc a0,0x6 + 8a32: 82e50513 addi a0,a0,-2002 # e25c <_data_lma> + 8a36: 1fff7597 auipc a1,0x1fff7 + 8a3a: 5ca58593 addi a1,a1,1482 # 20000000 <_data_vma> + 8a3e: 81818613 addi a2,gp,-2024 # 20000208 <_edata> + 8a42: 00c5fa63 bgeu a1,a2,8a56 + 8a46: 00052283 lw t0,0(a0) + 8a4a: 0055a023 sw t0,0(a1) + 8a4e: 0511 addi a0,a0,4 + 8a50: 0591 addi a1,a1,4 + 8a52: fec5eae3 bltu a1,a2,8a46 + 8a56: 81818513 addi a0,gp,-2024 # 20000208 <_edata> + 8a5a: 79018593 addi a1,gp,1936 # 20001180 <_ebss> + 8a5e: 00b57763 bgeu a0,a1,8a6c + 8a62: 00052023 sw zero,0(a0) + 8a66: 0511 addi a0,a0,4 + 8a68: feb56de3 bltu a0,a1,8a62 + 8a6c: 42fd li t0,31 + 8a6e: bc029073 csrw 0xbc0,t0 + 8a72: 42ad li t0,11 + 8a74: 80429073 csrw 0x804,t0 + 8a78: 000062b7 lui t0,0x6 + 8a7c: 08828293 addi t0,t0,136 # 6088 + 8a80: 30029073 csrw mstatus,t0 + 8a84: ffff7297 auipc t0,0xffff7 + 8a88: 58028293 addi t0,t0,1408 # 4 <_einit> + 8a8c: 0032e293 ori t0,t0,3 + 8a90: 30529073 csrw mtvec,t0 + 8a94: d61ff0ef jal ra,87f4 + 8a98: fffff297 auipc t0,0xfffff + 8a9c: c5a28293 addi t0,t0,-934 # 76f2
+ 8aa0: 34129073 csrw mepc,t0 + 8aa4: 30200073 mret + +00008aa8 : + 8aa8: f48f72ef jal t0,1f0 <__riscv_save_0> + 8aac: 400127b7 lui a5,0x40012 + 8ab0: 40078793 addi a5,a5,1024 # 40012400 <_eusrstack+0x2000a400> + 8ab4: 00f51c63 bne a0,a5,8acc + 8ab8: 4585 li a1,1 + 8aba: 20000513 li a0,512 + 8abe: 2d71 jal 915a + 8ac0: 4581 li a1,0 + 8ac2: 20000513 li a0,512 + 8ac6: 2d51 jal 915a + 8ac8: f4cf706f j 214 <__riscv_restore_0> + 8acc: 400137b7 lui a5,0x40013 + 8ad0: 80078793 addi a5,a5,-2048 # 40012800 <_eusrstack+0x2000a800> + 8ad4: fef51ae3 bne a0,a5,8ac8 + 8ad8: 4585 li a1,1 + 8ada: 40000513 li a0,1024 + 8ade: 2db5 jal 915a + 8ae0: 4581 li a1,0 + 8ae2: 40000513 li a0,1024 + 8ae6: b7c5 j 8ac6 + +00008ae8 : + 8ae8: 415c lw a5,4(a0) + 8aea: e0f10737 lui a4,0xe0f10 + 8aee: eff70713 addi a4,a4,-257 # e0f0feff <_eusrstack+0xc0f07eff> + 8af2: 4d94 lw a3,24(a1) + 8af4: 8f7d and a4,a4,a5 + 8af6: 419c lw a5,0(a1) + 8af8: 8fd5 or a5,a5,a3 + 8afa: 4dd4 lw a3,28(a1) + 8afc: 8fd5 or a5,a5,a3 + 8afe: 41d4 lw a3,4(a1) + 8b00: 06a2 slli a3,a3,0x8 + 8b02: 8fd5 or a5,a5,a3 + 8b04: 8fd9 or a5,a5,a4 + 8b06: c15c sw a5,4(a0) + 8b08: 451c lw a5,8(a0) + 8b0a: fff1f737 lui a4,0xfff1f + 8b0e: 7fd70713 addi a4,a4,2045 # fff1f7fd <_eusrstack+0xdff177fd> + 8b12: 45d4 lw a3,12(a1) + 8b14: 8f7d and a4,a4,a5 + 8b16: 499c lw a5,16(a1) + 8b18: 8fd5 or a5,a5,a3 + 8b1a: 4594 lw a3,8(a1) + 8b1c: 0686 slli a3,a3,0x1 + 8b1e: 8fd5 or a5,a5,a3 + 8b20: 8fd9 or a5,a5,a4 + 8b22: c51c sw a5,8(a0) + 8b24: 555c lw a5,44(a0) + 8b26: ff100737 lui a4,0xff100 + 8b2a: 177d addi a4,a4,-1 + 8b2c: 8f7d and a4,a4,a5 + 8b2e: 29dc lbu a5,20(a1) + 8b30: 17fd addi a5,a5,-1 + 8b32: 0ff7f793 andi a5,a5,255 + 8b36: 07d2 slli a5,a5,0x14 + 8b38: 8fd9 or a5,a5,a4 + 8b3a: d55c sw a5,44(a0) + 8b3c: 8082 ret + +00008b3e : + 8b3e: 451c lw a5,8(a0) + 8b40: c589 beqz a1,8b4a + 8b42: 0017e793 ori a5,a5,1 + 8b46: c51c sw a5,8(a0) + 8b48: 8082 ret + 8b4a: 9bf9 andi a5,a5,-2 + 8b4c: bfed j 8b46 + +00008b4e : + 8b4e: 451c lw a5,8(a0) + 8b50: 0087e793 ori a5,a5,8 + 8b54: c51c sw a5,8(a0) + 8b56: 8082 ret + +00008b58 : + 8b58: 4508 lw a0,8(a0) + 8b5a: 810d srli a0,a0,0x3 + 8b5c: 8905 andi a0,a0,1 + 8b5e: 8082 ret + +00008b60 : + 8b60: 451c lw a5,8(a0) + 8b62: 0047e793 ori a5,a5,4 + 8b66: c51c sw a5,8(a0) + 8b68: 8082 ret + +00008b6a : + 8b6a: 4508 lw a0,8(a0) + 8b6c: 8109 srli a0,a0,0x2 + 8b6e: 8905 andi a0,a0,1 + 8b70: 8082 ret + +00008b72 : + 8b72: 451c lw a5,8(a0) + 8b74: c591 beqz a1,8b80 + 8b76: 00500737 lui a4,0x500 + 8b7a: 8fd9 or a5,a5,a4 + 8b7c: c51c sw a5,8(a0) + 8b7e: 8082 ret + 8b80: ffb00737 lui a4,0xffb00 + 8b84: 177d addi a4,a4,-1 + 8b86: 8ff9 and a5,a5,a4 + 8b88: bfd5 j 8b7c + +00008b8a : + 8b8a: 47a5 li a5,9 + 8b8c: 04b7f763 bgeu a5,a1,8bda + 8b90: 478d li a5,3 + 8b92: ff658713 addi a4,a1,-10 + 8b96: 02f70733 mul a4,a4,a5 + 8b9a: 00c52803 lw a6,12(a0) + 8b9e: 479d li a5,7 + 8ba0: 00e797b3 sll a5,a5,a4 + 8ba4: fff7c793 not a5,a5 + 8ba8: 0107f7b3 and a5,a5,a6 + 8bac: 00e696b3 sll a3,a3,a4 + 8bb0: 8edd or a3,a3,a5 + 8bb2: c554 sw a3,12(a0) + 8bb4: 4799 li a5,6 + 8bb6: 04c7e363 bltu a5,a2,8bfc + 8bba: 4795 li a5,5 + 8bbc: 167d addi a2,a2,-1 + 8bbe: 02f60633 mul a2,a2,a5 + 8bc2: 5958 lw a4,52(a0) + 8bc4: 47fd li a5,31 + 8bc6: 00c797b3 sll a5,a5,a2 + 8bca: fff7c793 not a5,a5 + 8bce: 8ff9 and a5,a5,a4 + 8bd0: 00c59633 sll a2,a1,a2 + 8bd4: 8e5d or a2,a2,a5 + 8bd6: d950 sw a2,52(a0) + 8bd8: 8082 ret + 8bda: 470d li a4,3 + 8bdc: 02e58733 mul a4,a1,a4 + 8be0: 01052803 lw a6,16(a0) + 8be4: 479d li a5,7 + 8be6: 00e797b3 sll a5,a5,a4 + 8bea: fff7c793 not a5,a5 + 8bee: 0107f7b3 and a5,a5,a6 + 8bf2: 00e696b3 sll a3,a3,a4 + 8bf6: 8edd or a3,a3,a5 + 8bf8: c914 sw a3,16(a0) + 8bfa: bf6d j 8bb4 + 8bfc: 47b1 li a5,12 + 8bfe: 02c7e263 bltu a5,a2,8c22 + 8c02: 4795 li a5,5 + 8c04: 1665 addi a2,a2,-7 + 8c06: 02f60633 mul a2,a2,a5 + 8c0a: 5918 lw a4,48(a0) + 8c0c: 47fd li a5,31 + 8c0e: 00c797b3 sll a5,a5,a2 + 8c12: fff7c793 not a5,a5 + 8c16: 8ff9 and a5,a5,a4 + 8c18: 00c59633 sll a2,a1,a2 + 8c1c: 8e5d or a2,a2,a5 + 8c1e: d910 sw a2,48(a0) + 8c20: 8082 ret + 8c22: 4795 li a5,5 + 8c24: 164d addi a2,a2,-13 + 8c26: 02f60633 mul a2,a2,a5 + 8c2a: 5558 lw a4,44(a0) + 8c2c: 47fd li a5,31 + 8c2e: 00c797b3 sll a5,a5,a2 + 8c32: fff7c793 not a5,a5 + 8c36: 8ff9 and a5,a5,a4 + 8c38: 00c595b3 sll a1,a1,a2 + 8c3c: 8ddd or a1,a1,a5 + 8c3e: d54c sw a1,44(a0) + 8c40: 8082 ret + +00008c42 : + 8c42: 4568 lw a0,76(a0) + 8c44: 0542 slli a0,a0,0x10 + 8c46: 8141 srli a0,a0,0x10 + 8c48: 8082 ret + +00008c4a : + 8c4a: 400127b7 lui a5,0x40012 + 8c4e: 40078793 addi a5,a5,1024 # 40012400 <_eusrstack+0x2000a400> + 8c52: 4798 lw a4,8(a5) + 8c54: c511 beqz a0,8c60 + 8c56: 008006b7 lui a3,0x800 + 8c5a: 8f55 or a4,a4,a3 + 8c5c: c798 sw a4,8(a5) + 8c5e: 8082 ret + 8c60: ff8006b7 lui a3,0xff800 + 8c64: 16fd addi a3,a3,-1 + 8c66: 8f75 and a4,a4,a3 + 8c68: bfd5 j 8c5c + +00008c6a : + 8c6a: 4108 lw a0,0(a0) + 8c6c: 8d6d and a0,a0,a1 + 8c6e: 00a03533 snez a0,a0 + 8c72: 8082 ret + +00008c74 : + 8c74: 415c lw a5,4(a0) + 8c76: c591 beqz a1,8c82 + 8c78: 04000737 lui a4,0x4000 + 8c7c: 8fd9 or a5,a5,a4 + 8c7e: c15c sw a5,4(a0) + 8c80: 8082 ret + 8c82: fc000737 lui a4,0xfc000 + 8c86: 177d addi a4,a4,-1 + 8c88: 8ff9 and a5,a5,a4 + 8c8a: bfd5 j 8c7e + +00008c8c : + 8c8c: d64f72ef jal t0,1f0 <__riscv_save_0> + 8c90: 1101 addi sp,sp,-32 + 8c92: 842a mv s0,a0 + 8c94: 00010423 sb zero,8(sp) + 8c98: 44a5 li s1,9 + 8c9a: 841c lbu a5,8(sp) + 8c9c: 04f4f963 bgeu s1,a5,8cee + 8ca0: 00010423 sb zero,8(sp) + 8ca4: 46a5 li a3,9 + 8ca6: 4621 li a2,8 + 8ca8: 841c lbu a5,8(sp) + 8caa: 06f6ff63 bgeu a3,a5,8d28 + 8cae: 00011523 sh zero,10(sp) + 8cb2: 00010423 sb zero,8(sp) + 8cb6: 4695 li a3,5 + 8cb8: 841c lbu a5,8(sp) + 8cba: 0ef6f163 bgeu a3,a5,8d9c + 8cbe: 8538 lhu a4,10(sp) + 8cc0: 853c lhu a5,10(sp) + 8cc2: 4699 li a3,6 + 8cc4: 460d li a2,3 + 8cc6: 02d7f7b3 remu a5,a5,a3 + 8cca: 6505 lui a0,0x1 + 8ccc: 80050513 addi a0,a0,-2048 # 800 <__stack_size> + 8cd0: 02c7d7b3 divu a5,a5,a2 + 8cd4: 02d75733 divu a4,a4,a3 + 8cd8: 97ba add a5,a5,a4 + 8cda: 07c2 slli a5,a5,0x10 + 8cdc: 83c1 srli a5,a5,0x10 + 8cde: 857c sh a5,10(sp) + 8ce0: 853c lhu a5,10(sp) + 8ce2: 6105 addi sp,sp,32 + 8ce4: 8d1d sub a0,a0,a5 + 8ce6: 0542 slli a0,a0,0x10 + 8ce8: 8541 srai a0,a0,0x10 + 8cea: d2af706f j 214 <__riscv_restore_0> + 8cee: 441c lw a5,8(s0) + 8cf0: 0087e793 ori a5,a5,8 + 8cf4: c41c sw a5,8(s0) + 8cf6: 8522 mv a0,s0 + 8cf8: e61ff0ef jal ra,8b58 + 8cfc: fd6d bnez a0,8cf6 + 8cfe: 441c lw a5,8(s0) + 8d00: 0047e793 ori a5,a5,4 + 8d04: c41c sw a5,8(s0) + 8d06: 8522 mv a0,s0 + 8d08: e63ff0ef jal ra,8b6a + 8d0c: fd6d bnez a0,8d06 + 8d0e: 4478 lw a4,76(s0) + 8d10: 841c lbu a5,8(sp) + 8d12: 1014 addi a3,sp,32 + 8d14: 0786 slli a5,a5,0x1 + 8d16: 97b6 add a5,a5,a3 + 8d18: fee79623 sh a4,-20(a5) + 8d1c: 841c lbu a5,8(sp) + 8d1e: 0785 addi a5,a5,1 + 8d20: 0ff7f793 andi a5,a5,255 + 8d24: 845c sb a5,8(sp) + 8d26: bf95 j 8c9a + 8d28: 000104a3 sb zero,9(sp) + 8d2c: 849c lbu a5,9(sp) + 8d2e: 00f67863 bgeu a2,a5,8d3e + 8d32: 841c lbu a5,8(sp) + 8d34: 0785 addi a5,a5,1 + 8d36: 0ff7f793 andi a5,a5,255 + 8d3a: 845c sb a5,8(sp) + 8d3c: b7b5 j 8ca8 + 8d3e: 8498 lbu a4,9(sp) + 8d40: 849c lbu a5,9(sp) + 8d42: 100c addi a1,sp,32 + 8d44: 0706 slli a4,a4,0x1 + 8d46: 0785 addi a5,a5,1 + 8d48: 0786 slli a5,a5,0x1 + 8d4a: 972e add a4,a4,a1 + 8d4c: 97ae add a5,a5,a1 + 8d4e: fec75703 lhu a4,-20(a4) # fbffffec <_eusrstack+0xdbff7fec> + 8d52: fec7d783 lhu a5,-20(a5) + 8d56: 02e7fd63 bgeu a5,a4,8d90 + 8d5a: 849c lbu a5,9(sp) + 8d5c: 0786 slli a5,a5,0x1 + 8d5e: 97ae add a5,a5,a1 + 8d60: fec7d783 lhu a5,-20(a5) + 8d64: 857c sh a5,10(sp) + 8d66: 849c lbu a5,9(sp) + 8d68: 8498 lbu a4,9(sp) + 8d6a: 0785 addi a5,a5,1 + 8d6c: 0786 slli a5,a5,0x1 + 8d6e: 97ae add a5,a5,a1 + 8d70: fec7d583 lhu a1,-20(a5) + 8d74: 00171793 slli a5,a4,0x1 + 8d78: 1018 addi a4,sp,32 + 8d7a: 97ba add a5,a5,a4 + 8d7c: feb79623 sh a1,-20(a5) + 8d80: 849c lbu a5,9(sp) + 8d82: 8538 lhu a4,10(sp) + 8d84: 100c addi a1,sp,32 + 8d86: 0785 addi a5,a5,1 + 8d88: 0786 slli a5,a5,0x1 + 8d8a: 97ae add a5,a5,a1 + 8d8c: fee79623 sh a4,-20(a5) + 8d90: 849c lbu a5,9(sp) + 8d92: 0785 addi a5,a5,1 + 8d94: 0ff7f793 andi a5,a5,255 + 8d98: 84dc sb a5,9(sp) + 8d9a: bf49 j 8d2c + 8d9c: 841c lbu a5,8(sp) + 8d9e: 1010 addi a2,sp,32 + 8da0: 8538 lhu a4,10(sp) + 8da2: 0789 addi a5,a5,2 + 8da4: 0786 slli a5,a5,0x1 + 8da6: 97b2 add a5,a5,a2 + 8da8: fec7d783 lhu a5,-20(a5) + 8dac: 97ba add a5,a5,a4 + 8dae: 07c2 slli a5,a5,0x10 + 8db0: 83c1 srli a5,a5,0x10 + 8db2: 857c sh a5,10(sp) + 8db4: 841c lbu a5,8(sp) + 8db6: 0785 addi a5,a5,1 + 8db8: 0ff7f793 andi a5,a5,255 + 8dbc: 845c sb a5,8(sp) + 8dbe: bded j 8cb8 + +00008dc0 : + 8dc0: c30f72ef jal t0,1f0 <__riscv_save_0> + 8dc4: 4505 li a0,1 + 8dc6: 2e4d jal 9178 + 8dc8: 4501 li a0,0 + 8dca: 267d jal 9178 + 8dcc: c48f706f j 214 <__riscv_restore_0> + +00008dd0 : + 8dd0: 1141 addi sp,sp,-16 + 8dd2: 400077b7 lui a5,0x40007 + 8dd6: c602 sw zero,12(sp) + 8dd8: c0078793 addi a5,a5,-1024 # 40006c00 <_eusrstack+0x1fffec00> + 8ddc: c63e sw a5,12(sp) + 8dde: 47b2 lw a5,12(sp) + 8de0: 953e add a0,a0,a5 + 8de2: c62a sw a0,12(sp) + 8de4: 47b2 lw a5,12(sp) + 8de6: c38c sw a1,0(a5) + 8de8: 0141 addi sp,sp,16 + 8dea: 8082 ret + +00008dec : + 8dec: 1ffff7b7 lui a5,0x1ffff + 8df0: 7047a503 lw a0,1796(a5) # 1ffff704 <_data_lma+0x1fff14a8> + 8df4: 8082 ret + +00008df6 : + 8df6: 459c lw a5,8(a1) + 8df8: 0107f713 andi a4,a5,16 + 8dfc: 00f7f813 andi a6,a5,15 + 8e00: c701 beqz a4,8e08 + 8e02: 41d8 lw a4,4(a1) + 8e04: 00e86833 or a6,a6,a4 + 8e08: 218e lhu a1,0(a1) + 8e0a: 0ff5f713 andi a4,a1,255 + 8e0e: c339 beqz a4,8e54 + 8e10: 4118 lw a4,0(a0) + 8e12: 4681 li a3,0 + 8e14: 4e85 li t4,1 + 8e16: 4f3d li t5,15 + 8e18: 02800f93 li t6,40 + 8e1c: 04800293 li t0,72 + 8e20: 4e21 li t3,8 + 8e22: 00de9633 sll a2,t4,a3 + 8e26: 00c5f8b3 and a7,a1,a2 + 8e2a: 03161163 bne a2,a7,8e4c + 8e2e: 00269893 slli a7,a3,0x2 + 8e32: 011f1333 sll t1,t5,a7 + 8e36: fff34313 not t1,t1 + 8e3a: 00e37733 and a4,t1,a4 + 8e3e: 011818b3 sll a7,a6,a7 + 8e42: 00e8e733 or a4,a7,a4 + 8e46: 05f79f63 bne a5,t6,8ea4 + 8e4a: c950 sw a2,20(a0) + 8e4c: 0685 addi a3,a3,1 + 8e4e: fdc69ae3 bne a3,t3,8e22 + 8e52: c118 sw a4,0(a0) + 8e54: 0ff00713 li a4,255 + 8e58: 04b77563 bgeu a4,a1,8ea2 + 8e5c: 4154 lw a3,4(a0) + 8e5e: 4621 li a2,8 + 8e60: 4e85 li t4,1 + 8e62: 4f3d li t5,15 + 8e64: 02800f93 li t6,40 + 8e68: 04800293 li t0,72 + 8e6c: 4e41 li t3,16 + 8e6e: 00ce98b3 sll a7,t4,a2 + 8e72: 0115f733 and a4,a1,a7 + 8e76: 02e89263 bne a7,a4,8e9a + 8e7a: 00261713 slli a4,a2,0x2 + 8e7e: 1701 addi a4,a4,-32 + 8e80: 00ef1333 sll t1,t5,a4 + 8e84: fff34313 not t1,t1 + 8e88: 00d376b3 and a3,t1,a3 + 8e8c: 00e81733 sll a4,a6,a4 + 8e90: 8ed9 or a3,a3,a4 + 8e92: 01f79d63 bne a5,t6,8eac + 8e96: 01152a23 sw a7,20(a0) + 8e9a: 0605 addi a2,a2,1 + 8e9c: fdc619e3 bne a2,t3,8e6e + 8ea0: c154 sw a3,4(a0) + 8ea2: 8082 ret + 8ea4: fa5794e3 bne a5,t0,8e4c + 8ea8: c910 sw a2,16(a0) + 8eaa: b74d j 8e4c + 8eac: fe5797e3 bne a5,t0,8e9a + 8eb0: 01152823 sw a7,16(a0) + 8eb4: b7dd j 8e9a + +00008eb6 : + 8eb6: 4508 lw a0,8(a0) + 8eb8: 8d6d and a0,a0,a1 + 8eba: 00a03533 snez a0,a0 + 8ebe: 8082 ret + +00008ec0 : + 8ec0: c219 beqz a2,8ec6 + 8ec2: c90c sw a1,16(a0) + 8ec4: 8082 ret + 8ec6: c94c sw a1,20(a0) + 8ec8: 8082 ret + +00008eca : + 8eca: 82a1aa23 sw a0,-1996(gp) # 20000224 + 8ece: 8082 ret + +00008ed0 : + 8ed0: 8341a703 lw a4,-1996(gp) # 20000224 + 8ed4: 4789 li a5,2 + 8ed6: 2110 lbu a2,0(a0) + 8ed8: 02f71163 bne a4,a5,8efa + 8edc: 3114 lbu a3,1(a0) + 8ede: 478d li a5,3 + 8ee0: 00d7ed63 bltu a5,a3,8efa + 8ee4: 213c lbu a5,2(a0) + 8ee6: 069a slli a3,a3,0x6 + 8ee8: e000e737 lui a4,0xe000e + 8eec: 0796 slli a5,a5,0x5 + 8eee: 8fd5 or a5,a5,a3 + 8ef0: 0ff7f793 andi a5,a5,255 + 8ef4: 9732 add a4,a4,a2 + 8ef6: 40f70023 sb a5,1024(a4) # e000e400 <_eusrstack+0xc0006400> + 8efa: 4154 lw a3,4(a0) + 8efc: 4705 li a4,1 + 8efe: 00565793 srli a5,a2,0x5 + 8f02: 00c71733 sll a4,a4,a2 + 8f06: ca89 beqz a3,8f18 + 8f08: 04078793 addi a5,a5,64 + 8f0c: 078a slli a5,a5,0x2 + 8f0e: e000e6b7 lui a3,0xe000e + 8f12: 97b6 add a5,a5,a3 + 8f14: c398 sw a4,0(a5) + 8f16: 8082 ret + 8f18: 06078793 addi a5,a5,96 + 8f1c: e000e6b7 lui a3,0xe000e + 8f20: 078a slli a5,a5,0x2 + 8f22: 97b6 add a5,a5,a3 + 8f24: c398 sw a4,0(a5) + 8f26: 0000100f fence.i + 8f2a: 8082 ret + +00008f2c : + 8f2c: 40007737 lui a4,0x40007 + 8f30: 431c lw a5,0(a4) + 8f32: c509 beqz a0,8f3c + 8f34: 1007e793 ori a5,a5,256 + 8f38: c31c sw a5,0(a4) + 8f3a: 8082 ret + 8f3c: eff7f793 andi a5,a5,-257 + 8f40: bfe5 j 8f38 + +00008f42 : + 8f42: 400216b7 lui a3,0x40021 + 8f46: 42dc lw a5,4(a3) + 8f48: 7751 lui a4,0xffff4 + 8f4a: 177d addi a4,a4,-1 + 8f4c: 8ff9 and a5,a5,a4 + 8f4e: 8d5d or a0,a0,a5 + 8f50: c2c8 sw a0,4(a3) + 8f52: 8082 ret + +00008f54 : + 8f54: 400217b7 lui a5,0x40021 + 8f58: 02078023 sb zero,32(a5) # 40021020 <_eusrstack+0x20019020> + 8f5c: 02078023 sb zero,32(a5) + 8f60: 4705 li a4,1 + 8f62: 00e50663 beq a0,a4,8f6e + 8f66: 4711 li a4,4 + 8f68: 00e50663 beq a0,a4,8f74 + 8f6c: 8082 ret + 8f6e: 02a78023 sb a0,32(a5) + 8f72: 8082 ret + 8f74: 4715 li a4,5 + 8f76: 02e78023 sb a4,32(a5) + 8f7a: 8082 ret + +00008f7c : + 8f7c: 40021737 lui a4,0x40021 + 8f80: 531c lw a5,32(a4) + 8f82: 8d5d or a0,a0,a5 + 8f84: d308 sw a0,32(a4) + 8f86: 8082 ret + +00008f88 : + 8f88: c901 beqz a0,8f98 + 8f8a: 40021737 lui a4,0x40021 + 8f8e: 531c lw a5,32(a4) + 8f90: 66a1 lui a3,0x8 + 8f92: 8fd5 or a5,a5,a3 + 8f94: d31c sw a5,32(a4) + 8f96: 8082 ret + 8f98: 400216b7 lui a3,0x40021 + 8f9c: 529c lw a5,32(a3) + 8f9e: 7761 lui a4,0xffff8 + 8fa0: 177d addi a4,a4,-1 + 8fa2: 8ff9 and a5,a5,a4 + 8fa4: d29c sw a5,32(a3) + 8fa6: 8082 ret + +00008fa8 : + 8fa8: 40021737 lui a4,0x40021 + 8fac: 435c lw a5,4(a4) + 8fae: 4691 li a3,4 + 8fb0: 8bb1 andi a5,a5,12 + 8fb2: 00d78563 beq a5,a3,8fbc + 8fb6: 46a1 li a3,8 + 8fb8: 06d78263 beq a5,a3,901c + 8fbc: 007a17b7 lui a5,0x7a1 + 8fc0: 20078793 addi a5,a5,512 # 7a1200 <_data_lma+0x792fa4> + 8fc4: c11c sw a5,0(a0) + 8fc6: 40021637 lui a2,0x40021 + 8fca: 425c lw a5,4(a2) + 8fcc: 20000737 lui a4,0x20000 + 8fd0: 01070713 addi a4,a4,16 # 20000010 + 8fd4: 8391 srli a5,a5,0x4 + 8fd6: 8bbd andi a5,a5,15 + 8fd8: 97ba add a5,a5,a4 + 8fda: 2394 lbu a3,0(a5) + 8fdc: 411c lw a5,0(a0) + 8fde: 00d7d7b3 srl a5,a5,a3 + 8fe2: c15c sw a5,4(a0) + 8fe4: 4254 lw a3,4(a2) + 8fe6: 82a1 srli a3,a3,0x8 + 8fe8: 8a9d andi a3,a3,7 + 8fea: 96ba add a3,a3,a4 + 8fec: 2294 lbu a3,0(a3) + 8fee: 00d7d6b3 srl a3,a5,a3 + 8ff2: c514 sw a3,8(a0) + 8ff4: 4254 lw a3,4(a2) + 8ff6: 82ad srli a3,a3,0xb + 8ff8: 8a9d andi a3,a3,7 + 8ffa: 9736 add a4,a4,a3 + 8ffc: 2318 lbu a4,0(a4) + 8ffe: 00e7d7b3 srl a5,a5,a4 + 9002: c55c sw a5,12(a0) + 9004: 4258 lw a4,4(a2) + 9006: 8339 srli a4,a4,0xe + 9008: 00377693 andi a3,a4,3 + 900c: 80418713 addi a4,gp,-2044 # 200001f4 + 9010: 9736 add a4,a4,a3 + 9012: 2318 lbu a4,0(a4) + 9014: 02e7d7b3 divu a5,a5,a4 + 9018: c91c sw a5,16(a0) + 901a: 8082 ret + 901c: 435c lw a5,4(a4) + 901e: 4358 lw a4,4(a4) + 9020: 66c1 lui a3,0x10 + 9022: 83c9 srli a5,a5,0x12 + 9024: 8f75 and a4,a4,a3 + 9026: 1ffff6b7 lui a3,0x1ffff + 902a: 70c6a683 lw a3,1804(a3) # 1ffff70c <_data_lma+0x1fff14b0> + 902e: 8bbd andi a5,a5,15 + 9030: 0789 addi a5,a5,2 + 9032: 01169613 slli a2,a3,0x11 + 9036: 00064863 bltz a2,9046 + 903a: 46c5 li a3,17 + 903c: 4601 li a2,0 + 903e: 02d79263 bne a5,a3,9062 + 9042: 47c9 li a5,18 + 9044: a839 j 9062 + 9046: 4689 li a3,2 + 9048: 02d78f63 beq a5,a3,9086 + 904c: 46bd li a3,15 + 904e: 02d78e63 beq a5,a3,908a + 9052: 46c1 li a3,16 + 9054: 02d78e63 beq a5,a3,9090 + 9058: 46c5 li a3,17 + 905a: 4601 li a2,0 + 905c: 00d79363 bne a5,a3,9062 + 9060: 47c1 li a5,16 + 9062: ef1d bnez a4,90a0 + 9064: 40024737 lui a4,0x40024 + 9068: 80072703 lw a4,-2048(a4) # 40023800 <_eusrstack+0x2001b800> + 906c: 8b41 andi a4,a4,16 + 906e: c705 beqz a4,9096 + 9070: 007a1737 lui a4,0x7a1 + 9074: 20070713 addi a4,a4,512 # 7a1200 <_data_lma+0x792fa4> + 9078: 02f707b3 mul a5,a4,a5 + 907c: c11c sw a5,0(a0) + 907e: d621 beqz a2,8fc6 + 9080: 411c lw a5,0(a0) + 9082: 8385 srli a5,a5,0x1 + 9084: b781 j 8fc4 + 9086: 4601 li a2,0 + 9088: bf6d j 9042 + 908a: 4605 li a2,1 + 908c: 47b5 li a5,13 + 908e: bfd1 j 9062 + 9090: 4601 li a2,0 + 9092: 47bd li a5,15 + 9094: b7f9 j 9062 + 9096: 003d1737 lui a4,0x3d1 + 909a: 90070713 addi a4,a4,-1792 # 3d0900 <_data_lma+0x3c26a4> + 909e: bfe9 j 9078 + 90a0: 400215b7 lui a1,0x40021 + 90a4: 55d8 lw a4,44(a1) + 90a6: 00f71693 slli a3,a4,0xf + 90aa: 55d8 lw a4,44(a1) + 90ac: 0406df63 bgez a3,910a + 90b0: 8311 srli a4,a4,0x4 + 90b2: 8b3d andi a4,a4,15 + 90b4: 00170693 addi a3,a4,1 + 90b8: 007a1737 lui a4,0x7a1 + 90bc: 20070713 addi a4,a4,512 # 7a1200 <_data_lma+0x792fa4> + 90c0: 02d75733 divu a4,a4,a3 + 90c4: c118 sw a4,0(a0) + 90c6: 55d4 lw a3,44(a1) + 90c8: 82a1 srli a3,a3,0x8 + 90ca: 8abd andi a3,a3,15 + 90cc: e28d bnez a3,90ee + 90ce: 4695 li a3,5 + 90d0: 02d70733 mul a4,a4,a3 + 90d4: 8305 srli a4,a4,0x1 + 90d6: c118 sw a4,0(a0) + 90d8: 40021737 lui a4,0x40021 + 90dc: 5758 lw a4,44(a4) + 90de: 4114 lw a3,0(a0) + 90e0: 8b3d andi a4,a4,15 + 90e2: 0705 addi a4,a4,1 + 90e4: 02e6d733 divu a4,a3,a4 + 90e8: c118 sw a4,0(a0) + 90ea: 4118 lw a4,0(a0) + 90ec: b771 j 9078 + 90ee: 4585 li a1,1 + 90f0: 00b69463 bne a3,a1,90f8 + 90f4: 46e5 li a3,25 + 90f6: bfe9 j 90d0 + 90f8: 45bd li a1,15 + 90fa: 00b69663 bne a3,a1,9106 + 90fe: 46d1 li a3,20 + 9100: 02e68733 mul a4,a3,a4 + 9104: bfc9 j 90d6 + 9106: 0689 addi a3,a3,2 + 9108: bfe5 j 9100 + 910a: 8b3d andi a4,a4,15 + 910c: 00170693 addi a3,a4,1 # 40021001 <_eusrstack+0x20019001> + 9110: 007a1737 lui a4,0x7a1 + 9114: 20070713 addi a4,a4,512 # 7a1200 <_data_lma+0x792fa4> + 9118: 02d75733 divu a4,a4,a3 + 911c: b7f1 j 90e8 + +0000911e : + 911e: c599 beqz a1,912c + 9120: 40021737 lui a4,0x40021 + 9124: 4f1c lw a5,24(a4) + 9126: 8d5d or a0,a0,a5 + 9128: cf08 sw a0,24(a4) + 912a: 8082 ret + 912c: 400217b7 lui a5,0x40021 + 9130: 4f98 lw a4,24(a5) + 9132: fff54513 not a0,a0 + 9136: 8d79 and a0,a0,a4 + 9138: cf88 sw a0,24(a5) + 913a: 8082 ret + +0000913c : + 913c: c599 beqz a1,914a + 913e: 40021737 lui a4,0x40021 + 9142: 4f5c lw a5,28(a4) + 9144: 8d5d or a0,a0,a5 + 9146: cf48 sw a0,28(a4) + 9148: 8082 ret + 914a: 400217b7 lui a5,0x40021 + 914e: 4fd8 lw a4,28(a5) + 9150: fff54513 not a0,a0 + 9154: 8d79 and a0,a0,a4 + 9156: cfc8 sw a0,28(a5) + 9158: 8082 ret + +0000915a : + 915a: c599 beqz a1,9168 + 915c: 40021737 lui a4,0x40021 + 9160: 475c lw a5,12(a4) + 9162: 8d5d or a0,a0,a5 + 9164: c748 sw a0,12(a4) + 9166: 8082 ret + 9168: 400217b7 lui a5,0x40021 + 916c: 47d8 lw a4,12(a5) + 916e: fff54513 not a0,a0 + 9172: 8d79 and a0,a0,a4 + 9174: c7c8 sw a0,12(a5) + 9176: 8082 ret + +00009178 : + 9178: c901 beqz a0,9188 + 917a: 40021737 lui a4,0x40021 + 917e: 531c lw a5,32(a4) + 9180: 66c1 lui a3,0x10 + 9182: 8fd5 or a5,a5,a3 + 9184: d31c sw a5,32(a4) + 9186: 8082 ret + 9188: 400216b7 lui a3,0x40021 + 918c: 529c lw a5,32(a3) + 918e: 7741 lui a4,0xffff0 + 9190: 177d addi a4,a4,-1 + 9192: 8ff9 and a5,a5,a4 + 9194: d29c sw a5,32(a3) + 9196: 8082 ret + +00009198 : + 9198: 00555793 srli a5,a0,0x5 + 919c: 4705 li a4,1 + 919e: 00e79963 bne a5,a4,91b0 + 91a2: 400217b7 lui a5,0x40021 + 91a6: 439c lw a5,0(a5) + 91a8: 00a7d533 srl a0,a5,a0 + 91ac: 8905 andi a0,a0,1 + 91ae: 8082 ret + 91b0: 4709 li a4,2 + 91b2: 00e79663 bne a5,a4,91be + 91b6: 400217b7 lui a5,0x40021 + 91ba: 539c lw a5,32(a5) + 91bc: b7f5 j 91a8 + 91be: 400217b7 lui a5,0x40021 + 91c2: 53dc lw a5,36(a5) + 91c4: b7d5 j 91a8 + +000091c6 : + 91c6: 400037b7 lui a5,0x40003 + 91ca: 8007d703 lhu a4,-2048(a5) # 40002800 <_eusrstack+0x1fffa800> + 91ce: c589 beqz a1,91d8 + 91d0: 8d59 or a0,a0,a4 + 91d2: 80a79023 sh a0,-2048(a5) + 91d6: 8082 ret + 91d8: fff54513 not a0,a0 + 91dc: 8d79 and a0,a0,a4 + 91de: bfd5 j 91d2 + +000091e0 : + 91e0: 400037b7 lui a5,0x40003 + 91e4: 8047d703 lhu a4,-2044(a5) # 40002804 <_eusrstack+0x1fffa804> + 91e8: 01076713 ori a4,a4,16 + 91ec: 80e79223 sh a4,-2044(a5) + 91f0: 8082 ret + +000091f2 : + 91f2: 40003737 lui a4,0x40003 + 91f6: 80475783 lhu a5,-2044(a4) # 40002804 <_eusrstack+0x1fffa804> + 91fa: 07c2 slli a5,a5,0x10 + 91fc: 83c1 srli a5,a5,0x10 + 91fe: 9bbd andi a5,a5,-17 + 9200: 07c2 slli a5,a5,0x10 + 9202: 83c1 srli a5,a5,0x10 + 9204: 80f71223 sh a5,-2044(a4) + 9208: 8082 ret + +0000920a : + 920a: 40003637 lui a2,0x40003 + 920e: 81865683 lhu a3,-2024(a2) # 40002818 <_eusrstack+0x1fffa818> + 9212: 81865703 lhu a4,-2024(a2) + 9216: 0742 slli a4,a4,0x10 + 9218: 8341 srli a4,a4,0x10 + 921a: fed71ae3 bne a4,a3,920e + 921e: 40003637 lui a2,0x40003 + 9222: 81c65683 lhu a3,-2020(a2) # 4000281c <_eusrstack+0x1fffa81c> + 9226: 81c65783 lhu a5,-2020(a2) + 922a: 07c2 slli a5,a5,0x10 + 922c: 83c1 srli a5,a5,0x10 + 922e: fed79ae3 bne a5,a3,9222 + 9232: 400035b7 lui a1,0x40003 + 9236: 8185d603 lhu a2,-2024(a1) # 40002818 <_eusrstack+0x1fffa818> + 923a: 8185d503 lhu a0,-2024(a1) + 923e: 0542 slli a0,a0,0x10 + 9240: 8141 srli a0,a0,0x10 + 9242: fec51ae3 bne a0,a2,9236 + 9246: 00a70c63 beq a4,a0,925e + 924a: 400036b7 lui a3,0x40003 + 924e: 81c6d703 lhu a4,-2020(a3) # 4000281c <_eusrstack+0x1fffa81c> + 9252: 81c6d783 lhu a5,-2020(a3) + 9256: 07c2 slli a5,a5,0x10 + 9258: 83c1 srli a5,a5,0x10 + 925a: fee79ae3 bne a5,a4,924e + 925e: 0542 slli a0,a0,0x10 + 9260: 8d5d or a0,a0,a5 + 9262: 8082 ret + +00009264 : + 9264: f8df62ef jal t0,1f0 <__riscv_save_0> + 9268: 1141 addi sp,sp,-16 + 926a: c62a sw a0,12(sp) + 926c: f75ff0ef jal ra,91e0 + 9270: 4532 lw a0,12(sp) + 9272: 400037b7 lui a5,0x40003 + 9276: 01055713 srli a4,a0,0x10 + 927a: 0542 slli a0,a0,0x10 + 927c: 80e79c23 sh a4,-2024(a5) # 40002818 <_eusrstack+0x1fffa818> + 9280: 8141 srli a0,a0,0x10 + 9282: 80a79e23 sh a0,-2020(a5) + 9286: f6dff0ef jal ra,91f2 + 928a: 0141 addi sp,sp,16 + 928c: f89f606f j 214 <__riscv_restore_0> + +00009290 : + 9290: f61f62ef jal t0,1f0 <__riscv_save_0> + 9294: 1141 addi sp,sp,-16 + 9296: c62a sw a0,12(sp) + 9298: f49ff0ef jal ra,91e0 + 929c: 4532 lw a0,12(sp) + 929e: 400037b7 lui a5,0x40003 + 92a2: 01055713 srli a4,a0,0x10 + 92a6: 8b3d andi a4,a4,15 + 92a8: 0542 slli a0,a0,0x10 + 92aa: 80e79423 sh a4,-2040(a5) # 40002808 <_eusrstack+0x1fffa808> + 92ae: 8141 srli a0,a0,0x10 + 92b0: 80a79623 sh a0,-2036(a5) + 92b4: f3fff0ef jal ra,91f2 + 92b8: 0141 addi sp,sp,16 + 92ba: f5bf606f j 214 <__riscv_restore_0> + +000092be : + 92be: 40003737 lui a4,0x40003 + 92c2: 80475783 lhu a5,-2044(a4) # 40002804 <_eusrstack+0x1fffa804> + 92c6: 0207f793 andi a5,a5,32 + 92ca: dfe5 beqz a5,92c2 + 92cc: 8082 ret + +000092ce : + 92ce: 40003737 lui a4,0x40003 + 92d2: 80475783 lhu a5,-2044(a4) # 40002804 <_eusrstack+0x1fffa804> + 92d6: 07c2 slli a5,a5,0x10 + 92d8: 83c1 srli a5,a5,0x10 + 92da: 9bdd andi a5,a5,-9 + 92dc: 07c2 slli a5,a5,0x10 + 92de: 83c1 srli a5,a5,0x10 + 92e0: 80f71223 sh a5,-2044(a4) + 92e4: 40003737 lui a4,0x40003 + 92e8: 80475783 lhu a5,-2044(a4) # 40002804 <_eusrstack+0x1fffa804> + 92ec: 8ba1 andi a5,a5,8 + 92ee: dfed beqz a5,92e8 + 92f0: 8082 ret + +000092f2 : + 92f2: 400037b7 lui a5,0x40003 + 92f6: 8047d703 lhu a4,-2044(a5) # 40002804 <_eusrstack+0x1fffa804> + 92fa: fff54513 not a0,a0 + 92fe: 8d79 and a0,a0,a4 + 9300: 80a79223 sh a0,-2044(a5) + 9304: 8082 ret + +00009306 : + 9306: eebf62ef jal t0,1f0 <__riscv_save_0> + 930a: fe9ff0ef jal ra,92f2 + 930e: f07f606f j 214 <__riscv_restore_0> + +00009312 : + 9312: 211a lhu a4,0(a0) + 9314: 678d lui a5,0x3 + 9316: 04078793 addi a5,a5,64 # 3040 + 931a: 21b6 lhu a3,2(a1) + 931c: 8f7d and a4,a4,a5 + 931e: 219e lhu a5,0(a1) + 9320: 8fd5 or a5,a5,a3 + 9322: 21d6 lhu a3,4(a1) + 9324: 8fd5 or a5,a5,a3 + 9326: 21f6 lhu a3,6(a1) + 9328: 8fd5 or a5,a5,a3 + 932a: 2596 lhu a3,8(a1) + 932c: 8fd5 or a5,a5,a3 + 932e: 25b6 lhu a3,10(a1) + 9330: 8fd5 or a5,a5,a3 + 9332: 25d6 lhu a3,12(a1) + 9334: 8fd5 or a5,a5,a3 + 9336: 25f6 lhu a3,14(a1) + 9338: 8fd5 or a5,a5,a3 + 933a: 8fd9 or a5,a5,a4 + 933c: a11e sh a5,0(a0) + 933e: 2d5a lhu a4,28(a0) + 9340: 77fd lui a5,0xfffff + 9342: 7ff78793 addi a5,a5,2047 # fffff7ff <_eusrstack+0xdfff77ff> + 9346: 8ff9 and a5,a5,a4 + 9348: ad5e sh a5,28(a0) + 934a: 299e lhu a5,16(a1) + 934c: a91e sh a5,16(a0) + 934e: 8082 ret + +00009350 : + 9350: 211e lhu a5,0(a0) + 9352: c589 beqz a1,935c + 9354: 0407e793 ori a5,a5,64 + 9358: a11e sh a5,0(a0) + 935a: 8082 ret + 935c: 07c2 slli a5,a5,0x10 + 935e: 83c1 srli a5,a5,0x10 + 9360: fbf7f793 andi a5,a5,-65 + 9364: 07c2 slli a5,a5,0x10 + 9366: 83c1 srli a5,a5,0x10 + 9368: bfc5 j 9358 + +0000936a : + 936a: a54e sh a1,12(a0) + 936c: 8082 ret + +0000936e : + 936e: 254a lhu a0,12(a0) + 9370: 8082 ret + +00009372 : + 9372: 250a lhu a0,8(a0) + 9374: 8d6d and a0,a0,a1 + 9376: 00a03533 snez a0,a0 + 937a: 8082 ret + +0000937c : + 937c: e75f62ef jal t0,1f0 <__riscv_save_0> + 9380: 2916 lhu a3,16(a0) + 9382: 77f5 lui a5,0xffffd + 9384: 17fd addi a5,a5,-1 + 9386: 8ff5 and a5,a5,a3 + 9388: 21f6 lhu a3,6(a1) + 938a: 25da lhu a4,12(a1) + 938c: 7179 addi sp,sp,-48 + 938e: 8fd5 or a5,a5,a3 + 9390: a91e sh a5,16(a0) + 9392: 2556 lhu a3,12(a0) + 9394: 77fd lui a5,0xfffff + 9396: 9f378793 addi a5,a5,-1549 # ffffe9f3 <_eusrstack+0xdfff69f3> + 939a: 8ff5 and a5,a5,a3 + 939c: 21d6 lhu a3,4(a1) + 939e: 842a mv s0,a0 + 93a0: c62e sw a1,12(sp) + 93a2: 8fd5 or a5,a5,a3 + 93a4: 2596 lhu a3,8(a1) + 93a6: 8fd5 or a5,a5,a3 + 93a8: 25b6 lhu a3,10(a1) + 93aa: 8fd5 or a5,a5,a3 + 93ac: a55e sh a5,12(a0) + 93ae: 295e lhu a5,20(a0) + 93b0: 07c2 slli a5,a5,0x10 + 93b2: 83c1 srli a5,a5,0x10 + 93b4: cff7f793 andi a5,a5,-769 + 93b8: 8fd9 or a5,a5,a4 + 93ba: a95e sh a5,20(a0) + 93bc: 0868 addi a0,sp,28 + 93be: bebff0ef jal ra,8fa8 + 93c2: 400147b7 lui a5,0x40014 + 93c6: 80078793 addi a5,a5,-2048 # 40013800 <_eusrstack+0x2000b800> + 93ca: 45b2 lw a1,12(sp) + 93cc: 02f41e63 bne s0,a5,9408 + 93d0: 57a2 lw a5,40(sp) + 93d2: 4765 li a4,25 + 93d4: 02e787b3 mul a5,a5,a4 + 93d8: 4198 lw a4,0(a1) + 93da: 06400693 li a3,100 + 93de: 070a slli a4,a4,0x2 + 93e0: 02e7d7b3 divu a5,a5,a4 + 93e4: 02d7d733 divu a4,a5,a3 + 93e8: 02d7f7b3 remu a5,a5,a3 + 93ec: 0712 slli a4,a4,0x4 + 93ee: 0792 slli a5,a5,0x4 + 93f0: 03278793 addi a5,a5,50 + 93f4: 02d7d7b3 divu a5,a5,a3 + 93f8: 8bbd andi a5,a5,15 + 93fa: 8fd9 or a5,a5,a4 + 93fc: 07c2 slli a5,a5,0x10 + 93fe: 83c1 srli a5,a5,0x10 + 9400: a41e sh a5,8(s0) + 9402: 6145 addi sp,sp,48 + 9404: e11f606f j 214 <__riscv_restore_0> + 9408: 5792 lw a5,36(sp) + 940a: b7e1 j 93d2 + +0000940c : + 940c: c591 beqz a1,9418 + 940e: 255e lhu a5,12(a0) + 9410: 6709 lui a4,0x2 + 9412: 8fd9 or a5,a5,a4 + 9414: a55e sh a5,12(a0) + 9416: 8082 ret + 9418: 255a lhu a4,12(a0) + 941a: 77f9 lui a5,0xffffe + 941c: 17fd addi a5,a5,-1 + 941e: 8ff9 and a5,a5,a4 + 9420: bfd5 j 9414 + +00009422 : + 9422: 1ff5f593 andi a1,a1,511 + 9426: a14e sh a1,4(a0) + 9428: 8082 ret + +0000942a : + 942a: 214a lhu a0,4(a0) + 942c: 1ff57513 andi a0,a0,511 + 9430: 8082 ret + +00009432 : + 9432: 210a lhu a0,0(a0) + 9434: 8d6d and a0,a0,a1 + 9436: 00a03533 snez a0,a0 + 943a: 8082 ret + +0000943c : + 943c: 200007b7 lui a5,0x20000 + 9440: 1f07a783 lw a5,496(a5) # 200001f0 + 9444: 007a1737 lui a4,0x7a1 + 9448: 20070713 addi a4,a4,512 # 7a1200 <_data_lma+0x792fa4> + 944c: 02e7d7b3 divu a5,a5,a4 + 9450: 0ff7f793 andi a5,a5,255 + 9454: 82f18d23 sb a5,-1990(gp) # 2000022a + 9458: 3e800713 li a4,1000 + 945c: 02e787b3 mul a5,a5,a4 + 9460: 82f19c23 sh a5,-1992(gp) # 20000228 + 9464: 8082 ret + +00009466 : + 9466: e000f7b7 lui a5,0xe000f + 946a: 43d8 lw a4,4(a5) + 946c: 4681 li a3,0 + 946e: 9b79 andi a4,a4,-2 + 9470: c3d8 sw a4,4(a5) + 9472: 8381d703 lhu a4,-1992(gp) # 20000228 + 9476: 02a70633 mul a2,a4,a0 + 947a: cb90 sw a2,16(a5) + 947c: cbd4 sw a3,20(a5) + 947e: 4398 lw a4,0(a5) + 9480: 01076713 ori a4,a4,16 + 9484: c398 sw a4,0(a5) + 9486: 4398 lw a4,0(a5) + 9488: 02176713 ori a4,a4,33 + 948c: c398 sw a4,0(a5) + 948e: 43d8 lw a4,4(a5) + 9490: 8b05 andi a4,a4,1 + 9492: df75 beqz a4,948e + 9494: 4398 lw a4,0(a5) + 9496: 9b79 andi a4,a4,-2 + 9498: c398 sw a4,0(a5) + 949a: 8082 ret + +0000949c <_write>: + 949c: d3bf62ef jal t0,1d6 <__riscv_save_4> + 94a0: 400144b7 lui s1,0x40014 + 94a4: 89ae mv s3,a1 + 94a6: 8932 mv s2,a2 + 94a8: 4401 li s0,0 + 94aa: 80048493 addi s1,s1,-2048 # 40013800 <_eusrstack+0x2000b800> + 94ae: 01244563 blt s0,s2,94b8 <_write+0x1c> + 94b2: 854a mv a0,s2 + 94b4: d57f606f j 20a <__riscv_restore_4> + 94b8: 04000593 li a1,64 + 94bc: 8526 mv a0,s1 + 94be: f75ff0ef jal ra,9432 + 94c2: d97d beqz a0,94b8 <_write+0x1c> + 94c4: 008987b3 add a5,s3,s0 + 94c8: 00078583 lb a1,0(a5) # e000f000 <_eusrstack+0xc0007000> + 94cc: 8526 mv a0,s1 + 94ce: 0405 addi s0,s0,1 + 94d0: 05c2 slli a1,a1,0x10 + 94d2: 81c1 srli a1,a1,0x10 + 94d4: f4fff0ef jal ra,9422 + 94d8: bfd9 j 94ae <_write+0x12> + +000094da <_sbrk>: + 94da: 80818713 addi a4,gp,-2040 # 200001f8 + 94de: 431c lw a5,0(a4) + 94e0: 79018693 addi a3,gp,1936 # 20001180 <_ebss> + 94e4: 953e add a0,a0,a5 + 94e6: 00d56b63 bltu a0,a3,94fc <_sbrk+0x22> + 94ea: 200086b7 lui a3,0x20008 + 94ee: 80068693 addi a3,a3,-2048 # 20007800 <_heap_end> + 94f2: 00a6e563 bltu a3,a0,94fc <_sbrk+0x22> + 94f6: c308 sw a0,0(a4) + 94f8: 853e mv a0,a5 + 94fa: 8082 ret + 94fc: 57fd li a5,-1 + 94fe: bfed j 94f8 <_sbrk+0x1e> + +00009500 <__ashldi3>: + 9500: ce11 beqz a2,951c <__ashldi3+0x1c> + 9502: 02000793 li a5,32 + 9506: 8f91 sub a5,a5,a2 + 9508: 00f05b63 blez a5,951e <__ashldi3+0x1e> + 950c: 00c595b3 sll a1,a1,a2 + 9510: 00f557b3 srl a5,a0,a5 + 9514: 00c51633 sll a2,a0,a2 + 9518: 8ddd or a1,a1,a5 + 951a: 8532 mv a0,a2 + 951c: 8082 ret + 951e: fe060593 addi a1,a2,-32 + 9522: 4601 li a2,0 + 9524: 00b515b3 sll a1,a0,a1 + 9528: 8532 mv a0,a2 + 952a: bfcd j 951c <__ashldi3+0x1c> + +0000952c <__udivdi3>: + 952c: 87b6 mv a5,a3 + 952e: 88b2 mv a7,a2 + 9530: 832a mv t1,a0 + 9532: 882e mv a6,a1 + 9534: 14069b63 bnez a3,968a <__udivdi3+0x15e> + 9538: 0ac5f863 bgeu a1,a2,95e8 <__udivdi3+0xbc> + 953c: 6741 lui a4,0x10 + 953e: 1ae66b63 bltu a2,a4,96f4 <__udivdi3+0x1c8> + 9542: 010007b7 lui a5,0x1000 + 9546: 34f66063 bltu a2,a5,9886 <__udivdi3+0x35a> + 954a: 01865693 srli a3,a2,0x18 + 954e: 47e1 li a5,24 + 9550: 00005717 auipc a4,0x5 + 9554: a6070713 addi a4,a4,-1440 # dfb0 <__clz_tab> + 9558: 9736 add a4,a4,a3 + 955a: 2318 lbu a4,0(a4) + 955c: 97ba add a5,a5,a4 + 955e: 02000713 li a4,32 + 9562: 8f1d sub a4,a4,a5 + 9564: cb19 beqz a4,957a <__udivdi3+0x4e> + 9566: 00e59833 sll a6,a1,a4 + 956a: 00f557b3 srl a5,a0,a5 + 956e: 00e618b3 sll a7,a2,a4 + 9572: 0107e833 or a6,a5,a6 + 9576: 00e51333 sll t1,a0,a4 + 957a: 0108d613 srli a2,a7,0x10 + 957e: 02c85533 divu a0,a6,a2 + 9582: 01089693 slli a3,a7,0x10 + 9586: 82c1 srli a3,a3,0x10 + 9588: 01035793 srli a5,t1,0x10 + 958c: 02c87733 remu a4,a6,a2 + 9590: 02a685b3 mul a1,a3,a0 + 9594: 0742 slli a4,a4,0x10 + 9596: 00f76833 or a6,a4,a5 + 959a: 00b87a63 bgeu a6,a1,95ae <__udivdi3+0x82> + 959e: 9846 add a6,a6,a7 + 95a0: fff50793 addi a5,a0,-1 + 95a4: 01186463 bltu a6,a7,95ac <__udivdi3+0x80> + 95a8: 30b86563 bltu a6,a1,98b2 <__udivdi3+0x386> + 95ac: 853e mv a0,a5 + 95ae: 40b80833 sub a6,a6,a1 + 95b2: 02c85733 divu a4,a6,a2 + 95b6: 0342 slli t1,t1,0x10 + 95b8: 01035313 srli t1,t1,0x10 + 95bc: 02c87833 remu a6,a6,a2 + 95c0: 02e686b3 mul a3,a3,a4 + 95c4: 0842 slli a6,a6,0x10 + 95c6: 00686833 or a6,a6,t1 + 95ca: 00d87b63 bgeu a6,a3,95e0 <__udivdi3+0xb4> + 95ce: 9846 add a6,a6,a7 + 95d0: fff70793 addi a5,a4,-1 + 95d4: 01186563 bltu a6,a7,95de <__udivdi3+0xb2> + 95d8: 1779 addi a4,a4,-2 + 95da: 00d86363 bltu a6,a3,95e0 <__udivdi3+0xb4> + 95de: 873e mv a4,a5 + 95e0: 0542 slli a0,a0,0x10 + 95e2: 8d59 or a0,a0,a4 + 95e4: 4581 li a1,0 + 95e6: 8082 ret + 95e8: e601 bnez a2,95f0 <__udivdi3+0xc4> + 95ea: 4705 li a4,1 + 95ec: 02c758b3 divu a7,a4,a2 + 95f0: 6741 lui a4,0x10 + 95f2: 0ee8e863 bltu a7,a4,96e2 <__udivdi3+0x1b6> + 95f6: 010007b7 lui a5,0x1000 + 95fa: 28f8ea63 bltu a7,a5,988e <__udivdi3+0x362> + 95fe: 0188d693 srli a3,a7,0x18 + 9602: 47e1 li a5,24 + 9604: 00005717 auipc a4,0x5 + 9608: 9ac70713 addi a4,a4,-1620 # dfb0 <__clz_tab> + 960c: 9736 add a4,a4,a3 + 960e: 2314 lbu a3,0(a4) + 9610: 96be add a3,a3,a5 + 9612: 02000793 li a5,32 + 9616: 8f95 sub a5,a5,a3 + 9618: e7fd bnez a5,9706 <__udivdi3+0x1da> + 961a: 01089e93 slli t4,a7,0x10 + 961e: 41158733 sub a4,a1,a7 + 9622: 0108df13 srli t5,a7,0x10 + 9626: 010ede93 srli t4,t4,0x10 + 962a: 4585 li a1,1 + 962c: 01035793 srli a5,t1,0x10 + 9630: 03e75533 divu a0,a4,t5 + 9634: 03e77733 remu a4,a4,t5 + 9638: 03d506b3 mul a3,a0,t4 + 963c: 0742 slli a4,a4,0x10 + 963e: 8fd9 or a5,a5,a4 + 9640: 00d7fa63 bgeu a5,a3,9654 <__udivdi3+0x128> + 9644: 97c6 add a5,a5,a7 + 9646: fff50713 addi a4,a0,-1 + 964a: 0117e463 bltu a5,a7,9652 <__udivdi3+0x126> + 964e: 26d7e563 bltu a5,a3,98b8 <__udivdi3+0x38c> + 9652: 853a mv a0,a4 + 9654: 8f95 sub a5,a5,a3 + 9656: 03e7d733 divu a4,a5,t5 + 965a: 0342 slli t1,t1,0x10 + 965c: 01035313 srli t1,t1,0x10 + 9660: 03e7f7b3 remu a5,a5,t5 + 9664: 03d70eb3 mul t4,a4,t4 + 9668: 07c2 slli a5,a5,0x10 + 966a: 0067e7b3 or a5,a5,t1 + 966e: 01d7fb63 bgeu a5,t4,9684 <__udivdi3+0x158> + 9672: 97c6 add a5,a5,a7 + 9674: fff70693 addi a3,a4,-1 + 9678: 0117e563 bltu a5,a7,9682 <__udivdi3+0x156> + 967c: 1779 addi a4,a4,-2 + 967e: 01d7e363 bltu a5,t4,9684 <__udivdi3+0x158> + 9682: 8736 mv a4,a3 + 9684: 0542 slli a0,a0,0x10 + 9686: 8d59 or a0,a0,a4 + 9688: 8082 ret + 968a: 04d5e163 bltu a1,a3,96cc <__udivdi3+0x1a0> + 968e: 67c1 lui a5,0x10 + 9690: 04f6e163 bltu a3,a5,96d2 <__udivdi3+0x1a6> + 9694: 010007b7 lui a5,0x1000 + 9698: 1ef6e363 bltu a3,a5,987e <__udivdi3+0x352> + 969c: 0186d713 srli a4,a3,0x18 + 96a0: 4861 li a6,24 + 96a2: 00005797 auipc a5,0x5 + 96a6: 90e78793 addi a5,a5,-1778 # dfb0 <__clz_tab> + 96aa: 97ba add a5,a5,a4 + 96ac: 2398 lbu a4,0(a5) + 96ae: 02000e13 li t3,32 + 96b2: 9742 add a4,a4,a6 + 96b4: 40ee0e33 sub t3,t3,a4 + 96b8: 0c0e1a63 bnez t3,978c <__udivdi3+0x260> + 96bc: 1cb6ed63 bltu a3,a1,9896 <__udivdi3+0x36a> + 96c0: 00c53533 sltu a0,a0,a2 + 96c4: 00154513 xori a0,a0,1 + 96c8: 4581 li a1,0 + 96ca: 8082 ret + 96cc: 4581 li a1,0 + 96ce: 4501 li a0,0 + 96d0: 8082 ret + 96d2: 0ff00793 li a5,255 + 96d6: 1cd7f363 bgeu a5,a3,989c <__udivdi3+0x370> + 96da: 0086d713 srli a4,a3,0x8 + 96de: 4821 li a6,8 + 96e0: b7c9 j 96a2 <__udivdi3+0x176> + 96e2: 0ff00713 li a4,255 + 96e6: 86c6 mv a3,a7 + 96e8: f1177ee3 bgeu a4,a7,9604 <__udivdi3+0xd8> + 96ec: 0088d693 srli a3,a7,0x8 + 96f0: 47a1 li a5,8 + 96f2: bf09 j 9604 <__udivdi3+0xd8> + 96f4: 0ff00713 li a4,255 + 96f8: 86b2 mv a3,a2 + 96fa: e4c77be3 bgeu a4,a2,9550 <__udivdi3+0x24> + 96fe: 00865693 srli a3,a2,0x8 + 9702: 47a1 li a5,8 + 9704: b5b1 j 9550 <__udivdi3+0x24> + 9706: 00f898b3 sll a7,a7,a5 + 970a: 00d5d633 srl a2,a1,a3 + 970e: 0108df13 srli t5,a7,0x10 + 9712: 03e65e33 divu t3,a2,t5 + 9716: 00f59733 sll a4,a1,a5 + 971a: 00d556b3 srl a3,a0,a3 + 971e: 8f55 or a4,a4,a3 + 9720: 01089e93 slli t4,a7,0x10 + 9724: 010ede93 srli t4,t4,0x10 + 9728: 00f51333 sll t1,a0,a5 + 972c: 01075593 srli a1,a4,0x10 + 9730: 03e676b3 remu a3,a2,t5 + 9734: 03ce87b3 mul a5,t4,t3 + 9738: 06c2 slli a3,a3,0x10 + 973a: 8ecd or a3,a3,a1 + 973c: 00f6fb63 bgeu a3,a5,9752 <__udivdi3+0x226> + 9740: 96c6 add a3,a3,a7 + 9742: fffe0613 addi a2,t3,-1 + 9746: 1716e463 bltu a3,a7,98ae <__udivdi3+0x382> + 974a: 16f6f263 bgeu a3,a5,98ae <__udivdi3+0x382> + 974e: 1e79 addi t3,t3,-2 + 9750: 96c6 add a3,a3,a7 + 9752: 8e9d sub a3,a3,a5 + 9754: 03e6d633 divu a2,a3,t5 + 9758: 01071793 slli a5,a4,0x10 + 975c: 83c1 srli a5,a5,0x10 + 975e: 03e6f6b3 remu a3,a3,t5 + 9762: 02ce8533 mul a0,t4,a2 + 9766: 01069713 slli a4,a3,0x10 + 976a: 8f5d or a4,a4,a5 + 976c: 00a77b63 bgeu a4,a0,9782 <__udivdi3+0x256> + 9770: 9746 add a4,a4,a7 + 9772: fff60793 addi a5,a2,-1 + 9776: 13176863 bltu a4,a7,98a6 <__udivdi3+0x37a> + 977a: 12a77663 bgeu a4,a0,98a6 <__udivdi3+0x37a> + 977e: 1679 addi a2,a2,-2 + 9780: 9746 add a4,a4,a7 + 9782: 010e1593 slli a1,t3,0x10 + 9786: 8f09 sub a4,a4,a0 + 9788: 8dd1 or a1,a1,a2 + 978a: b54d j 962c <__udivdi3+0x100> + 978c: 00e657b3 srl a5,a2,a4 + 9790: 01c696b3 sll a3,a3,t3 + 9794: 8edd or a3,a3,a5 + 9796: 00e5d333 srl t1,a1,a4 + 979a: 0106df13 srli t5,a3,0x10 + 979e: 03e357b3 divu a5,t1,t5 + 97a2: 01069e93 slli t4,a3,0x10 + 97a6: 010ede93 srli t4,t4,0x10 + 97aa: 01c59833 sll a6,a1,t3 + 97ae: 00e55733 srl a4,a0,a4 + 97b2: 01076833 or a6,a4,a6 + 97b6: 01085893 srli a7,a6,0x10 + 97ba: 01c61633 sll a2,a2,t3 + 97be: 03e37333 remu t1,t1,t5 + 97c2: 02fe85b3 mul a1,t4,a5 + 97c6: 0342 slli t1,t1,0x10 + 97c8: 011368b3 or a7,t1,a7 + 97cc: 00b8fb63 bgeu a7,a1,97e2 <__udivdi3+0x2b6> + 97d0: 98b6 add a7,a7,a3 + 97d2: fff78713 addi a4,a5,-1 + 97d6: 0cd8ea63 bltu a7,a3,98aa <__udivdi3+0x37e> + 97da: 0cb8f863 bgeu a7,a1,98aa <__udivdi3+0x37e> + 97de: 17f9 addi a5,a5,-2 + 97e0: 98b6 add a7,a7,a3 + 97e2: 40b888b3 sub a7,a7,a1 + 97e6: 03e8d733 divu a4,a7,t5 + 97ea: 0842 slli a6,a6,0x10 + 97ec: 01085813 srli a6,a6,0x10 + 97f0: 03e8f8b3 remu a7,a7,t5 + 97f4: 02ee8333 mul t1,t4,a4 + 97f8: 08c2 slli a7,a7,0x10 + 97fa: 0108e5b3 or a1,a7,a6 + 97fe: 0065fb63 bgeu a1,t1,9814 <__udivdi3+0x2e8> + 9802: 95b6 add a1,a1,a3 + 9804: fff70813 addi a6,a4,-1 + 9808: 08d5ed63 bltu a1,a3,98a2 <__udivdi3+0x376> + 980c: 0865fb63 bgeu a1,t1,98a2 <__udivdi3+0x376> + 9810: 1779 addi a4,a4,-2 + 9812: 95b6 add a1,a1,a3 + 9814: 07c2 slli a5,a5,0x10 + 9816: 6f41 lui t5,0x10 + 9818: 8fd9 or a5,a5,a4 + 981a: ffff0713 addi a4,t5,-1 # ffff <_data_lma+0x1da3> + 981e: 00e7f6b3 and a3,a5,a4 + 9822: 0107d893 srli a7,a5,0x10 + 9826: 8f71 and a4,a4,a2 + 9828: 8241 srli a2,a2,0x10 + 982a: 02e68eb3 mul t4,a3,a4 + 982e: 406585b3 sub a1,a1,t1 + 9832: 02c686b3 mul a3,a3,a2 + 9836: 010ed813 srli a6,t4,0x10 + 983a: 02e88733 mul a4,a7,a4 + 983e: 96ba add a3,a3,a4 + 9840: 96c2 add a3,a3,a6 + 9842: 02c88633 mul a2,a7,a2 + 9846: 00e6f363 bgeu a3,a4,984c <__udivdi3+0x320> + 984a: 967a add a2,a2,t5 + 984c: 0106d893 srli a7,a3,0x10 + 9850: 9646 add a2,a2,a7 + 9852: 02c5e263 bltu a1,a2,9876 <__udivdi3+0x34a> + 9856: 00c58563 beq a1,a2,9860 <__udivdi3+0x334> + 985a: 853e mv a0,a5 + 985c: 4581 li a1,0 + 985e: 8082 ret + 9860: 6741 lui a4,0x10 + 9862: 177d addi a4,a4,-1 + 9864: 8ef9 and a3,a3,a4 + 9866: 06c2 slli a3,a3,0x10 + 9868: 00eefeb3 and t4,t4,a4 + 986c: 01c51533 sll a0,a0,t3 + 9870: 96f6 add a3,a3,t4 + 9872: fed574e3 bgeu a0,a3,985a <__udivdi3+0x32e> + 9876: fff78513 addi a0,a5,-1 + 987a: 4581 li a1,0 + 987c: 8082 ret + 987e: 0106d713 srli a4,a3,0x10 + 9882: 4841 li a6,16 + 9884: bd39 j 96a2 <__udivdi3+0x176> + 9886: 01065693 srli a3,a2,0x10 + 988a: 47c1 li a5,16 + 988c: b1d1 j 9550 <__udivdi3+0x24> + 988e: 0108d693 srli a3,a7,0x10 + 9892: 47c1 li a5,16 + 9894: bb85 j 9604 <__udivdi3+0xd8> + 9896: 4581 li a1,0 + 9898: 4505 li a0,1 + 989a: 8082 ret + 989c: 8736 mv a4,a3 + 989e: 4801 li a6,0 + 98a0: b509 j 96a2 <__udivdi3+0x176> + 98a2: 8742 mv a4,a6 + 98a4: bf85 j 9814 <__udivdi3+0x2e8> + 98a6: 863e mv a2,a5 + 98a8: bde9 j 9782 <__udivdi3+0x256> + 98aa: 87ba mv a5,a4 + 98ac: bf1d j 97e2 <__udivdi3+0x2b6> + 98ae: 8e32 mv t3,a2 + 98b0: b54d j 9752 <__udivdi3+0x226> + 98b2: 1579 addi a0,a0,-2 + 98b4: 9846 add a6,a6,a7 + 98b6: b9e5 j 95ae <__udivdi3+0x82> + 98b8: 1579 addi a0,a0,-2 + 98ba: 97c6 add a5,a5,a7 + 98bc: bb61 j 9654 <__udivdi3+0x128> + +000098be : + 98be: 1141 addi sp,sp,-16 + 98c0: 4519 li a0,6 + 98c2: c606 sw ra,12(sp) + 98c4: 239d jal 9e2a + 98c6: 4505 li a0,1 + 98c8: 391010ef jal ra,b458 <_exit> + +000098cc : + 98cc: 4629 li a2,10 + 98ce: 4581 li a1,0 + 98d0: 7e60006f j a0b6 + +000098d4 <__locale_ctype_ptr_l>: + 98d4: 0ec52503 lw a0,236(a0) + 98d8: 8082 ret + +000098da <__locale_ctype_ptr>: + 98da: 80c18793 addi a5,gp,-2036 # 200001fc <_impure_ptr> + 98de: 439c lw a5,0(a5) + 98e0: 539c lw a5,32(a5) + 98e2: e789 bnez a5,98ec <__locale_ctype_ptr+0x12> + 98e4: 1fff6797 auipc a5,0x1fff6 + 98e8: 73c78793 addi a5,a5,1852 # 20000020 <__global_locale> + 98ec: 0ec7a503 lw a0,236(a5) + 98f0: 8082 ret + +000098f2 : + 98f2: 80c18793 addi a5,gp,-2036 # 200001fc <_impure_ptr> + 98f6: 85aa mv a1,a0 + 98f8: 4388 lw a0,0(a5) + 98fa: aae5 j 9af2 <_malloc_r> + +000098fc <__ascii_mbtowc>: + 98fc: ed91 bnez a1,9918 <__ascii_mbtowc+0x1c> + 98fe: 1141 addi sp,sp,-16 + 9900: 006c addi a1,sp,12 + 9902: 4501 li a0,0 + 9904: ca01 beqz a2,9914 <__ascii_mbtowc+0x18> + 9906: 5579 li a0,-2 + 9908: c691 beqz a3,9914 <__ascii_mbtowc+0x18> + 990a: 221c lbu a5,0(a2) + 990c: c19c sw a5,0(a1) + 990e: 2208 lbu a0,0(a2) + 9910: 00a03533 snez a0,a0 + 9914: 0141 addi sp,sp,16 + 9916: 8082 ret + 9918: 4501 li a0,0 + 991a: ca09 beqz a2,992c <__ascii_mbtowc+0x30> + 991c: 5579 li a0,-2 + 991e: c699 beqz a3,992c <__ascii_mbtowc+0x30> + 9920: 221c lbu a5,0(a2) + 9922: c19c sw a5,0(a1) + 9924: 2208 lbu a0,0(a2) + 9926: 00a03533 snez a0,a0 + 992a: 8082 ret + 992c: 8082 ret + +0000992e : + 992e: 4701 li a4,0 + 9930: 00e61463 bne a2,a4,9938 + 9934: 4501 li a0,0 + 9936: 8082 ret + 9938: 00e507b3 add a5,a0,a4 + 993c: 0705 addi a4,a4,1 + 993e: 00e586b3 add a3,a1,a4 + 9942: 239c lbu a5,0(a5) + 9944: fff6c683 lbu a3,-1(a3) + 9948: fed784e3 beq a5,a3,9930 + 994c: 40d78533 sub a0,a5,a3 + 9950: 8082 ret + +00009952 : + 9952: 00a5c7b3 xor a5,a1,a0 + 9956: 8b8d andi a5,a5,3 + 9958: 00c50733 add a4,a0,a2 + 995c: e781 bnez a5,9964 + 995e: 478d li a5,3 + 9960: 00c7ed63 bltu a5,a2,997a + 9964: 87aa mv a5,a0 + 9966: 08e57e63 bgeu a0,a4,9a02 + 996a: 2194 lbu a3,0(a1) + 996c: 0785 addi a5,a5,1 + 996e: 0585 addi a1,a1,1 + 9970: fed78fa3 sb a3,-1(a5) + 9974: fee7ebe3 bltu a5,a4,996a + 9978: 8082 ret + 997a: 00357693 andi a3,a0,3 + 997e: 87aa mv a5,a0 + 9980: ca89 beqz a3,9992 + 9982: 2194 lbu a3,0(a1) + 9984: 0785 addi a5,a5,1 + 9986: 0585 addi a1,a1,1 + 9988: fed78fa3 sb a3,-1(a5) + 998c: 0037f693 andi a3,a5,3 + 9990: bfc5 j 9980 + 9992: ffc77693 andi a3,a4,-4 + 9996: fe068613 addi a2,a3,-32 + 999a: 06c7f063 bgeu a5,a2,99fa + 999e: 0005a383 lw t2,0(a1) + 99a2: 0045a283 lw t0,4(a1) + 99a6: 0085af83 lw t6,8(a1) + 99aa: 00c5af03 lw t5,12(a1) + 99ae: 0105ae83 lw t4,16(a1) + 99b2: 0145ae03 lw t3,20(a1) + 99b6: 0185a303 lw t1,24(a1) + 99ba: 01c5a883 lw a7,28(a1) + 99be: 02458593 addi a1,a1,36 + 99c2: 0077a023 sw t2,0(a5) + 99c6: ffc5a803 lw a6,-4(a1) + 99ca: 0057a223 sw t0,4(a5) + 99ce: 01f7a423 sw t6,8(a5) + 99d2: 01e7a623 sw t5,12(a5) + 99d6: 01d7a823 sw t4,16(a5) + 99da: 01c7aa23 sw t3,20(a5) + 99de: 0067ac23 sw t1,24(a5) + 99e2: 0117ae23 sw a7,28(a5) + 99e6: 02478793 addi a5,a5,36 + 99ea: ff07ae23 sw a6,-4(a5) + 99ee: b775 j 999a + 99f0: 4190 lw a2,0(a1) + 99f2: 0791 addi a5,a5,4 + 99f4: 0591 addi a1,a1,4 + 99f6: fec7ae23 sw a2,-4(a5) + 99fa: fed7ebe3 bltu a5,a3,99f0 + 99fe: f6e7e6e3 bltu a5,a4,996a + 9a02: 8082 ret + +00009a04 : + 9a04: 04a5f163 bgeu a1,a0,9a46 + 9a08: 00c586b3 add a3,a1,a2 + 9a0c: 02d57d63 bgeu a0,a3,9a46 + 9a10: fff64593 not a1,a2 + 9a14: 4781 li a5,0 + 9a16: 17fd addi a5,a5,-1 + 9a18: 00f59363 bne a1,a5,9a1e + 9a1c: 8082 ret + 9a1e: 00f68733 add a4,a3,a5 + 9a22: 00074803 lbu a6,0(a4) # 10000 <_data_lma+0x1da4> + 9a26: 00c78733 add a4,a5,a2 + 9a2a: 972a add a4,a4,a0 + 9a2c: 01070023 sb a6,0(a4) + 9a30: b7dd j 9a16 + 9a32: 00f58733 add a4,a1,a5 + 9a36: 2314 lbu a3,0(a4) + 9a38: 00f50733 add a4,a0,a5 + 9a3c: 0785 addi a5,a5,1 + 9a3e: a314 sb a3,0(a4) + 9a40: fef619e3 bne a2,a5,9a32 + 9a44: 8082 ret + 9a46: 4781 li a5,0 + 9a48: bfe5 j 9a40 + +00009a4a <_free_r>: + 9a4a: c1dd beqz a1,9af0 <_free_r+0xa6> + 9a4c: ffc5a783 lw a5,-4(a1) + 9a50: 1141 addi sp,sp,-16 + 9a52: c422 sw s0,8(sp) + 9a54: c606 sw ra,12(sp) + 9a56: c226 sw s1,4(sp) + 9a58: ffc58413 addi s0,a1,-4 + 9a5c: 0007d363 bgez a5,9a62 <_free_r+0x18> + 9a60: 943e add s0,s0,a5 + 9a62: 84aa mv s1,a0 + 9a64: 4fb000ef jal ra,a75e <__malloc_lock> + 9a68: 83c18793 addi a5,gp,-1988 # 2000022c <__malloc_free_list> + 9a6c: 439c lw a5,0(a5) + 9a6e: ef81 bnez a5,9a86 <_free_r+0x3c> + 9a70: 00042223 sw zero,4(s0) + 9a74: 8281ae23 sw s0,-1988(gp) # 2000022c <__malloc_free_list> + 9a78: 4422 lw s0,8(sp) + 9a7a: 40b2 lw ra,12(sp) + 9a7c: 8526 mv a0,s1 + 9a7e: 4492 lw s1,4(sp) + 9a80: 0141 addi sp,sp,16 + 9a82: 4df0006f j a760 <__malloc_unlock> + 9a86: 00f47e63 bgeu s0,a5,9aa2 <_free_r+0x58> + 9a8a: 4014 lw a3,0(s0) + 9a8c: 00d40733 add a4,s0,a3 + 9a90: 00e79663 bne a5,a4,9a9c <_free_r+0x52> + 9a94: 4398 lw a4,0(a5) + 9a96: 43dc lw a5,4(a5) + 9a98: 9736 add a4,a4,a3 + 9a9a: c018 sw a4,0(s0) + 9a9c: c05c sw a5,4(s0) + 9a9e: bfd9 j 9a74 <_free_r+0x2a> + 9aa0: 87ba mv a5,a4 + 9aa2: 43d8 lw a4,4(a5) + 9aa4: c319 beqz a4,9aaa <_free_r+0x60> + 9aa6: fee47de3 bgeu s0,a4,9aa0 <_free_r+0x56> + 9aaa: 4394 lw a3,0(a5) + 9aac: 00d78633 add a2,a5,a3 + 9ab0: 00861f63 bne a2,s0,9ace <_free_r+0x84> + 9ab4: 4010 lw a2,0(s0) + 9ab6: 96b2 add a3,a3,a2 + 9ab8: c394 sw a3,0(a5) + 9aba: 00d78633 add a2,a5,a3 + 9abe: fac71de3 bne a4,a2,9a78 <_free_r+0x2e> + 9ac2: 4310 lw a2,0(a4) + 9ac4: 4358 lw a4,4(a4) + 9ac6: 96b2 add a3,a3,a2 + 9ac8: c394 sw a3,0(a5) + 9aca: c3d8 sw a4,4(a5) + 9acc: b775 j 9a78 <_free_r+0x2e> + 9ace: 00c47563 bgeu s0,a2,9ad8 <_free_r+0x8e> + 9ad2: 47b1 li a5,12 + 9ad4: c09c sw a5,0(s1) + 9ad6: b74d j 9a78 <_free_r+0x2e> + 9ad8: 4010 lw a2,0(s0) + 9ada: 00c406b3 add a3,s0,a2 + 9ade: 00d71663 bne a4,a3,9aea <_free_r+0xa0> + 9ae2: 4314 lw a3,0(a4) + 9ae4: 4358 lw a4,4(a4) + 9ae6: 96b2 add a3,a3,a2 + 9ae8: c014 sw a3,0(s0) + 9aea: c058 sw a4,4(s0) + 9aec: c3c0 sw s0,4(a5) + 9aee: b769 j 9a78 <_free_r+0x2e> + 9af0: 8082 ret + +00009af2 <_malloc_r>: + 9af2: 1101 addi sp,sp,-32 + 9af4: ca26 sw s1,20(sp) + 9af6: 00358493 addi s1,a1,3 + 9afa: 98f1 andi s1,s1,-4 + 9afc: ce06 sw ra,28(sp) + 9afe: cc22 sw s0,24(sp) + 9b00: c84a sw s2,16(sp) + 9b02: c64e sw s3,12(sp) + 9b04: 04a1 addi s1,s1,8 + 9b06: 47b1 li a5,12 + 9b08: 04f4f363 bgeu s1,a5,9b4e <_malloc_r+0x5c> + 9b0c: 44b1 li s1,12 + 9b0e: 04b4e263 bltu s1,a1,9b52 <_malloc_r+0x60> + 9b12: 892a mv s2,a0 + 9b14: 44b000ef jal ra,a75e <__malloc_lock> + 9b18: 83c18793 addi a5,gp,-1988 # 2000022c <__malloc_free_list> + 9b1c: 4398 lw a4,0(a5) + 9b1e: 843a mv s0,a4 + 9b20: e039 bnez s0,9b66 <_malloc_r+0x74> + 9b22: 84018793 addi a5,gp,-1984 # 20000230 <__malloc_sbrk_start> + 9b26: 439c lw a5,0(a5) + 9b28: e791 bnez a5,9b34 <_malloc_r+0x42> + 9b2a: 4581 li a1,0 + 9b2c: 854a mv a0,s2 + 9b2e: 2c85 jal 9d9e <_sbrk_r> + 9b30: 84a1a023 sw a0,-1984(gp) # 20000230 <__malloc_sbrk_start> + 9b34: 85a6 mv a1,s1 + 9b36: 854a mv a0,s2 + 9b38: 249d jal 9d9e <_sbrk_r> + 9b3a: 59fd li s3,-1 + 9b3c: 07351963 bne a0,s3,9bae <_malloc_r+0xbc> + 9b40: 47b1 li a5,12 + 9b42: 00f92023 sw a5,0(s2) + 9b46: 854a mv a0,s2 + 9b48: 419000ef jal ra,a760 <__malloc_unlock> + 9b4c: a029 j 9b56 <_malloc_r+0x64> + 9b4e: fc04d0e3 bgez s1,9b0e <_malloc_r+0x1c> + 9b52: 47b1 li a5,12 + 9b54: c11c sw a5,0(a0) + 9b56: 4501 li a0,0 + 9b58: 40f2 lw ra,28(sp) + 9b5a: 4462 lw s0,24(sp) + 9b5c: 44d2 lw s1,20(sp) + 9b5e: 4942 lw s2,16(sp) + 9b60: 49b2 lw s3,12(sp) + 9b62: 6105 addi sp,sp,32 + 9b64: 8082 ret + 9b66: 401c lw a5,0(s0) + 9b68: 8f85 sub a5,a5,s1 + 9b6a: 0207cf63 bltz a5,9ba8 <_malloc_r+0xb6> + 9b6e: 46ad li a3,11 + 9b70: 00f6f663 bgeu a3,a5,9b7c <_malloc_r+0x8a> + 9b74: c01c sw a5,0(s0) + 9b76: 943e add s0,s0,a5 + 9b78: c004 sw s1,0(s0) + 9b7a: a031 j 9b86 <_malloc_r+0x94> + 9b7c: 405c lw a5,4(s0) + 9b7e: 02871363 bne a4,s0,9ba4 <_malloc_r+0xb2> + 9b82: 82f1ae23 sw a5,-1988(gp) # 2000022c <__malloc_free_list> + 9b86: 854a mv a0,s2 + 9b88: 3d9000ef jal ra,a760 <__malloc_unlock> + 9b8c: 00b40513 addi a0,s0,11 + 9b90: 00440793 addi a5,s0,4 + 9b94: 9961 andi a0,a0,-8 + 9b96: 40f50733 sub a4,a0,a5 + 9b9a: df5d beqz a4,9b58 <_malloc_r+0x66> + 9b9c: 943a add s0,s0,a4 + 9b9e: 8f89 sub a5,a5,a0 + 9ba0: c01c sw a5,0(s0) + 9ba2: bf5d j 9b58 <_malloc_r+0x66> + 9ba4: c35c sw a5,4(a4) + 9ba6: b7c5 j 9b86 <_malloc_r+0x94> + 9ba8: 8722 mv a4,s0 + 9baa: 4040 lw s0,4(s0) + 9bac: bf95 j 9b20 <_malloc_r+0x2e> + 9bae: 00350413 addi s0,a0,3 + 9bb2: 9871 andi s0,s0,-4 + 9bb4: fc8502e3 beq a0,s0,9b78 <_malloc_r+0x86> + 9bb8: 40a405b3 sub a1,s0,a0 + 9bbc: 854a mv a0,s2 + 9bbe: 22c5 jal 9d9e <_sbrk_r> + 9bc0: fb351ce3 bne a0,s3,9b78 <_malloc_r+0x86> + 9bc4: bfb5 j 9b40 <_malloc_r+0x4e> + +00009bc6 : + 9bc6: 7139 addi sp,sp,-64 + 9bc8: da3e sw a5,52(sp) + 9bca: d22e sw a1,36(sp) + 9bcc: d432 sw a2,40(sp) + 9bce: d636 sw a3,44(sp) + 9bd0: d83a sw a4,48(sp) + 9bd2: dc42 sw a6,56(sp) + 9bd4: de46 sw a7,60(sp) + 9bd6: 80c18793 addi a5,gp,-2036 # 200001fc <_impure_ptr> + 9bda: cc22 sw s0,24(sp) + 9bdc: 4380 lw s0,0(a5) + 9bde: ca26 sw s1,20(sp) + 9be0: ce06 sw ra,28(sp) + 9be2: 84aa mv s1,a0 + 9be4: c411 beqz s0,9bf0 + 9be6: 4c1c lw a5,24(s0) + 9be8: e781 bnez a5,9bf0 + 9bea: 8522 mv a0,s0 + 9bec: 111000ef jal ra,a4fc <__sinit> + 9bf0: 440c lw a1,8(s0) + 9bf2: 1054 addi a3,sp,36 + 9bf4: 8626 mv a2,s1 + 9bf6: 8522 mv a0,s0 + 9bf8: c636 sw a3,12(sp) + 9bfa: 721000ef jal ra,ab1a <_vfiprintf_r> + 9bfe: 40f2 lw ra,28(sp) + 9c00: 4462 lw s0,24(sp) + 9c02: 44d2 lw s1,20(sp) + 9c04: 6121 addi sp,sp,64 + 9c06: 8082 ret + +00009c08 : + 9c08: 1101 addi sp,sp,-32 + 9c0a: 80c18793 addi a5,gp,-2036 # 200001fc <_impure_ptr> + 9c0e: cc22 sw s0,24(sp) + 9c10: 4380 lw s0,0(a5) + 9c12: ce06 sw ra,28(sp) + 9c14: 85aa mv a1,a0 + 9c16: c801 beqz s0,9c26 + 9c18: 4c1c lw a5,24(s0) + 9c1a: e791 bnez a5,9c26 + 9c1c: c62a sw a0,12(sp) + 9c1e: 8522 mv a0,s0 + 9c20: 0dd000ef jal ra,a4fc <__sinit> + 9c24: 45b2 lw a1,12(sp) + 9c26: 4410 lw a2,8(s0) + 9c28: 8522 mv a0,s0 + 9c2a: 4462 lw s0,24(sp) + 9c2c: 40f2 lw ra,28(sp) + 9c2e: 6105 addi sp,sp,32 + 9c30: 5220106f j b152 <_putc_r> + +00009c34 <_puts_r>: + 9c34: 1101 addi sp,sp,-32 + 9c36: ca26 sw s1,20(sp) + 9c38: c84a sw s2,16(sp) + 9c3a: ce06 sw ra,28(sp) + 9c3c: cc22 sw s0,24(sp) + 9c3e: c64e sw s3,12(sp) + 9c40: c452 sw s4,8(sp) + 9c42: 84aa mv s1,a0 + 9c44: 892e mv s2,a1 + 9c46: c509 beqz a0,9c50 <_puts_r+0x1c> + 9c48: 4d1c lw a5,24(a0) + 9c4a: e399 bnez a5,9c50 <_puts_r+0x1c> + 9c4c: 0b1000ef jal ra,a4fc <__sinit> + 9c50: 4c9c lw a5,24(s1) + 9c52: 4480 lw s0,8(s1) + 9c54: e781 bnez a5,9c5c <_puts_r+0x28> + 9c56: 8526 mv a0,s1 + 9c58: 0a5000ef jal ra,a4fc <__sinit> + 9c5c: 00004797 auipc a5,0x4 + 9c60: 58478793 addi a5,a5,1412 # e1e0 <__sf_fake_stdin> + 9c64: 02f41b63 bne s0,a5,9c9a <_puts_r+0x66> + 9c68: 40c0 lw s0,4(s1) + 9c6a: 245e lhu a5,12(s0) + 9c6c: 8ba1 andi a5,a5,8 + 9c6e: c7b1 beqz a5,9cba <_puts_r+0x86> + 9c70: 481c lw a5,16(s0) + 9c72: c7a1 beqz a5,9cba <_puts_r+0x86> + 9c74: 59fd li s3,-1 + 9c76: 4a29 li s4,10 + 9c78: 441c lw a5,8(s0) + 9c7a: 00094583 lbu a1,0(s2) + 9c7e: 17fd addi a5,a5,-1 + 9c80: e9b1 bnez a1,9cd4 <_puts_r+0xa0> + 9c82: c41c sw a5,8(s0) + 9c84: 0607dd63 bgez a5,9cfe <_puts_r+0xca> + 9c88: 8622 mv a2,s0 + 9c8a: 45a9 li a1,10 + 9c8c: 8526 mv a0,s1 + 9c8e: 2199 jal a0d4 <__swbuf_r> + 9c90: 57fd li a5,-1 + 9c92: 02f50863 beq a0,a5,9cc2 <_puts_r+0x8e> + 9c96: 4529 li a0,10 + 9c98: a035 j 9cc4 <_puts_r+0x90> + 9c9a: 00004797 auipc a5,0x4 + 9c9e: 56678793 addi a5,a5,1382 # e200 <__sf_fake_stdout> + 9ca2: 00f41463 bne s0,a5,9caa <_puts_r+0x76> + 9ca6: 4480 lw s0,8(s1) + 9ca8: b7c9 j 9c6a <_puts_r+0x36> + 9caa: 00004797 auipc a5,0x4 + 9cae: 51678793 addi a5,a5,1302 # e1c0 <__sf_fake_stderr> + 9cb2: faf41ce3 bne s0,a5,9c6a <_puts_r+0x36> + 9cb6: 44c0 lw s0,12(s1) + 9cb8: bf4d j 9c6a <_puts_r+0x36> + 9cba: 85a2 mv a1,s0 + 9cbc: 8526 mv a0,s1 + 9cbe: 29c5 jal a1ae <__swsetup_r> + 9cc0: d955 beqz a0,9c74 <_puts_r+0x40> + 9cc2: 557d li a0,-1 + 9cc4: 40f2 lw ra,28(sp) + 9cc6: 4462 lw s0,24(sp) + 9cc8: 44d2 lw s1,20(sp) + 9cca: 4942 lw s2,16(sp) + 9ccc: 49b2 lw s3,12(sp) + 9cce: 4a22 lw s4,8(sp) + 9cd0: 6105 addi sp,sp,32 + 9cd2: 8082 ret + 9cd4: c41c sw a5,8(s0) + 9cd6: 0905 addi s2,s2,1 + 9cd8: 0007d763 bgez a5,9ce6 <_puts_r+0xb2> + 9cdc: 4c18 lw a4,24(s0) + 9cde: 00e7ca63 blt a5,a4,9cf2 <_puts_r+0xbe> + 9ce2: 01458863 beq a1,s4,9cf2 <_puts_r+0xbe> + 9ce6: 401c lw a5,0(s0) + 9ce8: 00178713 addi a4,a5,1 + 9cec: c018 sw a4,0(s0) + 9cee: a38c sb a1,0(a5) + 9cf0: b761 j 9c78 <_puts_r+0x44> + 9cf2: 8622 mv a2,s0 + 9cf4: 8526 mv a0,s1 + 9cf6: 2ef9 jal a0d4 <__swbuf_r> + 9cf8: f93510e3 bne a0,s3,9c78 <_puts_r+0x44> + 9cfc: b7d9 j 9cc2 <_puts_r+0x8e> + 9cfe: 401c lw a5,0(s0) + 9d00: 00178713 addi a4,a5,1 + 9d04: c018 sw a4,0(s0) + 9d06: 4729 li a4,10 + 9d08: a398 sb a4,0(a5) + 9d0a: b771 j 9c96 <_puts_r+0x62> + +00009d0c : + 9d0c: 80c18793 addi a5,gp,-2036 # 200001fc <_impure_ptr> + 9d10: 85aa mv a1,a0 + 9d12: 4388 lw a0,0(a5) + 9d14: f21ff06f j 9c34 <_puts_r> + +00009d18 : + 9d18: 1141 addi sp,sp,-16 + 9d1a: 80c18793 addi a5,gp,-2036 # 200001fc <_impure_ptr> + 9d1e: c422 sw s0,8(sp) + 9d20: 4380 lw s0,0(a5) + 9d22: c606 sw ra,12(sp) + 9d24: 5c1c lw a5,56(s0) + 9d26: eb95 bnez a5,9d5a + 9d28: 4561 li a0,24 + 9d2a: bc9ff0ef jal ra,98f2 + 9d2e: abcd37b7 lui a5,0xabcd3 + 9d32: dc08 sw a0,56(s0) + 9d34: 30e78793 addi a5,a5,782 # abcd330e <_eusrstack+0x8bccb30e> + 9d38: c11c sw a5,0(a0) + 9d3a: e66d17b7 lui a5,0xe66d1 + 9d3e: 23478793 addi a5,a5,564 # e66d1234 <_eusrstack+0xc66c9234> + 9d42: c15c sw a5,4(a0) + 9d44: 0005e7b7 lui a5,0x5e + 9d48: eec78793 addi a5,a5,-276 # 5deec <_data_lma+0x4fc90> + 9d4c: c51c sw a5,8(a0) + 9d4e: 47ad li a5,11 + 9d50: a55e sh a5,12(a0) + 9d52: 4705 li a4,1 + 9d54: 4781 li a5,0 + 9d56: c918 sw a4,16(a0) + 9d58: c95c sw a5,20(a0) + 9d5a: 5c10 lw a2,56(s0) + 9d5c: 4c958737 lui a4,0x4c958 + 9d60: 5851f7b7 lui a5,0x5851f + 9d64: 4a14 lw a3,16(a2) + 9d66: 4a48 lw a0,20(a2) + 9d68: f2d70713 addi a4,a4,-211 # 4c957f2d <_eusrstack+0x2c94ff2d> + 9d6c: 42d78793 addi a5,a5,1069 # 5851f42d <_eusrstack+0x3851742d> + 9d70: 02f687b3 mul a5,a3,a5 + 9d74: 40b2 lw ra,12(sp) + 9d76: 4422 lw s0,8(sp) + 9d78: 02e50533 mul a0,a0,a4 + 9d7c: 953e add a0,a0,a5 + 9d7e: 02e687b3 mul a5,a3,a4 + 9d82: 02e6b733 mulhu a4,a3,a4 + 9d86: 00178693 addi a3,a5,1 + 9d8a: ca14 sw a3,16(a2) + 9d8c: 972a add a4,a4,a0 + 9d8e: 00f6b533 sltu a0,a3,a5 + 9d92: 953a add a0,a0,a4 + 9d94: ca48 sw a0,20(a2) + 9d96: 0506 slli a0,a0,0x1 + 9d98: 8105 srli a0,a0,0x1 + 9d9a: 0141 addi sp,sp,16 + 9d9c: 8082 ret + +00009d9e <_sbrk_r>: + 9d9e: 1141 addi sp,sp,-16 + 9da0: c422 sw s0,8(sp) + 9da2: 842a mv s0,a0 + 9da4: 852e mv a0,a1 + 9da6: 7801a623 sw zero,1932(gp) # 2000117c + 9daa: c606 sw ra,12(sp) + 9dac: f2eff0ef jal ra,94da <_sbrk> + 9db0: 57fd li a5,-1 + 9db2: 00f51763 bne a0,a5,9dc0 <_sbrk_r+0x22> + 9db6: 78c18793 addi a5,gp,1932 # 2000117c + 9dba: 439c lw a5,0(a5) + 9dbc: c391 beqz a5,9dc0 <_sbrk_r+0x22> + 9dbe: c01c sw a5,0(s0) + 9dc0: 40b2 lw ra,12(sp) + 9dc2: 4422 lw s0,8(sp) + 9dc4: 0141 addi sp,sp,16 + 9dc6: 8082 ret + +00009dc8 <_raise_r>: + 9dc8: 47fd li a5,31 + 9dca: 00b7f663 bgeu a5,a1,9dd6 <_raise_r+0xe> + 9dce: 47d9 li a5,22 + 9dd0: c11c sw a5,0(a0) + 9dd2: 557d li a0,-1 + 9dd4: 8082 ret + 9dd6: 417c lw a5,68(a0) + 9dd8: 1101 addi sp,sp,-32 + 9dda: cc22 sw s0,24(sp) + 9ddc: ce06 sw ra,28(sp) + 9dde: 862e mv a2,a1 + 9de0: 842a mv s0,a0 + 9de2: c791 beqz a5,9dee <_raise_r+0x26> + 9de4: 00259713 slli a4,a1,0x2 + 9de8: 97ba add a5,a5,a4 + 9dea: 4398 lw a4,0(a5) + 9dec: eb19 bnez a4,9e02 <_raise_r+0x3a> + 9dee: 8522 mv a0,s0 + 9df0: c632 sw a2,12(sp) + 9df2: 2885 jal 9e62 <_getpid_r> + 9df4: 85aa mv a1,a0 + 9df6: 8522 mv a0,s0 + 9df8: 4462 lw s0,24(sp) + 9dfa: 4632 lw a2,12(sp) + 9dfc: 40f2 lw ra,28(sp) + 9dfe: 6105 addi sp,sp,32 + 9e00: a81d j 9e36 <_kill_r> + 9e02: 4685 li a3,1 + 9e04: 4501 li a0,0 + 9e06: 00d70863 beq a4,a3,9e16 <_raise_r+0x4e> + 9e0a: 56fd li a3,-1 + 9e0c: 00d71963 bne a4,a3,9e1e <_raise_r+0x56> + 9e10: 47d9 li a5,22 + 9e12: c01c sw a5,0(s0) + 9e14: 4505 li a0,1 + 9e16: 40f2 lw ra,28(sp) + 9e18: 4462 lw s0,24(sp) + 9e1a: 6105 addi sp,sp,32 + 9e1c: 8082 ret + 9e1e: 852e mv a0,a1 + 9e20: 0007a023 sw zero,0(a5) + 9e24: 9702 jalr a4 + 9e26: 4501 li a0,0 + 9e28: b7fd j 9e16 <_raise_r+0x4e> + +00009e2a : + 9e2a: 80c18793 addi a5,gp,-2036 # 200001fc <_impure_ptr> + 9e2e: 85aa mv a1,a0 + 9e30: 4388 lw a0,0(a5) + 9e32: f97ff06f j 9dc8 <_raise_r> + +00009e36 <_kill_r>: + 9e36: 1141 addi sp,sp,-16 + 9e38: c422 sw s0,8(sp) + 9e3a: 842a mv s0,a0 + 9e3c: 852e mv a0,a1 + 9e3e: 85b2 mv a1,a2 + 9e40: 7801a623 sw zero,1932(gp) # 2000117c + 9e44: c606 sw ra,12(sp) + 9e46: 5ee010ef jal ra,b434 <_kill> + 9e4a: 57fd li a5,-1 + 9e4c: 00f51763 bne a0,a5,9e5a <_kill_r+0x24> + 9e50: 78c18793 addi a5,gp,1932 # 2000117c + 9e54: 439c lw a5,0(a5) + 9e56: c391 beqz a5,9e5a <_kill_r+0x24> + 9e58: c01c sw a5,0(s0) + 9e5a: 40b2 lw ra,12(sp) + 9e5c: 4422 lw s0,8(sp) + 9e5e: 0141 addi sp,sp,16 + 9e60: 8082 ret + +00009e62 <_getpid_r>: + 9e62: 5ba0106f j b41c <_getpid> + +00009e66 : + 9e66: 7135 addi sp,sp,-160 + 9e68: cb3e sw a5,148(sp) + 9e6a: daa6 sw s1,116(sp) + 9e6c: c736 sw a3,140(sp) + 9e6e: c93a sw a4,144(sp) + 9e70: cd42 sw a6,152(sp) + 9e72: cf46 sw a7,156(sp) + 9e74: 80c18793 addi a5,gp,-2036 # 200001fc <_impure_ptr> + 9e78: de86 sw ra,124(sp) + 9e7a: dca2 sw s0,120(sp) + 9e7c: 4384 lw s1,0(a5) + 9e7e: 0005db63 bgez a1,9e94 + 9e82: 08b00793 li a5,139 + 9e86: c09c sw a5,0(s1) + 9e88: 557d li a0,-1 + 9e8a: 50f6 lw ra,124(sp) + 9e8c: 5466 lw s0,120(sp) + 9e8e: 54d6 lw s1,116(sp) + 9e90: 610d addi sp,sp,160 + 9e92: 8082 ret + 9e94: 20800793 li a5,520 + 9e98: 82fc sh a5,20(sp) + 9e9a: c42a sw a0,8(sp) + 9e9c: cc2a sw a0,24(sp) + 9e9e: 4781 li a5,0 + 9ea0: c199 beqz a1,9ea6 + 9ea2: fff58793 addi a5,a1,-1 + 9ea6: c83e sw a5,16(sp) + 9ea8: ce3e sw a5,28(sp) + 9eaa: 0174 addi a3,sp,140 + 9eac: 57fd li a5,-1 + 9eae: 842e mv s0,a1 + 9eb0: 8526 mv a0,s1 + 9eb2: 002c addi a1,sp,8 + 9eb4: 83fc sh a5,22(sp) + 9eb6: c236 sw a3,4(sp) + 9eb8: 18f000ef jal ra,a846 <_svfiprintf_r> + 9ebc: 57fd li a5,-1 + 9ebe: 00f55563 bge a0,a5,9ec8 + 9ec2: 08b00793 li a5,139 + 9ec6: c09c sw a5,0(s1) + 9ec8: d069 beqz s0,9e8a + 9eca: 47a2 lw a5,8(sp) + 9ecc: 00078023 sb zero,0(a5) + 9ed0: bf6d j 9e8a + +00009ed2 : + 9ed2: 7135 addi sp,sp,-160 + 9ed4: cb3e sw a5,148(sp) + 9ed6: 800007b7 lui a5,0x80000 + 9eda: fff7c793 not a5,a5 + 9ede: ce3e sw a5,28(sp) + 9ee0: c83e sw a5,16(sp) + 9ee2: 77c1 lui a5,0xffff0 + 9ee4: 20878793 addi a5,a5,520 # ffff0208 <_eusrstack+0xdffe8208> + 9ee8: c532 sw a2,136(sp) + 9eea: c736 sw a3,140(sp) + 9eec: c93a sw a4,144(sp) + 9eee: cd42 sw a6,152(sp) + 9ef0: cf46 sw a7,156(sp) + 9ef2: ca3e sw a5,20(sp) + 9ef4: 80c18793 addi a5,gp,-2036 # 200001fc <_impure_ptr> + 9ef8: c42a sw a0,8(sp) + 9efa: cc2a sw a0,24(sp) + 9efc: 4388 lw a0,0(a5) + 9efe: 0134 addi a3,sp,136 + 9f00: 862e mv a2,a1 + 9f02: 002c addi a1,sp,8 + 9f04: de86 sw ra,124(sp) + 9f06: c236 sw a3,4(sp) + 9f08: 13f000ef jal ra,a846 <_svfiprintf_r> + 9f0c: 47a2 lw a5,8(sp) + 9f0e: 00078023 sb zero,0(a5) + 9f12: 50f6 lw ra,124(sp) + 9f14: 610d addi sp,sp,160 + 9f16: 8082 ret + +00009f18 : + 9f18: 87aa mv a5,a0 + 9f1a: 2398 lbu a4,0(a5) + 9f1c: 00178693 addi a3,a5,1 + 9f20: eb09 bnez a4,9f32 + 9f22: 0585 addi a1,a1,1 + 9f24: fff5c703 lbu a4,-1(a1) + 9f28: 0785 addi a5,a5,1 + 9f2a: fee78fa3 sb a4,-1(a5) + 9f2e: fb75 bnez a4,9f22 + 9f30: 8082 ret + 9f32: 87b6 mv a5,a3 + 9f34: b7dd j 9f1a + +00009f36 : + 9f36: 87aa mv a5,a0 + 9f38: 2198 lbu a4,0(a1) + 9f3a: 0785 addi a5,a5,1 + 9f3c: 0585 addi a1,a1,1 + 9f3e: fee78fa3 sb a4,-1(a5) + 9f42: fb7d bnez a4,9f38 + 9f44: 8082 ret + +00009f46 : + 9f46: 87aa mv a5,a0 + 9f48: 0785 addi a5,a5,1 + 9f4a: fff7c703 lbu a4,-1(a5) + 9f4e: ff6d bnez a4,9f48 + 9f50: 40a78533 sub a0,a5,a0 + 9f54: 157d addi a0,a0,-1 + 9f56: 8082 ret + +00009f58 : + 9f58: 87aa mv a5,a0 + 9f5a: ca09 beqz a2,9f6c + 9f5c: 0585 addi a1,a1,1 + 9f5e: fff5c703 lbu a4,-1(a1) + 9f62: 0785 addi a5,a5,1 + 9f64: 167d addi a2,a2,-1 + 9f66: fee78fa3 sb a4,-1(a5) + 9f6a: fb65 bnez a4,9f5a + 9f6c: 963e add a2,a2,a5 + 9f6e: 00c79363 bne a5,a2,9f74 + 9f72: 8082 ret + 9f74: 0785 addi a5,a5,1 + 9f76: fe078fa3 sb zero,-1(a5) + 9f7a: bfd5 j 9f6e + +00009f7c <_strtol_l.isra.0>: + 9f7c: 7179 addi sp,sp,-48 + 9f7e: d04a sw s2,32(sp) + 9f80: ce4e sw s3,28(sp) + 9f82: d606 sw ra,44(sp) + 9f84: d422 sw s0,40(sp) + 9f86: d226 sw s1,36(sp) + 9f88: 89aa mv s3,a0 + 9f8a: 892e mv s2,a1 + 9f8c: 00190493 addi s1,s2,1 + 9f90: fff4c403 lbu s0,-1(s1) + 9f94: 853a mv a0,a4 + 9f96: c636 sw a3,12(sp) + 9f98: c432 sw a2,8(sp) + 9f9a: c22e sw a1,4(sp) + 9f9c: c03a sw a4,0(sp) + 9f9e: 937ff0ef jal ra,98d4 <__locale_ctype_ptr_l> + 9fa2: 9522 add a0,a0,s0 + 9fa4: 311c lbu a5,1(a0) + 9fa6: 4702 lw a4,0(sp) + 9fa8: 4592 lw a1,4(sp) + 9faa: 8ba1 andi a5,a5,8 + 9fac: 4622 lw a2,8(sp) + 9fae: 46b2 lw a3,12(sp) + 9fb0: e3d1 bnez a5,a034 <_strtol_l.isra.0+0xb8> + 9fb2: 02d00793 li a5,45 + 9fb6: 08f41163 bne s0,a5,a038 <_strtol_l.isra.0+0xbc> + 9fba: 209c lbu a5,0(s1) + 9fbc: 4305 li t1,1 + 9fbe: 00290493 addi s1,s2,2 + 9fc2: c6e5 beqz a3,a0aa <_strtol_l.isra.0+0x12e> + 9fc4: 4741 li a4,16 + 9fc6: 02e69063 bne a3,a4,9fe6 <_strtol_l.isra.0+0x6a> + 9fca: 03000713 li a4,48 + 9fce: 00e79c63 bne a5,a4,9fe6 <_strtol_l.isra.0+0x6a> + 9fd2: 209c lbu a5,0(s1) + 9fd4: 05800713 li a4,88 + 9fd8: 0df7f793 andi a5,a5,223 + 9fdc: 0ce79263 bne a5,a4,a0a0 <_strtol_l.isra.0+0x124> + 9fe0: 309c lbu a5,1(s1) + 9fe2: 46c1 li a3,16 + 9fe4: 0489 addi s1,s1,2 + 9fe6: 800008b7 lui a7,0x80000 + 9fea: 00031463 bnez t1,9ff2 <_strtol_l.isra.0+0x76> + 9fee: fff8c893 not a7,a7 + 9ff2: 02d8ff33 remu t5,a7,a3 + 9ff6: 4801 li a6,0 + 9ff8: 4501 li a0,0 + 9ffa: 4fa5 li t6,9 + 9ffc: 4ee5 li t4,25 + 9ffe: 52fd li t0,-1 + a000: 02d8de33 divu t3,a7,a3 + a004: fd078713 addi a4,a5,-48 + a008: 04efe363 bltu t6,a4,a04e <_strtol_l.isra.0+0xd2> + a00c: 87ba mv a5,a4 + a00e: 04d7de63 bge a5,a3,a06a <_strtol_l.isra.0+0xee> + a012: 00580d63 beq a6,t0,a02c <_strtol_l.isra.0+0xb0> + a016: 587d li a6,-1 + a018: 00ae6a63 bltu t3,a0,a02c <_strtol_l.isra.0+0xb0> + a01c: 00ae1463 bne t3,a0,a024 <_strtol_l.isra.0+0xa8> + a020: 00ff4663 blt t5,a5,a02c <_strtol_l.isra.0+0xb0> + a024: 4805 li a6,1 + a026: 02a68533 mul a0,a3,a0 + a02a: 953e add a0,a0,a5 + a02c: 0485 addi s1,s1,1 + a02e: fff4c783 lbu a5,-1(s1) + a032: bfc9 j a004 <_strtol_l.isra.0+0x88> + a034: 8926 mv s2,s1 + a036: bf99 j 9f8c <_strtol_l.isra.0+0x10> + a038: 02b00793 li a5,43 + a03c: 00f40563 beq s0,a5,a046 <_strtol_l.isra.0+0xca> + a040: 87a2 mv a5,s0 + a042: 4301 li t1,0 + a044: bfbd j 9fc2 <_strtol_l.isra.0+0x46> + a046: 209c lbu a5,0(s1) + a048: 00290493 addi s1,s2,2 + a04c: bfdd j a042 <_strtol_l.isra.0+0xc6> + a04e: fbf78713 addi a4,a5,-65 + a052: 00eee563 bltu t4,a4,a05c <_strtol_l.isra.0+0xe0> + a056: fc978793 addi a5,a5,-55 + a05a: bf55 j a00e <_strtol_l.isra.0+0x92> + a05c: f9f78713 addi a4,a5,-97 + a060: 00eee563 bltu t4,a4,a06a <_strtol_l.isra.0+0xee> + a064: fa978793 addi a5,a5,-87 + a068: b75d j a00e <_strtol_l.isra.0+0x92> + a06a: 57fd li a5,-1 + a06c: 00f81f63 bne a6,a5,a08a <_strtol_l.isra.0+0x10e> + a070: 02200793 li a5,34 + a074: 00f9a023 sw a5,0(s3) + a078: 8546 mv a0,a7 + a07a: ee19 bnez a2,a098 <_strtol_l.isra.0+0x11c> + a07c: 50b2 lw ra,44(sp) + a07e: 5422 lw s0,40(sp) + a080: 5492 lw s1,36(sp) + a082: 5902 lw s2,32(sp) + a084: 49f2 lw s3,28(sp) + a086: 6145 addi sp,sp,48 + a088: 8082 ret + a08a: 00030463 beqz t1,a092 <_strtol_l.isra.0+0x116> + a08e: 40a00533 neg a0,a0 + a092: d66d beqz a2,a07c <_strtol_l.isra.0+0x100> + a094: 00080463 beqz a6,a09c <_strtol_l.isra.0+0x120> + a098: fff48593 addi a1,s1,-1 + a09c: c20c sw a1,0(a2) + a09e: bff9 j a07c <_strtol_l.isra.0+0x100> + a0a0: 03000793 li a5,48 + a0a4: f2a9 bnez a3,9fe6 <_strtol_l.isra.0+0x6a> + a0a6: 46a1 li a3,8 + a0a8: bf3d j 9fe6 <_strtol_l.isra.0+0x6a> + a0aa: 03000713 li a4,48 + a0ae: f2e782e3 beq a5,a4,9fd2 <_strtol_l.isra.0+0x56> + a0b2: 46a9 li a3,10 + a0b4: bf0d j 9fe6 <_strtol_l.isra.0+0x6a> + +0000a0b6 : + a0b6: 80c18793 addi a5,gp,-2036 # 200001fc <_impure_ptr> + a0ba: 439c lw a5,0(a5) + a0bc: 86b2 mv a3,a2 + a0be: 5398 lw a4,32(a5) + a0c0: e709 bnez a4,a0ca + a0c2: 1fff6717 auipc a4,0x1fff6 + a0c6: f5e70713 addi a4,a4,-162 # 20000020 <__global_locale> + a0ca: 862e mv a2,a1 + a0cc: 85aa mv a1,a0 + a0ce: 853e mv a0,a5 + a0d0: eadff06f j 9f7c <_strtol_l.isra.0> + +0000a0d4 <__swbuf_r>: + a0d4: 1101 addi sp,sp,-32 + a0d6: cc22 sw s0,24(sp) + a0d8: ca26 sw s1,20(sp) + a0da: c84a sw s2,16(sp) + a0dc: ce06 sw ra,28(sp) + a0de: c64e sw s3,12(sp) + a0e0: 84aa mv s1,a0 + a0e2: 892e mv s2,a1 + a0e4: 8432 mv s0,a2 + a0e6: c501 beqz a0,a0ee <__swbuf_r+0x1a> + a0e8: 4d1c lw a5,24(a0) + a0ea: e391 bnez a5,a0ee <__swbuf_r+0x1a> + a0ec: 2901 jal a4fc <__sinit> + a0ee: 00004797 auipc a5,0x4 + a0f2: 0f278793 addi a5,a5,242 # e1e0 <__sf_fake_stdin> + a0f6: 06f41763 bne s0,a5,a164 <__swbuf_r+0x90> + a0fa: 40c0 lw s0,4(s1) + a0fc: 4c1c lw a5,24(s0) + a0fe: c41c sw a5,8(s0) + a100: 245e lhu a5,12(s0) + a102: 8ba1 andi a5,a5,8 + a104: c3c1 beqz a5,a184 <__swbuf_r+0xb0> + a106: 481c lw a5,16(s0) + a108: cfb5 beqz a5,a184 <__swbuf_r+0xb0> + a10a: 481c lw a5,16(s0) + a10c: 4008 lw a0,0(s0) + a10e: 0ff97993 andi s3,s2,255 + a112: 0ff97913 andi s2,s2,255 + a116: 8d1d sub a0,a0,a5 + a118: 485c lw a5,20(s0) + a11a: 00f54663 blt a0,a5,a126 <__swbuf_r+0x52> + a11e: 85a2 mv a1,s0 + a120: 8526 mv a0,s1 + a122: 2c75 jal a3de <_fflush_r> + a124: e525 bnez a0,a18c <__swbuf_r+0xb8> + a126: 441c lw a5,8(s0) + a128: 0505 addi a0,a0,1 + a12a: 17fd addi a5,a5,-1 + a12c: c41c sw a5,8(s0) + a12e: 401c lw a5,0(s0) + a130: 00178713 addi a4,a5,1 + a134: c018 sw a4,0(s0) + a136: 01378023 sb s3,0(a5) + a13a: 485c lw a5,20(s0) + a13c: 00a78863 beq a5,a0,a14c <__swbuf_r+0x78> + a140: 245e lhu a5,12(s0) + a142: 8b85 andi a5,a5,1 + a144: cb81 beqz a5,a154 <__swbuf_r+0x80> + a146: 47a9 li a5,10 + a148: 00f91663 bne s2,a5,a154 <__swbuf_r+0x80> + a14c: 85a2 mv a1,s0 + a14e: 8526 mv a0,s1 + a150: 2479 jal a3de <_fflush_r> + a152: ed0d bnez a0,a18c <__swbuf_r+0xb8> + a154: 40f2 lw ra,28(sp) + a156: 4462 lw s0,24(sp) + a158: 854a mv a0,s2 + a15a: 44d2 lw s1,20(sp) + a15c: 4942 lw s2,16(sp) + a15e: 49b2 lw s3,12(sp) + a160: 6105 addi sp,sp,32 + a162: 8082 ret + a164: 00004797 auipc a5,0x4 + a168: 09c78793 addi a5,a5,156 # e200 <__sf_fake_stdout> + a16c: 00f41463 bne s0,a5,a174 <__swbuf_r+0xa0> + a170: 4480 lw s0,8(s1) + a172: b769 j a0fc <__swbuf_r+0x28> + a174: 00004797 auipc a5,0x4 + a178: 04c78793 addi a5,a5,76 # e1c0 <__sf_fake_stderr> + a17c: f8f410e3 bne s0,a5,a0fc <__swbuf_r+0x28> + a180: 44c0 lw s0,12(s1) + a182: bfad j a0fc <__swbuf_r+0x28> + a184: 85a2 mv a1,s0 + a186: 8526 mv a0,s1 + a188: 201d jal a1ae <__swsetup_r> + a18a: d141 beqz a0,a10a <__swbuf_r+0x36> + a18c: 597d li s2,-1 + a18e: b7d9 j a154 <__swbuf_r+0x80> + +0000a190 <__ascii_wctomb>: + a190: cd89 beqz a1,a1aa <__ascii_wctomb+0x1a> + a192: 0ff00793 li a5,255 + a196: 00c7f763 bgeu a5,a2,a1a4 <__ascii_wctomb+0x14> + a19a: 08a00793 li a5,138 + a19e: c11c sw a5,0(a0) + a1a0: 557d li a0,-1 + a1a2: 8082 ret + a1a4: a190 sb a2,0(a1) + a1a6: 4505 li a0,1 + a1a8: 8082 ret + a1aa: 4501 li a0,0 + a1ac: 8082 ret + +0000a1ae <__swsetup_r>: + a1ae: 1141 addi sp,sp,-16 + a1b0: 80c18793 addi a5,gp,-2036 # 200001fc <_impure_ptr> + a1b4: c226 sw s1,4(sp) + a1b6: 4384 lw s1,0(a5) + a1b8: c422 sw s0,8(sp) + a1ba: c04a sw s2,0(sp) + a1bc: c606 sw ra,12(sp) + a1be: 892a mv s2,a0 + a1c0: 842e mv s0,a1 + a1c2: c489 beqz s1,a1cc <__swsetup_r+0x1e> + a1c4: 4c9c lw a5,24(s1) + a1c6: e399 bnez a5,a1cc <__swsetup_r+0x1e> + a1c8: 8526 mv a0,s1 + a1ca: 2e0d jal a4fc <__sinit> + a1cc: 00004797 auipc a5,0x4 + a1d0: 01478793 addi a5,a5,20 # e1e0 <__sf_fake_stdin> + a1d4: 02f41b63 bne s0,a5,a20a <__swsetup_r+0x5c> + a1d8: 40c0 lw s0,4(s1) + a1da: 00c41703 lh a4,12(s0) + a1de: 01071793 slli a5,a4,0x10 + a1e2: 83c1 srli a5,a5,0x10 + a1e4: 0087f693 andi a3,a5,8 + a1e8: eab5 bnez a3,a25c <__swsetup_r+0xae> + a1ea: 0107f693 andi a3,a5,16 + a1ee: ee95 bnez a3,a22a <__swsetup_r+0x7c> + a1f0: 47a5 li a5,9 + a1f2: 00f92023 sw a5,0(s2) + a1f6: 04076713 ori a4,a4,64 + a1fa: a45a sh a4,12(s0) + a1fc: 557d li a0,-1 + a1fe: 40b2 lw ra,12(sp) + a200: 4422 lw s0,8(sp) + a202: 4492 lw s1,4(sp) + a204: 4902 lw s2,0(sp) + a206: 0141 addi sp,sp,16 + a208: 8082 ret + a20a: 00004797 auipc a5,0x4 + a20e: ff678793 addi a5,a5,-10 # e200 <__sf_fake_stdout> + a212: 00f41463 bne s0,a5,a21a <__swsetup_r+0x6c> + a216: 4480 lw s0,8(s1) + a218: b7c9 j a1da <__swsetup_r+0x2c> + a21a: 00004797 auipc a5,0x4 + a21e: fa678793 addi a5,a5,-90 # e1c0 <__sf_fake_stderr> + a222: faf41ce3 bne s0,a5,a1da <__swsetup_r+0x2c> + a226: 44c0 lw s0,12(s1) + a228: bf4d j a1da <__swsetup_r+0x2c> + a22a: 8b91 andi a5,a5,4 + a22c: c785 beqz a5,a254 <__swsetup_r+0xa6> + a22e: 584c lw a1,52(s0) + a230: c991 beqz a1,a244 <__swsetup_r+0x96> + a232: 04440793 addi a5,s0,68 + a236: 00f58563 beq a1,a5,a240 <__swsetup_r+0x92> + a23a: 854a mv a0,s2 + a23c: 80fff0ef jal ra,9a4a <_free_r> + a240: 02042a23 sw zero,52(s0) + a244: 245e lhu a5,12(s0) + a246: 00042223 sw zero,4(s0) + a24a: fdb7f793 andi a5,a5,-37 + a24e: a45e sh a5,12(s0) + a250: 481c lw a5,16(s0) + a252: c01c sw a5,0(s0) + a254: 245e lhu a5,12(s0) + a256: 0087e793 ori a5,a5,8 + a25a: a45e sh a5,12(s0) + a25c: 481c lw a5,16(s0) + a25e: eb99 bnez a5,a274 <__swsetup_r+0xc6> + a260: 245e lhu a5,12(s0) + a262: 20000713 li a4,512 + a266: 2807f793 andi a5,a5,640 + a26a: 00e78563 beq a5,a4,a274 <__swsetup_r+0xc6> + a26e: 85a2 mv a1,s0 + a270: 854a mv a0,s2 + a272: 29a1 jal a6ca <__smakebuf_r> + a274: 245e lhu a5,12(s0) + a276: 0017f713 andi a4,a5,1 + a27a: c31d beqz a4,a2a0 <__swsetup_r+0xf2> + a27c: 485c lw a5,20(s0) + a27e: 00042423 sw zero,8(s0) + a282: 40f007b3 neg a5,a5 + a286: cc1c sw a5,24(s0) + a288: 481c lw a5,16(s0) + a28a: 4501 li a0,0 + a28c: fbad bnez a5,a1fe <__swsetup_r+0x50> + a28e: 00c41783 lh a5,12(s0) + a292: 0807f713 andi a4,a5,128 + a296: d725 beqz a4,a1fe <__swsetup_r+0x50> + a298: 0407e793 ori a5,a5,64 + a29c: a45e sh a5,12(s0) + a29e: bfb9 j a1fc <__swsetup_r+0x4e> + a2a0: 8b89 andi a5,a5,2 + a2a2: 4701 li a4,0 + a2a4: e391 bnez a5,a2a8 <__swsetup_r+0xfa> + a2a6: 4858 lw a4,20(s0) + a2a8: c418 sw a4,8(s0) + a2aa: bff9 j a288 <__swsetup_r+0xda> + +0000a2ac <__sflush_r>: + a2ac: 25de lhu a5,12(a1) + a2ae: 1101 addi sp,sp,-32 + a2b0: cc22 sw s0,24(sp) + a2b2: ca26 sw s1,20(sp) + a2b4: ce06 sw ra,28(sp) + a2b6: c84a sw s2,16(sp) + a2b8: c64e sw s3,12(sp) + a2ba: 0087f713 andi a4,a5,8 + a2be: 84aa mv s1,a0 + a2c0: 842e mv s0,a1 + a2c2: ef61 bnez a4,a39a <__sflush_r+0xee> + a2c4: 41d8 lw a4,4(a1) + a2c6: 00e04d63 bgtz a4,a2e0 <__sflush_r+0x34> + a2ca: 41b8 lw a4,64(a1) + a2cc: 00e04a63 bgtz a4,a2e0 <__sflush_r+0x34> + a2d0: 4501 li a0,0 + a2d2: 40f2 lw ra,28(sp) + a2d4: 4462 lw s0,24(sp) + a2d6: 44d2 lw s1,20(sp) + a2d8: 4942 lw s2,16(sp) + a2da: 49b2 lw s3,12(sp) + a2dc: 6105 addi sp,sp,32 + a2de: 8082 ret + a2e0: 5458 lw a4,44(s0) + a2e2: d77d beqz a4,a2d0 <__sflush_r+0x24> + a2e4: 0004a903 lw s2,0(s1) + a2e8: 01379693 slli a3,a5,0x13 + a2ec: 0004a023 sw zero,0(s1) + a2f0: 0606dc63 bgez a3,a368 <__sflush_r+0xbc> + a2f4: 4870 lw a2,84(s0) + a2f6: 245e lhu a5,12(s0) + a2f8: 8b91 andi a5,a5,4 + a2fa: c799 beqz a5,a308 <__sflush_r+0x5c> + a2fc: 405c lw a5,4(s0) + a2fe: 8e1d sub a2,a2,a5 + a300: 585c lw a5,52(s0) + a302: c399 beqz a5,a308 <__sflush_r+0x5c> + a304: 403c lw a5,64(s0) + a306: 8e1d sub a2,a2,a5 + a308: 545c lw a5,44(s0) + a30a: 500c lw a1,32(s0) + a30c: 4681 li a3,0 + a30e: 8526 mv a0,s1 + a310: 9782 jalr a5 + a312: 57fd li a5,-1 + a314: 245a lhu a4,12(s0) + a316: 00f51d63 bne a0,a5,a330 <__sflush_r+0x84> + a31a: 4094 lw a3,0(s1) + a31c: 47f5 li a5,29 + a31e: 06d7e963 bltu a5,a3,a390 <__sflush_r+0xe4> + a322: 204007b7 lui a5,0x20400 + a326: 0785 addi a5,a5,1 + a328: 00d7d7b3 srl a5,a5,a3 + a32c: 8b85 andi a5,a5,1 + a32e: c3ad beqz a5,a390 <__sflush_r+0xe4> + a330: 481c lw a5,16(s0) + a332: 00042223 sw zero,4(s0) + a336: c01c sw a5,0(s0) + a338: 01371793 slli a5,a4,0x13 + a33c: 0007d863 bgez a5,a34c <__sflush_r+0xa0> + a340: 57fd li a5,-1 + a342: 00f51463 bne a0,a5,a34a <__sflush_r+0x9e> + a346: 409c lw a5,0(s1) + a348: e391 bnez a5,a34c <__sflush_r+0xa0> + a34a: c868 sw a0,84(s0) + a34c: 584c lw a1,52(s0) + a34e: 0124a023 sw s2,0(s1) + a352: ddbd beqz a1,a2d0 <__sflush_r+0x24> + a354: 04440793 addi a5,s0,68 + a358: 00f58563 beq a1,a5,a362 <__sflush_r+0xb6> + a35c: 8526 mv a0,s1 + a35e: eecff0ef jal ra,9a4a <_free_r> + a362: 02042a23 sw zero,52(s0) + a366: b7ad j a2d0 <__sflush_r+0x24> + a368: 500c lw a1,32(s0) + a36a: 4601 li a2,0 + a36c: 4685 li a3,1 + a36e: 8526 mv a0,s1 + a370: 9702 jalr a4 + a372: 57fd li a5,-1 + a374: 862a mv a2,a0 + a376: f8f510e3 bne a0,a5,a2f6 <__sflush_r+0x4a> + a37a: 409c lw a5,0(s1) + a37c: dfad beqz a5,a2f6 <__sflush_r+0x4a> + a37e: 4775 li a4,29 + a380: 00e78563 beq a5,a4,a38a <__sflush_r+0xde> + a384: 4759 li a4,22 + a386: 04e79363 bne a5,a4,a3cc <__sflush_r+0x120> + a38a: 0124a023 sw s2,0(s1) + a38e: b789 j a2d0 <__sflush_r+0x24> + a390: 04076713 ori a4,a4,64 + a394: a45a sh a4,12(s0) + a396: 557d li a0,-1 + a398: bf2d j a2d2 <__sflush_r+0x26> + a39a: 0105a983 lw s3,16(a1) + a39e: f20989e3 beqz s3,a2d0 <__sflush_r+0x24> + a3a2: 0005a903 lw s2,0(a1) + a3a6: 8b8d andi a5,a5,3 + a3a8: 0135a023 sw s3,0(a1) + a3ac: 41390933 sub s2,s2,s3 + a3b0: 4701 li a4,0 + a3b2: e391 bnez a5,a3b6 <__sflush_r+0x10a> + a3b4: 49d8 lw a4,20(a1) + a3b6: c418 sw a4,8(s0) + a3b8: f1205ce3 blez s2,a2d0 <__sflush_r+0x24> + a3bc: 541c lw a5,40(s0) + a3be: 500c lw a1,32(s0) + a3c0: 86ca mv a3,s2 + a3c2: 864e mv a2,s3 + a3c4: 8526 mv a0,s1 + a3c6: 9782 jalr a5 + a3c8: 00a04763 bgtz a0,a3d6 <__sflush_r+0x12a> + a3cc: 245e lhu a5,12(s0) + a3ce: 0407e793 ori a5,a5,64 + a3d2: a45e sh a5,12(s0) + a3d4: b7c9 j a396 <__sflush_r+0xea> + a3d6: 99aa add s3,s3,a0 + a3d8: 40a90933 sub s2,s2,a0 + a3dc: bff1 j a3b8 <__sflush_r+0x10c> + +0000a3de <_fflush_r>: + a3de: 499c lw a5,16(a1) + a3e0: c3a5 beqz a5,a440 <_fflush_r+0x62> + a3e2: 1101 addi sp,sp,-32 + a3e4: cc22 sw s0,24(sp) + a3e6: ce06 sw ra,28(sp) + a3e8: 842a mv s0,a0 + a3ea: c511 beqz a0,a3f6 <_fflush_r+0x18> + a3ec: 4d1c lw a5,24(a0) + a3ee: e781 bnez a5,a3f6 <_fflush_r+0x18> + a3f0: c62e sw a1,12(sp) + a3f2: 2229 jal a4fc <__sinit> + a3f4: 45b2 lw a1,12(sp) + a3f6: 00004797 auipc a5,0x4 + a3fa: dea78793 addi a5,a5,-534 # e1e0 <__sf_fake_stdin> + a3fe: 00f59c63 bne a1,a5,a416 <_fflush_r+0x38> + a402: 404c lw a1,4(s0) + a404: 00c59783 lh a5,12(a1) + a408: c79d beqz a5,a436 <_fflush_r+0x58> + a40a: 8522 mv a0,s0 + a40c: 4462 lw s0,24(sp) + a40e: 40f2 lw ra,28(sp) + a410: 6105 addi sp,sp,32 + a412: e9bff06f j a2ac <__sflush_r> + a416: 00004797 auipc a5,0x4 + a41a: dea78793 addi a5,a5,-534 # e200 <__sf_fake_stdout> + a41e: 00f59463 bne a1,a5,a426 <_fflush_r+0x48> + a422: 440c lw a1,8(s0) + a424: b7c5 j a404 <_fflush_r+0x26> + a426: 00004797 auipc a5,0x4 + a42a: d9a78793 addi a5,a5,-614 # e1c0 <__sf_fake_stderr> + a42e: fcf59be3 bne a1,a5,a404 <_fflush_r+0x26> + a432: 444c lw a1,12(s0) + a434: bfc1 j a404 <_fflush_r+0x26> + a436: 40f2 lw ra,28(sp) + a438: 4462 lw s0,24(sp) + a43a: 4501 li a0,0 + a43c: 6105 addi sp,sp,32 + a43e: 8082 ret + a440: 4501 li a0,0 + a442: 8082 ret + +0000a444 : + a444: 1141 addi sp,sp,-16 + a446: c422 sw s0,8(sp) + a448: c606 sw ra,12(sp) + a44a: 842a mv s0,a0 + a44c: a54e sh a1,12(a0) + a44e: a572 sh a2,14(a0) + a450: 00052023 sw zero,0(a0) + a454: 00052223 sw zero,4(a0) + a458: 00052423 sw zero,8(a0) + a45c: 06052223 sw zero,100(a0) + a460: 00052823 sw zero,16(a0) + a464: 00052a23 sw zero,20(a0) + a468: 00052c23 sw zero,24(a0) + a46c: 4621 li a2,8 + a46e: 4581 li a1,0 + a470: 05c50513 addi a0,a0,92 + a474: dadf50ef jal ra,220 + a478: 00001797 auipc a5,0x1 + a47c: d5e78793 addi a5,a5,-674 # b1d6 <__sread> + a480: d05c sw a5,36(s0) + a482: 00001797 auipc a5,0x1 + a486: d8078793 addi a5,a5,-640 # b202 <__swrite> + a48a: d41c sw a5,40(s0) + a48c: 00001797 auipc a5,0x1 + a490: dbe78793 addi a5,a5,-578 # b24a <__sseek> + a494: d45c sw a5,44(s0) + a496: 00001797 auipc a5,0x1 + a49a: de478793 addi a5,a5,-540 # b27a <__sclose> + a49e: d000 sw s0,32(s0) + a4a0: d81c sw a5,48(s0) + a4a2: 40b2 lw ra,12(sp) + a4a4: 4422 lw s0,8(sp) + a4a6: 0141 addi sp,sp,16 + a4a8: 8082 ret + +0000a4aa <_cleanup_r>: + a4aa: 00000597 auipc a1,0x0 + a4ae: f3458593 addi a1,a1,-204 # a3de <_fflush_r> + a4b2: aa99 j a608 <_fwalk_reent> + +0000a4b4 <__sfmoreglue>: + a4b4: 1141 addi sp,sp,-16 + a4b6: c226 sw s1,4(sp) + a4b8: 06800613 li a2,104 + a4bc: fff58493 addi s1,a1,-1 + a4c0: 02c484b3 mul s1,s1,a2 + a4c4: c04a sw s2,0(sp) + a4c6: 892e mv s2,a1 + a4c8: c422 sw s0,8(sp) + a4ca: c606 sw ra,12(sp) + a4cc: 07448593 addi a1,s1,116 + a4d0: e22ff0ef jal ra,9af2 <_malloc_r> + a4d4: 842a mv s0,a0 + a4d6: cd01 beqz a0,a4ee <__sfmoreglue+0x3a> + a4d8: 00052023 sw zero,0(a0) + a4dc: 01252223 sw s2,4(a0) + a4e0: 0531 addi a0,a0,12 + a4e2: c408 sw a0,8(s0) + a4e4: 06848613 addi a2,s1,104 + a4e8: 4581 li a1,0 + a4ea: d37f50ef jal ra,220 + a4ee: 8522 mv a0,s0 + a4f0: 40b2 lw ra,12(sp) + a4f2: 4422 lw s0,8(sp) + a4f4: 4492 lw s1,4(sp) + a4f6: 4902 lw s2,0(sp) + a4f8: 0141 addi sp,sp,16 + a4fa: 8082 ret + +0000a4fc <__sinit>: + a4fc: 4d1c lw a5,24(a0) + a4fe: e7a5 bnez a5,a566 <__sinit+0x6a> + a500: 1141 addi sp,sp,-16 + a502: c606 sw ra,12(sp) + a504: c422 sw s0,8(sp) + a506: 00000797 auipc a5,0x0 + a50a: fa478793 addi a5,a5,-92 # a4aa <_cleanup_r> + a50e: d51c sw a5,40(a0) + a510: 81018793 addi a5,gp,-2032 # 20000200 <_global_impure_ptr> + a514: 439c lw a5,0(a5) + a516: 04052423 sw zero,72(a0) + a51a: 04052623 sw zero,76(a0) + a51e: 04052823 sw zero,80(a0) + a522: 00f51463 bne a0,a5,a52a <__sinit+0x2e> + a526: 4785 li a5,1 + a528: cd1c sw a5,24(a0) + a52a: 842a mv s0,a0 + a52c: 2835 jal a568 <__sfp> + a52e: c048 sw a0,4(s0) + a530: 8522 mv a0,s0 + a532: 281d jal a568 <__sfp> + a534: c408 sw a0,8(s0) + a536: 8522 mv a0,s0 + a538: 2805 jal a568 <__sfp> + a53a: c448 sw a0,12(s0) + a53c: 4048 lw a0,4(s0) + a53e: 4601 li a2,0 + a540: 4591 li a1,4 + a542: f03ff0ef jal ra,a444 + a546: 4408 lw a0,8(s0) + a548: 4605 li a2,1 + a54a: 45a5 li a1,9 + a54c: ef9ff0ef jal ra,a444 + a550: 4448 lw a0,12(s0) + a552: 4609 li a2,2 + a554: 45c9 li a1,18 + a556: eefff0ef jal ra,a444 + a55a: 4785 li a5,1 + a55c: cc1c sw a5,24(s0) + a55e: 40b2 lw ra,12(sp) + a560: 4422 lw s0,8(sp) + a562: 0141 addi sp,sp,16 + a564: 8082 ret + a566: 8082 ret + +0000a568 <__sfp>: + a568: 1141 addi sp,sp,-16 + a56a: 81018793 addi a5,gp,-2032 # 20000200 <_global_impure_ptr> + a56e: c226 sw s1,4(sp) + a570: 4384 lw s1,0(a5) + a572: c04a sw s2,0(sp) + a574: c606 sw ra,12(sp) + a576: 4c9c lw a5,24(s1) + a578: c422 sw s0,8(sp) + a57a: 892a mv s2,a0 + a57c: e781 bnez a5,a584 <__sfp+0x1c> + a57e: 8526 mv a0,s1 + a580: f7dff0ef jal ra,a4fc <__sinit> + a584: 04848493 addi s1,s1,72 + a588: 4480 lw s0,8(s1) + a58a: 40dc lw a5,4(s1) + a58c: 17fd addi a5,a5,-1 + a58e: 0007d663 bgez a5,a59a <__sfp+0x32> + a592: 409c lw a5,0(s1) + a594: cfb9 beqz a5,a5f2 <__sfp+0x8a> + a596: 4084 lw s1,0(s1) + a598: bfc5 j a588 <__sfp+0x20> + a59a: 00c41703 lh a4,12(s0) + a59e: e739 bnez a4,a5ec <__sfp+0x84> + a5a0: 77c1 lui a5,0xffff0 + a5a2: 0785 addi a5,a5,1 + a5a4: 06042223 sw zero,100(s0) + a5a8: 00042023 sw zero,0(s0) + a5ac: 00042223 sw zero,4(s0) + a5b0: 00042423 sw zero,8(s0) + a5b4: c45c sw a5,12(s0) + a5b6: 00042823 sw zero,16(s0) + a5ba: 00042a23 sw zero,20(s0) + a5be: 00042c23 sw zero,24(s0) + a5c2: 4621 li a2,8 + a5c4: 4581 li a1,0 + a5c6: 05c40513 addi a0,s0,92 + a5ca: c57f50ef jal ra,220 + a5ce: 02042a23 sw zero,52(s0) + a5d2: 02042c23 sw zero,56(s0) + a5d6: 04042423 sw zero,72(s0) + a5da: 04042623 sw zero,76(s0) + a5de: 8522 mv a0,s0 + a5e0: 40b2 lw ra,12(sp) + a5e2: 4422 lw s0,8(sp) + a5e4: 4492 lw s1,4(sp) + a5e6: 4902 lw s2,0(sp) + a5e8: 0141 addi sp,sp,16 + a5ea: 8082 ret + a5ec: 06840413 addi s0,s0,104 + a5f0: bf71 j a58c <__sfp+0x24> + a5f2: 4591 li a1,4 + a5f4: 854a mv a0,s2 + a5f6: ebfff0ef jal ra,a4b4 <__sfmoreglue> + a5fa: c088 sw a0,0(s1) + a5fc: fd49 bnez a0,a596 <__sfp+0x2e> + a5fe: 47b1 li a5,12 + a600: 00f92023 sw a5,0(s2) + a604: 4401 li s0,0 + a606: bfe1 j a5de <__sfp+0x76> + +0000a608 <_fwalk_reent>: + a608: 7179 addi sp,sp,-48 + a60a: d422 sw s0,40(sp) + a60c: d04a sw s2,32(sp) + a60e: cc52 sw s4,24(sp) + a610: ca56 sw s5,20(sp) + a612: c85a sw s6,16(sp) + a614: c65e sw s7,12(sp) + a616: d606 sw ra,44(sp) + a618: d226 sw s1,36(sp) + a61a: ce4e sw s3,28(sp) + a61c: 8a2a mv s4,a0 + a61e: 8aae mv s5,a1 + a620: 04850413 addi s0,a0,72 + a624: 4901 li s2,0 + a626: 4b05 li s6,1 + a628: 5bfd li s7,-1 + a62a: ec09 bnez s0,a644 <_fwalk_reent+0x3c> + a62c: 50b2 lw ra,44(sp) + a62e: 5422 lw s0,40(sp) + a630: 854a mv a0,s2 + a632: 5492 lw s1,36(sp) + a634: 5902 lw s2,32(sp) + a636: 49f2 lw s3,28(sp) + a638: 4a62 lw s4,24(sp) + a63a: 4ad2 lw s5,20(sp) + a63c: 4b42 lw s6,16(sp) + a63e: 4bb2 lw s7,12(sp) + a640: 6145 addi sp,sp,48 + a642: 8082 ret + a644: 4404 lw s1,8(s0) + a646: 00442983 lw s3,4(s0) + a64a: 19fd addi s3,s3,-1 + a64c: 0009d463 bgez s3,a654 <_fwalk_reent+0x4c> + a650: 4000 lw s0,0(s0) + a652: bfe1 j a62a <_fwalk_reent+0x22> + a654: 24de lhu a5,12(s1) + a656: 00fb7b63 bgeu s6,a5,a66c <_fwalk_reent+0x64> + a65a: 00e49783 lh a5,14(s1) + a65e: 01778763 beq a5,s7,a66c <_fwalk_reent+0x64> + a662: 85a6 mv a1,s1 + a664: 8552 mv a0,s4 + a666: 9a82 jalr s5 + a668: 00a96933 or s2,s2,a0 + a66c: 06848493 addi s1,s1,104 + a670: bfe9 j a64a <_fwalk_reent+0x42> + +0000a672 <__swhatbuf_r>: + a672: 7119 addi sp,sp,-128 + a674: daa6 sw s1,116(sp) + a676: 84ae mv s1,a1 + a678: 00e59583 lh a1,14(a1) + a67c: dca2 sw s0,120(sp) + a67e: de86 sw ra,124(sp) + a680: 8432 mv s0,a2 + a682: 0005db63 bgez a1,a698 <__swhatbuf_r+0x26> + a686: 24de lhu a5,12(s1) + a688: 0006a023 sw zero,0(a3) + a68c: 0807f793 andi a5,a5,128 + a690: e785 bnez a5,a6b8 <__swhatbuf_r+0x46> + a692: 40000793 li a5,1024 + a696: a01d j a6bc <__swhatbuf_r+0x4a> + a698: 0830 addi a2,sp,24 + a69a: c636 sw a3,12(sp) + a69c: 43b000ef jal ra,b2d6 <_fstat_r> + a6a0: 46b2 lw a3,12(sp) + a6a2: fe0542e3 bltz a0,a686 <__swhatbuf_r+0x14> + a6a6: 4772 lw a4,28(sp) + a6a8: 67bd lui a5,0xf + a6aa: 8ff9 and a5,a5,a4 + a6ac: 7779 lui a4,0xffffe + a6ae: 97ba add a5,a5,a4 + a6b0: 0017b793 seqz a5,a5 + a6b4: c29c sw a5,0(a3) + a6b6: bff1 j a692 <__swhatbuf_r+0x20> + a6b8: 04000793 li a5,64 + a6bc: c01c sw a5,0(s0) + a6be: 50f6 lw ra,124(sp) + a6c0: 5466 lw s0,120(sp) + a6c2: 54d6 lw s1,116(sp) + a6c4: 4501 li a0,0 + a6c6: 6109 addi sp,sp,128 + a6c8: 8082 ret + +0000a6ca <__smakebuf_r>: + a6ca: 25de lhu a5,12(a1) + a6cc: 1101 addi sp,sp,-32 + a6ce: cc22 sw s0,24(sp) + a6d0: ce06 sw ra,28(sp) + a6d2: ca26 sw s1,20(sp) + a6d4: c84a sw s2,16(sp) + a6d6: 8b89 andi a5,a5,2 + a6d8: 842e mv s0,a1 + a6da: cf89 beqz a5,a6f4 <__smakebuf_r+0x2a> + a6dc: 04740793 addi a5,s0,71 + a6e0: c01c sw a5,0(s0) + a6e2: c81c sw a5,16(s0) + a6e4: 4785 li a5,1 + a6e6: c85c sw a5,20(s0) + a6e8: 40f2 lw ra,28(sp) + a6ea: 4462 lw s0,24(sp) + a6ec: 44d2 lw s1,20(sp) + a6ee: 4942 lw s2,16(sp) + a6f0: 6105 addi sp,sp,32 + a6f2: 8082 ret + a6f4: 0074 addi a3,sp,12 + a6f6: 0030 addi a2,sp,8 + a6f8: 84aa mv s1,a0 + a6fa: f79ff0ef jal ra,a672 <__swhatbuf_r> + a6fe: 45a2 lw a1,8(sp) + a700: 892a mv s2,a0 + a702: 8526 mv a0,s1 + a704: beeff0ef jal ra,9af2 <_malloc_r> + a708: e919 bnez a0,a71e <__smakebuf_r+0x54> + a70a: 00c41783 lh a5,12(s0) + a70e: 2007f713 andi a4,a5,512 + a712: fb79 bnez a4,a6e8 <__smakebuf_r+0x1e> + a714: 9bf1 andi a5,a5,-4 + a716: 0027e793 ori a5,a5,2 + a71a: a45e sh a5,12(s0) + a71c: b7c1 j a6dc <__smakebuf_r+0x12> + a71e: 00000797 auipc a5,0x0 + a722: d8c78793 addi a5,a5,-628 # a4aa <_cleanup_r> + a726: d49c sw a5,40(s1) + a728: 245e lhu a5,12(s0) + a72a: c008 sw a0,0(s0) + a72c: c808 sw a0,16(s0) + a72e: 0807e793 ori a5,a5,128 + a732: a45e sh a5,12(s0) + a734: 47a2 lw a5,8(sp) + a736: c85c sw a5,20(s0) + a738: 47b2 lw a5,12(sp) + a73a: cf81 beqz a5,a752 <__smakebuf_r+0x88> + a73c: 00e41583 lh a1,14(s0) + a740: 8526 mv a0,s1 + a742: 3bf000ef jal ra,b300 <_isatty_r> + a746: c511 beqz a0,a752 <__smakebuf_r+0x88> + a748: 245e lhu a5,12(s0) + a74a: 9bf1 andi a5,a5,-4 + a74c: 0017e793 ori a5,a5,1 + a750: a45e sh a5,12(s0) + a752: 245e lhu a5,12(s0) + a754: 00f96933 or s2,s2,a5 + a758: 01241623 sh s2,12(s0) + a75c: b771 j a6e8 <__smakebuf_r+0x1e> + +0000a75e <__malloc_lock>: + a75e: 8082 ret + +0000a760 <__malloc_unlock>: + a760: 8082 ret + +0000a762 <__ssputs_r>: + a762: 1101 addi sp,sp,-32 + a764: c84a sw s2,16(sp) + a766: 0085a903 lw s2,8(a1) + a76a: cc22 sw s0,24(sp) + a76c: c452 sw s4,8(sp) + a76e: c05a sw s6,0(sp) + a770: ce06 sw ra,28(sp) + a772: ca26 sw s1,20(sp) + a774: c64e sw s3,12(sp) + a776: c256 sw s5,4(sp) + a778: 842e mv s0,a1 + a77a: 8b32 mv s6,a2 + a77c: 8a36 mv s4,a3 + a77e: 0926e963 bltu a3,s2,a810 <__ssputs_r+0xae> + a782: 25de lhu a5,12(a1) + a784: 4807f713 andi a4,a5,1152 + a788: c351 beqz a4,a80c <__ssputs_r+0xaa> + a78a: 4004 lw s1,0(s0) + a78c: 498c lw a1,16(a1) + a78e: 4858 lw a4,20(s0) + a790: 8aaa mv s5,a0 + a792: 40b489b3 sub s3,s1,a1 + a796: 448d li s1,3 + a798: 02e484b3 mul s1,s1,a4 + a79c: 4709 li a4,2 + a79e: 02e4c4b3 div s1,s1,a4 + a7a2: 00168713 addi a4,a3,1 + a7a6: 974e add a4,a4,s3 + a7a8: 00e4f363 bgeu s1,a4,a7ae <__ssputs_r+0x4c> + a7ac: 84ba mv s1,a4 + a7ae: 4007f793 andi a5,a5,1024 + a7b2: cfbd beqz a5,a830 <__ssputs_r+0xce> + a7b4: 85a6 mv a1,s1 + a7b6: 8556 mv a0,s5 + a7b8: b3aff0ef jal ra,9af2 <_malloc_r> + a7bc: 892a mv s2,a0 + a7be: e11d bnez a0,a7e4 <__ssputs_r+0x82> + a7c0: 47b1 li a5,12 + a7c2: 00faa023 sw a5,0(s5) + a7c6: 245e lhu a5,12(s0) + a7c8: 557d li a0,-1 + a7ca: 0407e793 ori a5,a5,64 + a7ce: a45e sh a5,12(s0) + a7d0: 40f2 lw ra,28(sp) + a7d2: 4462 lw s0,24(sp) + a7d4: 44d2 lw s1,20(sp) + a7d6: 4942 lw s2,16(sp) + a7d8: 49b2 lw s3,12(sp) + a7da: 4a22 lw s4,8(sp) + a7dc: 4a92 lw s5,4(sp) + a7de: 4b02 lw s6,0(sp) + a7e0: 6105 addi sp,sp,32 + a7e2: 8082 ret + a7e4: 480c lw a1,16(s0) + a7e6: 864e mv a2,s3 + a7e8: 96aff0ef jal ra,9952 + a7ec: 245e lhu a5,12(s0) + a7ee: b7f7f793 andi a5,a5,-1153 + a7f2: 0807e793 ori a5,a5,128 + a7f6: a45e sh a5,12(s0) + a7f8: 01242823 sw s2,16(s0) + a7fc: c844 sw s1,20(s0) + a7fe: 994e add s2,s2,s3 + a800: 413484b3 sub s1,s1,s3 + a804: 01242023 sw s2,0(s0) + a808: c404 sw s1,8(s0) + a80a: 8952 mv s2,s4 + a80c: 012a7363 bgeu s4,s2,a812 <__ssputs_r+0xb0> + a810: 8952 mv s2,s4 + a812: 4008 lw a0,0(s0) + a814: 864a mv a2,s2 + a816: 85da mv a1,s6 + a818: 9ecff0ef jal ra,9a04 + a81c: 441c lw a5,8(s0) + a81e: 4501 li a0,0 + a820: 412787b3 sub a5,a5,s2 + a824: c41c sw a5,8(s0) + a826: 401c lw a5,0(s0) + a828: 993e add s2,s2,a5 + a82a: 01242023 sw s2,0(s0) + a82e: b74d j a7d0 <__ssputs_r+0x6e> + a830: 8626 mv a2,s1 + a832: 8556 mv a0,s5 + a834: 339000ef jal ra,b36c <_realloc_r> + a838: 892a mv s2,a0 + a83a: fd5d bnez a0,a7f8 <__ssputs_r+0x96> + a83c: 480c lw a1,16(s0) + a83e: 8556 mv a0,s5 + a840: a0aff0ef jal ra,9a4a <_free_r> + a844: bfb5 j a7c0 <__ssputs_r+0x5e> + +0000a846 <_svfiprintf_r>: + a846: 25de lhu a5,12(a1) + a848: 7171 addi sp,sp,-176 + a84a: d326 sw s1,164(sp) + a84c: d14a sw s2,160(sp) + a84e: cf4e sw s3,156(sp) + a850: d706 sw ra,172(sp) + a852: d522 sw s0,168(sp) + a854: cd52 sw s4,152(sp) + a856: cb56 sw s5,148(sp) + a858: c95a sw s6,144(sp) + a85a: c75e sw s7,140(sp) + a85c: c562 sw s8,136(sp) + a85e: c366 sw s9,132(sp) + a860: 0807f793 andi a5,a5,128 + a864: 89aa mv s3,a0 + a866: 892e mv s2,a1 + a868: 84b2 mv s1,a2 + a86a: c3b9 beqz a5,a8b0 <_svfiprintf_r+0x6a> + a86c: 499c lw a5,16(a1) + a86e: e3a9 bnez a5,a8b0 <_svfiprintf_r+0x6a> + a870: 04000593 li a1,64 + a874: c636 sw a3,12(sp) + a876: a7cff0ef jal ra,9af2 <_malloc_r> + a87a: 00a92023 sw a0,0(s2) + a87e: 00a92823 sw a0,16(s2) + a882: 46b2 lw a3,12(sp) + a884: e115 bnez a0,a8a8 <_svfiprintf_r+0x62> + a886: 47b1 li a5,12 + a888: 00f9a023 sw a5,0(s3) + a88c: 557d li a0,-1 + a88e: 50ba lw ra,172(sp) + a890: 542a lw s0,168(sp) + a892: 549a lw s1,164(sp) + a894: 590a lw s2,160(sp) + a896: 49fa lw s3,156(sp) + a898: 4a6a lw s4,152(sp) + a89a: 4ada lw s5,148(sp) + a89c: 4b4a lw s6,144(sp) + a89e: 4bba lw s7,140(sp) + a8a0: 4c2a lw s8,136(sp) + a8a2: 4c9a lw s9,132(sp) + a8a4: 614d addi sp,sp,176 + a8a6: 8082 ret + a8a8: 04000793 li a5,64 + a8ac: 00f92a23 sw a5,20(s2) + a8b0: 02000793 li a5,32 + a8b4: 02f10ca3 sb a5,57(sp) + a8b8: 03000793 li a5,48 + a8bc: da02 sw zero,52(sp) + a8be: 02f10d23 sb a5,58(sp) + a8c2: ce36 sw a3,28(sp) + a8c4: 02500b93 li s7,37 + a8c8: 00004a97 auipc s5,0x4 + a8cc: 958a8a93 addi s5,s5,-1704 # e220 <__sf_fake_stdout+0x20> + a8d0: 4c05 li s8,1 + a8d2: 4b29 li s6,10 + a8d4: 8426 mv s0,s1 + a8d6: 201c lbu a5,0(s0) + a8d8: c399 beqz a5,a8de <_svfiprintf_r+0x98> + a8da: 09779963 bne a5,s7,a96c <_svfiprintf_r+0x126> + a8de: 40940cb3 sub s9,s0,s1 + a8e2: 000c8e63 beqz s9,a8fe <_svfiprintf_r+0xb8> + a8e6: 86e6 mv a3,s9 + a8e8: 8626 mv a2,s1 + a8ea: 85ca mv a1,s2 + a8ec: 854e mv a0,s3 + a8ee: e75ff0ef jal ra,a762 <__ssputs_r> + a8f2: 57fd li a5,-1 + a8f4: 18f50b63 beq a0,a5,aa8a <_svfiprintf_r+0x244> + a8f8: 56d2 lw a3,52(sp) + a8fa: 96e6 add a3,a3,s9 + a8fc: da36 sw a3,52(sp) + a8fe: 201c lbu a5,0(s0) + a900: 18078563 beqz a5,aa8a <_svfiprintf_r+0x244> + a904: 57fd li a5,-1 + a906: 00140493 addi s1,s0,1 + a90a: d002 sw zero,32(sp) + a90c: d602 sw zero,44(sp) + a90e: d23e sw a5,36(sp) + a910: d402 sw zero,40(sp) + a912: 060101a3 sb zero,99(sp) + a916: dc82 sw zero,120(sp) + a918: 208c lbu a1,0(s1) + a91a: 4615 li a2,5 + a91c: 8556 mv a0,s5 + a91e: 237000ef jal ra,b354 + a922: 00148413 addi s0,s1,1 + a926: 5782 lw a5,32(sp) + a928: e521 bnez a0,a970 <_svfiprintf_r+0x12a> + a92a: 0107f713 andi a4,a5,16 + a92e: c709 beqz a4,a938 <_svfiprintf_r+0xf2> + a930: 02000713 li a4,32 + a934: 06e101a3 sb a4,99(sp) + a938: 0087f713 andi a4,a5,8 + a93c: c709 beqz a4,a946 <_svfiprintf_r+0x100> + a93e: 02b00713 li a4,43 + a942: 06e101a3 sb a4,99(sp) + a946: 2094 lbu a3,0(s1) + a948: 02a00713 li a4,42 + a94c: 02e68a63 beq a3,a4,a980 <_svfiprintf_r+0x13a> + a950: 57b2 lw a5,44(sp) + a952: 8426 mv s0,s1 + a954: 4681 li a3,0 + a956: 4625 li a2,9 + a958: 2018 lbu a4,0(s0) + a95a: 00140593 addi a1,s0,1 + a95e: fd070713 addi a4,a4,-48 # ffffdfd0 <_eusrstack+0xdfff5fd0> + a962: 06e67263 bgeu a2,a4,a9c6 <_svfiprintf_r+0x180> + a966: c68d beqz a3,a990 <_svfiprintf_r+0x14a> + a968: d63e sw a5,44(sp) + a96a: a01d j a990 <_svfiprintf_r+0x14a> + a96c: 0405 addi s0,s0,1 + a96e: b7a5 j a8d6 <_svfiprintf_r+0x90> + a970: 41550533 sub a0,a0,s5 + a974: 00ac1533 sll a0,s8,a0 + a978: 8fc9 or a5,a5,a0 + a97a: d03e sw a5,32(sp) + a97c: 84a2 mv s1,s0 + a97e: bf69 j a918 <_svfiprintf_r+0xd2> + a980: 4772 lw a4,28(sp) + a982: 00470693 addi a3,a4,4 + a986: 4318 lw a4,0(a4) + a988: ce36 sw a3,28(sp) + a98a: 02074763 bltz a4,a9b8 <_svfiprintf_r+0x172> + a98e: d63a sw a4,44(sp) + a990: 2018 lbu a4,0(s0) + a992: 02e00793 li a5,46 + a996: 04f71d63 bne a4,a5,a9f0 <_svfiprintf_r+0x1aa> + a99a: 3018 lbu a4,1(s0) + a99c: 02a00793 li a5,42 + a9a0: 02f71b63 bne a4,a5,a9d6 <_svfiprintf_r+0x190> + a9a4: 47f2 lw a5,28(sp) + a9a6: 0409 addi s0,s0,2 + a9a8: 00478713 addi a4,a5,4 + a9ac: 439c lw a5,0(a5) + a9ae: ce3a sw a4,28(sp) + a9b0: 0207c163 bltz a5,a9d2 <_svfiprintf_r+0x18c> + a9b4: d23e sw a5,36(sp) + a9b6: a82d j a9f0 <_svfiprintf_r+0x1aa> + a9b8: 40e00733 neg a4,a4 + a9bc: 0027e793 ori a5,a5,2 + a9c0: d63a sw a4,44(sp) + a9c2: d03e sw a5,32(sp) + a9c4: b7f1 j a990 <_svfiprintf_r+0x14a> + a9c6: 036787b3 mul a5,a5,s6 + a9ca: 4685 li a3,1 + a9cc: 842e mv s0,a1 + a9ce: 97ba add a5,a5,a4 + a9d0: b761 j a958 <_svfiprintf_r+0x112> + a9d2: 57fd li a5,-1 + a9d4: b7c5 j a9b4 <_svfiprintf_r+0x16e> + a9d6: 0405 addi s0,s0,1 + a9d8: d202 sw zero,36(sp) + a9da: 4681 li a3,0 + a9dc: 4781 li a5,0 + a9de: 4625 li a2,9 + a9e0: 2018 lbu a4,0(s0) + a9e2: 00140593 addi a1,s0,1 + a9e6: fd070713 addi a4,a4,-48 + a9ea: 06e67663 bgeu a2,a4,aa56 <_svfiprintf_r+0x210> + a9ee: f2f9 bnez a3,a9b4 <_svfiprintf_r+0x16e> + a9f0: 200c lbu a1,0(s0) + a9f2: 460d li a2,3 + a9f4: 00004517 auipc a0,0x4 + a9f8: 83450513 addi a0,a0,-1996 # e228 <__sf_fake_stdout+0x28> + a9fc: 159000ef jal ra,b354 + aa00: cd11 beqz a0,aa1c <_svfiprintf_r+0x1d6> + aa02: 00004797 auipc a5,0x4 + aa06: 82678793 addi a5,a5,-2010 # e228 <__sf_fake_stdout+0x28> + aa0a: 8d1d sub a0,a0,a5 + aa0c: 04000793 li a5,64 + aa10: 00a797b3 sll a5,a5,a0 + aa14: 5502 lw a0,32(sp) + aa16: 0405 addi s0,s0,1 + aa18: 8d5d or a0,a0,a5 + aa1a: d02a sw a0,32(sp) + aa1c: 200c lbu a1,0(s0) + aa1e: 4619 li a2,6 + aa20: 00004517 auipc a0,0x4 + aa24: 80c50513 addi a0,a0,-2036 # e22c <__sf_fake_stdout+0x2c> + aa28: 00140493 addi s1,s0,1 + aa2c: 02b10c23 sb a1,56(sp) + aa30: 125000ef jal ra,b354 + aa34: c525 beqz a0,aa9c <_svfiprintf_r+0x256> + aa36: ffff5797 auipc a5,0xffff5 + aa3a: 5ca78793 addi a5,a5,1482 # 0 <_sinit> + aa3e: e795 bnez a5,aa6a <_svfiprintf_r+0x224> + aa40: 5702 lw a4,32(sp) + aa42: 47f2 lw a5,28(sp) + aa44: 10077713 andi a4,a4,256 + aa48: cf09 beqz a4,aa62 <_svfiprintf_r+0x21c> + aa4a: 0791 addi a5,a5,4 + aa4c: ce3e sw a5,28(sp) + aa4e: 57d2 lw a5,52(sp) + aa50: 97d2 add a5,a5,s4 + aa52: da3e sw a5,52(sp) + aa54: b541 j a8d4 <_svfiprintf_r+0x8e> + aa56: 036787b3 mul a5,a5,s6 + aa5a: 4685 li a3,1 + aa5c: 842e mv s0,a1 + aa5e: 97ba add a5,a5,a4 + aa60: b741 j a9e0 <_svfiprintf_r+0x19a> + aa62: 079d addi a5,a5,7 + aa64: 9be1 andi a5,a5,-8 + aa66: 07a1 addi a5,a5,8 + aa68: b7d5 j aa4c <_svfiprintf_r+0x206> + aa6a: 0878 addi a4,sp,28 + aa6c: 00000697 auipc a3,0x0 + aa70: cf668693 addi a3,a3,-778 # a762 <__ssputs_r> + aa74: 864a mv a2,s2 + aa76: 100c addi a1,sp,32 + aa78: 854e mv a0,s3 + aa7a: 00000097 auipc ra,0x0 + aa7e: 000000e7 jalr zero # 0 <_sinit> + aa82: 57fd li a5,-1 + aa84: 8a2a mv s4,a0 + aa86: fcf514e3 bne a0,a5,aa4e <_svfiprintf_r+0x208> + aa8a: 00c95783 lhu a5,12(s2) + aa8e: 557d li a0,-1 + aa90: 0407f793 andi a5,a5,64 + aa94: de079de3 bnez a5,a88e <_svfiprintf_r+0x48> + aa98: 5552 lw a0,52(sp) + aa9a: bbd5 j a88e <_svfiprintf_r+0x48> + aa9c: 0878 addi a4,sp,28 + aa9e: 00000697 auipc a3,0x0 + aaa2: cc468693 addi a3,a3,-828 # a762 <__ssputs_r> + aaa6: 864a mv a2,s2 + aaa8: 100c addi a1,sp,32 + aaaa: 854e mv a0,s3 + aaac: 2111 jal aeb0 <_printf_i> + aaae: bfd1 j aa82 <_svfiprintf_r+0x23c> + +0000aab0 <__sfputc_r>: + aab0: 461c lw a5,8(a2) + aab2: 17fd addi a5,a5,-1 + aab4: c61c sw a5,8(a2) + aab6: 0007da63 bgez a5,aaca <__sfputc_r+0x1a> + aaba: 4e18 lw a4,24(a2) + aabc: 00e7c563 blt a5,a4,aac6 <__sfputc_r+0x16> + aac0: 47a9 li a5,10 + aac2: 00f59463 bne a1,a5,aaca <__sfputc_r+0x1a> + aac6: e0eff06f j a0d4 <__swbuf_r> + aaca: 421c lw a5,0(a2) + aacc: 852e mv a0,a1 + aace: 00178713 addi a4,a5,1 + aad2: c218 sw a4,0(a2) + aad4: a38c sb a1,0(a5) + aad6: 8082 ret + +0000aad8 <__sfputs_r>: + aad8: 1101 addi sp,sp,-32 + aada: cc22 sw s0,24(sp) + aadc: ca26 sw s1,20(sp) + aade: c84a sw s2,16(sp) + aae0: c64e sw s3,12(sp) + aae2: c452 sw s4,8(sp) + aae4: ce06 sw ra,28(sp) + aae6: 892a mv s2,a0 + aae8: 89ae mv s3,a1 + aaea: 8432 mv s0,a2 + aaec: 00d604b3 add s1,a2,a3 + aaf0: 5a7d li s4,-1 + aaf2: 00941463 bne s0,s1,aafa <__sfputs_r+0x22> + aaf6: 4501 li a0,0 + aaf8: a809 j ab0a <__sfputs_r+0x32> + aafa: 200c lbu a1,0(s0) + aafc: 864e mv a2,s3 + aafe: 854a mv a0,s2 + ab00: fb1ff0ef jal ra,aab0 <__sfputc_r> + ab04: 0405 addi s0,s0,1 + ab06: ff4516e3 bne a0,s4,aaf2 <__sfputs_r+0x1a> + ab0a: 40f2 lw ra,28(sp) + ab0c: 4462 lw s0,24(sp) + ab0e: 44d2 lw s1,20(sp) + ab10: 4942 lw s2,16(sp) + ab12: 49b2 lw s3,12(sp) + ab14: 4a22 lw s4,8(sp) + ab16: 6105 addi sp,sp,32 + ab18: 8082 ret + +0000ab1a <_vfiprintf_r>: + ab1a: 7135 addi sp,sp,-160 + ab1c: cd22 sw s0,152(sp) + ab1e: cb26 sw s1,148(sp) + ab20: c94a sw s2,144(sp) + ab22: c74e sw s3,140(sp) + ab24: cf06 sw ra,156(sp) + ab26: c552 sw s4,136(sp) + ab28: c356 sw s5,132(sp) + ab2a: c15a sw s6,128(sp) + ab2c: dede sw s7,124(sp) + ab2e: dce2 sw s8,120(sp) + ab30: dae6 sw s9,116(sp) + ab32: 89aa mv s3,a0 + ab34: 84ae mv s1,a1 + ab36: 8932 mv s2,a2 + ab38: 8436 mv s0,a3 + ab3a: c509 beqz a0,ab44 <_vfiprintf_r+0x2a> + ab3c: 4d1c lw a5,24(a0) + ab3e: e399 bnez a5,ab44 <_vfiprintf_r+0x2a> + ab40: 9bdff0ef jal ra,a4fc <__sinit> + ab44: 00003797 auipc a5,0x3 + ab48: 69c78793 addi a5,a5,1692 # e1e0 <__sf_fake_stdin> + ab4c: 0cf49963 bne s1,a5,ac1e <_vfiprintf_r+0x104> + ab50: 0049a483 lw s1,4(s3) + ab54: 24de lhu a5,12(s1) + ab56: 8ba1 andi a5,a5,8 + ab58: c7ed beqz a5,ac42 <_vfiprintf_r+0x128> + ab5a: 489c lw a5,16(s1) + ab5c: c3fd beqz a5,ac42 <_vfiprintf_r+0x128> + ab5e: 02000793 li a5,32 + ab62: 02f104a3 sb a5,41(sp) + ab66: 03000793 li a5,48 + ab6a: d202 sw zero,36(sp) + ab6c: 02f10523 sb a5,42(sp) + ab70: c622 sw s0,12(sp) + ab72: 02500b93 li s7,37 + ab76: 00003a97 auipc s5,0x3 + ab7a: 6aaa8a93 addi s5,s5,1706 # e220 <__sf_fake_stdout+0x20> + ab7e: 4c05 li s8,1 + ab80: 4b29 li s6,10 + ab82: 844a mv s0,s2 + ab84: 201c lbu a5,0(s0) + ab86: c399 beqz a5,ab8c <_vfiprintf_r+0x72> + ab88: 0f779063 bne a5,s7,ac68 <_vfiprintf_r+0x14e> + ab8c: 41240cb3 sub s9,s0,s2 + ab90: 000c8e63 beqz s9,abac <_vfiprintf_r+0x92> + ab94: 86e6 mv a3,s9 + ab96: 864a mv a2,s2 + ab98: 85a6 mv a1,s1 + ab9a: 854e mv a0,s3 + ab9c: f3dff0ef jal ra,aad8 <__sfputs_r> + aba0: 57fd li a5,-1 + aba2: 1ef50063 beq a0,a5,ad82 <_vfiprintf_r+0x268> + aba6: 5692 lw a3,36(sp) + aba8: 96e6 add a3,a3,s9 + abaa: d236 sw a3,36(sp) + abac: 201c lbu a5,0(s0) + abae: 1c078a63 beqz a5,ad82 <_vfiprintf_r+0x268> + abb2: 57fd li a5,-1 + abb4: 00140913 addi s2,s0,1 + abb8: c802 sw zero,16(sp) + abba: ce02 sw zero,28(sp) + abbc: ca3e sw a5,20(sp) + abbe: cc02 sw zero,24(sp) + abc0: 040109a3 sb zero,83(sp) + abc4: d482 sw zero,104(sp) + abc6: 00094583 lbu a1,0(s2) + abca: 4615 li a2,5 + abcc: 8556 mv a0,s5 + abce: 786000ef jal ra,b354 + abd2: 00190413 addi s0,s2,1 + abd6: 47c2 lw a5,16(sp) + abd8: e951 bnez a0,ac6c <_vfiprintf_r+0x152> + abda: 0107f713 andi a4,a5,16 + abde: c709 beqz a4,abe8 <_vfiprintf_r+0xce> + abe0: 02000713 li a4,32 + abe4: 04e109a3 sb a4,83(sp) + abe8: 0087f713 andi a4,a5,8 + abec: c709 beqz a4,abf6 <_vfiprintf_r+0xdc> + abee: 02b00713 li a4,43 + abf2: 04e109a3 sb a4,83(sp) + abf6: 00094683 lbu a3,0(s2) + abfa: 02a00713 li a4,42 + abfe: 06e68f63 beq a3,a4,ac7c <_vfiprintf_r+0x162> + ac02: 47f2 lw a5,28(sp) + ac04: 844a mv s0,s2 + ac06: 4681 li a3,0 + ac08: 4625 li a2,9 + ac0a: 2018 lbu a4,0(s0) + ac0c: 00140593 addi a1,s0,1 + ac10: fd070713 addi a4,a4,-48 + ac14: 0ae67763 bgeu a2,a4,acc2 <_vfiprintf_r+0x1a8> + ac18: cab5 beqz a3,ac8c <_vfiprintf_r+0x172> + ac1a: ce3e sw a5,28(sp) + ac1c: a885 j ac8c <_vfiprintf_r+0x172> + ac1e: 00003797 auipc a5,0x3 + ac22: 5e278793 addi a5,a5,1506 # e200 <__sf_fake_stdout> + ac26: 00f49563 bne s1,a5,ac30 <_vfiprintf_r+0x116> + ac2a: 0089a483 lw s1,8(s3) + ac2e: b71d j ab54 <_vfiprintf_r+0x3a> + ac30: 00003797 auipc a5,0x3 + ac34: 59078793 addi a5,a5,1424 # e1c0 <__sf_fake_stderr> + ac38: f0f49ee3 bne s1,a5,ab54 <_vfiprintf_r+0x3a> + ac3c: 00c9a483 lw s1,12(s3) + ac40: bf11 j ab54 <_vfiprintf_r+0x3a> + ac42: 85a6 mv a1,s1 + ac44: 854e mv a0,s3 + ac46: d68ff0ef jal ra,a1ae <__swsetup_r> + ac4a: d911 beqz a0,ab5e <_vfiprintf_r+0x44> + ac4c: 557d li a0,-1 + ac4e: 40fa lw ra,156(sp) + ac50: 446a lw s0,152(sp) + ac52: 44da lw s1,148(sp) + ac54: 494a lw s2,144(sp) + ac56: 49ba lw s3,140(sp) + ac58: 4a2a lw s4,136(sp) + ac5a: 4a9a lw s5,132(sp) + ac5c: 4b0a lw s6,128(sp) + ac5e: 5bf6 lw s7,124(sp) + ac60: 5c66 lw s8,120(sp) + ac62: 5cd6 lw s9,116(sp) + ac64: 610d addi sp,sp,160 + ac66: 8082 ret + ac68: 0405 addi s0,s0,1 + ac6a: bf29 j ab84 <_vfiprintf_r+0x6a> + ac6c: 41550533 sub a0,a0,s5 + ac70: 00ac1533 sll a0,s8,a0 + ac74: 8fc9 or a5,a5,a0 + ac76: c83e sw a5,16(sp) + ac78: 8922 mv s2,s0 + ac7a: b7b1 j abc6 <_vfiprintf_r+0xac> + ac7c: 4732 lw a4,12(sp) + ac7e: 00470693 addi a3,a4,4 + ac82: 4318 lw a4,0(a4) + ac84: c636 sw a3,12(sp) + ac86: 02074763 bltz a4,acb4 <_vfiprintf_r+0x19a> + ac8a: ce3a sw a4,28(sp) + ac8c: 2018 lbu a4,0(s0) + ac8e: 02e00793 li a5,46 + ac92: 04f71d63 bne a4,a5,acec <_vfiprintf_r+0x1d2> + ac96: 3018 lbu a4,1(s0) + ac98: 02a00793 li a5,42 + ac9c: 02f71b63 bne a4,a5,acd2 <_vfiprintf_r+0x1b8> + aca0: 47b2 lw a5,12(sp) + aca2: 0409 addi s0,s0,2 + aca4: 00478713 addi a4,a5,4 + aca8: 439c lw a5,0(a5) + acaa: c63a sw a4,12(sp) + acac: 0207c163 bltz a5,acce <_vfiprintf_r+0x1b4> + acb0: ca3e sw a5,20(sp) + acb2: a82d j acec <_vfiprintf_r+0x1d2> + acb4: 40e00733 neg a4,a4 + acb8: 0027e793 ori a5,a5,2 + acbc: ce3a sw a4,28(sp) + acbe: c83e sw a5,16(sp) + acc0: b7f1 j ac8c <_vfiprintf_r+0x172> + acc2: 036787b3 mul a5,a5,s6 + acc6: 4685 li a3,1 + acc8: 842e mv s0,a1 + acca: 97ba add a5,a5,a4 + accc: bf3d j ac0a <_vfiprintf_r+0xf0> + acce: 57fd li a5,-1 + acd0: b7c5 j acb0 <_vfiprintf_r+0x196> + acd2: 0405 addi s0,s0,1 + acd4: ca02 sw zero,20(sp) + acd6: 4681 li a3,0 + acd8: 4781 li a5,0 + acda: 4625 li a2,9 + acdc: 2018 lbu a4,0(s0) + acde: 00140593 addi a1,s0,1 + ace2: fd070713 addi a4,a4,-48 + ace6: 06e67463 bgeu a2,a4,ad4e <_vfiprintf_r+0x234> + acea: f2f9 bnez a3,acb0 <_vfiprintf_r+0x196> + acec: 200c lbu a1,0(s0) + acee: 460d li a2,3 + acf0: 00003517 auipc a0,0x3 + acf4: 53850513 addi a0,a0,1336 # e228 <__sf_fake_stdout+0x28> + acf8: 2db1 jal b354 + acfa: cd11 beqz a0,ad16 <_vfiprintf_r+0x1fc> + acfc: 00003797 auipc a5,0x3 + ad00: 52c78793 addi a5,a5,1324 # e228 <__sf_fake_stdout+0x28> + ad04: 8d1d sub a0,a0,a5 + ad06: 04000793 li a5,64 + ad0a: 00a797b3 sll a5,a5,a0 + ad0e: 4542 lw a0,16(sp) + ad10: 0405 addi s0,s0,1 + ad12: 8d5d or a0,a0,a5 + ad14: c82a sw a0,16(sp) + ad16: 200c lbu a1,0(s0) + ad18: 4619 li a2,6 + ad1a: 00003517 auipc a0,0x3 + ad1e: 51250513 addi a0,a0,1298 # e22c <__sf_fake_stdout+0x2c> + ad22: 00140913 addi s2,s0,1 + ad26: 02b10423 sb a1,40(sp) + ad2a: 252d jal b354 + ad2c: c135 beqz a0,ad90 <_vfiprintf_r+0x276> + ad2e: ffff5797 auipc a5,0xffff5 + ad32: 2d278793 addi a5,a5,722 # 0 <_sinit> + ad36: e795 bnez a5,ad62 <_vfiprintf_r+0x248> + ad38: 4742 lw a4,16(sp) + ad3a: 47b2 lw a5,12(sp) + ad3c: 10077713 andi a4,a4,256 + ad40: cf09 beqz a4,ad5a <_vfiprintf_r+0x240> + ad42: 0791 addi a5,a5,4 + ad44: c63e sw a5,12(sp) + ad46: 5792 lw a5,36(sp) + ad48: 97d2 add a5,a5,s4 + ad4a: d23e sw a5,36(sp) + ad4c: bd1d j ab82 <_vfiprintf_r+0x68> + ad4e: 036787b3 mul a5,a5,s6 + ad52: 4685 li a3,1 + ad54: 842e mv s0,a1 + ad56: 97ba add a5,a5,a4 + ad58: b751 j acdc <_vfiprintf_r+0x1c2> + ad5a: 079d addi a5,a5,7 + ad5c: 9be1 andi a5,a5,-8 + ad5e: 07a1 addi a5,a5,8 + ad60: b7d5 j ad44 <_vfiprintf_r+0x22a> + ad62: 0078 addi a4,sp,12 + ad64: 00000697 auipc a3,0x0 + ad68: d7468693 addi a3,a3,-652 # aad8 <__sfputs_r> + ad6c: 8626 mv a2,s1 + ad6e: 080c addi a1,sp,16 + ad70: 854e mv a0,s3 + ad72: 00000097 auipc ra,0x0 + ad76: 000000e7 jalr zero # 0 <_sinit> + ad7a: 57fd li a5,-1 + ad7c: 8a2a mv s4,a0 + ad7e: fcf514e3 bne a0,a5,ad46 <_vfiprintf_r+0x22c> + ad82: 24de lhu a5,12(s1) + ad84: 0407f793 andi a5,a5,64 + ad88: ec0792e3 bnez a5,ac4c <_vfiprintf_r+0x132> + ad8c: 5512 lw a0,36(sp) + ad8e: b5c1 j ac4e <_vfiprintf_r+0x134> + ad90: 0078 addi a4,sp,12 + ad92: 00000697 auipc a3,0x0 + ad96: d4668693 addi a3,a3,-698 # aad8 <__sfputs_r> + ad9a: 8626 mv a2,s1 + ad9c: 080c addi a1,sp,16 + ad9e: 854e mv a0,s3 + ada0: 2a01 jal aeb0 <_printf_i> + ada2: bfe1 j ad7a <_vfiprintf_r+0x260> + +0000ada4 <_printf_common>: + ada4: 7179 addi sp,sp,-48 + ada6: ca56 sw s5,20(sp) + ada8: 499c lw a5,16(a1) + adaa: 8aba mv s5,a4 + adac: 4598 lw a4,8(a1) + adae: d422 sw s0,40(sp) + adb0: d226 sw s1,36(sp) + adb2: ce4e sw s3,28(sp) + adb4: cc52 sw s4,24(sp) + adb6: d606 sw ra,44(sp) + adb8: d04a sw s2,32(sp) + adba: c85a sw s6,16(sp) + adbc: c65e sw s7,12(sp) + adbe: 89aa mv s3,a0 + adc0: 842e mv s0,a1 + adc2: 84b2 mv s1,a2 + adc4: 8a36 mv s4,a3 + adc6: 00e7d363 bge a5,a4,adcc <_printf_common+0x28> + adca: 87ba mv a5,a4 + adcc: c09c sw a5,0(s1) + adce: 04344703 lbu a4,67(s0) + add2: c319 beqz a4,add8 <_printf_common+0x34> + add4: 0785 addi a5,a5,1 + add6: c09c sw a5,0(s1) + add8: 401c lw a5,0(s0) + adda: 0207f793 andi a5,a5,32 + adde: c781 beqz a5,ade6 <_printf_common+0x42> + ade0: 409c lw a5,0(s1) + ade2: 0789 addi a5,a5,2 + ade4: c09c sw a5,0(s1) + ade6: 00042903 lw s2,0(s0) + adea: 00697913 andi s2,s2,6 + adee: 00091a63 bnez s2,ae02 <_printf_common+0x5e> + adf2: 01940b13 addi s6,s0,25 + adf6: 5bfd li s7,-1 + adf8: 445c lw a5,12(s0) + adfa: 4098 lw a4,0(s1) + adfc: 8f99 sub a5,a5,a4 + adfe: 04f94c63 blt s2,a5,ae56 <_printf_common+0xb2> + ae02: 401c lw a5,0(s0) + ae04: 04344683 lbu a3,67(s0) + ae08: 0207f793 andi a5,a5,32 + ae0c: 00d036b3 snez a3,a3 + ae10: eba5 bnez a5,ae80 <_printf_common+0xdc> + ae12: 04340613 addi a2,s0,67 + ae16: 85d2 mv a1,s4 + ae18: 854e mv a0,s3 + ae1a: 9a82 jalr s5 + ae1c: 57fd li a5,-1 + ae1e: 04f50363 beq a0,a5,ae64 <_printf_common+0xc0> + ae22: 401c lw a5,0(s0) + ae24: 4611 li a2,4 + ae26: 4098 lw a4,0(s1) + ae28: 8b99 andi a5,a5,6 + ae2a: 4454 lw a3,12(s0) + ae2c: 4481 li s1,0 + ae2e: 00c79763 bne a5,a2,ae3c <_printf_common+0x98> + ae32: 40e684b3 sub s1,a3,a4 + ae36: 0004d363 bgez s1,ae3c <_printf_common+0x98> + ae3a: 4481 li s1,0 + ae3c: 441c lw a5,8(s0) + ae3e: 4818 lw a4,16(s0) + ae40: 00f75463 bge a4,a5,ae48 <_printf_common+0xa4> + ae44: 8f99 sub a5,a5,a4 + ae46: 94be add s1,s1,a5 + ae48: 4901 li s2,0 + ae4a: 0469 addi s0,s0,26 + ae4c: 5b7d li s6,-1 + ae4e: 05249863 bne s1,s2,ae9e <_printf_common+0xfa> + ae52: 4501 li a0,0 + ae54: a809 j ae66 <_printf_common+0xc2> + ae56: 4685 li a3,1 + ae58: 865a mv a2,s6 + ae5a: 85d2 mv a1,s4 + ae5c: 854e mv a0,s3 + ae5e: 9a82 jalr s5 + ae60: 01751e63 bne a0,s7,ae7c <_printf_common+0xd8> + ae64: 557d li a0,-1 + ae66: 50b2 lw ra,44(sp) + ae68: 5422 lw s0,40(sp) + ae6a: 5492 lw s1,36(sp) + ae6c: 5902 lw s2,32(sp) + ae6e: 49f2 lw s3,28(sp) + ae70: 4a62 lw s4,24(sp) + ae72: 4ad2 lw s5,20(sp) + ae74: 4b42 lw s6,16(sp) + ae76: 4bb2 lw s7,12(sp) + ae78: 6145 addi sp,sp,48 + ae7a: 8082 ret + ae7c: 0905 addi s2,s2,1 + ae7e: bfad j adf8 <_printf_common+0x54> + ae80: 00d40733 add a4,s0,a3 + ae84: 03000613 li a2,48 + ae88: 04c701a3 sb a2,67(a4) + ae8c: 04544703 lbu a4,69(s0) + ae90: 00168793 addi a5,a3,1 + ae94: 97a2 add a5,a5,s0 + ae96: 0689 addi a3,a3,2 + ae98: 04e781a3 sb a4,67(a5) + ae9c: bf9d j ae12 <_printf_common+0x6e> + ae9e: 4685 li a3,1 + aea0: 8622 mv a2,s0 + aea2: 85d2 mv a1,s4 + aea4: 854e mv a0,s3 + aea6: 9a82 jalr s5 + aea8: fb650ee3 beq a0,s6,ae64 <_printf_common+0xc0> + aeac: 0905 addi s2,s2,1 + aeae: b745 j ae4e <_printf_common+0xaa> + +0000aeb0 <_printf_i>: + aeb0: 7179 addi sp,sp,-48 + aeb2: d422 sw s0,40(sp) + aeb4: d226 sw s1,36(sp) + aeb6: d04a sw s2,32(sp) + aeb8: ce4e sw s3,28(sp) + aeba: d606 sw ra,44(sp) + aebc: cc52 sw s4,24(sp) + aebe: ca56 sw s5,20(sp) + aec0: c85a sw s6,16(sp) + aec2: 89b6 mv s3,a3 + aec4: 2d94 lbu a3,24(a1) + aec6: 06900793 li a5,105 + aeca: 8932 mv s2,a2 + aecc: 84aa mv s1,a0 + aece: 842e mv s0,a1 + aed0: 04358613 addi a2,a1,67 + aed4: 02f68d63 beq a3,a5,af0e <_printf_i+0x5e> + aed8: 06d7e263 bltu a5,a3,af3c <_printf_i+0x8c> + aedc: 05800793 li a5,88 + aee0: 18f68663 beq a3,a5,b06c <_printf_i+0x1bc> + aee4: 00d7ed63 bltu a5,a3,aefe <_printf_i+0x4e> + aee8: 20068e63 beqz a3,b104 <_printf_i+0x254> + aeec: 04300793 li a5,67 + aef0: 0af68e63 beq a3,a5,afac <_printf_i+0xfc> + aef4: 04240a93 addi s5,s0,66 + aef8: 04d40123 sb a3,66(s0) + aefc: a0c9 j afbe <_printf_i+0x10e> + aefe: 06300793 li a5,99 + af02: 0af68563 beq a3,a5,afac <_printf_i+0xfc> + af06: 06400793 li a5,100 + af0a: fef695e3 bne a3,a5,aef4 <_printf_i+0x44> + af0e: 401c lw a5,0(s0) + af10: 4308 lw a0,0(a4) + af12: 0807f693 andi a3,a5,128 + af16: 00450593 addi a1,a0,4 + af1a: c6c5 beqz a3,afc2 <_printf_i+0x112> + af1c: 411c lw a5,0(a0) + af1e: c30c sw a1,0(a4) + af20: 0007d863 bgez a5,af30 <_printf_i+0x80> + af24: 02d00713 li a4,45 + af28: 40f007b3 neg a5,a5 + af2c: 04e401a3 sb a4,67(s0) + af30: 00003697 auipc a3,0x3 + af34: 30468693 addi a3,a3,772 # e234 <__sf_fake_stdout+0x34> + af38: 4729 li a4,10 + af3a: a865 j aff2 <_printf_i+0x142> + af3c: 07000793 li a5,112 + af40: 16f68263 beq a3,a5,b0a4 <_printf_i+0x1f4> + af44: 02d7e563 bltu a5,a3,af6e <_printf_i+0xbe> + af48: 06e00793 li a5,110 + af4c: 18f68963 beq a3,a5,b0de <_printf_i+0x22e> + af50: 06f00793 li a5,111 + af54: faf690e3 bne a3,a5,aef4 <_printf_i+0x44> + af58: 400c lw a1,0(s0) + af5a: 431c lw a5,0(a4) + af5c: 0805f813 andi a6,a1,128 + af60: 00478513 addi a0,a5,4 + af64: 06080763 beqz a6,afd2 <_printf_i+0x122> + af68: c308 sw a0,0(a4) + af6a: 439c lw a5,0(a5) + af6c: a885 j afdc <_printf_i+0x12c> + af6e: 07500793 li a5,117 + af72: fef683e3 beq a3,a5,af58 <_printf_i+0xa8> + af76: 07800793 li a5,120 + af7a: 12f68963 beq a3,a5,b0ac <_printf_i+0x1fc> + af7e: 07300793 li a5,115 + af82: f6f699e3 bne a3,a5,aef4 <_printf_i+0x44> + af86: 431c lw a5,0(a4) + af88: 41d0 lw a2,4(a1) + af8a: 4581 li a1,0 + af8c: 00478693 addi a3,a5,4 + af90: c314 sw a3,0(a4) + af92: 0007aa83 lw s5,0(a5) + af96: 8556 mv a0,s5 + af98: 2e75 jal b354 + af9a: c501 beqz a0,afa2 <_printf_i+0xf2> + af9c: 41550533 sub a0,a0,s5 + afa0: c048 sw a0,4(s0) + afa2: 405c lw a5,4(s0) + afa4: c81c sw a5,16(s0) + afa6: 040401a3 sb zero,67(s0) + afaa: a861 j b042 <_printf_i+0x192> + afac: 431c lw a5,0(a4) + afae: 04240a93 addi s5,s0,66 + afb2: 00478693 addi a3,a5,4 + afb6: 439c lw a5,0(a5) + afb8: c314 sw a3,0(a4) + afba: 04f40123 sb a5,66(s0) + afbe: 4785 li a5,1 + afc0: b7d5 j afa4 <_printf_i+0xf4> + afc2: 0407f693 andi a3,a5,64 + afc6: 411c lw a5,0(a0) + afc8: c30c sw a1,0(a4) + afca: dab9 beqz a3,af20 <_printf_i+0x70> + afcc: 07c2 slli a5,a5,0x10 + afce: 87c1 srai a5,a5,0x10 + afd0: bf81 j af20 <_printf_i+0x70> + afd2: 0405f593 andi a1,a1,64 + afd6: c308 sw a0,0(a4) + afd8: d9c9 beqz a1,af6a <_printf_i+0xba> + afda: 239e lhu a5,0(a5) + afdc: 06f00713 li a4,111 + afe0: 0ee68763 beq a3,a4,b0ce <_printf_i+0x21e> + afe4: 00003697 auipc a3,0x3 + afe8: 25068693 addi a3,a3,592 # e234 <__sf_fake_stdout+0x34> + afec: 4729 li a4,10 + afee: 040401a3 sb zero,67(s0) + aff2: 404c lw a1,4(s0) + aff4: c40c sw a1,8(s0) + aff6: 0005c563 bltz a1,b000 <_printf_i+0x150> + affa: 4008 lw a0,0(s0) + affc: 996d andi a0,a0,-5 + affe: c008 sw a0,0(s0) + b000: e399 bnez a5,b006 <_printf_i+0x156> + b002: 8ab2 mv s5,a2 + b004: cd89 beqz a1,b01e <_printf_i+0x16e> + b006: 8ab2 mv s5,a2 + b008: 02e7f5b3 remu a1,a5,a4 + b00c: 1afd addi s5,s5,-1 + b00e: 95b6 add a1,a1,a3 + b010: 218c lbu a1,0(a1) + b012: 00ba8023 sb a1,0(s5) + b016: 02e7d5b3 divu a1,a5,a4 + b01a: 0ce7f063 bgeu a5,a4,b0da <_printf_i+0x22a> + b01e: 47a1 li a5,8 + b020: 00f71e63 bne a4,a5,b03c <_printf_i+0x18c> + b024: 401c lw a5,0(s0) + b026: 8b85 andi a5,a5,1 + b028: cb91 beqz a5,b03c <_printf_i+0x18c> + b02a: 4058 lw a4,4(s0) + b02c: 481c lw a5,16(s0) + b02e: 00e7c763 blt a5,a4,b03c <_printf_i+0x18c> + b032: 03000793 li a5,48 + b036: fefa8fa3 sb a5,-1(s5) + b03a: 1afd addi s5,s5,-1 + b03c: 41560633 sub a2,a2,s5 + b040: c810 sw a2,16(s0) + b042: 874e mv a4,s3 + b044: 86ca mv a3,s2 + b046: 0070 addi a2,sp,12 + b048: 85a2 mv a1,s0 + b04a: 8526 mv a0,s1 + b04c: d59ff0ef jal ra,ada4 <_printf_common> + b050: 5a7d li s4,-1 + b052: 0b451d63 bne a0,s4,b10c <_printf_i+0x25c> + b056: 557d li a0,-1 + b058: 50b2 lw ra,44(sp) + b05a: 5422 lw s0,40(sp) + b05c: 5492 lw s1,36(sp) + b05e: 5902 lw s2,32(sp) + b060: 49f2 lw s3,28(sp) + b062: 4a62 lw s4,24(sp) + b064: 4ad2 lw s5,20(sp) + b066: 4b42 lw s6,16(sp) + b068: 6145 addi sp,sp,48 + b06a: 8082 ret + b06c: 04d582a3 sb a3,69(a1) + b070: 00003697 auipc a3,0x3 + b074: 1c468693 addi a3,a3,452 # e234 <__sf_fake_stdout+0x34> + b078: 400c lw a1,0(s0) + b07a: 4308 lw a0,0(a4) + b07c: 0805f813 andi a6,a1,128 + b080: 411c lw a5,0(a0) + b082: 0511 addi a0,a0,4 + b084: 02080d63 beqz a6,b0be <_printf_i+0x20e> + b088: c308 sw a0,0(a4) + b08a: 0015f713 andi a4,a1,1 + b08e: c701 beqz a4,b096 <_printf_i+0x1e6> + b090: 0205e593 ori a1,a1,32 + b094: c00c sw a1,0(s0) + b096: 4741 li a4,16 + b098: fbb9 bnez a5,afee <_printf_i+0x13e> + b09a: 400c lw a1,0(s0) + b09c: fdf5f593 andi a1,a1,-33 + b0a0: c00c sw a1,0(s0) + b0a2: b7b1 j afee <_printf_i+0x13e> + b0a4: 419c lw a5,0(a1) + b0a6: 0207e793 ori a5,a5,32 + b0aa: c19c sw a5,0(a1) + b0ac: 07800793 li a5,120 + b0b0: 04f402a3 sb a5,69(s0) + b0b4: 00003697 auipc a3,0x3 + b0b8: 19468693 addi a3,a3,404 # e248 <__sf_fake_stdout+0x48> + b0bc: bf75 j b078 <_printf_i+0x1c8> + b0be: 0405f813 andi a6,a1,64 + b0c2: c308 sw a0,0(a4) + b0c4: fc0803e3 beqz a6,b08a <_printf_i+0x1da> + b0c8: 07c2 slli a5,a5,0x10 + b0ca: 83c1 srli a5,a5,0x10 + b0cc: bf7d j b08a <_printf_i+0x1da> + b0ce: 00003697 auipc a3,0x3 + b0d2: 16668693 addi a3,a3,358 # e234 <__sf_fake_stdout+0x34> + b0d6: 4721 li a4,8 + b0d8: bf19 j afee <_printf_i+0x13e> + b0da: 87ae mv a5,a1 + b0dc: b735 j b008 <_printf_i+0x158> + b0de: 4194 lw a3,0(a1) + b0e0: 431c lw a5,0(a4) + b0e2: 49cc lw a1,20(a1) + b0e4: 0806f813 andi a6,a3,128 + b0e8: 00478513 addi a0,a5,4 + b0ec: 00080663 beqz a6,b0f8 <_printf_i+0x248> + b0f0: c308 sw a0,0(a4) + b0f2: 439c lw a5,0(a5) + b0f4: c38c sw a1,0(a5) + b0f6: a039 j b104 <_printf_i+0x254> + b0f8: c308 sw a0,0(a4) + b0fa: 0406f693 andi a3,a3,64 + b0fe: 439c lw a5,0(a5) + b100: daf5 beqz a3,b0f4 <_printf_i+0x244> + b102: a38e sh a1,0(a5) + b104: 00042823 sw zero,16(s0) + b108: 8ab2 mv s5,a2 + b10a: bf25 j b042 <_printf_i+0x192> + b10c: 4814 lw a3,16(s0) + b10e: 8656 mv a2,s5 + b110: 85ca mv a1,s2 + b112: 8526 mv a0,s1 + b114: 9982 jalr s3 + b116: f54500e3 beq a0,s4,b056 <_printf_i+0x1a6> + b11a: 401c lw a5,0(s0) + b11c: 8b89 andi a5,a5,2 + b11e: e78d bnez a5,b148 <_printf_i+0x298> + b120: 47b2 lw a5,12(sp) + b122: 4448 lw a0,12(s0) + b124: f2f55ae3 bge a0,a5,b058 <_printf_i+0x1a8> + b128: 853e mv a0,a5 + b12a: b73d j b058 <_printf_i+0x1a8> + b12c: 4685 li a3,1 + b12e: 8656 mv a2,s5 + b130: 85ca mv a1,s2 + b132: 8526 mv a0,s1 + b134: 9982 jalr s3 + b136: f36500e3 beq a0,s6,b056 <_printf_i+0x1a6> + b13a: 0a05 addi s4,s4,1 + b13c: 445c lw a5,12(s0) + b13e: 4732 lw a4,12(sp) + b140: 8f99 sub a5,a5,a4 + b142: fefa45e3 blt s4,a5,b12c <_printf_i+0x27c> + b146: bfe9 j b120 <_printf_i+0x270> + b148: 4a01 li s4,0 + b14a: 01940a93 addi s5,s0,25 + b14e: 5b7d li s6,-1 + b150: b7f5 j b13c <_printf_i+0x28c> + +0000b152 <_putc_r>: + b152: 1101 addi sp,sp,-32 + b154: cc22 sw s0,24(sp) + b156: ce06 sw ra,28(sp) + b158: 842a mv s0,a0 + b15a: c909 beqz a0,b16c <_putc_r+0x1a> + b15c: 4d1c lw a5,24(a0) + b15e: e799 bnez a5,b16c <_putc_r+0x1a> + b160: c632 sw a2,12(sp) + b162: c42e sw a1,8(sp) + b164: b98ff0ef jal ra,a4fc <__sinit> + b168: 4632 lw a2,12(sp) + b16a: 45a2 lw a1,8(sp) + b16c: 00003797 auipc a5,0x3 + b170: 07478793 addi a5,a5,116 # e1e0 <__sf_fake_stdin> + b174: 02f61663 bne a2,a5,b1a0 <_putc_r+0x4e> + b178: 4050 lw a2,4(s0) + b17a: 461c lw a5,8(a2) + b17c: 17fd addi a5,a5,-1 + b17e: c61c sw a5,8(a2) + b180: 0407d063 bgez a5,b1c0 <_putc_r+0x6e> + b184: 4e18 lw a4,24(a2) + b186: 00e7c763 blt a5,a4,b194 <_putc_r+0x42> + b18a: 0ff5f793 andi a5,a1,255 + b18e: 4729 li a4,10 + b190: 02e79863 bne a5,a4,b1c0 <_putc_r+0x6e> + b194: 8522 mv a0,s0 + b196: 4462 lw s0,24(sp) + b198: 40f2 lw ra,28(sp) + b19a: 6105 addi sp,sp,32 + b19c: f39fe06f j a0d4 <__swbuf_r> + b1a0: 00003797 auipc a5,0x3 + b1a4: 06078793 addi a5,a5,96 # e200 <__sf_fake_stdout> + b1a8: 00f61463 bne a2,a5,b1b0 <_putc_r+0x5e> + b1ac: 4410 lw a2,8(s0) + b1ae: b7f1 j b17a <_putc_r+0x28> + b1b0: 00003797 auipc a5,0x3 + b1b4: 01078793 addi a5,a5,16 # e1c0 <__sf_fake_stderr> + b1b8: fcf611e3 bne a2,a5,b17a <_putc_r+0x28> + b1bc: 4450 lw a2,12(s0) + b1be: bf75 j b17a <_putc_r+0x28> + b1c0: 421c lw a5,0(a2) + b1c2: 0ff5f513 andi a0,a1,255 + b1c6: 00178713 addi a4,a5,1 + b1ca: c218 sw a4,0(a2) + b1cc: a38c sb a1,0(a5) + b1ce: 40f2 lw ra,28(sp) + b1d0: 4462 lw s0,24(sp) + b1d2: 6105 addi sp,sp,32 + b1d4: 8082 ret + +0000b1d6 <__sread>: + b1d6: 1141 addi sp,sp,-16 + b1d8: c422 sw s0,8(sp) + b1da: 842e mv s0,a1 + b1dc: 00e59583 lh a1,14(a1) + b1e0: c606 sw ra,12(sp) + b1e2: 22cd jal b3c4 <_read_r> + b1e4: 00054963 bltz a0,b1f6 <__sread+0x20> + b1e8: 487c lw a5,84(s0) + b1ea: 97aa add a5,a5,a0 + b1ec: c87c sw a5,84(s0) + b1ee: 40b2 lw ra,12(sp) + b1f0: 4422 lw s0,8(sp) + b1f2: 0141 addi sp,sp,16 + b1f4: 8082 ret + b1f6: 245e lhu a5,12(s0) + b1f8: 777d lui a4,0xfffff + b1fa: 177d addi a4,a4,-1 + b1fc: 8ff9 and a5,a5,a4 + b1fe: a45e sh a5,12(s0) + b200: b7fd j b1ee <__sread+0x18> + +0000b202 <__swrite>: + b202: 25de lhu a5,12(a1) + b204: 1101 addi sp,sp,-32 + b206: cc22 sw s0,24(sp) + b208: ca26 sw s1,20(sp) + b20a: c84a sw s2,16(sp) + b20c: c64e sw s3,12(sp) + b20e: ce06 sw ra,28(sp) + b210: 1007f793 andi a5,a5,256 + b214: 84aa mv s1,a0 + b216: 842e mv s0,a1 + b218: 8932 mv s2,a2 + b21a: 89b6 mv s3,a3 + b21c: c791 beqz a5,b228 <__swrite+0x26> + b21e: 00e59583 lh a1,14(a1) + b222: 4689 li a3,2 + b224: 4601 li a2,0 + b226: 2209 jal b328 <_lseek_r> + b228: 245e lhu a5,12(s0) + b22a: 777d lui a4,0xfffff + b22c: 177d addi a4,a4,-1 + b22e: 8ff9 and a5,a5,a4 + b230: a45e sh a5,12(s0) + b232: 00e41583 lh a1,14(s0) + b236: 4462 lw s0,24(sp) + b238: 40f2 lw ra,28(sp) + b23a: 86ce mv a3,s3 + b23c: 864a mv a2,s2 + b23e: 49b2 lw s3,12(sp) + b240: 4942 lw s2,16(sp) + b242: 8526 mv a0,s1 + b244: 44d2 lw s1,20(sp) + b246: 6105 addi sp,sp,32 + b248: a825 j b280 <_write_r> + +0000b24a <__sseek>: + b24a: 1141 addi sp,sp,-16 + b24c: c422 sw s0,8(sp) + b24e: 842e mv s0,a1 + b250: 00e59583 lh a1,14(a1) + b254: c606 sw ra,12(sp) + b256: 28c9 jal b328 <_lseek_r> + b258: 57fd li a5,-1 + b25a: 245a lhu a4,12(s0) + b25c: 00f51a63 bne a0,a5,b270 <__sseek+0x26> + b260: 77fd lui a5,0xfffff + b262: 17fd addi a5,a5,-1 + b264: 8ff9 and a5,a5,a4 + b266: a45e sh a5,12(s0) + b268: 40b2 lw ra,12(sp) + b26a: 4422 lw s0,8(sp) + b26c: 0141 addi sp,sp,16 + b26e: 8082 ret + b270: 6785 lui a5,0x1 + b272: 8fd9 or a5,a5,a4 + b274: a45e sh a5,12(s0) + b276: c868 sw a0,84(s0) + b278: bfc5 j b268 <__sseek+0x1e> + +0000b27a <__sclose>: + b27a: 00e59583 lh a1,14(a1) + b27e: a805 j b2ae <_close_r> + +0000b280 <_write_r>: + b280: 1141 addi sp,sp,-16 + b282: c422 sw s0,8(sp) + b284: 842a mv s0,a0 + b286: 852e mv a0,a1 + b288: 85b2 mv a1,a2 + b28a: 8636 mv a2,a3 + b28c: 7801a623 sw zero,1932(gp) # 2000117c + b290: c606 sw ra,12(sp) + b292: a0afe0ef jal ra,949c <_write> + b296: 57fd li a5,-1 + b298: 00f51763 bne a0,a5,b2a6 <_write_r+0x26> + b29c: 78c18793 addi a5,gp,1932 # 2000117c + b2a0: 439c lw a5,0(a5) + b2a2: c391 beqz a5,b2a6 <_write_r+0x26> + b2a4: c01c sw a5,0(s0) + b2a6: 40b2 lw ra,12(sp) + b2a8: 4422 lw s0,8(sp) + b2aa: 0141 addi sp,sp,16 + b2ac: 8082 ret + +0000b2ae <_close_r>: + b2ae: 1141 addi sp,sp,-16 + b2b0: c422 sw s0,8(sp) + b2b2: 842a mv s0,a0 + b2b4: 852e mv a0,a1 + b2b6: 7801a623 sw zero,1932(gp) # 2000117c + b2ba: c606 sw ra,12(sp) + b2bc: 22a1 jal b404 <_close> + b2be: 57fd li a5,-1 + b2c0: 00f51763 bne a0,a5,b2ce <_close_r+0x20> + b2c4: 78c18793 addi a5,gp,1932 # 2000117c + b2c8: 439c lw a5,0(a5) + b2ca: c391 beqz a5,b2ce <_close_r+0x20> + b2cc: c01c sw a5,0(s0) + b2ce: 40b2 lw ra,12(sp) + b2d0: 4422 lw s0,8(sp) + b2d2: 0141 addi sp,sp,16 + b2d4: 8082 ret + +0000b2d6 <_fstat_r>: + b2d6: 1141 addi sp,sp,-16 + b2d8: c422 sw s0,8(sp) + b2da: 842a mv s0,a0 + b2dc: 852e mv a0,a1 + b2de: 85b2 mv a1,a2 + b2e0: 7801a623 sw zero,1932(gp) # 2000117c + b2e4: c606 sw ra,12(sp) + b2e6: 222d jal b410 <_fstat> + b2e8: 57fd li a5,-1 + b2ea: 00f51763 bne a0,a5,b2f8 <_fstat_r+0x22> + b2ee: 78c18793 addi a5,gp,1932 # 2000117c + b2f2: 439c lw a5,0(a5) + b2f4: c391 beqz a5,b2f8 <_fstat_r+0x22> + b2f6: c01c sw a5,0(s0) + b2f8: 40b2 lw ra,12(sp) + b2fa: 4422 lw s0,8(sp) + b2fc: 0141 addi sp,sp,16 + b2fe: 8082 ret + +0000b300 <_isatty_r>: + b300: 1141 addi sp,sp,-16 + b302: c422 sw s0,8(sp) + b304: 842a mv s0,a0 + b306: 852e mv a0,a1 + b308: 7801a623 sw zero,1932(gp) # 2000117c + b30c: c606 sw ra,12(sp) + b30e: 2a29 jal b428 <_isatty> + b310: 57fd li a5,-1 + b312: 00f51763 bne a0,a5,b320 <_isatty_r+0x20> + b316: 78c18793 addi a5,gp,1932 # 2000117c + b31a: 439c lw a5,0(a5) + b31c: c391 beqz a5,b320 <_isatty_r+0x20> + b31e: c01c sw a5,0(s0) + b320: 40b2 lw ra,12(sp) + b322: 4422 lw s0,8(sp) + b324: 0141 addi sp,sp,16 + b326: 8082 ret + +0000b328 <_lseek_r>: + b328: 1141 addi sp,sp,-16 + b32a: c422 sw s0,8(sp) + b32c: 842a mv s0,a0 + b32e: 852e mv a0,a1 + b330: 85b2 mv a1,a2 + b332: 8636 mv a2,a3 + b334: 7801a623 sw zero,1932(gp) # 2000117c + b338: c606 sw ra,12(sp) + b33a: 2219 jal b440 <_lseek> + b33c: 57fd li a5,-1 + b33e: 00f51763 bne a0,a5,b34c <_lseek_r+0x24> + b342: 78c18793 addi a5,gp,1932 # 2000117c + b346: 439c lw a5,0(a5) + b348: c391 beqz a5,b34c <_lseek_r+0x24> + b34a: c01c sw a5,0(s0) + b34c: 40b2 lw ra,12(sp) + b34e: 4422 lw s0,8(sp) + b350: 0141 addi sp,sp,16 + b352: 8082 ret + +0000b354 : + b354: 0ff5f593 andi a1,a1,255 + b358: 962a add a2,a2,a0 + b35a: 00c51463 bne a0,a2,b362 + b35e: 4501 li a0,0 + b360: 8082 ret + b362: 211c lbu a5,0(a0) + b364: feb78ee3 beq a5,a1,b360 + b368: 0505 addi a0,a0,1 + b36a: bfc5 j b35a + +0000b36c <_realloc_r>: + b36c: e581 bnez a1,b374 <_realloc_r+0x8> + b36e: 85b2 mv a1,a2 + b370: f82fe06f j 9af2 <_malloc_r> + b374: 1101 addi sp,sp,-32 + b376: cc22 sw s0,24(sp) + b378: ce06 sw ra,28(sp) + b37a: ca26 sw s1,20(sp) + b37c: c84a sw s2,16(sp) + b37e: c64e sw s3,12(sp) + b380: 8432 mv s0,a2 + b382: ee01 bnez a2,b39a <_realloc_r+0x2e> + b384: ec6fe0ef jal ra,9a4a <_free_r> + b388: 4901 li s2,0 + b38a: 40f2 lw ra,28(sp) + b38c: 4462 lw s0,24(sp) + b38e: 854a mv a0,s2 + b390: 44d2 lw s1,20(sp) + b392: 4942 lw s2,16(sp) + b394: 49b2 lw s3,12(sp) + b396: 6105 addi sp,sp,32 + b398: 8082 ret + b39a: 84ae mv s1,a1 + b39c: 89aa mv s3,a0 + b39e: 2889 jal b3f0 <_malloc_usable_size_r> + b3a0: 8926 mv s2,s1 + b3a2: fe8574e3 bgeu a0,s0,b38a <_realloc_r+0x1e> + b3a6: 85a2 mv a1,s0 + b3a8: 854e mv a0,s3 + b3aa: f48fe0ef jal ra,9af2 <_malloc_r> + b3ae: 892a mv s2,a0 + b3b0: dd69 beqz a0,b38a <_realloc_r+0x1e> + b3b2: 85a6 mv a1,s1 + b3b4: 8622 mv a2,s0 + b3b6: d9cfe0ef jal ra,9952 + b3ba: 85a6 mv a1,s1 + b3bc: 854e mv a0,s3 + b3be: e8cfe0ef jal ra,9a4a <_free_r> + b3c2: b7e1 j b38a <_realloc_r+0x1e> + +0000b3c4 <_read_r>: + b3c4: 1141 addi sp,sp,-16 + b3c6: c422 sw s0,8(sp) + b3c8: 842a mv s0,a0 + b3ca: 852e mv a0,a1 + b3cc: 85b2 mv a1,a2 + b3ce: 8636 mv a2,a3 + b3d0: 7801a623 sw zero,1932(gp) # 2000117c + b3d4: c606 sw ra,12(sp) + b3d6: 289d jal b44c <_read> + b3d8: 57fd li a5,-1 + b3da: 00f51763 bne a0,a5,b3e8 <_read_r+0x24> + b3de: 78c18793 addi a5,gp,1932 # 2000117c + b3e2: 439c lw a5,0(a5) + b3e4: c391 beqz a5,b3e8 <_read_r+0x24> + b3e6: c01c sw a5,0(s0) + b3e8: 40b2 lw ra,12(sp) + b3ea: 4422 lw s0,8(sp) + b3ec: 0141 addi sp,sp,16 + b3ee: 8082 ret + +0000b3f0 <_malloc_usable_size_r>: + b3f0: ffc5a783 lw a5,-4(a1) + b3f4: ffc78513 addi a0,a5,-4 # ffc + b3f8: 0007d563 bgez a5,b402 <_malloc_usable_size_r+0x12> + b3fc: 95aa add a1,a1,a0 + b3fe: 419c lw a5,0(a1) + b400: 953e add a0,a0,a5 + b402: 8082 ret + +0000b404 <_close>: + b404: 05800793 li a5,88 + b408: 78f1a623 sw a5,1932(gp) # 2000117c + b40c: 557d li a0,-1 + b40e: 8082 ret + +0000b410 <_fstat>: + b410: 05800793 li a5,88 + b414: 78f1a623 sw a5,1932(gp) # 2000117c + b418: 557d li a0,-1 + b41a: 8082 ret + +0000b41c <_getpid>: + b41c: 05800793 li a5,88 + b420: 78f1a623 sw a5,1932(gp) # 2000117c + b424: 557d li a0,-1 + b426: 8082 ret + +0000b428 <_isatty>: + b428: 05800793 li a5,88 + b42c: 78f1a623 sw a5,1932(gp) # 2000117c + b430: 4501 li a0,0 + b432: 8082 ret + +0000b434 <_kill>: + b434: 05800793 li a5,88 + b438: 78f1a623 sw a5,1932(gp) # 2000117c + b43c: 557d li a0,-1 + b43e: 8082 ret + +0000b440 <_lseek>: + b440: 05800793 li a5,88 + b444: 78f1a623 sw a5,1932(gp) # 2000117c + b448: 557d li a0,-1 + b44a: 8082 ret + +0000b44c <_read>: + b44c: 05800793 li a5,88 + b450: 78f1a623 sw a5,1932(gp) # 2000117c + b454: 557d li a0,-1 + b456: 8082 ret + +0000b458 <_exit>: + b458: a001 j b458 <_exit> + b45a: 0000 unimp + b45c: 7325 lui t1,0xfffe9 + b45e: 2820 lbu s0,18(s0) + b460: 656c flw fa1,76(a0) + b462: 3d6e lhu a1,62(a0) + b464: 7525 lui a0,0xfffe9 + b466: 3a29 jal ad80 <_vfiprintf_r+0x266> + b468: 000a c.slli zero,0x2 + b46a: 0000 unimp + b46c: 3025 jal ac94 <_vfiprintf_r+0x17a> + b46e: 7534 flw fa3,104(a0) + b470: 2020 lbu s0,2(s0) + b472: 0000 unimp + b474: 3025 jal ac9c <_vfiprintf_r+0x182> + b476: 5832 lw a6,44(sp) + b478: 0020 addi s0,sp,8 + b47a: 0000 unimp + b47c: 2020 lbu s0,2(s0) + b47e: 0020 addi s0,sp,8 + b480: 6325 lui t1,0x9 + b482: 0000 unimp + b484: 3025 jal acac <_vfiprintf_r+0x192> + b486: 7832 flw fa6,44(sp) + b488: 0000 unimp + b48a: 0000 unimp + b48c: 6441 lui s0,0x10 + b48e: 6576 flw fa0,92(sp) + b490: 7472 flw fs0,60(sp) + b492: 0000 unimp + b494: 00000057 0x57 + b498: 5d73255b 0x5d73255b + b49c: 2520 lbu s0,10(a0) + b49e: 41203a73 csrrc s4,0x412,zero + b4a2: 7664 flw fs1,108(a2) + b4a4: 7265 lui tp,0xffff9 + b4a6: 6974 flw fa3,84(a0) + b4a8: 656d6573 csrrsi a0,0x656,26 + b4ac: 746e flw fs0,248(sp) + b4ae: 6620 flw fs0,72(a2) + b4b0: 6172 flw ft2,28(sp) + b4b2: 656d lui a0,0x1b + b4b4: 7420 flw fs0,104(s0) + b4b6: 73206f6f jal t5,11be8 <_data_lma+0x398c> + b4ba: 6f68 flw fa0,92(a4) + b4bc: 7472 flw fs0,60(sp) + b4be: 2820 lbu s0,18(s0) + b4c0: 6425 lui s0,0x9 + b4c2: 3c20 lbu s0,27(s0) + b4c4: 3120 lbu s0,3(a0) + b4c6: 3130 lbu a2,3(a0) + b4c8: 0d29 addi s10,s10,10 + b4ca: 000a c.slli zero,0x2 + b4cc: 5d73255b 0x5d73255b + b4d0: 2520 lbu s0,10(a0) + b4d2: 49203a73 csrrc s4,0x492,zero + b4d6: 636e flw ft6,216(sp) + b4d8: 6572726f jal tp,3332e <_data_lma+0x250d2> + b4dc: 73207463 bgeu zero,s2,bc04 <_exit+0x7ac> + b4e0: 6769 lui a4,0x1a + b4e2: 616e flw ft2,216(sp) + b4e4: 7574 flw fa3,108(a0) + b4e6: 6572 flw fa0,28(sp) + b4e8: 0a0d addi s4,s4,3 + b4ea: 0000 unimp + b4ec: 0049 c.nop 18 + b4ee: 0000 unimp + b4f0: 5d73255b 0x5d73255b + b4f4: 2520 lbu s0,10(a0) + b4f6: 41203a73 csrrc s4,0x412,zero + b4fa: 7664 flw fs1,108(a2) + b4fc: 7265 lui tp,0xffff9 + b4fe: 6974 flw fa3,84(a0) + b500: 656d6573 csrrsi a0,0x656,26 + b504: 746e flw fs0,248(sp) + b506: 7320 flw fs0,96(a4) + b508: 6769 lui a4,0x1a + b50a: 616e flw ft2,216(sp) + b50c: 7574 flw fa3,108(a0) + b50e: 6572 flw fa0,28(sp) + b510: 6f20 flw fs0,88(a4) + b512: 0a0d2e6b 0xa0d2e6b + b516: 0000 unimp + b518: 5d73255b 0x5d73255b + b51c: 2520 lbu s0,10(a0) + b51e: 41203a73 csrrc s4,0x412,zero + b522: 7664 flw fs1,108(a2) + b524: 7265 lui tp,0xffff9 + b526: 6974 flw fa3,84(a0) + b528: 656d6573 csrrsi a0,0x656,26 + b52c: 746e flw fs0,248(sp) + b52e: 6620 flw fs0,72(a2) + b530: 6172 flw ft2,28(sp) + b532: 656d lui a0,0x1b + b534: 7720 flw fs0,104(a4) + b536: 7469 lui s0,0xffffa + b538: 2068 lbu a0,6(s0) + b53a: 6164 flw fs1,68(a0) + b53c: 6174 flw fa3,68(a0) + b53e: 7420 flw fs0,104(s0) + b540: 73206f6f jal t5,11c72 <_data_lma+0x3a16> + b544: 6f68 flw fa0,92(a4) + b546: 7472 flw fs0,60(sp) + b548: 2820 lbu s0,18(s0) + b54a: 6425 lui s0,0x9 + b54c: 3c20 lbu s0,27(s0) + b54e: 2520 lbu s0,10(a0) + b550: 2964 lbu s1,22(a0) + b552: 0a0d addi s4,s4,3 + b554: 0000 unimp + b556: 0000 unimp + b558: 616e flw ft2,216(sp) + b55a: 656d lui a0,0x1b + b55c: 656c flw fa1,76(a0) + b55e: 6e207373 csrrci t1,0x6e2,0 + b562: 0065646f jal s0,61568 <_data_lma+0x5330c> + b566: 0000 unimp + b568: 6572 flw fa0,28(sp) + b56a: 6570 flw fa2,76(a0) + b56c: 7461 lui s0,0xffff8 + b56e: 7265 lui tp,0xffff9 + b570: 0000 unimp + b572: 0000 unimp + b574: 736e6573 csrrsi a0,0x736,28 + b578: 0000726f jal tp,12578 <_data_lma+0x431c> + b57c: 6f72 flw ft10,28(sp) + b57e: 73206d6f jal s10,11cb0 <_data_lma+0x3a54> + b582: 7265 lui tp,0xffff9 + b584: 6576 flw fa0,92(sp) + b586: 0072 c.slli zero,0x1c + b588: 74616863 bltu sp,t1,bcd8 <_exit+0x880> + b58c: 6e20 flw fs0,88(a2) + b58e: 0065646f jal s0,61594 <_data_lma+0x53338> + b592: 0000 unimp + b594: 776f6e6b 0x776f6e6b + b598: 006e c.slli zero,0x1b + b59a: 0000 unimp + b59c: 6e75 lui t3,0x1d + b59e: 776f6e6b 0x776f6e6b + b5a2: 006e c.slli zero,0x1b + b5a4: 7325 lui t1,0xfffe9 + b5a6: 6f20 flw fs0,88(a4) + b5a8: 206e lhu a1,6(s0) + b5aa: 6c25 lui s8,0x9 + b5ac: 2064 lbu s1,6(s0) + b5ae: 68746977 0x68746977 + b5b2: 7420 flw fs0,104(s0) + b5b4: 7079 c.lui zero,0xffffe + b5b6: 2065 jal b65e <_exit+0x206> + b5b8: 7325 lui t1,0xfffe9 + b5ba: 6f20 flw fs0,88(a4) + b5bc: 206e lhu a1,6(s0) + b5be: 7325 lui t1,0xfffe9 + b5c0: 6c20 flw fs0,88(s0) + b5c2: 7461636f jal t1,21d08 <_data_lma+0x13aac> + b5c6: 6f69 lui t5,0x1a + b5c8: 206e lhu a1,6(s0) + b5ca: 6c25 lui s8,0x9 + b5cc: 2064 lbu s1,6(s0) + b5ce: 6c25 lui s8,0x9 + b5d0: 0a64 addi s1,sp,284 + b5d2: 0000 unimp + b5d4: 7550 flw fa2,44(a0) + b5d6: 6c62 flw fs8,24(sp) + b5d8: 6369 lui t1,0x1a + b5da: 6b20 flw fs0,80(a4) + b5dc: 7965 lui s2,0xffff9 + b5de: 0000 unimp + b5e0: 6e676953 0x6e676953 + b5e4: 7461 lui s0,0xffff8 + b5e6: 7275 lui tp,0xffffd + b5e8: 0065 c.nop 25 + b5ea: 0000 unimp + b5ec: 7041 c.lui zero,0xffff0 + b5ee: 6470 flw fa2,76(s0) + b5f0: 7461 lui s0,0xffff8 + b5f2: 0061 c.nop 24 + b5f4: 6954 flw fa3,20(a0) + b5f6: 656d lui a0,0x1b + b5f8: 6d617473 csrrci s0,0x6d6,2 + b5fc: 2070 lbu a2,6(s0) + b5fe: 7369 lui t1,0xffffa + b600: 2520 lbu s0,10(a0) + b602: 756c flw fa1,108(a0) + b604: 000a c.slli zero,0x2 + b606: 0000 unimp + b608: 6f4e flw ft10,208(sp) + b60a: 6564 flw fs1,76(a0) + b60c: 614e flw ft2,208(sp) + b60e: 656d lui a0,0x1b + b610: 2520 lbu s0,10(a0) + b612: 00000a73 0xa73 + b616: 0000 unimp + b618: 6e41 lui t3,0x10 + b61a: 6d796e6f jal t3,a24f0 <_data_lma+0x94294> + b61e: 2073756f jal a0,43024 <_data_lma+0x34dc8> + b622: 6f6e flw ft10,216(sp) + b624: 6564 flw fs1,76(a0) + b626: 0000 unimp + b628: 6e41 lui t3,0x10 + b62a: 6d796e6f jal t3,a2500 <_data_lma+0x942a4> + b62e: 0073756f jal a0,42e34 <_data_lma+0x34bd8> + b632: 0000 unimp + b634: 5d73255b 0x5d73255b + b638: 2520 lbu s0,10(a0) + b63a: 4e203a73 csrrc s4,0x4e2,zero + b63e: 7765 lui a4,0xffff9 + b640: 6120 flw fs0,64(a0) + b642: 6f6e flw ft10,216(sp) + b644: 796e flw fs2,248(sp) + b646: 6f6d lui t5,0x1b + b648: 7375 lui t1,0xffffd + b64a: 6e20 flw fs0,88(a2) + b64c: 2065646f jal s0,61852 <_data_lma+0x535f6> + b650: 61657263 bgeu a0,s6,bc54 <_exit+0x7fc> + b654: 6574 flw fa3,76(a0) + b656: 3a64 lbu s1,23(a2) + b658: 2520 lbu s0,10(a0) + b65a: 000a0d73 0xa0d73 + b65e: 0000 unimp + b660: 0044 addi s1,sp,4 + b662: 0000 unimp + b664: 5d73255b 0x5d73255b + b668: 2520 lbu s0,10(a0) + b66a: 45203a73 csrrc s4,0x452,zero + b66e: 6978 flw fa4,84(a0) + b670: 6e697473 csrrci s0,0x6e6,18 + b674: 6f6e2067 0x6f6e2067 + b678: 6564 flw fs1,76(a0) + b67a: 6620 flw fs0,72(a2) + b67c: 646e756f jal a0,f2cc2 <_data_lma+0xe4a66> + b680: 6620 flw fs0,72(a2) + b682: 7020726f jal tp,12d84 <_data_lma+0x4b28> + b686: 6275 lui tp,0x1d + b688: 5b79654b fnmsub.d fa0,fs2,fs7,fa1,unknown + b68c: 5d30 lw a2,120(a0) + b68e: 303d jal aebc <_printf_i+0xc> + b690: 2578 lbu a4,14(a0) + b692: 3230 lbu a2,3(a2) + b694: 0d58 addi a4,sp,660 + b696: 000a c.slli zero,0x2 + b698: 6e41 lui t3,0x10 + b69a: 65526e6f jal t3,324ee <_data_lma+0x24292> + b69e: 2071 jal b72a <_exit+0x2d2> + b6a0: 6170 flw fa2,68(a0) + b6a2: 6c79 lui s8,0x1e + b6a4: 0064616f jal sp,516aa <_data_lma+0x4344e> + b6a8: 5d73255b 0x5d73255b + b6ac: 2520 lbu s0,10(a0) + b6ae: 50203a73 csrrc s4,0x502,zero + b6b2: 7361 lui t1,0xffff8 + b6b4: 726f7773 csrrci a4,0x726,30 + b6b8: 2064 lbu s1,6(s0) + b6ba: 656c flw fa1,76(a0) + b6bc: 206e lhu a1,6(s0) + b6be: 7369 lui t1,0xffffa + b6c0: 2520 lbu s0,10(a0) + b6c2: 2e64 lbu s1,30(a2) + b6c4: 0a0d addi s4,s4,3 + b6c6: 0000 unimp + b6c8: 5d73255b 0x5d73255b + b6cc: 2520 lbu s0,10(a0) + b6ce: 50203a73 csrrc s4,0x502,zero + b6d2: 7361 lui t1,0xffff8 + b6d4: 726f7773 csrrci a4,0x726,30 + b6d8: 2064 lbu s1,6(s0) + b6da: 72726f63 bltu tp,t2,be18 <_exit+0x9c0> + b6de: 6365 lui t1,0x19 + b6e0: 2c74 lbu a3,30(s0) + b6e2: 6e20 flw fs0,88(a2) + b6e4: 2065646f jal s0,618ea <_data_lma+0x5368e> + b6e8: 7325 lui t1,0xfffe9 + b6ea: 6120 flw fs0,64(a0) + b6ec: 7475 lui s0,0xffffd + b6ee: 6568 flw fa0,76(a0) + b6f0: 746e flw fs0,248(sp) + b6f2: 6369 lui t1,0x1a + b6f4: 7461 lui s0,0xffff8 + b6f6: 6465 lui s0,0x19 + b6f8: 0d2e slli s10,s10,0xb + b6fa: 000a c.slli zero,0x2 + b6fc: 5d73255b 0x5d73255b + b700: 2520 lbu s0,10(a0) + b702: 4c203a73 csrrc s4,0x4c2,zero + b706: 6e69676f jal a4,a1dec <_data_lma+0x93b90> + b70a: 7220 flw fs0,96(a2) + b70c: 7365 lui t1,0xffff9 + b70e: 6f70 flw fa2,92(a4) + b710: 736e flw ft6,248(sp) + b712: 2065 jal b7ba <_exit+0x362> + b714: 746e6573 csrrsi a0,0x746,28 + b718: 7420 flw fs0,104(s0) + b71a: 6f6e206f j ede10 <_data_lma+0xdfbb4> + b71e: 6564 flw fs1,76(a0) + b720: 2520 lbu s0,10(a0) + b722: 0a0d2e73 csrrs t3,0xa0,s10 + b726: 0000 unimp + b728: 5d73255b 0x5d73255b + b72c: 2520 lbu s0,10(a0) + b72e: 50203a73 csrrc s4,0x502,zero + b732: 7361 lui t1,0xffff8 + b734: 726f7773 csrrci a4,0x726,30 + b738: 2064 lbu s1,6(s0) + b73a: 6e69 lui t3,0x1a + b73c: 72726f63 bltu tp,t2,be7a <_exit+0xa22> + b740: 6365 lui t1,0x19 + b742: 2074 lbu a3,6(s0) + b744: 6f66 flw ft10,88(sp) + b746: 2072 lhu a2,6(s0) + b748: 6f6e flw ft10,216(sp) + b74a: 6564 flw fs1,76(a0) + b74c: 2520 lbu s0,10(a0) + b74e: 0a0d2e73 csrrs t3,0xa0,s10 + b752: 0000 unimp + b754: 6e41 lui t3,0x10 + b756: 6d796e6f jal t3,a262c <_data_lma+0x943d0> + b75a: 5273756f jal a0,43480 <_data_lma+0x35224> + b75e: 7165 addi sp,sp,-400 + b760: 6575 lui a0,0x1d + b762: 61507473 csrrci s0,0x615,0 + b766: 6c79 lui s8,0x1e + b768: 2064616f jal sp,5196e <_data_lma+0x43712> + b76c: 7461 lui s0,0xffff8 + b76e: 2520 lbu s0,10(a0) + b770: 0a70 addi a2,sp,284 + b772: 0000 unimp + b774: 2020 lbu s0,2(s0) + b776: 6564 flw fs1,76(a0) + b778: 6e697473 csrrci s0,0x6e6,18 + b77c: 7461 lui s0,0xffff8 + b77e: 6f69 lui t5,0x1a + b780: 206e lhu a1,6(s0) + b782: 6168 flw fa0,68(a0) + b784: 203a6873 csrrsi a6,hideleg,20 + b788: 7830 flw fa2,112(s0) + b78a: 3025 jal afb2 <_printf_i+0x102> + b78c: 5832 lw a6,44(sp) + b78e: 000a c.slli zero,0x2 + b790: 2020 lbu s0,2(s0) + b792: 646e6573 csrrsi a0,0x646,28 + b796: 7265 lui tp,0xffff9 + b798: 7020 flw fs0,96(s0) + b79a: 6275 lui tp,0x1d + b79c: 3a79654b fnmsub.d fa0,fs2,ft7,ft7,unknown + b7a0: 0020 addi s0,sp,8 + b7a2: 0000 unimp + b7a4: 3025 jal afcc <_printf_i+0x11c> + b7a6: 5832 lw a6,44(sp) + b7a8: 0000 unimp + b7aa: 0000 unimp + b7ac: 2020 lbu s0,2(s0) + b7ae: 68706963 bltu zero,t2,be40 <_exit+0x9e8> + b7b2: 7265 lui tp,0xffff9 + b7b4: 4d20 lw s0,88(a0) + b7b6: 4341 li t1,16 + b7b8: 203a lhu a4,2(s0) + b7ba: 7830 flw fa2,112(s0) + b7bc: 3025 jal afe4 <_printf_i+0x134> + b7be: 5834 lw a3,112(s0) + b7c0: 000a c.slli zero,0x2 + b7c2: 0000 unimp + b7c4: 2020 lbu s0,2(s0) + b7c6: 6564 flw fs1,76(a0) + b7c8: 70797263 bgeu s2,t2,becc <_exit+0xa74> + b7cc: 6574 flw fa3,76(a0) + b7ce: 2064 lbu s1,6(s0) + b7d0: 6170 flw fa2,68(a0) + b7d2: 6c79 lui s8,0x1e + b7d4: 2064616f jal sp,519da <_data_lma+0x4377e> + b7d8: 2528 lbu a0,10(a0) + b7da: 2075 jal b886 <_exit+0x42e> + b7dc: 7962 flw fs2,56(sp) + b7de: 6574 flw fa3,76(a0) + b7e0: 0a3a2973 csrrs s2,0xa3,s4 + b7e4: 0000 unimp + b7e6: 0000 unimp + b7e8: 2020 lbu s0,2(s0) + b7ea: 2020 lbu s0,2(s0) + b7ec: 6974 flw fa3,84(a0) + b7ee: 656d lui a0,0x1b + b7f0: 6d617473 csrrci s0,0x6d6,2 + b7f4: 3a70 lbu a2,23(a2) + b7f6: 2520 lbu s0,10(a0) + b7f8: 0a75 addi s4,s4,29 + b7fa: 0000 unimp + b7fc: 2020 lbu s0,2(s0) + b7fe: 2020 lbu s0,2(s0) + b800: 636e7973 csrrci s2,0x636,28 + b804: 7420 flw fs0,104(s0) + b806: 6d69 lui s10,0x1a + b808: 7365 lui t1,0xffff9 + b80a: 6174 flw fa3,68(a0) + b80c: 706d c.lui zero,0xffffb + b80e: 203a lhu a4,2(s0) + b810: 7525 lui a0,0xfffe9 + b812: 000a c.slli zero,0x2 + b814: 2020 lbu s0,2(s0) + b816: 2020 lbu s0,2(s0) + b818: 6170 flw fa2,68(a0) + b81a: 6f777373 csrrci t1,0x6f7,14 + b81e: 6472 flw fs0,28(sp) + b820: 203a lhu a4,2(s0) + b822: 0000 unimp + b824: 746e6f43 0x746e6f43 + b828: 6f72 flw ft10,28(sp) + b82a: 006c addi a1,sp,12 + b82c: 5d73255b 0x5d73255b + b830: 2520 lbu s0,10(a0) + b832: 52203a73 csrrc s4,0x522,zero + b836: 7065 c.lui zero,0xffff9 + b838: 796c flw fa1,116(a0) + b83a: 6e69 lui t3,0x1a + b83c: 6f742067 0x6f742067 + b840: 6120 flw fs0,64(a0) + b842: 6420 flw fs0,72(s0) + b844: 7369 lui t1,0xffffa + b846: 65766f63 bltu a2,s7,bea4 <_exit+0xa4c> + b84a: 2072 lhu a2,6(s0) + b84c: 6572 flw fa0,28(sp) + b84e: 7571 lui a0,0xffffc + b850: 7365 lui t1,0xffff9 + b852: 2074 lbu a3,6(s0) + b854: 68746977 0x68746977 + b858: 7420 flw fs0,104(s0) + b85a: 6761 lui a4,0x18 + b85c: 2520 lbu s0,10(a0) + b85e: 0d64 addi s1,sp,668 + b860: 000a c.slli zero,0x2 + b862: 0000 unimp + b864: 3d3d jal b6a2 <_exit+0x24a> + b866: 203d jal b894 <_exit+0x43c> + b868: 6944 flw fs1,20(a0) + b86a: 766f6373 csrrsi t1,0x766,30 + b86e: 7265 lui tp,0xffff9 + b870: 5220 lw s0,96(a2) + b872: 7165 addi sp,sp,-400 + b874: 6575 lui a0,0x1d + b876: 3d207473 csrrci s0,0x3d2,0 + b87a: 3d3d jal b6b8 <_exit+0x260> + b87c: 000a c.slli zero,0x2 + b87e: 0000 unimp + b880: 7270 flw fa2,100(a2) + b882: 6665 lui a2,0x19 + b884: 7869 lui a6,0xffffa + b886: 796c6e4f fnmadd.s ft8,fs8,fs6,fa5,unknown + b88a: 3a20 lbu s0,19(a2) + b88c: 2520 lbu s0,10(a0) + b88e: 0a75 addi s4,s4,29 + b890: 0000 unimp + b892: 0000 unimp + b894: 7974 flw fa3,116(a0) + b896: 6570 flw fa2,76(a0) + b898: 6946 flw fs2,80(sp) + b89a: 746c flw fa1,108(s0) + b89c: 7265 lui tp,0xffff9 + b89e: 3a20 lbu s0,19(a2) + b8a0: 3020 lbu s0,3(s0) + b8a2: 2578 lbu a4,14(a0) + b8a4: 3230 lbu a2,3(a2) + b8a6: 0a58 addi a4,sp,276 + b8a8: 0000 unimp + b8aa: 0000 unimp + b8ac: 6174 flw fa3,68(a0) + b8ae: 20202067 0x20202067 + b8b2: 2020 lbu s0,2(s0) + b8b4: 2020 lbu s0,2(s0) + b8b6: 3a20 lbu s0,19(a2) + b8b8: 3020 lbu s0,3(s0) + b8ba: 2578 lbu a4,14(a0) + b8bc: 3830 lbu a2,19(s0) + b8be: 586c lw a1,116(s0) + b8c0: 000a c.slli zero,0x2 + b8c2: 0000 unimp + b8c4: 636e6973 csrrsi s2,0x636,28 + b8c8: 2065 jal b970 <_exit+0x518> + b8ca: 2020 lbu s0,2(s0) + b8cc: 2020 lbu s0,2(s0) + b8ce: 3a20 lbu s0,19(a2) + b8d0: 3020 lbu s0,3(s0) + b8d2: 2578 lbu a4,14(a0) + b8d4: 3830 lbu a2,19(s0) + b8d6: 586c lw a1,116(s0) + b8d8: 000a c.slli zero,0x2 + b8da: 0000 unimp + b8dc: 3d3d jal b71a <_exit+0x2c2> + b8de: 203d jal b90c <_exit+0x4b4> + b8e0: 6944 flw fs1,20(a0) + b8e2: 766f6373 csrrsi t1,0x766,30 + b8e6: 7265 lui tp,0xffff9 + b8e8: 5220 lw s0,96(a2) + b8ea: 7365 lui t1,0xffff9 + b8ec: 6f70 flw fa2,92(a4) + b8ee: 736e flw ft6,248(sp) + b8f0: 2065 jal b998 <_exit+0x540> + b8f2: 3d3d jal b730 <_exit+0x2d8> + b8f4: 0a3d addi s4,s4,15 + b8f6: 0000 unimp + b8f8: 6f6e flw ft10,216(sp) + b8fa: 6564 flw fs1,76(a0) + b8fc: 7954 flw fa3,52(a0) + b8fe: 6570 flw fa2,76(a0) + b900: 3a20 lbu s0,19(a2) + b902: 2520 lbu s0,10(a0) + b904: 0a75 addi s4,s4,29 + b906: 0000 unimp + b908: 20726e73 csrrsi t3,0x207,4 + b90c: 2020 lbu s0,2(s0) + b90e: 2020 lbu s0,2(s0) + b910: 3a20 lbu s0,19(a2) + b912: 2520 lbu s0,10(a0) + b914: 0a75 addi s4,s4,29 + b916: 0000 unimp + b918: 6174 flw fa3,68(a0) + b91a: 20202067 0x20202067 + b91e: 2020 lbu s0,2(s0) + b920: 3a20 lbu s0,19(a2) + b922: 3020 lbu s0,3(s0) + b924: 2578 lbu a4,14(a0) + b926: 3830 lbu a2,19(s0) + b928: 586c lw a1,116(s0) + b92a: 000a c.slli zero,0x2 + b92c: 7570 flw fa2,108(a0) + b92e: 6b62 flw fs6,24(sp) + b930: 7965 lui s2,0xffff9 + b932: 2020 lbu s0,2(s0) + b934: 3a20 lbu s0,19(a2) + b936: 0020 addi s0,sp,8 + b938: 5d73255b 0x5d73255b + b93c: 2520 lbu s0,10(a0) + b93e: 46203a73 csrrc s4,0x462,zero + b942: 6e69 lui t3,0x1a + b944: 6964 flw fs1,84(a0) + b946: 676e flw fa4,216(sp) + b948: 7220 flw fs0,96(a2) + b94a: 6d65 lui s10,0x19 + b94c: 2065746f jal s0,62b52 <_data_lma+0x548f6> + b950: 6f6e flw ft10,216(sp) + b952: 6564 flw fs1,76(a0) + b954: 202c lbu a1,2(s0) + b956: 72756f73 csrrsi t5,0x727,10 + b95a: 61486563 bltu a6,s4,bf64 <_exit+0xb0c> + b95e: 69206873 csrrsi a6,0x692,0 + b962: 64252073 csrs 0x642,a0 + b966: 0a0d addi s4,s4,3 + b968: 0000 unimp + b96a: 0000 unimp + b96c: 5d73255b 0x5d73255b + b970: 2520 lbu s0,10(a0) + b972: 4e203a73 csrrc s4,0x4e2,zero + b976: 2065646f jal s0,61b7c <_data_lma+0x53920> + b97a: 6f6e flw ft10,216(sp) + b97c: 2074 lbu a3,6(s0) + b97e: 6e69 lui t3,0x1a + b980: 4420 lw s0,72(s0) + b982: 0d42 slli s10,s10,0x10 + b984: 000a c.slli zero,0x2 + b986: 0000 unimp + b988: 5d73255b 0x5d73255b + b98c: 2520 lbu s0,10(a0) + b98e: 46203a73 csrrc s4,0x462,zero + b992: 646e756f jal a0,f2fd8 <_data_lma+0xe4d7c> + b996: 6e20 flw fs0,88(a2) + b998: 2065646f jal s0,61b9e <_data_lma+0x53942> + b99c: 68746977 0x68746977 + b9a0: 6920 flw fs0,80(a0) + b9a2: 646e flw fs0,216(sp) + b9a4: 7865 lui a6,0xffff9 + b9a6: 2520 lbu s0,10(a0) + b9a8: 0d64 addi s1,sp,668 + b9aa: 000a c.slli zero,0x2 + b9ac: 5d73255b 0x5d73255b + b9b0: 2520 lbu s0,10(a0) + b9b2: 48203a73 csrrc s4,0x482,zero + b9b6: 414d li sp,19 + b9b8: 61662043 fmadd.s ft0,fa2,fs6,fa2,rdn + b9bc: 6c69 lui s8,0x1a + b9be: 6465 lui s0,0x19 + b9c0: 6f20 flw fs0,88(a4) + b9c2: 206e lhu a1,6(s0) + b9c4: 6e65 lui t3,0x19 + b9c6: 70797263 bgeu s2,t2,c0ca <_exit+0xc72> + b9ca: 6574 flw fa3,76(a0) + b9cc: 2064 lbu s1,6(s0) + b9ce: 656d lui a0,0x1b + b9d0: 67617373 csrrci t1,0x676,2 + b9d4: 2065 jal ba7c <_exit+0x624> + b9d6: 7325 lui t1,0xfffe9 + b9d8: 0a0d addi s4,s4,3 + b9da: 0000 unimp + b9dc: 5d73255b 0x5d73255b + b9e0: 2520 lbu s0,10(a0) + b9e2: 48203a73 csrrc s4,0x482,zero + b9e6: 414d li sp,19 + b9e8: 75732043 0x75732043 + b9ec: 73656363 bltu a0,s6,c112 <_exit+0xcba> + b9f0: 72662073 csrs 0x726,a2 + b9f4: 25206d6f jal s10,11c46 <_data_lma+0x39ea> + b9f8: 25202c73 csrr s8,0x252 + b9fc: 2075 jal baa8 <_exit+0x650> + b9fe: 7962 flw fs2,56(sp) + ba00: 6574 flw fa3,76(a0) + ba02: 6f6c2073 csrs 0x6f6,s8 + ba06: 676e flw fa4,216(sp) + ba08: 0a0d addi s4,s4,3 + ba0a: 0000 unimp + ba0c: 2020 lbu s0,2(s0) + ba0e: 7954 flw fa3,52(a0) + ba10: 6570 flw fa2,76(a0) + ba12: 6478 flw fa4,76(s0) + ba14: 3a64 lbu s1,23(a2) + ba16: 3020 lbu s0,3(s0) + ba18: 2578 lbu a4,14(a0) + ba1a: 3230 lbu a2,3(a2) + ba1c: 0a58 addi a4,sp,276 + ba1e: 0000 unimp + ba20: 2020 lbu s0,2(s0) + ba22: 6150 flw fa2,4(a0) + ba24: 6c79 lui s8,0x1e + ba26: 4c64616f jal sp,51eec <_data_lma+0x43c90> + ba2a: 6e65 lui t3,0x19 + ba2c: 203a lhu a4,2(s0) + ba2e: 7525 lui a0,0xfffe9 + ba30: 000a c.slli zero,0x2 + ba32: 0000 unimp + ba34: 5d73255b 0x5d73255b + ba38: 2520 lbu s0,10(a0) + ba3a: 50203a73 csrrc s4,0x502,zero + ba3e: 7461 lui s0,0xffff8 + ba40: 2068 lbu a0,6(s0) + ba42: 6f74 flw fa3,92(a4) + ba44: 6f6c206f j ce13a <_data_lma+0xbfede> + ba48: 676e flw fa4,216(sp) + ba4a: 0d0a slli s10,s10,0x2 + ba4c: 000a c.slli zero,0x2 + ba4e: 0000 unimp + ba50: 746e6553 0x746e6553 + ba54: 7220 flw fs0,96(a2) + ba56: 7365 lui t1,0xffff9 + ba58: 6f70 flw fa2,92(a4) + ba5a: 736e flw ft6,248(sp) + ba5c: 2c65 jal bd14 <_exit+0x8bc> + ba5e: 7420 flw fs0,104(s0) + ba60: 6568 flw fa0,76(a0) + ba62: 7420 flw fs0,104(s0) + ba64: 6d65 lui s10,0x19 + ba66: 6570 flw fa2,76(a0) + ba68: 6172 flw ft2,28(sp) + ba6a: 7574 flw fa3,108(a0) + ba6c: 6572 flw fa0,28(sp) + ba6e: 6920 flw fs0,80(a0) + ba70: 64252073 csrs 0x642,a0 + ba74: 6420 flw fs0,72(s0) + ba76: 6365 lui t1,0x19 + ba78: 6369 lui t1,0x1a + ba7a: 6c65 lui s8,0x19 + ba7c: 73756973 csrrsi s2,0x737,10 + ba80: 000a c.slli zero,0x2 + ba82: 0000 unimp + ba84: 6c50 flw fa2,28(s0) + ba86: 6961 lui s2,0x18 + ba88: 746e flw fs0,248(sp) + ba8a: 7865 lui a6,0xffff9 + ba8c: 2074 lbu a3,6(s0) + ba8e: 656d lui a0,0x1b + ba90: 67617373 csrrci t1,0x676,2 + ba94: 2065 jal bb3c <_exit+0x6e4> + ba96: 7266 flw ft4,120(sp) + ba98: 25206d6f jal s10,11cea <_data_lma+0x3a8e> + ba9c: 61202c73 csrr s8,0x612 + baa0: 7474 flw fa3,108(s0) + baa2: 6d65 lui s10,0x19 + baa4: 7470 flw fa2,108(s0) + baa6: 2520 lbu s0,10(a0) + baa8: 2c64 lbu s1,30(s0) + baaa: 7420 flw fs0,104(s0) + baac: 6d69 lui s10,0x1a + baae: 7365 lui t1,0xffff9 + bab0: 6174 flw fa3,68(a0) + bab2: 706d c.lui zero,0xffffb + bab4: 2520 lbu s0,10(a0) + bab6: 3a64 lbu s1,23(a2) + bab8: 2520 lbu s0,10(a0) + baba: 6c500073 0x6c500073 + babe: 6961 lui s2,0x18 + bac0: 746e flw fs0,248(sp) + bac2: 7865 lui a6,0xffff9 + bac4: 2074 lbu a3,6(s0) + bac6: 656d lui a0,0x1b + bac8: 67617373 csrrci t1,0x676,2 + bacc: 2065 jal bb74 <_exit+0x71c> + bace: 7266 flw ft4,120(sp) + bad0: 73206d6f jal s10,12202 <_data_lma+0x3fa6> + bad4: 7265 lui tp,0xffff9 + bad6: 6576 flw fa0,92(sp) + bad8: 2072 lhu a2,6(s0) + bada: 7325 lui t1,0xfffe9 + badc: 202c lbu a1,2(s0) + bade: 646e6573 csrrsi a0,0x646,28 + bae2: 7265 lui tp,0xffff9 + bae4: 6920 flw fs0,80(a0) + bae6: 73252073 csrs 0x732,a0 + baea: 202c lbu a1,2(s0) + baec: 7461 lui s0,0xffff8 + baee: 6574 flw fa3,76(a0) + baf0: 706d c.lui zero,0xffffb + baf2: 2074 lbu a3,6(s0) + baf4: 6425 lui s0,0x9 + baf6: 202c lbu a1,2(s0) + baf8: 6974 flw fa3,84(a0) + bafa: 656d lui a0,0x1b + bafc: 6d617473 csrrci s0,0x6d6,2 + bb00: 2070 lbu a2,6(s0) + bb02: 6425 lui s0,0x9 + bb04: 203a lhu a4,2(s0) + bb06: 7325 lui t1,0xfffe9 + bb08: 0000 unimp + bb0a: 0000 unimp + bb0c: 5d73255b 0x5d73255b + bb10: 2520 lbu s0,10(a0) + bb12: 55203a73 csrrc s4,0x552,zero + bb16: 6b6e flw fs6,216(sp) + bb18: 6f6e flw ft10,216(sp) + bb1a: 74206e77 0x74206e77 + bb1e: 7865 lui a6,0xffff9 + bb20: 2074 lbu a3,6(s0) + bb22: 7974 flw fa3,116(a0) + bb24: 6570 flw fa2,76(a0) + bb26: 203a lhu a4,2(s0) + bb28: 6425 lui s0,0x9 + bb2a: 0a0d addi s4,s4,3 + bb2c: 0000 unimp + bb2e: 0000 unimp + bb30: 6e45 lui t3,0x11 + bb32: 70797263 bgeu s2,t2,c236 <_exit+0xdde> + bb36: 6574 flw fa3,76(a0) + bb38: 5064 lw s1,100(s0) + bb3a: 7961 lui s2,0xffff8 + bb3c: 6f6c flw fa1,92(a4) + bb3e: 6461 lui s0,0x18 + bb40: 0a3a slli s4,s4,0xe + bb42: 0000 unimp + bb44: 2020 lbu s0,2(s0) + bb46: 6544 flw fs1,12(a0) + bb48: 6e697473 csrrci s0,0x6e6,18 + bb4c: 7461 lui s0,0xffff8 + bb4e: 6f69 lui t5,0x1a + bb50: 486e lw a6,216(sp) + bb52: 7361 lui t1,0xffff8 + bb54: 3a68 lbu a0,23(a2) + bb56: 3020 lbu s0,3(s0) + bb58: 2578 lbu a4,14(a0) + bb5a: 3230 lbu a2,3(a2) + bb5c: 0a58 addi a4,sp,276 + bb5e: 0000 unimp + bb60: 2020 lbu s0,2(s0) + bb62: 72756f53 0x72756f53 + bb66: 61486563 bltu a6,s4,c170 <_exit+0xd18> + bb6a: 203a6873 csrrsi a6,hideleg,20 + bb6e: 7830 flw fa2,112(s0) + bb70: 3025 jal b398 <_realloc_r+0x2c> + bb72: 5832 lw a6,44(sp) + bb74: 000a c.slli zero,0x2 + bb76: 0000 unimp + bb78: 2020 lbu s0,2(s0) + bb7a: 68706943 fmadd.s fs2,ft0,ft7,fa3,unknown + bb7e: 7265 lui tp,0xffff9 + bb80: 414d li sp,19 + bb82: 30203a43 fmadd.s fs4,ft0,ft2,ft6,rup + bb86: 2578 lbu a4,14(a0) + bb88: 3430 lbu a2,11(s0) + bb8a: 0a58 addi a4,sp,276 + bb8c: 0000 unimp + bb8e: 0000 unimp + bb90: 2020 lbu s0,2(s0) + bb92: 6150 flw fa2,4(a0) + bb94: 6c79 lui s8,0x1e + bb96: 4c64616f jal sp,5205c <_data_lma+0x43e00> + bb9a: 6e65 lui t3,0x19 + bb9c: 203a lhu a4,2(s0) + bb9e: 7a25 lui s4,0xfffe9 + bba0: 0a75 addi s4,s4,29 + bba2: 0000 unimp + bba4: 2020 lbu s0,2(s0) + bba6: 6150 flw fa2,4(a0) + bba8: 6c79 lui s8,0x1e + bbaa: 3a64616f jal sp,51f50 <_data_lma+0x43cf4> + bbae: 0020 addi s0,sp,8 + bbb0: 6552 flw fa0,20(sp) + bbb2: 7571 lui a0,0xffffc + bbb4: 7365 lui t1,0xffff9 + bbb6: 3a74 lbu a3,23(a2) + bbb8: 000a c.slli zero,0x2 + bbba: 0000 unimp + bbbc: 2020 lbu s0,2(s0) + bbbe: 6954 flw fa3,20(a0) + bbc0: 656d lui a0,0x1b + bbc2: 6d617473 csrrci s0,0x6d6,2 + bbc6: 3a70 lbu a2,23(a2) + bbc8: 2520 lbu s0,10(a0) + bbca: 0a75 addi s4,s4,29 + bbcc: 0000 unimp + bbce: 0000 unimp + bbd0: 2020 lbu s0,2(s0) + bbd2: 7954 flw fa3,52(a0) + bbd4: 6570 flw fa2,76(a0) + bbd6: 203a lhu a4,2(s0) + bbd8: 7830 flw fa2,112(s0) + bbda: 3025 jal b402 <_malloc_usable_size_r+0x12> + bbdc: 5832 lw a6,44(sp) + bbde: 000a c.slli zero,0x2 + bbe0: 2020 lbu s0,2(s0) + bbe2: 6144 flw fs1,4(a0) + bbe4: 6174 flw fa3,68(a0) + bbe6: 203a lhu a4,2(s0) + bbe8: 0000 unimp + bbea: 0000 unimp + bbec: 2020 lbu s0,2(s0) + bbee: 6144 flw fs1,4(a0) + bbf0: 6174 flw fa3,68(a0) + bbf2: 0000 unimp + bbf4: 6552 flw fa0,20(sp) + bbf6: 6e6f7073 csrci 0x6e6,30 + bbfa: 0a3a6573 csrrsi a0,0xa3,20 + bbfe: 0000 unimp + bc00: 2020 lbu s0,2(s0) + bc02: 6154 flw fa3,4(a0) + bc04: 25203a67 0x25203a67 + bc08: 0a75 addi s4,s4,29 + bc0a: 0000 unimp + bc0c: 00006e6f jal t3,11c0c <_data_lma+0x39b0> + bc10: 0066666f jal a2,71c16 <_data_lma+0x639ba> + bc14: 2d204b4f 0x2d204b4f + bc18: 7220 flw fs0,96(a2) + bc1a: 7065 c.lui zero,0xffff9 + bc1c: 6165 addi sp,sp,112 + bc1e: 2074 lbu a3,6(s0) + bc20: 7369 lui t1,0xffffa + bc22: 6e20 flw fs0,88(a2) + bc24: 4f20776f jal a4,13116 <_data_lma+0x4eba> + bc28: 004e c.slli zero,0x13 + bc2a: 0000 unimp + bc2c: 2d204b4f 0x2d204b4f + bc30: 7220 flw fs0,96(a2) + bc32: 7065 c.lui zero,0xffff9 + bc34: 6165 addi sp,sp,112 + bc36: 2074 lbu a3,6(s0) + bc38: 7369 lui t1,0xffffa + bc3a: 6e20 flw fs0,88(a2) + bc3c: 4f20776f jal a4,1312e <_data_lma+0x4ed2> + bc40: 4646 lw a2,80(sp) + bc42: 0000 unimp + bc44: 6572 flw fa0,28(sp) + bc46: 6f62 flw ft10,24(sp) + bc48: 0000746f jal s0,12c48 <_data_lma+0x49ec> + bc4c: 6461 lui s0,0x18 + bc4e: 6576 flw fa0,92(sp) + bc50: 7472 flw fs0,60(sp) + bc52: 0000 unimp + bc54: 2d204b4f 0x2d204b4f + bc58: 4120 lw s0,64(a0) + bc5a: 7664 flw fs1,108(a2) + bc5c: 7265 lui tp,0xffff9 + bc5e: 2074 lbu a3,6(s0) + bc60: 746e6573 csrrsi a0,0x746,28 + bc64: 0000 unimp + bc66: 0000 unimp + bc68: 61656c63 bltu a0,s6,c280 <_exit+0xe28> + bc6c: 2072 lhu a2,6(s0) + bc6e: 74617473 csrrci s0,0x746,2 + bc72: 4f280073 0x4f280073 + bc76: 202d204b fnmsub.s ft0,fs10,ft2,ft4,rdn + bc7a: 74617473 csrrci s0,0x746,2 + bc7e: 65722073 csrs 0x657,tp + bc82: 29746573 csrrsi a0,0x297,8 + bc86: 0000 unimp + bc88: 754a flw fa0,176(sp) + bc8a: 206e lhu a1,6(s0) + bc8c: 3532 lhu a2,42(a0) + bc8e: 3220 lbu s0,3(a2) + bc90: 3230 lbu a2,3(a2) + bc92: 0036 c.slli zero,0xd + bc94: 3076 lhu a3,38(s0) + bc96: 302e lhu a1,34(s0) + bc98: 312e lhu a1,34(a0) + bc9a: 2d20 lbu s0,26(a0) + bc9c: 4220 lw s0,64(a2) + bc9e: 4e52 lw t3,20(sp) + bca0: 5320 lw s0,96(a4) + bca2: 7379 lui t1,0xffffe + bca4: 6574 flw fa3,76(a0) + bca6: 736d lui t1,0xffffb + bca8: 5220 lw s0,96(a2) + bcaa: 5349 li t1,-14 + bcac: 00562d43 fmadd.s fs10,fa2,ft5,ft0,rdn + bcb0: 7325 lui t1,0xfffe9 + bcb2: 2820 lbu s0,18(s0) + bcb4: 7542 flw fa0,48(sp) + bcb6: 6c69 lui s8,0x1a + bcb8: 3a64 lbu s1,23(a2) + bcba: 2520 lbu s0,10(a0) + bcbc: 00002973 csrr s2,ustatus + bcc0: 6f62 flw ft10,24(sp) + bcc2: 7261 lui tp,0xffff8 + bcc4: 0064 addi s1,sp,12 + bcc6: 0000 unimp + bcc8: 20484357 0x20484357 + bccc: 32334843 fmadd.d fa6,ft6,ft3,ft6,rmm + bcd0: 3356 lhu a3,36(a4) + bcd2: 3730 lbu a2,11(a4) + bcd4: 0000 unimp + bcd6: 0000 unimp + bcd8: 636f6c63 bltu t5,s6,c310 <_exit+0xeb8> + bcdc: 0000006b 0x6b + bce0: 6974 flw fa3,84(a0) + bce2: 656d lui a0,0x1b + bce4: 0020 addi s0,sp,8 + bce6: 0000 unimp + bce8: 2d204b4f 0x2d204b4f + bcec: 6320 flw fs0,64(a4) + bcee: 6f6c flw fa1,92(a4) + bcf0: 73206b63 bltu zero,s2,c426 + bcf4: 7465 lui s0,0xffff9 + bcf6: 203a lhu a4,2(s0) + bcf8: 3025 jal b520 <_exit+0xc8> + bcfa: 6432 flw fs0,12(sp) + bcfc: 253a lhu a4,10(a0) + bcfe: 3230 lbu a2,3(a2) + bd00: 3a64 lbu s1,23(a2) + bd02: 3025 jal b52a <_exit+0xd2> + bd04: 6432 flw fs0,12(sp) + bd06: 2d20 lbu s0,26(a0) + bd08: 2520 lbu s0,10(a0) + bd0a: 2f64 lbu s1,30(a4) + bd0c: 6425 lui s0,0x9 + bd0e: 2064252f amoxor.w a0,t1,(s0) + bd12: 5455 li s0,-11 + bd14: 00000043 fmadd.s ft0,ft0,ft0,ft0,rne + bd18: 4528 lw a0,72(a0) + bd1a: 5252 lw tp,52(sp) + bd1c: 203a lhu a4,2(s0) + bd1e: 636f6c63 bltu t5,s6,c356 <_exit+0xefe> + bd22: 6163206b 0x6163206b + bd26: 6e6e flw ft8,216(sp) + bd28: 6720746f jal s0,1339a <_data_lma+0x513e> + bd2c: 6162206f j 2e342 <_data_lma+0x200e6> + bd30: 61776b63 bltu a4,s7,c346 <_exit+0xeee> + bd34: 6472 flw fs0,28(sp) + bd36: 00002973 csrr s2,ustatus + bd3a: 0000 unimp + bd3c: 636f6c63 bltu t5,s6,c374 <_exit+0xf1c> + bd40: 7973206b 0x7973206b + bd44: 636e flw ft6,216(sp) + bd46: 0000 unimp + bd48: 5245 li tp,-15 + bd4a: 3a52 lhu a2,52(a2) + bd4c: 6320 flw fs0,64(a4) + bd4e: 6f6c flw fa1,92(a4) + bd50: 63206b63 bltu zero,s2,c386 <_exit+0xf2e> + bd54: 6e61 lui t3,0x18 + bd56: 6f6e flw ft10,216(sp) + bd58: 2074 lbu a3,6(s0) + bd5a: 62206f67 0x62206f67 + bd5e: 6361 lui t1,0x18 + bd60: 7261776b 0x7261776b + bd64: 7364 flw fs1,100(a4) + bd66: 0000 unimp + bd68: 6170 flw fa2,68(a0) + bd6a: 6f777373 csrrci t1,0x6f7,14 + bd6e: 6472 flw fs0,28(sp) + bd70: 0020 addi s0,sp,8 + bd72: 0000 unimp + bd74: 6170 flw fa2,68(a0) + bd76: 6f777373 csrrci t1,0x6f7,14 + bd7a: 6472 flw fs0,28(sp) + bd7c: 6e20 flw fs0,88(a2) + bd7e: 203a776f jal a4,b3780 <_data_lma+0xa5524> + bd82: 7325 lui t1,0xfffe9 + bd84: 0000 unimp + bd86: 0000 unimp + bd88: 20746567 0x20746567 + bd8c: 0000 unimp + bd8e: 0000 unimp + bd90: 73657567 0x73657567 + bd94: 2e74 lbu a3,30(a2) + bd96: 6170 flw fa2,68(a0) + bd98: 6f777373 csrrci t1,0x6f7,14 + bd9c: 6472 flw fs0,28(sp) + bd9e: 0000 unimp + bda0: 203e lhu a5,2(s0) + bda2: 7325 lui t1,0xfffe9 + bda4: 0000 unimp + bda6: 0000 unimp + bda8: 616e flw ft2,216(sp) + bdaa: 656d lui a0,0x1b + bdac: 0000 unimp + bdae: 0000 unimp + bdb0: 6572 flw fa0,28(sp) + bdb2: 6570 flw fa2,76(a0) + bdb4: 7461 lui s0,0xffff8 + bdb6: 0000 unimp + bdb8: 616c flw fa1,68(a0) + bdba: 0074 addi a3,sp,12 + bdbc: 203e lhu a5,2(s0) + bdbe: 6425 lui s0,0x9 + bdc0: 0000 unimp + bdc2: 0000 unimp + bdc4: 6f6c flw fa1,92(a4) + bdc6: 006e c.slli zero,0x1b + bdc8: 7570 flw fa2,108(a0) + bdca: 6c62 flw fs8,24(sp) + bdcc: 6369 lui t1,0x1a + bdce: 6b2e flw fs6,200(sp) + bdd0: 7965 lui s2,0xffff9 + bdd2: 0000 unimp + bdd4: 203e lhu a5,2(s0) + bdd6: 0000 unimp + bdd8: 6f72 flw ft10,28(sp) + bdda: 656c flw fa1,76(a0) + bddc: 0000 unimp + bdde: 0000 unimp + bde0: 6461 lui s0,0x18 + bde2: 756d2e63 0x756d2e63 + bde6: 746c flw fa1,108(s0) + bde8: 7069 c.lui zero,0xffffa + bdea: 696c flw fa1,84(a0) + bdec: 7265 lui tp,0xffff9 + bdee: 0000 unimp + bdf0: 203e lhu a5,2(s0) + bdf2: 6425 lui s0,0x9 + bdf4: 252e lhu a1,10(a0) + bdf6: 0064 addi s1,sp,12 + bdf8: 203a3f3f 00007325 0x7325203a3f3f + be00: 20746573 csrrsi a0,0x207,8 + be04: 0000 unimp + be06: 0000 unimp + be08: 6c61 lui s8,0x18 + be0a: 6f6c flw fa1,92(a4) + be0c: 65722e77 0x65722e77 + be10: 6461 lui s0,0x18 + be12: 6f2e flw ft10,200(sp) + be14: 6c6e flw fs8,216(sp) + be16: 2079 jal bea4 <_exit+0xa4c> + be18: 0000 unimp + be1a: 0000 unimp + be1c: 00004b4f fnmadd.s fs6,ft0,ft0,ft0,rmm + be20: 73657567 0x73657567 + be24: 2e74 lbu a3,30(a2) + be26: 6170 flw fa2,68(a0) + be28: 6f777373 csrrci t1,0x6f7,14 + be2c: 6472 flw fs0,28(sp) + be2e: 0020 addi s0,sp,8 + be30: 616e flw ft2,216(sp) + be32: 656d lui a0,0x1b + be34: 0020 addi s0,sp,8 + be36: 0000 unimp + be38: 6572 flw fa0,28(sp) + be3a: 6570 flw fa2,76(a0) + be3c: 7461 lui s0,0xffff8 + be3e: 0020 addi s0,sp,8 + be40: 616c flw fa1,68(a0) + be42: 2074 lbu a3,6(s0) + be44: 0000 unimp + be46: 0000 unimp + be48: 6f6c flw fa1,92(a4) + be4a: 206e lhu a1,6(s0) + be4c: 0000 unimp + be4e: 0000 unimp + be50: 6e75 lui t3,0x1d + be52: 776f6e6b 0x776f6e6b + be56: 206e lhu a1,6(s0) + be58: 666e6f63 bltu t3,t1,c4d6 + be5c: 6769 lui a4,0x1a + be5e: 203a lhu a4,2(s0) + be60: 7325 lui t1,0xfffe9 + be62: 0000 unimp + be64: 74617473 csrrci s0,0x746,2 + be68: 61702d73 csrr s10,0x617 + be6c: 74656b63 bltu a0,t1,c5c2 + be70: 00000073 ecall + be74: 6572227b 0x6572227b + be78: 3a227663 bgeu tp,sp,c224 <_exit+0xdcc> + be7c: 7525 lui a0,0xfffe9 + be7e: 222c lbu a1,2(a2) + be80: 746e6573 csrrsi a0,0x746,28 + be84: 3a22 lhu s0,50(a2) + be86: 7525 lui a0,0xfffe9 + be88: 222c lbu a1,2(a2) + be8a: 6c66 flw fs8,88(sp) + be8c: 5f646f6f jal t5,52482 <_data_lma+0x44226> + be90: 7874 flw fa3,116(s0) + be92: 3a22 lhu s0,50(a2) + be94: 7525 lui a0,0xfffe9 + be96: 222c lbu a1,2(a2) + be98: 6964 flw fs1,84(a0) + be9a: 6572 flw fa0,28(sp) + be9c: 745f7463 bgeu t5,t0,c5e4 + bea0: 2278 lbu a4,6(a2) + bea2: 253a lhu a4,10(a0) + bea4: 2c75 jal c160 <_exit+0xd08> + bea6: 6622 flw fa2,8(sp) + bea8: 6f6c flw fa1,92(a4) + beaa: 725f646f jal s0,102dce <_data_lma+0xf4b72> + beae: 2278 lbu a4,6(a2) + beb0: 253a lhu a4,10(a0) + beb2: 2c75 jal c16e <_exit+0xd16> + beb4: 6422 flw fs0,8(sp) + beb6: 7269 lui tp,0xffffa + beb8: 6365 lui t1,0x19 + beba: 5f74 lw a3,124(a4) + bebc: 7872 flw fa6,60(sp) + bebe: 3a22 lhu s0,50(a2) + bec0: 7525 lui a0,0xfffe9 + bec2: 007d c.nop 31 + bec4: 74617473 csrrci s0,0x746,2 + bec8: 61722d73 csrrs s10,0x617,tp + becc: 6964 flw fs1,84(a0) + bece: 227b006f j bc8f4 <_data_lma+0xae698> + bed2: 6f6e flw ft10,216(sp) + bed4: 7369 lui t1,0xffffa + bed6: 5f65 li t5,-7 + bed8: 6c66 flw fs8,88(sp) + beda: 22726f6f jal t5,32900 <_data_lma+0x246a4> + bede: 253a lhu a4,10(a0) + bee0: 2c64 lbu s1,30(s0) + bee2: 6c22 flw fs8,8(sp) + bee4: 7361 lui t1,0xffff8 + bee6: 5f74 lw a3,124(a4) + bee8: 7372 flw ft6,60(sp) + beea: 3a226973 csrrsi s2,pmpcfg2,4 + beee: 6425 lui s0,0x9 + bef0: 222c lbu a1,2(a2) + bef2: 616c flw fa1,68(a0) + bef4: 735f7473 csrrci s0,0x735,30 + bef8: 726e flw ft4,248(sp) + befa: 3a22 lhu s0,50(a2) + befc: 6425 lui s0,0x9 + befe: 302e lhu a1,34(s0) + bf00: 2c30 lbu a2,26(s0) + bf02: 7422 flw fs0,40(sp) + bf04: 5f78 lw a4,124(a4) + bf06: 6961 lui s2,0x18 + bf08: 5f72 lw t5,60(sp) + bf0a: 73636573 csrrsi a0,0x736,6 + bf0e: 3a22 lhu s0,50(a2) + bf10: 7525 lui a0,0xfffe9 + bf12: 222c lbu a1,2(a2) + bf14: 7872 flw fa6,60(sp) + bf16: 615f 7269 735f 0x735f7269615f + bf1c: 6365 lui t1,0x19 + bf1e: 253a2273 csrrs tp,0x253,s4 + bf22: 7d75 lui s10,0xffffd + bf24: 0000 unimp + bf26: 0000 unimp + bf28: 74617473 csrrci s0,0x746,2 + bf2c: 6f632d73 csrrs s10,0x6f6,t1 + bf30: 6572 flw fa0,28(sp) + bf32: 0000 unimp + bf34: 6162227b 0x6162227b + bf38: 7474 flw fa3,108(s0) + bf3a: 7265 lui tp,0xffff9 + bf3c: 5f79 li t5,-2 + bf3e: 766d lui a2,0xffffb + bf40: 3a22 lhu s0,50(a2) + bf42: 7525 lui a0,0xfffe9 + bf44: 222c lbu a1,2(a2) + bf46: 7075 c.lui zero,0xffffd + bf48: 6974 flw fa3,84(a0) + bf4a: 656d lui a0,0x1b + bf4c: 735f 6365 2273 0x22736365735f + bf52: 253a lhu a4,10(a0) + bf54: 2c75 jal c210 <_exit+0xdb8> + bf56: 6522 flw fa0,8(sp) + bf58: 7272 flw ft4,60(sp) + bf5a: 2273726f jal tp,43980 <_data_lma+0x35724> + bf5e: 253a lhu a4,10(a0) + bf60: 2c75 jal c21c <_exit+0xdc4> + bf62: 7122 flw ft2,40(sp) + bf64: 6575 lui a0,0x1d + bf66: 6575 lui a0,0x1d + bf68: 6c5f 6e65 3a22 0x3a226e656c5f + bf6e: 7525 lui a0,0xfffe9 + bf70: 007d c.nop 31 + bf72: 0000 unimp + bf74: 6e55 lui t3,0x15 + bf76: 776f6e6b 0x776f6e6b + bf7a: 206e lhu a1,6(s0) + bf7c: 6d6d6f63 bltu s10,s6,c65a + bf80: 6e61 lui t3,0x18 + bf82: 0064 addi s1,sp,12 + bf84: 6e45 lui t3,0x11 + bf86: 70797263 bgeu s2,t2,c68a + bf8a: 6574 flw fa3,76(a0) + bf8c: 4d64 lw s1,92(a0) + bf8e: 7365 lui t1,0xffff9 + bf90: 65676173 csrrsi sp,0x656,14 + bf94: 0000 unimp + bf96: 0000 unimp + bf98: 5d73255b 0x5d73255b + bf9c: 2520 lbu s0,10(a0) + bf9e: 50203a73 csrrc s4,0x502,zero + bfa2: 616c flw fa1,68(a0) + bfa4: 6e69 lui t3,0x1a + bfa6: 6c20 flw fs0,88(s0) + bfa8: 6e65 lui t3,0x19 + bfaa: 203a lhu a4,2(s0) + bfac: 6425 lui s0,0x9 + bfae: 202c lbu a1,2(s0) + bfb0: 6e65 lui t3,0x19 + bfb2: 656c2063 0x656c2063 + bfb6: 3a6e lhu a1,54(a2) + bfb8: 2520 lbu s0,10(a0) + bfba: 0d64 addi s1,sp,668 + bfbc: 000a c.slli zero,0x2 + bfbe: 0000 unimp + bfc0: 6e45 lui t3,0x11 + bfc2: 70797263 bgeu s2,t2,c6c6 + bfc6: 6574 flw fa3,76(a0) + bfc8: 2064 lbu s1,6(s0) + bfca: 7266 flw ft4,120(sp) + bfcc: 6d61 lui s10,0x18 + bfce: 0065 c.nop 25 + bfd0: 5d73255b 0x5d73255b + bfd4: 2520 lbu s0,10(a0) + bfd6: 45203a73 csrrc s4,0x452,zero + bfda: 636e flw ft6,216(sp) + bfdc: 7972 flw fs2,60(sp) + bfde: 7470 flw fa2,108(s0) + bfe0: 6465 lui s0,0x19 + bfe2: 6620 flw fs0,72(a2) + bfe4: 6172 flw ft2,28(sp) + bfe6: 656d lui a0,0x1b + bfe8: 7420 flw fs0,104(s0) + bfea: 2078 lbu a4,6(s0) + bfec: 6966 flw fs2,88(sp) + bfee: 696e flw fs2,216(sp) + bff0: 0d0a6873 csrrsi a6,0xd0,20 + bff4: 000a c.slli zero,0x2 + bff6: 0000 unimp + bff8: 5d73255b 0x5d73255b + bffc: 2520 lbu s0,10(a0) + bffe: 4e203a73 csrrc s4,0x4e2,zero + c002: 2065646f jal s0,62208 <_data_lma+0x53fac> + c006: 7369 lui t1,0xffffa + c008: 6e20 flw fs0,88(a2) + c00a: 6c75 lui s8,0x1d + c00c: 0d6c addi a1,sp,668 + c00e: 000a c.slli zero,0x2 + c010: 5d73255b 0x5d73255b + c014: 2520 lbu s0,10(a0) + c016: 4e203a73 csrrc s4,0x4e2,zero + c01a: 2065646f jal s0,62220 <_data_lma+0x53fc4> + c01e: 7369 lui t1,0xffffa + c020: 6e20 flw fs0,88(a2) + c022: 7020746f jal s0,13724 <_data_lma+0x54c8> + c026: 6c75706f j 63eec <_data_lma+0x55c90> + c02a: 7461 lui s0,0xffff8 + c02c: 6465 lui s0,0x19 + c02e: 0a0d addi s4,s4,3 + c030: 0000 unimp + c032: 0000 unimp + c034: 756f7247 0x756f7247 + c038: 4d70 lw a2,92(a0) + c03a: 7365 lui t1,0xffff9 + c03c: 65676173 csrrsi sp,0x656,14 + c040: 0000 unimp + c042: 0000 unimp + c044: 5d73255b 0x5d73255b + c048: 2520 lbu s0,10(a0) + c04a: 4e203a73 csrrc s4,0x4e2,zero + c04e: 6120746f jal s0,13660 <_data_lma+0x5404> + c052: 6720 flw fs0,72(a4) + c054: 6f72 flw ft10,28(sp) + c056: 7075 c.lui zero,0xffffd + c058: 7420 flw fs0,104(s0) + c05a: 7865 lui a6,0xffff9 + c05c: 0d74 addi a3,sp,668 + c05e: 000a c.slli zero,0x2 + c060: 5d73255b 0x5d73255b + c064: 2520 lbu s0,10(a0) + c066: 43203a73 csrrc s4,0x432,zero + c06a: 6168 flw fa0,68(a0) + c06c: 6e6e flw ft8,216(sp) + c06e: 6c65 lui s8,0x19 + c070: 6820 flw fs0,80(s0) + c072: 7361 lui t1,0xffff8 + c074: 2068 lbu a0,6(s0) + c076: 6425 lui s0,0x9 + c078: 6e20 flw fs0,88(a2) + c07a: 6620746f jal s0,136dc <_data_lma+0x5480> + c07e: 646e756f jal a0,f36c4 <_data_lma+0xe5468> + c082: 0a0d addi s4,s4,3 + c084: 0000 unimp + c086: 0000 unimp + c088: 5d73255b 0x5d73255b + c08c: 2520 lbu s0,10(a0) + c08e: 48203a73 csrrc s4,0x482,zero + c092: 414d li sp,19 + c094: 61662043 fmadd.s ft0,fa2,fs6,fa2,rdn + c098: 6c69 lui s8,0x1a + c09a: 6465 lui s0,0x19 + c09c: 6f20 flw fs0,88(a4) + c09e: 206e lhu a1,6(s0) + c0a0: 756f7267 0x756f7267 + c0a4: 6870 flw fa2,84(s0) + c0a6: 7361 lui t1,0xffff8 + c0a8: 2068 lbu a0,6(s0) + c0aa: 2079656b 0x2079656b + c0ae: 6425 lui s0,0x9 + c0b0: 0a0d addi s4,s4,3 + c0b2: 0000 unimp + c0b4: 654d lui a0,0x13 + c0b6: 67617373 csrrci t1,0x676,2 + c0ba: 2065 jal c162 <_exit+0xd0a> + c0bc: 7266 flw ft4,120(sp) + c0be: 63206d6f jal s10,126f0 <_data_lma+0x4494> + c0c2: 6168 flw fa0,68(a0) + c0c4: 6e6e flw ft8,216(sp) + c0c6: 6c65 lui s8,0x19 + c0c8: 2520 lbu s0,10(a0) + c0ca: 25203a73 csrrc s4,0x252,zero + c0ce: 00000a73 0xa73 + c0d2: 0000 unimp + c0d4: 7854 flw fa3,52(s0) + c0d6: 7544 flw fs1,44(a0) + c0d8: 706d c.lui zero,0xffffb + c0da: 6544 flw fs1,12(a0) + c0dc: 00000063 beqz zero,c0dc <_exit+0xc84> + c0e0: 654d lui a0,0x13 + c0e2: 6f436873 csrrsi a6,0x6f4,6 + c0e6: 6572 flw fa0,28(sp) + c0e8: 0000 unimp + c0ea: 0000 unimp + c0ec: 5d73255b 0x5d73255b + c0f0: 2520 lbu s0,10(a0) + c0f2: 46203a73 csrrc s4,0x462,zero + c0f6: 6172 flw ft2,28(sp) + c0f8: 656d lui a0,0x1b + c0fa: 7420 flw fs0,104(s0) + c0fc: 6e206f6f jal t5,127de <_data_lma+0x4582> + c100: 7765 lui a4,0xffff9 + c102: 202c lbu a1,2(s0) + c104: 20746f67 0x20746f67 + c108: 6576 flw fa0,92(sp) + c10a: 7372 flw ft6,60(sp) + c10c: 6f69 lui t5,0x1a + c10e: 206e lhu a1,6(s0) + c110: 6425 lui s0,0x9 + c112: 6920 flw fs0,80(a0) + c114: 736e flw ft6,248(sp) + c116: 6574 flw fa3,76(a0) + c118: 6461 lui s0,0x18 + c11a: 6f20 flw fs0,88(a4) + c11c: 2066 lhu s1,6(s0) + c11e: 0d30 addi a2,sp,664 + c120: 000a c.slli zero,0x2 + c122: 0000 unimp + c124: 2020 lbu s0,2(s0) + c126: 7954 flw fa3,52(a0) + c128: 6570 flw fa2,76(a0) + c12a: 6478 flw fa4,76(s0) + c12c: 203a lhu a4,2(s0) + c12e: 7830 flw fa2,112(s0) + c130: 3025 jal b958 <_exit+0x500> + c132: 5832 lw a6,44(sp) + c134: 000a c.slli zero,0x2 + c136: 0000 unimp + c138: 5d73255b 0x5d73255b + c13c: 2520 lbu s0,10(a0) + c13e: 50203a73 csrrc s4,0x502,zero + c142: 6f72 flw ft10,28(sp) + c144: 73736563 bltu t1,s7,c86e + c148: 6465 lui s0,0x19 + c14a: 6620 flw fs0,72(a2) + c14c: 6172 flw ft2,28(sp) + c14e: 656d lui a0,0x1b + c150: 0a0d addi s4,s4,3 + c152: 0000 unimp + c154: 21ce lhu a1,4(a1) + c156: 0000 unimp + c158: 221e lhu a5,0(a2) + c15a: 0000 unimp + c15c: 2234 lbu a3,2(a2) + c15e: 0000 unimp + c160: 224c lbu a1,4(a2) + c162: 0000 unimp + c164: 2262 lhu s0,6(a2) + c166: 0000 unimp + c168: 2680 lbu s0,8(a3) + c16a: 0000 unimp + c16c: 2694 lbu a3,8(a3) + c16e: 0000 unimp + c170: 26aa lhu a0,10(a3) + c172: 0000 unimp + c174: 26b6 lhu a3,10(a3) + c176: 0000 unimp + c178: 26cc lbu a1,12(a3) + c17a: 0000 unimp + c17c: 654d lui a0,0x13 + c17e: 72666873 csrrsi a6,0x726,12 + c182: 6d61 lui s10,0x18 + c184: 6e69 lui t3,0x1a + c186: 00450067 jr 4(a0) # 13004 <_data_lma+0x4da8> + c18a: 0000 unimp + c18c: 5d73255b 0x5d73255b + c190: 2520 lbu s0,10(a0) + c192: 25203a73 csrrc s4,0x252,zero + c196: 2064 lbu s1,6(s0) + c198: 7369 lui t1,0xffffa + c19a: 7420 flw fs0,104(s0) + c19c: 62206f6f jal t5,127be <_data_lma+0x4562> + c1a0: 6769 lui a4,0x1a + c1a2: 6620 flw fs0,72(a2) + c1a4: 7320726f jal tp,138d6 <_data_lma+0x567a> + c1a8: 3178 lbu a4,7(a0) + c1aa: 3632 lhu a2,42(a2) + c1ac: 0d32 slli s10,s10,0xc + c1ae: 000a c.slli zero,0x2 + c1b0: 72617473 csrrci s0,0x726,2 + c1b4: 2074 lbu a3,6(s0) + c1b6: 74697257 0x74697257 + c1ba: 4265 li tp,25 + c1bc: 6675 lui a2,0x1d + c1be: 6566 flw fa0,88(sp) + c1c0: 0072 c.slli zero,0x1c + c1c2: 0000 unimp + c1c4: 6e65 lui t3,0x19 + c1c6: 2064 lbu s1,6(s0) + c1c8: 74697257 0x74697257 + c1cc: 4265 li tp,25 + c1ce: 6675 lui a2,0x1d + c1d0: 6566 flw fa0,88(sp) + c1d2: 0072 c.slli zero,0x1c + c1d4: 5d73255b 0x5d73255b + c1d8: 2520 lbu s0,10(a0) + c1da: 54203a73 csrrc s4,0x542,zero + c1de: 2058 lbu a4,4(s0) + c1e0: 6170 flw fa2,68(a0) + c1e2: 6c79 lui s8,0x1e + c1e4: 4c64616f jal sp,526aa <_data_lma+0x4444e> + c1e8: 6e65 lui t3,0x19 + c1ea: 253d jal c818 + c1ec: 2075 jal c298 <_exit+0xe40> + c1ee: 6170 flw fa2,68(a0) + c1f0: 6874 flw fa3,84(s0) + c1f2: 654c flw fa1,12(a0) + c1f4: 3d6e lhu a1,62(a0) + c1f6: 7525 lui a0,0xfffe9 + c1f8: 7420 flw fs0,104(s0) + c1fa: 6c61746f jal s0,238c0 <_data_lma+0x15664> + c1fe: 654c flw fa1,12(a0) + c200: 3d6e lhu a1,62(a0) + c202: 7525 lui a0,0xfffe9 + c204: 6820 flw fs0,80(s0) + c206: 6165 addi sp,sp,112 + c208: 6564 flw fs1,76(a0) + c20a: 3d72 lhu a2,62(a0) + c20c: 7830 flw fa2,112(s0) + c20e: 3025 jal ba36 <_exit+0x5de> + c210: 5832 lw a6,44(sp) + c212: 0a0d addi s4,s4,3 + c214: 0000 unimp + c216: 0000 unimp + c218: 5d73255b 0x5d73255b + c21c: 2520 lbu s0,10(a0) + c21e: 53203a73 csrrc s4,0x532,zero + c222: 6174 flw fa3,68(a0) + c224: 7472 flw fs0,60(sp) + c226: 6e69 lui t3,0x1a + c228: 78742067 0x78742067 + c22c: 6d20 flw fs0,88(a0) + c22e: 2c65646f jal s0,624f4 <_data_lma+0x54298> + c232: 7320 flw fs0,96(a4) + c234: 6e65 lui t3,0x19 + c236: 2074 lbu a3,6(s0) + c238: 6425 lui s0,0x9 + c23a: 202c lbu a1,2(s0) + c23c: 756f6873 csrrsi a6,0x756,30 + c240: 646c flw fa1,76(s0) + c242: 2520 lbu s0,10(a0) + c244: 0d64 addi s1,sp,668 + c246: 000a c.slli zero,0x2 + c248: 5d73255b 0x5d73255b + c24c: 2520 lbu s0,10(a0) + c24e: 53203a73 csrrc s4,0x532,zero + c252: 7465 lui s0,0xffff9 + c254: 7854 flw fa3,52(s0) + c256: 7220 flw fs0,96(a2) + c258: 6e75 lui t3,0x1d + c25a: 696e flw fs2,216(sp) + c25c: 676e flw fa4,216(sp) + c25e: 0a0d addi s4,s4,3 + c260: 0000 unimp + c262: 0000 unimp + c264: 5d73255b 0x5d73255b + c268: 2520 lbu s0,10(a0) + c26a: 69203a73 csrrc s4,0x692,zero + c26e: 7172 flw ft2,60(sp) + c270: 203a lhu a4,2(s0) + c272: 7830 flw fa2,112(s0) + c274: 3025 jal ba9c <_exit+0x644> + c276: 5834 lw a3,112(s0) + c278: 0a0d addi s4,s4,3 + c27a: 0000 unimp + c27c: 5d73255b 0x5d73255b + c280: 2520 lbu s0,10(a0) + c282: 46203a73 csrrc s4,0x462,zero + c286: 6e69 lui t3,0x1a + c288: 7369 lui t1,0xffffa + c28a: 6568 flw fa0,76(a0) + c28c: 2064 lbu s1,6(s0) + c28e: 7874 flw fa3,116(s0) + c290: 0a0d addi s4,s4,3 + c292: 0000 unimp + c294: 72617473 csrrci s0,0x726,2 + c298: 2074 lbu a3,6(s0) + c29a: 6552 flw fa0,20(sp) + c29c: 6461 lui s0,0x18 + c29e: 7542 flw fa0,48(sp) + c2a0: 6666 flw fa2,88(sp) + c2a2: 7265 lui tp,0xffff9 + c2a4: 0000 unimp + c2a6: 0000 unimp + c2a8: 6e65 lui t3,0x19 + c2aa: 2064 lbu s1,6(s0) + c2ac: 6552 flw fa0,20(sp) + c2ae: 6461 lui s0,0x18 + c2b0: 7542 flw fa0,48(sp) + c2b2: 6666 flw fa2,88(sp) + c2b4: 7265 lui tp,0xffff9 + c2b6: 0000 unimp + c2b8: 7274 flw fa3,100(a2) + c2ba: 6e61 lui t3,0x18 + c2bc: 726f7073 csrci 0x726,30 + c2c0: 2074 lbu a3,6(s0) + c2c2: 6c66 flw fs8,88(sp) + c2c4: 00646f6f jal t5,522ca <_data_lma+0x4406e> + c2c8: 6c66 flw fs8,88(sp) + c2ca: 00646f6f jal t5,522d0 <_data_lma+0x44074> + c2ce: 0000 unimp + c2d0: 6964 flw fs1,84(a0) + c2d2: 6572 flw fa0,28(sp) + c2d4: 00007463 bgeu zero,zero,c2dc <_exit+0xe84> + c2d8: 7274 flw fa3,100(a2) + c2da: 6e61 lui t3,0x18 + c2dc: 726f7073 csrci 0x726,30 + c2e0: 2074 lbu a3,6(s0) + c2e2: 6964 flw fs1,84(a0) + c2e4: 6572 flw fa0,28(sp) + c2e6: 00007463 bgeu zero,zero,c2ee <_exit+0xe96> + c2ea: 0000 unimp + c2ec: 202c lbu a1,2(s0) + c2ee: 6170 flw fa2,68(a0) + c2f0: 6c79 lui s8,0x1e + c2f2: 2064616f jal sp,524f8 <_data_lma+0x4429c> + c2f6: 7974 flw fa3,116(a0) + c2f8: 6570 flw fa2,76(a0) + c2fa: 6920 flw fs0,80(a0) + c2fc: 00002073 csrr zero,ustatus + c300: 6572 flw fa0,28(sp) + c302: 7571 lui a0,0xffffc + c304: 7365 lui t1,0xffff9 + c306: 0074 addi a3,sp,12 + c308: 6572 flw fa0,28(sp) + c30a: 6e6f7073 csrci 0x6e6,30 + c30e: 00006573 csrrsi a0,ustatus,0 + c312: 0000 unimp + c314: 6574 flw fa3,76(a0) + c316: 7478 flw fa4,108(s0) + c318: 6d20 flw fs0,88(a0) + c31a: 7365 lui t1,0xffff9 + c31c: 65676173 csrrsi sp,0x656,14 + c320: 0000 unimp + c322: 0000 unimp + c324: 6361 lui t1,0x18 + c326: 776f6e6b 0x776f6e6b + c32a: 656c flw fa1,76(a0) + c32c: 6764 flw fs1,76(a4) + c32e: 6d65 lui s10,0x19 + c330: 6e65 lui t3,0x19 + c332: 0074 addi a3,sp,12 + c334: 756f7267 0x756f7267 + c338: 2070 lbu a2,6(s0) + c33a: 6574 flw fa3,76(a0) + c33c: 7478 flw fa4,108(s0) + c33e: 0000 unimp + c340: 756f7267 0x756f7267 + c344: 2070 lbu a2,6(s0) + c346: 6164 flw fs1,68(a0) + c348: 6174 flw fa3,68(a0) + c34a: 0000 unimp + c34c: 6e61 lui t3,0x18 + c34e: 72206e6f jal t3,12a70 <_data_lma+0x4814> + c352: 7165 addi sp,sp,-400 + c354: 6575 lui a0,0x1d + c356: 00007473 csrrci s0,ustatus,0 + c35a: 0000 unimp + c35c: 6170 flw fa2,68(a0) + c35e: 6874 flw fa3,84(s0) + c360: 0000 unimp + c362: 0000 unimp + c364: 7274 flw fa3,100(a2) + c366: 6361 lui t1,0x18 + c368: 0065 c.nop 25 + c36a: 0000 unimp + c36c: 756d lui a0,0xffffb + c36e: 746c flw fa1,108(s0) + c370: 7069 c.lui zero,0xffffa + c372: 7261 lui tp,0xffff8 + c374: 0074 addi a3,sp,12 + c376: 0000 unimp + c378: 746e6f63 bltu t3,t1,cad6 + c37c: 6f72 flw ft10,28(sp) + c37e: 006c addi a1,sp,12 + c380: 6172 flw ft2,28(sp) + c382: 202c0077 0x202c0077 + c386: 6170 flw fa2,68(a0) + c388: 6c79 lui s8,0x1e + c38a: 2064616f jal sp,52590 <_data_lma+0x44334> + c38e: 6576 flw fa0,92(sp) + c390: 7372 flw ft6,60(sp) + c392: 6f69 lui t5,0x1a + c394: 206e lhu a1,6(s0) + c396: 7369 lui t1,0xffffa + c398: 2520 lbu s0,10(a0) + c39a: 00002073 csrr zero,ustatus + c39e: 0000 unimp + c3a0: 7254 flw fa3,36(a2) + c3a2: 6e61 lui t3,0x18 + c3a4: 726f7073 csrci 0x726,30 + c3a8: 2074 lbu a3,6(s0) + c3aa: 65646f63 bltu s0,s6,ca08 + c3ae: 25203a73 csrrc s4,0x252,zero + c3b2: 2064 lbu s1,6(s0) + c3b4: 6425 lui s0,0x9 + c3b6: 000a c.slli zero,0x2 + c3b8: 6150 flw fa2,4(a0) + c3ba: 6874 flw fa3,84(s0) + c3bc: 6920 flw fs0,80(a0) + c3be: 64252073 csrs 0x642,a0 + c3c2: 6e20 flw fs0,88(a2) + c3c4: 7365646f jal s0,62afa <_data_lma+0x5489e> + c3c8: 6c20 flw fs0,88(s0) + c3ca: 00676e6f jal t3,823d0 <_data_lma+0x74174> + c3ce: 0000 unimp + c3d0: 6f6e flw ft10,216(sp) + c3d2: 6564 flw fs1,76(a0) + c3d4: 2520 lbu s0,10(a0) + c3d6: 2064 lbu s1,6(s0) + c3d8: 202d jal c402 + c3da: 3025 jal bc02 <_exit+0x7aa> + c3dc: 5832 lw a6,44(sp) + c3de: 202c lbu a1,2(s0) + c3e0: 0000 unimp + ... + +0000c3e4 : + c3e4: 1c1f 1e1f 1e1f 1f1f 1f1e 1f1e ............ + +0000c3f0 : + c3f0: 614a 466e 6265 614d 4172 7270 614d 4a79 JanFebMarAprMayJ + c400: 6e75 754a 416c 6775 6553 4f70 7463 6f4e unJulAugSepOctNo + c410: 4476 6365 0000 0000 vDec.... + +0000c418 : + c418: 0300 0603 0401 0206 0005 0503 0000 0000 ................ + +0000c428 : + c428: ae22 d728 2f98 428a 65cd 23ef 4491 7137 ".(../.B.e.#.D7q + c438: 3b2f ec4d fbcf b5c0 dbbc 8189 dba5 e9b5 /;M............. + c448: b538 f348 c25b 3956 d019 b605 11f1 59f1 8.H.[.V9.......Y + c458: 4f9b af19 82a4 923f 8118 da6d 5ed5 ab1c .O....?...m..^.. + c468: 0242 a303 aa98 d807 6fbe 4570 5b01 1283 B........opE.[.. + c478: b28c 4ee4 85be 2431 b4e2 d5ff 7dc3 550c ...N..1$.....}.U + c488: 896f f27b 5d74 72be 96b1 3b16 b1fe 80de o.{.t].r...;.... + c498: 1235 25c7 06a7 9bdc 2694 cf69 f174 c19b 5..%.....&i.t... + c4a8: 4ad2 9ef1 69c1 e49b 25e3 384f 4786 efbe .J...i...%O8.G.. + c4b8: d5b5 8b8c 9dc6 0fc1 9c65 77ac a1cc 240c ........e..w...$ + c4c8: 0275 592b 2c6f 2de9 e483 6ea6 84aa 4a74 u.+Yo,.-...n..tJ + c4d8: fbd4 bd41 a9dc 5cb0 53b5 8311 88da 76f9 ..A....\.S.....v + c4e8: dfab ee66 5152 983e 3210 2db4 c66d a831 ..f.RQ>..2.-m.1. + c4f8: 213f 98fb 27c8 b003 0ee4 beef 7fc7 bf59 ?!...'........Y. + c508: 8fc2 3da8 0bf3 c6e0 a725 930a 9147 d5a7 ...=....%...G... + c518: 826f e003 6351 06ca 6e70 0a0e 2967 1429 o...Qc..pn..g)). + c528: 2ffc 46d2 0a85 27b7 c926 5c26 2138 2e1b ./.F...'&.&\8!.. + c538: 2aed 5ac4 6dfc 4d2c b3df 9d95 0d13 5338 .*.Z.m,M......8S + c548: 63de 8baf 7354 650a b2a8 3c77 0abb 766a .c..Ts.e..w<..jv + c558: aee6 47ed c92e 81c2 353b 1482 2c85 9272 ...G....;5...,r. + c568: 0364 4cf1 e8a1 a2bf 3001 bc42 664b a81a d..L.....0B.Kf.. + c578: 9791 d0f8 8b70 c24b be30 0654 51a3 c76c ....p.K.0.T..Ql. + c588: 5218 d6ef e819 d192 a910 5565 0624 d699 .R........eU$... + c598: 202a 5771 3585 f40e d1b8 32bb a070 106a * qW.5.....2p.j. + c5a8: d0c8 b8d2 c116 19a4 ab53 5141 6c08 1e37 ........S.AQ.l7. + c5b8: eb99 df8e 774c 2748 48a8 e19b bcb5 34b0 ....LwH'.H.....4 + c5c8: 5a63 c5c9 0cb3 391c 8acb e341 aa4a 4ed8 cZ.....9..A.J..N + c5d8: e373 7763 ca4f 5b9c b8a3 d6b2 6ff3 682e s.cwO..[.....o.h + c5e8: b2fc 5def 82ee 748f 2f60 4317 636f 78a5 ...]...t`/.Coc.x + c5f8: ab72 a1f0 7814 84c8 39ec 1a64 0208 8cc7 r....x...9d..... + c608: 1e28 2363 fffa 90be bde9 de82 6ceb a450 (.c#.........lP. + c618: 7915 b2c6 a3f7 bef9 532b e372 78f2 c671 .y......+Sr..xq. + c628: 619c ea26 3ece ca27 c207 21c0 b8c7 d186 .a&..>'....!.... + c638: eb1e cde0 7dd6 eada d178 ee6e 4f7f f57d .....}..x.n..O}. + c648: 6fba 7217 67aa 06f0 98a6 a2c8 7dc5 0a63 .o.r.g.......}c. + c658: 0dae bef9 9804 113f 471b 131c 0b35 1b71 ......?..G..5.q. + c668: 7d84 2304 77f5 28db 2493 40c7 ab7b 32ca .}.#.w.(.$.@{..2 + c678: bebc 15c9 be0a 3c9e 0d4c 9c10 67c4 431d ...........L*~e..).Y + c698: faec 3ad6 6fab 5fcb 5817 4a47 198c 6c44 ...:.o._.XGJ..Dl + c6a8: c908 f3bc e667 6a09 a73b 84ca ae85 bb67 ....g..j;.....g. + c6b8: f82b fe94 f372 3c6e 36f1 5f1d f53a a54f +...r.n<.6._:.O. + c6c8: 82d1 ade6 527f 510e 6c1f 2b3e 688c 9b05 .....R.Q.l>+.h.. + c6d8: bd6b fb41 d9ab 1f83 2179 137e cd19 5be0 k.A.....y!~....[ + +0000c6e8 : + c6e8: f159 feb2 e50a ffa6 dd7b fe2a 141e 00d4 Y.......{.*..... + c6f8: 8052 0003 d130 00f3 7977 ff40 e332 ff9c R...0...wy@.2... + c708: 6e00 01c5 1b67 0090 .n..g... + +0000c710 : + c710: d3ed 5cf5 631a 5812 9cd6 a2f7 f9de 14de ...\.c.X........ + ... + c72c: 0000 1000 .... + +0000c730 : + c730: 648f 01f8 6063 ffbc 09c5 fff8 88d5 0065 .d..c`........e. + c740: 8473 000e 61a0 ffa0 4b14 ffb1 be9d 006a s....a...K....j. + c750: a43e ffad 69f5 ff95 3fee 003d 4f37 006a >....i...?=.7Oj. + c760: 3b70 ff49 6cc2 003c 19c5 007a 483e 004e p;I..l<...z.>HN. + c770: 1ec4 ffdf 03ae ffe3 69c3 fe18 3468 ff09 .........i..h4.. + c780: 498d 00f8 6bec ff73 0c9a 016b 295e 000b .I...ks...k.^).. + c790: 324b fe76 e2e4 ffc9 4478 006a 409a ffb7 K2v.....xDj..@.. + c7a0: 7d51 00a7 5cc5 0099 a68f 0026 9049 ffbe Q}...\....&.I... + c7b0: a6c8 fe8a fbb3 ff42 c4bd ff32 e5c8 00dd ......B...2..... + c7c0: 7a0d 00c4 ff9f 00d3 ea74 00e5 2568 0083 .z......t...h%.. + c7d0: 4c1d 0132 a33b ff4e 4ccf 0030 ce86 ff37 .L2.;.N..L0...7. + c7e0: 3e00 00c9 e7f0 ff4f f233 ff5b 4551 ff32 .>....O.3.[.QE2. + c7f0: 7d4a 01c3 872f 0021 754e ffef 898d 00b4 J}../.!.Nu...... + c800: 09b5 005c 9484 00d6 0b0c 00e1 7d26 ff83 ..\.........&}.. + c810: cfa0 fec3 2d54 00b3 a602 01de d2f0 00c8 ....T-.......... + c820: 496c 001f 770b ff9d c87f 00e9 7710 0050 lI...w.......wP. + c830: db94 0184 e6ae 0001 7ae4 feea b459 ff93 .........z..Y... + c840: e4db ff99 2608 ff21 a514 0097 00c9 0021 .....&!.......!. + c850: 0906 ffa2 e370 ffe5 4a94 0041 597d ffd8 ....p....JA.}Y.. + c860: 1880 fea3 9e0c ff92 dba0 fe8c 3c05 00b3 .............<.. + c870: c048 fea5 48fc ff26 06ad 005b 2d9d 008f H....H&...[..-.. + c880: f22d 0137 53f0 0059 1237 01af ea4d ffea -.7..SY.7...M... + c890: a372 ff5a 513a 00d1 5e56 ff7e f92a 00f9 r.Z.:Q..V^~.*... + c8a0: b454 0091 23fd ffb4 75dd ffbb 753d ffc4 T....#...u..=u.. + c8b0: 5570 005e 3121 ff3c 4ff1 0196 9f10 009e pU^.!1<..O...... + c8c0: 0218 01a1 1759 ff0e bbb4 0075 0486 0085 ....Y.....u..... + c8d0: 61e2 ff73 b5f8 ff20 3bea 01ba 81c2 ffa9 .as... ..;...... + c8e0: 822c 0040 b1e4 0003 5d39 ff35 2128 ff86 ,.@.....9]5.(!.. + c8f0: a990 ff93 bc34 0085 caaa fe5f 408f 002f ....4....._..@/. + c900: db53 01c4 83cd ff74 9c95 003b e5da 00ab S.....t...;..... + c910: dbcd 00b5 5ab8 00ef 0b75 fef1 d66c ff54 .....Z..u...l.T. + c920: a2d9 fe5b 0dad 004a 6fc5 fe61 df3f 0067 ..[...J..oa.?.g. + c930: db8d 0068 95df ffef 748e fe45 6243 00d5 ..h......tE.Cb.. + c940: 4e7c fe62 989e ffd6 e25f 01ac 92e5 ff35 |Nb....._.....5. + c950: eb76 005d 7a92 00e6 ff27 0035 5944 ff8d v.]..z..'.5.DY.. + c960: 3276 00d7 6a79 00ab f02b fe05 996a 008d v2..yj..+...j... + c970: 3d08 01d9 25f2 0042 1ba0 ffe4 0d67 0046 .=...%B.....g.F. + c980: 0689 00d5 2000 00c3 6ace 0016 9927 ff00 ..... ...j..'... + c990: d358 01fd c028 00d4 7b8e 007b 0e10 ff7a X...(....{{...z. + c9a0: a277 ff55 f092 0015 a6d0 0157 6206 ffd5 w.U.......W..b.. + c9b0: 6781 01de a548 ffb6 893c fe7d 764f 003c .g..H...<.}.Ov<. + c9c0: 5e7e 00bf 929d ff70 8463 fe5d 8892 0079 ~^....p.c.]...y. + c9d0: 6293 fe94 8da7 0054 5c4b fe77 4009 ff97 .b....T.K\w..@.. + c9e0: e818 016b 60a3 002e 6c26 ff74 e6a0 005b ..k..`..<...[. + c9f0: 942b fe5d 97b9 00a1 32db 0182 d1da ffe7 +.]......2...... + ca00: ca30 fea1 0a74 004d 2649 01db 1894 fffd 0...t.M.I&...... + ca10: ce51 fed5 717a fff6 2e1f fef5 0c4b ff04 Q...zq......K... + ca20: 5a0f fee0 dccc ff39 3866 ff6c 069a 00e0 .Z....9.f8l..... + ca30: 3410 01d1 c38b 0075 c073 ff5a f321 0092 .4....u.s.Z.!... + ca40: 3275 01ce 4d58 ff5f d22e fe57 3ba7 ff2d u2..XM_...W..;-. + ca50: ecfb 0058 9f53 00f5 23b1 fe8a 8c9b 00b8 ..X.S....#...... + ca60: 20d4 0071 ab2f 00ae 1fcf 01ac a03d ffe4 . q./.......=... + ca70: 81eb ff29 8490 0042 a8ef 0191 bebc 0023 ..)...B.......#. + ca80: 04cf feb2 3932 ffe7 7f34 ffa3 26d2 0020 ....29..4....& . + ca90: b155 fe49 e2b0 0089 a5d1 fed4 cb2b ff38 U.I.........+.8. + caa0: db50 fe3a 4756 00e2 dd93 ffb9 fb39 00d8 P.:.VG......9... + cab0: e2c7 fe35 197d 002d 8a94 00b8 0d2c ff2f ..5.}.-.....,./. + cac0: 573b ffa5 8991 006b 2447 ffcf edd4 00db ;W....k.G$...... + cad0: 012c ff48 7ccb ff05 2079 ff76 c2b8 ff91 ,.H..|..y v..... + cae0: 44b0 008d 59c4 0015 d490 01cf 4266 ffa9 .D...Y......fB.. + +0000caf0 : + caf0: fca7 ff97 8941 ffdc c54b fea7 e5cc 0001 ....A...K....... + cb00: e502 0112 c4e9 007f 147c 0131 35e0 001e ........|.1..5.. + cb10: f35b fee4 a083 008a 4311 009d 2730 0006 [........C..0'.. + cb20: 7055 00e2 ffaa 0092 23ce 0081 835b ff80 Up.......#..[... + cb30: b677 ff25 d42f 00df 53b6 0191 0200 002b w.%./....S....+. + cb40: 9a44 fea5 03e8 ffcf f384 ff2c 538c ffd3 D.........,..S.. + cb50: e13f ff06 2098 ff2a 766e 00c5 b6f1 0002 ?.... *.nv...... + cb60: a18b 00b9 693b ffdb 966a ff44 da0e ff94 ....;i..j.D..... + cb70: 5f9d 0097 3dda ffd1 77f5 fe15 acae 002c ._...=...w....,. + cb80: ae74 0155 5e79 ff1d 80e7 0029 46c5 00fa t.U.y^....)..F.. + cb90: 929f ff91 d450 ffb7 fc02 0028 6f81 ff9c ....P.....(..o.. + cba0: 15ee fe8e c58d ff0c cec7 ffa0 e327 00d6 ............'... + cbb0: 50b5 0099 965d 00ba ac9c fe2e 41bf ff3b .P..]........A;. + cbc0: b153 ff55 01cd 0036 7c80 ff50 a43c 00fb S.U...6..|P.<... + cbd0: a2f2 fe5f a6fe ff1a 0659 ff91 dc09 ff0c .._.....Y....... + cbe0: 54ee 010d e299 0008 df04 fff2 229f fffd .T...........".. + cbf0: c83c ff47 fc01 ff5c 7283 fec9 64d0 00ed <.G...\..r...d.. + cc00: e073 fe25 6a4b ffb3 1e90 ffa0 8486 ffdd s.%.Kj.......... + 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Name: %s.. + d83c: 7550 6b62 7965 0000 6553 7263 7465 0000 Pubkey..Secret.. + d84c: 2020 5047 3a53 6c20 7461 253d 2c64 6c20 GPS: lat=%d, l + d85c: 6e6f 253d 0a64 0000 2020 6150 6874 203a on=%d... Path: + d86c: 2e2e 202e 6e28 746f 6520 7078 6e61 6564 ... (not expande + d87c: 2c64 6120 6464 6920 2066 656e 6465 6465 d, add if needed + d88c: 0a29 0000 2020 6c46 6761 3a73 3020 2578 )... Flags: 0x% + d89c: 3230 0a58 0000 0000 2020 7541 6874 6e65 02X..... Authen + d8ac: 6974 6163 6574 3a64 2520 0a73 0000 0000 ticated: %s..... + d8bc: 2020 614c 7473 5320 6565 206e 7228 6d65 Last Seen (rem + d8cc: 746f 2065 7374 3a29 2520 0a64 0000 0000 ote ts): %d..... + d8dc: 2020 614c 7473 5320 6565 206e 6c28 636f Last Seen (loc + d8ec: 6c61 7420 2973 203a 6425 000a 2020 7953 al ts): %d.. Sy + d8fc: 636e 7420 6d69 7365 6174 706d 203a 6425 nc timestamp: %d + d90c: 000a 0000 2d2d 2d2d 2d2d 2d2d 2d2d 2d2d ....------------ + d91c: 2d2d 2d2d 2d2d 2d2d 2d2d 2d2d 2d2d 2d2d ---------------- + d92c: 2d2d 2d2d 2d2d 2d2d 2d2d 000a ----------.. + +0000d938 : + d938: 338b e987 cdc5 6aea e5c9 baed 15a1 72cd .3.....j.......r + d948: 6843 7461 6e20 646f 0065 0000 6552 6570 Chat node...Repe + d958: 7461 7265 0000 0000 6f52 6d6f 7320 7265 ater....Room ser + d968: 6576 0072 6553 736e 726f 0000 6568 6c6c ver.Sensor..hell + d978: 206f 6874 7265 0065 255b 5d73 2520 3a73 o there.[%s] %s: + d988: 5320 7379 6574 436d 6b6c 253a 0d64 0d0a SystemClk:%d... + d998: 000a 0000 255b 5d73 2520 3a73 4320 6968 ....[%s] %s: Chi + d9a8: 4970 3a44 3025 7838 0a0d 0a0d 0000 0000 pID:%08x........ + d9b8: 255b 5d73 2520 3a73 5320 6e65 6964 676e [%s] %s: Sending + d9c8: 6d20 7365 6173 6567 0d0a 000a 7953 5453 message....SyST + d9d8: 6369 206b 7369 2520 6c6c 0075 255b 5d73 ick is %llu.[%s] + d9e8: 2520 3a73 5320 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snr=%d[dB] raw + dae8: 6e73 3d72 6425 715b 6175 7472 7265 6420 snr=%d[quarter d + daf8: 5d42 0a0d 0000 0000 255b 5d73 2520 3a73 B]......[%s] %s: + db08: 2520 2064 6170 6b63 7465 2073 6f6c 7473 %d packets lost + db18: 0a0d 0000 255b 5d73 2520 3a73 7320 6e79 ....[%s] %s: syn + db28: 5763 726f 3d64 7830 7825 0a0d 0000 0000 cWord=0x%x...... + db38: 255b 5d73 2520 3a73 5320 3158 3632 2078 [%s] %s: SX126x + db48: 7265 6f72 2c72 6d20 7961 6562 6e20 206f error, maybe no + db58: 5053 2049 6f63 6e6e 6365 6974 6e6f 0a0d SPI connection.. + db68: 0000 0000 255b 5d73 2520 3a73 5320 3158 ....[%s] %s: SX1 + db78: 3632 2078 6e69 7473 6c61 656c 0d64 000a 26x installed... + db88: 255b 5d73 2520 3a73 7520 6573 6552 7567 [%s] %s: useRegu + db98: 616c 6f74 4c72 4f44 253d 0d64 000a 0000 latorLDO=%d..... + dba8: 255b 5d73 2520 3a73 4120 6d6c 736f 2074 [%s] %s: Almost + dbb8: 6f64 656e 7320 7465 6974 676e 4c20 526f done setting LoR + dbc8: 0d61 000a 5853 3231 3236 0000 255b 5d73 a...SX1262..[%s] + dbd8: 2520 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7465 7972 tatus=%02x retry + dec8: 253d 0d64 000a 0000 255b 5d73 2520 3a73 =%d.....[%s] %s: + ded8: 5320 4950 5420 6172 736e 6361 6974 6e6f SPI Transaction + dee8: 6520 7272 726f 303a 2578 3230 0d78 000a error:0x%02x... + def8: 7473 7261 2074 7257 7469 4365 6d6f 616d start WriteComma + df08: 646e 0032 255b 5d73 2520 3a73 5720 6972 nd2.[%s] %s: Wri + df18: 6574 6f43 6d6d 6e61 3a64 4320 444d 303d teCommand: CMD=0 + df28: 2578 3230 0d78 000a 6e65 2064 7257 7469 x%02x...end Writ + df38: 4365 6d6f 616d 646e 0032 0000 7473 7261 eCommand2...star + df48: 2074 7257 7469 5265 6765 7369 6574 0072 t WriteRegister. + df58: 6e65 2064 7257 7469 5265 6765 7369 6574 end WriteRegiste + df68: 0072 0000 255b 5d73 2520 3a73 5720 6972 r...[%s] %s: Wri + df78: 6574 6552 6967 7473 7265 203a 4552 3d47 teRegister: REG= + df88: 7830 3025 7832 0a0d 0000 0000 255b 5d73 0x%02x......[%s] + df98: 2520 3a73 4420 7461 4f61 7475 253a 3230 %s: DataOut:%02 + dfa8: 2078 0a0d 0000 0000 x ...... + +0000dfb0 <__clz_tab>: + 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0808 0808 0808 0808 ................ + e0b0: 4f50 4953 0058 0000 002e 0000 POSIX....... + +0000e0bc <_ctype_>: + e0bc: 2000 2020 2020 2020 2020 2828 2828 2028 . ((((( + e0cc: 2020 2020 2020 2020 2020 2020 2020 2020 + e0dc: 8820 1010 1010 1010 1010 1010 1010 1010 ............... + e0ec: 0410 0404 0404 0404 0404 1004 1010 1010 ................ + e0fc: 1010 4141 4141 4141 0101 0101 0101 0101 ..AAAAAA........ + e10c: 0101 0101 0101 0101 0101 0101 1010 1010 ................ + e11c: 1010 4242 4242 4242 0202 0202 0202 0202 ..BBBBBB........ + e12c: 0202 0202 0202 0202 0202 0202 1010 1010 ................ + e13c: 0020 0000 0000 0000 0000 0000 0000 0000 ............... + ... + +0000e1c0 <__sf_fake_stderr>: + ... + +0000e1e0 <__sf_fake_stdin>: + ... + +0000e200 <__sf_fake_stdout>: + ... + e220: 2d23 2b30 0020 0000 6c68 004c 6665 4567 #-0+ ...hlL.efgE + e230: 4746 0000 3130 3332 3534 3736 3938 4241 FG..0123456789AB + e240: 4443 4645 0000 0000 3130 3332 3534 3736 CDEF....01234567 + e250: 3938 6261 6463 6665 0000 0000 89abcdef.... diff --git a/obj/meshcorenortos.map b/obj/meshcorenortos.map new file mode 100644 index 0000000..7f5c8d2 --- /dev/null +++ b/obj/meshcorenortos.map @@ -0,0 +1,4201 @@ +Archive member included to satisfy reference by file (symbol) + +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32/libgcc.a(_lshrdi3.o) + ./User/lib/monocypher/monocypher.o (__lshrdi3) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32/libgcc.a(_ashldi3.o) + ./User/lib/monocypher/monocypher-ed25519.o (__ashldi3) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32/libgcc.a(_divdi3.o) + ./User/sx1262.o (__divdi3) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32/libgcc.a(_udivdi3.o) + ./User/sx1262.o (__udivdi3) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32/libgcc.a(_umoddi3.o) + ./User/lib/monocypher/monocypher.o (__umoddi3) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32/libgcc.a(save-restore.o) + ./User/util/hexdump.o (__riscv_save_12) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32/libgcc.a(_clz.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32/libgcc.a(_divdi3.o) (__clz_tab) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-abort.o) + ./User/lib/cifra/aes.o (abort) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-atoi.o) + ./User/meshcore/packets/encrypted.o (atoi) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-locale.o) + ./User/util/hexdump.o (__locale_ctype_ptr) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-malloc.o) + ./User/sx1262.o (malloc) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-mbtowc_r.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-locale.o) (__ascii_mbtowc) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-memcmp.o) + ./User/meshcore/packets/anonymous.o (memcmp) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-memcpy.o) + ./User/meshcore/packets/advert.o (memcpy) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-memmove.o) + ./User/meshcore/meshframing.o (memmove) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-memset.o) + ./User/meshcore/packets/ack.o (memset) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-nano-freer.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-malloc.o) (_free_r) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-nano-mallocr.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-malloc.o) (_malloc_r) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-printf.o) + ./User/meshcore/packets/advert.o (printf) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-putchar.o) + ./User/meshcore/meshframing.o (putchar) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-puts.o) + ./User/lib/config.o (puts) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-rand.o) + ./User/meshcore/packets/anonymous.o (rand) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-sbrkr.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-nano-mallocr.o) (_sbrk_r) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-signal.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-abort.o) (raise) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-signalr.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-signal.o) (_kill_r) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-snprintf.o) + ./User/util/hexdump.o (snprintf) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-sprintf.o) + ./User/meshcore/packets/encrypted.o (sprintf) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-strcat.o) + ./User/meshcore/packets/group.o (strcat) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-strcmp.o) + ./User/meshcore/packets/encrypted.o (strcmp) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-strcpy.o) + ./User/meshcore/packets/anonymous.o (strcpy) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-strlen.o) + ./User/meshcore/packets/advert.o (strlen) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-strncpy.o) + ./User/meshcore/packets/encrypted.o (strncpy) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-strtol.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-atoi.o) (_strtol_r) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-wbuf.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-puts.o) (__swbuf_r) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-wctomb_r.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-locale.o) (__ascii_wctomb) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-wsetup.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-puts.o) (__swsetup_r) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-ctype_.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-locale.o) (_ctype_) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-fflush.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-wbuf.o) (_fflush_r) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-findfp.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-printf.o) (__sinit) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-fwalk.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-findfp.o) (_fwalk) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-impure.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-fflush.o) (_global_impure_ptr) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-makebuf.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-wsetup.o) (__smakebuf_r) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-mlock.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-nano-freer.o) (__malloc_lock) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-nano-svfprintf.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-snprintf.o) (_svfprintf_r) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-nano-vfprintf.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-printf.o) (_vfprintf_r) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-nano-vfprintf_i.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-nano-svfprintf.o) (_printf_i) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-putc.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-putchar.o) (_putc_r) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-reent.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-sbrkr.o) (errno) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-stdio.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-findfp.o) (__sread) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-writer.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-stdio.o) (_write_r) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-closer.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-stdio.o) (_close_r) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-fstatr.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-makebuf.o) (_fstat_r) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-fvwrite.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-nano-vfprintf.o) (__sfvwrite_r) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-isattyr.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-makebuf.o) (_isatty_r) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-lseekr.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-stdio.o) (_lseek_r) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-memchr.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-nano-svfprintf.o) (memchr) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-nano-reallocr.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-nano-svfprintf.o) (_realloc_r) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-readr.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-stdio.o) (_read_r) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-nano-msizer.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-nano-reallocr.o) (_malloc_usable_size_r) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libnosys.a(close.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-closer.o) (_close) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libnosys.a(fstat.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-fstatr.o) (_fstat) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libnosys.a(getpid.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-signalr.o) (_getpid) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libnosys.a(isatty.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-isattyr.o) (_isatty) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libnosys.a(kill.o) + /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-signalr.o) (_kill) +/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded 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./User/meshcore/meshframing.o +LOAD ./User/meshcore/stats.o +LOAD ./User/lib/telemetry/telemetry.o +LOAD ./User/lib/rtc/rtc.o +LOAD ./User/lib/monocypher/monocypher-ed25519.o +LOAD ./User/lib/monocypher/monocypher.o +LOAD ./User/lib/cifra/aes.o +LOAD ./User/lib/cifra/blockwise.o +LOAD ./User/lib/cifra/chash.o +LOAD ./User/lib/cifra/hmac.o +LOAD ./User/lib/cifra/sha256.o +LOAD ./User/lib/adc/temperature.o +LOAD ./User/lib/base64.o +LOAD ./User/lib/config.o +LOAD ./User/ch32v30x_it.o +LOAD ./User/main.o +LOAD ./User/sx1262.o +LOAD ./User/system_ch32v30x.o +LOAD ./Startup/startup_ch32v30x_D8C.o +LOAD ./Peripheral/src/ch32v30x_adc.o +LOAD ./Peripheral/src/ch32v30x_bkp.o +LOAD ./Peripheral/src/ch32v30x_can.o +LOAD ./Peripheral/src/ch32v30x_crc.o +LOAD ./Peripheral/src/ch32v30x_dac.o +LOAD ./Peripheral/src/ch32v30x_dbgmcu.o +LOAD ./Peripheral/src/ch32v30x_dma.o +LOAD ./Peripheral/src/ch32v30x_dvp.o +LOAD ./Peripheral/src/ch32v30x_eth.o +LOAD ./Peripheral/src/ch32v30x_exti.o +LOAD ./Peripheral/src/ch32v30x_flash.o +LOAD ./Peripheral/src/ch32v30x_fsmc.o +LOAD ./Peripheral/src/ch32v30x_gpio.o +LOAD ./Peripheral/src/ch32v30x_i2c.o +LOAD ./Peripheral/src/ch32v30x_iwdg.o +LOAD ./Peripheral/src/ch32v30x_misc.o +LOAD ./Peripheral/src/ch32v30x_opa.o +LOAD ./Peripheral/src/ch32v30x_pwr.o +LOAD ./Peripheral/src/ch32v30x_rcc.o +LOAD ./Peripheral/src/ch32v30x_rng.o +LOAD ./Peripheral/src/ch32v30x_rtc.o +LOAD ./Peripheral/src/ch32v30x_sdio.o +LOAD ./Peripheral/src/ch32v30x_spi.o +LOAD ./Peripheral/src/ch32v30x_tim.o +LOAD ./Peripheral/src/ch32v30x_usart.o +LOAD ./Peripheral/src/ch32v30x_wwdg.o +LOAD ./Debug/debug.o +LOAD ./Core/core_riscv.o +LOAD /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libm.a +LOAD /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32/libgcc.a +LOAD /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a +LOAD /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libc_nano.a +LOAD /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32/libgcc.a +START GROUP +LOAD /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32/libgcc.a +LOAD /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libc_nano.a +LOAD /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libnosys.a +END GROUP +START GROUP +LOAD /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32/libgcc.a +LOAD /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libc_nano.a +LOAD /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libnosys.a +END GROUP + 0x0000000000000800 __stack_size = 0x800 + [!provide] PROVIDE (_stack_size = __stack_size) + +.init 0x0000000000000000 0x4 + 0x0000000000000000 _sinit = . + 0x0000000000000000 . = ALIGN (0x4) + *(SORT_NONE(.init)) + .init 0x0000000000000000 0x4 ./Startup/startup_ch32v30x_D8C.o + 0x0000000000000000 _start + 0x0000000000000004 . = ALIGN (0x4) + 0x0000000000000004 _einit = . + +.vector 0x0000000000000004 0x1bc + *(.vector) + .vector 0x0000000000000004 0x1a0 ./Startup/startup_ch32v30x_D8C.o + 0x00000000000001c0 . = ALIGN (0x40) + *fill* 0x00000000000001a4 0x1c + +.text 0x00000000000001c0 0xe09c + 0x00000000000001c0 . = ALIGN (0x4) + *(.text) + .text 0x00000000000001c0 0x60 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32/libgcc.a(save-restore.o) + 0x00000000000001c0 __riscv_save_12 + 0x00000000000001c8 __riscv_save_8 + 0x00000000000001c8 __riscv_save_11 + 0x00000000000001c8 __riscv_save_9 + 0x00000000000001c8 __riscv_save_10 + 0x00000000000001d6 __riscv_save_7 + 0x00000000000001d6 __riscv_save_4 + 0x00000000000001d6 __riscv_save_6 + 0x00000000000001d6 __riscv_save_5 + 0x00000000000001f0 __riscv_save_1 + 0x00000000000001f0 __riscv_save_3 + 0x00000000000001f0 __riscv_save_2 + 0x00000000000001f0 __riscv_save_0 + 0x00000000000001fc __riscv_restore_12 + 0x0000000000000200 __riscv_restore_10 + 0x0000000000000200 __riscv_restore_11 + 0x0000000000000200 __riscv_restore_8 + 0x0000000000000200 __riscv_restore_9 + 0x000000000000020a __riscv_restore_5 + 0x000000000000020a __riscv_restore_6 + 0x000000000000020a __riscv_restore_4 + 0x000000000000020a __riscv_restore_7 + 0x0000000000000214 __riscv_restore_3 + 0x0000000000000214 __riscv_restore_2 + 0x0000000000000214 __riscv_restore_0 + 0x0000000000000214 __riscv_restore_1 + .text 0x0000000000000220 0xa8 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-memset.o) + 0x0000000000000220 memset + .text 0x00000000000002c8 0x11a /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-strcmp.o) + 0x00000000000002c8 strcmp + *(.text.*) + .text.hexdump 0x00000000000003e2 0xbc ./User/util/hexdump.o + 0x00000000000003e2 hexdump + .text.hexdump_compact + 0x000000000000049e 0x4e ./User/util/hexdump.o + 0x000000000000049e hexdump_compact + .text.sendDiscreteAck + 0x00000000000004ec 0x52 ./User/meshcore/packets/ack.o + 0x00000000000004ec sendDiscreteAck + .text.ed25519_sign_ad + 0x000000000000053e 0x40 ./User/meshcore/packets/advert.o + 0x000000000000053e ed25519_sign_ad + .text.ed25519_verify_ad + 0x000000000000057e 0x50 ./User/meshcore/packets/advert.o + 0x000000000000057e ed25519_verify_ad + .text.sendAdvert + 0x00000000000005ce 0xe4 ./User/meshcore/packets/advert.o + 0x00000000000005ce sendAdvert + .text.saveAdvert + 0x00000000000006b2 0x8e ./User/meshcore/packets/advert.o + 0x00000000000006b2 saveAdvert + .text.printAdvertisement + 0x0000000000000740 0xa8 ./User/meshcore/packets/advert.o + 0x0000000000000740 printAdvertisement + .text.decodeAdvertisement + 0x00000000000007e8 0x170 ./User/meshcore/packets/advert.o + 0x00000000000007e8 decodeAdvertisement + .text.strnlen 0x0000000000000958 0x18 ./User/meshcore/packets/anonymous.o + 0x0000000000000958 strnlen + .text.printAnonRequest + 0x0000000000000970 0x16c ./User/meshcore/packets/anonymous.o + 0x0000000000000970 printAnonRequest + .text.decodeAnonReq + 0x0000000000000adc 0x26e ./User/meshcore/packets/anonymous.o + 0x0000000000000adc decodeAnonReq + .text.sendDiscoverResponse + 0x0000000000000d4a 0x62 ./User/meshcore/packets/control.o + 0x0000000000000d4a sendDiscoverResponse + .text.printDiscoverRequest + 0x0000000000000dac 0x4e ./User/meshcore/packets/control.o + 0x0000000000000dac printDiscoverRequest + .text.printDiscoverResponse + 0x0000000000000dfa 0x62 ./User/meshcore/packets/control.o + 0x0000000000000dfa printDiscoverResponse + .text.decodeControlFrame + 0x0000000000000e5c 0xfe ./User/meshcore/packets/control.o + 0x0000000000000e5c decodeControlFrame + .text.parse_coord_micro + 0x0000000000000f5a 0x9c ./User/meshcore/packets/encrypted.o + .text.sendEncryptedFrame + 0x0000000000000ff6 0xba ./User/meshcore/packets/encrypted.o + 0x0000000000000ff6 sendEncryptedFrame + .text.sendEncryptedTextMessage + 0x00000000000010b0 0x92 ./User/meshcore/packets/encrypted.o + 0x00000000000010b0 sendEncryptedTextMessage + .text.sendEncryptedResponse + 0x0000000000001142 0x2e ./User/meshcore/packets/encrypted.o + 0x0000000000001142 sendEncryptedResponse + .text.sendEncryptedPathPayload + 0x0000000000001170 0xae ./User/meshcore/packets/encrypted.o + 0x0000000000001170 sendEncryptedPathPayload + .text.printRequest + 0x000000000000121e 0x50 ./User/meshcore/packets/encrypted.o + 0x000000000000121e printRequest + .text.printResponse + 0x000000000000126e 0x42 ./User/meshcore/packets/encrypted.o + 0x000000000000126e printResponse + .text.sendPathBack + 0x00000000000012b0 0x2c ./User/meshcore/packets/encrypted.o + 0x00000000000012b0 sendPathBack + .text.processCommand + 0x00000000000012dc 0x58c ./User/meshcore/packets/encrypted.o + 0x00000000000012dc processCommand + .text.parseEncryptedPayload + 0x0000000000001868 0x448 ./User/meshcore/packets/encrypted.o + 0x0000000000001868 parseEncryptedPayload + .text.decodeEncryptedPayload + 0x0000000000001cb0 0x148 ./User/meshcore/packets/encrypted.o + 0x0000000000001cb0 decodeEncryptedPayload + .text.sendGroupMessage + 0x0000000000001df8 0xb4 ./User/meshcore/packets/group.o + 0x0000000000001df8 sendGroupMessage + .text.makeSendGroupMessage + 0x0000000000001eac 0x40 ./User/meshcore/packets/group.o + 0x0000000000001eac makeSendGroupMessage + .text.decodeGroupMessage + 0x0000000000001eec 0xf8 ./User/meshcore/packets/group.o + 0x0000000000001eec decodeGroupMessage + .text.processFrame + 0x0000000000001fe4 0xfa ./User/meshcore/meshcore.o + 0x0000000000001fe4 processFrame + .text.ReadFrame + 0x00000000000020de 0x19c ./User/meshcore/meshframing.o + 0x00000000000020de ReadFrame + .text.printframeHeader + 0x000000000000227a 0x1ba ./User/meshcore/meshframing.o + 0x000000000000227a printframeHeader + .text.getFrameHash + 0x0000000000002434 0x2a ./User/meshcore/meshframing.o + 0x0000000000002434 getFrameHash + .text.addToNotReTX + 0x000000000000245e 0x3c ./User/meshcore/meshframing.o + 0x000000000000245e addToNotReTX + .text.LoRaTransmit + 0x000000000000249a 0x26e ./User/meshcore/meshframing.o + 0x000000000000249a LoRaTransmit + .text.retransmitFrame + 0x0000000000002708 0xb4 ./User/meshcore/meshframing.o + 0x0000000000002708 retransmitFrame + .text.encrypt_then_mac + 0x00000000000027bc 0x9a ./User/meshcore/meshframing.o + 0x00000000000027bc encrypt_then_mac + .text.mac_then_decrypt + 0x0000000000002856 0x52 ./User/meshcore/meshframing.o + 0x0000000000002856 mac_then_decrypt + .text.RTC_NVIC_Config + 0x00000000000028a8 0x1c ./User/lib/rtc/rtc.o + 0x00000000000028a8 RTC_NVIC_Config + .text.Is_Leap_Year + 0x00000000000028c4 0x26 ./User/lib/rtc/rtc.o + 0x00000000000028c4 Is_Leap_Year + .text.RTC_Set 0x00000000000028ea 0xdc ./User/lib/rtc/rtc.o + 0x00000000000028ea RTC_Set + .text.RTC_Set_From_BuildTime + 0x00000000000029c6 0x5e ./User/lib/rtc/rtc.o + 0x00000000000029c6 RTC_Set_From_BuildTime + .text.RTC_Get_Week + 0x0000000000002a24 0x4e ./User/lib/rtc/rtc.o + 0x0000000000002a24 RTC_Get_Week + .text.RTC_Get 0x0000000000002a72 0xf8 ./User/lib/rtc/rtc.o + 0x0000000000002a72 RTC_Get + .text.RTC_Init + 0x0000000000002b6a 0xbe ./User/lib/rtc/rtc.o + 0x0000000000002b6a RTC_Init + .text.load64_be_buf + 0x0000000000002c28 0x58 ./User/lib/monocypher/monocypher-ed25519.o + .text.sha512_compress + 0x0000000000002c80 0x5a4 ./User/lib/monocypher/monocypher-ed25519.o + .text.sha512_set_input + 0x0000000000003224 0x32 ./User/lib/monocypher/monocypher-ed25519.o + .text.crypto_sha512_update.part.1 + 0x0000000000003256 0x1ba ./User/lib/monocypher/monocypher-ed25519.o + .text.crypto_sha512_init + 0x0000000000003410 0xb0 ./User/lib/monocypher/monocypher-ed25519.o + 0x0000000000003410 crypto_sha512_init + .text.crypto_sha512_update + 0x00000000000034c0 0x10 ./User/lib/monocypher/monocypher-ed25519.o + 0x00000000000034c0 crypto_sha512_update + .text.crypto_sha512_final + 0x00000000000034d0 0x112 ./User/lib/monocypher/monocypher-ed25519.o + 0x00000000000034d0 crypto_sha512_final + .text.hash_reduce.constprop.2 + 0x00000000000035e2 0x66 ./User/lib/monocypher/monocypher-ed25519.o + .text.crypto_sha512 + 0x0000000000003648 0x2a ./User/lib/monocypher/monocypher-ed25519.o + 0x0000000000003648 crypto_sha512 + .text.ed25519_dom_sign + 0x0000000000003672 0x98 ./User/lib/monocypher/monocypher-ed25519.o + .text.crypto_ed25519_key_pair + 0x000000000000370a 0x8a ./User/lib/monocypher/monocypher-ed25519.o + 0x000000000000370a crypto_ed25519_key_pair + .text.crypto_ed25519_sign + 0x0000000000003794 0x14 ./User/lib/monocypher/monocypher-ed25519.o + 0x0000000000003794 crypto_ed25519_sign + .text.crypto_ed25519_check + 0x00000000000037a8 0x30 ./User/lib/monocypher/monocypher-ed25519.o + 0x00000000000037a8 crypto_ed25519_check + .text.load24_le + 0x00000000000037d8 0x10 ./User/lib/monocypher/monocypher.o + .text.load32_le + 0x00000000000037e8 0x16 ./User/lib/monocypher/monocypher.o + .text.load64_le + 0x00000000000037fe 0x1c ./User/lib/monocypher/monocypher.o + .text.store32_le + 0x000000000000381a 0x14 ./User/lib/monocypher/monocypher.o + .text.load32_le_buf + 0x000000000000382e 0x2c ./User/lib/monocypher/monocypher.o + .text.store32_le_buf + 0x000000000000385a 0x26 ./User/lib/monocypher/monocypher.o + .text.x16 0x0000000000003880 0x40 ./User/lib/monocypher/monocypher.o + .text.x32 0x00000000000038c0 0x24 ./User/lib/monocypher/monocypher.o + .text.fe_0 0x00000000000038e4 0x10 ./User/lib/monocypher/monocypher.o + .text.fe_1 0x00000000000038f4 0x18 ./User/lib/monocypher/monocypher.o + .text.fe_copy 0x000000000000390c 0x1a ./User/lib/monocypher/monocypher.o + .text.fe_neg 0x0000000000003926 0x1e ./User/lib/monocypher/monocypher.o + .text.fe_add 0x0000000000003944 0x26 ./User/lib/monocypher/monocypher.o + .text.fe_sub 0x000000000000396a 0x28 ./User/lib/monocypher/monocypher.o + .text.fe_cswap + 0x0000000000003992 0xd4 ./User/lib/monocypher/monocypher.o + .text.fe_ccopy + 0x0000000000003a66 0x98 ./User/lib/monocypher/monocypher.o + .text.fe_frombytes_mask + 0x0000000000003afe 0x258 ./User/lib/monocypher/monocypher.o + .text.fe_mul_small + 0x0000000000003d56 0x2f2 ./User/lib/monocypher/monocypher.o + .text.fe_mul 0x0000000000004048 0xa9c ./User/lib/monocypher/monocypher.o + .text.fe_sq 0x0000000000004ae4 0x676 ./User/lib/monocypher/monocypher.o + .text.scalar_bit + 0x000000000000515a 0x1a ./User/lib/monocypher/monocypher.o + .text.multiply + 0x0000000000005174 0x4a ./User/lib/monocypher/monocypher.o + .text.is_above_l + 0x00000000000051be 0x36 ./User/lib/monocypher/monocypher.o + .text.remove_l + 0x00000000000051f4 0x62 ./User/lib/monocypher/monocypher.o + .text.ge_zero 0x0000000000005256 0x26 ./User/lib/monocypher/monocypher.o + .text.ge_cache + 0x000000000000527c 0x42 ./User/lib/monocypher/monocypher.o + .text.ge_add 0x00000000000052be 0xc2 ./User/lib/monocypher/monocypher.o + .text.ge_madd 0x0000000000005380 0xb6 ./User/lib/monocypher/monocypher.o + .text.ge_double + 0x0000000000005436 0xaa ./User/lib/monocypher/monocypher.o + .text.slide_init + 0x00000000000054e0 0x28 ./User/lib/monocypher/monocypher.o + .text.slide_step + 0x0000000000005508 0xc4 ./User/lib/monocypher/monocypher.o + .text.lookup_add + 0x00000000000055cc 0xdc ./User/lib/monocypher/monocypher.o + .text.crypto_verify32 + 0x00000000000056a8 0x14 ./User/lib/monocypher/monocypher.o + 0x00000000000056a8 crypto_verify32 + .text.crypto_wipe + 0x00000000000056bc 0x14 ./User/lib/monocypher/monocypher.o + 0x00000000000056bc crypto_wipe + .text.fe_tobytes + 0x00000000000056d0 0x116 ./User/lib/monocypher/monocypher.o + .text.fe_isequal + 0x00000000000057e6 0x40 ./User/lib/monocypher/monocypher.o + .text.invsqrt 0x0000000000005826 0x1e8 ./User/lib/monocypher/monocypher.o + .text.fe_invert + 0x0000000000005a0e 0x3a ./User/lib/monocypher/monocypher.o + .text.scalarmult + 0x0000000000005a48 0x18a ./User/lib/monocypher/monocypher.o + .text.mod_l 0x0000000000005bd2 0x11c ./User/lib/monocypher/monocypher.o + .text.fe_isodd + 0x0000000000005cee 0x24 ./User/lib/monocypher/monocypher.o + .text.ge_frombytes_neg_vartime + 0x0000000000005d12 0x96 ./User/lib/monocypher/monocypher.o + .text.ge_tobytes + 0x0000000000005da8 0x6c ./User/lib/monocypher/monocypher.o + .text.crypto_eddsa_trim_scalar + 0x0000000000005e14 0x2c ./User/lib/monocypher/monocypher.o + 0x0000000000005e14 crypto_eddsa_trim_scalar + .text.crypto_x25519 + 0x0000000000005e40 0x2e ./User/lib/monocypher/monocypher.o + 0x0000000000005e40 crypto_x25519 + .text.crypto_eddsa_reduce + 0x0000000000005e6e 0x28 ./User/lib/monocypher/monocypher.o + 0x0000000000005e6e crypto_eddsa_reduce + .text.crypto_eddsa_mul_add + 0x0000000000005e96 0x70 ./User/lib/monocypher/monocypher.o + 0x0000000000005e96 crypto_eddsa_mul_add + .text.ge_scalarmult_base + 0x0000000000005f06 0xd6 ./User/lib/monocypher/monocypher.o + .text.crypto_eddsa_check_equation + 0x0000000000005fdc 0x1ba ./User/lib/monocypher/monocypher.o + 0x0000000000005fdc crypto_eddsa_check_equation + .text.crypto_eddsa_scalarbase + 0x0000000000006196 0x26 ./User/lib/monocypher/monocypher.o + 0x0000000000006196 crypto_eddsa_scalarbase + .text.crypto_eddsa_to_x25519 + 0x00000000000061bc 0x5e ./User/lib/monocypher/monocypher.o + 0x00000000000061bc crypto_eddsa_to_x25519 + .text.read32_be + 0x000000000000621a 0x16 ./User/lib/cifra/aes.o + .text.write32_be + 0x0000000000006230 0x16 ./User/lib/cifra/aes.o + .text.add_round_key + 0x0000000000006246 0x22 ./User/lib/cifra/aes.o + .text.shift_rows + 0x0000000000006268 0x8a ./User/lib/cifra/aes.o + .text.gf_poly_mul2 + 0x00000000000062f2 0x24 ./User/lib/cifra/aes.o + .text.mix_column + 0x0000000000006316 0x32 ./User/lib/cifra/aes.o + .text.inv_shift_rows + 0x0000000000006348 0x8a ./User/lib/cifra/aes.o + .text.inv_mix_column + 0x00000000000063d2 0x50 ./User/lib/cifra/aes.o + .text.sub_word + 0x0000000000006422 0xda ./User/lib/cifra/aes.o + .text.aes_schedule + 0x00000000000064fc 0xa2 ./User/lib/cifra/aes.o + .text.sub_block + 0x000000000000659e 0x3c ./User/lib/cifra/aes.o + .text.cf_aes_encrypt + 0x00000000000065da 0xd8 ./User/lib/cifra/aes.o + 0x00000000000065da cf_aes_encrypt + .text.inv_sub_block + 0x00000000000066b2 0x3c ./User/lib/cifra/aes.o + .text.cf_aes_decrypt + 0x00000000000066ee 0xe8 ./User/lib/cifra/aes.o + 0x00000000000066ee cf_aes_decrypt + .text.cf_aes_init + 0x00000000000067d6 0x50 ./User/lib/cifra/aes.o + 0x00000000000067d6 cf_aes_init + .text.cf_aes_finish + 0x0000000000006826 0x16 ./User/lib/cifra/aes.o + 0x0000000000006826 cf_aes_finish + .text.aes_encrypt_ecb + 0x000000000000683c 0x44 ./User/lib/cifra/aes.o + 0x000000000000683c aes_encrypt_ecb + .text.aes_decrypt_ecb + 0x0000000000006880 0x44 ./User/lib/cifra/aes.o + 0x0000000000006880 aes_decrypt_ecb + .text.cf_blockwise_accumulate_final + 0x00000000000068c4 0xbc ./User/lib/cifra/blockwise.o + 0x00000000000068c4 cf_blockwise_accumulate_final + .text.cf_blockwise_accumulate + 0x0000000000006980 0x10 ./User/lib/cifra/blockwise.o + 0x0000000000006980 cf_blockwise_accumulate + .text.cf_blockwise_acc_byte + 0x0000000000006990 0x64 ./User/lib/cifra/blockwise.o + 0x0000000000006990 cf_blockwise_acc_byte + .text.cf_blockwise_acc_pad + 0x00000000000069f4 0x9a ./User/lib/cifra/blockwise.o + 0x00000000000069f4 cf_blockwise_acc_pad + .text.cf_hash 0x0000000000006a8e 0x44 ./User/lib/cifra/chash.o + 0x0000000000006a8e cf_hash + .text.cf_hmac_init + 0x0000000000006ad2 0xe8 ./User/lib/cifra/hmac.o + 0x0000000000006ad2 cf_hmac_init + .text.cf_hmac_update + 0x0000000000006bba 0x18 ./User/lib/cifra/hmac.o + 0x0000000000006bba cf_hmac_update + .text.cf_hmac_finish + 0x0000000000006bd2 0x4c ./User/lib/cifra/hmac.o + 0x0000000000006bd2 cf_hmac_finish + .text.hmac_sha256 + 0x0000000000006c1e 0x3c ./User/lib/cifra/hmac.o + 0x0000000000006c1e hmac_sha256 + .text.write32_be + 0x0000000000006c5a 0x16 ./User/lib/cifra/sha256.o + .text.sha256_update_block + 0x0000000000006c70 0x20c ./User/lib/cifra/sha256.o + .text.cf_sha256_init + 0x0000000000006e7c 0x68 ./User/lib/cifra/sha256.o + 0x0000000000006e7c cf_sha256_init + .text.cf_sha256_update + 0x0000000000006ee4 0x26 ./User/lib/cifra/sha256.o + 0x0000000000006ee4 cf_sha256_update + .text.cf_sha256_digest_final + 0x0000000000006f0a 0x102 ./User/lib/cifra/sha256.o + 0x0000000000006f0a cf_sha256_digest_final + .text.cf_sha256_digest + 0x000000000000700c 0x22 ./User/lib/cifra/sha256.o + 0x000000000000700c cf_sha256_digest + .text.ADC_Function_Init + 0x000000000000702e 0xae ./User/lib/adc/temperature.o + 0x000000000000702e ADC_Function_Init + .text.Get_ADC_Val + 0x00000000000070dc 0x3a ./User/lib/adc/temperature.o + 0x00000000000070dc Get_ADC_Val + .text.Get_ADC_Average + 0x0000000000007116 0x38 ./User/lib/adc/temperature.o + 0x0000000000007116 Get_ADC_Average + .text.Get_ConversionVal + 0x000000000000714e 0x2a ./User/lib/adc/temperature.o + 0x000000000000714e Get_ConversionVal + .text.TempSensor_Volt_To_Temper_x10 + 0x0000000000007178 0x30 ./User/lib/adc/temperature.o + 0x0000000000007178 TempSensor_Volt_To_Temper_x10 + .text.getDeciTemperature + 0x00000000000071a8 0x2c ./User/lib/adc/temperature.o + 0x00000000000071a8 getDeciTemperature + .text.getVoltage + 0x00000000000071d4 0x24 ./User/lib/adc/temperature.o + 0x00000000000071d4 getVoltage + .text.int24_to_bytes + 0x00000000000071f8 0x1a ./User/lib/adc/temperature.o + 0x00000000000071f8 int24_to_bytes + .text.encode_gps + 0x0000000000007212 0x3e ./User/lib/adc/temperature.o + 0x0000000000007212 encode_gps + .text.getNextNode + 0x0000000000007250 0x42 ./User/lib/config.o + 0x0000000000007250 getNextNode + .text.getNode 0x0000000000007292 0x38 ./User/lib/config.o + 0x0000000000007292 getNode + .text.getNodePrefix + 0x00000000000072ca 0x3c ./User/lib/config.o + 0x00000000000072ca getNodePrefix + .text.getChannel + 0x0000000000007306 0x44 ./User/lib/config.o + 0x0000000000007306 getChannel + .text.addChannel + 0x000000000000734a 0xc6 ./User/lib/config.o + 0x000000000000734a addChannel + .text.printNodeDB + 0x0000000000007410 0x126 ./User/lib/config.o + 0x0000000000007410 printNodeDB + .text.getStringRole + 0x0000000000007536 0x24 ./User/lib/config.o + 0x0000000000007536 getStringRole + .text.populateDefaults + 0x000000000000755a 0x100 ./User/lib/config.o + 0x000000000000755a populateDefaults + .text.LoraApply + 0x000000000000765a 0x86 ./User/lib/config.o + 0x000000000000765a LoraApply + .text.NMI_Handler + 0x00000000000076e0 0x2 ./User/ch32v30x_it.o + 0x00000000000076e0 NMI_Handler + .text.HardFault_Handler + 0x00000000000076e2 0x10 ./User/ch32v30x_it.o + 0x00000000000076e2 HardFault_Handler + .text.startup.main + 0x00000000000076f2 0x2f2 ./User/main.o + 0x00000000000076f2 main + .text.LoRaError + 0x00000000000079e4 0x3c ./User/sx1262.o + 0x00000000000079e4 LoRaError + .text.LoRaInit + 0x0000000000007a20 0x10a ./User/sx1262.o + 0x0000000000007a20 LoRaInit + .text.spi_read_byte + 0x0000000000007b2a 0x7a ./User/sx1262.o + 0x0000000000007b2a spi_read_byte + .text.spi_write_byte + 0x0000000000007ba4 0x12 ./User/sx1262.o + 0x0000000000007ba4 spi_write_byte + .text.LoRaDebugPrint + 0x0000000000007bb6 0x6 ./User/sx1262.o + 0x0000000000007bb6 LoRaDebugPrint + .text.GetPacketLost + 0x0000000000007bbc 0x6 ./User/sx1262.o + 0x0000000000007bbc GetPacketLost + .text.WaitForIdle + 0x0000000000007bc2 0x84 ./User/sx1262.o + 0x0000000000007bc2 WaitForIdle + .text.ResetLora + 0x0000000000007c46 0x66 ./User/sx1262.o + 0x0000000000007c46 ResetLora + .text.WaitForIdleBegin + 0x0000000000007cac 0x5a ./User/sx1262.o + 0x0000000000007cac WaitForIdleBegin + .text.WriteRegister + 0x0000000000007d06 0xa6 ./User/sx1262.o + 0x0000000000007d06 WriteRegister + .text.ReadRegister + 0x0000000000007dac 0xee ./User/sx1262.o + 0x0000000000007dac ReadRegister + .text.FixInvertedIQ + 0x0000000000007e9a 0x40 ./User/sx1262.o + 0x0000000000007e9a FixInvertedIQ + .text.WriteCommand2 + 0x0000000000007eda 0xa6 ./User/sx1262.o + 0x0000000000007eda WriteCommand2 + .text.WriteCommand + 0x0000000000007f80 0x86 ./User/sx1262.o + 0x0000000000007f80 WriteCommand + .text.SetStandby + 0x0000000000008006 0x1c ./User/sx1262.o + 0x0000000000008006 SetStandby + .text.SetDio3AsTcxoCtrl + 0x0000000000008022 0x8a ./User/sx1262.o + 0x0000000000008022 SetDio3AsTcxoCtrl + .text.Calibrate + 0x00000000000080ac 0x1c ./User/sx1262.o + 0x00000000000080ac Calibrate + .text.SetDio2AsRfSwitchCtrl + 0x00000000000080c8 0x1c ./User/sx1262.o + 0x00000000000080c8 SetDio2AsRfSwitchCtrl + .text.CalibrateImage + 0x00000000000080e4 0x7c ./User/sx1262.o + 0x00000000000080e4 CalibrateImage + .text.SetRfFrequency + 0x0000000000008160 0x4e ./User/sx1262.o + 0x0000000000008160 SetRfFrequency + .text.SetRegulatorMode + 0x00000000000081ae 0x1c ./User/sx1262.o + 0x00000000000081ae SetRegulatorMode + .text.SetBufferBaseAddress + 0x00000000000081ca 0x1c ./User/sx1262.o + 0x00000000000081ca SetBufferBaseAddress + .text.SetPowerConfig + 0x00000000000081e6 0x34 ./User/sx1262.o + 0x00000000000081e6 SetPowerConfig + .text.SetPaConfig + 0x000000000000821a 0x20 ./User/sx1262.o + 0x000000000000821a SetPaConfig + .text.LoRaBegin + 0x000000000000823a 0x12e ./User/sx1262.o + 0x000000000000823a LoRaBegin + .text.SetDioIrqParams + 0x0000000000008368 0x3e ./User/sx1262.o + 0x0000000000008368 SetDioIrqParams + .text.SetStopRxTimerOnPreambleDetect + 0x00000000000083a6 0x46 ./User/sx1262.o + 0x00000000000083a6 SetStopRxTimerOnPreambleDetect + .text.SetLoRaSymbNumTimeout + 0x00000000000083ec 0x1c ./User/sx1262.o + 0x00000000000083ec SetLoRaSymbNumTimeout + .text.SetPacketType + 0x0000000000008408 0x1c ./User/sx1262.o + 0x0000000000008408 SetPacketType + .text.SetModulationParams + 0x0000000000008424 0x20 ./User/sx1262.o + 0x0000000000008424 SetModulationParams + .text.ClearIrqStatus + 0x0000000000008444 0x20 ./User/sx1262.o + 0x0000000000008444 ClearIrqStatus + .text.ReadCommand + 0x0000000000008464 0x8a ./User/sx1262.o + 0x0000000000008464 ReadCommand + .text.GetPacketStatus + 0x00000000000084ee 0x42 ./User/sx1262.o + 0x00000000000084ee GetPacketStatus + .text.GetStatus + 0x0000000000008530 0x1c ./User/sx1262.o + 0x0000000000008530 GetStatus + .text.SetRx 0x000000000000854c 0xa0 ./User/sx1262.o + 0x000000000000854c SetRx + .text.LoRaConfig + 0x00000000000085ec 0xb0 ./User/sx1262.o + 0x00000000000085ec LoRaConfig + .text.SetTx 0x000000000000869c 0x118 ./User/sx1262.o + 0x000000000000869c SetTx + .text.GetIrqStatus + 0x00000000000087b4 0x1e ./User/sx1262.o + 0x00000000000087b4 GetIrqStatus + .text.GetRxBufferStatus + 0x00000000000087d2 0x22 ./User/sx1262.o + 0x00000000000087d2 GetRxBufferStatus + .text.SystemInit + 0x00000000000087f4 0xfa ./User/system_ch32v30x.o + 0x00000000000087f4 SystemInit + .text.SystemCoreClockUpdate + 0x00000000000088ee 0x12e ./User/system_ch32v30x.o + 0x00000000000088ee SystemCoreClockUpdate + .text.vector_handler + 0x0000000000008a1c 0x2 ./Startup/startup_ch32v30x_D8C.o + 0x0000000000008a1c EXTI2_IRQHandler + 0x0000000000008a1c TIM8_TRG_COM_IRQHandler + 0x0000000000008a1c TIM8_CC_IRQHandler + 0x0000000000008a1c UART8_IRQHandler + 0x0000000000008a1c TIM1_CC_IRQHandler + 0x0000000000008a1c TIM6_IRQHandler + 0x0000000000008a1c SysTick_Handler + 0x0000000000008a1c PVD_IRQHandler + 0x0000000000008a1c SDIO_IRQHandler + 0x0000000000008a1c TIM9_BRK_IRQHandler + 0x0000000000008a1c DMA2_Channel8_IRQHandler + 0x0000000000008a1c CAN2_RX1_IRQHandler + 0x0000000000008a1c EXTI3_IRQHandler + 0x0000000000008a1c USBHS_IRQHandler + 0x0000000000008a1c DMA2_Channel9_IRQHandler + 0x0000000000008a1c TIM10_CC_IRQHandler + 0x0000000000008a1c USBFS_IRQHandler + 0x0000000000008a1c EXTI0_IRQHandler + 0x0000000000008a1c I2C2_EV_IRQHandler + 0x0000000000008a1c TIM10_TRG_COM_IRQHandler + 0x0000000000008a1c CAN2_SCE_IRQHandler + 0x0000000000008a1c ADC1_2_IRQHandler + 0x0000000000008a1c Break_Point_Handler + 0x0000000000008a1c SPI1_IRQHandler + 0x0000000000008a1c TAMPER_IRQHandler + 0x0000000000008a1c CAN2_RX0_IRQHandler + 0x0000000000008a1c TIM8_UP_IRQHandler + 0x0000000000008a1c Ecall_M_Mode_Handler + 0x0000000000008a1c DMA2_Channel2_IRQHandler + 0x0000000000008a1c DMA1_Channel4_IRQHandler + 0x0000000000008a1c TIM9_UP_IRQHandler + 0x0000000000008a1c USART3_IRQHandler + 0x0000000000008a1c RTC_IRQHandler + 0x0000000000008a1c DMA1_Channel7_IRQHandler + 0x0000000000008a1c CAN1_RX1_IRQHandler + 0x0000000000008a1c DVP_IRQHandler + 0x0000000000008a1c UART5_IRQHandler + 0x0000000000008a1c TIM4_IRQHandler + 0x0000000000008a1c DMA2_Channel1_IRQHandler + 0x0000000000008a1c I2C1_EV_IRQHandler + 0x0000000000008a1c DMA1_Channel6_IRQHandler + 0x0000000000008a1c UART4_IRQHandler + 0x0000000000008a1c DMA2_Channel4_IRQHandler + 0x0000000000008a1c TIM3_IRQHandler + 0x0000000000008a1c RCC_IRQHandler + 0x0000000000008a1c TIM1_TRG_COM_IRQHandler + 0x0000000000008a1c DMA1_Channel1_IRQHandler + 0x0000000000008a1c DMA2_Channel7_IRQHandler + 0x0000000000008a1c EXTI15_10_IRQHandler + 0x0000000000008a1c TIM7_IRQHandler + 0x0000000000008a1c CAN2_TX_IRQHandler + 0x0000000000008a1c TIM5_IRQHandler + 0x0000000000008a1c EXTI9_5_IRQHandler + 0x0000000000008a1c ETH_WKUP_IRQHandler + 0x0000000000008a1c SPI2_IRQHandler + 0x0000000000008a1c TIM10_BRK_IRQHandler + 0x0000000000008a1c TIM9_CC_IRQHandler + 0x0000000000008a1c DMA2_Channel5_IRQHandler + 0x0000000000008a1c DMA1_Channel5_IRQHandler + 0x0000000000008a1c EXTI4_IRQHandler + 0x0000000000008a1c USB_LP_CAN1_RX0_IRQHandler + 0x0000000000008a1c RNG_IRQHandler + 0x0000000000008a1c USB_HP_CAN1_TX_IRQHandler + 0x0000000000008a1c DMA1_Channel3_IRQHandler + 0x0000000000008a1c ETH_IRQHandler + 0x0000000000008a1c TIM1_UP_IRQHandler + 0x0000000000008a1c WWDG_IRQHandler + 0x0000000000008a1c USBHSWakeup_IRQHandler + 0x0000000000008a1c DMA2_Channel11_IRQHandler + 0x0000000000008a1c Ecall_U_Mode_Handler + 0x0000000000008a1c DMA2_Channel6_IRQHandler + 0x0000000000008a1c TIM2_IRQHandler + 0x0000000000008a1c SW_Handler + 0x0000000000008a1c TIM1_BRK_IRQHandler + 0x0000000000008a1c DMA2_Channel10_IRQHandler + 0x0000000000008a1c EXTI1_IRQHandler + 0x0000000000008a1c RTCAlarm_IRQHandler + 0x0000000000008a1c TIM10_UP_IRQHandler + 0x0000000000008a1c TIM9_TRG_COM_IRQHandler + 0x0000000000008a1c UART7_IRQHandler + 0x0000000000008a1c USART2_IRQHandler + 0x0000000000008a1c UART6_IRQHandler + 0x0000000000008a1c I2C2_ER_IRQHandler + 0x0000000000008a1c DMA1_Channel2_IRQHandler + 0x0000000000008a1c TIM8_BRK_IRQHandler + 0x0000000000008a1c CAN1_SCE_IRQHandler + 0x0000000000008a1c FLASH_IRQHandler + 0x0000000000008a1c USART1_IRQHandler + 0x0000000000008a1c SPI3_IRQHandler + 0x0000000000008a1c I2C1_ER_IRQHandler + 0x0000000000008a1c USBWakeUp_IRQHandler + 0x0000000000008a1c DMA2_Channel3_IRQHandler + .text.handle_reset + 0x0000000000008a1e 0x8a ./Startup/startup_ch32v30x_D8C.o + 0x0000000000008a1e handle_reset + .text.ADC_DeInit + 0x0000000000008aa8 0x40 ./Peripheral/src/ch32v30x_adc.o + 0x0000000000008aa8 ADC_DeInit + .text.ADC_Init + 0x0000000000008ae8 0x56 ./Peripheral/src/ch32v30x_adc.o + 0x0000000000008ae8 ADC_Init + .text.ADC_Cmd 0x0000000000008b3e 0x10 ./Peripheral/src/ch32v30x_adc.o + 0x0000000000008b3e ADC_Cmd + .text.ADC_ResetCalibration + 0x0000000000008b4e 0xa ./Peripheral/src/ch32v30x_adc.o + 0x0000000000008b4e ADC_ResetCalibration + .text.ADC_GetResetCalibrationStatus + 0x0000000000008b58 0x8 ./Peripheral/src/ch32v30x_adc.o + 0x0000000000008b58 ADC_GetResetCalibrationStatus + .text.ADC_StartCalibration + 0x0000000000008b60 0xa ./Peripheral/src/ch32v30x_adc.o + 0x0000000000008b60 ADC_StartCalibration + .text.ADC_GetCalibrationStatus + 0x0000000000008b6a 0x8 ./Peripheral/src/ch32v30x_adc.o + 0x0000000000008b6a ADC_GetCalibrationStatus + .text.ADC_SoftwareStartConvCmd + 0x0000000000008b72 0x18 ./Peripheral/src/ch32v30x_adc.o + 0x0000000000008b72 ADC_SoftwareStartConvCmd + .text.ADC_RegularChannelConfig + 0x0000000000008b8a 0xb8 ./Peripheral/src/ch32v30x_adc.o + 0x0000000000008b8a ADC_RegularChannelConfig + .text.ADC_GetConversionValue + 0x0000000000008c42 0x8 ./Peripheral/src/ch32v30x_adc.o + 0x0000000000008c42 ADC_GetConversionValue + .text.ADC_TempSensorVrefintCmd + 0x0000000000008c4a 0x20 ./Peripheral/src/ch32v30x_adc.o + 0x0000000000008c4a ADC_TempSensorVrefintCmd + .text.ADC_GetFlagStatus + 0x0000000000008c6a 0xa ./Peripheral/src/ch32v30x_adc.o + 0x0000000000008c6a ADC_GetFlagStatus + .text.ADC_BufferCmd + 0x0000000000008c74 0x18 ./Peripheral/src/ch32v30x_adc.o + 0x0000000000008c74 ADC_BufferCmd + .text.Get_CalibrationValue + 0x0000000000008c8c 0x134 ./Peripheral/src/ch32v30x_adc.o + 0x0000000000008c8c Get_CalibrationValue + .text.BKP_DeInit + 0x0000000000008dc0 0x10 ./Peripheral/src/ch32v30x_bkp.o + 0x0000000000008dc0 BKP_DeInit + .text.BKP_WriteBackupRegister + 0x0000000000008dd0 0x1c ./Peripheral/src/ch32v30x_bkp.o + 0x0000000000008dd0 BKP_WriteBackupRegister + .text.DBGMCU_GetCHIPID + 0x0000000000008dec 0xa ./Peripheral/src/ch32v30x_dbgmcu.o + 0x0000000000008dec DBGMCU_GetCHIPID + .text.GPIO_Init + 0x0000000000008df6 0xc0 ./Peripheral/src/ch32v30x_gpio.o + 0x0000000000008df6 GPIO_Init + .text.GPIO_ReadInputDataBit + 0x0000000000008eb6 0xa ./Peripheral/src/ch32v30x_gpio.o + 0x0000000000008eb6 GPIO_ReadInputDataBit + .text.GPIO_WriteBit + 0x0000000000008ec0 0xa ./Peripheral/src/ch32v30x_gpio.o + 0x0000000000008ec0 GPIO_WriteBit + .text.NVIC_PriorityGroupConfig + 0x0000000000008eca 0x6 ./Peripheral/src/ch32v30x_misc.o + 0x0000000000008eca NVIC_PriorityGroupConfig + .text.NVIC_Init + 0x0000000000008ed0 0x5c ./Peripheral/src/ch32v30x_misc.o + 0x0000000000008ed0 NVIC_Init + .text.PWR_BackupAccessCmd + 0x0000000000008f2c 0x16 ./Peripheral/src/ch32v30x_pwr.o + 0x0000000000008f2c PWR_BackupAccessCmd + .text.RCC_ADCCLKConfig + 0x0000000000008f42 0x12 ./Peripheral/src/ch32v30x_rcc.o + 0x0000000000008f42 RCC_ADCCLKConfig + .text.RCC_LSEConfig + 0x0000000000008f54 0x28 ./Peripheral/src/ch32v30x_rcc.o + 0x0000000000008f54 RCC_LSEConfig + .text.RCC_RTCCLKConfig + 0x0000000000008f7c 0xc ./Peripheral/src/ch32v30x_rcc.o + 0x0000000000008f7c RCC_RTCCLKConfig + .text.RCC_RTCCLKCmd + 0x0000000000008f88 0x20 ./Peripheral/src/ch32v30x_rcc.o + 0x0000000000008f88 RCC_RTCCLKCmd + .text.RCC_GetClocksFreq + 0x0000000000008fa8 0x176 ./Peripheral/src/ch32v30x_rcc.o + 0x0000000000008fa8 RCC_GetClocksFreq + .text.RCC_APB2PeriphClockCmd + 0x000000000000911e 0x1e ./Peripheral/src/ch32v30x_rcc.o + 0x000000000000911e RCC_APB2PeriphClockCmd + .text.RCC_APB1PeriphClockCmd + 0x000000000000913c 0x1e ./Peripheral/src/ch32v30x_rcc.o + 0x000000000000913c RCC_APB1PeriphClockCmd + .text.RCC_APB2PeriphResetCmd + 0x000000000000915a 0x1e ./Peripheral/src/ch32v30x_rcc.o + 0x000000000000915a RCC_APB2PeriphResetCmd + .text.RCC_BackupResetCmd + 0x0000000000009178 0x20 ./Peripheral/src/ch32v30x_rcc.o + 0x0000000000009178 RCC_BackupResetCmd + .text.RCC_GetFlagStatus + 0x0000000000009198 0x2e ./Peripheral/src/ch32v30x_rcc.o + 0x0000000000009198 RCC_GetFlagStatus + .text.RTC_ITConfig + 0x00000000000091c6 0x1a ./Peripheral/src/ch32v30x_rtc.o + 0x00000000000091c6 RTC_ITConfig + .text.RTC_EnterConfigMode + 0x00000000000091e0 0x12 ./Peripheral/src/ch32v30x_rtc.o + 0x00000000000091e0 RTC_EnterConfigMode + .text.RTC_ExitConfigMode + 0x00000000000091f2 0x18 ./Peripheral/src/ch32v30x_rtc.o + 0x00000000000091f2 RTC_ExitConfigMode + .text.RTC_GetCounter + 0x000000000000920a 0x5a ./Peripheral/src/ch32v30x_rtc.o + 0x000000000000920a RTC_GetCounter + .text.RTC_SetCounter + 0x0000000000009264 0x2c ./Peripheral/src/ch32v30x_rtc.o + 0x0000000000009264 RTC_SetCounter + .text.RTC_SetPrescaler + 0x0000000000009290 0x2e ./Peripheral/src/ch32v30x_rtc.o + 0x0000000000009290 RTC_SetPrescaler + .text.RTC_WaitForLastTask + 0x00000000000092be 0x10 ./Peripheral/src/ch32v30x_rtc.o + 0x00000000000092be RTC_WaitForLastTask + .text.RTC_WaitForSynchro + 0x00000000000092ce 0x24 ./Peripheral/src/ch32v30x_rtc.o + 0x00000000000092ce RTC_WaitForSynchro + .text.RTC_ClearFlag + 0x00000000000092f2 0x14 ./Peripheral/src/ch32v30x_rtc.o + 0x00000000000092f2 RTC_ClearFlag + .text.RTC_ClearITPendingBit + 0x0000000000009306 0xc ./Peripheral/src/ch32v30x_rtc.o + 0x0000000000009306 RTC_ClearITPendingBit + .text.SPI_Init + 0x0000000000009312 0x3e ./Peripheral/src/ch32v30x_spi.o + 0x0000000000009312 SPI_Init + .text.SPI_Cmd 0x0000000000009350 0x1a ./Peripheral/src/ch32v30x_spi.o + 0x0000000000009350 SPI_Cmd + .text.SPI_I2S_SendData + 0x000000000000936a 0x4 ./Peripheral/src/ch32v30x_spi.o + 0x000000000000936a SPI_I2S_SendData + .text.SPI_I2S_ReceiveData + 0x000000000000936e 0x4 ./Peripheral/src/ch32v30x_spi.o + 0x000000000000936e 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GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-nano-vfprintf.o) + .text.__sfputs_r + 0x000000000000aad8 0x42 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-nano-vfprintf.o) + 0x000000000000aad8 __sfputs_r + .text._vfprintf_r + 0x000000000000ab1a 0x28a /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-nano-vfprintf.o) + 0x000000000000ab1a _vfiprintf_r + 0x000000000000ab1a _vfprintf_r + .text._printf_common + 0x000000000000ada4 0x10c /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-nano-vfprintf_i.o) + 0x000000000000ada4 _printf_common + .text._printf_i + 0x000000000000aeb0 0x2a2 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-nano-vfprintf_i.o) + 0x000000000000aeb0 _printf_i + .text._putc_r 0x000000000000b152 0x84 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-putc.o) + 0x000000000000b152 _putc_r + .text.__sread 0x000000000000b1d6 0x2c /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-stdio.o) + 0x000000000000b1d6 __sread + .text.__swrite + 0x000000000000b202 0x48 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-stdio.o) + 0x000000000000b202 __swrite + .text.__sseek 0x000000000000b24a 0x30 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-stdio.o) + 0x000000000000b24a __sseek + .text.__sclose + 0x000000000000b27a 0x6 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-stdio.o) + 0x000000000000b27a __sclose + .text._write_r + 0x000000000000b280 0x2e /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-writer.o) + 0x000000000000b280 _write_r + .text._close_r + 0x000000000000b2ae 0x28 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-closer.o) + 0x000000000000b2ae _close_r + .text._fstat_r + 0x000000000000b2d6 0x2a /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-fstatr.o) + 0x000000000000b2d6 _fstat_r + .text._isatty_r + 0x000000000000b300 0x28 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-isattyr.o) + 0x000000000000b300 _isatty_r + .text._lseek_r + 0x000000000000b328 0x2c /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-lseekr.o) + 0x000000000000b328 _lseek_r + .text.memchr 0x000000000000b354 0x18 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-memchr.o) + 0x000000000000b354 memchr + .text._realloc_r + 0x000000000000b36c 0x58 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-nano-reallocr.o) + 0x000000000000b36c _realloc_r + .text._read_r 0x000000000000b3c4 0x2c /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-readr.o) + 0x000000000000b3c4 _read_r + .text._malloc_usable_size_r + 0x000000000000b3f0 0x14 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-nano-msizer.o) + 0x000000000000b3f0 _malloc_usable_size_r + .text._close 0x000000000000b404 0xc /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libnosys.a(close.o) + 0x000000000000b404 _close + .text._fstat 0x000000000000b410 0xc /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libnosys.a(fstat.o) + 0x000000000000b410 _fstat + .text._getpid 0x000000000000b41c 0xc /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libnosys.a(getpid.o) + 0x000000000000b41c _getpid + .text._isatty 0x000000000000b428 0xc /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libnosys.a(isatty.o) + 0x000000000000b428 _isatty + .text._kill 0x000000000000b434 0xc /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libnosys.a(kill.o) + 0x000000000000b434 _kill + .text._lseek 0x000000000000b440 0xc /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libnosys.a(lseek.o) + 0x000000000000b440 _lseek + .text._read 0x000000000000b44c 0xc /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libnosys.a(read.o) + 0x000000000000b44c _read + .text._exit 0x000000000000b458 0x2 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libnosys.a(_exit.o) + 0x000000000000b458 _exit + *(.rodata) + *(.rodata*) + *fill* 0x000000000000b45a 0x2 + .rodata.hexdump.str1.4 + 0x000000000000b45c 0x27 ./User/util/hexdump.o + 0x2e (size before relaxing) + *fill* 0x000000000000b483 0x1 + .rodata.hexdump_compact.str1.4 + 0x000000000000b484 0x5 ./User/util/hexdump.o + *fill* 0x000000000000b489 0x3 + .rodata.decodeAdvertisement.str1.4 + 0x000000000000b48c 0xc9 ./User/meshcore/packets/advert.o + *fill* 0x000000000000b555 0x3 + .rodata.printAdvertisement.str1.4 + 0x000000000000b558 0x7b ./User/meshcore/packets/advert.o + *fill* 0x000000000000b5d3 0x1 + .rodata.sendAdvert.str1.4 + 0x000000000000b5d4 0x41 ./User/meshcore/packets/advert.o + *fill* 0x000000000000b615 0x3 + .rodata.decodeAnonReq.str1.4 + 0x000000000000b618 0x13b ./User/meshcore/packets/anonymous.o + 0x143 (size before relaxing) + *fill* 0x000000000000b753 0x1 + .rodata.printAnonRequest.str1.4 + 0x000000000000b754 0xcf ./User/meshcore/packets/anonymous.o + 0xd7 (size before relaxing) + *fill* 0x000000000000b823 0x1 + .rodata.decodeControlFrame.str1.4 + 0x000000000000b824 0x3e ./User/meshcore/packets/control.o + 0x42 (size before relaxing) + *fill* 0x000000000000b862 0x2 + .rodata.printDiscoverRequest.str1.4 + 0x000000000000b864 0x76 ./User/meshcore/packets/control.o + *fill* 0x000000000000b8da 0x2 + .rodata.printDiscoverResponse.str1.4 + 0x000000000000b8dc 0x5c ./User/meshcore/packets/control.o + 0x5e (size before relaxing) + .rodata.decodeEncryptedPayload.str1.4 + 0x000000000000b938 0xe7 ./User/meshcore/packets/encrypted.o + 0xeb (size before relaxing) + *fill* 0x000000000000ba1f 0x1 + .rodata.parseEncryptedPayload.str1.4 + 0x000000000000ba20 0x10d ./User/meshcore/packets/encrypted.o + *fill* 0x000000000000bb2d 0x3 + .rodata.printEncryptedPayload.str1.4 + 0x000000000000bb30 0x80 ./User/meshcore/packets/encrypted.o + 0x8a (size before relaxing) + .rodata.printRequest.str1.4 + 0x000000000000bbb0 0x43 ./User/meshcore/packets/encrypted.o + *fill* 0x000000000000bbf3 0x1 + .rodata.printResponse.str1.4 + 0x000000000000bbf4 0x17 ./User/meshcore/packets/encrypted.o + *fill* 0x000000000000bc0b 0x1 + .rodata.processCommand.str1.4 + 0x000000000000bc0c 0x378 ./User/meshcore/packets/encrypted.o + 0x39c (size before relaxing) + .rodata.sendEncryptedFrame.str1.4 + 0x000000000000bf84 0x72 ./User/meshcore/packets/encrypted.o + 0x76 (size before relaxing) + *fill* 0x000000000000bff6 0x2 + .rodata.sendEncryptedTextMessage.str1.4 + 0x000000000000bff8 0x39 ./User/meshcore/packets/encrypted.o + 0x3d (size before relaxing) + *fill* 0x000000000000c031 0x3 + .rodata.decodeGroupMessage.str1.4 + 0x000000000000c034 0x9d ./User/meshcore/packets/group.o + 0xa1 (size before relaxing) + .rodata.makeSendGroupMessage.str1.4 + 0x000000000000c0d1 0x9d ./User/meshcore/packets/group.o + 0x3 (size before relaxing) + *fill* 0x000000000000c0d1 0x3 + .rodata.sendGroupMessage.str1.4 + 0x000000000000c0d4 0xa ./User/meshcore/packets/group.o + *fill* 0x000000000000c0de 0x2 + .rodata.processFrame.str1.4 + 0x000000000000c0e0 0x73 ./User/meshcore/meshcore.o + 0x7b (size before relaxing) + *fill* 0x000000000000c153 0x1 + .rodata.ReadFrame + 0x000000000000c154 0x14 ./User/meshcore/meshframing.o + .rodata.LoRaTransmit + 0x000000000000c168 0x14 ./User/meshcore/meshframing.o + .rodata.LoRaTransmit.str1.4 + 0x000000000000c17c 0x117 ./User/meshcore/meshframing.o + 0x11b (size before relaxing) + *fill* 0x000000000000c293 0x1 + .rodata.ReadFrame.str1.4 + 0x000000000000c294 0x23 ./User/meshcore/meshframing.o + *fill* 0x000000000000c2b7 0x1 + .rodata.printframeHeader.str1.4 + 0x000000000000c2b8 0x129 ./User/meshcore/meshframing.o + 0x131 (size before relaxing) + *fill* 0x000000000000c3e1 0x3 + .rodata.mon_table + 0x000000000000c3e4 0xc ./User/lib/rtc/rtc.o + 0x000000000000c3e4 mon_table + .rodata.months.5280 + 0x000000000000c3f0 0x25 ./User/lib/rtc/rtc.o + *fill* 0x000000000000c415 0x3 + .rodata.table_week + 0x000000000000c418 0xc ./User/lib/rtc/rtc.o + 0x000000000000c418 table_week + *fill* 0x000000000000c424 0x4 + .rodata.K 0x000000000000c428 0x280 ./User/lib/monocypher/monocypher-ed25519.o + .rodata.crypto_sha512_init.cst8 + 0x000000000000c6a8 0x40 ./User/lib/monocypher/monocypher-ed25519.o + .rodata.D2 0x000000000000c6e8 0x28 ./User/lib/monocypher/monocypher.o + .rodata.L 0x000000000000c710 0x20 ./User/lib/monocypher/monocypher.o + .rodata.b_comb_high + 0x000000000000c730 0x3c0 ./User/lib/monocypher/monocypher.o + .rodata.b_comb_low + 0x000000000000caf0 0x3c0 ./User/lib/monocypher/monocypher.o + .rodata.b_window + 0x000000000000ceb0 0x3c0 ./User/lib/monocypher/monocypher.o + .rodata.d 0x000000000000d270 0x28 ./User/lib/monocypher/monocypher.o + .rodata.fe_one + 0x000000000000d298 0x28 ./User/lib/monocypher/monocypher.o + .rodata.half_mod_L.2900 + 0x000000000000d2c0 0x20 ./User/lib/monocypher/monocypher.o + .rodata.half_ones.2901 + 0x000000000000d2e0 0x20 ./User/lib/monocypher/monocypher.o + .rodata.r.2702 + 0x000000000000d300 0x24 ./User/lib/monocypher/monocypher.o + .rodata.sqrtm1 + 0x000000000000d324 0x28 ./User/lib/monocypher/monocypher.o + .rodata.zero_point.2876 + 0x000000000000d34c 0x20 ./User/lib/monocypher/monocypher.o + .rodata.Rcon 0x000000000000d36c 0xb ./User/lib/cifra/aes.o + *fill* 0x000000000000d377 0x1 + .rodata.S 0x000000000000d378 0x100 ./User/lib/cifra/aes.o + .rodata.S_inv 0x000000000000d478 0x100 ./User/lib/cifra/aes.o + .rodata.K 0x000000000000d578 0x100 ./User/lib/cifra/sha256.o + .rodata.cf_sha256 + 0x000000000000d678 0x14 ./User/lib/cifra/sha256.o + 0x000000000000d678 cf_sha256 + .rodata.BRNTestChannelPSK + 0x000000000000d68c 0x10 ./User/lib/config.o + 0x000000000000d68c BRNTestChannelPSK + .rodata.CSWTCH.3 + 0x000000000000d69c 0x10 ./User/lib/config.o + .rodata.LoraApply.str1.4 + 0x000000000000d6ac 0x6c ./User/lib/config.o + 0x74 (size before relaxing) + .rodata.addChannel.str1.4 + 0x000000000000d718 0x9e ./User/lib/config.o + 0xa2 (size before relaxing) + *fill* 0x000000000000d7b6 0x2 + .rodata.getStringRole.str1.4 + 0x000000000000d7b8 0x8 ./User/lib/config.o + .rodata.populateDefaults.str1.4 + 0x000000000000d7c0 0x4c ./User/lib/config.o + .rodata.printNodeDB.str1.4 + 0x000000000000d80c 0x12c ./User/lib/config.o + 0x140 (size before relaxing) + .rodata.publicChannelPSK + 0x000000000000d938 0x10 ./User/lib/config.o + 0x000000000000d938 publicChannelPSK + .rodata.str1.4 + 0x000000000000d948 0x2b ./User/lib/config.o + *fill* 0x000000000000d973 0x1 + .rodata.main.str1.4 + 0x000000000000d974 0x1a7 ./User/main.o + 0x1c7 (size before relaxing) + *fill* 0x000000000000db1b 0x1 + .rodata.LoRaBegin.str1.4 + 0x000000000000db1c 0x8a ./User/sx1262.o + *fill* 0x000000000000dba6 0x2 + .rodata.LoRaConfig.str1.4 + 0x000000000000dba8 0x24 ./User/sx1262.o + .rodata.LoRaError.str1.4 + 0x000000000000dbcc 0x34 ./User/sx1262.o + 0x38 (size before relaxing) + .rodata.ReadCommand.str1.4 + 0x000000000000dc00 0x48 ./User/sx1262.o + .rodata.ReadRegister.str1.4 + 0x000000000000dc48 0x98 ./User/sx1262.o + .rodata.ResetLora.str1.4 + 0x000000000000dce0 0x22 ./User/sx1262.o + *fill* 0x000000000000dd02 0x2 + .rodata.SetRx.str1.4 + 0x000000000000dd04 0x44 ./User/sx1262.o + .rodata.SetStopRxTimerOnPreambleDetect.str1.4 + 0x000000000000dd48 0x34 ./User/sx1262.o + .rodata.SetTx.str1.4 + 0x000000000000dd7c 0xb0 ./User/sx1262.o + .rodata.WaitForIdle.str1.4 + 0x000000000000de2c 0x33 ./User/sx1262.o + 0x36 (size before relaxing) + *fill* 0x000000000000de5f 0x1 + .rodata.WaitForIdleBegin.str1.4 + 0x000000000000de60 0x25 ./User/sx1262.o + *fill* 0x000000000000de85 0x3 + .rodata.WriteCommand.str1.4 + 0x000000000000de88 0x70 ./User/sx1262.o + 0x74 (size before relaxing) + .rodata.WriteCommand2.str1.4 + 0x000000000000def8 0x4a ./User/sx1262.o + *fill* 0x000000000000df42 0x2 + .rodata.WriteRegister.str1.4 + 0x000000000000df44 0x69 ./User/sx1262.o + 0x6d (size before relaxing) + *fill* 0x000000000000dfad 0x3 + .rodata.__clz_tab + 0x000000000000dfb0 0x100 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32/libgcc.a(_clz.o) + 0x000000000000dfb0 __clz_tab + .rodata._setlocale_r.str1.4 + 0x000000000000e0b0 0x6 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-locale.o) + 0xd (size before relaxing) + *fill* 0x000000000000e0b6 0x2 + .rodata.str1.4 + 0x000000000000e0b8 0x2 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-locale.o) + *fill* 0x000000000000e0ba 0x2 + .rodata._ctype_ + 0x000000000000e0bc 0x101 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-ctype_.o) + 0x000000000000e0bc _ctype_ + *fill* 0x000000000000e1bd 0x3 + .rodata.__sf_fake_stderr + 0x000000000000e1c0 0x20 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-findfp.o) + 0x000000000000e1c0 __sf_fake_stderr + .rodata.__sf_fake_stdin + 0x000000000000e1e0 0x20 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-findfp.o) + 0x000000000000e1e0 __sf_fake_stdin + .rodata.__sf_fake_stdout + 0x000000000000e200 0x20 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-findfp.o) + 0x000000000000e200 __sf_fake_stdout + .rodata._svfprintf_r.str1.4 + 0x000000000000e220 0x13 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-nano-svfprintf.o) + .rodata._vfprintf_r.str1.4 + 0x000000000000e233 0x13 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-nano-vfprintf.o) + *fill* 0x000000000000e233 0x1 + .rodata._printf_i.str1.4 + 0x000000000000e234 0x28 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-nano-vfprintf_i.o) + 0x25 (size before relaxing) + *(.gnu.linkonce.t.*) + 0x000000000000e25c . = ALIGN (0x4) + +.rela.dyn 0x000000000000e25c 0x0 + .rela.init 0x000000000000e25c 0x0 ./User/util/hexdump.o + .rela.vector 0x000000000000e25c 0x0 ./User/util/hexdump.o + .rela.text.handle_reset + 0x000000000000e25c 0x0 ./User/util/hexdump.o + .rela.text._sbrk + 0x000000000000e25c 0x0 ./User/util/hexdump.o + .rela.sdata.curbrk.5271 + 0x000000000000e25c 0x0 ./User/util/hexdump.o + .rela.text._sbrk_r + 0x000000000000e25c 0x0 ./User/util/hexdump.o + .rela.text._kill_r + 0x000000000000e25c 0x0 ./User/util/hexdump.o + .rela.text._svfprintf_r + 0x000000000000e25c 0x0 ./User/util/hexdump.o + .rela.text._vfprintf_r + 0x000000000000e25c 0x0 ./User/util/hexdump.o + .rela.text._write_r + 0x000000000000e25c 0x0 ./User/util/hexdump.o + .rela.text._close_r + 0x000000000000e25c 0x0 ./User/util/hexdump.o + .rela.text._fstat_r + 0x000000000000e25c 0x0 ./User/util/hexdump.o + .rela.text._isatty_r + 0x000000000000e25c 0x0 ./User/util/hexdump.o + .rela.text._lseek_r + 0x000000000000e25c 0x0 ./User/util/hexdump.o + .rela.text._read_r + 0x000000000000e25c 0x0 ./User/util/hexdump.o + .rela.text._close + 0x000000000000e25c 0x0 ./User/util/hexdump.o + .rela.text._fstat + 0x000000000000e25c 0x0 ./User/util/hexdump.o + .rela.text._getpid + 0x000000000000e25c 0x0 ./User/util/hexdump.o + .rela.text._isatty + 0x000000000000e25c 0x0 ./User/util/hexdump.o + .rela.text._kill + 0x000000000000e25c 0x0 ./User/util/hexdump.o + .rela.text._lseek + 0x000000000000e25c 0x0 ./User/util/hexdump.o + .rela.text._read + 0x000000000000e25c 0x0 ./User/util/hexdump.o + +.fini 0x000000000000e25c 0x0 + *(SORT_NONE(.fini)) + 0x000000000000e25c . = ALIGN (0x4) + [!provide] PROVIDE (_etext = .) + [!provide] PROVIDE (_eitcm = .) + +.preinit_array 0x000000000000e25c 0x0 + [!provide] PROVIDE (__preinit_array_start = .) + *(.preinit_array) + [!provide] PROVIDE (__preinit_array_end = .) + +.init_array 0x000000000000e25c 0x0 + [!provide] PROVIDE (__init_array_start = .) + *(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)) + *(.init_array EXCLUDE_FILE(*crtend?.o *crtend.o *crtbegin?.o *crtbegin.o) .ctors) + [!provide] PROVIDE (__init_array_end = .) + +.fini_array 0x000000000000e25c 0x0 + [!provide] PROVIDE (__fini_array_start = .) + *(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)) + *(.fini_array EXCLUDE_FILE(*crtend?.o *crtend.o *crtbegin?.o *crtbegin.o) .dtors) + [!provide] PROVIDE (__fini_array_end = .) + +.ctors + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT_BY_NAME(.ctors.*)) + *(.ctors) + +.dtors + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT_BY_NAME(.dtors.*)) + *(.dtors) + +.dalign 0x0000000020000000 0x0 load address 0x000000000000e25c + 0x0000000020000000 . = ALIGN (0x4) + 0x0000000020000000 PROVIDE (_data_vma = .) + +.dlalign 0x000000000000e25c 0x0 + 0x000000000000e25c . = ALIGN (0x4) + 0x000000000000e25c PROVIDE (_data_lma = .) + +.data 0x0000000020000000 0x208 load address 0x000000000000e25c + *(.gnu.linkonce.r.*) + *(.data .data.*) + .data.AHBPrescTable + 0x0000000020000000 0x10 ./User/system_ch32v30x.o + 0x0000000020000000 AHBPrescTable + .data.APBAHBPrescTable + 0x0000000020000010 0x10 ./Peripheral/src/ch32v30x_rcc.o + .data.__global_locale + 0x0000000020000020 0x16c /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-locale.o) + 0x0000000020000020 __global_locale + .data.impure_data + 0x000000002000018c 0x60 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-impure.o) + *(.gnu.linkonce.d.*) + 0x00000000200001f0 . = ALIGN (0x8) + *fill* 0x00000000200001ec 0x4 + 0x00000000200009f0 PROVIDE (__global_pointer$ = (. + 0x800)) + *(.sdata .sdata.*) + .sdata.SystemCoreClock + 0x00000000200001f0 0x4 ./User/system_ch32v30x.o + 0x00000000200001f0 SystemCoreClock + .sdata.ADCPrescTable + 0x00000000200001f4 0x4 ./Peripheral/src/ch32v30x_rcc.o + .sdata.curbrk.5271 + 0x00000000200001f8 0x4 ./Debug/debug.o + .sdata._impure_ptr + 0x00000000200001fc 0x4 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-impure.o) + 0x00000000200001fc _impure_ptr + *(.sdata2.*) + .sdata2._global_impure_ptr + 0x0000000020000200 0x4 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-impure.o) + 0x0000000020000200 _global_impure_ptr + *(.gnu.linkonce.s.*) + 0x0000000020000208 . = ALIGN (0x8) + *fill* 0x0000000020000204 0x4 + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + 0x0000000020000208 . = ALIGN (0x4) + 0x0000000020000208 PROVIDE (_edata = .) + +.bss 0x0000000020000208 0xf78 load address 0x000000000000e464 + 0x0000000020000208 . = ALIGN (0x4) + 0x0000000020000208 PROVIDE (_sbss = .) + *(.sbss*) + .sbss.dontReTXHistoryIndex + 0x0000000020000208 0x1 ./User/meshcore/meshframing.o + 0x0000000020000208 dontReTXHistoryIndex + *fill* 0x0000000020000209 0x3 + .sbss.startupTime + 0x000000002000020c 0x4 ./User/meshcore/stats.o + 0x000000002000020c startupTime + .sbss.daycnt.5339 + 0x0000000020000210 0x2 ./User/lib/rtc/rtc.o + .sbss.Calibrattion_Val + 0x0000000020000212 0x2 ./User/lib/adc/temperature.o + 0x0000000020000212 Calibrattion_Val + .sbss.bootedUp + 0x0000000020000214 0x1 ./User/main.o + 0x0000000020000214 bootedUp + *fill* 0x0000000020000215 0x3 + .sbss.PacketParams + 0x0000000020000218 0x6 ./User/sx1262.o + 0x0000000020000218 PacketParams + .sbss.debugPrint + 0x000000002000021e 0x1 ./User/sx1262.o + 0x000000002000021e debugPrint + .sbss.txActive + 0x000000002000021f 0x1 ./User/sx1262.o + 0x000000002000021f txActive + .sbss.txLost 0x0000000020000220 0x4 ./User/sx1262.o + 0x0000000020000220 txLost + .sbss.NVIC_Priority_Group + 0x0000000020000224 0x4 ./Peripheral/src/ch32v30x_misc.o + 0x0000000020000224 NVIC_Priority_Group + .sbss.p_ms 0x0000000020000228 0x2 ./Debug/debug.o + .sbss.p_us 0x000000002000022a 0x1 ./Debug/debug.o + *fill* 0x000000002000022b 0x1 + .sbss.__malloc_free_list + 0x000000002000022c 0x4 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-nano-mallocr.o) + 0x000000002000022c __malloc_free_list + .sbss.__malloc_sbrk_start + 0x0000000020000230 0x4 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-nano-mallocr.o) + 0x0000000020000230 __malloc_sbrk_start + *(.gnu.linkonce.sb.*) + *(.bss*) + .bss.dontReTXHistory + 0x0000000020000234 0x108 ./User/meshcore/meshframing.o + 0x0000000020000234 dontReTXHistory + .bss.stats 0x000000002000033c 0x34 ./User/meshcore/stats.o + 0x000000002000033c stats + .bss.calendar 0x0000000020000370 0xa ./User/lib/rtc/rtc.o + 0x0000000020000370 calendar + *fill* 0x000000002000037a 0x2 + .bss.currentLoRaSettings + 0x000000002000037c 0x10 ./User/lib/config.o + 0x000000002000037c currentLoRaSettings + .bss.persistent + 0x000000002000038c 0xdf0 ./User/lib/config.o + 0x000000002000038c persistent + *(.gnu.linkonce.b.*) + *(COMMON*) + COMMON 0x000000002000117c 0x4 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-reent.o) + 0x000000002000117c errno + 0x0000000020001180 . = ALIGN (0x4) + 0x0000000020001180 PROVIDE (_ebss = .) + 0x0000000020001180 PROVIDE (_end = _ebss) + [!provide] PROVIDE (end = .) + +.stack 0x0000000020007800 0x800 + 0x0000000020007800 PROVIDE (_heap_end = .) + 0x0000000020007800 . = ALIGN (0x4) + [!provide] PROVIDE (_susrstack = .) + 0x0000000020008000 . = (. + __stack_size) + *fill* 0x0000000020007800 0x800 + 0x0000000020008000 PROVIDE (_eusrstack = .) +OUTPUT(meshcorenortos.elf elf32-littleriscv) + +.debug_info 0x0000000000000000 0x38f92 + .debug_info 0x0000000000000000 0xb77 ./User/util/hexdump.o + .debug_info 0x0000000000000b77 0x1115 ./User/meshcore/packets/ack.o + .debug_info 0x0000000000001c8c 0x182c ./User/meshcore/packets/advert.o + .debug_info 0x00000000000034b8 0x1850 ./User/meshcore/packets/anonymous.o + .debug_info 0x0000000000004d08 0x144d ./User/meshcore/packets/control.o + .debug_info 0x0000000000006155 0x2d2d ./User/meshcore/packets/encrypted.o + .debug_info 0x0000000000008e82 0x1383 ./User/meshcore/packets/group.o + .debug_info 0x000000000000a205 0x12ff ./User/meshcore/meshcore.o + .debug_info 0x000000000000b504 0x2090 ./User/meshcore/meshframing.o + .debug_info 0x000000000000d594 0x1f8 ./User/meshcore/stats.o + .debug_info 0x000000000000d78c 0x154b ./User/lib/rtc/rtc.o + .debug_info 0x000000000000ecd7 0x1e5d ./User/lib/monocypher/monocypher-ed25519.o + .debug_info 0x0000000000010b34 0xd47e ./User/lib/monocypher/monocypher.o + .debug_info 0x000000000001dfb2 0x1a76 ./User/lib/cifra/aes.o + .debug_info 0x000000000001fa28 0x108d ./User/lib/cifra/blockwise.o + .debug_info 0x0000000000020ab5 0xbf7 ./User/lib/cifra/chash.o + .debug_info 0x00000000000216ac 0x11db ./User/lib/cifra/hmac.o + .debug_info 0x0000000000022887 0x1174 ./User/lib/cifra/sha256.o + .debug_info 0x00000000000239fb 0x11df ./User/lib/adc/temperature.o + .debug_info 0x0000000000024bda 0x1aaf ./User/lib/config.o + .debug_info 0x0000000000026689 0xbc0 ./User/ch32v30x_it.o + .debug_info 0x0000000000027249 0x1efa ./User/main.o + .debug_info 0x0000000000029143 0x34aa ./User/sx1262.o + .debug_info 0x000000000002c5ed 0xbb5 ./User/system_ch32v30x.o + .debug_info 0x000000000002d1a2 0x22 ./Startup/startup_ch32v30x_D8C.o + .debug_info 0x000000000002d1c4 0x1703 ./Peripheral/src/ch32v30x_adc.o + .debug_info 0x000000000002e8c7 0x10d3 ./Peripheral/src/ch32v30x_bkp.o + .debug_info 0x000000000002f99a 0xa94 ./Peripheral/src/ch32v30x_dbgmcu.o + .debug_info 0x000000000003042e 0x12aa ./Peripheral/src/ch32v30x_gpio.o + .debug_info 0x00000000000316d8 0xf5b ./Peripheral/src/ch32v30x_misc.o + .debug_info 0x0000000000032633 0x101d ./Peripheral/src/ch32v30x_pwr.o + .debug_info 0x0000000000033650 0x158a ./Peripheral/src/ch32v30x_rcc.o + .debug_info 0x0000000000034bda 0xdd4 ./Peripheral/src/ch32v30x_rtc.o + .debug_info 0x00000000000359ae 0x12cd ./Peripheral/src/ch32v30x_spi.o + .debug_info 0x0000000000036c7b 0x13cd ./Peripheral/src/ch32v30x_usart.o + .debug_info 0x0000000000038048 0xf4a ./Debug/debug.o + +.debug_abbrev 0x0000000000000000 0x7410 + .debug_abbrev 0x0000000000000000 0x26e ./User/util/hexdump.o + .debug_abbrev 0x000000000000026e 0x28f ./User/meshcore/packets/ack.o + .debug_abbrev 0x00000000000004fd 0x31e ./User/meshcore/packets/advert.o + .debug_abbrev 0x000000000000081b 0x3a3 ./User/meshcore/packets/anonymous.o + .debug_abbrev 0x0000000000000bbe 0x2be ./User/meshcore/packets/control.o + .debug_abbrev 0x0000000000000e7c 0x452 ./User/meshcore/packets/encrypted.o + .debug_abbrev 0x00000000000012ce 0x2f5 ./User/meshcore/packets/group.o + .debug_abbrev 0x00000000000015c3 0x2b5 ./User/meshcore/meshcore.o + .debug_abbrev 0x0000000000001878 0x41b ./User/meshcore/meshframing.o + .debug_abbrev 0x0000000000001c93 0x79 ./User/meshcore/stats.o + .debug_abbrev 0x0000000000001d0c 0x408 ./User/lib/rtc/rtc.o + .debug_abbrev 0x0000000000002114 0x475 ./User/lib/monocypher/monocypher-ed25519.o + .debug_abbrev 0x0000000000002589 0x5c0 ./User/lib/monocypher/monocypher.o + .debug_abbrev 0x0000000000002b49 0x539 ./User/lib/cifra/aes.o + .debug_abbrev 0x0000000000003082 0x330 ./User/lib/cifra/blockwise.o + .debug_abbrev 0x00000000000033b2 0x2bc ./User/lib/cifra/chash.o + .debug_abbrev 0x000000000000366e 0x363 ./User/lib/cifra/hmac.o + .debug_abbrev 0x00000000000039d1 0x34c ./User/lib/cifra/sha256.o + .debug_abbrev 0x0000000000003d1d 0x322 ./User/lib/adc/temperature.o + .debug_abbrev 0x000000000000403f 0x3b3 ./User/lib/config.o + .debug_abbrev 0x00000000000043f2 0x22c ./User/ch32v30x_it.o + .debug_abbrev 0x000000000000461e 0x32c ./User/main.o + .debug_abbrev 0x000000000000494a 0x575 ./User/sx1262.o + .debug_abbrev 0x0000000000004ebf 0x2c0 ./User/system_ch32v30x.o + .debug_abbrev 0x000000000000517f 0x12 ./Startup/startup_ch32v30x_D8C.o + .debug_abbrev 0x0000000000005191 0x3a9 ./Peripheral/src/ch32v30x_adc.o + .debug_abbrev 0x000000000000553a 0x2cc ./Peripheral/src/ch32v30x_bkp.o + .debug_abbrev 0x0000000000005806 0x2f7 ./Peripheral/src/ch32v30x_dbgmcu.o + .debug_abbrev 0x0000000000005afd 0x31a ./Peripheral/src/ch32v30x_gpio.o + .debug_abbrev 0x0000000000005e17 0x2da ./Peripheral/src/ch32v30x_misc.o + .debug_abbrev 0x00000000000060f1 0x3aa ./Peripheral/src/ch32v30x_pwr.o + .debug_abbrev 0x000000000000649b 0x351 ./Peripheral/src/ch32v30x_rcc.o + .debug_abbrev 0x00000000000067ec 0x30b ./Peripheral/src/ch32v30x_rtc.o + .debug_abbrev 0x0000000000006af7 0x312 ./Peripheral/src/ch32v30x_spi.o + .debug_abbrev 0x0000000000006e09 0x312 ./Peripheral/src/ch32v30x_usart.o + .debug_abbrev 0x000000000000711b 0x2f5 ./Debug/debug.o + +.debug_loc 0x0000000000000000 0x18b98 + .debug_loc 0x0000000000000000 0x245 ./User/util/hexdump.o + .debug_loc 0x0000000000000245 0x5d ./User/meshcore/packets/ack.o + .debug_loc 0x00000000000002a2 0x3c4 ./User/meshcore/packets/advert.o + .debug_loc 0x0000000000000666 0x4c9 ./User/meshcore/packets/anonymous.o + .debug_loc 0x0000000000000b2f 0x263 ./User/meshcore/packets/control.o + .debug_loc 0x0000000000000d92 0x99b ./User/meshcore/packets/encrypted.o + .debug_loc 0x000000000000172d 0x1af ./User/meshcore/packets/group.o + .debug_loc 0x00000000000018dc 0x68 ./User/meshcore/meshcore.o + .debug_loc 0x0000000000001944 0xac7 ./User/meshcore/meshframing.o + .debug_loc 0x000000000000240b 0x677 ./User/lib/rtc/rtc.o + .debug_loc 0x0000000000002a82 0x19ac ./User/lib/monocypher/monocypher-ed25519.o + .debug_loc 0x000000000000442e 0xd006 ./User/lib/monocypher/monocypher.o + .debug_loc 0x0000000000011434 0xf9e ./User/lib/cifra/aes.o + .debug_loc 0x00000000000123d2 0xb2d ./User/lib/cifra/blockwise.o + .debug_loc 0x0000000000012eff 0x14e ./User/lib/cifra/chash.o + .debug_loc 0x000000000001304d 0x60c ./User/lib/cifra/hmac.o + .debug_loc 0x0000000000013659 0x5af ./User/lib/cifra/sha256.o + .debug_loc 0x0000000000013c08 0x3a9 ./User/lib/adc/temperature.o + .debug_loc 0x0000000000013fb1 0x553 ./User/lib/config.o + .debug_loc 0x0000000000014504 0xb3 ./User/main.o + .debug_loc 0x00000000000145b7 0x1196 ./User/sx1262.o + .debug_loc 0x000000000001574d 0x163 ./User/system_ch32v30x.o + .debug_loc 0x00000000000158b0 0xab6 ./Peripheral/src/ch32v30x_adc.o + .debug_loc 0x0000000000016366 0xd8 ./Peripheral/src/ch32v30x_bkp.o + .debug_loc 0x000000000001643e 0x7c ./Peripheral/src/ch32v30x_dbgmcu.o + .debug_loc 0x00000000000164ba 0x72b ./Peripheral/src/ch32v30x_gpio.o + .debug_loc 0x0000000000016be5 0x61 ./Peripheral/src/ch32v30x_misc.o + .debug_loc 0x0000000000016c46 0x278 ./Peripheral/src/ch32v30x_pwr.o + .debug_loc 0x0000000000016ebe 0xadb ./Peripheral/src/ch32v30x_rcc.o + .debug_loc 0x0000000000017999 0x377 ./Peripheral/src/ch32v30x_rtc.o + .debug_loc 0x0000000000017d10 0x598 ./Peripheral/src/ch32v30x_spi.o + .debug_loc 0x00000000000182a8 0x779 ./Peripheral/src/ch32v30x_usart.o + .debug_loc 0x0000000000018a21 0x177 ./Debug/debug.o + +.debug_aranges 0x0000000000000000 0x1348 + .debug_aranges + 0x0000000000000000 0x28 ./User/util/hexdump.o + .debug_aranges + 0x0000000000000028 0x20 ./User/meshcore/packets/ack.o + .debug_aranges + 0x0000000000000048 0x48 ./User/meshcore/packets/advert.o + .debug_aranges + 0x0000000000000090 0x38 ./User/meshcore/packets/anonymous.o + .debug_aranges + 0x00000000000000c8 0x40 ./User/meshcore/packets/control.o + .debug_aranges + 0x0000000000000108 0x90 ./User/meshcore/packets/encrypted.o + .debug_aranges + 0x0000000000000198 0x30 ./User/meshcore/packets/group.o + .debug_aranges + 0x00000000000001c8 0x20 ./User/meshcore/meshcore.o + .debug_aranges + 0x00000000000001e8 0x60 ./User/meshcore/meshframing.o + .debug_aranges + 0x0000000000000248 0x18 ./User/meshcore/stats.o + .debug_aranges + 0x0000000000000260 0x58 ./User/lib/rtc/rtc.o + .debug_aranges + 0x00000000000002b8 0xc0 ./User/lib/monocypher/monocypher-ed25519.o + .debug_aranges + 0x0000000000000378 0x350 ./User/lib/monocypher/monocypher.o + .debug_aranges + 0x00000000000006c8 0xa8 ./User/lib/cifra/aes.o + .debug_aranges + 0x0000000000000770 0x40 ./User/lib/cifra/blockwise.o + .debug_aranges + 0x00000000000007b0 0x20 ./User/lib/cifra/chash.o + .debug_aranges + 0x00000000000007d0 0x40 ./User/lib/cifra/hmac.o + .debug_aranges + 0x0000000000000810 0x48 ./User/lib/cifra/sha256.o + .debug_aranges + 0x0000000000000858 0x68 ./User/lib/adc/temperature.o + .debug_aranges + 0x00000000000008c0 0x78 ./User/lib/config.o + .debug_aranges + 0x0000000000000938 0x28 ./User/ch32v30x_it.o + .debug_aranges + 0x0000000000000960 0x30 ./User/main.o + .debug_aranges + 0x0000000000000990 0x1b8 ./User/sx1262.o + .debug_aranges + 0x0000000000000b48 0x28 ./User/system_ch32v30x.o + .debug_aranges + 0x0000000000000b70 0x30 ./Startup/startup_ch32v30x_D8C.o + .debug_aranges + 0x0000000000000ba0 0x150 ./Peripheral/src/ch32v30x_adc.o + .debug_aranges + 0x0000000000000cf0 0x78 ./Peripheral/src/ch32v30x_bkp.o + .debug_aranges + 0x0000000000000d68 0x48 ./Peripheral/src/ch32v30x_dbgmcu.o + .debug_aranges + 0x0000000000000db0 0xb0 ./Peripheral/src/ch32v30x_gpio.o + .debug_aranges + 0x0000000000000e60 0x28 ./Peripheral/src/ch32v30x_misc.o + .debug_aranges + 0x0000000000000e88 0x88 ./Peripheral/src/ch32v30x_pwr.o + .debug_aranges + 0x0000000000000f10 0x1a8 ./Peripheral/src/ch32v30x_rcc.o + .debug_aranges + 0x00000000000010b8 0x80 ./Peripheral/src/ch32v30x_rtc.o + .debug_aranges + 0x0000000000001138 0xd0 ./Peripheral/src/ch32v30x_spi.o + .debug_aranges + 0x0000000000001208 0xf0 ./Peripheral/src/ch32v30x_usart.o + .debug_aranges + 0x00000000000012f8 0x50 ./Debug/debug.o + +.debug_ranges 0x0000000000000000 0x4ea0 + .debug_ranges 0x0000000000000000 0xb0 ./User/util/hexdump.o + .debug_ranges 0x00000000000000b0 0x10 ./User/meshcore/packets/ack.o + .debug_ranges 0x00000000000000c0 0x50 ./User/meshcore/packets/advert.o + .debug_ranges 0x0000000000000110 0x88 ./User/meshcore/packets/anonymous.o + .debug_ranges 0x0000000000000198 0x48 ./User/meshcore/packets/control.o + .debug_ranges 0x00000000000001e0 0xe8 ./User/meshcore/packets/encrypted.o + .debug_ranges 0x00000000000002c8 0x20 ./User/meshcore/packets/group.o + .debug_ranges 0x00000000000002e8 0x10 ./User/meshcore/meshcore.o + .debug_ranges 0x00000000000002f8 0x148 ./User/meshcore/meshframing.o + .debug_ranges 0x0000000000000440 0x90 ./User/lib/rtc/rtc.o + .debug_ranges 0x00000000000004d0 0x5d0 ./User/lib/monocypher/monocypher-ed25519.o + .debug_ranges 0x0000000000000aa0 0x30a8 ./User/lib/monocypher/monocypher.o + .debug_ranges 0x0000000000003b48 0x2b8 ./User/lib/cifra/aes.o + .debug_ranges 0x0000000000003e00 0xa8 ./User/lib/cifra/blockwise.o + .debug_ranges 0x0000000000003ea8 0x10 ./User/lib/cifra/chash.o + .debug_ranges 0x0000000000003eb8 0x78 ./User/lib/cifra/hmac.o + .debug_ranges 0x0000000000003f30 0x1c0 ./User/lib/cifra/sha256.o + .debug_ranges 0x00000000000040f0 0x58 ./User/lib/adc/temperature.o + .debug_ranges 0x0000000000004148 0x1d8 ./User/lib/config.o + .debug_ranges 0x0000000000004320 0x18 ./User/ch32v30x_it.o + .debug_ranges 0x0000000000004338 0x98 ./User/main.o + .debug_ranges 0x00000000000043d0 0x2c8 ./User/sx1262.o + .debug_ranges 0x0000000000004698 0x38 ./User/system_ch32v30x.o + .debug_ranges 0x00000000000046d0 0x28 ./Startup/startup_ch32v30x_D8C.o + .debug_ranges 0x00000000000046f8 0x140 ./Peripheral/src/ch32v30x_adc.o + .debug_ranges 0x0000000000004838 0x68 ./Peripheral/src/ch32v30x_bkp.o + .debug_ranges 0x00000000000048a0 0x50 ./Peripheral/src/ch32v30x_dbgmcu.o + .debug_ranges 0x00000000000048f0 0xa0 ./Peripheral/src/ch32v30x_gpio.o + .debug_ranges 0x0000000000004990 0x30 ./Peripheral/src/ch32v30x_misc.o + .debug_ranges 0x00000000000049c0 0xf8 ./Peripheral/src/ch32v30x_pwr.o + .debug_ranges 0x0000000000004ab8 0x198 ./Peripheral/src/ch32v30x_rcc.o + .debug_ranges 0x0000000000004c50 0x70 ./Peripheral/src/ch32v30x_rtc.o + .debug_ranges 0x0000000000004cc0 0xc0 ./Peripheral/src/ch32v30x_spi.o + .debug_ranges 0x0000000000004d80 0xe0 ./Peripheral/src/ch32v30x_usart.o + .debug_ranges 0x0000000000004e60 0x40 ./Debug/debug.o + +.debug_line 0x0000000000000000 0x2a966 + .debug_line 0x0000000000000000 0x4ce ./User/util/hexdump.o + .debug_line 0x00000000000004ce 0x3e4 ./User/meshcore/packets/ack.o + .debug_line 0x00000000000008b2 0xd3d ./User/meshcore/packets/advert.o + .debug_line 0x00000000000015ef 0xfd3 ./User/meshcore/packets/anonymous.o + .debug_line 0x00000000000025c2 0x9f7 ./User/meshcore/packets/control.o + .debug_line 0x0000000000002fb9 0x2301 ./User/meshcore/packets/encrypted.o + .debug_line 0x00000000000052ba 0x926 ./User/meshcore/packets/group.o + .debug_line 0x0000000000005be0 0x6f1 ./User/meshcore/meshcore.o + .debug_line 0x00000000000062d1 0x14da ./User/meshcore/meshframing.o + .debug_line 0x00000000000077ab 0x1af ./User/meshcore/stats.o + .debug_line 0x000000000000795a 0xece ./User/lib/rtc/rtc.o + .debug_line 0x0000000000008828 0x1d01 ./User/lib/monocypher/monocypher-ed25519.o + .debug_line 0x000000000000a529 0xe780 ./User/lib/monocypher/monocypher.o + .debug_line 0x0000000000018ca9 0x1360 ./User/lib/cifra/aes.o + .debug_line 0x000000000001a009 0x880 ./User/lib/cifra/blockwise.o + .debug_line 0x000000000001a889 0x325 ./User/lib/cifra/chash.o + .debug_line 0x000000000001abae 0x6d1 ./User/lib/cifra/hmac.o + .debug_line 0x000000000001b27f 0xac7 ./User/lib/cifra/sha256.o + .debug_line 0x000000000001bd46 0x9e2 ./User/lib/adc/temperature.o + .debug_line 0x000000000001c728 0xebe ./User/lib/config.o + .debug_line 0x000000000001d5e6 0x301 ./User/ch32v30x_it.o + .debug_line 0x000000000001d8e7 0xc86 ./User/main.o + .debug_line 0x000000000001e56d 0x2bac ./User/sx1262.o + .debug_line 0x0000000000021119 0x94c ./User/system_ch32v30x.o + .debug_line 0x0000000000021a65 0x122 ./Startup/startup_ch32v30x_D8C.o + .debug_line 0x0000000000021b87 0x18cb ./Peripheral/src/ch32v30x_adc.o + .debug_line 0x0000000000023452 0x6c8 ./Peripheral/src/ch32v30x_bkp.o + .debug_line 0x0000000000023b1a 0x3dc ./Peripheral/src/ch32v30x_dbgmcu.o + .debug_line 0x0000000000023ef6 0x12b5 ./Peripheral/src/ch32v30x_gpio.o + .debug_line 0x00000000000251ab 0x433 ./Peripheral/src/ch32v30x_misc.o + .debug_line 0x00000000000255de 0xb1f ./Peripheral/src/ch32v30x_pwr.o + .debug_line 0x00000000000260fd 0x19e7 ./Peripheral/src/ch32v30x_rcc.o + .debug_line 0x0000000000027ae4 0xa03 ./Peripheral/src/ch32v30x_rtc.o + .debug_line 0x00000000000284e7 0xd8e ./Peripheral/src/ch32v30x_spi.o + .debug_line 0x0000000000029275 0xf54 ./Peripheral/src/ch32v30x_usart.o + .debug_line 0x000000000002a1c9 0x79d ./Debug/debug.o + +.debug_str 0x0000000000000000 0x5bf3 + .debug_str 0x0000000000000000 0x54d ./User/util/hexdump.o + 0x5f3 (size before relaxing) + .debug_str 0x000000000000054d 0x4eb ./User/meshcore/packets/ack.o + 0xb17 (size before relaxing) + .debug_str 0x0000000000000a38 0x37b ./User/meshcore/packets/advert.o + 0xddd (size before relaxing) + .debug_str 0x0000000000000db3 0x183 ./User/meshcore/packets/anonymous.o + 0xced (size before relaxing) + .debug_str 0x0000000000000f36 0x292 ./User/meshcore/packets/control.o + 0xce8 (size before relaxing) + .debug_str 0x00000000000011c8 0x46d ./User/meshcore/packets/encrypted.o + 0x1155 (size before relaxing) + .debug_str 0x0000000000001635 0xb7 ./User/meshcore/packets/group.o + 0xb6f (size before relaxing) + .debug_str 0x00000000000016ec 0x4d ./User/meshcore/meshcore.o + 0xcc8 (size before relaxing) + .debug_str 0x0000000000001739 0x302 ./User/meshcore/meshframing.o + 0xff4 (size before relaxing) + .debug_str 0x0000000000001a3b 0x19 ./User/meshcore/stats.o + 0x30a (size before relaxing) + .debug_str 0x0000000000001a54 0x7c1 ./User/lib/rtc/rtc.o + 0xe11 (size before relaxing) + .debug_str 0x0000000000002215 0x333 ./User/lib/monocypher/monocypher-ed25519.o + 0x5de (size before relaxing) + .debug_str 0x0000000000002548 0xa63 ./User/lib/monocypher/monocypher.o + 0xec9 (size before relaxing) + .debug_str 0x0000000000002fab 0x156 ./User/lib/cifra/aes.o + 0x7cb (size before relaxing) + .debug_str 0x0000000000003101 0x117 ./User/lib/cifra/blockwise.o + 0x6f3 (size before relaxing) + .debug_str 0x0000000000003218 0x2f ./User/lib/cifra/chash.o + 0x67a (size before relaxing) + .debug_str 0x0000000000003247 0x84 ./User/lib/cifra/hmac.o + 0x733 (size before relaxing) + .debug_str 0x00000000000032cb 0x81 ./User/lib/cifra/sha256.o + 0x785 (size before relaxing) + .debug_str 0x000000000000334c 0x354 ./User/lib/adc/temperature.o + 0x9f0 (size before relaxing) + .debug_str 0x00000000000036a0 0x21b ./User/lib/config.o + 0xc4d (size before relaxing) + .debug_str 0x00000000000038bb 0x34 ./User/ch32v30x_it.o + 0x692 (size before relaxing) + .debug_str 0x00000000000038ef 0x494 ./User/main.o + 0x1147 (size before relaxing) + .debug_str 0x0000000000003d83 0x560 ./User/sx1262.o + 0xfe5 (size before relaxing) + .debug_str 0x00000000000042e3 0x109 ./User/system_ch32v30x.o + 0x6f7 (size before relaxing) + .debug_str 0x00000000000043ec 0x2e ./Startup/startup_ch32v30x_D8C.o + 0x67 (size before relaxing) + .debug_str 0x000000000000441a 0x38c ./Peripheral/src/ch32v30x_adc.o + 0xc2e (size before relaxing) + .debug_str 0x00000000000047a6 0x382 ./Peripheral/src/ch32v30x_bkp.o + 0xab2 (size before relaxing) + .debug_str 0x0000000000004b28 0x7e ./Peripheral/src/ch32v30x_dbgmcu.o + 0x653 (size before relaxing) + .debug_str 0x0000000000004ba6 0x222 ./Peripheral/src/ch32v30x_gpio.o + 0x9bd (size before relaxing) + .debug_str 0x0000000000004dc8 0x9c ./Peripheral/src/ch32v30x_misc.o + 0xcc6 (size before relaxing) + .debug_str 0x0000000000004e64 0x19b ./Peripheral/src/ch32v30x_pwr.o + 0x864 (size before relaxing) + .debug_str 0x0000000000004fff 0x51b ./Peripheral/src/ch32v30x_rcc.o + 0xcec (size before relaxing) + .debug_str 0x000000000000551a 0xf4 ./Peripheral/src/ch32v30x_rtc.o + 0x813 (size before relaxing) + .debug_str 0x000000000000560e 0x24c ./Peripheral/src/ch32v30x_spi.o + 0xa9c (size before relaxing) + .debug_str 0x000000000000585a 0x31a ./Peripheral/src/ch32v30x_usart.o + 0xb07 (size before relaxing) + .debug_str 0x0000000000005b74 0x7f ./Debug/debug.o + 0x92e (size before relaxing) + +.comment 0x0000000000000000 0x33 + .comment 0x0000000000000000 0x33 ./User/util/hexdump.o + 0x34 (size before relaxing) + .comment 0x0000000000000033 0x34 ./User/meshcore/packets/ack.o + .comment 0x0000000000000033 0x34 ./User/meshcore/packets/advert.o + .comment 0x0000000000000033 0x34 ./User/meshcore/packets/anonymous.o + .comment 0x0000000000000033 0x34 ./User/meshcore/packets/control.o + .comment 0x0000000000000033 0x34 ./User/meshcore/packets/encrypted.o + .comment 0x0000000000000033 0x34 ./User/meshcore/packets/group.o + .comment 0x0000000000000033 0x34 ./User/meshcore/meshcore.o + .comment 0x0000000000000033 0x34 ./User/meshcore/meshframing.o + .comment 0x0000000000000033 0x34 ./User/meshcore/stats.o + .comment 0x0000000000000033 0x34 ./User/lib/rtc/rtc.o + .comment 0x0000000000000033 0x34 ./User/lib/monocypher/monocypher-ed25519.o + .comment 0x0000000000000033 0x34 ./User/lib/monocypher/monocypher.o + .comment 0x0000000000000033 0x34 ./User/lib/cifra/aes.o + .comment 0x0000000000000033 0x34 ./User/lib/cifra/blockwise.o + .comment 0x0000000000000033 0x34 ./User/lib/cifra/chash.o + .comment 0x0000000000000033 0x34 ./User/lib/cifra/hmac.o + .comment 0x0000000000000033 0x34 ./User/lib/cifra/sha256.o + .comment 0x0000000000000033 0x34 ./User/lib/adc/temperature.o + .comment 0x0000000000000033 0x34 ./User/lib/config.o + .comment 0x0000000000000033 0x34 ./User/ch32v30x_it.o + .comment 0x0000000000000033 0x34 ./User/main.o + .comment 0x0000000000000033 0x34 ./User/sx1262.o + .comment 0x0000000000000033 0x34 ./User/system_ch32v30x.o + .comment 0x0000000000000033 0x34 ./Peripheral/src/ch32v30x_adc.o + .comment 0x0000000000000033 0x34 ./Peripheral/src/ch32v30x_bkp.o + .comment 0x0000000000000033 0x34 ./Peripheral/src/ch32v30x_dbgmcu.o + .comment 0x0000000000000033 0x34 ./Peripheral/src/ch32v30x_gpio.o + .comment 0x0000000000000033 0x34 ./Peripheral/src/ch32v30x_misc.o + .comment 0x0000000000000033 0x34 ./Peripheral/src/ch32v30x_pwr.o + .comment 0x0000000000000033 0x34 ./Peripheral/src/ch32v30x_rcc.o + .comment 0x0000000000000033 0x34 ./Peripheral/src/ch32v30x_rtc.o + .comment 0x0000000000000033 0x34 ./Peripheral/src/ch32v30x_spi.o + .comment 0x0000000000000033 0x34 ./Peripheral/src/ch32v30x_usart.o + .comment 0x0000000000000033 0x34 ./Debug/debug.o + +.debug_frame 0x0000000000000000 0x4d90 + .debug_frame 0x0000000000000000 0x88 ./User/util/hexdump.o + .debug_frame 0x0000000000000088 0x3c ./User/meshcore/packets/ack.o + .debug_frame 0x00000000000000c4 0x114 ./User/meshcore/packets/advert.o + .debug_frame 0x00000000000001d8 0xc0 ./User/meshcore/packets/anonymous.o + .debug_frame 0x0000000000000298 0xbc ./User/meshcore/packets/control.o + .debug_frame 0x0000000000000354 0x258 ./User/meshcore/packets/encrypted.o + .debug_frame 0x00000000000005ac 0xa0 ./User/meshcore/packets/group.o + .debug_frame 0x000000000000064c 0x34 ./User/meshcore/meshcore.o + .debug_frame 0x0000000000000680 0x1d8 ./User/meshcore/meshframing.o + .debug_frame 0x0000000000000858 0x168 ./User/lib/rtc/rtc.o + .debug_frame 0x00000000000009c0 0x32c ./User/lib/monocypher/monocypher-ed25519.o + .debug_frame 0x0000000000000cec 0x104c ./User/lib/monocypher/monocypher.o + .debug_frame 0x0000000000001d38 0x24c ./User/lib/cifra/aes.o + .debug_frame 0x0000000000001f84 0x100 ./User/lib/cifra/blockwise.o + .debug_frame 0x0000000000002084 0x34 ./User/lib/cifra/chash.o + .debug_frame 0x00000000000020b8 0xd8 ./User/lib/cifra/hmac.o + .debug_frame 0x0000000000002190 0x100 ./User/lib/cifra/sha256.o + .debug_frame 0x0000000000002290 0x12c ./User/lib/adc/temperature.o + .debug_frame 0x00000000000023bc 0x19c ./User/lib/config.o + .debug_frame 0x0000000000002558 0x30 ./User/ch32v30x_it.o + .debug_frame 0x0000000000002588 0x7c ./User/main.o + .debug_frame 0x0000000000002604 0x794 ./User/sx1262.o + .debug_frame 0x0000000000002d98 0x3c ./User/system_ch32v30x.o + .debug_frame 0x0000000000002dd4 0x2b4 ./Peripheral/src/ch32v30x_adc.o + .debug_frame 0x0000000000003088 0xec ./Peripheral/src/ch32v30x_bkp.o + .debug_frame 0x0000000000003174 0x70 ./Peripheral/src/ch32v30x_dbgmcu.o + .debug_frame 0x00000000000031e4 0x174 ./Peripheral/src/ch32v30x_gpio.o + .debug_frame 0x0000000000003358 0x30 ./Peripheral/src/ch32v30x_misc.o + .debug_frame 0x0000000000003388 0xfc ./Peripheral/src/ch32v30x_pwr.o + .debug_frame 0x0000000000003484 0x344 ./Peripheral/src/ch32v30x_rcc.o + .debug_frame 0x00000000000037c8 0x12c ./Peripheral/src/ch32v30x_rtc.o + .debug_frame 0x00000000000038f4 0x1a8 ./Peripheral/src/ch32v30x_spi.o + .debug_frame 0x0000000000003a9c 0x1e4 ./Peripheral/src/ch32v30x_usart.o + .debug_frame 0x0000000000003c80 0xb8 ./Debug/debug.o + .debug_frame 0x0000000000003d38 0x20 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/rv32imacxw/ilp32/libgcc.a(_ashldi3.o) + .debug_frame 0x0000000000003d58 0x28 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-abort.o) + .debug_frame 0x0000000000003d80 0x30 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-atoi.o) + .debug_frame 0x0000000000003db0 0x78 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-locale.o) + .debug_frame 0x0000000000003e28 0x30 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libg_nano.a(lib_a-malloc.o) + .debug_frame 0x0000000000003e58 0x38 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded 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/usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libnosys.a(lseek.o) + 0x24 (size before relaxing) + .stab 0x000000000000009c 0x18 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libnosys.a(read.o) + 0x24 (size before relaxing) + +.stabstr 0x0000000000000000 0x183 + .stabstr 0x0000000000000000 0x183 /usr/share/MRS2/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC/bin/../lib/gcc/riscv-none-embed/8.2.0/../../../../riscv-none-embed/lib/rv32imacxw/ilp32/libnosys.a(close.o) diff --git a/obj/objects.mk b/obj/objects.mk new file mode 100644 index 0000000..a770626 --- /dev/null +++ b/obj/objects.mk @@ -0,0 +1,9 @@ +################################################################################ +# MRS Version: 2.4.0 +# Automatically-generated file. Do not edit! +################################################################################ +USER_OBJS := + +USER_OBJS_ESCAPE := + +LIBS := -lm \ No newline at end of file diff --git a/obj/sources.mk b/obj/sources.mk new file mode 100644 index 0000000..db59867 --- /dev/null +++ b/obj/sources.mk @@ -0,0 +1,43 @@ +################################################################################ +# MRS Version: 2.4.0 +# Automatically-generated file. Do not edit! +################################################################################ + +S_DEPS := +S_UPPER_DEPS := +ASM_DEPS := +ASM_UPPER_DEPS := +C_DEPS := +OBJS := +DIR_OBJS := +DIR_DEPS := +DIR_EXPANDS := +ELF_SRCS := +OBJ_SRCS := +O_SRCS := +S_SRCS := +S_UPPER_SRCS := +ASM_SRCS := +ASM_UPPER_SRCS := +C_SRCS := +SECONDARY_FLASH := +SECONDARY_LIST := +SECONDARY_SIZE := + +CALLGRAPH_DOT := callgraph.dot \ +# Every subdirectory with source files must be described here +SUBDIRS := \ +Core \ +Debug \ +Peripheral/src \ +Startup \ +User \ +User/lib \ +User/lib/adc \ +User/lib/cifra \ +User/lib/monocypher \ +User/lib/rtc \ +User/lib/telemetry \ +User/meshcore \ +User/meshcore/packets \ +User/util \