finish es8311 manual
This commit is contained in:
+249
-86
@@ -3,26 +3,40 @@
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#include <stddef.h>
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#include <stdint.h>
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#define ES8311_BIT(pos) (1U << (pos))
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#define ES8311_FLD(pos, val) ((val) << (pos))
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// ----------------------
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// I2C
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// ----------------------
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#define ES8311_RESET_REG00 0x00 /*reset digital,csm,clock manager etc.*/
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#define ES8311_RESET_CSM_OFF (0 << 7)
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#define ES8311_RESET_CSM_ON (1 << 7)
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#define ES8311_RESET_CSM_ON ES8311_BIT(7)
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#define ES8311_RESET_CSM_MSC_SLAVE (0 << 6)
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#define ES8311_RESET_CSM_MSC_MASTER (1 << 6)
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#define ES8311_RESET_CSM_MSC_MASTER ES8311_BIT(6)
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// #define ES8311_RESET_CSM_MSC_SLAVE (0 << 5)
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// #define ES8311_RESET_CSM_MSC_MASTER (1 << 5)
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// #define ES8311_RESET_CSM_MSC_MASTER ES8311_BIT(5)
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#define ES8311_RESET_DIGITAL_RUN (0 << 4)
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#define ES8311_RESET_DIGITAL_RST (1 << 4)
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#define ES8311_RESET_DIGITAL_RST ES8311_BIT(4)
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#define ES8311_RESET_CLOCK_MANAGER_RUN (0 << 3)
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#define ES8311_RESET_CLOCK_MANAGER_RST (1 << 3)
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#define ES8311_RESET_CLOCK_MANAGER_RST ES8311_BIT(3)
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#define ES8311_RESET_MASTER_RUN (0 << 2)
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#define ES8311_RESET_MASTER_RST (1 << 2)
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#define ES8311_RESET_MASTER_RST ES8311_BIT(2)
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#define ES8311_RESET_ADC_DIGITAL_RUN (0 << 1)
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#define ES8311_RESET_ADC_DIGITAL_RST (1 << 1)
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#define ES8311_RESET_DAC_DIGITAL_RUN (0 << 0)
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#define ES8311_RESET_DAC_DIGITAL_RST (1 << 0)
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#define ES8311_RESET_ADC_DIGITAL_RST ES8311_BIT(1)
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#define ES8311_RESET_DAC_DIGITAL_RUN (0)
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#define ES8311_RESET_DAC_DIGITAL_RST ES8311_BIT(0)
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typedef struct {
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uint32_t b0;
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uint32_t a1;
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uint32_t a2;
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uint32_t b1;
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uint32_t b2;
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} es8311_eq_t;
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void es8311_set_eq(const es8311_eq_t *eq);
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/*
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* Clock Scheme Register definition
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@@ -30,24 +44,40 @@
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#define ES8311_CLK_MANAGER_REG01 \
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0x01 /* select clk src for mclk, enable clock for codec */
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#define ES8311_CLK_MANAGER_REG01_MCLK_SEL_FROM_MCLK (0 << 7)
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#define ES8311_CLK_MANAGER_REG01_MCLK_SEL_FROM_BCLK (1 << 7)
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#define ES8311_CLK_MANAGER_REG01_MCLK_SEL_FROM_BCLK ES8311_BIT(7)
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#define ES8311_CLK_MANAGER_REG01_MCLK_INV_OFF (0 << 6)
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#define ES8311_CLK_MANAGER_REG01_MCLK_INV_ON (1 << 6)
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#define ES8311_CLK_MANAGER_REG01_MCLK_INV_ON ES8311_BIT(6)
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#define ES8311_CLK_MANAGER_REG01_MCLK_OFF (0 << 5)
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#define ES8311_CLK_MANAGER_REG01_MCLK_ON (1 << 5)
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#define ES8311_CLK_MANAGER_REG01_MCLK_ON ES8311_BIT(5)
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#define ES8311_CLK_MANAGER_REG01_BCLK_OFF (0 << 4)
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#define ES8311_CLK_MANAGER_REG01_BCLK_ON (1 << 4)
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#define ES8311_CLK_MANAGER_REG01_BCLK_ON ES8311_BIT(4)
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#define ES8311_CLK_MANAGER_REG02 0x02 /* clk divider and clk multiplier */
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#define ES8311_CLK_MANAGER_REG03 0x03 /* adc fsmode and osr */
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#define ES8311_CLK_MANAGER_REG03_ADC_FSMODE_SINGLE_SPEED (0 << 6)
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#define ES8311_CLK_MANAGER_REG03_ADC_FSMODE_DOUBLE_SPEED ES8311_BIT(6)
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/*
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ADC_OSR 5:0 ADC delta sigma over sample rate
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0~14 – not use
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15 – 60*fs(ss) / (ds not support)
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16 – 64*fs(ss) / 32*fs(ds) (default)
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...
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31 – 124*fs(ss) / 62*fs(ds)
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32 – 128*fs(ss) / 64*fs(ds)
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...
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63 – 252*fs(ss) / 126*fs(ds)
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*/
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#define ES8311_CLK_MANAGER_REG04 0x04 /* dac osr */
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#define ES8311_CLK_MANAGER_REG05 0x05 /* clk divier for adc and dac */
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#define ES8311_CLK_MANAGER_REG06 0x06 /* bclk inverter and divider */
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#define ES8311_CLK_MANAGER_REG06_CONTINUAL_BCLK (0 << 6)
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#define ES8311_CLK_MANAGER_REG06_WHEN_DATA_TRANSFER_BCLK (1 << 6)
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#define ES8311_CLK_MANAGER_REG06_WHEN_DATA_TRANSFER_BCLK ES8311_BIT(6)
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#define ES8311_CLK_MANAGER_REG06_NORMAL_BCLK (0 << 5)
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#define ES8311_CLK_MANAGER_REG06_INVERT_BCLK (1 << 5)
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#define ES8311_CLK_MANAGER_REG06_INVERT_BCLK ES8311_BIT(5)
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_1 0x00
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_2 0x01
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#define ES8311_CLK_MANAGER_REG06_DIV_BCLK_3 0x02
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@@ -84,42 +114,42 @@
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#define ES8311_CLK_MANAGER_REG07 0x07 /* tri-state, lrck divider */
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#define ES8311_CLK_MANAGER_REG07_BCLK_LRCLK_NORMAL_MODE (0 << 5)
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#define ES8311_CLK_MANAGER_REG07_BCLK_LRCLK_TRISTATE_MODE (1 << 5)
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#define ES8311_CLK_MANAGER_REG07_BCLK_LRCLK_TRISTATE_MODE ES8311_BIT(5)
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#define ES8311_CLK_MANAGER_REG07_ADCDAT_NORMAL_MODE (0 << 4)
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#define ES8311_CLK_MANAGER_REG07_ADCDAT_TRISTATE_MODE (1 << 4)
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#define ES8311_CLK_MANAGER_REG07_ADCDAT_TRISTATE_MODE ES8311_BIT(4)
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#define ES8311_CLK_MANAGER_REG08 0x08 /* lrck divider */
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/*
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* SDP
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*/
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#define ES8311_SDPIN_REG 0x09
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#define ES8311_SDPIN_SEL_LEFT_TO_DAC (0 << 7)
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#define ES8311_SDPIN_SEL_RIGHT_TO_DAC (1 << 7)
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#define ES8311_SDPIN_SEL_RIGHT_TO_DAC ES8311_BIT(7)
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#define ES8311_SDPIN_UNMUTE (0 << 6)
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#define ES8311_SDPIN_MUTE (1 << 6)
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#define ES8311_SDPIN_MUTE ES8311_BIT(6)
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#define ES8311_SDPIN_LR_NORMAL_POLARITY (0 << 5)
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#define ES8311_SDPIN_LR_INVERTED_POLARITY (1 << 5)
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#define ES8311_SDPIN_LR_INVERTED_POLARITY ES8311_BIT(5)
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#define ES8311_SDPIN_WORD_24BIT (0 << 2)
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#define ES8311_SDPIN_WORD_20BIT (1 << 2)
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#define ES8311_SDPIN_WORD_20BIT ES8311_BIT(2)
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#define ES8311_SDPIN_WORD_18BIT (2 << 2)
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#define ES8311_SDPIN_WORD_16BIT (3 << 2)
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#define ES8311_SDPIN_WORD_32BIT (4 << 2)
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#define ES8311_SDPIN_FORMAT_I2S (0 << 0)
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#define ES8311_SDPIN_FORMAT_LEFT_JUSTIFY_SERIAL (1 << 0)
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#define ES8311_SDPIN_FORMAT_PCM (3 << 0)
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#define ES8311_SDPIN_FORMAT_I2S (0)
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#define ES8311_SDPIN_FORMAT_LEFT_JUSTIFY_SERIAL ES8311_BIT(0)
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#define ES8311_SDPIN_FORMAT_PCM (0)
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#define ES8311_SDPOUT_REG 0x0A
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#define ES8311_SDPOUT_UNMUTE (0 << 6)
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#define ES8311_SDPOUT_MUTE (1 << 6)
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#define ES8311_SDPOUT_MUTE ES8311_BIT(6)
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#define ES8311_SDPOUT_LR_NORMAL_POLARITY (0 << 5)
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#define ES8311_SDPOUT_LR_INVERTED_POLARITY (1 << 5)
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#define ES8311_SDPOUT_LR_INVERTED_POLARITY ES8311_BIT(5)
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#define ES8311_SDPOUT_WORD_24BIT (0 << 2)
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#define ES8311_SDPOUT_WORD_20BIT (1 << 2)
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#define ES8311_SDPOUT_WORD_20BIT ES8311_BIT(2)
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#define ES8311_SDPOUT_WORD_18BIT (2 << 2)
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#define ES8311_SDPOUT_WORD_16BIT (3 << 2)
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#define ES8311_SDPOUT_WORD_32BIT (4 << 2)
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#define ES8311_SDPOUT_FORMAT_I2S (0 << 0)
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#define ES8311_SDPOUT_FORMAT_LEFT_JUSTIFY_SERIAL (1 << 0)
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#define ES8311_SDPOUT_FORMAT_PCM (3 << 0)
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#define ES8311_SDPOUT_FORMAT_I2S (0)
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#define ES8311_SDPOUT_FORMAT_LEFT_JUSTIFY_SERIAL ES8311_BIT(0)
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#define ES8311_SDPOUT_FORMAT_PCM (0)
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/*
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* SYSTEM
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*/
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@@ -128,15 +158,15 @@
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#define ES8311_SYSTEM_REG0D 0x0D /* system, power up/down */
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#define ES8311_SYSTEM_REG0D_ANALOG_ENABLED (0 << 7)
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#define ES8311_SYSTEM_REG0D_ANALOG_DISABLED (1 << 7)
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#define ES8311_SYSTEM_REG0D_ANALOG_DISABLED ES8311_BIT(7)
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#define ES8311_SYSTEM_REG0D_ANALOG_BIAS_ENABLED (0 << 6)
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#define ES8311_SYSTEM_REG0D_ANALOG_BIAS_DISABLED (1 << 6)
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#define ES8311_SYSTEM_REG0D_ANALOG_BIAS_DISABLED ES8311_BIT(6)
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#define ES8311_SYSTEM_REG0D_ANALOG_ADC_BIAS_ENABLED (0 << 5)
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#define ES8311_SYSTEM_REG0D_ANALOG_ADC_BIAS_DISABLED (1 << 5)
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#define ES8311_SYSTEM_REG0D_ANALOG_ADC_BIAS_DISABLED ES8311_BIT(5)
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#define ES8311_SYSTEM_REG0D_ANALOG_ADC_REFERENCE_ENABLED (0 << 4)
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#define ES8311_SYSTEM_REG0D_ANALOG_ADC_REFERENCE_DISABLED (1 << 4)
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#define ES8311_SYSTEM_REG0D_ANALOG_ADC_REFERENCE_DISABLED ES8311_BIT(4)
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#define ES8311_SYSTEM_REG0D_ANALOG_DAC_REFERENCE_ENABLED (0 << 3)
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#define ES8311_SYSTEM_REG0D_ANALOG_DAC_REFERENCE_DISABLED (1 << 3)
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#define ES8311_SYSTEM_REG0D_ANALOG_DAC_REFERENCE_DISABLED ES8311_BIT(3)
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#define ES8311_SYSTEM_REG0D_VMID_POWER_DOWN 0x00
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#define ES8311_SYSTEM_REG0D_VMID_START_NORMAL_SPEED 0x01
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#define ES8311_SYSTEM_REG0D_VMID_NORMAL 0x02
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@@ -145,31 +175,31 @@
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#define ES8311_SYSTEM_REG0E 0x0E /* system, power up/down */
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#define ES8311_SYSTEM_REG0E_PGA_ENABLE (0 << 6)
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#define ES8311_SYSTEM_REG0E_PGA_DISABLE (1 << 6)
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#define ES8311_SYSTEM_REG0E_PGA_DISABLE ES8311_BIT(6)
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#define ES8311_SYSTEM_REG0E_PDN_MOD_ENABLE (0 << 5)
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#define ES8311_SYSTEM_REG0E_PDN_MOD_DISABLE (1 << 5)
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#define ES8311_SYSTEM_REG0E_PDN_MOD_DISABLE ES8311_BIT(5)
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#define ES8311_SYSTEM_REG0E_MOD_NORMAL (0 << 4)
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#define ES8311_SYSTEM_REG0E_MOD_RESET (1 << 4)
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#define ES8311_SYSTEM_REG0E_MOD_RESET ES8311_BIT(4)
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#define ES8311_SYSTEM_REG0F 0x0F /* system, low power */
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#define ES8311_SYSTEM_REG0F_DAC_NORMAL_MODE (0 << 7)
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#define ES8311_SYSTEM_REG0F_DAC_LOW_POWER_MODE (1 << 7)
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#define ES8311_SYSTEM_REG0F_DAC_LOW_POWER_MODE ES8311_BIT(7)
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#define ES8311_SYSTEM_REG0F_PGA_NORMAL_MODE (0 << 6)
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#define ES8311_SYSTEM_REG0F_PGA_LOW_POWER_MODE (1 << 6)
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#define ES8311_SYSTEM_REG0F_PGA_LOW_POWER_MODE ES8311_BIT(6)
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#define ES8311_SYSTEM_REG0F_PGA_OUTPUT_NORMAL_MODE (0 << 5)
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#define ES8311_SYSTEM_REG0F_PGA_OUTPUT_LOW_POWER_MODE (1 << 5)
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#define ES8311_SYSTEM_REG0F_PGA_OUTPUT_LOW_POWER_MODE ES8311_BIT(5)
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#define ES8311_SYSTEM_REG0F_VCMMOD_NORMAL_MODE (0 << 4)
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#define ES8311_SYSTEM_REG0F_VCMMOD_LOW_POWER_MODE (1 << 4)
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#define ES8311_SYSTEM_REG0F_VCMMOD_LOW_POWER_MODE ES8311_BIT(4)
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#define ES8311_SYSTEM_REG0F_ADC_REFERENCE_NORMAL_MODE (0 << 3)
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#define ES8311_SYSTEM_REG0F_ADC_REFERENCE_LOW_POWER_MODE (1 << 3)
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#define ES8311_SYSTEM_REG0F_ADC_REFERENCE_LOW_POWER_MODE ES8311_BIT(3)
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#define ES8311_SYSTEM_REG0F_DAC_REFERENCE_NORMAL_MODE (0 << 2)
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#define ES8311_SYSTEM_REG0F_DAC_REFERENCE_LOW_POWER_MODE (1 << 2)
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#define ES8311_SYSTEM_REG0F_DAC_REFERENCE_LOW_POWER_MODE ES8311_BIT(2)
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#define ES8311_SYSTEM_REG0F_FLASH_NORMAL_MODE (0 << 1)
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#define ES8311_SYSTEM_REG0F_FLASH_LOW_POWER_MODE (1 << 1)
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#define ES8311_SYSTEM_REG0F_INT1_NORMAL_MODE (0 << 0)
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#define ES8311_SYSTEM_REG0F_INT1_LOW_POWER_MODE (1 << 0)
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#define ES8311_SYSTEM_REG0F_FLASH_LOW_POWER_MODE ES8311_BIT(1)
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#define ES8311_SYSTEM_REG0F_INT1_NORMAL_MODE (0)
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#define ES8311_SYSTEM_REG0F_INT1_LOW_POWER_MODE ES8311_BIT(0)
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@@ -182,9 +212,9 @@
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0x14 /* system, select DMIC, select analog pga gain */
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#define ES8311_SYSTEM_REG14_DMIC_OFF (0 << 6)
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#define ES8311_SYSTEM_REG14_DMIC_AND_DMIC_SDA (1 << 6)
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#define ES8311_SYSTEM_REG14_DMIC_AND_DMIC_SDA ES8311_BIT(6)
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#define ES8311_SYSTEM_REG14_NO_MIC (0 << 4)
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#define ES8311_SYSTEM_REG14_MIC1 (1 << 4)
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#define ES8311_SYSTEM_REG14_MIC1 ES8311_BIT(4)
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#define ES8311_SYSTEM_REG14_MIC2 (2 << 4)
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#define ES8311_SYSTEM_REG14_MIC1_MIC2 (3 << 4)
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#define ES8311_SYSTEM_REG14_GAIN_0DB 0
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@@ -198,6 +228,8 @@
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#define ES8311_SYSTEM_REG14_GAIN_24DB 8
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#define ES8311_SYSTEM_REG14_GAIN_27DB 9
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#define ES8311_SYSTEM_REG14_GAIN_30DB 10
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#define ES8311_SYSTEM_REG14_DMIC_CLOCK_POSITIVE (0)
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#define ES8311_SYSTEM_REG14_DMIC_CLOCK_NEGATIVE ES8311_BIT(0)
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@@ -205,14 +237,44 @@
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* ADC
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*/
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#define ES8311_ADC_REG15 0x15 /* ADC, adc ramp rate, dmic sense */
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#define ES8311_ADC_REG15_RAMPRATE_DISABLE (0x00 << 4)
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#define ES8311_ADC_REG15_RAMPRATE_0_25_4LRCK (0x01 << 4)
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#define ES8311_ADC_REG15_RAMPRATE_0_25_8LRCK (0x02 << 4)
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#define ES8311_ADC_REG15_RAMPRATE_0_25_16LRCK (0x03 << 4)
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#define ES8311_ADC_REG15_RAMPRATE_0_25_32LRCK (0x04 << 4)
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#define ES8311_ADC_REG15_RAMPRATE_0_25_64LRCK (0x05 << 4)
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#define ES8311_ADC_REG15_RAMPRATE_0_25_128LRCK (0x06 << 4)
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#define ES8311_ADC_REG15_RAMPRATE_0_25_256LRCK (0x07 << 4)
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#define ES8311_ADC_REG15_RAMPRATE_0_25_512LRCK (0x08 << 4)
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#define ES8311_ADC_REG15_RAMPRATE_0_25_1024LRCK (0x09 << 4)
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#define ES8311_ADC_REG15_RAMPRATE_0_25_2048LRCK (0x0a << 4)
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#define ES8311_ADC_REG15_RAMPRATE_0_25_4096LRCK (0x0b << 4)
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#define ES8311_ADC_REG15_RAMPRATE_0_25_8192LRCK (0x0c << 4)
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#define ES8311_ADC_REG15_RAMPRATE_0_25_16384LRCK (0x0d << 4)
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#define ES8311_ADC_REG15_RAMPRATE_0_25_32768LRCK (0x0e << 4)
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#define ES8311_ADC_REG15_RAMPRATE_0_25_65536LRCK (0x0f << 4)
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#define ES8311_ADC_REG16 0x16 /* ADC */
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#define ES8311_ADC_REG16_ADC_RAM_CLR (1 << 3)
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#define ES8311_ADC_REG16_ADC_GAIN_0DB 0x00
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#define ES8311_ADC_REG16_ADC_GAIN_6DB 0x01
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#define ES8311_ADC_REG16_ADC_GAIN_12DB 0x02
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#define ES8311_ADC_REG16_ADC_GAIN_18DB 0x03
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#define ES8311_ADC_REG16_ADC_GAIN_24DB 0x04
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#define ES8311_ADC_REG16_ADC_GAIN_30DB 0x05
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#define ES8311_ADC_REG16_ADC_GAIN_36DB 0x06
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#define ES8311_ADC_REG16_ADC_GAIN_42DB 0x07
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#define ES8311_ADC_REG16_ADC_RAM_CLR ES8311_BIT(3)
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#define ES8311_ADC_REG17 0x17 /* ADC, volume */
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#define ES8311_ADC_REG18 0x18 /* ADC, alc enable and winsize */
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#define ES8311_ADC_REG18_AUTO_LEVEL_CONTROL_DISABLE (0 << 7)
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#define ES8311_ADC_REG18_AUTO_LEVEL_CONTROL_ENABLE (1 << 7)
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#define ES8311_ADC_REG18_AUTO_LEVEL_CONTROL_ENABLE ES8311_BIT(7)
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#define ES8311_ADC_REG18_AUTO_MUTE_DISABLE (0 << 6)
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#define ES8311_ADC_REG18_AUTO_MUTE_ENABLE (1 << 6)
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#define ES8311_ADC_REG18_AUTO_MUTE_ENABLE ES8311_BIT(6)
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#define ES8311_ADC_REG18_0_25DB_PER_2LRCK 0x00
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#define ES8311_ADC_REG18_0_25DB_PER_4LRCK 0x01
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#define ES8311_ADC_REG18_0_25DB_PER_8LRCK 0x02
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@@ -249,16 +311,16 @@
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#define ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_6_6DB (0x0E << 4)
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#define ES8311_ADC_REG19_ALC_MAX_LEVEL_NEG_6_0DB (0x0F << 4)
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#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_30_1DB (0x00 << 0)
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#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_24_1DB (0x01 << 0)
|
||||
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_20_6DB (0x02 << 0)
|
||||
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_18_1DB (0x03 << 0)
|
||||
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_16_1DB (0x04 << 0)
|
||||
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_14_5DB (0x05 << 0)
|
||||
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_13_2DB (0x06 << 0)
|
||||
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_12_0DB (0x07 << 0)
|
||||
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_11_0DB (0x08 << 0)
|
||||
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_10_1DB (0x09 << 0)
|
||||
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_30_1DB (0x00)
|
||||
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_24_1DB (0x00)
|
||||
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_20_6DB (0x00)
|
||||
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_18_1DB (0x00)
|
||||
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_16_1DB (0x00)
|
||||
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_14_5DB (0x00)
|
||||
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_13_2DB (0x00)
|
||||
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_12_0DB (0x00)
|
||||
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_11_0DB (0x00)
|
||||
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_10_1DB (0x00)
|
||||
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_9_3DB (0x0A << 0)
|
||||
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_8_5DB (0x0B << 0)
|
||||
#define ES8311_ADC_REG19_ALC_MIN_LEVEL_NEG_7_8DB (0x0C << 0)
|
||||
@@ -285,16 +347,16 @@
|
||||
#define ES8311_ADC_REG1A_AUTOMUTE_30720_SAMPLES (0x0E << 4)
|
||||
#define ES8311_ADC_REG1A_AUTOMUTE_32768_SAMPLES (0x0F << 4)
|
||||
|
||||
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_96DB (0x00 << 0)
|
||||
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_90DB (0x01 << 0)
|
||||
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_84DB (0x02 << 0)
|
||||
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_78DB (0x03 << 0)
|
||||
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_72DB (0x04 << 0)
|
||||
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_66DB (0x05 << 0)
|
||||
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_60DB (0x06 << 0)
|
||||
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_54DB (0x07 << 0)
|
||||
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_51DB (0x08 << 0)
|
||||
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_48DB (0x09 << 0)
|
||||
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_96DB (0x00)
|
||||
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_90DB (0x00)
|
||||
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_84DB (0x00)
|
||||
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_78DB (0x00)
|
||||
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_72DB (0x00)
|
||||
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_66DB (0x00)
|
||||
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_60DB (0x00)
|
||||
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_54DB (0x00)
|
||||
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_51DB (0x00)
|
||||
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_48DB (0x00)
|
||||
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_45DB (0x0A << 0)
|
||||
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_42DB (0x0B << 0)
|
||||
#define ES8311_ADC_REG1A_AUTOMUTE_NEG_39DB (0x0C << 0)
|
||||
@@ -307,39 +369,140 @@
|
||||
// bits 4:0 have ADCHPF stage 1 coefficient - reg1b
|
||||
#define ES8311_ADC_REG1C 0x1C /* ADC, equalizer, hpf s2 */
|
||||
#define ES8311_ADC_REG1C_ADCEQ_NORMAL (0 << 6)
|
||||
#define ES8311_ADC_REG1C_ADCEQ_BYPASS (1 << 6)
|
||||
#define ES8311_ADC_REG1C_ADCEQ_BYPASS ES8311_BIT(6)
|
||||
#define ES8311_ADC_REG1C_HPF_FREEZE_OFFSET (0 << 5)
|
||||
#define ES8311_ADC_REG1C_HPF_DYNAMIC_HPF (1 << 5)
|
||||
#define ES8311_ADC_REG1C_HPF_DYNAMIC_HPF ES8311_BIT(5)
|
||||
// bits 4:0 have ADCHPF stage 2 coefficient - reg1c
|
||||
|
||||
/*
|
||||
reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
|
||||
reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
|
||||
reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
|
||||
reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
|
||||
reg1d - ADCEQ_A1[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
|
||||
reg1d - ADCEQ_A1[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
|
||||
reg1d - ADCEQ_A1[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
|
||||
reg1d - ADCEQ_A1[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
|
||||
reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
|
||||
reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
|
||||
reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
|
||||
reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
|
||||
reg1d - ADCEQ_B0[29:24] - bit 5:0 30-bit B0 coefficient for ADCEQ
|
||||
reg1e - ADCEQ_B0[23:16] - bit 7:0 30-bit B0 coefficient for ADCEQ
|
||||
reg1f - ADCEQ_B0[15:8] - bit 7:0 30-bit B0 coefficient for ADCEQ
|
||||
reg20 - ADCEQ_B0[7:0] - bit 7:0 30-bit B0 coefficient for ADCEQ
|
||||
|
||||
reg21 - ADCEQ_A1[29:24] - bit 5:0 30-bit A1 coefficient for ADCEQ
|
||||
reg22 - ADCEQ_A1[23:16] - bit 7:0 30-bit A1 coefficient for ADCEQ
|
||||
reg23 - ADCEQ_A1[15:8] - bit 7:0 30-bit A1 coefficient for ADCEQ
|
||||
reg24 - ADCEQ_A1[7:0] - bit 7:0 30-bit A1 coefficient for ADCEQ
|
||||
|
||||
reg25 - ADCEQ_A2[29:24] - bit 5:0 30-bit A2 coefficient for ADCEQ
|
||||
reg26 - ADCEQ_A2[23:16] - bit 7:0 30-bit A2 coefficient for ADCEQ
|
||||
reg27 - ADCEQ_A2[15:8] - bit 7:0 30-bit A2 coefficient for ADCEQ
|
||||
reg28 - ADCEQ_A2[7:0] - bit 7:0 30-bit A2 coefficient for ADCEQ
|
||||
|
||||
reg29 - ADCEQ_B1[29:24] - bit 5:0 30-bit B1 coefficient for ADCEQ
|
||||
reg2a - ADCEQ_B1[23:16] - bit 7:0 30-bit B1 coefficient for ADCEQ
|
||||
reg2b - ADCEQ_B1[15:8] - bit 7:0 30-bit B1 coefficient for ADCEQ
|
||||
reg2c - ADCEQ_B1[7:0] - bit 7:0 30-bit B1 coefficient for ADCEQ
|
||||
|
||||
reg2d - ADCEQ_B2[29:24] - bit 5:0 30-bit B1 coefficient for ADCEQ
|
||||
reg2e - ADCEQ_B2[23:16] - bit 7:0 30-bit B1 coefficient for ADCEQ
|
||||
reg2f - ADCEQ_B2[15:8] - bit 7:0 30-bit B1 coefficient for ADCEQ
|
||||
reg30 - ADCEQ_B2[7:0] - bit 7:0 30-bit B1 coefficient for ADCEQ
|
||||
*/
|
||||
/*
|
||||
* DAC
|
||||
*/
|
||||
#define ES8311_DAC_REG31 0x31 /* DAC, mute */
|
||||
#define ES8311_DAC_REG31_MUTE_TO8 (0 << 7)
|
||||
#define ES8311_DAC_REG31_MUTE_TO7_9 ES8311_BIT(7)
|
||||
#define ES8311_DAC_REG31_DSM_UNMUTE (0 << 6)
|
||||
#define ES8311_DAC_REG31_DSM_MUTE ES8311_BIT(6)
|
||||
#define ES8311_DAC_REG31_DEM_UNMUTE (0 << 5)
|
||||
#define ES8311_DAC_REG31_DEM_MUTE ES8311_BIT(5)
|
||||
|
||||
|
||||
|
||||
#define ES8311_DAC_REG32 0x32 /* DAC, volume */
|
||||
#define ES8311_DAC_REG33 0x33 /* DAC, offset */
|
||||
#define ES8311_DAC_REG34 0x34 /* DAC, drc enable, drc winsize */
|
||||
#define ES8311_DAC_REG34_DRC_DISABLE (0 << 7)
|
||||
#define ES8311_DAC_REG34_DRC_ENABLE ES8311_BIT(7)
|
||||
#define ES8311_DAC_REG34_DRC_WINSIZE_DISABLE (0x00)
|
||||
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_4LRCK (0x00)
|
||||
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_8LRCK (0x00)
|
||||
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_16LRCK (0x00)
|
||||
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_32LRCK (0x00)
|
||||
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_64LRCK (0x00)
|
||||
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_128LRCK (0x00)
|
||||
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_256LRCK (0x00)
|
||||
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_512LRCK (0x00)
|
||||
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_1024LRCK (0x00)
|
||||
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_2048LRCK (0x0a << 0)
|
||||
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_4096LRCK (0x0b << 0)
|
||||
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_8192LRCK (0x0c << 0)
|
||||
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_16384LRCK (0x0d << 0)
|
||||
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_32768LRCK (0x0e << 0)
|
||||
#define ES8311_DAC_REG34_DRC_WINSIZE_0_25_65536LRCK (0x0f << 0)
|
||||
|
||||
#define ES8311_DAC_REG35 0x35 /* DAC, drc maxlevel, minilevel */
|
||||
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_30_1DB (0x00 << 4)
|
||||
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_24_1DB (0x01 << 4)
|
||||
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_20_6DB (0x02 << 4)
|
||||
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_18_1DB (0x03 << 4)
|
||||
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_16_1DB (0x04 << 4)
|
||||
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_14_5DB (0x05 << 4)
|
||||
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_13_2DB (0x06 << 4)
|
||||
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_12_0DB (0x07 << 4)
|
||||
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_11_0DB (0x08 << 4)
|
||||
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_10_1DB (0x09 << 4)
|
||||
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_9_3DB (0x0A << 4)
|
||||
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_8_5DB (0x0B << 4)
|
||||
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_7_8DB (0x0C << 4)
|
||||
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_7_2DB (0x0D << 4)
|
||||
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_6_6DB (0x0E << 4)
|
||||
#define ES8311_DAC_REG35_DRC_MAX_LEVEL_NEG_6_0DB (0x0F << 4)
|
||||
|
||||
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_30_1DB (0x00)
|
||||
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_24_1DB (0x00)
|
||||
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_20_6DB (0x00)
|
||||
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_18_1DB (0x00)
|
||||
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_16_1DB (0x00)
|
||||
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_14_5DB (0x00)
|
||||
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_13_2DB (0x00)
|
||||
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_12_0DB (0x00)
|
||||
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_11_0DB (0x00)
|
||||
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_10_1DB (0x00)
|
||||
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_9_3DB (0x0A << 0)
|
||||
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_8_5DB (0x0B << 0)
|
||||
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_7_8DB (0x0C << 0)
|
||||
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_7_2DB (0x0D << 0)
|
||||
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_6_6DB (0x0E << 0)
|
||||
#define ES8311_DAC_REG35_DRC_MIN_LEVEL_NEG_6_0DB (0x0F << 0)
|
||||
|
||||
|
||||
#define ES8311_DAC_REG37 0x37 /* DAC, ramprate */
|
||||
#define ES8311_DAC_REG37_RAMPRATE_DISABLE (0x00 << 4)
|
||||
#define ES8311_DAC_REG37_RAMPRATE_0_25_4LRCK (0x01 << 4)
|
||||
#define ES8311_DAC_REG37_RAMPRATE_0_25_8LRCK (0x02 << 4)
|
||||
#define ES8311_DAC_REG37_RAMPRATE_0_25_16LRCK (0x03 << 4)
|
||||
#define ES8311_DAC_REG37_RAMPRATE_0_25_32LRCK (0x04 << 4)
|
||||
#define ES8311_DAC_REG37_RAMPRATE_0_25_64LRCK (0x05 << 4)
|
||||
#define ES8311_DAC_REG37_RAMPRATE_0_25_128LRCK (0x06 << 4)
|
||||
#define ES8311_DAC_REG37_RAMPRATE_0_25_256LRCK (0x07 << 4)
|
||||
#define ES8311_DAC_REG37_RAMPRATE_0_25_512LRCK (0x08 << 4)
|
||||
#define ES8311_DAC_REG37_RAMPRATE_0_25_1024LRCK (0x09 << 4)
|
||||
#define ES8311_DAC_REG37_RAMPRATE_0_25_2048LRCK (0x0a << 4)
|
||||
#define ES8311_DAC_REG37_RAMPRATE_0_25_4096LRCK (0x0b << 4)
|
||||
#define ES8311_DAC_REG37_RAMPRATE_0_25_8192LRCK (0x0c << 4)
|
||||
#define ES8311_DAC_REG37_RAMPRATE_0_25_16384LRCK (0x0d << 4)
|
||||
#define ES8311_DAC_REG37_RAMPRATE_0_25_32768LRCK (0x0e << 4)
|
||||
#define ES8311_DAC_REG37_RAMPRATE_0_25_65536LRCK (0x0f << 4)
|
||||
/*
|
||||
*GPIO
|
||||
*/
|
||||
#define ES8311_GPIO_REG44 0x44 /* GPIO, dac2adc for test */
|
||||
#define ES8311_GPIO_REG44_ADCDAT_SEL_NO_LOOPBACK (0 << 7)
|
||||
#define ES8311_GPIO_REG44_ADCDAT_ADC_TO_DAC ES8311_BIT(7)
|
||||
#define ES8311_GPIO_REG44_ADCDAT_SEL_ADC_ADC (0x00 << 4)
|
||||
#define ES8311_GPIO_REG44_ADCDAT_SEL_ADC_0 (0x01 << 4)
|
||||
#define ES8311_GPIO_REG44_ADCDAT_SEL_0_ADC (0x02 << 4)
|
||||
#define ES8311_GPIO_REG44_ADCDAT_SEL_0_0 (0x03 << 4)
|
||||
#define ES8311_GPIO_REG44_ADCDAT_SEL_DACL_ADC (0x04 << 4)
|
||||
#define ES8311_GPIO_REG44_ADCDAT_SEL_ADC_DACR (0x05 << 4)
|
||||
#define ES8311_GPIO_REG44_ADCDAT_SEL_DACL_DACR (0x06 << 4)
|
||||
//#define ES8311_GPIO_REG44_ADCDAT_SEL_NA (0x07 << 4)
|
||||
|
||||
#define ES8311_GP_REG45 0x45 /* GP CONTROL */
|
||||
/*
|
||||
* CHIP
|
||||
|
||||
Reference in New Issue
Block a user