Do some work on the CPU, assembler still needs update
This commit is contained in:
525
assembler/assembler.c
Normal file
525
assembler/assembler.c
Normal file
@@ -0,0 +1,525 @@
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//
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// Created by bruno on 1.2.2025.
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//
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#include "assembler.h"
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Label labels[MAX_LABELS];
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int labelCount = 0;
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//
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// Helper functions for string manipulation
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//
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void trim(char *s) {
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// Remove leading whitespace
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while (isspace((unsigned char) *s)) s++;
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// Remove trailing whitespace
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char *end = s + strlen(s) - 1;
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while (end > s && isspace((unsigned char) *end)) {
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*end = '\0';
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end--;
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}
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}
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// Look up a label by name; returns -1 if not found.
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int lookupLabel(const char *name) {
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for (int i = 0; i < labelCount; i++) {
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if (strcmp(labels[i].name, name) == 0)
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return labels[i].address;
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}
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return -1;
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}
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// Add a label to the table
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void addLabel(const char *name, int address) {
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if (labelCount >= MAX_LABELS) {
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fprintf(stderr, "Too many labels!\n");
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exit(1);
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}
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strncpy(labels[labelCount].name, name, sizeof(labels[labelCount].name));
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labels[labelCount].address = address;
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labelCount++;
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}
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//
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// Parse a register string (e.g., "R0", "R1", etc.) and return it's number.
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// Returns -1 on error.
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int parseRegister(const char *token) {
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if (token[0] == 'R' || token[0] == 'r') {
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int reg = atoi(token + 1);
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if (reg >= 0 && reg < REG_COUNT)
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return reg;
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}
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return -1;
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}
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// Parse an immediate value (supports decimal and 0x... hexadecimal)
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uint8_t parseImmediate(const char *token) {
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int value;
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if (strlen(token) > 2 && token[0] == '0' && (token[1] == 'x' || token[1] == 'X'))
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sscanf(token, "%x", &value);
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else
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sscanf(token, "%d", &value);
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return (uint8_t) value;
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}
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void toUpperCase(char *string) {
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while (*string) {
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if (*string > 0x60 && *string < 0x7b) {
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(*string) -= 0x20;
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}
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}
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}
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//
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// Map an instruction mnemonic (string) to its opcode value and expected operand types.
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// For simplicity, we will return the opcode value and then in our parser we’ll decide how many operands to expect.
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// (In a full assembler you might use a more sophisticated data structure.)
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//
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int getOpcode(char *mnemonic) {
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toUpperCase(mnemonic);
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if (strcmp(mnemonic, "BRK") == 0)
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return BRK;
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else if (strcmp(mnemonic, "NOP") == 0)
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return NOP;
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else if (strcmp(mnemonic, "MOV") == 0)
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return -2; // Special case: we must decide between MOV_RN_IMM, MOV_RN_RM, MOV_RN_ADDR, MOV_ADDR_RN
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else if (strcmp(mnemonic, "SWAP") == 0)
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return SWAP;
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else if (strcmp(mnemonic, "SWAPN") == 0)
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return SWAPN;
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else if (strcmp(mnemonic, "ADD") == 0)
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return -3; // Special: decide between ADD_RN_RM and ADD_RN_IMM
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else if (strcmp(mnemonic, "SUB") == 0)
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return -4; // Special: decide between SUB_RN_RM and SUB_RN_IMM
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else if (strcmp(mnemonic, "MUL") == 0)
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return -5; // Special: decide between MUL_RN_RM and MUL_RN_IMM
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else if (strcmp(mnemonic, "DIV") == 0)
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return -6; // Special: decide between DIV_RN_RM and DIV_RN_IMM
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else if (strcmp(mnemonic, "MOD") == 0)
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return -7; // Special: decide between MOD_RN_RM and MOD_RN_IMM
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else if (strcmp(mnemonic, "NEG") == 0)
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return NEG_RN;
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else if (strcmp(mnemonic, "AND") == 0)
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return -8; // Special: decide between AND_RN_RM and AND_RN_IMM
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else if (strcmp(mnemonic, "OR") == 0)
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return -9; // Special: decide between OR_RN_RM and OR_RN_IMM
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else if (strcmp(mnemonic, "XOR") == 0)
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return -10; // Special: decide between XOR_RN_RM and XOR_RN_IMM
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else if (strcmp(mnemonic, "NOT") == 0)
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return NOT_RN;
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else if (strcmp(mnemonic, "SHL") == 0)
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return SHL_RN_IMM;
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else if (strcmp(mnemonic, "SHR") == 0)
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return SHR_RN_IMM;
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else if (strcmp(mnemonic, "SAR") == 0)
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return SAR_RN_IMM;
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else if (strcmp(mnemonic, "JMP") == 0)
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return JMP;
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else if (strcmp(mnemonic, "CMP") == 0)
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return CMP;
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else if (strcmp(mnemonic, "JE") == 0)
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return JE;
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else if (strcmp(mnemonic, "JNE") == 0)
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return JNE;
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else if (strcmp(mnemonic, "JG") == 0)
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return JG;
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else if (strcmp(mnemonic, "JL") == 0)
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return JL;
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else if (strcmp(mnemonic, "JGE") == 0)
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return JGE;
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else if (strcmp(mnemonic, "JLE") == 0)
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return JLE;
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else if (strcmp(mnemonic, "CALL") == 0)
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return CALL;
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else if (strcmp(mnemonic, "RET") == 0)
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return RET;
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else if (strcmp(mnemonic, "PUSH") == 0)
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return PUSH;
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else if (strcmp(mnemonic, "POP") == 0)
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return POP;
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else if (strcmp(mnemonic, "PUSHF") == 0)
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return PUSHF;
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else if (strcmp(mnemonic, "POPF") == 0)
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return POPF;
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else {
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return -1;
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}
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}
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//
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// In this simple assembler, some instructions share a mnemonic, and we must choose the correct opcode
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// based on the type of the operand (register vs. immediate vs. memory).
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// The following helper functions decide that, given two operands (as strings).
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//
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// For example, "MOV Rn, 42" should choose MOV_RN_IMM, while "MOV Rn, Rm" should choose MOV_RN_RM.
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// We assume that memory addresses are written in square brackets, e.g. "[123]".
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//
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int resolveMOV(const char *dest, const char *src) {
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// If dest starts with '[' then it is a memory destination.
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if (dest[0] == '[') return MOV_ADDR_RN; // actually, MOV [Addr], Rn expects Rn in second operand
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// Otherwise, dest is a register.
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// Now, check src:
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if (src[0] == 'R' || src[0] == 'r') {
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return MOV_RN_RM;
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} else if (src[0] == '[') {
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return MOV_RN_ADDR;
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} else {
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return MOV_RN_IMM;
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}
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}
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int resolveALU(int baseOpcode, const char *src) {
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// baseOpcode is one of our special negative values for ADD, SUB, etc.
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if (src[0] == 'R' || src[0] == 'r')
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switch (baseOpcode) {
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case -3:
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return ADD_RN_RM;
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case -4:
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return SUB_RN_RM;
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case -5:
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return MUL_RN_RM;
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case -6:
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return DIV_RN_RM;
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case -7:
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return MOD_RN_RM;
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case -8:
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return AND_RN_RM;
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case -9:
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return OR_RN_RM;
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case -10:
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return XOR_RN_RM;
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default:
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return -1;
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}
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else
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switch (baseOpcode) {
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case -3:
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return ADD_RN_IMM;
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case -4:
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return SUB_RN_IMM;
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case -5:
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return MUL_RN_IMM;
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case -6:
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return DIV_RN_IMM;
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case -7:
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return MOD_RN_IMM;
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case -8:
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return AND_RN_IMM;
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case -9:
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return OR_RN_IMM;
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case -10:
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return XOR_RN_IMM;
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default:
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return -1;
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}
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}
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// Reads a single line from the source string.
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const char *readLine(const char *source, char *buffer, size_t maxLen) {
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size_t i = 0;
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while (*source && *source != '\n' && i < maxLen - 1) {
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buffer[i++] = *source++;
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}
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buffer[i] = '\0';
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return (*source == '\n') ? source + 1 : source;
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}
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//
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// The first pass scans the assembly source file to record all labels and their addresses.
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// The address is simply the offset into the output machine code buffer.
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// For this example, every instruction is assumed to have a fixed length (opcode plus operand bytes).
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//
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int firstPass(const char *source) {
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char line[MAX_LINE_LENGTH];
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int addr = 0;
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const char *ptr = source;
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while (*ptr) {
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// Read a line from the source string
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ptr = readLine(ptr, line, sizeof(line));
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trim(line);
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if (line[0] == '\0' || line[0] == ';' || line[0] == '#')
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continue; // Skip empty or comment lines
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char *colon = strchr(line, ':');
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if (colon != NULL) {
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*colon = '\0';
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trim(line);
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addLabel(line, addr);
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char *rest = colon + 1;
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trim(rest);
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if (strlen(rest) == 0)
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continue;
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strcpy(line, rest);
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}
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// For simplicity, we assume each instruction (with its operands) takes a fixed number of bytes.
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// Here we calculate the number of bytes by looking at the opcode mnemonic.
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// (A more robust approach would have a table for instruction sizes.)
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char mnemonic[32];
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sscanf(line, "%31s", mnemonic);
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int opcode = getOpcode(mnemonic);
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if (opcode == -2) {
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// MOV: two operands separated by comma
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// e.g. MOV R1, 42
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// We add 3 bytes: opcode, operand1, operand2.
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addr += 3;
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} else if (opcode == -3 || opcode == -4 || opcode == -5 || opcode == -6 ||
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opcode == -7 || opcode == -8 || opcode == -9 || opcode == -10) {
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// ALU instructions with two operands: 3 bytes.
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addr += 3;
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} else if (opcode == NEG_RN || opcode == SWAPN || opcode == NOT_RN) {
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// One operand: 2 bytes.
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addr += 2;
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} else if (opcode == SWAP || opcode == CMP) {
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// Two operands: 3 bytes.
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addr += 3;
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} else if (opcode == SHL_RN_IMM || opcode == SHR_RN_IMM ||
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opcode == SAR_RN_IMM) {
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addr += 3;
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} else if (opcode == JMP || opcode == JE || opcode == JNE ||
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opcode == JG || opcode == JL || opcode == JGE || opcode == JLE ||
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opcode == CALL) {
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// Jump or call: 2 bytes (opcode and one byte address/immediate).
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addr += 2;
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} else if (opcode == RET || opcode == PUSHF || opcode == POPF) {
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addr += 1;
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} else if (opcode == PUSH || opcode == POP) {
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addr += 2;
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} else {
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// For other instructions, we assume 3 bytes.
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addr += 3;
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}
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}
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return addr;
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}
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//
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// The second pass actually translates the assembly instructions to machine code.
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// The machine code is written into the provided buffer. (It must be large enough.)
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//
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int secondPass(const char *source, uint8_t *code) {
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char line[MAX_LINE_LENGTH];
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int addr = 0;
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const char *ptr = source;
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while (*ptr) {
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ptr = readLine(ptr, line, sizeof(line));
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trim(line);
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if (line[0] == '\0' || line[0] == ';' || line[0] == '#')
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continue;
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char *colon = strchr(line, ':');
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if (colon != NULL) {
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*colon = ' ';
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}
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if (strlen(line) == 0)
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continue;
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char *token = strtok(line, " ,");
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if (!token)
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continue;
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char mnemonic[32];
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strncpy(mnemonic, token, sizeof(mnemonic));
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int opcode = getOpcode(mnemonic);
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code[addr++] = opcode;
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// Handle instructions that need operand disambiguation.
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if (strcmp(mnemonic, "MOV") == 0) {
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// Get first operand.
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char *dest = strtok(NULL, " ,");
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char *src = strtok(NULL, " ,");
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if (!dest || !src) {
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fprintf(stderr, "Error: MOV requires two operands.\n");
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exit(1);
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}
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int opcode2 = resolveMOV(dest, src);
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code[addr++] = opcode2;
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// For the MOV instructions we decide that:
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// - For MOV_RN_IMM: operand bytes: [register, immediate]
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// - For MOV_RN_RM: operand bytes: [dest register, src register]
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// - For MOV_RN_ADDR: operand bytes: [dest register, address]
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// - For MOV_ADDR_RN: operand bytes: [address, register]
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if (opcode2 == MOV_RN_IMM) {
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int reg = parseRegister(dest);
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uint8_t imm = parseImmediate(src);
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code[addr++] = reg;
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code[addr++] = imm;
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} else if (opcode2 == MOV_RN_RM) {
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int regDest = parseRegister(dest);
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int regSrc = parseRegister(src);
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code[addr++] = regDest;
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code[addr++] = regSrc;
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} else if (opcode2 == MOV_RN_ADDR) {
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// src is memory reference like "[123]"
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int regDest = parseRegister(dest);
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// Remove the brackets.
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char addrStr[32];
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strncpy(addrStr, src + 1, strlen(src) - 2);
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addrStr[strlen(src) - 2] = '\0';
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uint8_t memAddr = parseImmediate(addrStr);
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code[addr++] = regDest;
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code[addr++] = memAddr;
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} else if (opcode2 == MOV_ADDR_RN) {
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// dest is a memory reference, src is a register.
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// Remove brackets from dest.
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char addrStr[32];
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strncpy(addrStr, dest + 1, strlen(dest) - 2);
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addrStr[strlen(dest) - 2] = '\0';
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uint8_t memAddr = parseImmediate(addrStr);
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int regSrc = parseRegister(src);
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code[addr++] = memAddr;
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code[addr++] = regSrc;
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}
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} else if (strcmp(mnemonic, "ADD") == 0 ||
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strcmp(mnemonic, "SUB") == 0 ||
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strcmp(mnemonic, "MUL") == 0 ||
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strcmp(mnemonic, "DIV") == 0 ||
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strcmp(mnemonic, "MOD") == 0 ||
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strcmp(mnemonic, "AND") == 0 ||
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strcmp(mnemonic, "OR") == 0 ||
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strcmp(mnemonic, "XOR") == 0) {
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// ALU instructions with two operands.
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char *dest = strtok(NULL, " ,");
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char *src = strtok(NULL, " ,");
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if (!dest || !src) {
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fprintf(stderr, "Error: %s requires two operands.\n", mnemonic);
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exit(1);
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}
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int baseOpcode;
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if (strcmp(mnemonic, "ADD") == 0) baseOpcode = -3;
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else if (strcmp(mnemonic, "SUB") == 0) baseOpcode = -4;
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else if (strcmp(mnemonic, "MUL") == 0) baseOpcode = -5;
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else if (strcmp(mnemonic, "DIV") == 0) baseOpcode = -6;
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else if (strcmp(mnemonic, "MOD") == 0) baseOpcode = -7;
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else if (strcmp(mnemonic, "AND") == 0) baseOpcode = -8;
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else if (strcmp(mnemonic, "OR") == 0) baseOpcode = -9;
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else if (strcmp(mnemonic, "XOR") == 0) baseOpcode = -10;
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else baseOpcode = -1;
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int opcode3 = resolveALU(baseOpcode, src);
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code[addr++] = opcode3;
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int regDest = parseRegister(dest);
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code[addr++] = regDest;
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// For a register source, encode the register; for an immediate, encode the value.
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if (src[0] == 'R' || src[0] == 'r') {
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int regSrc = parseRegister(src);
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code[addr++] = regSrc;
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} else {
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uint8_t imm = parseImmediate(src);
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code[addr++] = imm;
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}
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} else if (strcmp(mnemonic, "NEG") == 0 ||
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strcmp(mnemonic, "SWAPN") == 0 ||
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strcmp(mnemonic, "NOT") == 0) {
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// One operand instructions.
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char *op = strtok(NULL, " ,");
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if (!op) {
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fprintf(stderr, "Error: %s requires one operand.\n", mnemonic);
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exit(1);
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}
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int opcode4 = getOpcode(mnemonic);
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code[addr++] = opcode4;
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int reg = parseRegister(op);
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code[addr++] = reg;
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} else if (strcmp(mnemonic, "SWAP") == 0 || strcmp(mnemonic, "CMP") == 0) {
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// Two operand instructions: both registers.
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char *op1 = strtok(NULL, " ,");
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char *op2 = strtok(NULL, " ,");
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if (!op1 || !op2) {
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fprintf(stderr, "Error: %s requires two operands.\n", mnemonic);
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exit(1);
|
||||
}
|
||||
int opcode5 = getOpcode(mnemonic);
|
||||
code[addr++] = opcode5;
|
||||
int r1 = parseRegister(op1);
|
||||
int r2 = parseRegister(op2);
|
||||
code[addr++] = r1;
|
||||
code[addr++] = r2;
|
||||
} else if (strcmp(mnemonic, "SHL") == 0 ||
|
||||
strcmp(mnemonic, "SHR") == 0 ||
|
||||
strcmp(mnemonic, "SAR") == 0 ||
|
||||
strcmp(mnemonic, "SHRS") == 0) {
|
||||
// Shift instructions: one register operand and one immediate.
|
||||
char *regToken = strtok(NULL, " ,");
|
||||
char *immToken = strtok(NULL, " ,");
|
||||
if (!regToken || !immToken) {
|
||||
fprintf(stderr, "Error: %s requires two operands.\n", mnemonic);
|
||||
exit(1);
|
||||
}
|
||||
int opcode6 = getOpcode(mnemonic);
|
||||
code[addr++] = opcode6;
|
||||
int reg = parseRegister(regToken);
|
||||
code[addr++] = reg;
|
||||
uint8_t imm = parseImmediate(immToken);
|
||||
code[addr++] = imm;
|
||||
} else if (strcmp(mnemonic, "JMP") == 0 ||
|
||||
strcmp(mnemonic, "JE") == 0 ||
|
||||
strcmp(mnemonic, "JNE") == 0 ||
|
||||
strcmp(mnemonic, "JG") == 0 ||
|
||||
strcmp(mnemonic, "JL") == 0 ||
|
||||
strcmp(mnemonic, "JGE") == 0 ||
|
||||
strcmp(mnemonic, "JLE") == 0 ||
|
||||
strcmp(mnemonic, "CALL") == 0) {
|
||||
// Jump instructions: one operand which may be a label or an immediate address.
|
||||
char *operand = strtok(NULL, " ,");
|
||||
if (!operand) {
|
||||
fprintf(stderr, "Error: %s requires an operand.\n", mnemonic);
|
||||
exit(1);
|
||||
}
|
||||
int opcode7 = getOpcode(mnemonic);
|
||||
code[addr++] = opcode7;
|
||||
// If the operand is not a number, assume it is a label.
|
||||
if (!isdigit(operand[0])) {
|
||||
int labelAddr = lookupLabel(operand);
|
||||
if (labelAddr < 0) {
|
||||
fprintf(stderr, "Error: undefined label '%s'\n", operand);
|
||||
exit(1);
|
||||
}
|
||||
code[addr++] = (uint8_t) labelAddr;
|
||||
} else {
|
||||
uint8_t imm = parseImmediate(operand);
|
||||
code[addr++] = imm;
|
||||
}
|
||||
} else if (strcmp(mnemonic, "RET") == 0 ||
|
||||
strcmp(mnemonic, "PUSHF") == 0 ||
|
||||
strcmp(mnemonic, "POPF") == 0) {
|
||||
// Instructions with no operand.
|
||||
int opcode8 = getOpcode(mnemonic);
|
||||
code[addr++] = opcode8;
|
||||
} else if (strcmp(mnemonic, "PUSH") == 0 ||
|
||||
strcmp(mnemonic, "POP") == 0) {
|
||||
// One operand (a register)
|
||||
char *regToken = strtok(NULL, " ,");
|
||||
if (!regToken) {
|
||||
fprintf(stderr, "Error: %s requires a register operand.\n", mnemonic);
|
||||
exit(1);
|
||||
}
|
||||
int opcode9 = getOpcode(mnemonic);
|
||||
code[addr++] = opcode9;
|
||||
int reg = parseRegister(regToken);
|
||||
code[addr++] = reg;
|
||||
} else {
|
||||
fprintf(stderr, "Error: Unknown instruction '%s'\n", mnemonic);
|
||||
exit(1);
|
||||
}
|
||||
}
|
||||
return addr;
|
||||
}
|
||||
|
||||
void completePass(const char *input, CPU *cpu) {
|
||||
// First pass: determine label addresses.
|
||||
firstPass(input);
|
||||
|
||||
memset(cpu->memory, 0, MEM_SIZE);
|
||||
|
||||
// Second pass: generate machine code.
|
||||
secondPass(input, cpu->memory);
|
||||
}
|
||||
Reference in New Issue
Block a user