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.cproject
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
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<storageModule moduleId="org.eclipse.cdt.core.settings">
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<cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074">
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<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" moduleId="org.eclipse.cdt.core.settings" name="obj">
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<macros/>
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<externalSettings/>
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<extensions>
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<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
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<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
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<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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</extensions>
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</storageModule>
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<storageModule moduleId="cdtBuildSystem" version="4.0.0">
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<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="${cross_rm} -rf" description="" errorParsers="org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GCCErrorParser" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" name="obj" parent="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release" postannouncebuildStep="" postbuildStep="" preannouncebuildStep="" prebuildStep="">
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<folderInfo id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" name="/" resourcePath="">
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<toolChain id="ilg.gnumcueclipse.managedbuild.cross.riscv.toolchain.elf.release.231146001" name="RISC-V Cross GCC" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.toolchain.elf.release">
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.rvGcc.1171217701" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.rvGcc" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.rvGcc.12" valueType="enumerated"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.base.1900297968" name="Architecture" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.base" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.arch.rv32i" valueType="enumerated"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply.1509705449" name="Multiply extension (RVM)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic.1590833110" name="Atomic extension (RVA)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.fp.1709872289" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.fp" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.isa.fp.none" valueType="enumerated"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed.1038505275" name="Compressed extension (RVC)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw.1505432023" name="Extra Compressed extension (RVXW)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.xw" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.b.1896185078" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.b" useByScannerDiscovery="false" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.zmmul.724822239" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.zmmul" useByScannerDiscovery="false" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.387605487" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.integer.ilp32" valueType="enumerated"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.fp.966196099" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.fp" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.fp.none" valueType="enumerated"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.tune.394563202" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.tune" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.tune.default" valueType="enumerated"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.105093140" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.default" valueType="enumerated"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.smalldatalimit.1147643442" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.smalldatalimit" useByScannerDiscovery="false" value="8" valueType="string"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.align.322546450" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.align" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.align.default" valueType="enumerated"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore.367800619" name="Small prologue/epilogue (-msave-restore)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.saverestore" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.other.1526047739" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.other" useByScannerDiscovery="true" value="" valueType="string"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level.514997414" name="Optimization Level" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level" useByScannerDiscovery="true" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.level.size" valueType="enumerated"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.messagelength.1008570639" name="Message length (-fmessage-length=0)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.messagelength" useByScannerDiscovery="true" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.signedchar.467272439" name="'char' is signed (-fsigned-char)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.signedchar" useByScannerDiscovery="true" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.functionsections.2047756949" name="Function sections (-ffunction-sections)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.functionsections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.datasections.207613650" name="Data sections (-fdata-sections)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.datasections" useByScannerDiscovery="true" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nocommon.358586167" name="No common unitialized (-fno-common)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nocommon" useByScannerDiscovery="true" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.noinlinefunctions.1298414520" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.noinlinefunctions" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.freestanding.213924425" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.freestanding" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nobuiltin.2007120903" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nobuiltin" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.spconstant.938841347" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.spconstant" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.PIC.234574726" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.PIC" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.lto.1002322664" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.lto" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nomoveloopinvariants.1270575343" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.nomoveloopinvariants" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.mrs.highcode.114339272" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.mrs.highcode" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.mrs.asmsoftlib.896763512" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.mrs.asmsoftlib" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.mrs.pipe.1835231981" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.mrs.pipe" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.mrs.caret.2021231049" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.mrs.caret" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.other.180560481" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.optimization.other" useByScannerDiscovery="true" value="" valueType="string"/>
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||||||
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.syntaxonly.1145714735" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.syntaxonly" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.pedantic.1546854128" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.pedantic" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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||||||
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.pedanticerrors.338820707" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.pedanticerrors" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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||||||
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.nowarn.254465728" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.nowarn" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.unused.1961191588" name="Warn on various unused elements (-Wunused)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.unused" useByScannerDiscovery="true" value="true" valueType="boolean"/>
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||||||
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.uninitialized.929829166" name="Warn on uninitialized variables (-Wuninitialized)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.uninitialized" useByScannerDiscovery="true" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.allwarn.1168626160" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.allwarn" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.extrawarn.291772487" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.extrawarn" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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||||||
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.missingdeclaration.102344169" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.missingdeclaration" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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||||||
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.conversion.550923640" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.conversion" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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||||||
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.pointerarith.773148082" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.pointerarith" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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||||||
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.padded.1788238782" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.padded" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.shadow.427580978" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.shadow" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.logicalop.1501889551" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.logicalop" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.agreggatereturn.1785504720" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.agreggatereturn" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.toerrors.1117291056" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.warnings.toerrors" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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||||||
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||||||
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.debugging.level.1204865254" name="Debug level" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.debugging.level" useByScannerDiscovery="true" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.debugging.level.default" valueType="enumerated"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.debugging.gprof.1910159761" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.debugging.gprof" useByScannerDiscovery="true" value="false" valueType="boolean"/>
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||||||
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||||||
|
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.prefix.103341323" name="Prefix" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.prefix" useByScannerDiscovery="false" value="riscv-none-elf-" valueType="string"/>
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||||||
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.c.487601824" name="C compiler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.c" useByScannerDiscovery="false" value="gcc" valueType="string"/>
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||||||
|
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.cpp.1062130429" name="C++ compiler" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.cpp" useByScannerDiscovery="false" value="g++" valueType="string"/>
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||||||
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.objdump.1053750745" name="Listing generator" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.objdump" useByScannerDiscovery="false" value="objdump" valueType="string"/>
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||||||
|
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.size.1441326233" name="Size command" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.size" useByScannerDiscovery="false" value="size" valueType="string"/>
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||||||
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.make.550105535" name="Build command" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.make" useByScannerDiscovery="false" value="make" valueType="string"/>
|
||||||
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.rm.719280496" name="Remove command" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.command.rm" useByScannerDiscovery="false" value="rm" valueType="string"/>
|
||||||
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||||||
|
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.addtools.createflash.1311852988" name="Create flash image" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.addtools.createflash" useByScannerDiscovery="false" value="true" valueType="boolean"/>
|
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||||||
|
<entry excluding="FreeRTOS/portable/Common/mpu_wrappers.c|Startup/startup_ch32v30x_D8.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
|
||||||
|
</sourceEntries>
|
||||||
|
</configuration>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||||
|
<storageModule moduleId="ilg.gnumcueclipse.managedbuild.packs"/>
|
||||||
|
</cconfiguration>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||||
|
<project id="999.ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf.275846018" name="Executable file" projectType="ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf"/>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="scannerConfiguration">
|
||||||
|
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||||
|
<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1375371130;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.1473381709">
|
||||||
|
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||||
|
</scannerConfigBuildInfo>
|
||||||
|
<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1731377187;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.2036806839">
|
||||||
|
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||||
|
</scannerConfigBuildInfo>
|
||||||
|
</storageModule>
|
||||||
|
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
|
||||||
|
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
|
||||||
|
</cproject>
|
||||||
1
.gitignore
vendored
Normal file
1
.gitignore
vendored
Normal file
@@ -0,0 +1 @@
|
|||||||
|
/obj
|
||||||
26
.mrs/femtomesh_sw.mrs-workspace
Normal file
26
.mrs/femtomesh_sw.mrs-workspace
Normal file
@@ -0,0 +1,26 @@
|
|||||||
|
{
|
||||||
|
"folders": [
|
||||||
|
{
|
||||||
|
"path": "."
|
||||||
|
},
|
||||||
|
{
|
||||||
|
"name": "femtomesh_sw",
|
||||||
|
"path": "../"
|
||||||
|
}
|
||||||
|
],
|
||||||
|
"settings": {
|
||||||
|
"mrs.workspace.type": "project",
|
||||||
|
"files.associations": {
|
||||||
|
"*.c": "c",
|
||||||
|
"*.h": "cpp",
|
||||||
|
"*.hxx": "cpp",
|
||||||
|
"*.hpp": "cpp",
|
||||||
|
"*.c++": "cpp",
|
||||||
|
"*.cpp": "cpp",
|
||||||
|
"*.cxx": "cpp",
|
||||||
|
"*.cc": "cpp",
|
||||||
|
"*.hh": "cpp",
|
||||||
|
"*.h++": "cpp"
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
68
.mrs/launch.json
Normal file
68
.mrs/launch.json
Normal file
@@ -0,0 +1,68 @@
|
|||||||
|
{
|
||||||
|
"version": "0.2.0",
|
||||||
|
"configurations": [
|
||||||
|
{
|
||||||
|
"type": "mrs-debugger",
|
||||||
|
"request": "launch",
|
||||||
|
"name": "femtomesh_sw",
|
||||||
|
"cwd": "/home/bruno/Documents/Programming/projects/femtomesh_sw",
|
||||||
|
"openOCDCfg": {
|
||||||
|
"useLocalOpenOCD": true,
|
||||||
|
"executable": "/usr/share/MRS2/MRS-linux-x64/resources/app/resources/linux/components/WCH/OpenOCD/OpenOCD/bin/openocd",
|
||||||
|
"configOptions": [
|
||||||
|
"-f \"/usr/share/MRS2/MRS-linux-x64/resources/app/resources/linux/components/WCH/OpenOCD/OpenOCD/bin/wch-riscv.cfg\" -c \"chip_id CH32V30x\""
|
||||||
|
],
|
||||||
|
"gdbport": 3333,
|
||||||
|
"telnetport": 4444,
|
||||||
|
"tclport": 6666,
|
||||||
|
"host": "localhost",
|
||||||
|
"port": 3333,
|
||||||
|
"skipDownloadBeforeDebug": false,
|
||||||
|
"enablePageEraser": false,
|
||||||
|
"enableNoZeroWaitingAreaFlash": false
|
||||||
|
},
|
||||||
|
"gdbCfg": {
|
||||||
|
"executable": "/usr/share/MRS2/MRS-linux-x64/resources/app/resources/linux/components/WCH/Toolchain/RISC-V Embedded GCC12/bin/riscv-wch-elf-gdb",
|
||||||
|
"commands": [
|
||||||
|
"set mem inaccessible-by-default off",
|
||||||
|
"set architecture riscv:rv32",
|
||||||
|
"set remotetimeout unlimited",
|
||||||
|
"set disassembler-options xw"
|
||||||
|
],
|
||||||
|
"options": []
|
||||||
|
},
|
||||||
|
"startup": {
|
||||||
|
"initCommands": {
|
||||||
|
"initReset": true,
|
||||||
|
"initResetType": "init",
|
||||||
|
"armSemihosting": false,
|
||||||
|
"additionalCommands": []
|
||||||
|
},
|
||||||
|
"loadedFiles": {
|
||||||
|
"executableFile": "/home/bruno/Documents/Programming/projects/femtomesh_sw/obj/femtomesh_sw.elf",
|
||||||
|
"symbolFile": "/home/bruno/Documents/Programming/projects/femtomesh_sw/obj/femtomesh_sw.elf",
|
||||||
|
"executableFileOffset": 0,
|
||||||
|
"symbolFileOffset": 0
|
||||||
|
},
|
||||||
|
"runCommands": {
|
||||||
|
"runReset": true,
|
||||||
|
"runResetType": "halt",
|
||||||
|
"additionalCommands": [],
|
||||||
|
"setBreakAt": "handle_reset",
|
||||||
|
"continue": true,
|
||||||
|
"setProgramCounterAt": 0
|
||||||
|
},
|
||||||
|
"debugInRAM": false
|
||||||
|
},
|
||||||
|
"svdpath": "/usr/share/MRS2/MRS-linux-x64/resources/app/resources/linux/components/WCH/SDK/default/RISC-V/CH32V307/NoneOS/CH32V307xx.svd",
|
||||||
|
"output": {
|
||||||
|
"showDebugGDBTrace": true,
|
||||||
|
"saveDebugOutputToFile": false,
|
||||||
|
"showDebugOutputTimestamps": true
|
||||||
|
},
|
||||||
|
"isDualCoreDebug": false,
|
||||||
|
"dualCoreDebugRole": null,
|
||||||
|
"architecture": "RISC-V"
|
||||||
|
}
|
||||||
|
]
|
||||||
|
}
|
||||||
34
.project
Normal file
34
.project
Normal file
@@ -0,0 +1,34 @@
|
|||||||
|
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||||
|
<projectDescription>
|
||||||
|
<name>femtomesh_sw</name>
|
||||||
|
<comment/>
|
||||||
|
<projects/>
|
||||||
|
<buildSpec>
|
||||||
|
<buildCommand>
|
||||||
|
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||||
|
<triggers>clean,full,incremental,</triggers>
|
||||||
|
<arguments/>
|
||||||
|
</buildCommand>
|
||||||
|
<buildCommand>
|
||||||
|
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||||
|
<triggers>full,incremental,</triggers>
|
||||||
|
<arguments/>
|
||||||
|
</buildCommand>
|
||||||
|
</buildSpec>
|
||||||
|
<natures>
|
||||||
|
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||||
|
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||||
|
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||||
|
</natures>
|
||||||
|
<linkedResources/>
|
||||||
|
<filteredResources>
|
||||||
|
<filter>
|
||||||
|
<name/>
|
||||||
|
<type>6</type>
|
||||||
|
<matcher>
|
||||||
|
<id>org.eclipse.ui.ide.multiFilter</id>
|
||||||
|
<arguments>1.0-name-matches-false-false-*.wvproj</arguments>
|
||||||
|
</matcher>
|
||||||
|
</filter>
|
||||||
|
</filteredResources>
|
||||||
|
</projectDescription>
|
||||||
25
.template
Normal file
25
.template
Normal file
@@ -0,0 +1,25 @@
|
|||||||
|
Vendor=WCH
|
||||||
|
Toolchain=RISC-V
|
||||||
|
Series=CH32V307
|
||||||
|
RTOS=FreeRTOS
|
||||||
|
CalibrateSupport=false
|
||||||
|
CalibrateCommand=
|
||||||
|
MCU=CH32V307-FreeRTOS
|
||||||
|
Link=WCH-Link
|
||||||
|
PeripheralVersion=2.8
|
||||||
|
Description=Website: http://www.wch.cn/products/CH32V307.html?\nROM(byte): 256K, SRAM(byte): 64K, CHIP PINS: 64, GPIO PORTS: 51.\nWCH CH32V3 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
|
||||||
|
Mcu Type=CH32V30x
|
||||||
|
Address=0x08000000
|
||||||
|
Target Path=obj\femtomesh_sw.hex
|
||||||
|
Exe Path=
|
||||||
|
Exe Arguments=
|
||||||
|
CLKSpeed=1
|
||||||
|
DebugInterfaceMode=0
|
||||||
|
Erase All=true
|
||||||
|
Program=true
|
||||||
|
Verify=true
|
||||||
|
Reset=true
|
||||||
|
SDIPrintf=false
|
||||||
|
Disable Power Output=false
|
||||||
|
Clear CodeFlash=false
|
||||||
|
Disable Code-Protect=false
|
||||||
392
Core/core_riscv.c
Normal file
392
Core/core_riscv.c
Normal file
@@ -0,0 +1,392 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : core_riscv.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.1
|
||||||
|
* Date : 2023/11/11
|
||||||
|
* Description : RISC-V V4 Core Peripheral Access Layer Source File for CH32V30x
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
/* define compiler specific symbols */
|
||||||
|
#if defined ( __CC_ARM )
|
||||||
|
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||||
|
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||||
|
|
||||||
|
#elif defined ( __ICCARM__ )
|
||||||
|
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
||||||
|
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
|
||||||
|
|
||||||
|
#elif defined ( __GNUC__ )
|
||||||
|
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||||
|
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||||
|
|
||||||
|
#elif defined ( __TASKING__ )
|
||||||
|
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
||||||
|
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_FFLAGS
|
||||||
|
*
|
||||||
|
* @brief Return the Floating-Point Accrued Exceptions
|
||||||
|
*
|
||||||
|
* @return fflags value
|
||||||
|
*/
|
||||||
|
uint32_t __get_FFLAGS(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "fflags" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __set_FFLAGS
|
||||||
|
*
|
||||||
|
* @brief Set the Floating-Point Accrued Exceptions
|
||||||
|
*
|
||||||
|
* @param value - set FFLAGS value
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void __set_FFLAGS(uint32_t value)
|
||||||
|
{
|
||||||
|
__ASM volatile ("csrw fflags, %0" : : "r" (value) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_FRM
|
||||||
|
*
|
||||||
|
* @brief Return the Floating-Point Dynamic Rounding Mode
|
||||||
|
*
|
||||||
|
* @return frm value
|
||||||
|
*/
|
||||||
|
uint32_t __get_FRM(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "frm" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __set_FRM
|
||||||
|
*
|
||||||
|
* @brief Set the Floating-Point Dynamic Rounding Mode
|
||||||
|
*
|
||||||
|
* @param value - set frm value
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void __set_FRM(uint32_t value)
|
||||||
|
{
|
||||||
|
__ASM volatile ("csrw frm, %0" : : "r" (value) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_FCSR
|
||||||
|
*
|
||||||
|
* @brief Return the Floating-Point Control and Status Register
|
||||||
|
*
|
||||||
|
* @return fcsr value
|
||||||
|
*/
|
||||||
|
uint32_t __get_FCSR(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "fcsr" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __set_FCSR
|
||||||
|
*
|
||||||
|
* @brief Set the Floating-Point Dynamic Rounding Mode
|
||||||
|
*
|
||||||
|
* @param value - set fcsr value
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void __set_FCSR(uint32_t value)
|
||||||
|
{
|
||||||
|
__ASM volatile ("csrw fcsr, %0" : : "r" (value) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_MSTATUS
|
||||||
|
*
|
||||||
|
* @brief Return the Machine Status Register
|
||||||
|
*
|
||||||
|
* @return mstatus value
|
||||||
|
*/
|
||||||
|
uint32_t __get_MSTATUS(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "mstatus" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __set_MSTATUS
|
||||||
|
*
|
||||||
|
* @brief Set the Machine Status Register
|
||||||
|
*
|
||||||
|
* @param value - set mstatus value
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void __set_MSTATUS(uint32_t value)
|
||||||
|
{
|
||||||
|
__ASM volatile ("csrw mstatus, %0" : : "r" (value) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_MISA
|
||||||
|
*
|
||||||
|
* @brief Return the Machine ISA Register
|
||||||
|
*
|
||||||
|
* @return misa value
|
||||||
|
*/
|
||||||
|
uint32_t __get_MISA(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "misa" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __set_MISA
|
||||||
|
*
|
||||||
|
* @brief Set the Machine ISA Register
|
||||||
|
*
|
||||||
|
* @param value - set misa value
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void __set_MISA(uint32_t value)
|
||||||
|
{
|
||||||
|
__ASM volatile ("csrw misa, %0" : : "r" (value) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_MTVEC
|
||||||
|
*
|
||||||
|
* @brief Return the Machine Trap-Vector Base-Address Register
|
||||||
|
*
|
||||||
|
* @return mtvec value
|
||||||
|
*/
|
||||||
|
uint32_t __get_MTVEC(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "mtvec" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __set_MTVEC
|
||||||
|
*
|
||||||
|
* @brief Set the Machine Trap-Vector Base-Address Register
|
||||||
|
*
|
||||||
|
* @param value - set mtvec value
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void __set_MTVEC(uint32_t value)
|
||||||
|
{
|
||||||
|
__ASM volatile ("csrw mtvec, %0" : : "r" (value) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_MSCRATCH
|
||||||
|
*
|
||||||
|
* @brief Return the Machine Seratch Register
|
||||||
|
*
|
||||||
|
* @return mscratch value
|
||||||
|
*/
|
||||||
|
uint32_t __get_MSCRATCH(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "mscratch" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __set_MSCRATCH
|
||||||
|
*
|
||||||
|
* @brief Set the Machine Seratch Register
|
||||||
|
*
|
||||||
|
* @param value - set mscratch value
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void __set_MSCRATCH(uint32_t value)
|
||||||
|
{
|
||||||
|
__ASM volatile ("csrw mscratch, %0" : : "r" (value) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_MEPC
|
||||||
|
*
|
||||||
|
* @brief Return the Machine Exception Program Register
|
||||||
|
*
|
||||||
|
* @return mepc value
|
||||||
|
*/
|
||||||
|
uint32_t __get_MEPC(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "mepc" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __set_MEPC
|
||||||
|
*
|
||||||
|
* @brief Set the Machine Exception Program Register
|
||||||
|
*
|
||||||
|
* @return mepc value
|
||||||
|
*/
|
||||||
|
void __set_MEPC(uint32_t value)
|
||||||
|
{
|
||||||
|
__ASM volatile ("csrw mepc, %0" : : "r" (value) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_MCAUSE
|
||||||
|
*
|
||||||
|
* @brief Return the Machine Cause Register
|
||||||
|
*
|
||||||
|
* @return mcause value
|
||||||
|
*/
|
||||||
|
uint32_t __get_MCAUSE(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "mcause" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __set_MEPC
|
||||||
|
*
|
||||||
|
* @brief Set the Machine Cause Register
|
||||||
|
*
|
||||||
|
* @return mcause value
|
||||||
|
*/
|
||||||
|
void __set_MCAUSE(uint32_t value)
|
||||||
|
{
|
||||||
|
__ASM volatile ("csrw mcause, %0" : : "r" (value) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_MTVAL
|
||||||
|
*
|
||||||
|
* @brief Return the Machine Trap Value Register
|
||||||
|
*
|
||||||
|
* @return mtval value
|
||||||
|
*/
|
||||||
|
uint32_t __get_MTVAL(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "mtval" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __set_MTVAL
|
||||||
|
*
|
||||||
|
* @brief Set the Machine Trap Value Register
|
||||||
|
*
|
||||||
|
* @return mtval value
|
||||||
|
*/
|
||||||
|
void __set_MTVAL(uint32_t value)
|
||||||
|
{
|
||||||
|
__ASM volatile ("csrw mtval, %0" : : "r" (value) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_MVENDORID
|
||||||
|
*
|
||||||
|
* @brief Return Vendor ID Register
|
||||||
|
*
|
||||||
|
* @return mvendorid value
|
||||||
|
*/
|
||||||
|
uint32_t __get_MVENDORID(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_MARCHID
|
||||||
|
*
|
||||||
|
* @brief Return Machine Architecture ID Register
|
||||||
|
*
|
||||||
|
* @return marchid value
|
||||||
|
*/
|
||||||
|
uint32_t __get_MARCHID(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "marchid" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_MIMPID
|
||||||
|
*
|
||||||
|
* @brief Return Machine Implementation ID Register
|
||||||
|
*
|
||||||
|
* @return mimpid value
|
||||||
|
*/
|
||||||
|
uint32_t __get_MIMPID(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "mimpid" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_MHARTID
|
||||||
|
*
|
||||||
|
* @brief Return Hart ID Register
|
||||||
|
*
|
||||||
|
* @return mhartid value
|
||||||
|
*/
|
||||||
|
uint32_t __get_MHARTID(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "csrr %0," "mhartid" : "=r" (result) );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_SP
|
||||||
|
*
|
||||||
|
* @brief Return SP Register
|
||||||
|
*
|
||||||
|
* @return SP value
|
||||||
|
*/
|
||||||
|
uint32_t __get_SP(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__ASM volatile ( "mv %0," "sp" : "=r"(result) : );
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
599
Core/core_riscv.h
Normal file
599
Core/core_riscv.h
Normal file
@@ -0,0 +1,599 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : core_riscv.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.2
|
||||||
|
* Date : 2025/03/06
|
||||||
|
* Description : RISC-V V4 Core Peripheral Access Layer Header File for CH32V30x
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CORE_RISCV_H__
|
||||||
|
#define __CORE_RISCV_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* IO definitions */
|
||||||
|
#ifdef __cplusplus
|
||||||
|
#define __I volatile /* defines 'read only' permissions */
|
||||||
|
#else
|
||||||
|
#define __I volatile const /* defines 'read only' permissions */
|
||||||
|
#endif
|
||||||
|
#define __O volatile /* defines 'write only' permissions */
|
||||||
|
#define __IO volatile /* defines 'read / write' permissions */
|
||||||
|
|
||||||
|
/* Standard Peripheral Library old types (maintained for legacy purpose) */
|
||||||
|
typedef __I uint64_t vuc64; /* Read Only */
|
||||||
|
typedef __I uint32_t vuc32; /* Read Only */
|
||||||
|
typedef __I uint16_t vuc16; /* Read Only */
|
||||||
|
typedef __I uint8_t vuc8; /* Read Only */
|
||||||
|
|
||||||
|
typedef const uint64_t uc64; /* Read Only */
|
||||||
|
typedef const uint32_t uc32; /* Read Only */
|
||||||
|
typedef const uint16_t uc16; /* Read Only */
|
||||||
|
typedef const uint8_t uc8; /* Read Only */
|
||||||
|
|
||||||
|
typedef __I int64_t vsc64; /* Read Only */
|
||||||
|
typedef __I int32_t vsc32; /* Read Only */
|
||||||
|
typedef __I int16_t vsc16; /* Read Only */
|
||||||
|
typedef __I int8_t vsc8; /* Read Only */
|
||||||
|
|
||||||
|
typedef const int64_t sc64; /* Read Only */
|
||||||
|
typedef const int32_t sc32; /* Read Only */
|
||||||
|
typedef const int16_t sc16; /* Read Only */
|
||||||
|
typedef const int8_t sc8; /* Read Only */
|
||||||
|
|
||||||
|
typedef __IO uint64_t vu64;
|
||||||
|
typedef __IO uint32_t vu32;
|
||||||
|
//typedef __IO uint16_t volatile uint16_t;
|
||||||
|
//typedef __IO uint8_t volatile uint8_t;
|
||||||
|
|
||||||
|
typedef uint64_t u64;
|
||||||
|
typedef uint32_t u32;
|
||||||
|
typedef uint16_t u16;
|
||||||
|
typedef uint8_t u8;
|
||||||
|
|
||||||
|
typedef __IO int64_t vs64;
|
||||||
|
typedef __IO int32_t vs32;
|
||||||
|
typedef __IO int16_t vs16;
|
||||||
|
typedef __IO int8_t vs8;
|
||||||
|
|
||||||
|
typedef int64_t s64;
|
||||||
|
typedef int32_t s32;
|
||||||
|
typedef int16_t s16;
|
||||||
|
typedef int8_t s8;
|
||||||
|
|
||||||
|
typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus;
|
||||||
|
|
||||||
|
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
|
||||||
|
|
||||||
|
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
|
||||||
|
|
||||||
|
#define RV_STATIC_INLINE static inline
|
||||||
|
|
||||||
|
/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
|
||||||
|
typedef struct{
|
||||||
|
__I uint32_t ISR[8];
|
||||||
|
__I uint32_t IPR[8];
|
||||||
|
__IO uint32_t ITHRESDR;
|
||||||
|
__IO uint32_t RESERVED;
|
||||||
|
__IO uint32_t CFGR;
|
||||||
|
__I uint32_t GISR;
|
||||||
|
__IO uint8_t VTFIDR[4];
|
||||||
|
uint8_t RESERVED0[12];
|
||||||
|
__IO uint32_t VTFADDR[4];
|
||||||
|
uint8_t RESERVED1[0x90];
|
||||||
|
__O uint32_t IENR[8];
|
||||||
|
uint8_t RESERVED2[0x60];
|
||||||
|
__O uint32_t IRER[8];
|
||||||
|
uint8_t RESERVED3[0x60];
|
||||||
|
__O uint32_t IPSR[8];
|
||||||
|
uint8_t RESERVED4[0x60];
|
||||||
|
__O uint32_t IPRR[8];
|
||||||
|
uint8_t RESERVED5[0x60];
|
||||||
|
__IO uint32_t IACTR[8];
|
||||||
|
uint8_t RESERVED6[0xE0];
|
||||||
|
__IO uint8_t IPRIOR[256];
|
||||||
|
uint8_t RESERVED7[0x810];
|
||||||
|
__IO uint32_t SCTLR;
|
||||||
|
}PFIC_Type;
|
||||||
|
|
||||||
|
/* memory mapped structure for SysTick */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
__IO uint32_t CTLR;
|
||||||
|
__IO uint32_t SR;
|
||||||
|
__IO uint64_t CNT;
|
||||||
|
__IO uint64_t CMP;
|
||||||
|
}SysTick_Type;
|
||||||
|
|
||||||
|
|
||||||
|
#define PFIC ((PFIC_Type *) 0xE000E000 )
|
||||||
|
#define NVIC PFIC
|
||||||
|
#define NVIC_KEY1 ((uint32_t)0xFA050000)
|
||||||
|
#define NVIC_KEY2 ((uint32_t)0xBCAF0000)
|
||||||
|
#define NVIC_KEY3 ((uint32_t)0xBEEF0000)
|
||||||
|
|
||||||
|
#define SysTick ((SysTick_Type *) 0xE000F000)
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __enable_irq
|
||||||
|
*
|
||||||
|
* @brief Enable Global Interrupt
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq()
|
||||||
|
{
|
||||||
|
__asm volatile ("csrs 0x800, %0" : : "r" (0x88) );
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __disable_irq
|
||||||
|
*
|
||||||
|
* @brief Disable Global Interrupt
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq()
|
||||||
|
{
|
||||||
|
__asm volatile ("csrc 0x800, %0" : : "r" (0x88) );
|
||||||
|
__asm volatile ("fence.i");
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __NOP
|
||||||
|
*
|
||||||
|
* @brief nop
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP()
|
||||||
|
{
|
||||||
|
__asm volatile ("nop");
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn NVIC_EnableIRQ
|
||||||
|
*
|
||||||
|
* @brief Enable Interrupt
|
||||||
|
*
|
||||||
|
* @param IRQn - Interrupt Numbers
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn NVIC_DisableIRQ
|
||||||
|
*
|
||||||
|
* @brief Disable Interrupt
|
||||||
|
*
|
||||||
|
* @param IRQn - Interrupt Numbers
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||||
|
__asm volatile ("fence.i");
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn NVIC_GetStatusIRQ
|
||||||
|
*
|
||||||
|
* @brief Get Interrupt Enable State
|
||||||
|
*
|
||||||
|
* @param IRQn - Interrupt Numbers
|
||||||
|
*
|
||||||
|
* @return 1 - Interrupt Enable
|
||||||
|
* 0 - Interrupt Disable
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn NVIC_GetPendingIRQ
|
||||||
|
*
|
||||||
|
* @brief Get Interrupt Pending State
|
||||||
|
*
|
||||||
|
* @param IRQn - Interrupt Numbers
|
||||||
|
*
|
||||||
|
* @return 1 - Interrupt Pending Enable
|
||||||
|
* 0 - Interrupt Pending Disable
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn NVIC_SetPendingIRQ
|
||||||
|
*
|
||||||
|
* @brief Set Interrupt Pending
|
||||||
|
*
|
||||||
|
* @param IRQn - Interrupt Numbers
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn NVIC_ClearPendingIRQ
|
||||||
|
*
|
||||||
|
* @brief Clear Interrupt Pending
|
||||||
|
*
|
||||||
|
* @param IRQn - Interrupt Numbers
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn NVIC_GetActive
|
||||||
|
*
|
||||||
|
* @brief Get Interrupt Active State
|
||||||
|
*
|
||||||
|
* @param IRQn - Interrupt Numbers
|
||||||
|
*
|
||||||
|
* @return 1 - Interrupt Active
|
||||||
|
* 0 - Interrupt No Active
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn NVIC_SetPriority
|
||||||
|
*
|
||||||
|
* @brief Set Interrupt Priority
|
||||||
|
*
|
||||||
|
* @param IRQn - Interrupt Numbers
|
||||||
|
* interrupt nesting enable-8 Level(CSR-0x804 bit1 = 1 bit[3:2] = 3)
|
||||||
|
* priority - bit[7:5] - Preemption Priority
|
||||||
|
* bit[4:0] - Reserve
|
||||||
|
* interrupt nesting enable-4 Level(CSR-0x804 bit1 = 1 bit[3:2] = 2)
|
||||||
|
* priority - bit[7:6] - Preemption Priority
|
||||||
|
* bit[5] - Sub priority
|
||||||
|
* bit[4:0] - Reserve
|
||||||
|
* interrupt nesting enable-2 Level(CSR-0x804 bit1 = 1 bit[3:2] = 1)
|
||||||
|
* priority - bit[7] - Preemption Priority
|
||||||
|
* bit[6:5] - Sub priority
|
||||||
|
* bit[4:0] - Reserve
|
||||||
|
* interrupt nesting disable(CSR-0x804 bit1 = 0)
|
||||||
|
* priority - bit[7:5] - Sub priority
|
||||||
|
* bit[4:0] - Reserve
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
|
||||||
|
{
|
||||||
|
NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __WFI
|
||||||
|
*
|
||||||
|
* @brief Wait for Interrupt
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
|
||||||
|
{
|
||||||
|
NVIC->SCTLR &= ~(1<<3); // wfi
|
||||||
|
asm volatile ("wfi");
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn _SEV
|
||||||
|
*
|
||||||
|
* @brief Set Event
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void)
|
||||||
|
{
|
||||||
|
uint32_t t;
|
||||||
|
|
||||||
|
t = NVIC->SCTLR;
|
||||||
|
NVIC->SCTLR |= (1<<3)|(1<<5);
|
||||||
|
NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn _WFE
|
||||||
|
*
|
||||||
|
* @brief Wait for Events
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void)
|
||||||
|
{
|
||||||
|
NVIC->SCTLR |= (1<<3);
|
||||||
|
asm volatile ("wfi");
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __WFE
|
||||||
|
*
|
||||||
|
* @brief Wait for Events
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
|
||||||
|
{
|
||||||
|
_SEV();
|
||||||
|
_WFE();
|
||||||
|
_WFE();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SetVTFIRQ
|
||||||
|
*
|
||||||
|
* @brief Set VTF Interrupt
|
||||||
|
*
|
||||||
|
* @param add - VTF interrupt service function base address.
|
||||||
|
* IRQn -Interrupt Numbers
|
||||||
|
* num - VTF Interrupt Numbers
|
||||||
|
* NewState - DISABLE or ENABLE
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(num > 3) return ;
|
||||||
|
|
||||||
|
if (NewState != DISABLE)
|
||||||
|
{
|
||||||
|
NVIC->VTFIDR[num] = IRQn;
|
||||||
|
NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
NVIC->VTFIDR[num] = IRQn;
|
||||||
|
NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn NVIC_SystemReset
|
||||||
|
*
|
||||||
|
* @brief Initiate a system reset request
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
|
{
|
||||||
|
NVIC->CFGR = NVIC_KEY3|(1<<7);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __AMOADD_W
|
||||||
|
*
|
||||||
|
* @brief Atomic Add with 32bit value
|
||||||
|
* Atomically ADD 32bit value with value in memory using amoadd.d.
|
||||||
|
*
|
||||||
|
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||||
|
* value - value to be ADDed
|
||||||
|
*
|
||||||
|
* @return return memory value + add value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value)
|
||||||
|
{
|
||||||
|
int32_t result;
|
||||||
|
|
||||||
|
__asm volatile ("amoadd.w %0, %2, %1" : \
|
||||||
|
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||||
|
return *addr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __AMOAND_W
|
||||||
|
*
|
||||||
|
* @brief Atomic And with 32bit value
|
||||||
|
* Atomically AND 32bit value with value in memory using amoand.d.
|
||||||
|
*
|
||||||
|
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||||
|
* value - value to be ANDed
|
||||||
|
*
|
||||||
|
* @return return memory value & and value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value)
|
||||||
|
{
|
||||||
|
int32_t result;
|
||||||
|
|
||||||
|
__asm volatile ("amoand.w %0, %2, %1" : \
|
||||||
|
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||||
|
return *addr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __AMOMAX_W
|
||||||
|
*
|
||||||
|
* @brief Atomic signed MAX with 32bit value
|
||||||
|
* Atomically signed max compare 32bit value with value in memory using amomax.d.
|
||||||
|
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||||
|
* value - value to be compared
|
||||||
|
*
|
||||||
|
* @return return the bigger value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value)
|
||||||
|
{
|
||||||
|
int32_t result;
|
||||||
|
|
||||||
|
__asm volatile ("amomax.w %0, %2, %1" : \
|
||||||
|
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||||
|
return *addr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __AMOMAXU_W
|
||||||
|
*
|
||||||
|
* @brief Atomic unsigned MAX with 32bit value
|
||||||
|
* Atomically unsigned max compare 32bit value with value in memory using amomaxu.d.
|
||||||
|
*
|
||||||
|
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||||
|
* value - value to be compared
|
||||||
|
*
|
||||||
|
* @return return the bigger value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__asm volatile ("amomaxu.w %0, %2, %1" : \
|
||||||
|
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||||
|
return *addr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __AMOMIN_W
|
||||||
|
*
|
||||||
|
* @brief Atomic signed MIN with 32bit value
|
||||||
|
* Atomically signed min compare 32bit value with value in memory using amomin.d.
|
||||||
|
*
|
||||||
|
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||||
|
* value - value to be compared
|
||||||
|
*
|
||||||
|
* @return return the smaller value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value)
|
||||||
|
{
|
||||||
|
int32_t result;
|
||||||
|
|
||||||
|
__asm volatile ("amomin.w %0, %2, %1" : \
|
||||||
|
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||||
|
return *addr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __AMOMINU_W
|
||||||
|
*
|
||||||
|
* @brief Atomic unsigned MIN with 32bit value
|
||||||
|
* Atomically unsigned min compare 32bit value with value in memory using amominu.d.
|
||||||
|
*
|
||||||
|
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||||
|
* value - value to be compared
|
||||||
|
*
|
||||||
|
* @return return the smaller value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__asm volatile ("amominu.w %0, %2, %1" : \
|
||||||
|
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||||
|
return *addr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __AMOOR_W
|
||||||
|
*
|
||||||
|
* @brief Atomic OR with 32bit value
|
||||||
|
* Atomically OR 32bit value with value in memory using amoor.d.
|
||||||
|
*
|
||||||
|
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||||
|
* value - value to be ORed
|
||||||
|
*
|
||||||
|
* @return return memory value | and value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value)
|
||||||
|
{
|
||||||
|
int32_t result;
|
||||||
|
|
||||||
|
__asm volatile ("amoor.w %0, %2, %1" : \
|
||||||
|
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||||
|
return *addr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __AMOSWAP_W
|
||||||
|
*
|
||||||
|
* @brief Atomically swap new 32bit value into memory using amoswap.d.
|
||||||
|
*
|
||||||
|
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||||
|
* newval - New value to be stored into the address
|
||||||
|
*
|
||||||
|
* @return return the original value in memory
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__asm volatile ("amoswap.w %0, %2, %1" : \
|
||||||
|
"=r"(result), "+A"(*addr) : "r"(newval) : "memory");
|
||||||
|
return result;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __AMOXOR_W
|
||||||
|
*
|
||||||
|
* @brief Atomic XOR with 32bit value
|
||||||
|
* Atomically XOR 32bit value with value in memory using amoxor.d.
|
||||||
|
*
|
||||||
|
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||||
|
* value - value to be XORed
|
||||||
|
*
|
||||||
|
* @return return memory value ^ and value
|
||||||
|
*/
|
||||||
|
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value)
|
||||||
|
{
|
||||||
|
int32_t result;
|
||||||
|
|
||||||
|
__asm volatile ("amoxor.w %0, %2, %1" : \
|
||||||
|
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||||
|
return *addr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Core_Exported_Functions */
|
||||||
|
extern uint32_t __get_FFLAGS(void);
|
||||||
|
extern void __set_FFLAGS(uint32_t value);
|
||||||
|
extern uint32_t __get_FRM(void);
|
||||||
|
extern void __set_FRM(uint32_t value);
|
||||||
|
extern uint32_t __get_FCSR(void);
|
||||||
|
extern void __set_FCSR(uint32_t value);
|
||||||
|
extern uint32_t __get_MSTATUS(void);
|
||||||
|
extern void __set_MSTATUS(uint32_t value);
|
||||||
|
extern uint32_t __get_MISA(void);
|
||||||
|
extern void __set_MISA(uint32_t value);
|
||||||
|
extern uint32_t __get_MTVEC(void);
|
||||||
|
extern void __set_MTVEC(uint32_t value);
|
||||||
|
extern uint32_t __get_MSCRATCH(void);
|
||||||
|
extern void __set_MSCRATCH(uint32_t value);
|
||||||
|
extern uint32_t __get_MEPC(void);
|
||||||
|
extern void __set_MEPC(uint32_t value);
|
||||||
|
extern uint32_t __get_MCAUSE(void);
|
||||||
|
extern void __set_MCAUSE(uint32_t value);
|
||||||
|
extern uint32_t __get_MTVAL(void);
|
||||||
|
extern void __set_MTVAL(uint32_t value);
|
||||||
|
extern uint32_t __get_MVENDORID(void);
|
||||||
|
extern uint32_t __get_MARCHID(void);
|
||||||
|
extern uint32_t __get_MIMPID(void);
|
||||||
|
extern uint32_t __get_MHARTID(void);
|
||||||
|
extern uint32_t __get_SP(void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
253
Debug/debug.c
Normal file
253
Debug/debug.c
Normal file
@@ -0,0 +1,253 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : debug.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for UART
|
||||||
|
* Printf , Delay functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "debug.h"
|
||||||
|
|
||||||
|
static uint8_t p_us = 0;
|
||||||
|
static uint16_t p_ms = 0;
|
||||||
|
|
||||||
|
#define DEBUG_DATA0_ADDRESS ((volatile uint32_t*)0xE0000380)
|
||||||
|
#define DEBUG_DATA1_ADDRESS ((volatile uint32_t*)0xE0000384)
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn Delay_Init
|
||||||
|
*
|
||||||
|
* @brief Initializes Delay Funcation.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void Delay_Init(void)
|
||||||
|
{
|
||||||
|
p_us = SystemCoreClock / 8000000;
|
||||||
|
p_ms = (uint16_t)p_us * 1000;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn Delay_Us
|
||||||
|
*
|
||||||
|
* @brief Microsecond Delay Time.
|
||||||
|
*
|
||||||
|
* @param n - Microsecond number.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void Delay_Us(uint32_t n)
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
|
||||||
|
SysTick->SR &= ~(1 << 0);
|
||||||
|
i = (uint32_t)n * p_us;
|
||||||
|
|
||||||
|
SysTick->CMP = i;
|
||||||
|
SysTick->CTLR |= (1 << 4);
|
||||||
|
SysTick->CTLR |= (1 << 5) | (1 << 0);
|
||||||
|
|
||||||
|
while((SysTick->SR & (1 << 0)) != (1 << 0))
|
||||||
|
;
|
||||||
|
SysTick->CTLR &= ~(1 << 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn Delay_Ms
|
||||||
|
*
|
||||||
|
* @brief Millisecond Delay Time.
|
||||||
|
*
|
||||||
|
* @param n - Millisecond number.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void Delay_Ms(uint32_t n)
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
|
||||||
|
SysTick->SR &= ~(1 << 0);
|
||||||
|
i = (uint32_t)n * p_ms;
|
||||||
|
|
||||||
|
SysTick->CMP = i;
|
||||||
|
SysTick->CTLR |= (1 << 4);
|
||||||
|
SysTick->CTLR |= (1 << 5) | (1 << 0);
|
||||||
|
|
||||||
|
while((SysTick->SR & (1 << 0)) != (1 << 0))
|
||||||
|
;
|
||||||
|
SysTick->CTLR &= ~(1 << 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn USART_Printf_Init
|
||||||
|
*
|
||||||
|
* @brief Initializes the USARTx peripheral.
|
||||||
|
*
|
||||||
|
* @param baudrate - USART communication baud rate.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void USART_Printf_Init(uint32_t baudrate)
|
||||||
|
{
|
||||||
|
GPIO_InitTypeDef GPIO_InitStructure;
|
||||||
|
USART_InitTypeDef USART_InitStructure;
|
||||||
|
|
||||||
|
#if(DEBUG == DEBUG_UART1)
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE);
|
||||||
|
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
|
||||||
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||||
|
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||||
|
|
||||||
|
#elif(DEBUG == DEBUG_UART2)
|
||||||
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
|
||||||
|
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
|
||||||
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||||
|
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||||
|
|
||||||
|
#elif(DEBUG == DEBUG_UART3)
|
||||||
|
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
|
||||||
|
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10;
|
||||||
|
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||||
|
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
USART_InitStructure.USART_BaudRate = baudrate;
|
||||||
|
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
|
||||||
|
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
||||||
|
USART_InitStructure.USART_Parity = USART_Parity_No;
|
||||||
|
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||||
|
USART_InitStructure.USART_Mode = USART_Mode_Tx;
|
||||||
|
|
||||||
|
#if(DEBUG == DEBUG_UART1)
|
||||||
|
USART_Init(USART1, &USART_InitStructure);
|
||||||
|
USART_Cmd(USART1, ENABLE);
|
||||||
|
|
||||||
|
#elif(DEBUG == DEBUG_UART2)
|
||||||
|
USART_Init(USART2, &USART_InitStructure);
|
||||||
|
USART_Cmd(USART2, ENABLE);
|
||||||
|
|
||||||
|
#elif(DEBUG == DEBUG_UART3)
|
||||||
|
USART_Init(USART3, &USART_InitStructure);
|
||||||
|
USART_Cmd(USART3, ENABLE);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDI_Printf_Enable
|
||||||
|
*
|
||||||
|
* @brief Initializes the SDI printf Function.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void SDI_Printf_Enable(void)
|
||||||
|
{
|
||||||
|
*(DEBUG_DATA0_ADDRESS) = 0;
|
||||||
|
Delay_Init();
|
||||||
|
Delay_Ms(1);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn _write
|
||||||
|
*
|
||||||
|
* @brief Support Printf Function
|
||||||
|
*
|
||||||
|
* @param *buf - UART send Data.
|
||||||
|
* size - Data length
|
||||||
|
*
|
||||||
|
* @return size: Data length
|
||||||
|
*/
|
||||||
|
__attribute__((used)) int _write(int fd, char *buf, int size)
|
||||||
|
{
|
||||||
|
int i = 0;
|
||||||
|
|
||||||
|
#if (SDI_PRINT == SDI_PR_OPEN)
|
||||||
|
int writeSize = size;
|
||||||
|
|
||||||
|
do
|
||||||
|
{
|
||||||
|
|
||||||
|
/**
|
||||||
|
* data0 data1 8 bytes
|
||||||
|
* data0 The lowest byte storage length, the maximum is 7
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
while( (*(DEBUG_DATA0_ADDRESS) != 0u))
|
||||||
|
{
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
if(writeSize>7)
|
||||||
|
{
|
||||||
|
*(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24);
|
||||||
|
*(DEBUG_DATA0_ADDRESS) = (7u) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24);
|
||||||
|
|
||||||
|
i += 7;
|
||||||
|
writeSize -= 7;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
*(DEBUG_DATA1_ADDRESS) = (*(buf+i+3)) | (*(buf+i+4)<<8) | (*(buf+i+5)<<16) | (*(buf+i+6)<<24);
|
||||||
|
*(DEBUG_DATA0_ADDRESS) = (writeSize) | (*(buf+i)<<8) | (*(buf+i+1)<<16) | (*(buf+i+2)<<24);
|
||||||
|
|
||||||
|
writeSize = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
} while (writeSize);
|
||||||
|
|
||||||
|
|
||||||
|
#else
|
||||||
|
for(i = 0; i < size; i++)
|
||||||
|
{
|
||||||
|
#if(DEBUG == DEBUG_UART1)
|
||||||
|
while(USART_GetFlagStatus(USART1, USART_FLAG_TC) == RESET);
|
||||||
|
USART_SendData(USART1, *buf++);
|
||||||
|
#elif(DEBUG == DEBUG_UART2)
|
||||||
|
while(USART_GetFlagStatus(USART2, USART_FLAG_TC) == RESET);
|
||||||
|
USART_SendData(USART2, *buf++);
|
||||||
|
#elif(DEBUG == DEBUG_UART3)
|
||||||
|
while(USART_GetFlagStatus(USART3, USART_FLAG_TC) == RESET);
|
||||||
|
USART_SendData(USART3, *buf++);
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
return size;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn _sbrk
|
||||||
|
*
|
||||||
|
* @brief Change the spatial position of data segment.
|
||||||
|
*
|
||||||
|
* @return size: Data length
|
||||||
|
*/
|
||||||
|
__attribute__((used)) void *_sbrk(ptrdiff_t incr)
|
||||||
|
{
|
||||||
|
extern char _end[];
|
||||||
|
extern char _heap_end[];
|
||||||
|
static char *curbrk = _end;
|
||||||
|
|
||||||
|
if ((curbrk + incr < _end) || (curbrk + incr > _heap_end))
|
||||||
|
return NULL - 1;
|
||||||
|
|
||||||
|
curbrk += incr;
|
||||||
|
return curbrk - incr;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
55
Debug/debug.h
Normal file
55
Debug/debug.h
Normal file
@@ -0,0 +1,55 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : debug.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for UART
|
||||||
|
* Printf , Delay functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __DEBUG_H
|
||||||
|
#define __DEBUG_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "stdio.h"
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* UART Printf Definition */
|
||||||
|
#define DEBUG_UART1 1
|
||||||
|
#define DEBUG_UART2 2
|
||||||
|
#define DEBUG_UART3 3
|
||||||
|
|
||||||
|
/* DEBUG UATR Definition */
|
||||||
|
#ifndef DEBUG
|
||||||
|
#define DEBUG DEBUG_UART1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* SDI Printf Definition */
|
||||||
|
#define SDI_PR_CLOSE 0
|
||||||
|
#define SDI_PR_OPEN 1
|
||||||
|
|
||||||
|
#ifndef SDI_PRINT
|
||||||
|
#define SDI_PRINT SDI_PR_CLOSE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
void Delay_Init(void);
|
||||||
|
void Delay_Us (uint32_t n);
|
||||||
|
void Delay_Ms (uint32_t n);
|
||||||
|
void USART_Printf_Init(uint32_t baudrate);
|
||||||
|
void SDI_Printf_Enable(void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
6
FreeRTOS/.gitmodules
vendored
Normal file
6
FreeRTOS/.gitmodules
vendored
Normal file
@@ -0,0 +1,6 @@
|
|||||||
|
[submodule "ThirdParty/FreeRTOS-Kernel-Partner-Supported-Ports"]
|
||||||
|
path = portable/ThirdParty/Partner-Supported-Ports
|
||||||
|
url = https://github.com/FreeRTOS/FreeRTOS-Kernel-Partner-Supported-Ports
|
||||||
|
[submodule "ThirdParty/FreeRTOS-Kernel-Community-Supported-Ports"]
|
||||||
|
path = portable/ThirdParty/Community-Supported-Ports
|
||||||
|
url = https://github.com/FreeRTOS/FreeRTOS-Kernel-Community-Supported-Ports
|
||||||
363
FreeRTOS/croutine.c
Normal file
363
FreeRTOS/croutine.c
Normal file
@@ -0,0 +1,363 @@
|
|||||||
|
/*
|
||||||
|
* FreeRTOS Kernel V10.4.6
|
||||||
|
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: MIT
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* https://www.FreeRTOS.org
|
||||||
|
* https://github.com/FreeRTOS
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "FreeRTOS.h"
|
||||||
|
#include "task.h"
|
||||||
|
#include "croutine.h"
|
||||||
|
|
||||||
|
/* Remove the whole file is co-routines are not being used. */
|
||||||
|
#if ( configUSE_CO_ROUTINES != 0 )
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Some kernel aware debuggers require data to be viewed to be global, rather
|
||||||
|
* than file scope.
|
||||||
|
*/
|
||||||
|
#ifdef portREMOVE_STATIC_QUALIFIER
|
||||||
|
#define static
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/* Lists for ready and blocked co-routines. --------------------*/
|
||||||
|
static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */
|
||||||
|
static List_t xDelayedCoRoutineList1; /*< Delayed co-routines. */
|
||||||
|
static List_t xDelayedCoRoutineList2; /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */
|
||||||
|
static List_t * pxDelayedCoRoutineList = NULL; /*< Points to the delayed co-routine list currently being used. */
|
||||||
|
static List_t * pxOverflowDelayedCoRoutineList = NULL; /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */
|
||||||
|
static List_t xPendingReadyCoRoutineList; /*< Holds co-routines that have been readied by an external event. They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */
|
||||||
|
|
||||||
|
/* Other file private variables. --------------------------------*/
|
||||||
|
CRCB_t * pxCurrentCoRoutine = NULL;
|
||||||
|
static UBaseType_t uxTopCoRoutineReadyPriority = 0;
|
||||||
|
static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0;
|
||||||
|
|
||||||
|
/* The initial state of the co-routine when it is created. */
|
||||||
|
#define corINITIAL_STATE ( 0 )
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Place the co-routine represented by pxCRCB into the appropriate ready queue
|
||||||
|
* for the priority. It is inserted at the end of the list.
|
||||||
|
*
|
||||||
|
* This macro accesses the co-routine ready lists and therefore must not be
|
||||||
|
* used from within an ISR.
|
||||||
|
*/
|
||||||
|
#define prvAddCoRoutineToReadyQueue( pxCRCB ) \
|
||||||
|
{ \
|
||||||
|
if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority ) \
|
||||||
|
{ \
|
||||||
|
uxTopCoRoutineReadyPriority = pxCRCB->uxPriority; \
|
||||||
|
} \
|
||||||
|
vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Utility to ready all the lists used by the scheduler. This is called
|
||||||
|
* automatically upon the creation of the first co-routine.
|
||||||
|
*/
|
||||||
|
static void prvInitialiseCoRoutineLists( void );
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Co-routines that are readied by an interrupt cannot be placed directly into
|
||||||
|
* the ready lists (there is no mutual exclusion). Instead they are placed in
|
||||||
|
* in the pending ready list in order that they can later be moved to the ready
|
||||||
|
* list by the co-routine scheduler.
|
||||||
|
*/
|
||||||
|
static void prvCheckPendingReadyList( void );
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Macro that looks at the list of co-routines that are currently delayed to
|
||||||
|
* see if any require waking.
|
||||||
|
*
|
||||||
|
* Co-routines are stored in the queue in the order of their wake time -
|
||||||
|
* meaning once one co-routine has been found whose timer has not expired
|
||||||
|
* we need not look any further down the list.
|
||||||
|
*/
|
||||||
|
static void prvCheckDelayedList( void );
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode,
|
||||||
|
UBaseType_t uxPriority,
|
||||||
|
UBaseType_t uxIndex )
|
||||||
|
{
|
||||||
|
BaseType_t xReturn;
|
||||||
|
CRCB_t * pxCoRoutine;
|
||||||
|
|
||||||
|
/* Allocate the memory that will store the co-routine control block. */
|
||||||
|
pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) );
|
||||||
|
|
||||||
|
if( pxCoRoutine )
|
||||||
|
{
|
||||||
|
/* If pxCurrentCoRoutine is NULL then this is the first co-routine to
|
||||||
|
* be created and the co-routine data structures need initialising. */
|
||||||
|
if( pxCurrentCoRoutine == NULL )
|
||||||
|
{
|
||||||
|
pxCurrentCoRoutine = pxCoRoutine;
|
||||||
|
prvInitialiseCoRoutineLists();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check the priority is within limits. */
|
||||||
|
if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES )
|
||||||
|
{
|
||||||
|
uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Fill out the co-routine control block from the function parameters. */
|
||||||
|
pxCoRoutine->uxState = corINITIAL_STATE;
|
||||||
|
pxCoRoutine->uxPriority = uxPriority;
|
||||||
|
pxCoRoutine->uxIndex = uxIndex;
|
||||||
|
pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode;
|
||||||
|
|
||||||
|
/* Initialise all the other co-routine control block parameters. */
|
||||||
|
vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) );
|
||||||
|
vListInitialiseItem( &( pxCoRoutine->xEventListItem ) );
|
||||||
|
|
||||||
|
/* Set the co-routine control block as a link back from the ListItem_t.
|
||||||
|
* This is so we can get back to the containing CRCB from a generic item
|
||||||
|
* in a list. */
|
||||||
|
listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine );
|
||||||
|
listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine );
|
||||||
|
|
||||||
|
/* Event lists are always in priority order. */
|
||||||
|
listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) );
|
||||||
|
|
||||||
|
/* Now the co-routine has been initialised it can be added to the ready
|
||||||
|
* list at the correct priority. */
|
||||||
|
prvAddCoRoutineToReadyQueue( pxCoRoutine );
|
||||||
|
|
||||||
|
xReturn = pdPASS;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
|
||||||
|
}
|
||||||
|
|
||||||
|
return xReturn;
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay,
|
||||||
|
List_t * pxEventList )
|
||||||
|
{
|
||||||
|
TickType_t xTimeToWake;
|
||||||
|
|
||||||
|
/* Calculate the time to wake - this may overflow but this is
|
||||||
|
* not a problem. */
|
||||||
|
xTimeToWake = xCoRoutineTickCount + xTicksToDelay;
|
||||||
|
|
||||||
|
/* We must remove ourselves from the ready list before adding
|
||||||
|
* ourselves to the blocked list as the same list item is used for
|
||||||
|
* both lists. */
|
||||||
|
( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
|
||||||
|
|
||||||
|
/* The list item will be inserted in wake time order. */
|
||||||
|
listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake );
|
||||||
|
|
||||||
|
if( xTimeToWake < xCoRoutineTickCount )
|
||||||
|
{
|
||||||
|
/* Wake time has overflowed. Place this item in the
|
||||||
|
* overflow list. */
|
||||||
|
vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* The wake time has not overflowed, so we can use the
|
||||||
|
* current block list. */
|
||||||
|
vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
|
||||||
|
}
|
||||||
|
|
||||||
|
if( pxEventList )
|
||||||
|
{
|
||||||
|
/* Also add the co-routine to an event list. If this is done then the
|
||||||
|
* function must be called with interrupts disabled. */
|
||||||
|
vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) );
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
static void prvCheckPendingReadyList( void )
|
||||||
|
{
|
||||||
|
/* Are there any co-routines waiting to get moved to the ready list? These
|
||||||
|
* are co-routines that have been readied by an ISR. The ISR cannot access
|
||||||
|
* the ready lists itself. */
|
||||||
|
while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pd0 )
|
||||||
|
{
|
||||||
|
CRCB_t * pxUnblockedCRCB;
|
||||||
|
|
||||||
|
/* The pending ready list can be accessed by an ISR. */
|
||||||
|
portDISABLE_INTERRUPTS();
|
||||||
|
{
|
||||||
|
pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyCoRoutineList ) );
|
||||||
|
( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
|
||||||
|
}
|
||||||
|
portENABLE_INTERRUPTS();
|
||||||
|
|
||||||
|
( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) );
|
||||||
|
prvAddCoRoutineToReadyQueue( pxUnblockedCRCB );
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
static void prvCheckDelayedList( void )
|
||||||
|
{
|
||||||
|
CRCB_t * pxCRCB;
|
||||||
|
|
||||||
|
xPassedTicks = xTaskGetTickCount() - xLastTickCount;
|
||||||
|
|
||||||
|
while( xPassedTicks )
|
||||||
|
{
|
||||||
|
xCoRoutineTickCount++;
|
||||||
|
xPassedTicks--;
|
||||||
|
|
||||||
|
/* If the tick count has overflowed we need to swap the ready lists. */
|
||||||
|
if( xCoRoutineTickCount == 0 )
|
||||||
|
{
|
||||||
|
List_t * pxTemp;
|
||||||
|
|
||||||
|
/* Tick count has overflowed so we need to swap the delay lists. If there are
|
||||||
|
* any items in pxDelayedCoRoutineList here then there is an error! */
|
||||||
|
pxTemp = pxDelayedCoRoutineList;
|
||||||
|
pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList;
|
||||||
|
pxOverflowDelayedCoRoutineList = pxTemp;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* See if this tick has made a timeout expire. */
|
||||||
|
while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pd0 )
|
||||||
|
{
|
||||||
|
pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList );
|
||||||
|
|
||||||
|
if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) )
|
||||||
|
{
|
||||||
|
/* Timeout not yet expired. */
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
portDISABLE_INTERRUPTS();
|
||||||
|
{
|
||||||
|
/* The event could have occurred just before this critical
|
||||||
|
* section. If this is the case then the generic list item will
|
||||||
|
* have been moved to the pending ready list and the following
|
||||||
|
* line is still valid. Also the pvContainer parameter will have
|
||||||
|
* been set to NULL so the following lines are also valid. */
|
||||||
|
( void ) uxListRemove( &( pxCRCB->xGenericListItem ) );
|
||||||
|
|
||||||
|
/* Is the co-routine waiting on an event also? */
|
||||||
|
if( pxCRCB->xEventListItem.pxContainer )
|
||||||
|
{
|
||||||
|
( void ) uxListRemove( &( pxCRCB->xEventListItem ) );
|
||||||
|
}
|
||||||
|
}
|
||||||
|
portENABLE_INTERRUPTS();
|
||||||
|
|
||||||
|
prvAddCoRoutineToReadyQueue( pxCRCB );
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
xLastTickCount = xCoRoutineTickCount;
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
void vCoRoutineSchedule( void )
|
||||||
|
{
|
||||||
|
/* Only run a co-routine after prvInitialiseCoRoutineLists() has been
|
||||||
|
* called. prvInitialiseCoRoutineLists() is called automatically when a
|
||||||
|
* co-routine is created. */
|
||||||
|
if( pxDelayedCoRoutineList != NULL )
|
||||||
|
{
|
||||||
|
/* See if any co-routines readied by events need moving to the ready lists. */
|
||||||
|
prvCheckPendingReadyList();
|
||||||
|
|
||||||
|
/* See if any delayed co-routines have timed out. */
|
||||||
|
prvCheckDelayedList();
|
||||||
|
|
||||||
|
/* Find the highest priority queue that contains ready co-routines. */
|
||||||
|
while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) )
|
||||||
|
{
|
||||||
|
if( uxTopCoRoutineReadyPriority == 0 )
|
||||||
|
{
|
||||||
|
/* No more co-routines to check. */
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
--uxTopCoRoutineReadyPriority;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines
|
||||||
|
* of the same priority get an equal share of the processor time. */
|
||||||
|
listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) );
|
||||||
|
|
||||||
|
/* Call the co-routine. */
|
||||||
|
( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex );
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
static void prvInitialiseCoRoutineLists( void )
|
||||||
|
{
|
||||||
|
UBaseType_t uxPriority;
|
||||||
|
|
||||||
|
for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ )
|
||||||
|
{
|
||||||
|
vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) );
|
||||||
|
}
|
||||||
|
|
||||||
|
vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 );
|
||||||
|
vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 );
|
||||||
|
vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList );
|
||||||
|
|
||||||
|
/* Start with pxDelayedCoRoutineList using list1 and the
|
||||||
|
* pxOverflowDelayedCoRoutineList using list2. */
|
||||||
|
pxDelayedCoRoutineList = &xDelayedCoRoutineList1;
|
||||||
|
pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2;
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList )
|
||||||
|
{
|
||||||
|
CRCB_t * pxUnblockedCRCB;
|
||||||
|
BaseType_t xReturn;
|
||||||
|
|
||||||
|
/* This function is called from within an interrupt. It can only access
|
||||||
|
* event lists and the pending ready list. This function assumes that a
|
||||||
|
* check has already been made to ensure pxEventList is not empty. */
|
||||||
|
pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
|
||||||
|
( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
|
||||||
|
vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) );
|
||||||
|
|
||||||
|
if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority )
|
||||||
|
{
|
||||||
|
xReturn = pd1;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
xReturn = pd0;
|
||||||
|
}
|
||||||
|
|
||||||
|
return xReturn;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* configUSE_CO_ROUTINES == 0 */
|
||||||
777
FreeRTOS/event_groups.c
Normal file
777
FreeRTOS/event_groups.c
Normal file
@@ -0,0 +1,777 @@
|
|||||||
|
/*
|
||||||
|
* FreeRTOS Kernel V10.4.6
|
||||||
|
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: MIT
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* https://www.FreeRTOS.org
|
||||||
|
* https://github.com/FreeRTOS
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Standard includes. */
|
||||||
|
#include <stdlib.h>
|
||||||
|
|
||||||
|
/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
|
||||||
|
* all the API functions to use the MPU wrappers. That should only be done when
|
||||||
|
* task.h is included from an application file. */
|
||||||
|
#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
|
||||||
|
|
||||||
|
/* FreeRTOS includes. */
|
||||||
|
#include "FreeRTOS.h"
|
||||||
|
#include "task.h"
|
||||||
|
#include "timers.h"
|
||||||
|
#include "event_groups.h"
|
||||||
|
|
||||||
|
/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified
|
||||||
|
* because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
|
||||||
|
* for the header files above, but not in this file, in order to generate the
|
||||||
|
* correct privileged Vs unprivileged linkage and placement. */
|
||||||
|
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */
|
||||||
|
|
||||||
|
/* The following bit fields convey control information in a task's event list
|
||||||
|
* item value. It is important they don't clash with the
|
||||||
|
* taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */
|
||||||
|
#if configUSE_16_BIT_TICKS == 1
|
||||||
|
#define eventCLEAR_EVENTS_ON_EXIT_BIT 0x0100U
|
||||||
|
#define eventUNBLOCKED_DUE_TO_BIT_SET 0x0200U
|
||||||
|
#define eventWAIT_FOR_ALL_BITS 0x0400U
|
||||||
|
#define eventEVENT_BITS_CONTROL_BYTES 0xff00U
|
||||||
|
#else
|
||||||
|
#define eventCLEAR_EVENTS_ON_EXIT_BIT 0x01000000UL
|
||||||
|
#define eventUNBLOCKED_DUE_TO_BIT_SET 0x02000000UL
|
||||||
|
#define eventWAIT_FOR_ALL_BITS 0x04000000UL
|
||||||
|
#define eventEVENT_BITS_CONTROL_BYTES 0xff000000UL
|
||||||
|
#endif
|
||||||
|
|
||||||
|
typedef struct EventGroupDef_t
|
||||||
|
{
|
||||||
|
EventBits_t uxEventBits;
|
||||||
|
List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */
|
||||||
|
|
||||||
|
#if ( configUSE_TRACE_FACILITY == 1 )
|
||||||
|
UBaseType_t uxEventGroupNumber;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
|
||||||
|
uint8_t ucStaticallyAllocated; /*< Set to pd1 if the event group is statically allocated to ensure no attempt is made to free the memory. */
|
||||||
|
#endif
|
||||||
|
} EventGroup_t;
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Test the bits set in uxCurrentEventBits to see if the wait condition is met.
|
||||||
|
* The wait condition is defined by xWaitForAllBits. If xWaitForAllBits is
|
||||||
|
* pd1 then the wait condition is met if all the bits set in uxBitsToWaitFor
|
||||||
|
* are also set in uxCurrentEventBits. If xWaitForAllBits is pd0 then the
|
||||||
|
* wait condition is met if any of the bits set in uxBitsToWait for are also set
|
||||||
|
* in uxCurrentEventBits.
|
||||||
|
*/
|
||||||
|
static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
|
||||||
|
const EventBits_t uxBitsToWaitFor,
|
||||||
|
const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
|
||||||
|
|
||||||
|
EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer )
|
||||||
|
{
|
||||||
|
EventGroup_t * pxEventBits;
|
||||||
|
|
||||||
|
/* A StaticEventGroup_t object must be provided. */
|
||||||
|
configASSERT( pxEventGroupBuffer );
|
||||||
|
|
||||||
|
#if ( configASSERT_DEFINED == 1 )
|
||||||
|
{
|
||||||
|
/* Sanity check that the size of the structure used to declare a
|
||||||
|
* variable of type StaticEventGroup_t equals the size of the real
|
||||||
|
* event group structure. */
|
||||||
|
volatile size_t xSize = sizeof( StaticEventGroup_t );
|
||||||
|
configASSERT( xSize == sizeof( EventGroup_t ) );
|
||||||
|
} /*lint !e529 xSize is referenced if configASSERT() is defined. */
|
||||||
|
#endif /* configASSERT_DEFINED */
|
||||||
|
|
||||||
|
/* The user has provided a statically allocated event group - use it. */
|
||||||
|
pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */
|
||||||
|
|
||||||
|
if( pxEventBits != NULL )
|
||||||
|
{
|
||||||
|
pxEventBits->uxEventBits = 0;
|
||||||
|
vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
|
||||||
|
|
||||||
|
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
|
||||||
|
{
|
||||||
|
/* Both static and dynamic allocation can be used, so note that
|
||||||
|
* this event group was created statically in case the event group
|
||||||
|
* is later deleted. */
|
||||||
|
pxEventBits->ucStaticallyAllocated = pd1;
|
||||||
|
}
|
||||||
|
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
|
||||||
|
|
||||||
|
traceEVENT_GROUP_CREATE( pxEventBits );
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* xEventGroupCreateStatic should only ever be called with
|
||||||
|
* pxEventGroupBuffer pointing to a pre-allocated (compile time
|
||||||
|
* allocated) StaticEventGroup_t variable. */
|
||||||
|
traceEVENT_GROUP_CREATE_FAILED();
|
||||||
|
}
|
||||||
|
|
||||||
|
return pxEventBits;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* configSUPPORT_STATIC_ALLOCATION */
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
|
||||||
|
|
||||||
|
EventGroupHandle_t xEventGroupCreate( void )
|
||||||
|
{
|
||||||
|
EventGroup_t * pxEventBits;
|
||||||
|
|
||||||
|
/* Allocate the event group. Justification for MISRA deviation as
|
||||||
|
* follows: pvPortMalloc() always ensures returned memory blocks are
|
||||||
|
* aligned per the requirements of the MCU stack. In this case
|
||||||
|
* pvPortMalloc() must return a pointer that is guaranteed to meet the
|
||||||
|
* alignment requirements of the EventGroup_t structure - which (if you
|
||||||
|
* follow it through) is the alignment requirements of the TickType_t type
|
||||||
|
* (EventBits_t being of TickType_t itself). Therefore, whenever the
|
||||||
|
* stack alignment requirements are greater than or equal to the
|
||||||
|
* TickType_t alignment requirements the cast is safe. In other cases,
|
||||||
|
* where the natural word size of the architecture is less than
|
||||||
|
* sizeof( TickType_t ), the TickType_t variables will be accessed in two
|
||||||
|
* or more reads operations, and the alignment requirements is only that
|
||||||
|
* of each individual read. */
|
||||||
|
pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */
|
||||||
|
|
||||||
|
if( pxEventBits != NULL )
|
||||||
|
{
|
||||||
|
pxEventBits->uxEventBits = 0;
|
||||||
|
vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
|
||||||
|
|
||||||
|
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
|
||||||
|
{
|
||||||
|
/* Both static and dynamic allocation can be used, so note this
|
||||||
|
* event group was allocated statically in case the event group is
|
||||||
|
* later deleted. */
|
||||||
|
pxEventBits->ucStaticallyAllocated = pd0;
|
||||||
|
}
|
||||||
|
#endif /* configSUPPORT_STATIC_ALLOCATION */
|
||||||
|
|
||||||
|
traceEVENT_GROUP_CREATE( pxEventBits );
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */
|
||||||
|
}
|
||||||
|
|
||||||
|
return pxEventBits;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,
|
||||||
|
const EventBits_t uxBitsToSet,
|
||||||
|
const EventBits_t uxBitsToWaitFor,
|
||||||
|
TickType_t xTicksToWait )
|
||||||
|
{
|
||||||
|
EventBits_t uxOriginalBitValue, uxReturn;
|
||||||
|
EventGroup_t * pxEventBits = xEventGroup;
|
||||||
|
BaseType_t xAlreadyYielded;
|
||||||
|
BaseType_t xTimeoutOccurred = pd0;
|
||||||
|
|
||||||
|
configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
|
||||||
|
configASSERT( uxBitsToWaitFor != 0 );
|
||||||
|
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
||||||
|
{
|
||||||
|
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
vTaskSuspendAll();
|
||||||
|
{
|
||||||
|
uxOriginalBitValue = pxEventBits->uxEventBits;
|
||||||
|
|
||||||
|
( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet );
|
||||||
|
|
||||||
|
if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor )
|
||||||
|
{
|
||||||
|
/* All the rendezvous bits are now set - no need to block. */
|
||||||
|
uxReturn = ( uxOriginalBitValue | uxBitsToSet );
|
||||||
|
|
||||||
|
/* Rendezvous always clear the bits. They will have been cleared
|
||||||
|
* already unless this is the only task in the rendezvous. */
|
||||||
|
pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
|
||||||
|
|
||||||
|
xTicksToWait = 0;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if( xTicksToWait != ( TickType_t ) 0 )
|
||||||
|
{
|
||||||
|
traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor );
|
||||||
|
|
||||||
|
/* Store the bits that the calling task is waiting for in the
|
||||||
|
* task's event list item so the kernel knows when a match is
|
||||||
|
* found. Then enter the blocked state. */
|
||||||
|
vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait );
|
||||||
|
|
||||||
|
/* This assignment is obsolete as uxReturn will get set after
|
||||||
|
* the task unblocks, but some compilers mistakenly generate a
|
||||||
|
* warning about uxReturn being returned without being set if the
|
||||||
|
* assignment is omitted. */
|
||||||
|
uxReturn = 0;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* The rendezvous bits were not set, but no block time was
|
||||||
|
* specified - just return the current event bit value. */
|
||||||
|
uxReturn = pxEventBits->uxEventBits;
|
||||||
|
xTimeoutOccurred = pd1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
xAlreadyYielded = xTaskResumeAll();
|
||||||
|
|
||||||
|
if( xTicksToWait != ( TickType_t ) 0 )
|
||||||
|
{
|
||||||
|
if( xAlreadyYielded == pd0 )
|
||||||
|
{
|
||||||
|
portYIELD_WITHIN_API();
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
mtCOVERAGE_TEST_MARKER();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* The task blocked to wait for its required bits to be set - at this
|
||||||
|
* point either the required bits were set or the block time expired. If
|
||||||
|
* the required bits were set they will have been stored in the task's
|
||||||
|
* event list item, and they should now be retrieved then cleared. */
|
||||||
|
uxReturn = uxTaskResetEventItemValue();
|
||||||
|
|
||||||
|
if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
|
||||||
|
{
|
||||||
|
/* The task timed out, just return the current event bit value. */
|
||||||
|
taskENTER_CRITICAL();
|
||||||
|
{
|
||||||
|
uxReturn = pxEventBits->uxEventBits;
|
||||||
|
|
||||||
|
/* Although the task got here because it timed out before the
|
||||||
|
* bits it was waiting for were set, it is possible that since it
|
||||||
|
* unblocked another task has set the bits. If this is the case
|
||||||
|
* then it needs to clear the bits before exiting. */
|
||||||
|
if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor )
|
||||||
|
{
|
||||||
|
pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
mtCOVERAGE_TEST_MARKER();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
taskEXIT_CRITICAL();
|
||||||
|
|
||||||
|
xTimeoutOccurred = pd1;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* The task unblocked because the bits were set. */
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Control bits might be set as the task had blocked should not be
|
||||||
|
* returned. */
|
||||||
|
uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
|
||||||
|
}
|
||||||
|
|
||||||
|
traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred );
|
||||||
|
|
||||||
|
/* Prevent compiler warnings when trace macros are not used. */
|
||||||
|
( void ) xTimeoutOccurred;
|
||||||
|
|
||||||
|
return uxReturn;
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
|
||||||
|
const EventBits_t uxBitsToWaitFor,
|
||||||
|
const BaseType_t xClearOnExit,
|
||||||
|
const BaseType_t xWaitForAllBits,
|
||||||
|
TickType_t xTicksToWait )
|
||||||
|
{
|
||||||
|
EventGroup_t * pxEventBits = xEventGroup;
|
||||||
|
EventBits_t uxReturn, uxControlBits = 0;
|
||||||
|
BaseType_t xWaitConditionMet, xAlreadyYielded;
|
||||||
|
BaseType_t xTimeoutOccurred = pd0;
|
||||||
|
|
||||||
|
/* Check the user is not attempting to wait on the bits used by the kernel
|
||||||
|
* itself, and that at least one bit is being requested. */
|
||||||
|
configASSERT( xEventGroup );
|
||||||
|
configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
|
||||||
|
configASSERT( uxBitsToWaitFor != 0 );
|
||||||
|
#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
|
||||||
|
{
|
||||||
|
configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
vTaskSuspendAll();
|
||||||
|
{
|
||||||
|
const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits;
|
||||||
|
|
||||||
|
/* Check to see if the wait condition is already met or not. */
|
||||||
|
xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits );
|
||||||
|
|
||||||
|
if( xWaitConditionMet != pd0 )
|
||||||
|
{
|
||||||
|
/* The wait condition has already been met so there is no need to
|
||||||
|
* block. */
|
||||||
|
uxReturn = uxCurrentEventBits;
|
||||||
|
xTicksToWait = ( TickType_t ) 0;
|
||||||
|
|
||||||
|
/* Clear the wait bits if requested to do so. */
|
||||||
|
if( xClearOnExit != pd0 )
|
||||||
|
{
|
||||||
|
pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
mtCOVERAGE_TEST_MARKER();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else if( xTicksToWait == ( TickType_t ) 0 )
|
||||||
|
{
|
||||||
|
/* The wait condition has not been met, but no block time was
|
||||||
|
* specified, so just return the current value. */
|
||||||
|
uxReturn = uxCurrentEventBits;
|
||||||
|
xTimeoutOccurred = pd1;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* The task is going to block to wait for its required bits to be
|
||||||
|
* set. uxControlBits are used to remember the specified behaviour of
|
||||||
|
* this call to xEventGroupWaitBits() - for use when the event bits
|
||||||
|
* unblock the task. */
|
||||||
|
if( xClearOnExit != pd0 )
|
||||||
|
{
|
||||||
|
uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
mtCOVERAGE_TEST_MARKER();
|
||||||
|
}
|
||||||
|
|
||||||
|
if( xWaitForAllBits != pd0 )
|
||||||
|
{
|
||||||
|
uxControlBits |= eventWAIT_FOR_ALL_BITS;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
mtCOVERAGE_TEST_MARKER();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Store the bits that the calling task is waiting for in the
|
||||||
|
* task's event list item so the kernel knows when a match is
|
||||||
|
* found. Then enter the blocked state. */
|
||||||
|
vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait );
|
||||||
|
|
||||||
|
/* This is obsolete as it will get set after the task unblocks, but
|
||||||
|
* some compilers mistakenly generate a warning about the variable
|
||||||
|
* being returned without being set if it is not done. */
|
||||||
|
uxReturn = 0;
|
||||||
|
|
||||||
|
traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor );
|
||||||
|
}
|
||||||
|
}
|
||||||
|
xAlreadyYielded = xTaskResumeAll();
|
||||||
|
|
||||||
|
if( xTicksToWait != ( TickType_t ) 0 )
|
||||||
|
{
|
||||||
|
if( xAlreadyYielded == pd0 )
|
||||||
|
{
|
||||||
|
portYIELD_WITHIN_API();
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
mtCOVERAGE_TEST_MARKER();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* The task blocked to wait for its required bits to be set - at this
|
||||||
|
* point either the required bits were set or the block time expired. If
|
||||||
|
* the required bits were set they will have been stored in the task's
|
||||||
|
* event list item, and they should now be retrieved then cleared. */
|
||||||
|
uxReturn = uxTaskResetEventItemValue();
|
||||||
|
|
||||||
|
if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
|
||||||
|
{
|
||||||
|
taskENTER_CRITICAL();
|
||||||
|
{
|
||||||
|
/* The task timed out, just return the current event bit value. */
|
||||||
|
uxReturn = pxEventBits->uxEventBits;
|
||||||
|
|
||||||
|
/* It is possible that the event bits were updated between this
|
||||||
|
* task leaving the Blocked state and running again. */
|
||||||
|
if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pd0 )
|
||||||
|
{
|
||||||
|
if( xClearOnExit != pd0 )
|
||||||
|
{
|
||||||
|
pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
mtCOVERAGE_TEST_MARKER();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
mtCOVERAGE_TEST_MARKER();
|
||||||
|
}
|
||||||
|
|
||||||
|
xTimeoutOccurred = pd1;
|
||||||
|
}
|
||||||
|
taskEXIT_CRITICAL();
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* The task unblocked because the bits were set. */
|
||||||
|
}
|
||||||
|
|
||||||
|
/* The task blocked so control bits may have been set. */
|
||||||
|
uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
|
||||||
|
}
|
||||||
|
|
||||||
|
traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred );
|
||||||
|
|
||||||
|
/* Prevent compiler warnings when trace macros are not used. */
|
||||||
|
( void ) xTimeoutOccurred;
|
||||||
|
|
||||||
|
return uxReturn;
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup,
|
||||||
|
const EventBits_t uxBitsToClear )
|
||||||
|
{
|
||||||
|
EventGroup_t * pxEventBits = xEventGroup;
|
||||||
|
EventBits_t uxReturn;
|
||||||
|
|
||||||
|
/* Check the user is not attempting to clear the bits used by the kernel
|
||||||
|
* itself. */
|
||||||
|
configASSERT( xEventGroup );
|
||||||
|
configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
|
||||||
|
|
||||||
|
taskENTER_CRITICAL();
|
||||||
|
{
|
||||||
|
traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear );
|
||||||
|
|
||||||
|
/* The value returned is the event group value prior to the bits being
|
||||||
|
* cleared. */
|
||||||
|
uxReturn = pxEventBits->uxEventBits;
|
||||||
|
|
||||||
|
/* Clear the bits. */
|
||||||
|
pxEventBits->uxEventBits &= ~uxBitsToClear;
|
||||||
|
}
|
||||||
|
taskEXIT_CRITICAL();
|
||||||
|
|
||||||
|
return uxReturn;
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
|
||||||
|
|
||||||
|
BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
|
||||||
|
const EventBits_t uxBitsToClear )
|
||||||
|
{
|
||||||
|
BaseType_t xReturn;
|
||||||
|
|
||||||
|
traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );
|
||||||
|
xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */
|
||||||
|
|
||||||
|
return xReturn;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )
|
||||||
|
{
|
||||||
|
UBaseType_t uxSavedInterruptStatus;
|
||||||
|
EventGroup_t const * const pxEventBits = xEventGroup;
|
||||||
|
EventBits_t uxReturn;
|
||||||
|
|
||||||
|
uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
|
||||||
|
{
|
||||||
|
uxReturn = pxEventBits->uxEventBits;
|
||||||
|
}
|
||||||
|
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
|
||||||
|
|
||||||
|
return uxReturn;
|
||||||
|
} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup,
|
||||||
|
const EventBits_t uxBitsToSet )
|
||||||
|
{
|
||||||
|
ListItem_t * pxListItem, * pxNext;
|
||||||
|
ListItem_t const * pxListEnd;
|
||||||
|
List_t const * pxList;
|
||||||
|
EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits;
|
||||||
|
EventGroup_t * pxEventBits = xEventGroup;
|
||||||
|
BaseType_t xMatchFound = pd0;
|
||||||
|
|
||||||
|
/* Check the user is not attempting to set the bits used by the kernel
|
||||||
|
* itself. */
|
||||||
|
configASSERT( xEventGroup );
|
||||||
|
configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
|
||||||
|
|
||||||
|
pxList = &( pxEventBits->xTasksWaitingForBits );
|
||||||
|
pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
|
||||||
|
vTaskSuspendAll();
|
||||||
|
{
|
||||||
|
traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet );
|
||||||
|
|
||||||
|
pxListItem = listGET_HEAD_ENTRY( pxList );
|
||||||
|
|
||||||
|
/* Set the bits. */
|
||||||
|
pxEventBits->uxEventBits |= uxBitsToSet;
|
||||||
|
|
||||||
|
/* See if the new bit value should unblock any tasks. */
|
||||||
|
while( pxListItem != pxListEnd )
|
||||||
|
{
|
||||||
|
pxNext = listGET_NEXT( pxListItem );
|
||||||
|
uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem );
|
||||||
|
xMatchFound = pd0;
|
||||||
|
|
||||||
|
/* Split the bits waited for from the control bits. */
|
||||||
|
uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES;
|
||||||
|
uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES;
|
||||||
|
|
||||||
|
if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 )
|
||||||
|
{
|
||||||
|
/* Just looking for single bit being set. */
|
||||||
|
if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 )
|
||||||
|
{
|
||||||
|
xMatchFound = pd1;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
mtCOVERAGE_TEST_MARKER();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor )
|
||||||
|
{
|
||||||
|
/* All bits are set. */
|
||||||
|
xMatchFound = pd1;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Need all bits to be set, but not all the bits were set. */
|
||||||
|
}
|
||||||
|
|
||||||
|
if( xMatchFound != pd0 )
|
||||||
|
{
|
||||||
|
/* The bits match. Should the bits be cleared on exit? */
|
||||||
|
if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 )
|
||||||
|
{
|
||||||
|
uxBitsToClear |= uxBitsWaitedFor;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
mtCOVERAGE_TEST_MARKER();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Store the actual event flag value in the task's event list
|
||||||
|
* item before removing the task from the event list. The
|
||||||
|
* eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows
|
||||||
|
* that is was unblocked due to its required bits matching, rather
|
||||||
|
* than because it timed out. */
|
||||||
|
vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET );
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Move onto the next list item. Note pxListItem->pxNext is not
|
||||||
|
* used here as the list item may have been removed from the event list
|
||||||
|
* and inserted into the ready/pending reading list. */
|
||||||
|
pxListItem = pxNext;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT
|
||||||
|
* bit was set in the control word. */
|
||||||
|
pxEventBits->uxEventBits &= ~uxBitsToClear;
|
||||||
|
}
|
||||||
|
( void ) xTaskResumeAll();
|
||||||
|
|
||||||
|
return pxEventBits->uxEventBits;
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
void vEventGroupDelete( EventGroupHandle_t xEventGroup )
|
||||||
|
{
|
||||||
|
EventGroup_t * pxEventBits = xEventGroup;
|
||||||
|
const List_t * pxTasksWaitingForBits;
|
||||||
|
|
||||||
|
configASSERT( pxEventBits );
|
||||||
|
|
||||||
|
pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );
|
||||||
|
|
||||||
|
vTaskSuspendAll();
|
||||||
|
{
|
||||||
|
traceEVENT_GROUP_DELETE( xEventGroup );
|
||||||
|
|
||||||
|
while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 )
|
||||||
|
{
|
||||||
|
/* Unblock the task, returning 0 as the event list is being deleted
|
||||||
|
* and cannot therefore have any bits set. */
|
||||||
|
configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) );
|
||||||
|
vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET );
|
||||||
|
}
|
||||||
|
|
||||||
|
#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
|
||||||
|
{
|
||||||
|
/* The event group can only have been allocated dynamically - free
|
||||||
|
* it again. */
|
||||||
|
vPortFree( pxEventBits );
|
||||||
|
}
|
||||||
|
#elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
|
||||||
|
{
|
||||||
|
/* The event group could have been allocated statically or
|
||||||
|
* dynamically, so check before attempting to free the memory. */
|
||||||
|
if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pd0 )
|
||||||
|
{
|
||||||
|
vPortFree( pxEventBits );
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
mtCOVERAGE_TEST_MARKER();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
|
||||||
|
}
|
||||||
|
( void ) xTaskResumeAll();
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* For internal use only - execute a 'set bits' command that was pended from
|
||||||
|
* an interrupt. */
|
||||||
|
void vEventGroupSetBitsCallback( void * pvEventGroup,
|
||||||
|
const uint32_t ulBitsToSet )
|
||||||
|
{
|
||||||
|
( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* For internal use only - execute a 'clear bits' command that was pended from
|
||||||
|
* an interrupt. */
|
||||||
|
void vEventGroupClearBitsCallback( void * pvEventGroup,
|
||||||
|
const uint32_t ulBitsToClear )
|
||||||
|
{
|
||||||
|
( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
|
||||||
|
const EventBits_t uxBitsToWaitFor,
|
||||||
|
const BaseType_t xWaitForAllBits )
|
||||||
|
{
|
||||||
|
BaseType_t xWaitConditionMet = pd0;
|
||||||
|
|
||||||
|
if( xWaitForAllBits == pd0 )
|
||||||
|
{
|
||||||
|
/* Task only has to wait for one bit within uxBitsToWaitFor to be
|
||||||
|
* set. Is one already set? */
|
||||||
|
if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 )
|
||||||
|
{
|
||||||
|
xWaitConditionMet = pd1;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
mtCOVERAGE_TEST_MARKER();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Task has to wait for all the bits in uxBitsToWaitFor to be set.
|
||||||
|
* Are they set already? */
|
||||||
|
if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor )
|
||||||
|
{
|
||||||
|
xWaitConditionMet = pd1;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
mtCOVERAGE_TEST_MARKER();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return xWaitConditionMet;
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
|
||||||
|
|
||||||
|
BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
|
||||||
|
const EventBits_t uxBitsToSet,
|
||||||
|
BaseType_t * pxHigherPriorityTaskWoken )
|
||||||
|
{
|
||||||
|
BaseType_t xReturn;
|
||||||
|
|
||||||
|
traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );
|
||||||
|
xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */
|
||||||
|
|
||||||
|
return xReturn;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
#if ( configUSE_TRACE_FACILITY == 1 )
|
||||||
|
|
||||||
|
UBaseType_t uxEventGroupGetNumber( void * xEventGroup )
|
||||||
|
{
|
||||||
|
UBaseType_t xReturn;
|
||||||
|
EventGroup_t const * pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */
|
||||||
|
|
||||||
|
if( xEventGroup == NULL )
|
||||||
|
{
|
||||||
|
xReturn = 0;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
xReturn = pxEventBits->uxEventGroupNumber;
|
||||||
|
}
|
||||||
|
|
||||||
|
return xReturn;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* configUSE_TRACE_FACILITY */
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
#if ( configUSE_TRACE_FACILITY == 1 )
|
||||||
|
|
||||||
|
void vEventGroupSetNumber( void * xEventGroup,
|
||||||
|
UBaseType_t uxEventGroupNumber )
|
||||||
|
{
|
||||||
|
( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* configUSE_TRACE_FACILITY */
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
1362
FreeRTOS/include/FreeRTOS.h
Normal file
1362
FreeRTOS/include/FreeRTOS.h
Normal file
File diff suppressed because it is too large
Load Diff
34
FreeRTOS/include/StackMacros.h
Normal file
34
FreeRTOS/include/StackMacros.h
Normal file
@@ -0,0 +1,34 @@
|
|||||||
|
/*
|
||||||
|
* FreeRTOS Kernel V10.4.6
|
||||||
|
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: MIT
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* https://www.FreeRTOS.org
|
||||||
|
* https://github.com/FreeRTOS
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */
|
||||||
|
#warning The name of this file has changed to stack_macros.h. Please update your code accordingly. This source file (which has the original name) will be removed in future released.
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "stack_macros.h"
|
||||||
419
FreeRTOS/include/atomic.h
Normal file
419
FreeRTOS/include/atomic.h
Normal file
@@ -0,0 +1,419 @@
|
|||||||
|
/*
|
||||||
|
* FreeRTOS Kernel V10.4.6
|
||||||
|
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: MIT
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* https://www.FreeRTOS.org
|
||||||
|
* https://github.com/FreeRTOS
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @file atomic.h
|
||||||
|
* @brief FreeRTOS atomic operation support.
|
||||||
|
*
|
||||||
|
* This file implements atomic functions by disabling interrupts globally.
|
||||||
|
* Implementations with architecture specific atomic instructions can be
|
||||||
|
* provided under each compiler directory.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef ATOMIC_H
|
||||||
|
#define ATOMIC_H
|
||||||
|
|
||||||
|
#ifndef INC_FREERTOS_H
|
||||||
|
#error "include FreeRTOS.h must appear in source files before include atomic.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Standard includes. */
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
/* *INDENT-OFF* */
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
/* *INDENT-ON* */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Port specific definitions -- entering/exiting critical section.
|
||||||
|
* Refer template -- ./lib/FreeRTOS/portable/Compiler/Arch/portmacro.h
|
||||||
|
*
|
||||||
|
* Every call to ATOMIC_EXIT_CRITICAL() must be closely paired with
|
||||||
|
* ATOMIC_ENTER_CRITICAL().
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#if defined( portSET_INTERRUPT_MASK_FROM_ISR )
|
||||||
|
|
||||||
|
/* Nested interrupt scheme is supported in this port. */
|
||||||
|
#define ATOMIC_ENTER_CRITICAL() \
|
||||||
|
UBaseType_t uxCriticalSectionType = portSET_INTERRUPT_MASK_FROM_ISR()
|
||||||
|
|
||||||
|
#define ATOMIC_EXIT_CRITICAL() \
|
||||||
|
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxCriticalSectionType )
|
||||||
|
|
||||||
|
#else
|
||||||
|
|
||||||
|
/* Nested interrupt scheme is NOT supported in this port. */
|
||||||
|
#define ATOMIC_ENTER_CRITICAL() portENTER_CRITICAL()
|
||||||
|
#define ATOMIC_EXIT_CRITICAL() portEXIT_CRITICAL()
|
||||||
|
|
||||||
|
#endif /* portSET_INTERRUPT_MASK_FROM_ISR() */
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Port specific definition -- "always inline".
|
||||||
|
* Inline is compiler specific, and may not always get inlined depending on your
|
||||||
|
* optimization level. Also, inline is considered as performance optimization
|
||||||
|
* for atomic. Thus, if portFORCE_INLINE is not provided by portmacro.h,
|
||||||
|
* instead of resulting error, simply define it away.
|
||||||
|
*/
|
||||||
|
#ifndef portFORCE_INLINE
|
||||||
|
#define portFORCE_INLINE
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define ATOMIC_COMPARE_AND_SWAP_SUCCESS 0x1U /**< Compare and swap succeeded, swapped. */
|
||||||
|
#define ATOMIC_COMPARE_AND_SWAP_FAILURE 0x0U /**< Compare and swap failed, did not swap. */
|
||||||
|
|
||||||
|
/*----------------------------- Swap && CAS ------------------------------*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Atomic compare-and-swap
|
||||||
|
*
|
||||||
|
* @brief Performs an atomic compare-and-swap operation on the specified values.
|
||||||
|
*
|
||||||
|
* @param[in, out] pulDestination Pointer to memory location from where value is
|
||||||
|
* to be loaded and checked.
|
||||||
|
* @param[in] ulExchange If condition meets, write this value to memory.
|
||||||
|
* @param[in] ulComparand Swap condition.
|
||||||
|
*
|
||||||
|
* @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped.
|
||||||
|
*
|
||||||
|
* @note This function only swaps *pulDestination with ulExchange, if previous
|
||||||
|
* *pulDestination value equals ulComparand.
|
||||||
|
*/
|
||||||
|
static portFORCE_INLINE uint32_t Atomic_CompareAndSwap_u32( uint32_t volatile * pulDestination,
|
||||||
|
uint32_t ulExchange,
|
||||||
|
uint32_t ulComparand )
|
||||||
|
{
|
||||||
|
uint32_t ulReturnValue;
|
||||||
|
|
||||||
|
ATOMIC_ENTER_CRITICAL();
|
||||||
|
{
|
||||||
|
if( *pulDestination == ulComparand )
|
||||||
|
{
|
||||||
|
*pulDestination = ulExchange;
|
||||||
|
ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
ATOMIC_EXIT_CRITICAL();
|
||||||
|
|
||||||
|
return ulReturnValue;
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Atomic swap (pointers)
|
||||||
|
*
|
||||||
|
* @brief Atomically sets the address pointed to by *ppvDestination to the value
|
||||||
|
* of *pvExchange.
|
||||||
|
*
|
||||||
|
* @param[in, out] ppvDestination Pointer to memory location from where a pointer
|
||||||
|
* value is to be loaded and written back to.
|
||||||
|
* @param[in] pvExchange Pointer value to be written to *ppvDestination.
|
||||||
|
*
|
||||||
|
* @return The initial value of *ppvDestination.
|
||||||
|
*/
|
||||||
|
static portFORCE_INLINE void * Atomic_SwapPointers_p32( void * volatile * ppvDestination,
|
||||||
|
void * pvExchange )
|
||||||
|
{
|
||||||
|
void * pReturnValue;
|
||||||
|
|
||||||
|
ATOMIC_ENTER_CRITICAL();
|
||||||
|
{
|
||||||
|
pReturnValue = *ppvDestination;
|
||||||
|
*ppvDestination = pvExchange;
|
||||||
|
}
|
||||||
|
ATOMIC_EXIT_CRITICAL();
|
||||||
|
|
||||||
|
return pReturnValue;
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Atomic compare-and-swap (pointers)
|
||||||
|
*
|
||||||
|
* @brief Performs an atomic compare-and-swap operation on the specified pointer
|
||||||
|
* values.
|
||||||
|
*
|
||||||
|
* @param[in, out] ppvDestination Pointer to memory location from where a pointer
|
||||||
|
* value is to be loaded and checked.
|
||||||
|
* @param[in] pvExchange If condition meets, write this value to memory.
|
||||||
|
* @param[in] pvComparand Swap condition.
|
||||||
|
*
|
||||||
|
* @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped.
|
||||||
|
*
|
||||||
|
* @note This function only swaps *ppvDestination with pvExchange, if previous
|
||||||
|
* *ppvDestination value equals pvComparand.
|
||||||
|
*/
|
||||||
|
static portFORCE_INLINE uint32_t Atomic_CompareAndSwapPointers_p32( void * volatile * ppvDestination,
|
||||||
|
void * pvExchange,
|
||||||
|
void * pvComparand )
|
||||||
|
{
|
||||||
|
uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;
|
||||||
|
|
||||||
|
ATOMIC_ENTER_CRITICAL();
|
||||||
|
{
|
||||||
|
if( *ppvDestination == pvComparand )
|
||||||
|
{
|
||||||
|
*ppvDestination = pvExchange;
|
||||||
|
ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
ATOMIC_EXIT_CRITICAL();
|
||||||
|
|
||||||
|
return ulReturnValue;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*----------------------------- Arithmetic ------------------------------*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Atomic add
|
||||||
|
*
|
||||||
|
* @brief Atomically adds count to the value of the specified pointer points to.
|
||||||
|
*
|
||||||
|
* @param[in,out] pulAddend Pointer to memory location from where value is to be
|
||||||
|
* loaded and written back to.
|
||||||
|
* @param[in] ulCount Value to be added to *pulAddend.
|
||||||
|
*
|
||||||
|
* @return previous *pulAddend value.
|
||||||
|
*/
|
||||||
|
static portFORCE_INLINE uint32_t Atomic_Add_u32( uint32_t volatile * pulAddend,
|
||||||
|
uint32_t ulCount )
|
||||||
|
{
|
||||||
|
uint32_t ulCurrent;
|
||||||
|
|
||||||
|
ATOMIC_ENTER_CRITICAL();
|
||||||
|
{
|
||||||
|
ulCurrent = *pulAddend;
|
||||||
|
*pulAddend += ulCount;
|
||||||
|
}
|
||||||
|
ATOMIC_EXIT_CRITICAL();
|
||||||
|
|
||||||
|
return ulCurrent;
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Atomic subtract
|
||||||
|
*
|
||||||
|
* @brief Atomically subtracts count from the value of the specified pointer
|
||||||
|
* pointers to.
|
||||||
|
*
|
||||||
|
* @param[in,out] pulAddend Pointer to memory location from where value is to be
|
||||||
|
* loaded and written back to.
|
||||||
|
* @param[in] ulCount Value to be subtract from *pulAddend.
|
||||||
|
*
|
||||||
|
* @return previous *pulAddend value.
|
||||||
|
*/
|
||||||
|
static portFORCE_INLINE uint32_t Atomic_Subtract_u32( uint32_t volatile * pulAddend,
|
||||||
|
uint32_t ulCount )
|
||||||
|
{
|
||||||
|
uint32_t ulCurrent;
|
||||||
|
|
||||||
|
ATOMIC_ENTER_CRITICAL();
|
||||||
|
{
|
||||||
|
ulCurrent = *pulAddend;
|
||||||
|
*pulAddend -= ulCount;
|
||||||
|
}
|
||||||
|
ATOMIC_EXIT_CRITICAL();
|
||||||
|
|
||||||
|
return ulCurrent;
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Atomic increment
|
||||||
|
*
|
||||||
|
* @brief Atomically increments the value of the specified pointer points to.
|
||||||
|
*
|
||||||
|
* @param[in,out] pulAddend Pointer to memory location from where value is to be
|
||||||
|
* loaded and written back to.
|
||||||
|
*
|
||||||
|
* @return *pulAddend value before increment.
|
||||||
|
*/
|
||||||
|
static portFORCE_INLINE uint32_t Atomic_Increment_u32( uint32_t volatile * pulAddend )
|
||||||
|
{
|
||||||
|
uint32_t ulCurrent;
|
||||||
|
|
||||||
|
ATOMIC_ENTER_CRITICAL();
|
||||||
|
{
|
||||||
|
ulCurrent = *pulAddend;
|
||||||
|
*pulAddend += 1;
|
||||||
|
}
|
||||||
|
ATOMIC_EXIT_CRITICAL();
|
||||||
|
|
||||||
|
return ulCurrent;
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Atomic decrement
|
||||||
|
*
|
||||||
|
* @brief Atomically decrements the value of the specified pointer points to
|
||||||
|
*
|
||||||
|
* @param[in,out] pulAddend Pointer to memory location from where value is to be
|
||||||
|
* loaded and written back to.
|
||||||
|
*
|
||||||
|
* @return *pulAddend value before decrement.
|
||||||
|
*/
|
||||||
|
static portFORCE_INLINE uint32_t Atomic_Decrement_u32( uint32_t volatile * pulAddend )
|
||||||
|
{
|
||||||
|
uint32_t ulCurrent;
|
||||||
|
|
||||||
|
ATOMIC_ENTER_CRITICAL();
|
||||||
|
{
|
||||||
|
ulCurrent = *pulAddend;
|
||||||
|
*pulAddend -= 1;
|
||||||
|
}
|
||||||
|
ATOMIC_EXIT_CRITICAL();
|
||||||
|
|
||||||
|
return ulCurrent;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*----------------------------- Bitwise Logical ------------------------------*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Atomic OR
|
||||||
|
*
|
||||||
|
* @brief Performs an atomic OR operation on the specified values.
|
||||||
|
*
|
||||||
|
* @param [in, out] pulDestination Pointer to memory location from where value is
|
||||||
|
* to be loaded and written back to.
|
||||||
|
* @param [in] ulValue Value to be ORed with *pulDestination.
|
||||||
|
*
|
||||||
|
* @return The original value of *pulDestination.
|
||||||
|
*/
|
||||||
|
static portFORCE_INLINE uint32_t Atomic_OR_u32( uint32_t volatile * pulDestination,
|
||||||
|
uint32_t ulValue )
|
||||||
|
{
|
||||||
|
uint32_t ulCurrent;
|
||||||
|
|
||||||
|
ATOMIC_ENTER_CRITICAL();
|
||||||
|
{
|
||||||
|
ulCurrent = *pulDestination;
|
||||||
|
*pulDestination |= ulValue;
|
||||||
|
}
|
||||||
|
ATOMIC_EXIT_CRITICAL();
|
||||||
|
|
||||||
|
return ulCurrent;
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Atomic AND
|
||||||
|
*
|
||||||
|
* @brief Performs an atomic AND operation on the specified values.
|
||||||
|
*
|
||||||
|
* @param [in, out] pulDestination Pointer to memory location from where value is
|
||||||
|
* to be loaded and written back to.
|
||||||
|
* @param [in] ulValue Value to be ANDed with *pulDestination.
|
||||||
|
*
|
||||||
|
* @return The original value of *pulDestination.
|
||||||
|
*/
|
||||||
|
static portFORCE_INLINE uint32_t Atomic_AND_u32( uint32_t volatile * pulDestination,
|
||||||
|
uint32_t ulValue )
|
||||||
|
{
|
||||||
|
uint32_t ulCurrent;
|
||||||
|
|
||||||
|
ATOMIC_ENTER_CRITICAL();
|
||||||
|
{
|
||||||
|
ulCurrent = *pulDestination;
|
||||||
|
*pulDestination &= ulValue;
|
||||||
|
}
|
||||||
|
ATOMIC_EXIT_CRITICAL();
|
||||||
|
|
||||||
|
return ulCurrent;
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Atomic NAND
|
||||||
|
*
|
||||||
|
* @brief Performs an atomic NAND operation on the specified values.
|
||||||
|
*
|
||||||
|
* @param [in, out] pulDestination Pointer to memory location from where value is
|
||||||
|
* to be loaded and written back to.
|
||||||
|
* @param [in] ulValue Value to be NANDed with *pulDestination.
|
||||||
|
*
|
||||||
|
* @return The original value of *pulDestination.
|
||||||
|
*/
|
||||||
|
static portFORCE_INLINE uint32_t Atomic_NAND_u32( uint32_t volatile * pulDestination,
|
||||||
|
uint32_t ulValue )
|
||||||
|
{
|
||||||
|
uint32_t ulCurrent;
|
||||||
|
|
||||||
|
ATOMIC_ENTER_CRITICAL();
|
||||||
|
{
|
||||||
|
ulCurrent = *pulDestination;
|
||||||
|
*pulDestination = ~( ulCurrent & ulValue );
|
||||||
|
}
|
||||||
|
ATOMIC_EXIT_CRITICAL();
|
||||||
|
|
||||||
|
return ulCurrent;
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Atomic XOR
|
||||||
|
*
|
||||||
|
* @brief Performs an atomic XOR operation on the specified values.
|
||||||
|
*
|
||||||
|
* @param [in, out] pulDestination Pointer to memory location from where value is
|
||||||
|
* to be loaded and written back to.
|
||||||
|
* @param [in] ulValue Value to be XORed with *pulDestination.
|
||||||
|
*
|
||||||
|
* @return The original value of *pulDestination.
|
||||||
|
*/
|
||||||
|
static portFORCE_INLINE uint32_t Atomic_XOR_u32( uint32_t volatile * pulDestination,
|
||||||
|
uint32_t ulValue )
|
||||||
|
{
|
||||||
|
uint32_t ulCurrent;
|
||||||
|
|
||||||
|
ATOMIC_ENTER_CRITICAL();
|
||||||
|
{
|
||||||
|
ulCurrent = *pulDestination;
|
||||||
|
*pulDestination ^= ulValue;
|
||||||
|
}
|
||||||
|
ATOMIC_EXIT_CRITICAL();
|
||||||
|
|
||||||
|
return ulCurrent;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* *INDENT-OFF* */
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
/* *INDENT-ON* */
|
||||||
|
|
||||||
|
#endif /* ATOMIC_H */
|
||||||
753
FreeRTOS/include/croutine.h
Normal file
753
FreeRTOS/include/croutine.h
Normal file
@@ -0,0 +1,753 @@
|
|||||||
|
/*
|
||||||
|
* FreeRTOS Kernel V10.4.6
|
||||||
|
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: MIT
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* https://www.FreeRTOS.org
|
||||||
|
* https://github.com/FreeRTOS
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef CO_ROUTINE_H
|
||||||
|
#define CO_ROUTINE_H
|
||||||
|
|
||||||
|
#ifndef INC_FREERTOS_H
|
||||||
|
#error "include FreeRTOS.h must appear in source files before include croutine.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "list.h"
|
||||||
|
|
||||||
|
/* *INDENT-OFF* */
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
/* *INDENT-ON* */
|
||||||
|
|
||||||
|
/* Used to hide the implementation of the co-routine control block. The
|
||||||
|
* control block structure however has to be included in the header due to
|
||||||
|
* the macro implementation of the co-routine functionality. */
|
||||||
|
typedef void * CoRoutineHandle_t;
|
||||||
|
|
||||||
|
/* Defines the prototype to which co-routine functions must conform. */
|
||||||
|
typedef void (* crCOROUTINE_CODE)( CoRoutineHandle_t,
|
||||||
|
UBaseType_t );
|
||||||
|
|
||||||
|
typedef struct corCoRoutineControlBlock
|
||||||
|
{
|
||||||
|
crCOROUTINE_CODE pxCoRoutineFunction;
|
||||||
|
ListItem_t xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */
|
||||||
|
ListItem_t xEventListItem; /*< List item used to place the CRCB in event lists. */
|
||||||
|
UBaseType_t uxPriority; /*< The priority of the co-routine in relation to other co-routines. */
|
||||||
|
UBaseType_t uxIndex; /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */
|
||||||
|
uint16_t uxState; /*< Used internally by the co-routine implementation. */
|
||||||
|
} CRCB_t; /* Co-routine control block. Note must be identical in size down to uxPriority with TCB_t. */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* croutine. h
|
||||||
|
* @code{c}
|
||||||
|
* BaseType_t xCoRoutineCreate(
|
||||||
|
* crCOROUTINE_CODE pxCoRoutineCode,
|
||||||
|
* UBaseType_t uxPriority,
|
||||||
|
* UBaseType_t uxIndex
|
||||||
|
* );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Create a new co-routine and add it to the list of co-routines that are
|
||||||
|
* ready to run.
|
||||||
|
*
|
||||||
|
* @param pxCoRoutineCode Pointer to the co-routine function. Co-routine
|
||||||
|
* functions require special syntax - see the co-routine section of the WEB
|
||||||
|
* documentation for more information.
|
||||||
|
*
|
||||||
|
* @param uxPriority The priority with respect to other co-routines at which
|
||||||
|
* the co-routine will run.
|
||||||
|
*
|
||||||
|
* @param uxIndex Used to distinguish between different co-routines that
|
||||||
|
* execute the same function. See the example below and the co-routine section
|
||||||
|
* of the WEB documentation for further information.
|
||||||
|
*
|
||||||
|
* @return pdPASS if the co-routine was successfully created and added to a ready
|
||||||
|
* list, otherwise an error code defined with ProjDefs.h.
|
||||||
|
*
|
||||||
|
* Example usage:
|
||||||
|
* @code{c}
|
||||||
|
* // Co-routine to be created.
|
||||||
|
* void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
|
||||||
|
* {
|
||||||
|
* // Variables in co-routines must be declared static if they must maintain value across a blocking call.
|
||||||
|
* // This may not be necessary for const variables.
|
||||||
|
* static const char cLedToFlash[ 2 ] = { 5, 6 };
|
||||||
|
* static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };
|
||||||
|
*
|
||||||
|
* // Must start every co-routine with a call to crSTART();
|
||||||
|
* crSTART( xHandle );
|
||||||
|
*
|
||||||
|
* for( ;; )
|
||||||
|
* {
|
||||||
|
* // This co-routine just delays for a fixed period, then toggles
|
||||||
|
* // an LED. Two co-routines are created using this function, so
|
||||||
|
* // the uxIndex parameter is used to tell the co-routine which
|
||||||
|
* // LED to flash and how int32_t to delay. This assumes xQueue has
|
||||||
|
* // already been created.
|
||||||
|
* vParTestToggleLED( cLedToFlash[ uxIndex ] );
|
||||||
|
* crDELAY( xHandle, uxFlashRates[ uxIndex ] );
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* // Must end every co-routine with a call to crEND();
|
||||||
|
* crEND();
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* // Function that creates two co-routines.
|
||||||
|
* void vOtherFunction( void )
|
||||||
|
* {
|
||||||
|
* uint8_t ucParameterToPass;
|
||||||
|
* TaskHandle_t xHandle;
|
||||||
|
*
|
||||||
|
* // Create two co-routines at priority 0. The first is given index 0
|
||||||
|
* // so (from the code above) toggles LED 5 every 200 ticks. The second
|
||||||
|
* // is given index 1 so toggles LED 6 every 400 ticks.
|
||||||
|
* for( uxIndex = 0; uxIndex < 2; uxIndex++ )
|
||||||
|
* {
|
||||||
|
* xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
|
||||||
|
* }
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
* \defgroup xCoRoutineCreate xCoRoutineCreate
|
||||||
|
* \ingroup Tasks
|
||||||
|
*/
|
||||||
|
BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode,
|
||||||
|
UBaseType_t uxPriority,
|
||||||
|
UBaseType_t uxIndex );
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* croutine. h
|
||||||
|
* @code{c}
|
||||||
|
* void vCoRoutineSchedule( void );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Run a co-routine.
|
||||||
|
*
|
||||||
|
* vCoRoutineSchedule() executes the highest priority co-routine that is able
|
||||||
|
* to run. The co-routine will execute until it either blocks, yields or is
|
||||||
|
* preempted by a task. Co-routines execute cooperatively so one
|
||||||
|
* co-routine cannot be preempted by another, but can be preempted by a task.
|
||||||
|
*
|
||||||
|
* If an application comprises of both tasks and co-routines then
|
||||||
|
* vCoRoutineSchedule should be called from the idle task (in an idle task
|
||||||
|
* hook).
|
||||||
|
*
|
||||||
|
* Example usage:
|
||||||
|
* @code{c}
|
||||||
|
* // This idle task hook will schedule a co-routine each time it is called.
|
||||||
|
* // The rest of the idle task will execute between co-routine calls.
|
||||||
|
* void vApplicationIdleHook( void )
|
||||||
|
* {
|
||||||
|
* vCoRoutineSchedule();
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* // Alternatively, if you do not require any other part of the idle task to
|
||||||
|
* // execute, the idle task hook can call vCoRoutineSchedule() within an
|
||||||
|
* // infinite loop.
|
||||||
|
* void vApplicationIdleHook( void )
|
||||||
|
* {
|
||||||
|
* for( ;; )
|
||||||
|
* {
|
||||||
|
* vCoRoutineSchedule();
|
||||||
|
* }
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
* \defgroup vCoRoutineSchedule vCoRoutineSchedule
|
||||||
|
* \ingroup Tasks
|
||||||
|
*/
|
||||||
|
void vCoRoutineSchedule( void );
|
||||||
|
|
||||||
|
/**
|
||||||
|
* croutine. h
|
||||||
|
* @code{c}
|
||||||
|
* crSTART( CoRoutineHandle_t xHandle );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* This macro MUST always be called at the start of a co-routine function.
|
||||||
|
*
|
||||||
|
* Example usage:
|
||||||
|
* @code{c}
|
||||||
|
* // Co-routine to be created.
|
||||||
|
* void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
|
||||||
|
* {
|
||||||
|
* // Variables in co-routines must be declared static if they must maintain value across a blocking call.
|
||||||
|
* static int32_t ulAVariable;
|
||||||
|
*
|
||||||
|
* // Must start every co-routine with a call to crSTART();
|
||||||
|
* crSTART( xHandle );
|
||||||
|
*
|
||||||
|
* for( ;; )
|
||||||
|
* {
|
||||||
|
* // Co-routine functionality goes here.
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* // Must end every co-routine with a call to crEND();
|
||||||
|
* crEND();
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
* \defgroup crSTART crSTART
|
||||||
|
* \ingroup Tasks
|
||||||
|
*/
|
||||||
|
#define crSTART( pxCRCB ) \
|
||||||
|
switch( ( ( CRCB_t * ) ( pxCRCB ) )->uxState ) { \
|
||||||
|
case 0:
|
||||||
|
|
||||||
|
/**
|
||||||
|
* croutine. h
|
||||||
|
* @code{c}
|
||||||
|
* crEND();
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* This macro MUST always be called at the end of a co-routine function.
|
||||||
|
*
|
||||||
|
* Example usage:
|
||||||
|
* @code{c}
|
||||||
|
* // Co-routine to be created.
|
||||||
|
* void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
|
||||||
|
* {
|
||||||
|
* // Variables in co-routines must be declared static if they must maintain value across a blocking call.
|
||||||
|
* static int32_t ulAVariable;
|
||||||
|
*
|
||||||
|
* // Must start every co-routine with a call to crSTART();
|
||||||
|
* crSTART( xHandle );
|
||||||
|
*
|
||||||
|
* for( ;; )
|
||||||
|
* {
|
||||||
|
* // Co-routine functionality goes here.
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* // Must end every co-routine with a call to crEND();
|
||||||
|
* crEND();
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
* \defgroup crSTART crSTART
|
||||||
|
* \ingroup Tasks
|
||||||
|
*/
|
||||||
|
#define crEND() }
|
||||||
|
|
||||||
|
/*
|
||||||
|
* These macros are intended for internal use by the co-routine implementation
|
||||||
|
* only. The macros should not be used directly by application writers.
|
||||||
|
*/
|
||||||
|
#define crSET_STATE0( xHandle ) \
|
||||||
|
( ( CRCB_t * ) ( xHandle ) )->uxState = ( __LINE__ * 2 ); return; \
|
||||||
|
case ( __LINE__ * 2 ):
|
||||||
|
#define crSET_STATE1( xHandle ) \
|
||||||
|
( ( CRCB_t * ) ( xHandle ) )->uxState = ( ( __LINE__ * 2 ) + 1 ); return; \
|
||||||
|
case ( ( __LINE__ * 2 ) + 1 ):
|
||||||
|
|
||||||
|
/**
|
||||||
|
* croutine. h
|
||||||
|
* @code{c}
|
||||||
|
* crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Delay a co-routine for a fixed period of time.
|
||||||
|
*
|
||||||
|
* crDELAY can only be called from the co-routine function itself - not
|
||||||
|
* from within a function called by the co-routine function. This is because
|
||||||
|
* co-routines do not maintain their own stack.
|
||||||
|
*
|
||||||
|
* @param xHandle The handle of the co-routine to delay. This is the xHandle
|
||||||
|
* parameter of the co-routine function.
|
||||||
|
*
|
||||||
|
* @param xTickToDelay The number of ticks that the co-routine should delay
|
||||||
|
* for. The actual amount of time this equates to is defined by
|
||||||
|
* configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant portTICK_PERIOD_MS
|
||||||
|
* can be used to convert ticks to milliseconds.
|
||||||
|
*
|
||||||
|
* Example usage:
|
||||||
|
* @code{c}
|
||||||
|
* // Co-routine to be created.
|
||||||
|
* void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
|
||||||
|
* {
|
||||||
|
* // Variables in co-routines must be declared static if they must maintain value across a blocking call.
|
||||||
|
* // This may not be necessary for const variables.
|
||||||
|
* // We are to delay for 200ms.
|
||||||
|
* static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;
|
||||||
|
*
|
||||||
|
* // Must start every co-routine with a call to crSTART();
|
||||||
|
* crSTART( xHandle );
|
||||||
|
*
|
||||||
|
* for( ;; )
|
||||||
|
* {
|
||||||
|
* // Delay for 200ms.
|
||||||
|
* crDELAY( xHandle, xDelayTime );
|
||||||
|
*
|
||||||
|
* // Do something here.
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* // Must end every co-routine with a call to crEND();
|
||||||
|
* crEND();
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
* \defgroup crDELAY crDELAY
|
||||||
|
* \ingroup Tasks
|
||||||
|
*/
|
||||||
|
#define crDELAY( xHandle, xTicksToDelay ) \
|
||||||
|
if( ( xTicksToDelay ) > 0 ) \
|
||||||
|
{ \
|
||||||
|
vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL ); \
|
||||||
|
} \
|
||||||
|
crSET_STATE0( ( xHandle ) );
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @code{c}
|
||||||
|
* crQUEUE_SEND(
|
||||||
|
* CoRoutineHandle_t xHandle,
|
||||||
|
* QueueHandle_t pxQueue,
|
||||||
|
* void *pvItemToQueue,
|
||||||
|
* TickType_t xTicksToWait,
|
||||||
|
* BaseType_t *pxResult
|
||||||
|
* )
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
|
||||||
|
* equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
|
||||||
|
*
|
||||||
|
* crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
|
||||||
|
* xQueueSend() and xQueueReceive() can only be used from tasks.
|
||||||
|
*
|
||||||
|
* crQUEUE_SEND can only be called from the co-routine function itself - not
|
||||||
|
* from within a function called by the co-routine function. This is because
|
||||||
|
* co-routines do not maintain their own stack.
|
||||||
|
*
|
||||||
|
* See the co-routine section of the WEB documentation for information on
|
||||||
|
* passing data between tasks and co-routines and between ISR's and
|
||||||
|
* co-routines.
|
||||||
|
*
|
||||||
|
* @param xHandle The handle of the calling co-routine. This is the xHandle
|
||||||
|
* parameter of the co-routine function.
|
||||||
|
*
|
||||||
|
* @param pxQueue The handle of the queue on which the data will be posted.
|
||||||
|
* The handle is obtained as the return value when the queue is created using
|
||||||
|
* the xQueueCreate() API function.
|
||||||
|
*
|
||||||
|
* @param pvItemToQueue A pointer to the data being posted onto the queue.
|
||||||
|
* The number of bytes of each queued item is specified when the queue is
|
||||||
|
* created. This number of bytes is copied from pvItemToQueue into the queue
|
||||||
|
* itself.
|
||||||
|
*
|
||||||
|
* @param xTickToDelay The number of ticks that the co-routine should block
|
||||||
|
* to wait for space to become available on the queue, should space not be
|
||||||
|
* available immediately. The actual amount of time this equates to is defined
|
||||||
|
* by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant
|
||||||
|
* portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example
|
||||||
|
* below).
|
||||||
|
*
|
||||||
|
* @param pxResult The variable pointed to by pxResult will be set to pdPASS if
|
||||||
|
* data was successfully posted onto the queue, otherwise it will be set to an
|
||||||
|
* error defined within ProjDefs.h.
|
||||||
|
*
|
||||||
|
* Example usage:
|
||||||
|
* @code{c}
|
||||||
|
* // Co-routine function that blocks for a fixed period then posts a number onto
|
||||||
|
* // a queue.
|
||||||
|
* static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
|
||||||
|
* {
|
||||||
|
* // Variables in co-routines must be declared static if they must maintain value across a blocking call.
|
||||||
|
* static BaseType_t xNumberToPost = 0;
|
||||||
|
* static BaseType_t xResult;
|
||||||
|
*
|
||||||
|
* // Co-routines must begin with a call to crSTART().
|
||||||
|
* crSTART( xHandle );
|
||||||
|
*
|
||||||
|
* for( ;; )
|
||||||
|
* {
|
||||||
|
* // This assumes the queue has already been created.
|
||||||
|
* crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
|
||||||
|
*
|
||||||
|
* if( xResult != pdPASS )
|
||||||
|
* {
|
||||||
|
* // The message was not posted!
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* // Increment the number to be posted onto the queue.
|
||||||
|
* xNumberToPost++;
|
||||||
|
*
|
||||||
|
* // Delay for 100 ticks.
|
||||||
|
* crDELAY( xHandle, 100 );
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* // Co-routines must end with a call to crEND().
|
||||||
|
* crEND();
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
* \defgroup crQUEUE_SEND crQUEUE_SEND
|
||||||
|
* \ingroup Tasks
|
||||||
|
*/
|
||||||
|
#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult ) \
|
||||||
|
{ \
|
||||||
|
*( pxResult ) = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), ( xTicksToWait ) ); \
|
||||||
|
if( *( pxResult ) == errQUEUE_BLOCKED ) \
|
||||||
|
{ \
|
||||||
|
crSET_STATE0( ( xHandle ) ); \
|
||||||
|
*pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 ); \
|
||||||
|
} \
|
||||||
|
if( *pxResult == errQUEUE_YIELD ) \
|
||||||
|
{ \
|
||||||
|
crSET_STATE1( ( xHandle ) ); \
|
||||||
|
*pxResult = pdPASS; \
|
||||||
|
} \
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* croutine. h
|
||||||
|
* @code{c}
|
||||||
|
* crQUEUE_RECEIVE(
|
||||||
|
* CoRoutineHandle_t xHandle,
|
||||||
|
* QueueHandle_t pxQueue,
|
||||||
|
* void *pvBuffer,
|
||||||
|
* TickType_t xTicksToWait,
|
||||||
|
* BaseType_t *pxResult
|
||||||
|
* )
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
|
||||||
|
* equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
|
||||||
|
*
|
||||||
|
* crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
|
||||||
|
* xQueueSend() and xQueueReceive() can only be used from tasks.
|
||||||
|
*
|
||||||
|
* crQUEUE_RECEIVE can only be called from the co-routine function itself - not
|
||||||
|
* from within a function called by the co-routine function. This is because
|
||||||
|
* co-routines do not maintain their own stack.
|
||||||
|
*
|
||||||
|
* See the co-routine section of the WEB documentation for information on
|
||||||
|
* passing data between tasks and co-routines and between ISR's and
|
||||||
|
* co-routines.
|
||||||
|
*
|
||||||
|
* @param xHandle The handle of the calling co-routine. This is the xHandle
|
||||||
|
* parameter of the co-routine function.
|
||||||
|
*
|
||||||
|
* @param pxQueue The handle of the queue from which the data will be received.
|
||||||
|
* The handle is obtained as the return value when the queue is created using
|
||||||
|
* the xQueueCreate() API function.
|
||||||
|
*
|
||||||
|
* @param pvBuffer The buffer into which the received item is to be copied.
|
||||||
|
* The number of bytes of each queued item is specified when the queue is
|
||||||
|
* created. This number of bytes is copied into pvBuffer.
|
||||||
|
*
|
||||||
|
* @param xTickToDelay The number of ticks that the co-routine should block
|
||||||
|
* to wait for data to become available from the queue, should data not be
|
||||||
|
* available immediately. The actual amount of time this equates to is defined
|
||||||
|
* by configTICK_RATE_HZ (set in FreeRTOSConfig.h). The constant
|
||||||
|
* portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the
|
||||||
|
* crQUEUE_SEND example).
|
||||||
|
*
|
||||||
|
* @param pxResult The variable pointed to by pxResult will be set to pdPASS if
|
||||||
|
* data was successfully retrieved from the queue, otherwise it will be set to
|
||||||
|
* an error code as defined within ProjDefs.h.
|
||||||
|
*
|
||||||
|
* Example usage:
|
||||||
|
* @code{c}
|
||||||
|
* // A co-routine receives the number of an LED to flash from a queue. It
|
||||||
|
* // blocks on the queue until the number is received.
|
||||||
|
* static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
|
||||||
|
* {
|
||||||
|
* // Variables in co-routines must be declared static if they must maintain value across a blocking call.
|
||||||
|
* static BaseType_t xResult;
|
||||||
|
* static UBaseType_t uxLEDToFlash;
|
||||||
|
*
|
||||||
|
* // All co-routines must start with a call to crSTART().
|
||||||
|
* crSTART( xHandle );
|
||||||
|
*
|
||||||
|
* for( ;; )
|
||||||
|
* {
|
||||||
|
* // Wait for data to become available on the queue.
|
||||||
|
* crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
|
||||||
|
*
|
||||||
|
* if( xResult == pdPASS )
|
||||||
|
* {
|
||||||
|
* // We received the LED to flash - flash it!
|
||||||
|
* vParTestToggleLED( uxLEDToFlash );
|
||||||
|
* }
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* crEND();
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
* \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE
|
||||||
|
* \ingroup Tasks
|
||||||
|
*/
|
||||||
|
#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult ) \
|
||||||
|
{ \
|
||||||
|
*( pxResult ) = xQueueCRReceive( ( pxQueue ), ( pvBuffer ), ( xTicksToWait ) ); \
|
||||||
|
if( *( pxResult ) == errQUEUE_BLOCKED ) \
|
||||||
|
{ \
|
||||||
|
crSET_STATE0( ( xHandle ) ); \
|
||||||
|
*( pxResult ) = xQueueCRReceive( ( pxQueue ), ( pvBuffer ), 0 ); \
|
||||||
|
} \
|
||||||
|
if( *( pxResult ) == errQUEUE_YIELD ) \
|
||||||
|
{ \
|
||||||
|
crSET_STATE1( ( xHandle ) ); \
|
||||||
|
*( pxResult ) = pdPASS; \
|
||||||
|
} \
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* croutine. h
|
||||||
|
* @code{c}
|
||||||
|
* crQUEUE_SEND_FROM_ISR(
|
||||||
|
* QueueHandle_t pxQueue,
|
||||||
|
* void *pvItemToQueue,
|
||||||
|
* BaseType_t xCoRoutinePreviouslyWoken
|
||||||
|
* )
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
|
||||||
|
* co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
|
||||||
|
* functions used by tasks.
|
||||||
|
*
|
||||||
|
* crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
|
||||||
|
* pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
|
||||||
|
* xQueueReceiveFromISR() can only be used to pass data between a task and and
|
||||||
|
* ISR.
|
||||||
|
*
|
||||||
|
* crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue
|
||||||
|
* that is being used from within a co-routine.
|
||||||
|
*
|
||||||
|
* See the co-routine section of the WEB documentation for information on
|
||||||
|
* passing data between tasks and co-routines and between ISR's and
|
||||||
|
* co-routines.
|
||||||
|
*
|
||||||
|
* @param xQueue The handle to the queue on which the item is to be posted.
|
||||||
|
*
|
||||||
|
* @param pvItemToQueue A pointer to the item that is to be placed on the
|
||||||
|
* queue. The size of the items the queue will hold was defined when the
|
||||||
|
* queue was created, so this many bytes will be copied from pvItemToQueue
|
||||||
|
* into the queue storage area.
|
||||||
|
*
|
||||||
|
* @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto
|
||||||
|
* the same queue multiple times from a single interrupt. The first call
|
||||||
|
* should always pass in pd0. Subsequent calls should pass in
|
||||||
|
* the value returned from the previous call.
|
||||||
|
*
|
||||||
|
* @return pd1 if a co-routine was woken by posting onto the queue. This is
|
||||||
|
* used by the ISR to determine if a context switch may be required following
|
||||||
|
* the ISR.
|
||||||
|
*
|
||||||
|
* Example usage:
|
||||||
|
* @code{c}
|
||||||
|
* // A co-routine that blocks on a queue waiting for characters to be received.
|
||||||
|
* static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
|
||||||
|
* {
|
||||||
|
* char cRxedChar;
|
||||||
|
* BaseType_t xResult;
|
||||||
|
*
|
||||||
|
* // All co-routines must start with a call to crSTART().
|
||||||
|
* crSTART( xHandle );
|
||||||
|
*
|
||||||
|
* for( ;; )
|
||||||
|
* {
|
||||||
|
* // Wait for data to become available on the queue. This assumes the
|
||||||
|
* // queue xCommsRxQueue has already been created!
|
||||||
|
* crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
|
||||||
|
*
|
||||||
|
* // Was a character received?
|
||||||
|
* if( xResult == pdPASS )
|
||||||
|
* {
|
||||||
|
* // Process the character here.
|
||||||
|
* }
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* // All co-routines must end with a call to crEND().
|
||||||
|
* crEND();
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* // An ISR that uses a queue to send characters received on a serial port to
|
||||||
|
* // a co-routine.
|
||||||
|
* void vUART_ISR( void )
|
||||||
|
* {
|
||||||
|
* char cRxedChar;
|
||||||
|
* BaseType_t xCRWokenByPost = pd0;
|
||||||
|
*
|
||||||
|
* // We loop around reading characters until there are none left in the UART.
|
||||||
|
* while( UART_RX_REG_NOT_EMPTY() )
|
||||||
|
* {
|
||||||
|
* // Obtain the character from the UART.
|
||||||
|
* cRxedChar = UART_RX_REG;
|
||||||
|
*
|
||||||
|
* // Post the character onto a queue. xCRWokenByPost will be pd0
|
||||||
|
* // the first time around the loop. If the post causes a co-routine
|
||||||
|
* // to be woken (unblocked) then xCRWokenByPost will be set to pd1.
|
||||||
|
* // In this manner we can ensure that if more than one co-routine is
|
||||||
|
* // blocked on the queue only one is woken by this ISR no matter how
|
||||||
|
* // many characters are posted to the queue.
|
||||||
|
* xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
|
||||||
|
* }
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
* \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR
|
||||||
|
* \ingroup Tasks
|
||||||
|
*/
|
||||||
|
#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) \
|
||||||
|
xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) )
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* croutine. h
|
||||||
|
* @code{c}
|
||||||
|
* crQUEUE_SEND_FROM_ISR(
|
||||||
|
* QueueHandle_t pxQueue,
|
||||||
|
* void *pvBuffer,
|
||||||
|
* BaseType_t * pxCoRoutineWoken
|
||||||
|
* )
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
|
||||||
|
* co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
|
||||||
|
* functions used by tasks.
|
||||||
|
*
|
||||||
|
* crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
|
||||||
|
* pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
|
||||||
|
* xQueueReceiveFromISR() can only be used to pass data between a task and and
|
||||||
|
* ISR.
|
||||||
|
*
|
||||||
|
* crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data
|
||||||
|
* from a queue that is being used from within a co-routine (a co-routine
|
||||||
|
* posted to the queue).
|
||||||
|
*
|
||||||
|
* See the co-routine section of the WEB documentation for information on
|
||||||
|
* passing data between tasks and co-routines and between ISR's and
|
||||||
|
* co-routines.
|
||||||
|
*
|
||||||
|
* @param xQueue The handle to the queue on which the item is to be posted.
|
||||||
|
*
|
||||||
|
* @param pvBuffer A pointer to a buffer into which the received item will be
|
||||||
|
* placed. The size of the items the queue will hold was defined when the
|
||||||
|
* queue was created, so this many bytes will be copied from the queue into
|
||||||
|
* pvBuffer.
|
||||||
|
*
|
||||||
|
* @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become
|
||||||
|
* available on the queue. If crQUEUE_RECEIVE_FROM_ISR causes such a
|
||||||
|
* co-routine to unblock *pxCoRoutineWoken will get set to pd1, otherwise
|
||||||
|
* *pxCoRoutineWoken will remain unchanged.
|
||||||
|
*
|
||||||
|
* @return pd1 an item was successfully received from the queue, otherwise
|
||||||
|
* pd0.
|
||||||
|
*
|
||||||
|
* Example usage:
|
||||||
|
* @code{c}
|
||||||
|
* // A co-routine that posts a character to a queue then blocks for a fixed
|
||||||
|
* // period. The character is incremented each time.
|
||||||
|
* static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
|
||||||
|
* {
|
||||||
|
* // cChar holds its value while this co-routine is blocked and must therefore
|
||||||
|
* // be declared static.
|
||||||
|
* static char cCharToTx = 'a';
|
||||||
|
* BaseType_t xResult;
|
||||||
|
*
|
||||||
|
* // All co-routines must start with a call to crSTART().
|
||||||
|
* crSTART( xHandle );
|
||||||
|
*
|
||||||
|
* for( ;; )
|
||||||
|
* {
|
||||||
|
* // Send the next character to the queue.
|
||||||
|
* crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
|
||||||
|
*
|
||||||
|
* if( xResult == pdPASS )
|
||||||
|
* {
|
||||||
|
* // The character was successfully posted to the queue.
|
||||||
|
* }
|
||||||
|
* else
|
||||||
|
* {
|
||||||
|
* // Could not post the character to the queue.
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* // Enable the UART Tx interrupt to cause an interrupt in this
|
||||||
|
* // hypothetical UART. The interrupt will obtain the character
|
||||||
|
* // from the queue and send it.
|
||||||
|
* ENABLE_RX_INTERRUPT();
|
||||||
|
*
|
||||||
|
* // Increment to the next character then block for a fixed period.
|
||||||
|
* // cCharToTx will maintain its value across the delay as it is
|
||||||
|
* // declared static.
|
||||||
|
* cCharToTx++;
|
||||||
|
* if( cCharToTx > 'x' )
|
||||||
|
* {
|
||||||
|
* cCharToTx = 'a';
|
||||||
|
* }
|
||||||
|
* crDELAY( 100 );
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* // All co-routines must end with a call to crEND().
|
||||||
|
* crEND();
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* // An ISR that uses a queue to receive characters to send on a UART.
|
||||||
|
* void vUART_ISR( void )
|
||||||
|
* {
|
||||||
|
* char cCharToTx;
|
||||||
|
* BaseType_t xCRWokenByPost = pd0;
|
||||||
|
*
|
||||||
|
* while( UART_TX_REG_EMPTY() )
|
||||||
|
* {
|
||||||
|
* // Are there any characters in the queue waiting to be sent?
|
||||||
|
* // xCRWokenByPost will automatically be set to pd1 if a co-routine
|
||||||
|
* // is woken by the post - ensuring that only a single co-routine is
|
||||||
|
* // woken no matter how many times we go around this loop.
|
||||||
|
* if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
|
||||||
|
* {
|
||||||
|
* SEND_CHARACTER( cCharToTx );
|
||||||
|
* }
|
||||||
|
* }
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
* \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR
|
||||||
|
* \ingroup Tasks
|
||||||
|
*/
|
||||||
|
#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) \
|
||||||
|
xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) )
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This function is intended for internal use by the co-routine macros only.
|
||||||
|
* The macro nature of the co-routine implementation requires that the
|
||||||
|
* prototype appears here. The function should not be used by application
|
||||||
|
* writers.
|
||||||
|
*
|
||||||
|
* Removes the current co-routine from its ready list and places it in the
|
||||||
|
* appropriate delayed list.
|
||||||
|
*/
|
||||||
|
void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay,
|
||||||
|
List_t * pxEventList );
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This function is intended for internal use by the queue implementation only.
|
||||||
|
* The function should not be used by application writers.
|
||||||
|
*
|
||||||
|
* Removes the highest priority co-routine from the event list and places it in
|
||||||
|
* the pending ready list.
|
||||||
|
*/
|
||||||
|
BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList );
|
||||||
|
|
||||||
|
/* *INDENT-OFF* */
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
/* *INDENT-ON* */
|
||||||
|
|
||||||
|
#endif /* CO_ROUTINE_H */
|
||||||
281
FreeRTOS/include/deprecated_definitions.h
Normal file
281
FreeRTOS/include/deprecated_definitions.h
Normal file
@@ -0,0 +1,281 @@
|
|||||||
|
/*
|
||||||
|
* FreeRTOS Kernel V10.4.6
|
||||||
|
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: MIT
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* https://www.FreeRTOS.org
|
||||||
|
* https://github.com/FreeRTOS
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef DEPRECATED_DEFINITIONS_H
|
||||||
|
#define DEPRECATED_DEFINITIONS_H
|
||||||
|
|
||||||
|
|
||||||
|
/* Each FreeRTOS port has a unique portmacro.h header file. Originally a
|
||||||
|
* pre-processor definition was used to ensure the pre-processor found the correct
|
||||||
|
* portmacro.h file for the port being used. That scheme was deprecated in favour
|
||||||
|
* of setting the compiler's include path such that it found the correct
|
||||||
|
* portmacro.h file - removing the need for the constant and allowing the
|
||||||
|
* portmacro.h file to be located anywhere in relation to the port being used. The
|
||||||
|
* definitions below remain in the code for backward compatibility only. New
|
||||||
|
* projects should not use them. */
|
||||||
|
|
||||||
|
#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT
|
||||||
|
#include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h"
|
||||||
|
typedef void ( __interrupt __far * pxISR )();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT
|
||||||
|
#include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h"
|
||||||
|
typedef void ( __interrupt __far * pxISR )();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef GCC_MEGA_AVR
|
||||||
|
#include "../portable/GCC/ATMega323/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef IAR_MEGA_AVR
|
||||||
|
#include "../portable/IAR/ATMega323/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef MPLAB_PIC24_PORT
|
||||||
|
#include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef MPLAB_DSPIC_PORT
|
||||||
|
#include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef MPLAB_PIC18F_PORT
|
||||||
|
#include "../../Source/portable/MPLAB/PIC18F/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef MPLAB_PIC32MX_PORT
|
||||||
|
#include "../../Source/portable/MPLAB/PIC32MX/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef _FEDPICC
|
||||||
|
#include "libFreeRTOS/Include/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef SDCC_CYGNAL
|
||||||
|
#include "../../Source/portable/SDCC/Cygnal/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef GCC_ARM7
|
||||||
|
#include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef GCC_ARM7_ECLIPSE
|
||||||
|
#include "portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef ROWLEY_LPC23xx
|
||||||
|
#include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef IAR_MSP430
|
||||||
|
#include "..\..\Source\portable\IAR\MSP430\portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef GCC_MSP430
|
||||||
|
#include "../../Source/portable/GCC/MSP430F449/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef ROWLEY_MSP430
|
||||||
|
#include "../../Source/portable/Rowley/MSP430F449/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef ARM7_LPC21xx_KEIL_RVDS
|
||||||
|
#include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef SAM7_GCC
|
||||||
|
#include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef SAM7_IAR
|
||||||
|
#include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef SAM9XE_IAR
|
||||||
|
#include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef LPC2000_IAR
|
||||||
|
#include "..\..\Source\portable\IAR\LPC2000\portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef STR71X_IAR
|
||||||
|
#include "..\..\Source\portable\IAR\STR71x\portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef STR75X_IAR
|
||||||
|
#include "..\..\Source\portable\IAR\STR75x\portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef STR75X_GCC
|
||||||
|
#include "..\..\Source\portable\GCC\STR75x\portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef STR91X_IAR
|
||||||
|
#include "..\..\Source\portable\IAR\STR91x\portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef GCC_H8S
|
||||||
|
#include "../../Source/portable/GCC/H8S2329/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef GCC_AT91FR40008
|
||||||
|
#include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef RVDS_ARMCM3_LM3S102
|
||||||
|
#include "../../Source/portable/RVDS/ARM_CM3/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef GCC_ARMCM3_LM3S102
|
||||||
|
#include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef GCC_ARMCM3
|
||||||
|
#include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef IAR_ARM_CM3
|
||||||
|
#include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef IAR_ARMCM3_LM
|
||||||
|
#include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef HCS12_CODE_WARRIOR
|
||||||
|
#include "../../Source/portable/CodeWarrior/HCS12/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef MICROBLAZE_GCC
|
||||||
|
#include "../../Source/portable/GCC/MicroBlaze/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef TERN_EE
|
||||||
|
#include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef GCC_HCS12
|
||||||
|
#include "../../Source/portable/GCC/HCS12/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef GCC_MCF5235
|
||||||
|
#include "../../Source/portable/GCC/MCF5235/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef COLDFIRE_V2_GCC
|
||||||
|
#include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef COLDFIRE_V2_CODEWARRIOR
|
||||||
|
#include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef GCC_PPC405
|
||||||
|
#include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef GCC_PPC440
|
||||||
|
#include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef _16FX_SOFTUNE
|
||||||
|
#include "..\..\Source\portable\Softune\MB96340\portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef BCC_INDUSTRIAL_PC_PORT
|
||||||
|
|
||||||
|
/* A short file name has to be used in place of the normal
|
||||||
|
* FreeRTOSConfig.h when using the Borland compiler. */
|
||||||
|
#include "frconfig.h"
|
||||||
|
#include "..\portable\BCC\16BitDOS\PC\prtmacro.h"
|
||||||
|
typedef void ( __interrupt __far * pxISR )();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef BCC_FLASH_LITE_186_PORT
|
||||||
|
|
||||||
|
/* A short file name has to be used in place of the normal
|
||||||
|
* FreeRTOSConfig.h when using the Borland compiler. */
|
||||||
|
#include "frconfig.h"
|
||||||
|
#include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h"
|
||||||
|
typedef void ( __interrupt __far * pxISR )();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __GNUC__
|
||||||
|
#ifdef __AVR32_AVR32A__
|
||||||
|
#include "portmacro.h"
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __ICCAVR32__
|
||||||
|
#ifdef __CORE__
|
||||||
|
#if __CORE__ == __AVR32A__
|
||||||
|
#include "portmacro.h"
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __91467D
|
||||||
|
#include "portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __96340
|
||||||
|
#include "portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __IAR_V850ES_Fx3__
|
||||||
|
#include "../../Source/portable/IAR/V850ES/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __IAR_V850ES_Jx3__
|
||||||
|
#include "../../Source/portable/IAR/V850ES/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __IAR_V850ES_Jx3_L__
|
||||||
|
#include "../../Source/portable/IAR/V850ES/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __IAR_V850ES_Jx2__
|
||||||
|
#include "../../Source/portable/IAR/V850ES/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __IAR_V850ES_Hx2__
|
||||||
|
#include "../../Source/portable/IAR/V850ES/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __IAR_78K0R_Kx3__
|
||||||
|
#include "../../Source/portable/IAR/78K0R/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __IAR_78K0R_Kx3L__
|
||||||
|
#include "../../Source/portable/IAR/78K0R/portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* DEPRECATED_DEFINITIONS_H */
|
||||||
777
FreeRTOS/include/event_groups.h
Normal file
777
FreeRTOS/include/event_groups.h
Normal file
@@ -0,0 +1,777 @@
|
|||||||
|
/*
|
||||||
|
* FreeRTOS Kernel V10.4.6
|
||||||
|
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: MIT
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* https://www.FreeRTOS.org
|
||||||
|
* https://github.com/FreeRTOS
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef EVENT_GROUPS_H
|
||||||
|
#define EVENT_GROUPS_H
|
||||||
|
|
||||||
|
#ifndef INC_FREERTOS_H
|
||||||
|
#error "include FreeRTOS.h" must appear in source files before "include event_groups.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* FreeRTOS includes. */
|
||||||
|
#include "timers.h"
|
||||||
|
|
||||||
|
/* *INDENT-OFF* */
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
/* *INDENT-ON* */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* An event group is a collection of bits to which an application can assign a
|
||||||
|
* meaning. For example, an application may create an event group to convey
|
||||||
|
* the status of various CAN bus related events in which bit 0 might mean "A CAN
|
||||||
|
* message has been received and is ready for processing", bit 1 might mean "The
|
||||||
|
* application has queued a message that is ready for sending onto the CAN
|
||||||
|
* network", and bit 2 might mean "It is time to send a SYNC message onto the
|
||||||
|
* CAN network" etc. A task can then test the bit values to see which events
|
||||||
|
* are active, and optionally enter the Blocked state to wait for a specified
|
||||||
|
* bit or a group of specified bits to be active. To continue the CAN bus
|
||||||
|
* example, a CAN controlling task can enter the Blocked state (and therefore
|
||||||
|
* not consume any processing time) until either bit 0, bit 1 or bit 2 are
|
||||||
|
* active, at which time the bit that was actually active would inform the task
|
||||||
|
* which action it had to take (process a received message, send a message, or
|
||||||
|
* send a SYNC).
|
||||||
|
*
|
||||||
|
* The event groups implementation contains intelligence to avoid race
|
||||||
|
* conditions that would otherwise occur were an application to use a simple
|
||||||
|
* variable for the same purpose. This is particularly important with respect
|
||||||
|
* to when a bit within an event group is to be cleared, and when bits have to
|
||||||
|
* be set and then tested atomically - as is the case where event groups are
|
||||||
|
* used to create a synchronisation point between multiple tasks (a
|
||||||
|
* 'rendezvous').
|
||||||
|
*
|
||||||
|
* \defgroup EventGroup
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* event_groups.h
|
||||||
|
*
|
||||||
|
* Type by which event groups are referenced. For example, a call to
|
||||||
|
* xEventGroupCreate() returns an EventGroupHandle_t variable that can then
|
||||||
|
* be used as a parameter to other event group functions.
|
||||||
|
*
|
||||||
|
* \defgroup EventGroupHandle_t EventGroupHandle_t
|
||||||
|
* \ingroup EventGroup
|
||||||
|
*/
|
||||||
|
struct EventGroupDef_t;
|
||||||
|
typedef struct EventGroupDef_t * EventGroupHandle_t;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The type that holds event bits always matches TickType_t - therefore the
|
||||||
|
* number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1,
|
||||||
|
* 32 bits if set to 0.
|
||||||
|
*
|
||||||
|
* \defgroup EventBits_t EventBits_t
|
||||||
|
* \ingroup EventGroup
|
||||||
|
*/
|
||||||
|
typedef TickType_t EventBits_t;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* event_groups.h
|
||||||
|
* @code{c}
|
||||||
|
* EventGroupHandle_t xEventGroupCreate( void );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Create a new event group.
|
||||||
|
*
|
||||||
|
* Internally, within the FreeRTOS implementation, event groups use a [small]
|
||||||
|
* block of memory, in which the event group's structure is stored. If an event
|
||||||
|
* groups is created using xEventGroupCreate() then the required memory is
|
||||||
|
* automatically dynamically allocated inside the xEventGroupCreate() function.
|
||||||
|
* (see https://www.FreeRTOS.org/a00111.html). If an event group is created
|
||||||
|
* using xEventGroupCreateStatic() then the application writer must instead
|
||||||
|
* provide the memory that will get used by the event group.
|
||||||
|
* xEventGroupCreateStatic() therefore allows an event group to be created
|
||||||
|
* without using any dynamic memory allocation.
|
||||||
|
*
|
||||||
|
* Although event groups are not related to ticks, for internal implementation
|
||||||
|
* reasons the number of bits available for use in an event group is dependent
|
||||||
|
* on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If
|
||||||
|
* configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit
|
||||||
|
* 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has
|
||||||
|
* 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store
|
||||||
|
* event bits within an event group.
|
||||||
|
*
|
||||||
|
* @return If the event group was created then a handle to the event group is
|
||||||
|
* returned. If there was insufficient FreeRTOS heap available to create the
|
||||||
|
* event group then NULL is returned. See https://www.FreeRTOS.org/a00111.html
|
||||||
|
*
|
||||||
|
* Example usage:
|
||||||
|
* @code{c}
|
||||||
|
* // Declare a variable to hold the created event group.
|
||||||
|
* EventGroupHandle_t xCreatedEventGroup;
|
||||||
|
*
|
||||||
|
* // Attempt to create the event group.
|
||||||
|
* xCreatedEventGroup = xEventGroupCreate();
|
||||||
|
*
|
||||||
|
* // Was the event group created successfully?
|
||||||
|
* if( xCreatedEventGroup == NULL )
|
||||||
|
* {
|
||||||
|
* // The event group was not created because there was insufficient
|
||||||
|
* // FreeRTOS heap available.
|
||||||
|
* }
|
||||||
|
* else
|
||||||
|
* {
|
||||||
|
* // The event group was created.
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
* \defgroup xEventGroupCreate xEventGroupCreate
|
||||||
|
* \ingroup EventGroup
|
||||||
|
*/
|
||||||
|
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
|
||||||
|
EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* event_groups.h
|
||||||
|
* @code{c}
|
||||||
|
* EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Create a new event group.
|
||||||
|
*
|
||||||
|
* Internally, within the FreeRTOS implementation, event groups use a [small]
|
||||||
|
* block of memory, in which the event group's structure is stored. If an event
|
||||||
|
* groups is created using xEventGroupCreate() then the required memory is
|
||||||
|
* automatically dynamically allocated inside the xEventGroupCreate() function.
|
||||||
|
* (see https://www.FreeRTOS.org/a00111.html). If an event group is created
|
||||||
|
* using xEventGroupCreateStatic() then the application writer must instead
|
||||||
|
* provide the memory that will get used by the event group.
|
||||||
|
* xEventGroupCreateStatic() therefore allows an event group to be created
|
||||||
|
* without using any dynamic memory allocation.
|
||||||
|
*
|
||||||
|
* Although event groups are not related to ticks, for internal implementation
|
||||||
|
* reasons the number of bits available for use in an event group is dependent
|
||||||
|
* on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If
|
||||||
|
* configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit
|
||||||
|
* 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has
|
||||||
|
* 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store
|
||||||
|
* event bits within an event group.
|
||||||
|
*
|
||||||
|
* @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type
|
||||||
|
* StaticEventGroup_t, which will be then be used to hold the event group's data
|
||||||
|
* structures, removing the need for the memory to be allocated dynamically.
|
||||||
|
*
|
||||||
|
* @return If the event group was created then a handle to the event group is
|
||||||
|
* returned. If pxEventGroupBuffer was NULL then NULL is returned.
|
||||||
|
*
|
||||||
|
* Example usage:
|
||||||
|
* @code{c}
|
||||||
|
* // StaticEventGroup_t is a publicly accessible structure that has the same
|
||||||
|
* // size and alignment requirements as the real event group structure. It is
|
||||||
|
* // provided as a mechanism for applications to know the size of the event
|
||||||
|
* // group (which is dependent on the architecture and configuration file
|
||||||
|
* // settings) without breaking the strict data hiding policy by exposing the
|
||||||
|
* // real event group internals. This StaticEventGroup_t variable is passed
|
||||||
|
* // into the xSemaphoreCreateEventGroupStatic() function and is used to store
|
||||||
|
* // the event group's data structures
|
||||||
|
* StaticEventGroup_t xEventGroupBuffer;
|
||||||
|
*
|
||||||
|
* // Create the event group without dynamically allocating any memory.
|
||||||
|
* xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
|
||||||
|
* @endcode
|
||||||
|
*/
|
||||||
|
#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
|
||||||
|
EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) PRIVILEGED_FUNCTION;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* event_groups.h
|
||||||
|
* @code{c}
|
||||||
|
* EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
|
||||||
|
* const EventBits_t uxBitsToWaitFor,
|
||||||
|
* const BaseType_t xClearOnExit,
|
||||||
|
* const BaseType_t xWaitForAllBits,
|
||||||
|
* const TickType_t xTicksToWait );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* [Potentially] block to wait for one or more bits to be set within a
|
||||||
|
* previously created event group.
|
||||||
|
*
|
||||||
|
* This function cannot be called from an interrupt.
|
||||||
|
*
|
||||||
|
* @param xEventGroup The event group in which the bits are being tested. The
|
||||||
|
* event group must have previously been created using a call to
|
||||||
|
* xEventGroupCreate().
|
||||||
|
*
|
||||||
|
* @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
|
||||||
|
* inside the event group. For example, to wait for bit 0 and/or bit 2 set
|
||||||
|
* uxBitsToWaitFor to 0x05. To wait for bits 0 and/or bit 1 and/or bit 2 set
|
||||||
|
* uxBitsToWaitFor to 0x07. Etc.
|
||||||
|
*
|
||||||
|
* @param xClearOnExit If xClearOnExit is set to pd1 then any bits within
|
||||||
|
* uxBitsToWaitFor that are set within the event group will be cleared before
|
||||||
|
* xEventGroupWaitBits() returns if the wait condition was met (if the function
|
||||||
|
* returns for a reason other than a timeout). If xClearOnExit is set to
|
||||||
|
* pd0 then the bits set in the event group are not altered when the call to
|
||||||
|
* xEventGroupWaitBits() returns.
|
||||||
|
*
|
||||||
|
* @param xWaitForAllBits If xWaitForAllBits is set to pd1 then
|
||||||
|
* xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor
|
||||||
|
* are set or the specified block time expires. If xWaitForAllBits is set to
|
||||||
|
* pd0 then xEventGroupWaitBits() will return when any one of the bits set
|
||||||
|
* in uxBitsToWaitFor is set or the specified block time expires. The block
|
||||||
|
* time is specified by the xTicksToWait parameter.
|
||||||
|
*
|
||||||
|
* @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
|
||||||
|
* for one/all (depending on the xWaitForAllBits value) of the bits specified by
|
||||||
|
* uxBitsToWaitFor to become set.
|
||||||
|
*
|
||||||
|
* @return The value of the event group at the time either the bits being waited
|
||||||
|
* for became set, or the block time expired. Test the return value to know
|
||||||
|
* which bits were set. If xEventGroupWaitBits() returned because its timeout
|
||||||
|
* expired then not all the bits being waited for will be set. If
|
||||||
|
* xEventGroupWaitBits() returned because the bits it was waiting for were set
|
||||||
|
* then the returned value is the event group value before any bits were
|
||||||
|
* automatically cleared in the case that xClearOnExit parameter was set to
|
||||||
|
* pd1.
|
||||||
|
*
|
||||||
|
* Example usage:
|
||||||
|
* @code{c}
|
||||||
|
* #define BIT_0 ( 1 << 0 )
|
||||||
|
* #define BIT_4 ( 1 << 4 )
|
||||||
|
*
|
||||||
|
* void aFunction( EventGroupHandle_t xEventGroup )
|
||||||
|
* {
|
||||||
|
* EventBits_t uxBits;
|
||||||
|
* const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
|
||||||
|
*
|
||||||
|
* // Wait a maximum of 100ms for either bit 0 or bit 4 to be set within
|
||||||
|
* // the event group. Clear the bits before exiting.
|
||||||
|
* uxBits = xEventGroupWaitBits(
|
||||||
|
* xEventGroup, // The event group being tested.
|
||||||
|
* BIT_0 | BIT_4, // The bits within the event group to wait for.
|
||||||
|
* pd1, // BIT_0 and BIT_4 should be cleared before returning.
|
||||||
|
* pd0, // Don't wait for both bits, either bit will do.
|
||||||
|
* xTicksToWait ); // Wait a maximum of 100ms for either bit to be set.
|
||||||
|
*
|
||||||
|
* if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
|
||||||
|
* {
|
||||||
|
* // xEventGroupWaitBits() returned because both bits were set.
|
||||||
|
* }
|
||||||
|
* else if( ( uxBits & BIT_0 ) != 0 )
|
||||||
|
* {
|
||||||
|
* // xEventGroupWaitBits() returned because just BIT_0 was set.
|
||||||
|
* }
|
||||||
|
* else if( ( uxBits & BIT_4 ) != 0 )
|
||||||
|
* {
|
||||||
|
* // xEventGroupWaitBits() returned because just BIT_4 was set.
|
||||||
|
* }
|
||||||
|
* else
|
||||||
|
* {
|
||||||
|
* // xEventGroupWaitBits() returned because xTicksToWait ticks passed
|
||||||
|
* // without either BIT_0 or BIT_4 becoming set.
|
||||||
|
* }
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
* \defgroup xEventGroupWaitBits xEventGroupWaitBits
|
||||||
|
* \ingroup EventGroup
|
||||||
|
*/
|
||||||
|
EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
|
||||||
|
const EventBits_t uxBitsToWaitFor,
|
||||||
|
const BaseType_t xClearOnExit,
|
||||||
|
const BaseType_t xWaitForAllBits,
|
||||||
|
TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* event_groups.h
|
||||||
|
* @code{c}
|
||||||
|
* EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Clear bits within an event group. This function cannot be called from an
|
||||||
|
* interrupt.
|
||||||
|
*
|
||||||
|
* @param xEventGroup The event group in which the bits are to be cleared.
|
||||||
|
*
|
||||||
|
* @param uxBitsToClear A bitwise value that indicates the bit or bits to clear
|
||||||
|
* in the event group. For example, to clear bit 3 only, set uxBitsToClear to
|
||||||
|
* 0x08. To clear bit 3 and bit 0 set uxBitsToClear to 0x09.
|
||||||
|
*
|
||||||
|
* @return The value of the event group before the specified bits were cleared.
|
||||||
|
*
|
||||||
|
* Example usage:
|
||||||
|
* @code{c}
|
||||||
|
* #define BIT_0 ( 1 << 0 )
|
||||||
|
* #define BIT_4 ( 1 << 4 )
|
||||||
|
*
|
||||||
|
* void aFunction( EventGroupHandle_t xEventGroup )
|
||||||
|
* {
|
||||||
|
* EventBits_t uxBits;
|
||||||
|
*
|
||||||
|
* // Clear bit 0 and bit 4 in xEventGroup.
|
||||||
|
* uxBits = xEventGroupClearBits(
|
||||||
|
* xEventGroup, // The event group being updated.
|
||||||
|
* BIT_0 | BIT_4 );// The bits being cleared.
|
||||||
|
*
|
||||||
|
* if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
|
||||||
|
* {
|
||||||
|
* // Both bit 0 and bit 4 were set before xEventGroupClearBits() was
|
||||||
|
* // called. Both will now be clear (not set).
|
||||||
|
* }
|
||||||
|
* else if( ( uxBits & BIT_0 ) != 0 )
|
||||||
|
* {
|
||||||
|
* // Bit 0 was set before xEventGroupClearBits() was called. It will
|
||||||
|
* // now be clear.
|
||||||
|
* }
|
||||||
|
* else if( ( uxBits & BIT_4 ) != 0 )
|
||||||
|
* {
|
||||||
|
* // Bit 4 was set before xEventGroupClearBits() was called. It will
|
||||||
|
* // now be clear.
|
||||||
|
* }
|
||||||
|
* else
|
||||||
|
* {
|
||||||
|
* // Neither bit 0 nor bit 4 were set in the first place.
|
||||||
|
* }
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
* \defgroup xEventGroupClearBits xEventGroupClearBits
|
||||||
|
* \ingroup EventGroup
|
||||||
|
*/
|
||||||
|
EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup,
|
||||||
|
const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* event_groups.h
|
||||||
|
* @code{c}
|
||||||
|
* BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* A version of xEventGroupClearBits() that can be called from an interrupt.
|
||||||
|
*
|
||||||
|
* Setting bits in an event group is not a deterministic operation because there
|
||||||
|
* are an unknown number of tasks that may be waiting for the bit or bits being
|
||||||
|
* set. FreeRTOS does not allow nondeterministic operations to be performed
|
||||||
|
* while interrupts are disabled, so protects event groups that are accessed
|
||||||
|
* from tasks by suspending the scheduler rather than disabling interrupts. As
|
||||||
|
* a result event groups cannot be accessed directly from an interrupt service
|
||||||
|
* routine. Therefore xEventGroupClearBitsFromISR() sends a message to the
|
||||||
|
* timer task to have the clear operation performed in the context of the timer
|
||||||
|
* task.
|
||||||
|
*
|
||||||
|
* @param xEventGroup The event group in which the bits are to be cleared.
|
||||||
|
*
|
||||||
|
* @param uxBitsToClear A bitwise value that indicates the bit or bits to clear.
|
||||||
|
* For example, to clear bit 3 only, set uxBitsToClear to 0x08. To clear bit 3
|
||||||
|
* and bit 0 set uxBitsToClear to 0x09.
|
||||||
|
*
|
||||||
|
* @return If the request to execute the function was posted successfully then
|
||||||
|
* pdPASS is returned, otherwise pd0 is returned. pd0 will be returned
|
||||||
|
* if the timer service queue was full.
|
||||||
|
*
|
||||||
|
* Example usage:
|
||||||
|
* @code{c}
|
||||||
|
* #define BIT_0 ( 1 << 0 )
|
||||||
|
* #define BIT_4 ( 1 << 4 )
|
||||||
|
*
|
||||||
|
* // An event group which it is assumed has already been created by a call to
|
||||||
|
* // xEventGroupCreate().
|
||||||
|
* EventGroupHandle_t xEventGroup;
|
||||||
|
*
|
||||||
|
* void anInterruptHandler( void )
|
||||||
|
* {
|
||||||
|
* // Clear bit 0 and bit 4 in xEventGroup.
|
||||||
|
* xResult = xEventGroupClearBitsFromISR(
|
||||||
|
* xEventGroup, // The event group being updated.
|
||||||
|
* BIT_0 | BIT_4 ); // The bits being set.
|
||||||
|
*
|
||||||
|
* if( xResult == pdPASS )
|
||||||
|
* {
|
||||||
|
* // The message was posted successfully.
|
||||||
|
* }
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
* \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR
|
||||||
|
* \ingroup EventGroup
|
||||||
|
*/
|
||||||
|
#if ( configUSE_TRACE_FACILITY == 1 )
|
||||||
|
BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
|
||||||
|
const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
|
||||||
|
#else
|
||||||
|
#define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) \
|
||||||
|
xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL )
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* event_groups.h
|
||||||
|
* @code{c}
|
||||||
|
* EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Set bits within an event group.
|
||||||
|
* This function cannot be called from an interrupt. xEventGroupSetBitsFromISR()
|
||||||
|
* is a version that can be called from an interrupt.
|
||||||
|
*
|
||||||
|
* Setting bits in an event group will automatically unblock tasks that are
|
||||||
|
* blocked waiting for the bits.
|
||||||
|
*
|
||||||
|
* @param xEventGroup The event group in which the bits are to be set.
|
||||||
|
*
|
||||||
|
* @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
|
||||||
|
* For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3
|
||||||
|
* and bit 0 set uxBitsToSet to 0x09.
|
||||||
|
*
|
||||||
|
* @return The value of the event group at the time the call to
|
||||||
|
* xEventGroupSetBits() returns. There are two reasons why the returned value
|
||||||
|
* might have the bits specified by the uxBitsToSet parameter cleared. First,
|
||||||
|
* if setting a bit results in a task that was waiting for the bit leaving the
|
||||||
|
* blocked state then it is possible the bit will be cleared automatically
|
||||||
|
* (see the xClearBitOnExit parameter of xEventGroupWaitBits()). Second, any
|
||||||
|
* unblocked (or otherwise Ready state) task that has a priority above that of
|
||||||
|
* the task that called xEventGroupSetBits() will execute and may change the
|
||||||
|
* event group value before the call to xEventGroupSetBits() returns.
|
||||||
|
*
|
||||||
|
* Example usage:
|
||||||
|
* @code{c}
|
||||||
|
* #define BIT_0 ( 1 << 0 )
|
||||||
|
* #define BIT_4 ( 1 << 4 )
|
||||||
|
*
|
||||||
|
* void aFunction( EventGroupHandle_t xEventGroup )
|
||||||
|
* {
|
||||||
|
* EventBits_t uxBits;
|
||||||
|
*
|
||||||
|
* // Set bit 0 and bit 4 in xEventGroup.
|
||||||
|
* uxBits = xEventGroupSetBits(
|
||||||
|
* xEventGroup, // The event group being updated.
|
||||||
|
* BIT_0 | BIT_4 );// The bits being set.
|
||||||
|
*
|
||||||
|
* if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
|
||||||
|
* {
|
||||||
|
* // Both bit 0 and bit 4 remained set when the function returned.
|
||||||
|
* }
|
||||||
|
* else if( ( uxBits & BIT_0 ) != 0 )
|
||||||
|
* {
|
||||||
|
* // Bit 0 remained set when the function returned, but bit 4 was
|
||||||
|
* // cleared. It might be that bit 4 was cleared automatically as a
|
||||||
|
* // task that was waiting for bit 4 was removed from the Blocked
|
||||||
|
* // state.
|
||||||
|
* }
|
||||||
|
* else if( ( uxBits & BIT_4 ) != 0 )
|
||||||
|
* {
|
||||||
|
* // Bit 4 remained set when the function returned, but bit 0 was
|
||||||
|
* // cleared. It might be that bit 0 was cleared automatically as a
|
||||||
|
* // task that was waiting for bit 0 was removed from the Blocked
|
||||||
|
* // state.
|
||||||
|
* }
|
||||||
|
* else
|
||||||
|
* {
|
||||||
|
* // Neither bit 0 nor bit 4 remained set. It might be that a task
|
||||||
|
* // was waiting for both of the bits to be set, and the bits were
|
||||||
|
* // cleared as the task left the Blocked state.
|
||||||
|
* }
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
* \defgroup xEventGroupSetBits xEventGroupSetBits
|
||||||
|
* \ingroup EventGroup
|
||||||
|
*/
|
||||||
|
EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup,
|
||||||
|
const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* event_groups.h
|
||||||
|
* @code{c}
|
||||||
|
* BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* A version of xEventGroupSetBits() that can be called from an interrupt.
|
||||||
|
*
|
||||||
|
* Setting bits in an event group is not a deterministic operation because there
|
||||||
|
* are an unknown number of tasks that may be waiting for the bit or bits being
|
||||||
|
* set. FreeRTOS does not allow nondeterministic operations to be performed in
|
||||||
|
* interrupts or from critical sections. Therefore xEventGroupSetBitsFromISR()
|
||||||
|
* sends a message to the timer task to have the set operation performed in the
|
||||||
|
* context of the timer task - where a scheduler lock is used in place of a
|
||||||
|
* critical section.
|
||||||
|
*
|
||||||
|
* @param xEventGroup The event group in which the bits are to be set.
|
||||||
|
*
|
||||||
|
* @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
|
||||||
|
* For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3
|
||||||
|
* and bit 0 set uxBitsToSet to 0x09.
|
||||||
|
*
|
||||||
|
* @param pxHigherPriorityTaskWoken As mentioned above, calling this function
|
||||||
|
* will result in a message being sent to the timer daemon task. If the
|
||||||
|
* priority of the timer daemon task is higher than the priority of the
|
||||||
|
* currently running task (the task the interrupt interrupted) then
|
||||||
|
* *pxHigherPriorityTaskWoken will be set to pd1 by
|
||||||
|
* xEventGroupSetBitsFromISR(), indicating that a context switch should be
|
||||||
|
* requested before the interrupt exits. For that reason
|
||||||
|
* *pxHigherPriorityTaskWoken must be initialised to pd0. See the
|
||||||
|
* example code below.
|
||||||
|
*
|
||||||
|
* @return If the request to execute the function was posted successfully then
|
||||||
|
* pdPASS is returned, otherwise pd0 is returned. pd0 will be returned
|
||||||
|
* if the timer service queue was full.
|
||||||
|
*
|
||||||
|
* Example usage:
|
||||||
|
* @code{c}
|
||||||
|
* #define BIT_0 ( 1 << 0 )
|
||||||
|
* #define BIT_4 ( 1 << 4 )
|
||||||
|
*
|
||||||
|
* // An event group which it is assumed has already been created by a call to
|
||||||
|
* // xEventGroupCreate().
|
||||||
|
* EventGroupHandle_t xEventGroup;
|
||||||
|
*
|
||||||
|
* void anInterruptHandler( void )
|
||||||
|
* {
|
||||||
|
* BaseType_t xHigherPriorityTaskWoken, xResult;
|
||||||
|
*
|
||||||
|
* // xHigherPriorityTaskWoken must be initialised to pd0.
|
||||||
|
* xHigherPriorityTaskWoken = pd0;
|
||||||
|
*
|
||||||
|
* // Set bit 0 and bit 4 in xEventGroup.
|
||||||
|
* xResult = xEventGroupSetBitsFromISR(
|
||||||
|
* xEventGroup, // The event group being updated.
|
||||||
|
* BIT_0 | BIT_4 // The bits being set.
|
||||||
|
* &xHigherPriorityTaskWoken );
|
||||||
|
*
|
||||||
|
* // Was the message posted successfully?
|
||||||
|
* if( xResult == pdPASS )
|
||||||
|
* {
|
||||||
|
* // If xHigherPriorityTaskWoken is now set to pd1 then a context
|
||||||
|
* // switch should be requested. The macro used is port specific and
|
||||||
|
* // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
|
||||||
|
* // refer to the documentation page for the port being used.
|
||||||
|
* portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
|
||||||
|
* }
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
* \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR
|
||||||
|
* \ingroup EventGroup
|
||||||
|
*/
|
||||||
|
#if ( configUSE_TRACE_FACILITY == 1 )
|
||||||
|
BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
|
||||||
|
const EventBits_t uxBitsToSet,
|
||||||
|
BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
|
||||||
|
#else
|
||||||
|
#define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) \
|
||||||
|
xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken )
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
* event_groups.h
|
||||||
|
* @code{c}
|
||||||
|
* EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,
|
||||||
|
* const EventBits_t uxBitsToSet,
|
||||||
|
* const EventBits_t uxBitsToWaitFor,
|
||||||
|
* TickType_t xTicksToWait );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Atomically set bits within an event group, then wait for a combination of
|
||||||
|
* bits to be set within the same event group. This functionality is typically
|
||||||
|
* used to synchronise multiple tasks, where each task has to wait for the other
|
||||||
|
* tasks to reach a synchronisation point before proceeding.
|
||||||
|
*
|
||||||
|
* This function cannot be used from an interrupt.
|
||||||
|
*
|
||||||
|
* The function will return before its block time expires if the bits specified
|
||||||
|
* by the uxBitsToWait parameter are set, or become set within that time. In
|
||||||
|
* this case all the bits specified by uxBitsToWait will be automatically
|
||||||
|
* cleared before the function returns.
|
||||||
|
*
|
||||||
|
* @param xEventGroup The event group in which the bits are being tested. The
|
||||||
|
* event group must have previously been created using a call to
|
||||||
|
* xEventGroupCreate().
|
||||||
|
*
|
||||||
|
* @param uxBitsToSet The bits to set in the event group before determining
|
||||||
|
* if, and possibly waiting for, all the bits specified by the uxBitsToWait
|
||||||
|
* parameter are set.
|
||||||
|
*
|
||||||
|
* @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
|
||||||
|
* inside the event group. For example, to wait for bit 0 and bit 2 set
|
||||||
|
* uxBitsToWaitFor to 0x05. To wait for bits 0 and bit 1 and bit 2 set
|
||||||
|
* uxBitsToWaitFor to 0x07. Etc.
|
||||||
|
*
|
||||||
|
* @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
|
||||||
|
* for all of the bits specified by uxBitsToWaitFor to become set.
|
||||||
|
*
|
||||||
|
* @return The value of the event group at the time either the bits being waited
|
||||||
|
* for became set, or the block time expired. Test the return value to know
|
||||||
|
* which bits were set. If xEventGroupSync() returned because its timeout
|
||||||
|
* expired then not all the bits being waited for will be set. If
|
||||||
|
* xEventGroupSync() returned because all the bits it was waiting for were
|
||||||
|
* set then the returned value is the event group value before any bits were
|
||||||
|
* automatically cleared.
|
||||||
|
*
|
||||||
|
* Example usage:
|
||||||
|
* @code{c}
|
||||||
|
* // Bits used by the three tasks.
|
||||||
|
* #define TASK_0_BIT ( 1 << 0 )
|
||||||
|
* #define TASK_1_BIT ( 1 << 1 )
|
||||||
|
* #define TASK_2_BIT ( 1 << 2 )
|
||||||
|
*
|
||||||
|
* #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )
|
||||||
|
*
|
||||||
|
* // Use an event group to synchronise three tasks. It is assumed this event
|
||||||
|
* // group has already been created elsewhere.
|
||||||
|
* EventGroupHandle_t xEventBits;
|
||||||
|
*
|
||||||
|
* void vTask0( void *pvParameters )
|
||||||
|
* {
|
||||||
|
* EventBits_t uxReturn;
|
||||||
|
* TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
|
||||||
|
*
|
||||||
|
* for( ;; )
|
||||||
|
* {
|
||||||
|
* // Perform task functionality here.
|
||||||
|
*
|
||||||
|
* // Set bit 0 in the event flag to note this task has reached the
|
||||||
|
* // sync point. The other two tasks will set the other two bits defined
|
||||||
|
* // by ALL_SYNC_BITS. All three tasks have reached the synchronisation
|
||||||
|
* // point when all the ALL_SYNC_BITS are set. Wait a maximum of 100ms
|
||||||
|
* // for this to happen.
|
||||||
|
* uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );
|
||||||
|
*
|
||||||
|
* if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )
|
||||||
|
* {
|
||||||
|
* // All three tasks reached the synchronisation point before the call
|
||||||
|
* // to xEventGroupSync() timed out.
|
||||||
|
* }
|
||||||
|
* }
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* void vTask1( void *pvParameters )
|
||||||
|
* {
|
||||||
|
* for( ;; )
|
||||||
|
* {
|
||||||
|
* // Perform task functionality here.
|
||||||
|
*
|
||||||
|
* // Set bit 1 in the event flag to note this task has reached the
|
||||||
|
* // synchronisation point. The other two tasks will set the other two
|
||||||
|
* // bits defined by ALL_SYNC_BITS. All three tasks have reached the
|
||||||
|
* // synchronisation point when all the ALL_SYNC_BITS are set. Wait
|
||||||
|
* // indefinitely for this to happen.
|
||||||
|
* xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );
|
||||||
|
*
|
||||||
|
* // xEventGroupSync() was called with an indefinite block time, so
|
||||||
|
* // this task will only reach here if the synchronisation was made by all
|
||||||
|
* // three tasks, so there is no need to test the return value.
|
||||||
|
* }
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* void vTask2( void *pvParameters )
|
||||||
|
* {
|
||||||
|
* for( ;; )
|
||||||
|
* {
|
||||||
|
* // Perform task functionality here.
|
||||||
|
*
|
||||||
|
* // Set bit 2 in the event flag to note this task has reached the
|
||||||
|
* // synchronisation point. The other two tasks will set the other two
|
||||||
|
* // bits defined by ALL_SYNC_BITS. All three tasks have reached the
|
||||||
|
* // synchronisation point when all the ALL_SYNC_BITS are set. Wait
|
||||||
|
* // indefinitely for this to happen.
|
||||||
|
* xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );
|
||||||
|
*
|
||||||
|
* // xEventGroupSync() was called with an indefinite block time, so
|
||||||
|
* // this task will only reach here if the synchronisation was made by all
|
||||||
|
* // three tasks, so there is no need to test the return value.
|
||||||
|
* }
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* @endcode
|
||||||
|
* \defgroup xEventGroupSync xEventGroupSync
|
||||||
|
* \ingroup EventGroup
|
||||||
|
*/
|
||||||
|
EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,
|
||||||
|
const EventBits_t uxBitsToSet,
|
||||||
|
const EventBits_t uxBitsToWaitFor,
|
||||||
|
TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* event_groups.h
|
||||||
|
* @code{c}
|
||||||
|
* EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Returns the current value of the bits in an event group. This function
|
||||||
|
* cannot be used from an interrupt.
|
||||||
|
*
|
||||||
|
* @param xEventGroup The event group being queried.
|
||||||
|
*
|
||||||
|
* @return The event group bits at the time xEventGroupGetBits() was called.
|
||||||
|
*
|
||||||
|
* \defgroup xEventGroupGetBits xEventGroupGetBits
|
||||||
|
* \ingroup EventGroup
|
||||||
|
*/
|
||||||
|
#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* event_groups.h
|
||||||
|
* @code{c}
|
||||||
|
* EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* A version of xEventGroupGetBits() that can be called from an ISR.
|
||||||
|
*
|
||||||
|
* @param xEventGroup The event group being queried.
|
||||||
|
*
|
||||||
|
* @return The event group bits at the time xEventGroupGetBitsFromISR() was called.
|
||||||
|
*
|
||||||
|
* \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR
|
||||||
|
* \ingroup EventGroup
|
||||||
|
*/
|
||||||
|
EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* event_groups.h
|
||||||
|
* @code{c}
|
||||||
|
* void xEventGroupDelete( EventGroupHandle_t xEventGroup );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Delete an event group that was previously created by a call to
|
||||||
|
* xEventGroupCreate(). Tasks that are blocked on the event group will be
|
||||||
|
* unblocked and obtain 0 as the event group's value.
|
||||||
|
*
|
||||||
|
* @param xEventGroup The event group being deleted.
|
||||||
|
*/
|
||||||
|
void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/* For internal use only. */
|
||||||
|
void vEventGroupSetBitsCallback( void * pvEventGroup,
|
||||||
|
const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION;
|
||||||
|
void vEventGroupClearBitsCallback( void * pvEventGroup,
|
||||||
|
const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
|
||||||
|
#if ( configUSE_TRACE_FACILITY == 1 )
|
||||||
|
UBaseType_t uxEventGroupGetNumber( void * xEventGroup ) PRIVILEGED_FUNCTION;
|
||||||
|
void vEventGroupSetNumber( void * xEventGroup,
|
||||||
|
UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* *INDENT-OFF* */
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
/* *INDENT-ON* */
|
||||||
|
|
||||||
|
#endif /* EVENT_GROUPS_H */
|
||||||
499
FreeRTOS/include/list.h
Normal file
499
FreeRTOS/include/list.h
Normal file
@@ -0,0 +1,499 @@
|
|||||||
|
/*
|
||||||
|
* FreeRTOS Kernel V10.4.6
|
||||||
|
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: MIT
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* https://www.FreeRTOS.org
|
||||||
|
* https://github.com/FreeRTOS
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This is the list implementation used by the scheduler. While it is tailored
|
||||||
|
* heavily for the schedulers needs, it is also available for use by
|
||||||
|
* application code.
|
||||||
|
*
|
||||||
|
* list_ts can only store pointers to list_item_ts. Each ListItem_t contains a
|
||||||
|
* numeric value (xItemValue). Most of the time the lists are sorted in
|
||||||
|
* ascending item value order.
|
||||||
|
*
|
||||||
|
* Lists are created already containing one list item. The value of this
|
||||||
|
* item is the maximum possible that can be stored, it is therefore always at
|
||||||
|
* the end of the list and acts as a marker. The list member pxHead always
|
||||||
|
* points to this marker - even though it is at the tail of the list. This
|
||||||
|
* is because the tail contains a wrap back pointer to the 1 head of
|
||||||
|
* the list.
|
||||||
|
*
|
||||||
|
* In addition to it's value, each list item contains a pointer to the next
|
||||||
|
* item in the list (pxNext), a pointer to the list it is in (pxContainer)
|
||||||
|
* and a pointer to back to the object that contains it. These later two
|
||||||
|
* pointers are included for efficiency of list manipulation. There is
|
||||||
|
* effectively a two way link between the object containing the list item and
|
||||||
|
* the list item itself.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* \page ListIntroduction List Implementation
|
||||||
|
* \ingroup FreeRTOSIntro
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef LIST_H
|
||||||
|
#define LIST_H
|
||||||
|
|
||||||
|
#ifndef INC_FREERTOS_H
|
||||||
|
#error "FreeRTOS.h must be included before list.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The list structure members are modified from within interrupts, and therefore
|
||||||
|
* by rights should be declared volatile. However, they are only modified in a
|
||||||
|
* functionally atomic way (within critical sections of with the scheduler
|
||||||
|
* suspended) and are either passed by reference into a function or indexed via
|
||||||
|
* a volatile variable. Therefore, in all use cases tested so far, the volatile
|
||||||
|
* qualifier can be omitted in order to provide a moderate performance
|
||||||
|
* improvement without adversely affecting functional behaviour. The assembly
|
||||||
|
* instructions generated by the IAR, ARM and GCC compilers when the respective
|
||||||
|
* compiler's options were set for maximum optimisation has been inspected and
|
||||||
|
* deemed to be as intended. That said, as compiler technology advances, and
|
||||||
|
* especially if aggressive cross module optimisation is used (a use case that
|
||||||
|
* has not been exercised to any great extend) then it is feasible that the
|
||||||
|
* volatile qualifier will be needed for correct optimisation. It is expected
|
||||||
|
* that a compiler removing essential code because, without the volatile
|
||||||
|
* qualifier on the list structure members and with aggressive cross module
|
||||||
|
* optimisation, the compiler deemed the code unnecessary will result in
|
||||||
|
* complete and obvious failure of the scheduler. If this is ever experienced
|
||||||
|
* then the volatile qualifier can be inserted in the relevant places within the
|
||||||
|
* list structures by simply defining configLIST_VOLATILE to volatile in
|
||||||
|
* FreeRTOSConfig.h (as per the example at the bottom of this comment block).
|
||||||
|
* If configLIST_VOLATILE is not defined then the preprocessor directives below
|
||||||
|
* will simply #define configLIST_VOLATILE away completely.
|
||||||
|
*
|
||||||
|
* To use volatile list structure members then add the following line to
|
||||||
|
* FreeRTOSConfig.h (without the quotes):
|
||||||
|
* "#define configLIST_VOLATILE volatile"
|
||||||
|
*/
|
||||||
|
#ifndef configLIST_VOLATILE
|
||||||
|
#define configLIST_VOLATILE
|
||||||
|
#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */
|
||||||
|
|
||||||
|
/* *INDENT-OFF* */
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
/* *INDENT-ON* */
|
||||||
|
|
||||||
|
/* Macros that can be used to place known values within the list structures,
|
||||||
|
* then check that the known values do not get corrupted during the execution of
|
||||||
|
* the application. These may catch the list data structures being overwritten in
|
||||||
|
* memory. They will not catch data errors caused by incorrect configuration or
|
||||||
|
* use of FreeRTOS.*/
|
||||||
|
#if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 )
|
||||||
|
/* Define the macros to do nothing. */
|
||||||
|
#define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE
|
||||||
|
#define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE
|
||||||
|
#define listFIRST_LIST_INTEGRITY_CHECK_VALUE
|
||||||
|
#define listSECOND_LIST_INTEGRITY_CHECK_VALUE
|
||||||
|
#define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
|
||||||
|
#define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
|
||||||
|
#define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )
|
||||||
|
#define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )
|
||||||
|
#define listTEST_LIST_ITEM_INTEGRITY( pxItem )
|
||||||
|
#define listTEST_LIST_INTEGRITY( pxList )
|
||||||
|
#else /* if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) */
|
||||||
|
/* Define macros that add new members into the list structures. */
|
||||||
|
#define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue1;
|
||||||
|
#define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue2;
|
||||||
|
#define listFIRST_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue1;
|
||||||
|
#define listSECOND_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue2;
|
||||||
|
|
||||||
|
/* Define macros that set the new structure members to known values. */
|
||||||
|
#define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
|
||||||
|
#define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
|
||||||
|
#define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) ( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
|
||||||
|
#define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) ( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
|
||||||
|
|
||||||
|
/* Define macros that will assert if one of the structure members does not
|
||||||
|
* contain its expected value. */
|
||||||
|
#define listTEST_LIST_ITEM_INTEGRITY( pxItem ) configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
|
||||||
|
#define listTEST_LIST_INTEGRITY( pxList ) configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
|
||||||
|
#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Definition of the only type of object that a list can contain.
|
||||||
|
*/
|
||||||
|
struct xLIST;
|
||||||
|
struct xLIST_ITEM
|
||||||
|
{
|
||||||
|
listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
|
||||||
|
configLIST_VOLATILE TickType_t xItemValue; /*< The value being listed. In most cases this is used to sort the list in ascending order. */
|
||||||
|
struct xLIST_ITEM * configLIST_VOLATILE pxNext; /*< Pointer to the next ListItem_t in the list. */
|
||||||
|
struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /*< Pointer to the previous ListItem_t in the list. */
|
||||||
|
void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */
|
||||||
|
struct xLIST * configLIST_VOLATILE pxContainer; /*< Pointer to the list in which this list item is placed (if any). */
|
||||||
|
listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
|
||||||
|
};
|
||||||
|
typedef struct xLIST_ITEM ListItem_t; /* For some reason lint wants this as two separate definitions. */
|
||||||
|
|
||||||
|
struct xMINI_LIST_ITEM
|
||||||
|
{
|
||||||
|
listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
|
||||||
|
configLIST_VOLATILE TickType_t xItemValue;
|
||||||
|
struct xLIST_ITEM * configLIST_VOLATILE pxNext;
|
||||||
|
struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;
|
||||||
|
};
|
||||||
|
typedef struct xMINI_LIST_ITEM MiniListItem_t;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Definition of the type of queue used by the scheduler.
|
||||||
|
*/
|
||||||
|
typedef struct xLIST
|
||||||
|
{
|
||||||
|
listFIRST_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
|
||||||
|
volatile UBaseType_t uxNumberOfItems;
|
||||||
|
ListItem_t * configLIST_VOLATILE pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */
|
||||||
|
MiniListItem_t xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */
|
||||||
|
listSECOND_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
|
||||||
|
} List_t;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Access macro to set the owner of a list item. The owner of a list item
|
||||||
|
* is the object (usually a TCB) that contains the list item.
|
||||||
|
*
|
||||||
|
* \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
|
||||||
|
* \ingroup LinkedList
|
||||||
|
*/
|
||||||
|
#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) )
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Access macro to get the owner of a list item. The owner of a list item
|
||||||
|
* is the object (usually a TCB) that contains the list item.
|
||||||
|
*
|
||||||
|
* \page listGET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
|
||||||
|
* \ingroup LinkedList
|
||||||
|
*/
|
||||||
|
#define listGET_LIST_ITEM_OWNER( pxListItem ) ( ( pxListItem )->pvOwner )
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Access macro to set the value of the list item. In most cases the value is
|
||||||
|
* used to sort the list in ascending order.
|
||||||
|
*
|
||||||
|
* \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE
|
||||||
|
* \ingroup LinkedList
|
||||||
|
*/
|
||||||
|
#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( ( pxListItem )->xItemValue = ( xValue ) )
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Access macro to retrieve the value of the list item. The value can
|
||||||
|
* represent anything - for example the priority of a task, or the time at
|
||||||
|
* which a task should be unblocked.
|
||||||
|
*
|
||||||
|
* \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
|
||||||
|
* \ingroup LinkedList
|
||||||
|
*/
|
||||||
|
#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue )
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Access macro to retrieve the value of the list item at the head of a given
|
||||||
|
* list.
|
||||||
|
*
|
||||||
|
* \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
|
||||||
|
* \ingroup LinkedList
|
||||||
|
*/
|
||||||
|
#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext->xItemValue )
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Return the list item at the head of the list.
|
||||||
|
*
|
||||||
|
* \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY
|
||||||
|
* \ingroup LinkedList
|
||||||
|
*/
|
||||||
|
#define listGET_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext )
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Return the next list item.
|
||||||
|
*
|
||||||
|
* \page listGET_NEXT listGET_NEXT
|
||||||
|
* \ingroup LinkedList
|
||||||
|
*/
|
||||||
|
#define listGET_NEXT( pxListItem ) ( ( pxListItem )->pxNext )
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Return the list item that marks the end of the list
|
||||||
|
*
|
||||||
|
* \page listGET_END_MARKER listGET_END_MARKER
|
||||||
|
* \ingroup LinkedList
|
||||||
|
*/
|
||||||
|
#define listGET_END_MARKER( pxList ) ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) )
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Access macro to determine if a list contains any items. The macro will
|
||||||
|
* only have the value 1 if the list is empty.
|
||||||
|
*
|
||||||
|
* \page listLIST_IS_EMPTY listLIST_IS_EMPTY
|
||||||
|
* \ingroup LinkedList
|
||||||
|
*/
|
||||||
|
#define listLIST_IS_EMPTY( pxList ) ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pd1 : pd0 )
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Access macro to return the number of items in the list.
|
||||||
|
*/
|
||||||
|
#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems )
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Access function to obtain the owner of the next entry in a list.
|
||||||
|
*
|
||||||
|
* The list member pxIndex is used to walk through a list. Calling
|
||||||
|
* listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list
|
||||||
|
* and returns that entry's pxOwner parameter. Using multiple calls to this
|
||||||
|
* function it is therefore possible to move through every item contained in
|
||||||
|
* a list.
|
||||||
|
*
|
||||||
|
* The pxOwner parameter of a list item is a pointer to the object that owns
|
||||||
|
* the list item. In the scheduler this is normally a task control block.
|
||||||
|
* The pxOwner parameter effectively creates a two way link between the list
|
||||||
|
* item and its owner.
|
||||||
|
*
|
||||||
|
* @param pxTCB pxTCB is set to the address of the owner of the next list item.
|
||||||
|
* @param pxList The list from which the next item owner is to be returned.
|
||||||
|
*
|
||||||
|
* \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY
|
||||||
|
* \ingroup LinkedList
|
||||||
|
*/
|
||||||
|
#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \
|
||||||
|
{ \
|
||||||
|
List_t * const pxConstList = ( pxList ); \
|
||||||
|
/* Increment the index to the next item and return the item, ensuring */ \
|
||||||
|
/* we don't return the marker used at the end of the list. */ \
|
||||||
|
( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \
|
||||||
|
if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) \
|
||||||
|
{ \
|
||||||
|
( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \
|
||||||
|
} \
|
||||||
|
( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; \
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Version of uxListRemove() that does not return a value. Provided as a slight
|
||||||
|
* optimisation for xTaskIncrementTick() by being inline.
|
||||||
|
*
|
||||||
|
* Remove an item from a list. The list item has a pointer to the list that
|
||||||
|
* it is in, so only the list item need be passed into the function.
|
||||||
|
*
|
||||||
|
* @param uxListRemove The item to be removed. The item will remove itself from
|
||||||
|
* the list pointed to by it's pxContainer parameter.
|
||||||
|
*
|
||||||
|
* @return The number of items that remain in the list after the list item has
|
||||||
|
* been removed.
|
||||||
|
*
|
||||||
|
* \page listREMOVE_ITEM listREMOVE_ITEM
|
||||||
|
* \ingroup LinkedList
|
||||||
|
*/
|
||||||
|
#define listREMOVE_ITEM( pxItemToRemove ) \
|
||||||
|
{ \
|
||||||
|
/* The list item knows which list it is in. Obtain the list from the list \
|
||||||
|
* item. */ \
|
||||||
|
List_t * const pxList = ( pxItemToRemove )->pxContainer; \
|
||||||
|
\
|
||||||
|
( pxItemToRemove )->pxNext->pxPrevious = ( pxItemToRemove )->pxPrevious; \
|
||||||
|
( pxItemToRemove )->pxPrevious->pxNext = ( pxItemToRemove )->pxNext; \
|
||||||
|
/* Make sure the index is left pointing to a valid item. */ \
|
||||||
|
if( pxList->pxIndex == ( pxItemToRemove ) ) \
|
||||||
|
{ \
|
||||||
|
pxList->pxIndex = ( pxItemToRemove )->pxPrevious; \
|
||||||
|
} \
|
||||||
|
\
|
||||||
|
( pxItemToRemove )->pxContainer = NULL; \
|
||||||
|
( pxList->uxNumberOfItems )--; \
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Inline version of vListInsertEnd() to provide slight optimisation for
|
||||||
|
* xTaskIncrementTick().
|
||||||
|
*
|
||||||
|
* Insert a list item into a list. The item will be inserted in a position
|
||||||
|
* such that it will be the last item within the list returned by multiple
|
||||||
|
* calls to listGET_OWNER_OF_NEXT_ENTRY.
|
||||||
|
*
|
||||||
|
* The list member pxIndex is used to walk through a list. Calling
|
||||||
|
* listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list.
|
||||||
|
* Placing an item in a list using vListInsertEnd effectively places the item
|
||||||
|
* in the list position pointed to by pxIndex. This means that every other
|
||||||
|
* item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before
|
||||||
|
* the pxIndex parameter again points to the item being inserted.
|
||||||
|
*
|
||||||
|
* @param pxList The list into which the item is to be inserted.
|
||||||
|
*
|
||||||
|
* @param pxNewListItem The list item to be inserted into the list.
|
||||||
|
*
|
||||||
|
* \page listINSERT_END listINSERT_END
|
||||||
|
* \ingroup LinkedList
|
||||||
|
*/
|
||||||
|
#define listINSERT_END( pxList, pxNewListItem ) \
|
||||||
|
{ \
|
||||||
|
ListItem_t * const pxIndex = ( pxList )->pxIndex; \
|
||||||
|
\
|
||||||
|
/* Only effective when configASSERT() is also defined, these tests may catch \
|
||||||
|
* the list data structures being overwritten in memory. They will not catch \
|
||||||
|
* data errors caused by incorrect configuration or use of FreeRTOS. */ \
|
||||||
|
listTEST_LIST_INTEGRITY( ( pxList ) ); \
|
||||||
|
listTEST_LIST_ITEM_INTEGRITY( ( pxNewListItem ) ); \
|
||||||
|
\
|
||||||
|
/* Insert a new list item into ( pxList ), but rather than sort the list, \
|
||||||
|
* makes the new list item the last item to be removed by a call to \
|
||||||
|
* listGET_OWNER_OF_NEXT_ENTRY(). */ \
|
||||||
|
( pxNewListItem )->pxNext = pxIndex; \
|
||||||
|
( pxNewListItem )->pxPrevious = pxIndex->pxPrevious; \
|
||||||
|
\
|
||||||
|
pxIndex->pxPrevious->pxNext = ( pxNewListItem ); \
|
||||||
|
pxIndex->pxPrevious = ( pxNewListItem ); \
|
||||||
|
\
|
||||||
|
/* Remember which list the item is in. */ \
|
||||||
|
( pxNewListItem )->pxContainer = ( pxList ); \
|
||||||
|
\
|
||||||
|
( ( pxList )->uxNumberOfItems )++; \
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Access function to obtain the owner of the first entry in a list. Lists
|
||||||
|
* are normally sorted in ascending item value order.
|
||||||
|
*
|
||||||
|
* This function returns the pxOwner member of the first item in the list.
|
||||||
|
* The pxOwner parameter of a list item is a pointer to the object that owns
|
||||||
|
* the list item. In the scheduler this is normally a task control block.
|
||||||
|
* The pxOwner parameter effectively creates a two way link between the list
|
||||||
|
* item and its owner.
|
||||||
|
*
|
||||||
|
* @param pxList The list from which the owner of the head item is to be
|
||||||
|
* returned.
|
||||||
|
*
|
||||||
|
* \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY
|
||||||
|
* \ingroup LinkedList
|
||||||
|
*/
|
||||||
|
#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( ( &( ( pxList )->xListEnd ) )->pxNext->pvOwner )
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Check to see if a list item is within a list. The list item maintains a
|
||||||
|
* "container" pointer that points to the list it is in. All this macro does
|
||||||
|
* is check to see if the container and the list match.
|
||||||
|
*
|
||||||
|
* @param pxList The list we want to know if the list item is within.
|
||||||
|
* @param pxListItem The list item we want to know if is in the list.
|
||||||
|
* @return pd1 if the list item is in the list, otherwise pd0.
|
||||||
|
*/
|
||||||
|
#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pd1 ) : ( pd0 ) )
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Return the list a list item is contained within (referenced from).
|
||||||
|
*
|
||||||
|
* @param pxListItem The list item being queried.
|
||||||
|
* @return A pointer to the List_t object that references the pxListItem
|
||||||
|
*/
|
||||||
|
#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pxContainer )
|
||||||
|
|
||||||
|
/*
|
||||||
|
* This provides a crude means of knowing if a list has been initialised, as
|
||||||
|
* pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise()
|
||||||
|
* function.
|
||||||
|
*/
|
||||||
|
#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY )
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Must be called before a list is used! This initialises all the members
|
||||||
|
* of the list structure and inserts the xListEnd item into the list as a
|
||||||
|
* marker to the back of the list.
|
||||||
|
*
|
||||||
|
* @param pxList Pointer to the list being initialised.
|
||||||
|
*
|
||||||
|
* \page vListInitialise vListInitialise
|
||||||
|
* \ingroup LinkedList
|
||||||
|
*/
|
||||||
|
void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Must be called before a list item is used. This sets the list container to
|
||||||
|
* null so the item does not think that it is already contained in a list.
|
||||||
|
*
|
||||||
|
* @param pxItem Pointer to the list item being initialised.
|
||||||
|
*
|
||||||
|
* \page vListInitialiseItem vListInitialiseItem
|
||||||
|
* \ingroup LinkedList
|
||||||
|
*/
|
||||||
|
void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Insert a list item into a list. The item will be inserted into the list in
|
||||||
|
* a position determined by its item value (ascending item value order).
|
||||||
|
*
|
||||||
|
* @param pxList The list into which the item is to be inserted.
|
||||||
|
*
|
||||||
|
* @param pxNewListItem The item that is to be placed in the list.
|
||||||
|
*
|
||||||
|
* \page vListInsert vListInsert
|
||||||
|
* \ingroup LinkedList
|
||||||
|
*/
|
||||||
|
void vListInsert( List_t * const pxList,
|
||||||
|
ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Insert a list item into a list. The item will be inserted in a position
|
||||||
|
* such that it will be the last item within the list returned by multiple
|
||||||
|
* calls to listGET_OWNER_OF_NEXT_ENTRY.
|
||||||
|
*
|
||||||
|
* The list member pxIndex is used to walk through a list. Calling
|
||||||
|
* listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list.
|
||||||
|
* Placing an item in a list using vListInsertEnd effectively places the item
|
||||||
|
* in the list position pointed to by pxIndex. This means that every other
|
||||||
|
* item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before
|
||||||
|
* the pxIndex parameter again points to the item being inserted.
|
||||||
|
*
|
||||||
|
* @param pxList The list into which the item is to be inserted.
|
||||||
|
*
|
||||||
|
* @param pxNewListItem The list item to be inserted into the list.
|
||||||
|
*
|
||||||
|
* \page vListInsertEnd vListInsertEnd
|
||||||
|
* \ingroup LinkedList
|
||||||
|
*/
|
||||||
|
void vListInsertEnd( List_t * const pxList,
|
||||||
|
ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Remove an item from a list. The list item has a pointer to the list that
|
||||||
|
* it is in, so only the list item need be passed into the function.
|
||||||
|
*
|
||||||
|
* @param uxListRemove The item to be removed. The item will remove itself from
|
||||||
|
* the list pointed to by it's pxContainer parameter.
|
||||||
|
*
|
||||||
|
* @return The number of items that remain in the list after the list item has
|
||||||
|
* been removed.
|
||||||
|
*
|
||||||
|
* \page uxListRemove uxListRemove
|
||||||
|
* \ingroup LinkedList
|
||||||
|
*/
|
||||||
|
UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/* *INDENT-OFF* */
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
/* *INDENT-ON* */
|
||||||
|
|
||||||
|
#endif /* ifndef LIST_H */
|
||||||
823
FreeRTOS/include/message_buffer.h
Normal file
823
FreeRTOS/include/message_buffer.h
Normal file
@@ -0,0 +1,823 @@
|
|||||||
|
/*
|
||||||
|
* FreeRTOS Kernel V10.4.6
|
||||||
|
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: MIT
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* https://www.FreeRTOS.org
|
||||||
|
* https://github.com/FreeRTOS
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Message buffers build functionality on top of FreeRTOS stream buffers.
|
||||||
|
* Whereas stream buffers are used to send a continuous stream of data from one
|
||||||
|
* task or interrupt to another, message buffers are used to send variable
|
||||||
|
* length discrete messages from one task or interrupt to another. Their
|
||||||
|
* implementation is light weight, making them particularly suited for interrupt
|
||||||
|
* to task and core to core communication scenarios.
|
||||||
|
*
|
||||||
|
* ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer
|
||||||
|
* implementation (so also the message buffer implementation, as message buffers
|
||||||
|
* are built on top of stream buffers) assumes there is only one task or
|
||||||
|
* interrupt that will write to the buffer (the writer), and only one task or
|
||||||
|
* interrupt that will read from the buffer (the reader). It is safe for the
|
||||||
|
* writer and reader to be different tasks or interrupts, but, unlike other
|
||||||
|
* FreeRTOS objects, it is not safe to have multiple different writers or
|
||||||
|
* multiple different readers. If there are to be multiple different writers
|
||||||
|
* then the application writer must place each call to a writing API function
|
||||||
|
* (such as xMessageBufferSend()) inside a critical section and set the send
|
||||||
|
* block time to 0. Likewise, if there are to be multiple different readers
|
||||||
|
* then the application writer must place each call to a reading API function
|
||||||
|
* (such as xMessageBufferRead()) inside a critical section and set the receive
|
||||||
|
* timeout to 0.
|
||||||
|
*
|
||||||
|
* Message buffers hold variable length messages. To enable that, when a
|
||||||
|
* message is written to the message buffer an additional sizeof( size_t ) bytes
|
||||||
|
* are also written to store the message's length (that happens internally, with
|
||||||
|
* the API function). sizeof( size_t ) is typically 4 bytes on a 32-bit
|
||||||
|
* architecture, so writing a 10 byte message to a message buffer on a 32-bit
|
||||||
|
* architecture will actually reduce the available space in the message buffer
|
||||||
|
* by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length
|
||||||
|
* of the message).
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef FREERTOS_MESSAGE_BUFFER_H
|
||||||
|
#define FREERTOS_MESSAGE_BUFFER_H
|
||||||
|
|
||||||
|
#ifndef INC_FREERTOS_H
|
||||||
|
#error "include FreeRTOS.h must appear in source files before include message_buffer.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Message buffers are built onto of stream buffers. */
|
||||||
|
#include "stream_buffer.h"
|
||||||
|
|
||||||
|
/* *INDENT-OFF* */
|
||||||
|
#if defined( __cplusplus )
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
/* *INDENT-ON* */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Type by which message buffers are referenced. For example, a call to
|
||||||
|
* xMessageBufferCreate() returns an MessageBufferHandle_t variable that can
|
||||||
|
* then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(),
|
||||||
|
* etc.
|
||||||
|
*/
|
||||||
|
typedef void * MessageBufferHandle_t;
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* message_buffer.h
|
||||||
|
*
|
||||||
|
* @code{c}
|
||||||
|
* MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Creates a new message buffer using dynamically allocated memory. See
|
||||||
|
* xMessageBufferCreateStatic() for a version that uses statically allocated
|
||||||
|
* memory (memory that is allocated at compile time).
|
||||||
|
*
|
||||||
|
* configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
|
||||||
|
* FreeRTOSConfig.h for xMessageBufferCreate() to be available.
|
||||||
|
*
|
||||||
|
* @param xBufferSizeBytes The total number of bytes (not messages) the message
|
||||||
|
* buffer will be able to hold at any one time. When a message is written to
|
||||||
|
* the message buffer an additional sizeof( size_t ) bytes are also written to
|
||||||
|
* store the message's length. sizeof( size_t ) is typically 4 bytes on a
|
||||||
|
* 32-bit architecture, so on most 32-bit architectures a 10 byte message will
|
||||||
|
* take up 14 bytes of message buffer space.
|
||||||
|
*
|
||||||
|
* @return If NULL is returned, then the message buffer cannot be created
|
||||||
|
* because there is insufficient heap memory available for FreeRTOS to allocate
|
||||||
|
* the message buffer data structures and storage area. A non-NULL value being
|
||||||
|
* returned indicates that the message buffer has been created successfully -
|
||||||
|
* the returned value should be stored as the handle to the created message
|
||||||
|
* buffer.
|
||||||
|
*
|
||||||
|
* Example use:
|
||||||
|
* @code{c}
|
||||||
|
*
|
||||||
|
* void vAFunction( void )
|
||||||
|
* {
|
||||||
|
* MessageBufferHandle_t xMessageBuffer;
|
||||||
|
* const size_t xMessageBufferSizeBytes = 100;
|
||||||
|
*
|
||||||
|
* // Create a message buffer that can hold 100 bytes. The memory used to hold
|
||||||
|
* // both the message buffer structure and the messages themselves is allocated
|
||||||
|
* // dynamically. Each message added to the buffer consumes an additional 4
|
||||||
|
* // bytes which are used to hold the lengh of the message.
|
||||||
|
* xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );
|
||||||
|
*
|
||||||
|
* if( xMessageBuffer == NULL )
|
||||||
|
* {
|
||||||
|
* // There was not enough heap memory space available to create the
|
||||||
|
* // message buffer.
|
||||||
|
* }
|
||||||
|
* else
|
||||||
|
* {
|
||||||
|
* // The message buffer was created successfully and can now be used.
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* @endcode
|
||||||
|
* \defgroup xMessageBufferCreate xMessageBufferCreate
|
||||||
|
* \ingroup MessageBufferManagement
|
||||||
|
*/
|
||||||
|
#define xMessageBufferCreate( xBufferSizeBytes ) \
|
||||||
|
( MessageBufferHandle_t ) xStreamBufferGenericCreate( xBufferSizeBytes, ( size_t ) 0, pd1 )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* message_buffer.h
|
||||||
|
*
|
||||||
|
* @code{c}
|
||||||
|
* MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
|
||||||
|
* uint8_t *pucMessageBufferStorageArea,
|
||||||
|
* StaticMessageBuffer_t *pxStaticMessageBuffer );
|
||||||
|
* @endcode
|
||||||
|
* Creates a new message buffer using statically allocated memory. See
|
||||||
|
* xMessageBufferCreate() for a version that uses dynamically allocated memory.
|
||||||
|
*
|
||||||
|
* @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
|
||||||
|
* pucMessageBufferStorageArea parameter. When a message is written to the
|
||||||
|
* message buffer an additional sizeof( size_t ) bytes are also written to store
|
||||||
|
* the message's length. sizeof( size_t ) is typically 4 bytes on a 32-bit
|
||||||
|
* architecture, so on most 32-bit architecture a 10 byte message will take up
|
||||||
|
* 14 bytes of message buffer space. The maximum number of bytes that can be
|
||||||
|
* stored in the message buffer is actually (xBufferSizeBytes - 1).
|
||||||
|
*
|
||||||
|
* @param pucMessageBufferStorageArea Must point to a uint8_t array that is at
|
||||||
|
* least xBufferSizeBytes big. This is the array to which messages are
|
||||||
|
* copied when they are written to the message buffer.
|
||||||
|
*
|
||||||
|
* @param pxStaticMessageBuffer Must point to a variable of type
|
||||||
|
* StaticMessageBuffer_t, which will be used to hold the message buffer's data
|
||||||
|
* structure.
|
||||||
|
*
|
||||||
|
* @return If the message buffer is created successfully then a handle to the
|
||||||
|
* created message buffer is returned. If either pucMessageBufferStorageArea or
|
||||||
|
* pxStaticmessageBuffer are NULL then NULL is returned.
|
||||||
|
*
|
||||||
|
* Example use:
|
||||||
|
* @code{c}
|
||||||
|
*
|
||||||
|
* // Used to dimension the array used to hold the messages. The available space
|
||||||
|
* // will actually be one less than this, so 999.
|
||||||
|
#define STORAGE_SIZE_BYTES 1000
|
||||||
|
*
|
||||||
|
* // Defines the memory that will actually hold the messages within the message
|
||||||
|
* // buffer.
|
||||||
|
* static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
|
||||||
|
*
|
||||||
|
* // The variable used to hold the message buffer structure.
|
||||||
|
* StaticMessageBuffer_t xMessageBufferStruct;
|
||||||
|
*
|
||||||
|
* void MyFunction( void )
|
||||||
|
* {
|
||||||
|
* MessageBufferHandle_t xMessageBuffer;
|
||||||
|
*
|
||||||
|
* xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucStorageBuffer ),
|
||||||
|
* ucStorageBuffer,
|
||||||
|
* &xMessageBufferStruct );
|
||||||
|
*
|
||||||
|
* // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer
|
||||||
|
* // parameters were NULL, xMessageBuffer will not be NULL, and can be used to
|
||||||
|
* // reference the created message buffer in other message buffer API calls.
|
||||||
|
*
|
||||||
|
* // Other code that uses the message buffer can go here.
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* @endcode
|
||||||
|
* \defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic
|
||||||
|
* \ingroup MessageBufferManagement
|
||||||
|
*/
|
||||||
|
#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) \
|
||||||
|
( MessageBufferHandle_t ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, 0, pd1, pucMessageBufferStorageArea, pxStaticMessageBuffer )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* message_buffer.h
|
||||||
|
*
|
||||||
|
* @code{c}
|
||||||
|
* size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
|
||||||
|
* const void *pvTxData,
|
||||||
|
* size_t xDataLengthBytes,
|
||||||
|
* TickType_t xTicksToWait );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Sends a discrete message to the message buffer. The message can be any
|
||||||
|
* length that fits within the buffer's free space, and is copied into the
|
||||||
|
* buffer.
|
||||||
|
*
|
||||||
|
* ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer
|
||||||
|
* implementation (so also the message buffer implementation, as message buffers
|
||||||
|
* are built on top of stream buffers) assumes there is only one task or
|
||||||
|
* interrupt that will write to the buffer (the writer), and only one task or
|
||||||
|
* interrupt that will read from the buffer (the reader). It is safe for the
|
||||||
|
* writer and reader to be different tasks or interrupts, but, unlike other
|
||||||
|
* FreeRTOS objects, it is not safe to have multiple different writers or
|
||||||
|
* multiple different readers. If there are to be multiple different writers
|
||||||
|
* then the application writer must place each call to a writing API function
|
||||||
|
* (such as xMessageBufferSend()) inside a critical section and set the send
|
||||||
|
* block time to 0. Likewise, if there are to be multiple different readers
|
||||||
|
* then the application writer must place each call to a reading API function
|
||||||
|
* (such as xMessageBufferRead()) inside a critical section and set the receive
|
||||||
|
* block time to 0.
|
||||||
|
*
|
||||||
|
* Use xMessageBufferSend() to write to a message buffer from a task. Use
|
||||||
|
* xMessageBufferSendFromISR() to write to a message buffer from an interrupt
|
||||||
|
* service routine (ISR).
|
||||||
|
*
|
||||||
|
* @param xMessageBuffer The handle of the message buffer to which a message is
|
||||||
|
* being sent.
|
||||||
|
*
|
||||||
|
* @param pvTxData A pointer to the message that is to be copied into the
|
||||||
|
* message buffer.
|
||||||
|
*
|
||||||
|
* @param xDataLengthBytes The length of the message. That is, the number of
|
||||||
|
* bytes to copy from pvTxData into the message buffer. When a message is
|
||||||
|
* written to the message buffer an additional sizeof( size_t ) bytes are also
|
||||||
|
* written to store the message's length. sizeof( size_t ) is typically 4 bytes
|
||||||
|
* on a 32-bit architecture, so on most 32-bit architecture setting
|
||||||
|
* xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
|
||||||
|
* bytes (20 bytes of message data and 4 bytes to hold the message length).
|
||||||
|
*
|
||||||
|
* @param xTicksToWait The maximum amount of time the calling task should remain
|
||||||
|
* in the Blocked state to wait for enough space to become available in the
|
||||||
|
* message buffer, should the message buffer have insufficient space when
|
||||||
|
* xMessageBufferSend() is called. The calling task will never block if
|
||||||
|
* xTicksToWait is zero. The block time is specified in tick periods, so the
|
||||||
|
* absolute time it represents is dependent on the tick frequency. The macro
|
||||||
|
* pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into
|
||||||
|
* a time specified in ticks. Setting xTicksToWait to portMAX_DELAY will cause
|
||||||
|
* the task to wait indefinitely (without timing out), provided
|
||||||
|
* INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h. Tasks do not use any
|
||||||
|
* CPU time when they are in the Blocked state.
|
||||||
|
*
|
||||||
|
* @return The number of bytes written to the message buffer. If the call to
|
||||||
|
* xMessageBufferSend() times out before there was enough space to write the
|
||||||
|
* message into the message buffer then zero is returned. If the call did not
|
||||||
|
* time out then xDataLengthBytes is returned.
|
||||||
|
*
|
||||||
|
* Example use:
|
||||||
|
* @code{c}
|
||||||
|
* void vAFunction( MessageBufferHandle_t xMessageBuffer )
|
||||||
|
* {
|
||||||
|
* size_t xBytesSent;
|
||||||
|
* uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
|
||||||
|
* char *pcStringToSend = "String to send";
|
||||||
|
* const TickType_t x100ms = pdMS_TO_TICKS( 100 );
|
||||||
|
*
|
||||||
|
* // Send an array to the message buffer, blocking for a maximum of 100ms to
|
||||||
|
* // wait for enough space to be available in the message buffer.
|
||||||
|
* xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
|
||||||
|
*
|
||||||
|
* if( xBytesSent != sizeof( ucArrayToSend ) )
|
||||||
|
* {
|
||||||
|
* // The call to xMessageBufferSend() times out before there was enough
|
||||||
|
* // space in the buffer for the data to be written.
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* // Send the string to the message buffer. Return immediately if there is
|
||||||
|
* // not enough space in the buffer.
|
||||||
|
* xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
|
||||||
|
*
|
||||||
|
* if( xBytesSent != strlen( pcStringToSend ) )
|
||||||
|
* {
|
||||||
|
* // The string could not be added to the message buffer because there was
|
||||||
|
* // not enough free space in the buffer.
|
||||||
|
* }
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
* \defgroup xMessageBufferSend xMessageBufferSend
|
||||||
|
* \ingroup MessageBufferManagement
|
||||||
|
*/
|
||||||
|
#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) \
|
||||||
|
xStreamBufferSend( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* message_buffer.h
|
||||||
|
*
|
||||||
|
* @code{c}
|
||||||
|
* size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
|
||||||
|
* const void *pvTxData,
|
||||||
|
* size_t xDataLengthBytes,
|
||||||
|
* BaseType_t *pxHigherPriorityTaskWoken );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Interrupt safe version of the API function that sends a discrete message to
|
||||||
|
* the message buffer. The message can be any length that fits within the
|
||||||
|
* buffer's free space, and is copied into the buffer.
|
||||||
|
*
|
||||||
|
* ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer
|
||||||
|
* implementation (so also the message buffer implementation, as message buffers
|
||||||
|
* are built on top of stream buffers) assumes there is only one task or
|
||||||
|
* interrupt that will write to the buffer (the writer), and only one task or
|
||||||
|
* interrupt that will read from the buffer (the reader). It is safe for the
|
||||||
|
* writer and reader to be different tasks or interrupts, but, unlike other
|
||||||
|
* FreeRTOS objects, it is not safe to have multiple different writers or
|
||||||
|
* multiple different readers. If there are to be multiple different writers
|
||||||
|
* then the application writer must place each call to a writing API function
|
||||||
|
* (such as xMessageBufferSend()) inside a critical section and set the send
|
||||||
|
* block time to 0. Likewise, if there are to be multiple different readers
|
||||||
|
* then the application writer must place each call to a reading API function
|
||||||
|
* (such as xMessageBufferRead()) inside a critical section and set the receive
|
||||||
|
* block time to 0.
|
||||||
|
*
|
||||||
|
* Use xMessageBufferSend() to write to a message buffer from a task. Use
|
||||||
|
* xMessageBufferSendFromISR() to write to a message buffer from an interrupt
|
||||||
|
* service routine (ISR).
|
||||||
|
*
|
||||||
|
* @param xMessageBuffer The handle of the message buffer to which a message is
|
||||||
|
* being sent.
|
||||||
|
*
|
||||||
|
* @param pvTxData A pointer to the message that is to be copied into the
|
||||||
|
* message buffer.
|
||||||
|
*
|
||||||
|
* @param xDataLengthBytes The length of the message. That is, the number of
|
||||||
|
* bytes to copy from pvTxData into the message buffer. When a message is
|
||||||
|
* written to the message buffer an additional sizeof( size_t ) bytes are also
|
||||||
|
* written to store the message's length. sizeof( size_t ) is typically 4 bytes
|
||||||
|
* on a 32-bit architecture, so on most 32-bit architecture setting
|
||||||
|
* xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
|
||||||
|
* bytes (20 bytes of message data and 4 bytes to hold the message length).
|
||||||
|
*
|
||||||
|
* @param pxHigherPriorityTaskWoken It is possible that a message buffer will
|
||||||
|
* have a task blocked on it waiting for data. Calling
|
||||||
|
* xMessageBufferSendFromISR() can make data available, and so cause a task that
|
||||||
|
* was waiting for data to leave the Blocked state. If calling
|
||||||
|
* xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the
|
||||||
|
* unblocked task has a priority higher than the currently executing task (the
|
||||||
|
* task that was interrupted), then, internally, xMessageBufferSendFromISR()
|
||||||
|
* will set *pxHigherPriorityTaskWoken to pd1. If
|
||||||
|
* xMessageBufferSendFromISR() sets this value to pd1, then normally a
|
||||||
|
* context switch should be performed before the interrupt is exited. This will
|
||||||
|
* ensure that the interrupt returns directly to the highest priority Ready
|
||||||
|
* state task. *pxHigherPriorityTaskWoken should be set to pd0 before it
|
||||||
|
* is passed into the function. See the code example below for an example.
|
||||||
|
*
|
||||||
|
* @return The number of bytes actually written to the message buffer. If the
|
||||||
|
* message buffer didn't have enough free space for the message to be stored
|
||||||
|
* then 0 is returned, otherwise xDataLengthBytes is returned.
|
||||||
|
*
|
||||||
|
* Example use:
|
||||||
|
* @code{c}
|
||||||
|
* // A message buffer that has already been created.
|
||||||
|
* MessageBufferHandle_t xMessageBuffer;
|
||||||
|
*
|
||||||
|
* void vAnInterruptServiceRoutine( void )
|
||||||
|
* {
|
||||||
|
* size_t xBytesSent;
|
||||||
|
* char *pcStringToSend = "String to send";
|
||||||
|
* BaseType_t xHigherPriorityTaskWoken = pd0; // Initialised to pd0.
|
||||||
|
*
|
||||||
|
* // Attempt to send the string to the message buffer.
|
||||||
|
* xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,
|
||||||
|
* ( void * ) pcStringToSend,
|
||||||
|
* strlen( pcStringToSend ),
|
||||||
|
* &xHigherPriorityTaskWoken );
|
||||||
|
*
|
||||||
|
* if( xBytesSent != strlen( pcStringToSend ) )
|
||||||
|
* {
|
||||||
|
* // The string could not be added to the message buffer because there was
|
||||||
|
* // not enough free space in the buffer.
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* // If xHigherPriorityTaskWoken was set to pd1 inside
|
||||||
|
* // xMessageBufferSendFromISR() then a task that has a priority above the
|
||||||
|
* // priority of the currently executing task was unblocked and a context
|
||||||
|
* // switch should be performed to ensure the ISR returns to the unblocked
|
||||||
|
* // task. In most FreeRTOS ports this is done by simply passing
|
||||||
|
* // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
|
||||||
|
* // variables value, and perform the context switch if necessary. Check the
|
||||||
|
* // documentation for the port in use for port specific instructions.
|
||||||
|
* portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
* \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR
|
||||||
|
* \ingroup MessageBufferManagement
|
||||||
|
*/
|
||||||
|
#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) \
|
||||||
|
xStreamBufferSendFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* message_buffer.h
|
||||||
|
*
|
||||||
|
* @code{c}
|
||||||
|
* size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
|
||||||
|
* void *pvRxData,
|
||||||
|
* size_t xBufferLengthBytes,
|
||||||
|
* TickType_t xTicksToWait );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Receives a discrete message from a message buffer. Messages can be of
|
||||||
|
* variable length and are copied out of the buffer.
|
||||||
|
*
|
||||||
|
* ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer
|
||||||
|
* implementation (so also the message buffer implementation, as message buffers
|
||||||
|
* are built on top of stream buffers) assumes there is only one task or
|
||||||
|
* interrupt that will write to the buffer (the writer), and only one task or
|
||||||
|
* interrupt that will read from the buffer (the reader). It is safe for the
|
||||||
|
* writer and reader to be different tasks or interrupts, but, unlike other
|
||||||
|
* FreeRTOS objects, it is not safe to have multiple different writers or
|
||||||
|
* multiple different readers. If there are to be multiple different writers
|
||||||
|
* then the application writer must place each call to a writing API function
|
||||||
|
* (such as xMessageBufferSend()) inside a critical section and set the send
|
||||||
|
* block time to 0. Likewise, if there are to be multiple different readers
|
||||||
|
* then the application writer must place each call to a reading API function
|
||||||
|
* (such as xMessageBufferRead()) inside a critical section and set the receive
|
||||||
|
* block time to 0.
|
||||||
|
*
|
||||||
|
* Use xMessageBufferReceive() to read from a message buffer from a task. Use
|
||||||
|
* xMessageBufferReceiveFromISR() to read from a message buffer from an
|
||||||
|
* interrupt service routine (ISR).
|
||||||
|
*
|
||||||
|
* @param xMessageBuffer The handle of the message buffer from which a message
|
||||||
|
* is being received.
|
||||||
|
*
|
||||||
|
* @param pvRxData A pointer to the buffer into which the received message is
|
||||||
|
* to be copied.
|
||||||
|
*
|
||||||
|
* @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
|
||||||
|
* parameter. This sets the maximum length of the message that can be received.
|
||||||
|
* If xBufferLengthBytes is too small to hold the next message then the message
|
||||||
|
* will be left in the message buffer and 0 will be returned.
|
||||||
|
*
|
||||||
|
* @param xTicksToWait The maximum amount of time the task should remain in the
|
||||||
|
* Blocked state to wait for a message, should the message buffer be empty.
|
||||||
|
* xMessageBufferReceive() will return immediately if xTicksToWait is zero and
|
||||||
|
* the message buffer is empty. The block time is specified in tick periods, so
|
||||||
|
* the absolute time it represents is dependent on the tick frequency. The
|
||||||
|
* macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
|
||||||
|
* into a time specified in ticks. Setting xTicksToWait to portMAX_DELAY will
|
||||||
|
* cause the task to wait indefinitely (without timing out), provided
|
||||||
|
* INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h. Tasks do not use any
|
||||||
|
* CPU time when they are in the Blocked state.
|
||||||
|
*
|
||||||
|
* @return The length, in bytes, of the message read from the message buffer, if
|
||||||
|
* any. If xMessageBufferReceive() times out before a message became available
|
||||||
|
* then zero is returned. If the length of the message is greater than
|
||||||
|
* xBufferLengthBytes then the message will be left in the message buffer and
|
||||||
|
* zero is returned.
|
||||||
|
*
|
||||||
|
* Example use:
|
||||||
|
* @code{c}
|
||||||
|
* void vAFunction( MessageBuffer_t xMessageBuffer )
|
||||||
|
* {
|
||||||
|
* uint8_t ucRxData[ 20 ];
|
||||||
|
* size_t xReceivedBytes;
|
||||||
|
* const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
|
||||||
|
*
|
||||||
|
* // Receive the next message from the message buffer. Wait in the Blocked
|
||||||
|
* // state (so not using any CPU processing time) for a maximum of 100ms for
|
||||||
|
* // a message to become available.
|
||||||
|
* xReceivedBytes = xMessageBufferReceive( xMessageBuffer,
|
||||||
|
* ( void * ) ucRxData,
|
||||||
|
* sizeof( ucRxData ),
|
||||||
|
* xBlockTime );
|
||||||
|
*
|
||||||
|
* if( xReceivedBytes > 0 )
|
||||||
|
* {
|
||||||
|
* // A ucRxData contains a message that is xReceivedBytes long. Process
|
||||||
|
* // the message here....
|
||||||
|
* }
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
* \defgroup xMessageBufferReceive xMessageBufferReceive
|
||||||
|
* \ingroup MessageBufferManagement
|
||||||
|
*/
|
||||||
|
#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) \
|
||||||
|
xStreamBufferReceive( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait )
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* message_buffer.h
|
||||||
|
*
|
||||||
|
* @code{c}
|
||||||
|
* size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
|
||||||
|
* void *pvRxData,
|
||||||
|
* size_t xBufferLengthBytes,
|
||||||
|
* BaseType_t *pxHigherPriorityTaskWoken );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* An interrupt safe version of the API function that receives a discrete
|
||||||
|
* message from a message buffer. Messages can be of variable length and are
|
||||||
|
* copied out of the buffer.
|
||||||
|
*
|
||||||
|
* ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer
|
||||||
|
* implementation (so also the message buffer implementation, as message buffers
|
||||||
|
* are built on top of stream buffers) assumes there is only one task or
|
||||||
|
* interrupt that will write to the buffer (the writer), and only one task or
|
||||||
|
* interrupt that will read from the buffer (the reader). It is safe for the
|
||||||
|
* writer and reader to be different tasks or interrupts, but, unlike other
|
||||||
|
* FreeRTOS objects, it is not safe to have multiple different writers or
|
||||||
|
* multiple different readers. If there are to be multiple different writers
|
||||||
|
* then the application writer must place each call to a writing API function
|
||||||
|
* (such as xMessageBufferSend()) inside a critical section and set the send
|
||||||
|
* block time to 0. Likewise, if there are to be multiple different readers
|
||||||
|
* then the application writer must place each call to a reading API function
|
||||||
|
* (such as xMessageBufferRead()) inside a critical section and set the receive
|
||||||
|
* block time to 0.
|
||||||
|
*
|
||||||
|
* Use xMessageBufferReceive() to read from a message buffer from a task. Use
|
||||||
|
* xMessageBufferReceiveFromISR() to read from a message buffer from an
|
||||||
|
* interrupt service routine (ISR).
|
||||||
|
*
|
||||||
|
* @param xMessageBuffer The handle of the message buffer from which a message
|
||||||
|
* is being received.
|
||||||
|
*
|
||||||
|
* @param pvRxData A pointer to the buffer into which the received message is
|
||||||
|
* to be copied.
|
||||||
|
*
|
||||||
|
* @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
|
||||||
|
* parameter. This sets the maximum length of the message that can be received.
|
||||||
|
* If xBufferLengthBytes is too small to hold the next message then the message
|
||||||
|
* will be left in the message buffer and 0 will be returned.
|
||||||
|
*
|
||||||
|
* @param pxHigherPriorityTaskWoken It is possible that a message buffer will
|
||||||
|
* have a task blocked on it waiting for space to become available. Calling
|
||||||
|
* xMessageBufferReceiveFromISR() can make space available, and so cause a task
|
||||||
|
* that is waiting for space to leave the Blocked state. If calling
|
||||||
|
* xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and
|
||||||
|
* the unblocked task has a priority higher than the currently executing task
|
||||||
|
* (the task that was interrupted), then, internally,
|
||||||
|
* xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pd1.
|
||||||
|
* If xMessageBufferReceiveFromISR() sets this value to pd1, then normally a
|
||||||
|
* context switch should be performed before the interrupt is exited. That will
|
||||||
|
* ensure the interrupt returns directly to the highest priority Ready state
|
||||||
|
* task. *pxHigherPriorityTaskWoken should be set to pd0 before it is
|
||||||
|
* passed into the function. See the code example below for an example.
|
||||||
|
*
|
||||||
|
* @return The length, in bytes, of the message read from the message buffer, if
|
||||||
|
* any.
|
||||||
|
*
|
||||||
|
* Example use:
|
||||||
|
* @code{c}
|
||||||
|
* // A message buffer that has already been created.
|
||||||
|
* MessageBuffer_t xMessageBuffer;
|
||||||
|
*
|
||||||
|
* void vAnInterruptServiceRoutine( void )
|
||||||
|
* {
|
||||||
|
* uint8_t ucRxData[ 20 ];
|
||||||
|
* size_t xReceivedBytes;
|
||||||
|
* BaseType_t xHigherPriorityTaskWoken = pd0; // Initialised to pd0.
|
||||||
|
*
|
||||||
|
* // Receive the next message from the message buffer.
|
||||||
|
* xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,
|
||||||
|
* ( void * ) ucRxData,
|
||||||
|
* sizeof( ucRxData ),
|
||||||
|
* &xHigherPriorityTaskWoken );
|
||||||
|
*
|
||||||
|
* if( xReceivedBytes > 0 )
|
||||||
|
* {
|
||||||
|
* // A ucRxData contains a message that is xReceivedBytes long. Process
|
||||||
|
* // the message here....
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* // If xHigherPriorityTaskWoken was set to pd1 inside
|
||||||
|
* // xMessageBufferReceiveFromISR() then a task that has a priority above the
|
||||||
|
* // priority of the currently executing task was unblocked and a context
|
||||||
|
* // switch should be performed to ensure the ISR returns to the unblocked
|
||||||
|
* // task. In most FreeRTOS ports this is done by simply passing
|
||||||
|
* // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
|
||||||
|
* // variables value, and perform the context switch if necessary. Check the
|
||||||
|
* // documentation for the port in use for port specific instructions.
|
||||||
|
* portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
* \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR
|
||||||
|
* \ingroup MessageBufferManagement
|
||||||
|
*/
|
||||||
|
#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) \
|
||||||
|
xStreamBufferReceiveFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* message_buffer.h
|
||||||
|
*
|
||||||
|
* @code{c}
|
||||||
|
* void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Deletes a message buffer that was previously created using a call to
|
||||||
|
* xMessageBufferCreate() or xMessageBufferCreateStatic(). If the message
|
||||||
|
* buffer was created using dynamic memory (that is, by xMessageBufferCreate()),
|
||||||
|
* then the allocated memory is freed.
|
||||||
|
*
|
||||||
|
* A message buffer handle must not be used after the message buffer has been
|
||||||
|
* deleted.
|
||||||
|
*
|
||||||
|
* @param xMessageBuffer The handle of the message buffer to be deleted.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define vMessageBufferDelete( xMessageBuffer ) \
|
||||||
|
vStreamBufferDelete( ( StreamBufferHandle_t ) xMessageBuffer )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* message_buffer.h
|
||||||
|
* @code{c}
|
||||||
|
* BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Tests to see if a message buffer is full. A message buffer is full if it
|
||||||
|
* cannot accept any more messages, of any size, until space is made available
|
||||||
|
* by a message being removed from the message buffer.
|
||||||
|
*
|
||||||
|
* @param xMessageBuffer The handle of the message buffer being queried.
|
||||||
|
*
|
||||||
|
* @return If the message buffer referenced by xMessageBuffer is full then
|
||||||
|
* pd1 is returned. Otherwise pd0 is returned.
|
||||||
|
*/
|
||||||
|
#define xMessageBufferIsFull( xMessageBuffer ) \
|
||||||
|
xStreamBufferIsFull( ( StreamBufferHandle_t ) xMessageBuffer )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* message_buffer.h
|
||||||
|
* @code{c}
|
||||||
|
* BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Tests to see if a message buffer is empty (does not contain any messages).
|
||||||
|
*
|
||||||
|
* @param xMessageBuffer The handle of the message buffer being queried.
|
||||||
|
*
|
||||||
|
* @return If the message buffer referenced by xMessageBuffer is empty then
|
||||||
|
* pd1 is returned. Otherwise pd0 is returned.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define xMessageBufferIsEmpty( xMessageBuffer ) \
|
||||||
|
xStreamBufferIsEmpty( ( StreamBufferHandle_t ) xMessageBuffer )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* message_buffer.h
|
||||||
|
* @code{c}
|
||||||
|
* BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Resets a message buffer to its initial empty state, discarding any message it
|
||||||
|
* contained.
|
||||||
|
*
|
||||||
|
* A message buffer can only be reset if there are no tasks blocked on it.
|
||||||
|
*
|
||||||
|
* @param xMessageBuffer The handle of the message buffer being reset.
|
||||||
|
*
|
||||||
|
* @return If the message buffer was reset then pdPASS is returned. If the
|
||||||
|
* message buffer could not be reset because either there was a task blocked on
|
||||||
|
* the message queue to wait for space to become available, or to wait for a
|
||||||
|
* a message to be available, then pdFAIL is returned.
|
||||||
|
*
|
||||||
|
* \defgroup xMessageBufferReset xMessageBufferReset
|
||||||
|
* \ingroup MessageBufferManagement
|
||||||
|
*/
|
||||||
|
#define xMessageBufferReset( xMessageBuffer ) \
|
||||||
|
xStreamBufferReset( ( StreamBufferHandle_t ) xMessageBuffer )
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* message_buffer.h
|
||||||
|
* @code{c}
|
||||||
|
* size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer );
|
||||||
|
* @endcode
|
||||||
|
* Returns the number of bytes of free space in the message buffer.
|
||||||
|
*
|
||||||
|
* @param xMessageBuffer The handle of the message buffer being queried.
|
||||||
|
*
|
||||||
|
* @return The number of bytes that can be written to the message buffer before
|
||||||
|
* the message buffer would be full. When a message is written to the message
|
||||||
|
* buffer an additional sizeof( size_t ) bytes are also written to store the
|
||||||
|
* message's length. sizeof( size_t ) is typically 4 bytes on a 32-bit
|
||||||
|
* architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size
|
||||||
|
* of the largest message that can be written to the message buffer is 6 bytes.
|
||||||
|
*
|
||||||
|
* \defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable
|
||||||
|
* \ingroup MessageBufferManagement
|
||||||
|
*/
|
||||||
|
#define xMessageBufferSpaceAvailable( xMessageBuffer ) \
|
||||||
|
xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer )
|
||||||
|
#define xMessageBufferSpacesAvailable( xMessageBuffer ) \
|
||||||
|
xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) /* Corrects typo in original macro name. */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* message_buffer.h
|
||||||
|
* @code{c}
|
||||||
|
* size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer );
|
||||||
|
* @endcode
|
||||||
|
* Returns the length (in bytes) of the next message in a message buffer.
|
||||||
|
* Useful if xMessageBufferReceive() returned 0 because the size of the buffer
|
||||||
|
* passed into xMessageBufferReceive() was too small to hold the next message.
|
||||||
|
*
|
||||||
|
* @param xMessageBuffer The handle of the message buffer being queried.
|
||||||
|
*
|
||||||
|
* @return The length (in bytes) of the next message in the message buffer, or 0
|
||||||
|
* if the message buffer is empty.
|
||||||
|
*
|
||||||
|
* \defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes
|
||||||
|
* \ingroup MessageBufferManagement
|
||||||
|
*/
|
||||||
|
#define xMessageBufferNextLengthBytes( xMessageBuffer ) \
|
||||||
|
xStreamBufferNextMessageLengthBytes( ( StreamBufferHandle_t ) xMessageBuffer ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* message_buffer.h
|
||||||
|
*
|
||||||
|
* @code{c}
|
||||||
|
* BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xMessageBuffer, BaseType_t *pxHigherPriorityTaskWoken );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* For advanced users only.
|
||||||
|
*
|
||||||
|
* The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
|
||||||
|
* data is sent to a message buffer or stream buffer. If there was a task that
|
||||||
|
* was blocked on the message or stream buffer waiting for data to arrive then
|
||||||
|
* the sbSEND_COMPLETED() macro sends a notification to the task to remove it
|
||||||
|
* from the Blocked state. xMessageBufferSendCompletedFromISR() does the same
|
||||||
|
* thing. It is provided to enable application writers to implement their own
|
||||||
|
* version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
|
||||||
|
*
|
||||||
|
* See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
|
||||||
|
* additional information.
|
||||||
|
*
|
||||||
|
* @param xMessageBuffer The handle of the stream buffer to which data was
|
||||||
|
* written.
|
||||||
|
*
|
||||||
|
* @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
|
||||||
|
* initialised to pd0 before it is passed into
|
||||||
|
* xMessageBufferSendCompletedFromISR(). If calling
|
||||||
|
* xMessageBufferSendCompletedFromISR() removes a task from the Blocked state,
|
||||||
|
* and the task has a priority above the priority of the currently running task,
|
||||||
|
* then *pxHigherPriorityTaskWoken will get set to pd1 indicating that a
|
||||||
|
* context switch should be performed before exiting the ISR.
|
||||||
|
*
|
||||||
|
* @return If a task was removed from the Blocked state then pd1 is returned.
|
||||||
|
* Otherwise pd0 is returned.
|
||||||
|
*
|
||||||
|
* \defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR
|
||||||
|
* \ingroup StreamBufferManagement
|
||||||
|
*/
|
||||||
|
#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) \
|
||||||
|
xStreamBufferSendCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* message_buffer.h
|
||||||
|
*
|
||||||
|
* @code{c}
|
||||||
|
* BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xMessageBuffer, BaseType_t *pxHigherPriorityTaskWoken );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* For advanced users only.
|
||||||
|
*
|
||||||
|
* The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
|
||||||
|
* data is read out of a message buffer or stream buffer. If there was a task
|
||||||
|
* that was blocked on the message or stream buffer waiting for data to arrive
|
||||||
|
* then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
|
||||||
|
* remove it from the Blocked state. xMessageBufferReceiveCompletedFromISR()
|
||||||
|
* does the same thing. It is provided to enable application writers to
|
||||||
|
* implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
|
||||||
|
* ANY OTHER TIME.
|
||||||
|
*
|
||||||
|
* See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
|
||||||
|
* additional information.
|
||||||
|
*
|
||||||
|
* @param xMessageBuffer The handle of the stream buffer from which data was
|
||||||
|
* read.
|
||||||
|
*
|
||||||
|
* @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
|
||||||
|
* initialised to pd0 before it is passed into
|
||||||
|
* xMessageBufferReceiveCompletedFromISR(). If calling
|
||||||
|
* xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state,
|
||||||
|
* and the task has a priority above the priority of the currently running task,
|
||||||
|
* then *pxHigherPriorityTaskWoken will get set to pd1 indicating that a
|
||||||
|
* context switch should be performed before exiting the ISR.
|
||||||
|
*
|
||||||
|
* @return If a task was removed from the Blocked state then pd1 is returned.
|
||||||
|
* Otherwise pd0 is returned.
|
||||||
|
*
|
||||||
|
* \defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR
|
||||||
|
* \ingroup StreamBufferManagement
|
||||||
|
*/
|
||||||
|
#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) \
|
||||||
|
xStreamBufferReceiveCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
|
||||||
|
|
||||||
|
/* *INDENT-OFF* */
|
||||||
|
#if defined( __cplusplus )
|
||||||
|
} /* extern "C" */
|
||||||
|
#endif
|
||||||
|
/* *INDENT-ON* */
|
||||||
|
|
||||||
|
#endif /* !defined( FREERTOS_MESSAGE_BUFFER_H ) */
|
||||||
260
FreeRTOS/include/mpu_prototypes.h
Normal file
260
FreeRTOS/include/mpu_prototypes.h
Normal file
@@ -0,0 +1,260 @@
|
|||||||
|
/*
|
||||||
|
* FreeRTOS Kernel V10.4.6
|
||||||
|
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: MIT
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* https://www.FreeRTOS.org
|
||||||
|
* https://github.com/FreeRTOS
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* When the MPU is used the standard (non MPU) API functions are mapped to
|
||||||
|
* equivalents that start "MPU_", the prototypes for which are defined in this
|
||||||
|
* header files. This will cause the application code to call the MPU_ version
|
||||||
|
* which wraps the non-MPU version with privilege promoting then demoting code,
|
||||||
|
* so the kernel code always runs will full privileges.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef MPU_PROTOTYPES_H
|
||||||
|
#define MPU_PROTOTYPES_H
|
||||||
|
|
||||||
|
/* MPU versions of tasks.h API functions. */
|
||||||
|
BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode,
|
||||||
|
const char * const pcName,
|
||||||
|
const uint16_t usStackDepth,
|
||||||
|
void * const pvParameters,
|
||||||
|
UBaseType_t uxPriority,
|
||||||
|
TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL;
|
||||||
|
TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode,
|
||||||
|
const char * const pcName,
|
||||||
|
const uint32_t ulStackDepth,
|
||||||
|
void * const pvParameters,
|
||||||
|
UBaseType_t uxPriority,
|
||||||
|
StackType_t * const puxStackBuffer,
|
||||||
|
StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL;
|
||||||
|
void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL;
|
||||||
|
void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
|
||||||
|
const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
|
||||||
|
UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
|
||||||
|
eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
|
||||||
|
void MPU_vTaskGetInfo( TaskHandle_t xTask,
|
||||||
|
TaskStatus_t * pxTaskStatus,
|
||||||
|
BaseType_t xGetFreeStackSpace,
|
||||||
|
eTaskState eState ) FREERTOS_SYSTEM_CALL;
|
||||||
|
void MPU_vTaskPrioritySet( TaskHandle_t xTask,
|
||||||
|
UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;
|
||||||
|
void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;
|
||||||
|
void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
|
||||||
|
void MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL;
|
||||||
|
void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL;
|
||||||
|
TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
|
||||||
|
UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
|
||||||
|
char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;
|
||||||
|
TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) FREERTOS_SYSTEM_CALL;
|
||||||
|
UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
|
||||||
|
configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
|
||||||
|
void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
|
||||||
|
TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;
|
||||||
|
TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
|
||||||
|
void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
|
||||||
|
BaseType_t xIndex,
|
||||||
|
void * pvValue ) FREERTOS_SYSTEM_CALL;
|
||||||
|
void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
|
||||||
|
BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask,
|
||||||
|
void * pvParameter ) FREERTOS_SYSTEM_CALL;
|
||||||
|
TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;
|
||||||
|
UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
|
||||||
|
const UBaseType_t uxArraySize,
|
||||||
|
configRUN_TIME_COUNTER_TYPE * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;
|
||||||
|
configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;
|
||||||
|
configRUN_TIME_COUNTER_TYPE MPU_ulTaskGetIdleRunTimePercent( void ) FREERTOS_SYSTEM_CALL;
|
||||||
|
void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
|
||||||
|
void MPU_vTaskGetRunTimeStats( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
|
||||||
|
UBaseType_t uxIndexToNotify,
|
||||||
|
uint32_t ulValue,
|
||||||
|
eNotifyAction eAction,
|
||||||
|
uint32_t * pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
|
||||||
|
uint32_t ulBitsToClearOnEntry,
|
||||||
|
uint32_t ulBitsToClearOnExit,
|
||||||
|
uint32_t * pulNotificationValue,
|
||||||
|
TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
|
||||||
|
uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
|
||||||
|
BaseType_t xClearCountOnExit,
|
||||||
|
TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
|
||||||
|
UBaseType_t uxIndexToClear ) FREERTOS_SYSTEM_CALL;
|
||||||
|
uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
|
||||||
|
UBaseType_t uxIndexToClear,
|
||||||
|
uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL;
|
||||||
|
TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;
|
||||||
|
void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
|
||||||
|
TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;
|
||||||
|
void MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) FREERTOS_SYSTEM_CALL;
|
||||||
|
|
||||||
|
/* MPU versions of queue.h API functions. */
|
||||||
|
BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
|
||||||
|
const void * const pvItemToQueue,
|
||||||
|
TickType_t xTicksToWait,
|
||||||
|
const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
|
||||||
|
void * const pvBuffer,
|
||||||
|
TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
|
||||||
|
void * const pvBuffer,
|
||||||
|
TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
|
||||||
|
TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
|
||||||
|
UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
|
||||||
|
UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
|
||||||
|
void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
|
||||||
|
QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
|
||||||
|
QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType,
|
||||||
|
StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL;
|
||||||
|
QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
|
||||||
|
const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL;
|
||||||
|
QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
|
||||||
|
const UBaseType_t uxInitialCount,
|
||||||
|
StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL;
|
||||||
|
TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
|
||||||
|
TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;
|
||||||
|
void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
|
||||||
|
const char * pcName ) FREERTOS_SYSTEM_CALL;
|
||||||
|
void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
|
||||||
|
const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
|
||||||
|
QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength,
|
||||||
|
const UBaseType_t uxItemSize,
|
||||||
|
const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
|
||||||
|
QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,
|
||||||
|
const UBaseType_t uxItemSize,
|
||||||
|
uint8_t * pucQueueStorage,
|
||||||
|
StaticQueue_t * pxStaticQueue,
|
||||||
|
const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
|
||||||
|
QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
|
||||||
|
QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
|
||||||
|
QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
|
||||||
|
QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
|
||||||
|
const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue,
|
||||||
|
BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL;
|
||||||
|
void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue,
|
||||||
|
UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL;
|
||||||
|
UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
|
||||||
|
uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
|
||||||
|
|
||||||
|
/* MPU versions of timers.h API functions. */
|
||||||
|
TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName,
|
||||||
|
const TickType_t xTimerPeriodInTicks,
|
||||||
|
const UBaseType_t uxAutoReload,
|
||||||
|
void * const pvTimerID,
|
||||||
|
TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL;
|
||||||
|
TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName,
|
||||||
|
const TickType_t xTimerPeriodInTicks,
|
||||||
|
const UBaseType_t uxAutoReload,
|
||||||
|
void * const pvTimerID,
|
||||||
|
TimerCallbackFunction_t pxCallbackFunction,
|
||||||
|
StaticTimer_t * pxTimerBuffer ) FREERTOS_SYSTEM_CALL;
|
||||||
|
void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
|
||||||
|
void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
|
||||||
|
void * pvNewID ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
|
||||||
|
TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
|
||||||
|
void * pvParameter1,
|
||||||
|
uint32_t ulParameter2,
|
||||||
|
TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
|
||||||
|
const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
|
||||||
|
void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
|
||||||
|
const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
|
||||||
|
UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
|
||||||
|
TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
|
||||||
|
TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
|
||||||
|
const BaseType_t xCommandID,
|
||||||
|
const TickType_t xOptionalValue,
|
||||||
|
BaseType_t * const pxHigherPriorityTaskWoken,
|
||||||
|
const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
|
||||||
|
|
||||||
|
/* MPU versions of event_group.h API functions. */
|
||||||
|
EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL;
|
||||||
|
EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL;
|
||||||
|
EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
|
||||||
|
const EventBits_t uxBitsToWaitFor,
|
||||||
|
const BaseType_t xClearOnExit,
|
||||||
|
const BaseType_t xWaitForAllBits,
|
||||||
|
TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
|
||||||
|
EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
|
||||||
|
const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
|
||||||
|
EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
|
||||||
|
const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
|
||||||
|
EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
|
||||||
|
const EventBits_t uxBitsToSet,
|
||||||
|
const EventBits_t uxBitsToWaitFor,
|
||||||
|
TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
|
||||||
|
void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL;
|
||||||
|
UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) FREERTOS_SYSTEM_CALL;
|
||||||
|
|
||||||
|
/* MPU versions of message/stream_buffer.h API functions. */
|
||||||
|
size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
|
||||||
|
const void * pvTxData,
|
||||||
|
size_t xDataLengthBytes,
|
||||||
|
TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
|
||||||
|
size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
|
||||||
|
void * pvRxData,
|
||||||
|
size_t xBufferLengthBytes,
|
||||||
|
TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
|
||||||
|
size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
|
||||||
|
void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
|
||||||
|
size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
|
||||||
|
size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
|
||||||
|
BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
|
||||||
|
size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
|
||||||
|
StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes,
|
||||||
|
size_t xTriggerLevelBytes,
|
||||||
|
BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL;
|
||||||
|
StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
|
||||||
|
size_t xTriggerLevelBytes,
|
||||||
|
BaseType_t xIsMessageBuffer,
|
||||||
|
uint8_t * const pucStreamBufferStorageArea,
|
||||||
|
StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* MPU_PROTOTYPES_H */
|
||||||
217
FreeRTOS/include/mpu_wrappers.h
Normal file
217
FreeRTOS/include/mpu_wrappers.h
Normal file
@@ -0,0 +1,217 @@
|
|||||||
|
/*
|
||||||
|
* FreeRTOS Kernel V10.4.6
|
||||||
|
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: MIT
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* https://www.FreeRTOS.org
|
||||||
|
* https://github.com/FreeRTOS
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef MPU_WRAPPERS_H
|
||||||
|
#define MPU_WRAPPERS_H
|
||||||
|
|
||||||
|
/* This file redefines API functions to be called through a wrapper macro, but
|
||||||
|
* only for ports that are using the MPU. */
|
||||||
|
#if ( portUSING_MPU_WRAPPERS == 1 )
|
||||||
|
|
||||||
|
/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is
|
||||||
|
* included from queue.c or task.c to prevent it from having an effect within
|
||||||
|
* those files. */
|
||||||
|
#ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Map standard (non MPU) API functions to equivalents that start
|
||||||
|
* "MPU_". This will cause the application code to call the MPU_
|
||||||
|
* version, which wraps the non-MPU version with privilege promoting
|
||||||
|
* then demoting code, so the kernel code always runs will full
|
||||||
|
* privileges.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Map standard tasks.h API functions to the MPU equivalents. */
|
||||||
|
#define xTaskCreate MPU_xTaskCreate
|
||||||
|
#define xTaskCreateStatic MPU_xTaskCreateStatic
|
||||||
|
#define vTaskDelete MPU_vTaskDelete
|
||||||
|
#define vTaskDelay MPU_vTaskDelay
|
||||||
|
#define xTaskDelayUntil MPU_xTaskDelayUntil
|
||||||
|
#define xTaskAbortDelay MPU_xTaskAbortDelay
|
||||||
|
#define uxTaskPriorityGet MPU_uxTaskPriorityGet
|
||||||
|
#define eTaskGetState MPU_eTaskGetState
|
||||||
|
#define vTaskGetInfo MPU_vTaskGetInfo
|
||||||
|
#define vTaskPrioritySet MPU_vTaskPrioritySet
|
||||||
|
#define vTaskSuspend MPU_vTaskSuspend
|
||||||
|
#define vTaskResume MPU_vTaskResume
|
||||||
|
#define vTaskSuspendAll MPU_vTaskSuspendAll
|
||||||
|
#define xTaskResumeAll MPU_xTaskResumeAll
|
||||||
|
#define xTaskGetTickCount MPU_xTaskGetTickCount
|
||||||
|
#define uxTaskGetNumberOfTasks MPU_uxTaskGetNumberOfTasks
|
||||||
|
#define pcTaskGetName MPU_pcTaskGetName
|
||||||
|
#define xTaskGetHandle MPU_xTaskGetHandle
|
||||||
|
#define uxTaskGetStackHighWaterMark MPU_uxTaskGetStackHighWaterMark
|
||||||
|
#define uxTaskGetStackHighWaterMark2 MPU_uxTaskGetStackHighWaterMark2
|
||||||
|
#define vTaskSetApplicationTaskTag MPU_vTaskSetApplicationTaskTag
|
||||||
|
#define xTaskGetApplicationTaskTag MPU_xTaskGetApplicationTaskTag
|
||||||
|
#define vTaskSetThreadLocalStoragePointer MPU_vTaskSetThreadLocalStoragePointer
|
||||||
|
#define pvTaskGetThreadLocalStoragePointer MPU_pvTaskGetThreadLocalStoragePointer
|
||||||
|
#define xTaskCallApplicationTaskHook MPU_xTaskCallApplicationTaskHook
|
||||||
|
#define xTaskGetIdleTaskHandle MPU_xTaskGetIdleTaskHandle
|
||||||
|
#define uxTaskGetSystemState MPU_uxTaskGetSystemState
|
||||||
|
#define vTaskList MPU_vTaskList
|
||||||
|
#define vTaskGetRunTimeStats MPU_vTaskGetRunTimeStats
|
||||||
|
#define ulTaskGetIdleRunTimeCounter MPU_ulTaskGetIdleRunTimeCounter
|
||||||
|
#define ulTaskGetIdleRunTimePercent MPU_ulTaskGetIdleRunTimePercent
|
||||||
|
#define xTaskGenericNotify MPU_xTaskGenericNotify
|
||||||
|
#define xTaskGenericNotifyWait MPU_xTaskGenericNotifyWait
|
||||||
|
#define ulTaskGenericNotifyTake MPU_ulTaskGenericNotifyTake
|
||||||
|
#define xTaskGenericNotifyStateClear MPU_xTaskGenericNotifyStateClear
|
||||||
|
#define ulTaskGenericNotifyValueClear MPU_ulTaskGenericNotifyValueClear
|
||||||
|
#define xTaskCatchUpTicks MPU_xTaskCatchUpTicks
|
||||||
|
|
||||||
|
#define xTaskGetCurrentTaskHandle MPU_xTaskGetCurrentTaskHandle
|
||||||
|
#define vTaskSetTimeOutState MPU_vTaskSetTimeOutState
|
||||||
|
#define xTaskCheckForTimeOut MPU_xTaskCheckForTimeOut
|
||||||
|
#define xTaskGetSchedulerState MPU_xTaskGetSchedulerState
|
||||||
|
|
||||||
|
/* Map standard queue.h API functions to the MPU equivalents. */
|
||||||
|
#define xQueueGenericSend MPU_xQueueGenericSend
|
||||||
|
#define xQueueReceive MPU_xQueueReceive
|
||||||
|
#define xQueuePeek MPU_xQueuePeek
|
||||||
|
#define xQueueSemaphoreTake MPU_xQueueSemaphoreTake
|
||||||
|
#define uxQueueMessagesWaiting MPU_uxQueueMessagesWaiting
|
||||||
|
#define uxQueueSpacesAvailable MPU_uxQueueSpacesAvailable
|
||||||
|
#define vQueueDelete MPU_vQueueDelete
|
||||||
|
#define xQueueCreateMutex MPU_xQueueCreateMutex
|
||||||
|
#define xQueueCreateMutexStatic MPU_xQueueCreateMutexStatic
|
||||||
|
#define xQueueCreateCountingSemaphore MPU_xQueueCreateCountingSemaphore
|
||||||
|
#define xQueueCreateCountingSemaphoreStatic MPU_xQueueCreateCountingSemaphoreStatic
|
||||||
|
#define xQueueGetMutexHolder MPU_xQueueGetMutexHolder
|
||||||
|
#define xQueueTakeMutexRecursive MPU_xQueueTakeMutexRecursive
|
||||||
|
#define xQueueGiveMutexRecursive MPU_xQueueGiveMutexRecursive
|
||||||
|
#define xQueueGenericCreate MPU_xQueueGenericCreate
|
||||||
|
#define xQueueGenericCreateStatic MPU_xQueueGenericCreateStatic
|
||||||
|
#define xQueueCreateSet MPU_xQueueCreateSet
|
||||||
|
#define xQueueAddToSet MPU_xQueueAddToSet
|
||||||
|
#define xQueueRemoveFromSet MPU_xQueueRemoveFromSet
|
||||||
|
#define xQueueSelectFromSet MPU_xQueueSelectFromSet
|
||||||
|
#define xQueueGenericReset MPU_xQueueGenericReset
|
||||||
|
|
||||||
|
#if ( configQUEUE_REGISTRY_SIZE > 0 )
|
||||||
|
#define vQueueAddToRegistry MPU_vQueueAddToRegistry
|
||||||
|
#define vQueueUnregisterQueue MPU_vQueueUnregisterQueue
|
||||||
|
#define pcQueueGetName MPU_pcQueueGetName
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Map standard timer.h API functions to the MPU equivalents. */
|
||||||
|
#define xTimerCreate MPU_xTimerCreate
|
||||||
|
#define xTimerCreateStatic MPU_xTimerCreateStatic
|
||||||
|
#define pvTimerGetTimerID MPU_pvTimerGetTimerID
|
||||||
|
#define vTimerSetTimerID MPU_vTimerSetTimerID
|
||||||
|
#define xTimerIsTimerActive MPU_xTimerIsTimerActive
|
||||||
|
#define xTimerGetTimerDaemonTaskHandle MPU_xTimerGetTimerDaemonTaskHandle
|
||||||
|
#define xTimerPendFunctionCall MPU_xTimerPendFunctionCall
|
||||||
|
#define pcTimerGetName MPU_pcTimerGetName
|
||||||
|
#define vTimerSetReloadMode MPU_vTimerSetReloadMode
|
||||||
|
#define uxTimerGetReloadMode MPU_uxTimerGetReloadMode
|
||||||
|
#define xTimerGetPeriod MPU_xTimerGetPeriod
|
||||||
|
#define xTimerGetExpiryTime MPU_xTimerGetExpiryTime
|
||||||
|
#define xTimerGenericCommand MPU_xTimerGenericCommand
|
||||||
|
|
||||||
|
/* Map standard event_group.h API functions to the MPU equivalents. */
|
||||||
|
#define xEventGroupCreate MPU_xEventGroupCreate
|
||||||
|
#define xEventGroupCreateStatic MPU_xEventGroupCreateStatic
|
||||||
|
#define xEventGroupWaitBits MPU_xEventGroupWaitBits
|
||||||
|
#define xEventGroupClearBits MPU_xEventGroupClearBits
|
||||||
|
#define xEventGroupSetBits MPU_xEventGroupSetBits
|
||||||
|
#define xEventGroupSync MPU_xEventGroupSync
|
||||||
|
#define vEventGroupDelete MPU_vEventGroupDelete
|
||||||
|
|
||||||
|
/* Map standard message/stream_buffer.h API functions to the MPU
|
||||||
|
* equivalents. */
|
||||||
|
#define xStreamBufferSend MPU_xStreamBufferSend
|
||||||
|
#define xStreamBufferReceive MPU_xStreamBufferReceive
|
||||||
|
#define xStreamBufferNextMessageLengthBytes MPU_xStreamBufferNextMessageLengthBytes
|
||||||
|
#define vStreamBufferDelete MPU_vStreamBufferDelete
|
||||||
|
#define xStreamBufferIsFull MPU_xStreamBufferIsFull
|
||||||
|
#define xStreamBufferIsEmpty MPU_xStreamBufferIsEmpty
|
||||||
|
#define xStreamBufferReset MPU_xStreamBufferReset
|
||||||
|
#define xStreamBufferSpacesAvailable MPU_xStreamBufferSpacesAvailable
|
||||||
|
#define xStreamBufferBytesAvailable MPU_xStreamBufferBytesAvailable
|
||||||
|
#define xStreamBufferSetTriggerLevel MPU_xStreamBufferSetTriggerLevel
|
||||||
|
#define xStreamBufferGenericCreate MPU_xStreamBufferGenericCreate
|
||||||
|
#define xStreamBufferGenericCreateStatic MPU_xStreamBufferGenericCreateStatic
|
||||||
|
|
||||||
|
|
||||||
|
/* Remove the privileged function macro, but keep the PRIVILEGED_DATA
|
||||||
|
* macro so applications can place data in privileged access sections
|
||||||
|
* (useful when using statically allocated objects). */
|
||||||
|
#define PRIVILEGED_FUNCTION
|
||||||
|
#define PRIVILEGED_DATA __attribute__( ( section( "privileged_data" ) ) )
|
||||||
|
#define FREERTOS_SYSTEM_CALL
|
||||||
|
|
||||||
|
#else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
|
||||||
|
|
||||||
|
/* Ensure API functions go in the privileged execution section. */
|
||||||
|
#define PRIVILEGED_FUNCTION __attribute__( ( section( "privileged_functions" ) ) )
|
||||||
|
#define PRIVILEGED_DATA __attribute__( ( section( "privileged_data" ) ) )
|
||||||
|
#define FREERTOS_SYSTEM_CALL __attribute__( ( section( "freertos_system_calls" ) ) )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Calls the port specific code to raise the privilege.
|
||||||
|
*
|
||||||
|
* Sets xRunningPrivileged to pd0 if privilege was raised, else sets
|
||||||
|
* it to pd1.
|
||||||
|
*/
|
||||||
|
#define xPortRaisePrivilege( xRunningPrivileged ) \
|
||||||
|
{ \
|
||||||
|
/* Check whether the processor is already privileged. */ \
|
||||||
|
xRunningPrivileged = portIS_PRIVILEGED(); \
|
||||||
|
\
|
||||||
|
/* If the processor is not already privileged, raise privilege. */ \
|
||||||
|
if( xRunningPrivileged == pd0 ) \
|
||||||
|
{ \
|
||||||
|
portRAISE_PRIVILEGE(); \
|
||||||
|
} \
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief If xRunningPrivileged is not pd1, calls the port specific
|
||||||
|
* code to reset the privilege, otherwise does nothing.
|
||||||
|
*/
|
||||||
|
#define vPortResetPrivilege( xRunningPrivileged ) \
|
||||||
|
{ \
|
||||||
|
if( xRunningPrivileged == pd0 ) \
|
||||||
|
{ \
|
||||||
|
portRESET_PRIVILEGE(); \
|
||||||
|
} \
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
|
||||||
|
|
||||||
|
#else /* portUSING_MPU_WRAPPERS */
|
||||||
|
|
||||||
|
#define PRIVILEGED_FUNCTION
|
||||||
|
#define PRIVILEGED_DATA
|
||||||
|
#define FREERTOS_SYSTEM_CALL
|
||||||
|
|
||||||
|
#endif /* portUSING_MPU_WRAPPERS */
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* MPU_WRAPPERS_H */
|
||||||
223
FreeRTOS/include/portable.h
Normal file
223
FreeRTOS/include/portable.h
Normal file
@@ -0,0 +1,223 @@
|
|||||||
|
/*
|
||||||
|
* FreeRTOS Kernel V10.4.6
|
||||||
|
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: MIT
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* https://www.FreeRTOS.org
|
||||||
|
* https://github.com/FreeRTOS
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------
|
||||||
|
* Portable layer API. Each function must be defined for each port.
|
||||||
|
*----------------------------------------------------------*/
|
||||||
|
|
||||||
|
#ifndef PORTABLE_H
|
||||||
|
#define PORTABLE_H
|
||||||
|
|
||||||
|
/* Each FreeRTOS port has a unique portmacro.h header file. Originally a
|
||||||
|
* pre-processor definition was used to ensure the pre-processor found the correct
|
||||||
|
* portmacro.h file for the port being used. That scheme was deprecated in favour
|
||||||
|
* of setting the compiler's include path such that it found the correct
|
||||||
|
* portmacro.h file - removing the need for the constant and allowing the
|
||||||
|
* portmacro.h file to be located anywhere in relation to the port being used.
|
||||||
|
* Purely for reasons of backward compatibility the old method is still valid, but
|
||||||
|
* to make it clear that new projects should not use it, support for the port
|
||||||
|
* specific constants has been moved into the deprecated_definitions.h header
|
||||||
|
* file. */
|
||||||
|
#include "deprecated_definitions.h"
|
||||||
|
|
||||||
|
/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h
|
||||||
|
* did not result in a portmacro.h header file being included - and it should be
|
||||||
|
* included here. In this case the path to the correct portmacro.h header file
|
||||||
|
* must be set in the compiler's include path. */
|
||||||
|
#ifndef portENTER_CRITICAL
|
||||||
|
#include "portmacro.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if portBYTE_ALIGNMENT == 32
|
||||||
|
#define portBYTE_ALIGNMENT_MASK ( 0x001f )
|
||||||
|
#elif portBYTE_ALIGNMENT == 16
|
||||||
|
#define portBYTE_ALIGNMENT_MASK ( 0x000f )
|
||||||
|
#elif portBYTE_ALIGNMENT == 8
|
||||||
|
#define portBYTE_ALIGNMENT_MASK ( 0x0007 )
|
||||||
|
#elif portBYTE_ALIGNMENT == 4
|
||||||
|
#define portBYTE_ALIGNMENT_MASK ( 0x0003 )
|
||||||
|
#elif portBYTE_ALIGNMENT == 2
|
||||||
|
#define portBYTE_ALIGNMENT_MASK ( 0x0001 )
|
||||||
|
#elif portBYTE_ALIGNMENT == 1
|
||||||
|
#define portBYTE_ALIGNMENT_MASK ( 0x0000 )
|
||||||
|
#else /* if portBYTE_ALIGNMENT == 32 */
|
||||||
|
#error "Invalid portBYTE_ALIGNMENT definition"
|
||||||
|
#endif /* if portBYTE_ALIGNMENT == 32 */
|
||||||
|
|
||||||
|
#ifndef portUSING_MPU_WRAPPERS
|
||||||
|
#define portUSING_MPU_WRAPPERS 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef portNUM_CONFIGURABLE_REGIONS
|
||||||
|
#define portNUM_CONFIGURABLE_REGIONS 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef portHAS_STACK_OVERFLOW_CHECKING
|
||||||
|
#define portHAS_STACK_OVERFLOW_CHECKING 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef portARCH_NAME
|
||||||
|
#define portARCH_NAME NULL
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef configSTACK_ALLOCATION_FROM_SEPARATE_HEAP
|
||||||
|
/* Defaults to 0 for backward compatibility. */
|
||||||
|
#define configSTACK_ALLOCATION_FROM_SEPARATE_HEAP 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* *INDENT-OFF* */
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
/* *INDENT-ON* */
|
||||||
|
|
||||||
|
#include "mpu_wrappers.h"
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Setup the stack of a new task so it is ready to be placed under the
|
||||||
|
* scheduler control. The registers have to be placed on the stack in
|
||||||
|
* the order that the port expects to find them.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#if ( portUSING_MPU_WRAPPERS == 1 )
|
||||||
|
#if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
|
||||||
|
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
|
||||||
|
StackType_t * pxEndOfStack,
|
||||||
|
TaskFunction_t pxCode,
|
||||||
|
void * pvParameters,
|
||||||
|
BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
|
||||||
|
#else
|
||||||
|
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
|
||||||
|
TaskFunction_t pxCode,
|
||||||
|
void * pvParameters,
|
||||||
|
BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
|
||||||
|
#endif
|
||||||
|
#else /* if ( portUSING_MPU_WRAPPERS == 1 ) */
|
||||||
|
#if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
|
||||||
|
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
|
||||||
|
StackType_t * pxEndOfStack,
|
||||||
|
TaskFunction_t pxCode,
|
||||||
|
void * pvParameters ) PRIVILEGED_FUNCTION;
|
||||||
|
#else
|
||||||
|
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
|
||||||
|
TaskFunction_t pxCode,
|
||||||
|
void * pvParameters ) PRIVILEGED_FUNCTION;
|
||||||
|
#endif
|
||||||
|
#endif /* if ( portUSING_MPU_WRAPPERS == 1 ) */
|
||||||
|
|
||||||
|
/* Used by heap_5.c to define the start address and size of each memory region
|
||||||
|
* that together comprise the total FreeRTOS heap space. */
|
||||||
|
typedef struct HeapRegion
|
||||||
|
{
|
||||||
|
uint8_t * pucStartAddress;
|
||||||
|
size_t xSizeInBytes;
|
||||||
|
} HeapRegion_t;
|
||||||
|
|
||||||
|
/* Used to pass information about the heap out of vPortGetHeapStats(). */
|
||||||
|
typedef struct xHeapStats
|
||||||
|
{
|
||||||
|
size_t xAvailableHeapSpaceInBytes; /* The total heap size currently available - this is the sum of all the free blocks, not the largest block that can be allocated. */
|
||||||
|
size_t xSizeOfLargestFreeBlockInBytes; /* The maximum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
|
||||||
|
size_t xSizeOfSmallestFreeBlockInBytes; /* The minimum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
|
||||||
|
size_t xNumberOfFreeBlocks; /* The number of free memory blocks within the heap at the time vPortGetHeapStats() is called. */
|
||||||
|
size_t xMinimumEverFreeBytesRemaining; /* The minimum amount of total free memory (sum of all free blocks) there has been in the heap since the system booted. */
|
||||||
|
size_t xNumberOfSuccessfulAllocations; /* The number of calls to pvPortMalloc() that have returned a valid memory block. */
|
||||||
|
size_t xNumberOfSuccessfulFrees; /* The number of calls to vPortFree() that has successfully freed a block of memory. */
|
||||||
|
} HeapStats_t;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Used to define multiple heap regions for use by heap_5.c. This function
|
||||||
|
* must be called before any calls to pvPortMalloc() - not creating a task,
|
||||||
|
* queue, semaphore, mutex, software timer, event group, etc. will result in
|
||||||
|
* pvPortMalloc being called.
|
||||||
|
*
|
||||||
|
* pxHeapRegions passes in an array of HeapRegion_t structures - each of which
|
||||||
|
* defines a region of memory that can be used as the heap. The array is
|
||||||
|
* terminated by a HeapRegions_t structure that has a size of 0. The region
|
||||||
|
* with the lowest start address must appear first in the array.
|
||||||
|
*/
|
||||||
|
void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Returns a HeapStats_t structure filled with information about the current
|
||||||
|
* heap state.
|
||||||
|
*/
|
||||||
|
void vPortGetHeapStats( HeapStats_t * pxHeapStats );
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Map to the memory management routines required for the port.
|
||||||
|
*/
|
||||||
|
void * pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
|
||||||
|
void vPortFree( void * pv ) PRIVILEGED_FUNCTION;
|
||||||
|
void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;
|
||||||
|
size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;
|
||||||
|
size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
#if ( configSTACK_ALLOCATION_FROM_SEPARATE_HEAP == 1 )
|
||||||
|
void * pvPortMallocStack( size_t xSize ) PRIVILEGED_FUNCTION;
|
||||||
|
void vPortFreeStack( void * pv ) PRIVILEGED_FUNCTION;
|
||||||
|
#else
|
||||||
|
#define pvPortMallocStack pvPortMalloc
|
||||||
|
#define vPortFreeStack vPortFree
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Setup the hardware ready for the scheduler to take control. This generally
|
||||||
|
* sets up a tick interrupt and sets timers for the correct tick frequency.
|
||||||
|
*/
|
||||||
|
BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Undo any hardware/ISR setup that was performed by xPortStartScheduler() so
|
||||||
|
* the hardware is left in its original condition after the scheduler stops
|
||||||
|
* executing.
|
||||||
|
*/
|
||||||
|
void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The structures and methods of manipulating the MPU are contained within the
|
||||||
|
* port layer.
|
||||||
|
*
|
||||||
|
* Fills the xMPUSettings structure with the memory region information
|
||||||
|
* contained in xRegions.
|
||||||
|
*/
|
||||||
|
#if ( portUSING_MPU_WRAPPERS == 1 )
|
||||||
|
struct xMEMORY_REGION;
|
||||||
|
void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
|
||||||
|
const struct xMEMORY_REGION * const xRegions,
|
||||||
|
StackType_t * pxBottomOfStack,
|
||||||
|
uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* *INDENT-OFF* */
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
/* *INDENT-ON* */
|
||||||
|
|
||||||
|
#endif /* PORTABLE_H */
|
||||||
122
FreeRTOS/include/projdefs.h
Normal file
122
FreeRTOS/include/projdefs.h
Normal file
@@ -0,0 +1,122 @@
|
|||||||
|
/*
|
||||||
|
* FreeRTOS Kernel V10.4.6
|
||||||
|
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: MIT
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* https://www.FreeRTOS.org
|
||||||
|
* https://github.com/FreeRTOS
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef PROJDEFS_H
|
||||||
|
#define PROJDEFS_H
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Defines the prototype to which task functions must conform. Defined in this
|
||||||
|
* file to ensure the type is known before portable.h is included.
|
||||||
|
*/
|
||||||
|
typedef void (* TaskFunction_t)( void * );
|
||||||
|
|
||||||
|
/* Converts a time in milliseconds to a time in ticks. This macro can be
|
||||||
|
* overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
|
||||||
|
* definition here is not suitable for your application. */
|
||||||
|
#ifndef pdMS_TO_TICKS
|
||||||
|
#define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000U ) )
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define pd0 ( ( BaseType_t ) 0 )
|
||||||
|
#define pd1 ( ( BaseType_t ) 1 )
|
||||||
|
|
||||||
|
#define pdPASS ( pd1 )
|
||||||
|
#define pdFAIL ( pd0 )
|
||||||
|
#define errQUEUE_EMPTY ( ( BaseType_t ) 0 )
|
||||||
|
#define errQUEUE_FULL ( ( BaseType_t ) 0 )
|
||||||
|
|
||||||
|
/* FreeRTOS error definitions. */
|
||||||
|
#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY ( -1 )
|
||||||
|
#define errQUEUE_BLOCKED ( -4 )
|
||||||
|
#define errQUEUE_YIELD ( -5 )
|
||||||
|
|
||||||
|
/* Macros used for basic data corruption checks. */
|
||||||
|
#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES
|
||||||
|
#define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ( configUSE_16_BIT_TICKS == 1 )
|
||||||
|
#define pdINTEGRITY_CHECK_VALUE 0x5a5a
|
||||||
|
#else
|
||||||
|
#define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* The following errno values are used by FreeRTOS+ components, not FreeRTOS
|
||||||
|
* itself. */
|
||||||
|
#define pdFREERTOS_ERRNO_NONE 0 /* No errors */
|
||||||
|
#define pdFREERTOS_ERRNO_ENOENT 2 /* No such file or directory */
|
||||||
|
#define pdFREERTOS_ERRNO_EINTR 4 /* Interrupted system call */
|
||||||
|
#define pdFREERTOS_ERRNO_EIO 5 /* I/O error */
|
||||||
|
#define pdFREERTOS_ERRNO_ENXIO 6 /* No such device or address */
|
||||||
|
#define pdFREERTOS_ERRNO_EBADF 9 /* Bad file number */
|
||||||
|
#define pdFREERTOS_ERRNO_EAGAIN 11 /* No more processes */
|
||||||
|
#define pdFREERTOS_ERRNO_EWOULDBLOCK 11 /* Operation would block */
|
||||||
|
#define pdFREERTOS_ERRNO_ENOMEM 12 /* Not enough memory */
|
||||||
|
#define pdFREERTOS_ERRNO_EACCES 13 /* Permission denied */
|
||||||
|
#define pdFREERTOS_ERRNO_EFAULT 14 /* Bad address */
|
||||||
|
#define pdFREERTOS_ERRNO_EBUSY 16 /* Mount device busy */
|
||||||
|
#define pdFREERTOS_ERRNO_EEXIST 17 /* File exists */
|
||||||
|
#define pdFREERTOS_ERRNO_EXDEV 18 /* Cross-device link */
|
||||||
|
#define pdFREERTOS_ERRNO_ENODEV 19 /* No such device */
|
||||||
|
#define pdFREERTOS_ERRNO_ENOTDIR 20 /* Not a directory */
|
||||||
|
#define pdFREERTOS_ERRNO_EISDIR 21 /* Is a directory */
|
||||||
|
#define pdFREERTOS_ERRNO_EINVAL 22 /* Invalid argument */
|
||||||
|
#define pdFREERTOS_ERRNO_ENOSPC 28 /* No space left on device */
|
||||||
|
#define pdFREERTOS_ERRNO_ESPIPE 29 /* Illegal seek */
|
||||||
|
#define pdFREERTOS_ERRNO_EROFS 30 /* Read only file system */
|
||||||
|
#define pdFREERTOS_ERRNO_EUNATCH 42 /* Protocol driver not attached */
|
||||||
|
#define pdFREERTOS_ERRNO_EBADE 50 /* Invalid exchange */
|
||||||
|
#define pdFREERTOS_ERRNO_EFTYPE 79 /* Inappropriate file type or format */
|
||||||
|
#define pdFREERTOS_ERRNO_ENMFILE 89 /* No more files */
|
||||||
|
#define pdFREERTOS_ERRNO_ENOTEMPTY 90 /* Directory not empty */
|
||||||
|
#define pdFREERTOS_ERRNO_ENAMETOOLONG 91 /* File or path name too long */
|
||||||
|
#define pdFREERTOS_ERRNO_EOPNOTSUPP 95 /* Operation not supported on transport endpoint */
|
||||||
|
#define pdFREERTOS_ERRNO_ENOBUFS 105 /* No buffer space available */
|
||||||
|
#define pdFREERTOS_ERRNO_ENOPROTOOPT 109 /* Protocol not available */
|
||||||
|
#define pdFREERTOS_ERRNO_EADDRINUSE 112 /* Address already in use */
|
||||||
|
#define pdFREERTOS_ERRNO_ETIMEDOUT 116 /* Connection timed out */
|
||||||
|
#define pdFREERTOS_ERRNO_EINPROGRESS 119 /* Connection already in progress */
|
||||||
|
#define pdFREERTOS_ERRNO_EALREADY 120 /* Socket already connected */
|
||||||
|
#define pdFREERTOS_ERRNO_EADDRNOTAVAIL 125 /* Address not available */
|
||||||
|
#define pdFREERTOS_ERRNO_EISCONN 127 /* Socket is already connected */
|
||||||
|
#define pdFREERTOS_ERRNO_ENOTCONN 128 /* Socket is not connected */
|
||||||
|
#define pdFREERTOS_ERRNO_ENOMEDIUM 135 /* No medium inserted */
|
||||||
|
#define pdFREERTOS_ERRNO_EILSEQ 138 /* An invalid UTF-16 sequence was encountered. */
|
||||||
|
#define pdFREERTOS_ERRNO_ECANCELED 140 /* Operation canceled. */
|
||||||
|
|
||||||
|
/* The following endian values are used by FreeRTOS+ components, not FreeRTOS
|
||||||
|
* itself. */
|
||||||
|
#define pdFREERTOS_LITTLE_ENDIAN 0
|
||||||
|
#define pdFREERTOS_BIG_ENDIAN 1
|
||||||
|
|
||||||
|
/* Re-defining endian values for generic naming. */
|
||||||
|
#define pdLITTLE_ENDIAN pdFREERTOS_LITTLE_ENDIAN
|
||||||
|
#define pdBIG_ENDIAN pdFREERTOS_BIG_ENDIAN
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* PROJDEFS_H */
|
||||||
1722
FreeRTOS/include/queue.h
Normal file
1722
FreeRTOS/include/queue.h
Normal file
File diff suppressed because it is too large
Load Diff
1189
FreeRTOS/include/semphr.h
Normal file
1189
FreeRTOS/include/semphr.h
Normal file
File diff suppressed because it is too large
Load Diff
137
FreeRTOS/include/stack_macros.h
Normal file
137
FreeRTOS/include/stack_macros.h
Normal file
@@ -0,0 +1,137 @@
|
|||||||
|
/*
|
||||||
|
* FreeRTOS Kernel V10.4.6
|
||||||
|
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: MIT
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* https://www.FreeRTOS.org
|
||||||
|
* https://github.com/FreeRTOS
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef STACK_MACROS_H
|
||||||
|
#define STACK_MACROS_H
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Call the stack overflow hook function if the stack of the task being swapped
|
||||||
|
* out is currently overflowed, or looks like it might have overflowed in the
|
||||||
|
* past.
|
||||||
|
*
|
||||||
|
* Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
|
||||||
|
* the current stack state only - comparing the current top of stack value to
|
||||||
|
* the stack limit. Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
|
||||||
|
* will also cause the last few stack bytes to be checked to ensure the value
|
||||||
|
* to which the bytes were set when the task was created have not been
|
||||||
|
* overwritten. Note this second test does not guarantee that an overflowed
|
||||||
|
* stack will always be recognised.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* portSTACK_LIMIT_PADDING is a number of extra words to consider to be in
|
||||||
|
* use on the stack.
|
||||||
|
*/
|
||||||
|
#ifndef portSTACK_LIMIT_PADDING
|
||||||
|
#define portSTACK_LIMIT_PADDING 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
|
||||||
|
|
||||||
|
/* Only the current stack state is to be checked. */
|
||||||
|
#define taskCHECK_FOR_STACK_OVERFLOW() \
|
||||||
|
{ \
|
||||||
|
/* Is the currently saved stack pointer within the stack limit? */ \
|
||||||
|
if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack + portSTACK_LIMIT_PADDING ) \
|
||||||
|
{ \
|
||||||
|
vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
|
||||||
|
} \
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
|
||||||
|
|
||||||
|
/* Only the current stack state is to be checked. */
|
||||||
|
#define taskCHECK_FOR_STACK_OVERFLOW() \
|
||||||
|
{ \
|
||||||
|
\
|
||||||
|
/* Is the currently saved stack pointer within the stack limit? */ \
|
||||||
|
if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack - portSTACK_LIMIT_PADDING ) \
|
||||||
|
{ \
|
||||||
|
vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
|
||||||
|
} \
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
|
||||||
|
|
||||||
|
#define taskCHECK_FOR_STACK_OVERFLOW() \
|
||||||
|
{ \
|
||||||
|
const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack; \
|
||||||
|
const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5; \
|
||||||
|
\
|
||||||
|
if( ( pulStack[ 0 ] != ulCheckValue ) || \
|
||||||
|
( pulStack[ 1 ] != ulCheckValue ) || \
|
||||||
|
( pulStack[ 2 ] != ulCheckValue ) || \
|
||||||
|
( pulStack[ 3 ] != ulCheckValue ) ) \
|
||||||
|
{ \
|
||||||
|
vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
|
||||||
|
} \
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
|
||||||
|
|
||||||
|
#define taskCHECK_FOR_STACK_OVERFLOW() \
|
||||||
|
{ \
|
||||||
|
int8_t * pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack; \
|
||||||
|
static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
|
||||||
|
tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
|
||||||
|
tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
|
||||||
|
tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, \
|
||||||
|
tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \
|
||||||
|
\
|
||||||
|
\
|
||||||
|
pcEndOfStack -= sizeof( ucExpectedStackBytes ); \
|
||||||
|
\
|
||||||
|
/* Has the extremity of the task stack ever been written over? */ \
|
||||||
|
if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 ) \
|
||||||
|
{ \
|
||||||
|
vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
|
||||||
|
} \
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Remove stack overflow macro if not being used. */
|
||||||
|
#ifndef taskCHECK_FOR_STACK_OVERFLOW
|
||||||
|
#define taskCHECK_FOR_STACK_OVERFLOW()
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#endif /* STACK_MACROS_H */
|
||||||
58
FreeRTOS/include/stdint.readme
Normal file
58
FreeRTOS/include/stdint.readme
Normal file
@@ -0,0 +1,58 @@
|
|||||||
|
/*
|
||||||
|
* FreeRTOS Kernel V10.4.6
|
||||||
|
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: MIT
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* https://www.FreeRTOS.org
|
||||||
|
* https://github.com/FreeRTOS
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef FREERTOS_STDINT
|
||||||
|
#define FREERTOS_STDINT
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
* THIS IS NOT A FULL stdint.h IMPLEMENTATION - It only contains the definitions
|
||||||
|
* necessary to build the FreeRTOS code. It is provided to allow FreeRTOS to be
|
||||||
|
* built using compilers that do not provide their own stdint.h definition.
|
||||||
|
*
|
||||||
|
* To use this file:
|
||||||
|
*
|
||||||
|
* 1) Copy this file into the directory that contains your FreeRTOSConfig.h
|
||||||
|
* header file, as that directory will already be in the compiler's include
|
||||||
|
* path.
|
||||||
|
*
|
||||||
|
* 2) Rename the copied file stdint.h.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
typedef signed char int8_t;
|
||||||
|
typedef unsigned char uint8_t;
|
||||||
|
typedef short int16_t;
|
||||||
|
typedef unsigned short uint16_t;
|
||||||
|
typedef long int32_t;
|
||||||
|
typedef unsigned long uint32_t;
|
||||||
|
|
||||||
|
#ifndef SIZE_MAX
|
||||||
|
#define SIZE_MAX ( ( size_t ) -1 )
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* FREERTOS_STDINT */
|
||||||
869
FreeRTOS/include/stream_buffer.h
Normal file
869
FreeRTOS/include/stream_buffer.h
Normal file
@@ -0,0 +1,869 @@
|
|||||||
|
/*
|
||||||
|
* FreeRTOS Kernel V10.4.6
|
||||||
|
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: MIT
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* https://www.FreeRTOS.org
|
||||||
|
* https://github.com/FreeRTOS
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Stream buffers are used to send a continuous stream of data from one task or
|
||||||
|
* interrupt to another. Their implementation is light weight, making them
|
||||||
|
* particularly suited for interrupt to task and core to core communication
|
||||||
|
* scenarios.
|
||||||
|
*
|
||||||
|
* ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer
|
||||||
|
* implementation (so also the message buffer implementation, as message buffers
|
||||||
|
* are built on top of stream buffers) assumes there is only one task or
|
||||||
|
* interrupt that will write to the buffer (the writer), and only one task or
|
||||||
|
* interrupt that will read from the buffer (the reader). It is safe for the
|
||||||
|
* writer and reader to be different tasks or interrupts, but, unlike other
|
||||||
|
* FreeRTOS objects, it is not safe to have multiple different writers or
|
||||||
|
* multiple different readers. If there are to be multiple different writers
|
||||||
|
* then the application writer must place each call to a writing API function
|
||||||
|
* (such as xStreamBufferSend()) inside a critical section and set the send
|
||||||
|
* block time to 0. Likewise, if there are to be multiple different readers
|
||||||
|
* then the application writer must place each call to a reading API function
|
||||||
|
* (such as xStreamBufferReceive()) inside a critical section section and set the
|
||||||
|
* receive block time to 0.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef STREAM_BUFFER_H
|
||||||
|
#define STREAM_BUFFER_H
|
||||||
|
|
||||||
|
#ifndef INC_FREERTOS_H
|
||||||
|
#error "include FreeRTOS.h must appear in source files before include stream_buffer.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* *INDENT-OFF* */
|
||||||
|
#if defined( __cplusplus )
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
/* *INDENT-ON* */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Type by which stream buffers are referenced. For example, a call to
|
||||||
|
* xStreamBufferCreate() returns an StreamBufferHandle_t variable that can
|
||||||
|
* then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(),
|
||||||
|
* etc.
|
||||||
|
*/
|
||||||
|
struct StreamBufferDef_t;
|
||||||
|
typedef struct StreamBufferDef_t * StreamBufferHandle_t;
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* stream_buffer.h
|
||||||
|
*
|
||||||
|
* @code{c}
|
||||||
|
* StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Creates a new stream buffer using dynamically allocated memory. See
|
||||||
|
* xStreamBufferCreateStatic() for a version that uses statically allocated
|
||||||
|
* memory (memory that is allocated at compile time).
|
||||||
|
*
|
||||||
|
* configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
|
||||||
|
* FreeRTOSConfig.h for xStreamBufferCreate() to be available.
|
||||||
|
*
|
||||||
|
* @param xBufferSizeBytes The total number of bytes the stream buffer will be
|
||||||
|
* able to hold at any one time.
|
||||||
|
*
|
||||||
|
* @param xTriggerLevelBytes The number of bytes that must be in the stream
|
||||||
|
* buffer before a task that is blocked on the stream buffer to wait for data is
|
||||||
|
* moved out of the blocked state. For example, if a task is blocked on a read
|
||||||
|
* of an empty stream buffer that has a trigger level of 1 then the task will be
|
||||||
|
* unblocked when a single byte is written to the buffer or the task's block
|
||||||
|
* time expires. As another example, if a task is blocked on a read of an empty
|
||||||
|
* stream buffer that has a trigger level of 10 then the task will not be
|
||||||
|
* unblocked until the stream buffer contains at least 10 bytes or the task's
|
||||||
|
* block time expires. If a reading task's block time expires before the
|
||||||
|
* trigger level is reached then the task will still receive however many bytes
|
||||||
|
* are actually available. Setting a trigger level of 0 will result in a
|
||||||
|
* trigger level of 1 being used. It is not valid to specify a trigger level
|
||||||
|
* that is greater than the buffer size.
|
||||||
|
*
|
||||||
|
* @return If NULL is returned, then the stream buffer cannot be created
|
||||||
|
* because there is insufficient heap memory available for FreeRTOS to allocate
|
||||||
|
* the stream buffer data structures and storage area. A non-NULL value being
|
||||||
|
* returned indicates that the stream buffer has been created successfully -
|
||||||
|
* the returned value should be stored as the handle to the created stream
|
||||||
|
* buffer.
|
||||||
|
*
|
||||||
|
* Example use:
|
||||||
|
* @code{c}
|
||||||
|
*
|
||||||
|
* void vAFunction( void )
|
||||||
|
* {
|
||||||
|
* StreamBufferHandle_t xStreamBuffer;
|
||||||
|
* const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
|
||||||
|
*
|
||||||
|
* // Create a stream buffer that can hold 100 bytes. The memory used to hold
|
||||||
|
* // both the stream buffer structure and the data in the stream buffer is
|
||||||
|
* // allocated dynamically.
|
||||||
|
* xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
|
||||||
|
*
|
||||||
|
* if( xStreamBuffer == NULL )
|
||||||
|
* {
|
||||||
|
* // There was not enough heap memory space available to create the
|
||||||
|
* // stream buffer.
|
||||||
|
* }
|
||||||
|
* else
|
||||||
|
* {
|
||||||
|
* // The stream buffer was created successfully and can now be used.
|
||||||
|
* }
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
* \defgroup xStreamBufferCreate xStreamBufferCreate
|
||||||
|
* \ingroup StreamBufferManagement
|
||||||
|
*/
|
||||||
|
#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, pd0 )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* stream_buffer.h
|
||||||
|
*
|
||||||
|
* @code{c}
|
||||||
|
* StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
|
||||||
|
* size_t xTriggerLevelBytes,
|
||||||
|
* uint8_t *pucStreamBufferStorageArea,
|
||||||
|
* StaticStreamBuffer_t *pxStaticStreamBuffer );
|
||||||
|
* @endcode
|
||||||
|
* Creates a new stream buffer using statically allocated memory. See
|
||||||
|
* xStreamBufferCreate() for a version that uses dynamically allocated memory.
|
||||||
|
*
|
||||||
|
* configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for
|
||||||
|
* xStreamBufferCreateStatic() to be available.
|
||||||
|
*
|
||||||
|
* @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
|
||||||
|
* pucStreamBufferStorageArea parameter.
|
||||||
|
*
|
||||||
|
* @param xTriggerLevelBytes The number of bytes that must be in the stream
|
||||||
|
* buffer before a task that is blocked on the stream buffer to wait for data is
|
||||||
|
* moved out of the blocked state. For example, if a task is blocked on a read
|
||||||
|
* of an empty stream buffer that has a trigger level of 1 then the task will be
|
||||||
|
* unblocked when a single byte is written to the buffer or the task's block
|
||||||
|
* time expires. As another example, if a task is blocked on a read of an empty
|
||||||
|
* stream buffer that has a trigger level of 10 then the task will not be
|
||||||
|
* unblocked until the stream buffer contains at least 10 bytes or the task's
|
||||||
|
* block time expires. If a reading task's block time expires before the
|
||||||
|
* trigger level is reached then the task will still receive however many bytes
|
||||||
|
* are actually available. Setting a trigger level of 0 will result in a
|
||||||
|
* trigger level of 1 being used. It is not valid to specify a trigger level
|
||||||
|
* that is greater than the buffer size.
|
||||||
|
*
|
||||||
|
* @param pucStreamBufferStorageArea Must point to a uint8_t array that is at
|
||||||
|
* least xBufferSizeBytes big. This is the array to which streams are
|
||||||
|
* copied when they are written to the stream buffer.
|
||||||
|
*
|
||||||
|
* @param pxStaticStreamBuffer Must point to a variable of type
|
||||||
|
* StaticStreamBuffer_t, which will be used to hold the stream buffer's data
|
||||||
|
* structure.
|
||||||
|
*
|
||||||
|
* @return If the stream buffer is created successfully then a handle to the
|
||||||
|
* created stream buffer is returned. If either pucStreamBufferStorageArea or
|
||||||
|
* pxStaticstreamBuffer are NULL then NULL is returned.
|
||||||
|
*
|
||||||
|
* Example use:
|
||||||
|
* @code{c}
|
||||||
|
*
|
||||||
|
* // Used to dimension the array used to hold the streams. The available space
|
||||||
|
* // will actually be one less than this, so 999.
|
||||||
|
#define STORAGE_SIZE_BYTES 1000
|
||||||
|
*
|
||||||
|
* // Defines the memory that will actually hold the streams within the stream
|
||||||
|
* // buffer.
|
||||||
|
* static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
|
||||||
|
*
|
||||||
|
* // The variable used to hold the stream buffer structure.
|
||||||
|
* StaticStreamBuffer_t xStreamBufferStruct;
|
||||||
|
*
|
||||||
|
* void MyFunction( void )
|
||||||
|
* {
|
||||||
|
* StreamBufferHandle_t xStreamBuffer;
|
||||||
|
* const size_t xTriggerLevel = 1;
|
||||||
|
*
|
||||||
|
* xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucStorageBuffer ),
|
||||||
|
* xTriggerLevel,
|
||||||
|
* ucStorageBuffer,
|
||||||
|
* &xStreamBufferStruct );
|
||||||
|
*
|
||||||
|
* // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
|
||||||
|
* // parameters were NULL, xStreamBuffer will not be NULL, and can be used to
|
||||||
|
* // reference the created stream buffer in other stream buffer API calls.
|
||||||
|
*
|
||||||
|
* // Other code that uses the stream buffer can go here.
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* @endcode
|
||||||
|
* \defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic
|
||||||
|
* \ingroup StreamBufferManagement
|
||||||
|
*/
|
||||||
|
#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) \
|
||||||
|
xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pd0, pucStreamBufferStorageArea, pxStaticStreamBuffer )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* stream_buffer.h
|
||||||
|
*
|
||||||
|
* @code{c}
|
||||||
|
* size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
|
||||||
|
* const void *pvTxData,
|
||||||
|
* size_t xDataLengthBytes,
|
||||||
|
* TickType_t xTicksToWait );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Sends bytes to a stream buffer. The bytes are copied into the stream buffer.
|
||||||
|
*
|
||||||
|
* ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer
|
||||||
|
* implementation (so also the message buffer implementation, as message buffers
|
||||||
|
* are built on top of stream buffers) assumes there is only one task or
|
||||||
|
* interrupt that will write to the buffer (the writer), and only one task or
|
||||||
|
* interrupt that will read from the buffer (the reader). It is safe for the
|
||||||
|
* writer and reader to be different tasks or interrupts, but, unlike other
|
||||||
|
* FreeRTOS objects, it is not safe to have multiple different writers or
|
||||||
|
* multiple different readers. If there are to be multiple different writers
|
||||||
|
* then the application writer must place each call to a writing API function
|
||||||
|
* (such as xStreamBufferSend()) inside a critical section and set the send
|
||||||
|
* block time to 0. Likewise, if there are to be multiple different readers
|
||||||
|
* then the application writer must place each call to a reading API function
|
||||||
|
* (such as xStreamBufferReceive()) inside a critical section and set the receive
|
||||||
|
* block time to 0.
|
||||||
|
*
|
||||||
|
* Use xStreamBufferSend() to write to a stream buffer from a task. Use
|
||||||
|
* xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
|
||||||
|
* service routine (ISR).
|
||||||
|
*
|
||||||
|
* @param xStreamBuffer The handle of the stream buffer to which a stream is
|
||||||
|
* being sent.
|
||||||
|
*
|
||||||
|
* @param pvTxData A pointer to the buffer that holds the bytes to be copied
|
||||||
|
* into the stream buffer.
|
||||||
|
*
|
||||||
|
* @param xDataLengthBytes The maximum number of bytes to copy from pvTxData
|
||||||
|
* into the stream buffer.
|
||||||
|
*
|
||||||
|
* @param xTicksToWait The maximum amount of time the task should remain in the
|
||||||
|
* Blocked state to wait for enough space to become available in the stream
|
||||||
|
* buffer, should the stream buffer contain too little space to hold the
|
||||||
|
* another xDataLengthBytes bytes. The block time is specified in tick periods,
|
||||||
|
* so the absolute time it represents is dependent on the tick frequency. The
|
||||||
|
* macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
|
||||||
|
* into a time specified in ticks. Setting xTicksToWait to portMAX_DELAY will
|
||||||
|
* cause the task to wait indefinitely (without timing out), provided
|
||||||
|
* INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h. If a task times out
|
||||||
|
* before it can write all xDataLengthBytes into the buffer it will still write
|
||||||
|
* as many bytes as possible. A task does not use any CPU time when it is in
|
||||||
|
* the blocked state.
|
||||||
|
*
|
||||||
|
* @return The number of bytes written to the stream buffer. If a task times
|
||||||
|
* out before it can write all xDataLengthBytes into the buffer it will still
|
||||||
|
* write as many bytes as possible.
|
||||||
|
*
|
||||||
|
* Example use:
|
||||||
|
* @code{c}
|
||||||
|
* void vAFunction( StreamBufferHandle_t xStreamBuffer )
|
||||||
|
* {
|
||||||
|
* size_t xBytesSent;
|
||||||
|
* uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
|
||||||
|
* char *pcStringToSend = "String to send";
|
||||||
|
* const TickType_t x100ms = pdMS_TO_TICKS( 100 );
|
||||||
|
*
|
||||||
|
* // Send an array to the stream buffer, blocking for a maximum of 100ms to
|
||||||
|
* // wait for enough space to be available in the stream buffer.
|
||||||
|
* xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
|
||||||
|
*
|
||||||
|
* if( xBytesSent != sizeof( ucArrayToSend ) )
|
||||||
|
* {
|
||||||
|
* // The call to xStreamBufferSend() times out before there was enough
|
||||||
|
* // space in the buffer for the data to be written, but it did
|
||||||
|
* // successfully write xBytesSent bytes.
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* // Send the string to the stream buffer. Return immediately if there is not
|
||||||
|
* // enough space in the buffer.
|
||||||
|
* xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
|
||||||
|
*
|
||||||
|
* if( xBytesSent != strlen( pcStringToSend ) )
|
||||||
|
* {
|
||||||
|
* // The entire string could not be added to the stream buffer because
|
||||||
|
* // there was not enough free space in the buffer, but xBytesSent bytes
|
||||||
|
* // were sent. Could try again to send the remaining bytes.
|
||||||
|
* }
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
* \defgroup xStreamBufferSend xStreamBufferSend
|
||||||
|
* \ingroup StreamBufferManagement
|
||||||
|
*/
|
||||||
|
size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
|
||||||
|
const void * pvTxData,
|
||||||
|
size_t xDataLengthBytes,
|
||||||
|
TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* stream_buffer.h
|
||||||
|
*
|
||||||
|
* @code{c}
|
||||||
|
* size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
|
||||||
|
* const void *pvTxData,
|
||||||
|
* size_t xDataLengthBytes,
|
||||||
|
* BaseType_t *pxHigherPriorityTaskWoken );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Interrupt safe version of the API function that sends a stream of bytes to
|
||||||
|
* the stream buffer.
|
||||||
|
*
|
||||||
|
* ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer
|
||||||
|
* implementation (so also the message buffer implementation, as message buffers
|
||||||
|
* are built on top of stream buffers) assumes there is only one task or
|
||||||
|
* interrupt that will write to the buffer (the writer), and only one task or
|
||||||
|
* interrupt that will read from the buffer (the reader). It is safe for the
|
||||||
|
* writer and reader to be different tasks or interrupts, but, unlike other
|
||||||
|
* FreeRTOS objects, it is not safe to have multiple different writers or
|
||||||
|
* multiple different readers. If there are to be multiple different writers
|
||||||
|
* then the application writer must place each call to a writing API function
|
||||||
|
* (such as xStreamBufferSend()) inside a critical section and set the send
|
||||||
|
* block time to 0. Likewise, if there are to be multiple different readers
|
||||||
|
* then the application writer must place each call to a reading API function
|
||||||
|
* (such as xStreamBufferReceive()) inside a critical section and set the receive
|
||||||
|
* block time to 0.
|
||||||
|
*
|
||||||
|
* Use xStreamBufferSend() to write to a stream buffer from a task. Use
|
||||||
|
* xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
|
||||||
|
* service routine (ISR).
|
||||||
|
*
|
||||||
|
* @param xStreamBuffer The handle of the stream buffer to which a stream is
|
||||||
|
* being sent.
|
||||||
|
*
|
||||||
|
* @param pvTxData A pointer to the data that is to be copied into the stream
|
||||||
|
* buffer.
|
||||||
|
*
|
||||||
|
* @param xDataLengthBytes The maximum number of bytes to copy from pvTxData
|
||||||
|
* into the stream buffer.
|
||||||
|
*
|
||||||
|
* @param pxHigherPriorityTaskWoken It is possible that a stream buffer will
|
||||||
|
* have a task blocked on it waiting for data. Calling
|
||||||
|
* xStreamBufferSendFromISR() can make data available, and so cause a task that
|
||||||
|
* was waiting for data to leave the Blocked state. If calling
|
||||||
|
* xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the
|
||||||
|
* unblocked task has a priority higher than the currently executing task (the
|
||||||
|
* task that was interrupted), then, internally, xStreamBufferSendFromISR()
|
||||||
|
* will set *pxHigherPriorityTaskWoken to pd1. If
|
||||||
|
* xStreamBufferSendFromISR() sets this value to pd1, then normally a
|
||||||
|
* context switch should be performed before the interrupt is exited. This will
|
||||||
|
* ensure that the interrupt returns directly to the highest priority Ready
|
||||||
|
* state task. *pxHigherPriorityTaskWoken should be set to pd0 before it
|
||||||
|
* is passed into the function. See the example code below for an example.
|
||||||
|
*
|
||||||
|
* @return The number of bytes actually written to the stream buffer, which will
|
||||||
|
* be less than xDataLengthBytes if the stream buffer didn't have enough free
|
||||||
|
* space for all the bytes to be written.
|
||||||
|
*
|
||||||
|
* Example use:
|
||||||
|
* @code{c}
|
||||||
|
* // A stream buffer that has already been created.
|
||||||
|
* StreamBufferHandle_t xStreamBuffer;
|
||||||
|
*
|
||||||
|
* void vAnInterruptServiceRoutine( void )
|
||||||
|
* {
|
||||||
|
* size_t xBytesSent;
|
||||||
|
* char *pcStringToSend = "String to send";
|
||||||
|
* BaseType_t xHigherPriorityTaskWoken = pd0; // Initialised to pd0.
|
||||||
|
*
|
||||||
|
* // Attempt to send the string to the stream buffer.
|
||||||
|
* xBytesSent = xStreamBufferSendFromISR( xStreamBuffer,
|
||||||
|
* ( void * ) pcStringToSend,
|
||||||
|
* strlen( pcStringToSend ),
|
||||||
|
* &xHigherPriorityTaskWoken );
|
||||||
|
*
|
||||||
|
* if( xBytesSent != strlen( pcStringToSend ) )
|
||||||
|
* {
|
||||||
|
* // There was not enough free space in the stream buffer for the entire
|
||||||
|
* // string to be written, ut xBytesSent bytes were written.
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* // If xHigherPriorityTaskWoken was set to pd1 inside
|
||||||
|
* // xStreamBufferSendFromISR() then a task that has a priority above the
|
||||||
|
* // priority of the currently executing task was unblocked and a context
|
||||||
|
* // switch should be performed to ensure the ISR returns to the unblocked
|
||||||
|
* // task. In most FreeRTOS ports this is done by simply passing
|
||||||
|
* // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
|
||||||
|
* // variables value, and perform the context switch if necessary. Check the
|
||||||
|
* // documentation for the port in use for port specific instructions.
|
||||||
|
* taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
* \defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR
|
||||||
|
* \ingroup StreamBufferManagement
|
||||||
|
*/
|
||||||
|
size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
|
||||||
|
const void * pvTxData,
|
||||||
|
size_t xDataLengthBytes,
|
||||||
|
BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* stream_buffer.h
|
||||||
|
*
|
||||||
|
* @code{c}
|
||||||
|
* size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
|
||||||
|
* void *pvRxData,
|
||||||
|
* size_t xBufferLengthBytes,
|
||||||
|
* TickType_t xTicksToWait );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Receives bytes from a stream buffer.
|
||||||
|
*
|
||||||
|
* ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer
|
||||||
|
* implementation (so also the message buffer implementation, as message buffers
|
||||||
|
* are built on top of stream buffers) assumes there is only one task or
|
||||||
|
* interrupt that will write to the buffer (the writer), and only one task or
|
||||||
|
* interrupt that will read from the buffer (the reader). It is safe for the
|
||||||
|
* writer and reader to be different tasks or interrupts, but, unlike other
|
||||||
|
* FreeRTOS objects, it is not safe to have multiple different writers or
|
||||||
|
* multiple different readers. If there are to be multiple different writers
|
||||||
|
* then the application writer must place each call to a writing API function
|
||||||
|
* (such as xStreamBufferSend()) inside a critical section and set the send
|
||||||
|
* block time to 0. Likewise, if there are to be multiple different readers
|
||||||
|
* then the application writer must place each call to a reading API function
|
||||||
|
* (such as xStreamBufferReceive()) inside a critical section and set the receive
|
||||||
|
* block time to 0.
|
||||||
|
*
|
||||||
|
* Use xStreamBufferReceive() to read from a stream buffer from a task. Use
|
||||||
|
* xStreamBufferReceiveFromISR() to read from a stream buffer from an
|
||||||
|
* interrupt service routine (ISR).
|
||||||
|
*
|
||||||
|
* @param xStreamBuffer The handle of the stream buffer from which bytes are to
|
||||||
|
* be received.
|
||||||
|
*
|
||||||
|
* @param pvRxData A pointer to the buffer into which the received bytes will be
|
||||||
|
* copied.
|
||||||
|
*
|
||||||
|
* @param xBufferLengthBytes The length of the buffer pointed to by the
|
||||||
|
* pvRxData parameter. This sets the maximum number of bytes to receive in one
|
||||||
|
* call. xStreamBufferReceive will return as many bytes as possible up to a
|
||||||
|
* maximum set by xBufferLengthBytes.
|
||||||
|
*
|
||||||
|
* @param xTicksToWait The maximum amount of time the task should remain in the
|
||||||
|
* Blocked state to wait for data to become available if the stream buffer is
|
||||||
|
* empty. xStreamBufferReceive() will return immediately if xTicksToWait is
|
||||||
|
* zero. The block time is specified in tick periods, so the absolute time it
|
||||||
|
* represents is dependent on the tick frequency. The macro pdMS_TO_TICKS() can
|
||||||
|
* be used to convert a time specified in milliseconds into a time specified in
|
||||||
|
* ticks. Setting xTicksToWait to portMAX_DELAY will cause the task to wait
|
||||||
|
* indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1
|
||||||
|
* in FreeRTOSConfig.h. A task does not use any CPU time when it is in the
|
||||||
|
* Blocked state.
|
||||||
|
*
|
||||||
|
* @return The number of bytes actually read from the stream buffer, which will
|
||||||
|
* be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed
|
||||||
|
* out before xBufferLengthBytes were available.
|
||||||
|
*
|
||||||
|
* Example use:
|
||||||
|
* @code{c}
|
||||||
|
* void vAFunction( StreamBuffer_t xStreamBuffer )
|
||||||
|
* {
|
||||||
|
* uint8_t ucRxData[ 20 ];
|
||||||
|
* size_t xReceivedBytes;
|
||||||
|
* const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
|
||||||
|
*
|
||||||
|
* // Receive up to another sizeof( ucRxData ) bytes from the stream buffer.
|
||||||
|
* // Wait in the Blocked state (so not using any CPU processing time) for a
|
||||||
|
* // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be
|
||||||
|
* // available.
|
||||||
|
* xReceivedBytes = xStreamBufferReceive( xStreamBuffer,
|
||||||
|
* ( void * ) ucRxData,
|
||||||
|
* sizeof( ucRxData ),
|
||||||
|
* xBlockTime );
|
||||||
|
*
|
||||||
|
* if( xReceivedBytes > 0 )
|
||||||
|
* {
|
||||||
|
* // A ucRxData contains another xRecievedBytes bytes of data, which can
|
||||||
|
* // be processed here....
|
||||||
|
* }
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
* \defgroup xStreamBufferReceive xStreamBufferReceive
|
||||||
|
* \ingroup StreamBufferManagement
|
||||||
|
*/
|
||||||
|
size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
|
||||||
|
void * pvRxData,
|
||||||
|
size_t xBufferLengthBytes,
|
||||||
|
TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* stream_buffer.h
|
||||||
|
*
|
||||||
|
* @code{c}
|
||||||
|
* size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
|
||||||
|
* void *pvRxData,
|
||||||
|
* size_t xBufferLengthBytes,
|
||||||
|
* BaseType_t *pxHigherPriorityTaskWoken );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* An interrupt safe version of the API function that receives bytes from a
|
||||||
|
* stream buffer.
|
||||||
|
*
|
||||||
|
* Use xStreamBufferReceive() to read bytes from a stream buffer from a task.
|
||||||
|
* Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an
|
||||||
|
* interrupt service routine (ISR).
|
||||||
|
*
|
||||||
|
* @param xStreamBuffer The handle of the stream buffer from which a stream
|
||||||
|
* is being received.
|
||||||
|
*
|
||||||
|
* @param pvRxData A pointer to the buffer into which the received bytes are
|
||||||
|
* copied.
|
||||||
|
*
|
||||||
|
* @param xBufferLengthBytes The length of the buffer pointed to by the
|
||||||
|
* pvRxData parameter. This sets the maximum number of bytes to receive in one
|
||||||
|
* call. xStreamBufferReceive will return as many bytes as possible up to a
|
||||||
|
* maximum set by xBufferLengthBytes.
|
||||||
|
*
|
||||||
|
* @param pxHigherPriorityTaskWoken It is possible that a stream buffer will
|
||||||
|
* have a task blocked on it waiting for space to become available. Calling
|
||||||
|
* xStreamBufferReceiveFromISR() can make space available, and so cause a task
|
||||||
|
* that is waiting for space to leave the Blocked state. If calling
|
||||||
|
* xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and
|
||||||
|
* the unblocked task has a priority higher than the currently executing task
|
||||||
|
* (the task that was interrupted), then, internally,
|
||||||
|
* xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pd1.
|
||||||
|
* If xStreamBufferReceiveFromISR() sets this value to pd1, then normally a
|
||||||
|
* context switch should be performed before the interrupt is exited. That will
|
||||||
|
* ensure the interrupt returns directly to the highest priority Ready state
|
||||||
|
* task. *pxHigherPriorityTaskWoken should be set to pd0 before it is
|
||||||
|
* passed into the function. See the code example below for an example.
|
||||||
|
*
|
||||||
|
* @return The number of bytes read from the stream buffer, if any.
|
||||||
|
*
|
||||||
|
* Example use:
|
||||||
|
* @code{c}
|
||||||
|
* // A stream buffer that has already been created.
|
||||||
|
* StreamBuffer_t xStreamBuffer;
|
||||||
|
*
|
||||||
|
* void vAnInterruptServiceRoutine( void )
|
||||||
|
* {
|
||||||
|
* uint8_t ucRxData[ 20 ];
|
||||||
|
* size_t xReceivedBytes;
|
||||||
|
* BaseType_t xHigherPriorityTaskWoken = pd0; // Initialised to pd0.
|
||||||
|
*
|
||||||
|
* // Receive the next stream from the stream buffer.
|
||||||
|
* xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer,
|
||||||
|
* ( void * ) ucRxData,
|
||||||
|
* sizeof( ucRxData ),
|
||||||
|
* &xHigherPriorityTaskWoken );
|
||||||
|
*
|
||||||
|
* if( xReceivedBytes > 0 )
|
||||||
|
* {
|
||||||
|
* // ucRxData contains xReceivedBytes read from the stream buffer.
|
||||||
|
* // Process the stream here....
|
||||||
|
* }
|
||||||
|
*
|
||||||
|
* // If xHigherPriorityTaskWoken was set to pd1 inside
|
||||||
|
* // xStreamBufferReceiveFromISR() then a task that has a priority above the
|
||||||
|
* // priority of the currently executing task was unblocked and a context
|
||||||
|
* // switch should be performed to ensure the ISR returns to the unblocked
|
||||||
|
* // task. In most FreeRTOS ports this is done by simply passing
|
||||||
|
* // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
|
||||||
|
* // variables value, and perform the context switch if necessary. Check the
|
||||||
|
* // documentation for the port in use for port specific instructions.
|
||||||
|
* taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
|
||||||
|
* }
|
||||||
|
* @endcode
|
||||||
|
* \defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR
|
||||||
|
* \ingroup StreamBufferManagement
|
||||||
|
*/
|
||||||
|
size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
|
||||||
|
void * pvRxData,
|
||||||
|
size_t xBufferLengthBytes,
|
||||||
|
BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* stream_buffer.h
|
||||||
|
*
|
||||||
|
* @code{c}
|
||||||
|
* void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Deletes a stream buffer that was previously created using a call to
|
||||||
|
* xStreamBufferCreate() or xStreamBufferCreateStatic(). If the stream
|
||||||
|
* buffer was created using dynamic memory (that is, by xStreamBufferCreate()),
|
||||||
|
* then the allocated memory is freed.
|
||||||
|
*
|
||||||
|
* A stream buffer handle must not be used after the stream buffer has been
|
||||||
|
* deleted.
|
||||||
|
*
|
||||||
|
* @param xStreamBuffer The handle of the stream buffer to be deleted.
|
||||||
|
*
|
||||||
|
* \defgroup vStreamBufferDelete vStreamBufferDelete
|
||||||
|
* \ingroup StreamBufferManagement
|
||||||
|
*/
|
||||||
|
void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* stream_buffer.h
|
||||||
|
*
|
||||||
|
* @code{c}
|
||||||
|
* BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Queries a stream buffer to see if it is full. A stream buffer is full if it
|
||||||
|
* does not have any free space, and therefore cannot accept any more data.
|
||||||
|
*
|
||||||
|
* @param xStreamBuffer The handle of the stream buffer being queried.
|
||||||
|
*
|
||||||
|
* @return If the stream buffer is full then pd1 is returned. Otherwise
|
||||||
|
* pd0 is returned.
|
||||||
|
*
|
||||||
|
* \defgroup xStreamBufferIsFull xStreamBufferIsFull
|
||||||
|
* \ingroup StreamBufferManagement
|
||||||
|
*/
|
||||||
|
BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* stream_buffer.h
|
||||||
|
*
|
||||||
|
* @code{c}
|
||||||
|
* BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Queries a stream buffer to see if it is empty. A stream buffer is empty if
|
||||||
|
* it does not contain any data.
|
||||||
|
*
|
||||||
|
* @param xStreamBuffer The handle of the stream buffer being queried.
|
||||||
|
*
|
||||||
|
* @return If the stream buffer is empty then pd1 is returned. Otherwise
|
||||||
|
* pd0 is returned.
|
||||||
|
*
|
||||||
|
* \defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty
|
||||||
|
* \ingroup StreamBufferManagement
|
||||||
|
*/
|
||||||
|
BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* stream_buffer.h
|
||||||
|
*
|
||||||
|
* @code{c}
|
||||||
|
* BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Resets a stream buffer to its initial, empty, state. Any data that was in
|
||||||
|
* the stream buffer is discarded. A stream buffer can only be reset if there
|
||||||
|
* are no tasks blocked waiting to either send to or receive from the stream
|
||||||
|
* buffer.
|
||||||
|
*
|
||||||
|
* @param xStreamBuffer The handle of the stream buffer being reset.
|
||||||
|
*
|
||||||
|
* @return If the stream buffer is reset then pdPASS is returned. If there was
|
||||||
|
* a task blocked waiting to send to or read from the stream buffer then the
|
||||||
|
* stream buffer is not reset and pdFAIL is returned.
|
||||||
|
*
|
||||||
|
* \defgroup xStreamBufferReset xStreamBufferReset
|
||||||
|
* \ingroup StreamBufferManagement
|
||||||
|
*/
|
||||||
|
BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* stream_buffer.h
|
||||||
|
*
|
||||||
|
* @code{c}
|
||||||
|
* size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Queries a stream buffer to see how much free space it contains, which is
|
||||||
|
* equal to the amount of data that can be sent to the stream buffer before it
|
||||||
|
* is full.
|
||||||
|
*
|
||||||
|
* @param xStreamBuffer The handle of the stream buffer being queried.
|
||||||
|
*
|
||||||
|
* @return The number of bytes that can be written to the stream buffer before
|
||||||
|
* the stream buffer would be full.
|
||||||
|
*
|
||||||
|
* \defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable
|
||||||
|
* \ingroup StreamBufferManagement
|
||||||
|
*/
|
||||||
|
size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* stream_buffer.h
|
||||||
|
*
|
||||||
|
* @code{c}
|
||||||
|
* size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* Queries a stream buffer to see how much data it contains, which is equal to
|
||||||
|
* the number of bytes that can be read from the stream buffer before the stream
|
||||||
|
* buffer would be empty.
|
||||||
|
*
|
||||||
|
* @param xStreamBuffer The handle of the stream buffer being queried.
|
||||||
|
*
|
||||||
|
* @return The number of bytes that can be read from the stream buffer before
|
||||||
|
* the stream buffer would be empty.
|
||||||
|
*
|
||||||
|
* \defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable
|
||||||
|
* \ingroup StreamBufferManagement
|
||||||
|
*/
|
||||||
|
size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* stream_buffer.h
|
||||||
|
*
|
||||||
|
* @code{c}
|
||||||
|
* BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* A stream buffer's trigger level is the number of bytes that must be in the
|
||||||
|
* stream buffer before a task that is blocked on the stream buffer to
|
||||||
|
* wait for data is moved out of the blocked state. For example, if a task is
|
||||||
|
* blocked on a read of an empty stream buffer that has a trigger level of 1
|
||||||
|
* then the task will be unblocked when a single byte is written to the buffer
|
||||||
|
* or the task's block time expires. As another example, if a task is blocked
|
||||||
|
* on a read of an empty stream buffer that has a trigger level of 10 then the
|
||||||
|
* task will not be unblocked until the stream buffer contains at least 10 bytes
|
||||||
|
* or the task's block time expires. If a reading task's block time expires
|
||||||
|
* before the trigger level is reached then the task will still receive however
|
||||||
|
* many bytes are actually available. Setting a trigger level of 0 will result
|
||||||
|
* in a trigger level of 1 being used. It is not valid to specify a trigger
|
||||||
|
* level that is greater than the buffer size.
|
||||||
|
*
|
||||||
|
* A trigger level is set when the stream buffer is created, and can be modified
|
||||||
|
* using xStreamBufferSetTriggerLevel().
|
||||||
|
*
|
||||||
|
* @param xStreamBuffer The handle of the stream buffer being updated.
|
||||||
|
*
|
||||||
|
* @param xTriggerLevel The new trigger level for the stream buffer.
|
||||||
|
*
|
||||||
|
* @return If xTriggerLevel was less than or equal to the stream buffer's length
|
||||||
|
* then the trigger level will be updated and pd1 is returned. Otherwise
|
||||||
|
* pd0 is returned.
|
||||||
|
*
|
||||||
|
* \defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel
|
||||||
|
* \ingroup StreamBufferManagement
|
||||||
|
*/
|
||||||
|
BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
|
||||||
|
size_t xTriggerLevel ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* stream_buffer.h
|
||||||
|
*
|
||||||
|
* @code{c}
|
||||||
|
* BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* For advanced users only.
|
||||||
|
*
|
||||||
|
* The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
|
||||||
|
* data is sent to a message buffer or stream buffer. If there was a task that
|
||||||
|
* was blocked on the message or stream buffer waiting for data to arrive then
|
||||||
|
* the sbSEND_COMPLETED() macro sends a notification to the task to remove it
|
||||||
|
* from the Blocked state. xStreamBufferSendCompletedFromISR() does the same
|
||||||
|
* thing. It is provided to enable application writers to implement their own
|
||||||
|
* version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
|
||||||
|
*
|
||||||
|
* See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
|
||||||
|
* additional information.
|
||||||
|
*
|
||||||
|
* @param xStreamBuffer The handle of the stream buffer to which data was
|
||||||
|
* written.
|
||||||
|
*
|
||||||
|
* @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
|
||||||
|
* initialised to pd0 before it is passed into
|
||||||
|
* xStreamBufferSendCompletedFromISR(). If calling
|
||||||
|
* xStreamBufferSendCompletedFromISR() removes a task from the Blocked state,
|
||||||
|
* and the task has a priority above the priority of the currently running task,
|
||||||
|
* then *pxHigherPriorityTaskWoken will get set to pd1 indicating that a
|
||||||
|
* context switch should be performed before exiting the ISR.
|
||||||
|
*
|
||||||
|
* @return If a task was removed from the Blocked state then pd1 is returned.
|
||||||
|
* Otherwise pd0 is returned.
|
||||||
|
*
|
||||||
|
* \defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR
|
||||||
|
* \ingroup StreamBufferManagement
|
||||||
|
*/
|
||||||
|
BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
|
||||||
|
BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* stream_buffer.h
|
||||||
|
*
|
||||||
|
* @code{c}
|
||||||
|
* BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
|
||||||
|
* @endcode
|
||||||
|
*
|
||||||
|
* For advanced users only.
|
||||||
|
*
|
||||||
|
* The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
|
||||||
|
* data is read out of a message buffer or stream buffer. If there was a task
|
||||||
|
* that was blocked on the message or stream buffer waiting for data to arrive
|
||||||
|
* then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
|
||||||
|
* remove it from the Blocked state. xStreamBufferReceiveCompletedFromISR()
|
||||||
|
* does the same thing. It is provided to enable application writers to
|
||||||
|
* implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
|
||||||
|
* ANY OTHER TIME.
|
||||||
|
*
|
||||||
|
* See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
|
||||||
|
* additional information.
|
||||||
|
*
|
||||||
|
* @param xStreamBuffer The handle of the stream buffer from which data was
|
||||||
|
* read.
|
||||||
|
*
|
||||||
|
* @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
|
||||||
|
* initialised to pd0 before it is passed into
|
||||||
|
* xStreamBufferReceiveCompletedFromISR(). If calling
|
||||||
|
* xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state,
|
||||||
|
* and the task has a priority above the priority of the currently running task,
|
||||||
|
* then *pxHigherPriorityTaskWoken will get set to pd1 indicating that a
|
||||||
|
* context switch should be performed before exiting the ISR.
|
||||||
|
*
|
||||||
|
* @return If a task was removed from the Blocked state then pd1 is returned.
|
||||||
|
* Otherwise pd0 is returned.
|
||||||
|
*
|
||||||
|
* \defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR
|
||||||
|
* \ingroup StreamBufferManagement
|
||||||
|
*/
|
||||||
|
BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
|
||||||
|
BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/* Functions below here are not part of the public API. */
|
||||||
|
StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
|
||||||
|
size_t xTriggerLevelBytes,
|
||||||
|
BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
|
||||||
|
size_t xTriggerLevelBytes,
|
||||||
|
BaseType_t xIsMessageBuffer,
|
||||||
|
uint8_t * const pucStreamBufferStorageArea,
|
||||||
|
StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
#if ( configUSE_TRACE_FACILITY == 1 )
|
||||||
|
void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer,
|
||||||
|
UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION;
|
||||||
|
UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
|
||||||
|
uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* *INDENT-OFF* */
|
||||||
|
#if defined( __cplusplus )
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
/* *INDENT-ON* */
|
||||||
|
|
||||||
|
#endif /* !defined( STREAM_BUFFER_H ) */
|
||||||
3112
FreeRTOS/include/task.h
Normal file
3112
FreeRTOS/include/task.h
Normal file
File diff suppressed because it is too large
Load Diff
1355
FreeRTOS/include/timers.h
Normal file
1355
FreeRTOS/include/timers.h
Normal file
File diff suppressed because it is too large
Load Diff
215
FreeRTOS/list.c
Normal file
215
FreeRTOS/list.c
Normal file
@@ -0,0 +1,215 @@
|
|||||||
|
/*
|
||||||
|
* FreeRTOS Kernel V10.4.6
|
||||||
|
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: MIT
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* https://www.FreeRTOS.org
|
||||||
|
* https://github.com/FreeRTOS
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#include <stdlib.h>
|
||||||
|
|
||||||
|
/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
|
||||||
|
* all the API functions to use the MPU wrappers. That should only be done when
|
||||||
|
* task.h is included from an application file. */
|
||||||
|
#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
|
||||||
|
|
||||||
|
#include "FreeRTOS.h"
|
||||||
|
#include "list.h"
|
||||||
|
|
||||||
|
/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
|
||||||
|
* because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be
|
||||||
|
* defined for the header files above, but not in this file, in order to
|
||||||
|
* generate the correct privileged Vs unprivileged linkage and placement. */
|
||||||
|
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------
|
||||||
|
* PUBLIC LIST API documented in list.h
|
||||||
|
*----------------------------------------------------------*/
|
||||||
|
|
||||||
|
void vListInitialise( List_t * const pxList )
|
||||||
|
{
|
||||||
|
/* The list structure contains a list item which is used to mark the
|
||||||
|
* end of the list. To initialise the list the list end is inserted
|
||||||
|
* as the only list entry. */
|
||||||
|
pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
|
||||||
|
|
||||||
|
/* The list end value is the highest possible value in the list to
|
||||||
|
* ensure it remains at the end of the list. */
|
||||||
|
pxList->xListEnd.xItemValue = portMAX_DELAY;
|
||||||
|
|
||||||
|
/* The list end next and previous pointers point to itself so we know
|
||||||
|
* when the list is empty. */
|
||||||
|
pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
|
||||||
|
pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */
|
||||||
|
|
||||||
|
pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
|
||||||
|
|
||||||
|
/* Write known values into the list if
|
||||||
|
* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
|
||||||
|
listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
|
||||||
|
listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
void vListInitialiseItem( ListItem_t * const pxItem )
|
||||||
|
{
|
||||||
|
/* Make sure the list item is not recorded as being on a list. */
|
||||||
|
pxItem->pxContainer = NULL;
|
||||||
|
|
||||||
|
/* Write known values into the list item if
|
||||||
|
* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
|
||||||
|
listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
|
||||||
|
listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
void vListInsertEnd( List_t * const pxList,
|
||||||
|
ListItem_t * const pxNewListItem )
|
||||||
|
{
|
||||||
|
ListItem_t * const pxIndex = pxList->pxIndex;
|
||||||
|
|
||||||
|
/* Only effective when configASSERT() is also defined, these tests may catch
|
||||||
|
* the list data structures being overwritten in memory. They will not catch
|
||||||
|
* data errors caused by incorrect configuration or use of FreeRTOS. */
|
||||||
|
listTEST_LIST_INTEGRITY( pxList );
|
||||||
|
listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
|
||||||
|
|
||||||
|
/* Insert a new list item into pxList, but rather than sort the list,
|
||||||
|
* makes the new list item the last item to be removed by a call to
|
||||||
|
* listGET_OWNER_OF_NEXT_ENTRY(). */
|
||||||
|
pxNewListItem->pxNext = pxIndex;
|
||||||
|
pxNewListItem->pxPrevious = pxIndex->pxPrevious;
|
||||||
|
|
||||||
|
/* Only used during decision coverage testing. */
|
||||||
|
mtCOVERAGE_TEST_DELAY();
|
||||||
|
|
||||||
|
pxIndex->pxPrevious->pxNext = pxNewListItem;
|
||||||
|
pxIndex->pxPrevious = pxNewListItem;
|
||||||
|
|
||||||
|
/* Remember which list the item is in. */
|
||||||
|
pxNewListItem->pxContainer = pxList;
|
||||||
|
|
||||||
|
( pxList->uxNumberOfItems )++;
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
void vListInsert( List_t * const pxList,
|
||||||
|
ListItem_t * const pxNewListItem )
|
||||||
|
{
|
||||||
|
ListItem_t * pxIterator;
|
||||||
|
const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
|
||||||
|
|
||||||
|
/* Only effective when configASSERT() is also defined, these tests may catch
|
||||||
|
* the list data structures being overwritten in memory. They will not catch
|
||||||
|
* data errors caused by incorrect configuration or use of FreeRTOS. */
|
||||||
|
listTEST_LIST_INTEGRITY( pxList );
|
||||||
|
listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
|
||||||
|
|
||||||
|
/* Insert the new list item into the list, sorted in xItemValue order.
|
||||||
|
*
|
||||||
|
* If the list already contains a list item with the same item value then the
|
||||||
|
* new list item should be placed after it. This ensures that TCBs which are
|
||||||
|
* stored in ready lists (all of which have the same xItemValue value) get a
|
||||||
|
* share of the CPU. However, if the xItemValue is the same as the back marker
|
||||||
|
* the iteration loop below will not end. Therefore the value is checked
|
||||||
|
* first, and the algorithm slightly modified if necessary. */
|
||||||
|
if( xValueOfInsertion == portMAX_DELAY )
|
||||||
|
{
|
||||||
|
pxIterator = pxList->xListEnd.pxPrevious;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* *** NOTE ***********************************************************
|
||||||
|
* If you find your application is crashing here then likely causes are
|
||||||
|
* listed below. In addition see https://www.FreeRTOS.org/FAQHelp.html for
|
||||||
|
* more tips, and ensure configASSERT() is defined!
|
||||||
|
* https://www.FreeRTOS.org/a00110.html#configASSERT
|
||||||
|
*
|
||||||
|
* 1) Stack overflow -
|
||||||
|
* see https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html
|
||||||
|
* 2) Incorrect interrupt priority assignment, especially on Cortex-M
|
||||||
|
* parts where numerically high priority values denote low actual
|
||||||
|
* interrupt priorities, which can seem counter intuitive. See
|
||||||
|
* https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html and the definition
|
||||||
|
* of configMAX_SYSCALL_INTERRUPT_PRIORITY on
|
||||||
|
* https://www.FreeRTOS.org/a00110.html
|
||||||
|
* 3) Calling an API function from within a critical section or when
|
||||||
|
* the scheduler is suspended, or calling an API function that does
|
||||||
|
* not end in "FromISR" from an interrupt.
|
||||||
|
* 4) Using a queue or semaphore before it has been initialised or
|
||||||
|
* before the scheduler has been started (are interrupts firing
|
||||||
|
* before vTaskStartScheduler() has been called?).
|
||||||
|
* 5) If the FreeRTOS port supports interrupt nesting then ensure that
|
||||||
|
* the priority of the tick interrupt is at or below
|
||||||
|
* configMAX_SYSCALL_INTERRUPT_PRIORITY.
|
||||||
|
**********************************************************************/
|
||||||
|
|
||||||
|
for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
|
||||||
|
{
|
||||||
|
/* There is nothing to do here, just iterating to the wanted
|
||||||
|
* insertion position. */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
pxNewListItem->pxNext = pxIterator->pxNext;
|
||||||
|
pxNewListItem->pxNext->pxPrevious = pxNewListItem;
|
||||||
|
pxNewListItem->pxPrevious = pxIterator;
|
||||||
|
pxIterator->pxNext = pxNewListItem;
|
||||||
|
|
||||||
|
/* Remember which list the item is in. This allows fast removal of the
|
||||||
|
* item later. */
|
||||||
|
pxNewListItem->pxContainer = pxList;
|
||||||
|
|
||||||
|
( pxList->uxNumberOfItems )++;
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
|
||||||
|
{
|
||||||
|
/* The list item knows which list it is in. Obtain the list from the list
|
||||||
|
* item. */
|
||||||
|
List_t * const pxList = pxItemToRemove->pxContainer;
|
||||||
|
|
||||||
|
pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
|
||||||
|
pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
|
||||||
|
|
||||||
|
/* Only used during decision coverage testing. */
|
||||||
|
mtCOVERAGE_TEST_DELAY();
|
||||||
|
|
||||||
|
/* Make sure the index is left pointing to a valid item. */
|
||||||
|
if( pxList->pxIndex == pxItemToRemove )
|
||||||
|
{
|
||||||
|
pxList->pxIndex = pxItemToRemove->pxPrevious;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
mtCOVERAGE_TEST_MARKER();
|
||||||
|
}
|
||||||
|
|
||||||
|
pxItemToRemove->pxContainer = NULL;
|
||||||
|
( pxList->uxNumberOfItems )--;
|
||||||
|
|
||||||
|
return pxList->uxNumberOfItems;
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
1482
FreeRTOS/portable/Common/mpu_wrappers.c
Normal file
1482
FreeRTOS/portable/Common/mpu_wrappers.c
Normal file
File diff suppressed because it is too large
Load Diff
5
FreeRTOS/portable/GCC/RISC-V/Documentation.url
Normal file
5
FreeRTOS/portable/GCC/RISC-V/Documentation.url
Normal file
@@ -0,0 +1,5 @@
|
|||||||
|
[{000214A0-0000-0000-C000-000000000046}]
|
||||||
|
Prop3=19,11
|
||||||
|
[InternetShortcut]
|
||||||
|
IDList=
|
||||||
|
URL=https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
|
||||||
@@ -0,0 +1,150 @@
|
|||||||
|
/*
|
||||||
|
* FreeRTOS Kernel V10.4.6
|
||||||
|
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: MIT
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* https://www.FreeRTOS.org
|
||||||
|
* https://github.com/FreeRTOS
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The FreeRTOS kernel's RISC-V port is split between the the code that is
|
||||||
|
* common across all currently supported RISC-V chips (implementations of the
|
||||||
|
* RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
|
||||||
|
*
|
||||||
|
* + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
|
||||||
|
* is common to all currently supported RISC-V chips. There is only one
|
||||||
|
* portASM.S file because the same file is built for all RISC-V target chips.
|
||||||
|
*
|
||||||
|
* + Header files called freertos_risc_v_chip_specific_extensions.h contain the
|
||||||
|
* code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
|
||||||
|
* chip. There are multiple freertos_risc_v_chip_specific_extensions.h files
|
||||||
|
* as there are multiple RISC-V chip implementations.
|
||||||
|
*
|
||||||
|
* !!!NOTE!!!
|
||||||
|
* TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
|
||||||
|
* HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
|
||||||
|
* compiler's!) include path. For example, if the chip in use includes a core
|
||||||
|
* local interrupter (CLINT) and does not include any chip specific register
|
||||||
|
* extensions then add the path below to the assembler's include path:
|
||||||
|
* FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
|
||||||
|
#define __FREERTOS_RISC_V_EXTENSIONS_H__
|
||||||
|
|
||||||
|
#define portasmHAS_SIFIVE_CLINT 0
|
||||||
|
#define portasmHAS_MTIME 0
|
||||||
|
/* if you want to use FPU, please define ARCH_FPU and enable float point and ABI of gcc */
|
||||||
|
#define ARCH_FPU 0
|
||||||
|
|
||||||
|
|
||||||
|
#if ARCH_FPU
|
||||||
|
#define portasmADDITIONAL_CONTEXT_SIZE 32 /* Must be even number on 32-bit cores. */
|
||||||
|
.macro portasmSAVE_ADDITIONAL_REGISTERS
|
||||||
|
addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE* portWORD_SIZE)
|
||||||
|
fsw f0, 1*portWORD_SIZE(sp)
|
||||||
|
fsw f1, 2*portWORD_SIZE(sp)
|
||||||
|
fsw f2, 3*portWORD_SIZE(sp)
|
||||||
|
fsw f3, 4*portWORD_SIZE(sp)
|
||||||
|
fsw f4, 5*portWORD_SIZE(sp)
|
||||||
|
fsw f5, 6*portWORD_SIZE(sp)
|
||||||
|
fsw f6, 7*portWORD_SIZE(sp)
|
||||||
|
fsw f7, 8*portWORD_SIZE(sp)
|
||||||
|
fsw f8, 9*portWORD_SIZE(sp)
|
||||||
|
fsw f9, 10*portWORD_SIZE(sp)
|
||||||
|
fsw f10, 11*portWORD_SIZE(sp)
|
||||||
|
fsw f11, 12*portWORD_SIZE(sp)
|
||||||
|
fsw f12, 13*portWORD_SIZE(sp)
|
||||||
|
fsw f13, 14*portWORD_SIZE(sp)
|
||||||
|
fsw f14, 15*portWORD_SIZE(sp)
|
||||||
|
fsw f15, 16*portWORD_SIZE(sp)
|
||||||
|
fsw f16, 17*portWORD_SIZE(sp)
|
||||||
|
fsw f17, 18*portWORD_SIZE(sp)
|
||||||
|
fsw f18, 19*portWORD_SIZE(sp)
|
||||||
|
fsw f19, 20*portWORD_SIZE(sp)
|
||||||
|
fsw f20, 21*portWORD_SIZE(sp)
|
||||||
|
fsw f21, 22*portWORD_SIZE(sp)
|
||||||
|
fsw f22, 23*portWORD_SIZE(sp)
|
||||||
|
fsw f23, 24*portWORD_SIZE(sp)
|
||||||
|
fsw f24, 25*portWORD_SIZE(sp)
|
||||||
|
fsw f25, 26*portWORD_SIZE(sp)
|
||||||
|
fsw f26, 27*portWORD_SIZE(sp)
|
||||||
|
fsw f27, 28*portWORD_SIZE(sp)
|
||||||
|
fsw f28, 29*portWORD_SIZE(sp)
|
||||||
|
fsw f29, 30*portWORD_SIZE(sp)
|
||||||
|
fsw f30, 31*portWORD_SIZE(sp)
|
||||||
|
fsw f31, 32*portWORD_SIZE(sp)
|
||||||
|
.endm
|
||||||
|
|
||||||
|
.macro portasmRESTORE_ADDITIONAL_REGISTERS
|
||||||
|
flw f0, 1*portWORD_SIZE(sp)
|
||||||
|
flw f1, 2*portWORD_SIZE(sp)
|
||||||
|
flw f2, 3*portWORD_SIZE(sp)
|
||||||
|
flw f3, 4*portWORD_SIZE(sp)
|
||||||
|
flw f4, 5*portWORD_SIZE(sp)
|
||||||
|
flw f5, 6*portWORD_SIZE(sp)
|
||||||
|
flw f6, 7*portWORD_SIZE(sp)
|
||||||
|
flw f7, 8*portWORD_SIZE(sp)
|
||||||
|
flw f8, 9*portWORD_SIZE(sp)
|
||||||
|
flw f9, 10*portWORD_SIZE(sp)
|
||||||
|
flw f10, 11*portWORD_SIZE(sp)
|
||||||
|
flw f11, 12*portWORD_SIZE(sp)
|
||||||
|
flw f12, 13*portWORD_SIZE(sp)
|
||||||
|
flw f13, 14*portWORD_SIZE(sp)
|
||||||
|
flw f14, 15*portWORD_SIZE(sp)
|
||||||
|
flw f15, 16*portWORD_SIZE(sp)
|
||||||
|
flw f16, 17*portWORD_SIZE(sp)
|
||||||
|
flw f17, 18*portWORD_SIZE(sp)
|
||||||
|
flw f18, 19*portWORD_SIZE(sp)
|
||||||
|
flw f19, 20*portWORD_SIZE(sp)
|
||||||
|
flw f20, 21*portWORD_SIZE(sp)
|
||||||
|
flw f21, 22*portWORD_SIZE(sp)
|
||||||
|
flw f22, 23*portWORD_SIZE(sp)
|
||||||
|
flw f23, 24*portWORD_SIZE(sp)
|
||||||
|
flw f24, 25*portWORD_SIZE(sp)
|
||||||
|
flw f25, 26*portWORD_SIZE(sp)
|
||||||
|
flw f26, 27*portWORD_SIZE(sp)
|
||||||
|
flw f27, 28*portWORD_SIZE(sp)
|
||||||
|
flw f28, 29*portWORD_SIZE(sp)
|
||||||
|
flw f29, 30*portWORD_SIZE(sp)
|
||||||
|
flw f30, 31*portWORD_SIZE(sp)
|
||||||
|
flw f31, 32*portWORD_SIZE(sp)
|
||||||
|
addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE* portWORD_SIZE)
|
||||||
|
.endm
|
||||||
|
#else
|
||||||
|
#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */
|
||||||
|
|
||||||
|
|
||||||
|
.macro portasmSAVE_ADDITIONAL_REGISTERS
|
||||||
|
/* No additional registers to save, so this macro does nothing. */
|
||||||
|
.endm
|
||||||
|
|
||||||
|
.macro portasmRESTORE_ADDITIONAL_REGISTERS
|
||||||
|
/* No additional registers to restore, so this macro does nothing. */
|
||||||
|
.endm
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
|
||||||
@@ -0,0 +1,23 @@
|
|||||||
|
/*
|
||||||
|
* The FreeRTOS kernel's RISC-V port is split between the the code that is
|
||||||
|
* common across all currently supported RISC-V chips (implementations of the
|
||||||
|
* RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
|
||||||
|
*
|
||||||
|
* + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
|
||||||
|
* is common to all currently supported RISC-V chips. There is only one
|
||||||
|
* portASM.S file because the same file is built for all RISC-V target chips.
|
||||||
|
*
|
||||||
|
* + Header files called freertos_risc_v_chip_specific_extensions.h contain the
|
||||||
|
* code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
|
||||||
|
* chip. There are multiple freertos_risc_v_chip_specific_extensions.h files
|
||||||
|
* as there are multiple RISC-V chip implementations.
|
||||||
|
*
|
||||||
|
* !!!NOTE!!!
|
||||||
|
* TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
|
||||||
|
* HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
|
||||||
|
* compiler's!) include path. For example, if the chip in use includes a core
|
||||||
|
* local interrupter (CLINT) and does not include any chip specific register
|
||||||
|
* extensions then add the path below to the assembler's include path:
|
||||||
|
* FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
|
||||||
|
*
|
||||||
|
*/
|
||||||
280
FreeRTOS/portable/GCC/RISC-V/port.c
Normal file
280
FreeRTOS/portable/GCC/RISC-V/port.c
Normal file
@@ -0,0 +1,280 @@
|
|||||||
|
/*
|
||||||
|
* FreeRTOS Kernel V10.4.6
|
||||||
|
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: MIT
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* https://www.FreeRTOS.org
|
||||||
|
* https://github.com/FreeRTOS
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------
|
||||||
|
* Implementation of functions defined in portable.h for the RISC-V RV32 port.
|
||||||
|
*----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Scheduler includes. */
|
||||||
|
#include "FreeRTOS.h"
|
||||||
|
#include "task.h"
|
||||||
|
#include "portmacro.h"
|
||||||
|
|
||||||
|
/* Standard includes. */
|
||||||
|
#include "string.h"
|
||||||
|
|
||||||
|
#ifdef configCLINT_BASE_ADDRESS
|
||||||
|
#warning The configCLINT_BASE_ADDRESS constant has been deprecated. configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting. Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS dirctly in place of configCLINT_BASE_ADDRESS. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef configMTIME_BASE_ADDRESS
|
||||||
|
#warning configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address. Otherwise set configMTIME_BASE_ADDRESS to 0. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef configMTIMECMP_BASE_ADDRESS
|
||||||
|
#warning configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address. Otherwise set configMTIMECMP_BASE_ADDRESS to 0. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Let the user override the pre-loading of the initial LR with the address of
|
||||||
|
prvTaskExitError() in case it messes up unwinding of the stack in the
|
||||||
|
debugger. */
|
||||||
|
#ifdef configTASK_RETURN_ADDRESS
|
||||||
|
#define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
|
||||||
|
#else
|
||||||
|
#define portTASK_RETURN_ADDRESS prvTaskExitError
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* The stack used by interrupt service routines. Set configISR_STACK_SIZE_WORDS
|
||||||
|
to use a statically allocated array as the interrupt stack. Alternative leave
|
||||||
|
configISR_STACK_SIZE_WORDS undefined and update the linker script so that a
|
||||||
|
linker variable names __freertos_irq_stack_top has the same value as the top
|
||||||
|
of the stack used by main. Using the linker script method will repurpose the
|
||||||
|
stack that was used by main before the scheduler was started for use as the
|
||||||
|
interrupt stack after the scheduler has started. */
|
||||||
|
#ifdef configISR_STACK_SIZE_WORDS
|
||||||
|
static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };
|
||||||
|
const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] );
|
||||||
|
|
||||||
|
/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
|
||||||
|
the task stacks, and so will legitimately appear in many positions within
|
||||||
|
the ISR stack. */
|
||||||
|
#define portISR_STACK_FILL_BYTE 0xee
|
||||||
|
#else
|
||||||
|
/* __freertos_irq_stack_top define by .ld file */
|
||||||
|
extern const uint32_t __freertos_irq_stack_top[];
|
||||||
|
const StackType_t xISRStackTop = ( StackType_t ) __freertos_irq_stack_top;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
|
||||||
|
/*
|
||||||
|
* Setup the timer to generate the tick interrupts. The implementation in this
|
||||||
|
* file is weak to allow application writers to change the timer used to
|
||||||
|
* generate the tick interrupt.
|
||||||
|
*/
|
||||||
|
void vPortSetupTimerInterrupt( void ) __attribute__(( weak ));
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
#if( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 )
|
||||||
|
/* Used to program the machine timer compare register. */
|
||||||
|
uint64_t ullNextTime = 0ULL;
|
||||||
|
const uint64_t *pullNextTime = &ullNextTime;
|
||||||
|
const uint64_t uxTimerIncrementsForOneTick = ( uint64_t) ( ( configCPU_CLOCK_HZ )/( configTICK_RATE_HZ ) ); /* Assumes increment won't go over 32-bits. */
|
||||||
|
uint64_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS;
|
||||||
|
volatile uint64_t * pullMachineTimerCompareRegister = NULL;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
|
||||||
|
stack checking. A problem in the ISR stack will trigger an assert, not call the
|
||||||
|
stack overflow hook function (because the stack overflow hook is specific to a
|
||||||
|
task stack, not the ISR stack). */
|
||||||
|
#if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 )
|
||||||
|
#warning This path not tested, or even compiled yet.
|
||||||
|
|
||||||
|
static const uint8_t ucExpectedStackBytes[] = {
|
||||||
|
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||||
|
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||||
|
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||||
|
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, \
|
||||||
|
portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE }; \
|
||||||
|
|
||||||
|
#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
|
||||||
|
#else
|
||||||
|
/* Define the function away. */
|
||||||
|
#define portCHECK_ISR_STACK()
|
||||||
|
#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
#if( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 )
|
||||||
|
|
||||||
|
void vPortSetupTimerInterrupt( void )
|
||||||
|
{
|
||||||
|
uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
|
||||||
|
volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( ( configMTIME_BASE_ADDRESS ) + 4UL ); /* 8-byte typer so high 32-bit word is 4 bytes up. */
|
||||||
|
volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configMTIME_BASE_ADDRESS );
|
||||||
|
volatile uint32_t ulHartId;
|
||||||
|
|
||||||
|
__asm volatile( "csrr %0, mhartid" : "=r"( ulHartId ) );
|
||||||
|
pullMachineTimerCompareRegister = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) );
|
||||||
|
|
||||||
|
do
|
||||||
|
{
|
||||||
|
ulCurrentTimeHigh = *pulTimeHigh;
|
||||||
|
ulCurrentTimeLow = *pulTimeLow;
|
||||||
|
} while( ulCurrentTimeHigh != *pulTimeHigh );
|
||||||
|
|
||||||
|
ullNextTime = ( uint64_t ) ulCurrentTimeHigh;
|
||||||
|
ullNextTime <<= 32ULL; /* High 4-byte word is 32-bits up. */
|
||||||
|
ullNextTime |= ( uint64_t ) ulCurrentTimeLow;
|
||||||
|
ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
|
||||||
|
*pullMachineTimerCompareRegister = ullNextTime;
|
||||||
|
|
||||||
|
/* Prepare the time to use after the next tick interrupt. */
|
||||||
|
ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
|
||||||
|
}
|
||||||
|
|
||||||
|
#else
|
||||||
|
|
||||||
|
/* just for wch's systick,don't have mtime */
|
||||||
|
void vPortSetupTimerInterrupt( void )
|
||||||
|
{
|
||||||
|
/* set software is lowest priority */
|
||||||
|
NVIC_SetPriority(Software_IRQn,0xf0);
|
||||||
|
/* set systick is lowest priority */
|
||||||
|
NVIC_SetPriority(SysTicK_IRQn,0xf0);
|
||||||
|
|
||||||
|
SysTick->CTLR= 0;
|
||||||
|
SysTick->SR = 0;
|
||||||
|
SysTick->CNT = 0;
|
||||||
|
SysTick->CMP = configCPU_CLOCK_HZ/configTICK_RATE_HZ;
|
||||||
|
SysTick->CTLR= 0xf;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIME_BASE_ADDRESS != 0 ) */
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
BaseType_t xPortStartScheduler( void )
|
||||||
|
{
|
||||||
|
extern void xPortStartFirstTask( void );
|
||||||
|
|
||||||
|
#if( configASSERT_DEFINED == 1 )
|
||||||
|
{
|
||||||
|
volatile uint32_t mtvec = 0;
|
||||||
|
|
||||||
|
/* Check the least significant two bits of mtvec are 0b11 - indicating
|
||||||
|
multiply vector mode. */
|
||||||
|
__asm volatile( "csrr %0, mtvec" : "=r"( mtvec ) );
|
||||||
|
configASSERT( ( mtvec & 0x03UL ) == 0x3 );
|
||||||
|
|
||||||
|
/* Check alignment of the interrupt stack - which is the same as the
|
||||||
|
stack that was being used by main() prior to the scheduler being
|
||||||
|
started. */
|
||||||
|
configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 );
|
||||||
|
|
||||||
|
#ifdef configISR_STACK_SIZE_WORDS
|
||||||
|
{
|
||||||
|
memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
|
||||||
|
}
|
||||||
|
#endif /* configISR_STACK_SIZE_WORDS */
|
||||||
|
}
|
||||||
|
#endif /* configASSERT_DEFINED */
|
||||||
|
|
||||||
|
/* If there is a CLINT then it is ok to use the default implementation
|
||||||
|
in this file, otherwise vPortSetupTimerInterrupt() must be implemented to
|
||||||
|
configure whichever clock is to be used to generate the tick interrupt. */
|
||||||
|
vPortSetupTimerInterrupt();
|
||||||
|
|
||||||
|
#if( ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) )
|
||||||
|
{
|
||||||
|
/* Enable mtime and external interrupts. 1<<7 for timer interrupt, 1<<11
|
||||||
|
for external interrupt. _RB_ What happens here when mtime is not present as
|
||||||
|
with pulpino? */
|
||||||
|
NVIC_EnableIRQ(SysTicK_IRQn);
|
||||||
|
NVIC_EnableIRQ(Software_IRQn);
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
{
|
||||||
|
/* Enable external interrupts,global interrupt is enabled at first task start. */
|
||||||
|
NVIC_EnableIRQ(SysTicK_IRQn);
|
||||||
|
NVIC_EnableIRQ(Software_IRQn);
|
||||||
|
}
|
||||||
|
#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) */
|
||||||
|
|
||||||
|
/* Initialise the critical nesting count ready for the first task. */
|
||||||
|
uxCriticalNesting = 0;
|
||||||
|
xPortStartFirstTask();
|
||||||
|
|
||||||
|
/* Should not get here as after calling xPortStartFirstTask() only tasks
|
||||||
|
should be executing. */
|
||||||
|
return pdFAIL;
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
void vPortEndScheduler( void )
|
||||||
|
{
|
||||||
|
/* Not implemented. */
|
||||||
|
for( ;; );
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
void SysTick_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||||
|
void SysTick_Handler( void )
|
||||||
|
{
|
||||||
|
GET_INT_SP();
|
||||||
|
portDISABLE_INTERRUPTS();
|
||||||
|
SysTick->SR=0;
|
||||||
|
if( xTaskIncrementTick() != pd0 )
|
||||||
|
{
|
||||||
|
portYIELD();
|
||||||
|
}
|
||||||
|
portENABLE_INTERRUPTS();
|
||||||
|
FREE_INT_SP();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
void vPortEnterCritical( void )
|
||||||
|
{
|
||||||
|
portDISABLE_INTERRUPTS();
|
||||||
|
uxCriticalNesting++;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
void vPortExitCritical( void )
|
||||||
|
{
|
||||||
|
configASSERT( uxCriticalNesting );
|
||||||
|
uxCriticalNesting--;
|
||||||
|
|
||||||
|
if( uxCriticalNesting == 0 )
|
||||||
|
{
|
||||||
|
portENABLE_INTERRUPTS();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
portUBASE_TYPE xPortSetInterruptMask(void)
|
||||||
|
{
|
||||||
|
portUBASE_TYPE uvalue=0;
|
||||||
|
__asm volatile("csrrw %0, mstatus, %1":"=r"(uvalue):"r"(0x7800));
|
||||||
|
return uvalue;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
void vPortClearInterruptMask(portUBASE_TYPE uvalue)
|
||||||
|
{
|
||||||
|
__asm volatile("csrw mstatus, %0"::"r"(uvalue));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
363
FreeRTOS/portable/GCC/RISC-V/portASM.S
Normal file
363
FreeRTOS/portable/GCC/RISC-V/portASM.S
Normal file
@@ -0,0 +1,363 @@
|
|||||||
|
/*
|
||||||
|
* FreeRTOS Kernel V10.4.6
|
||||||
|
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: MIT
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* https://www.FreeRTOS.org
|
||||||
|
* https://github.com/FreeRTOS
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* The FreeRTOS kernel's RISC-V port is split between the the code that is
|
||||||
|
* common across all currently supported RISC-V chips (implementations of the
|
||||||
|
* RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
|
||||||
|
*
|
||||||
|
* + The code that is common to all RISC-V chips is implemented in
|
||||||
|
* FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one
|
||||||
|
* portASM.S file because the same file is used no matter which RISC-V chip is
|
||||||
|
* in use.
|
||||||
|
*
|
||||||
|
* + The code that tailors the kernel's RISC-V port to a specific RISC-V
|
||||||
|
* chip is implemented in freertos_risc_v_chip_specific_extensions.h. There
|
||||||
|
* is one freertos_risc_v_chip_specific_extensions.h that can be used with any
|
||||||
|
* RISC-V chip that both includes a standard CLINT and does not add to the
|
||||||
|
* base set of RISC-V registers. There are additional
|
||||||
|
* freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations
|
||||||
|
* that do not include a standard CLINT or do add to the base set of RISC-V
|
||||||
|
* registers.
|
||||||
|
*
|
||||||
|
* CARE MUST BE TAKEN TO INCLDUE THE CORRECT
|
||||||
|
* freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP
|
||||||
|
* IN USE. To include the correct freertos_risc_v_chip_specific_extensions.h
|
||||||
|
* header file ensure the path to the correct header file is in the assembler's
|
||||||
|
* include path.
|
||||||
|
*
|
||||||
|
* This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips
|
||||||
|
* that include a standard CLINT and do not add to the base set of RISC-V
|
||||||
|
* registers.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#if __riscv_xlen == 64
|
||||||
|
#define portWORD_SIZE 8
|
||||||
|
#define store_x sd
|
||||||
|
#define load_x ld
|
||||||
|
#elif __riscv_xlen == 32
|
||||||
|
#define store_x sw
|
||||||
|
#define load_x lw
|
||||||
|
#define portWORD_SIZE 4
|
||||||
|
#else
|
||||||
|
#error Assembler did not define __riscv_xlen
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* we define float registers at specific_extensions.h, V30x support hardware floating point unit
|
||||||
|
can be enable by defined ARCH_FPU*/
|
||||||
|
#include "freertos_risc_v_chip_specific_extensions.h"
|
||||||
|
|
||||||
|
|
||||||
|
/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line
|
||||||
|
definitions. */
|
||||||
|
#if defined( portasmHAS_CLINT ) && defined( portasmHAS_MTIME )
|
||||||
|
#error The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME. portasmHAS_CLINT and portasmHAS_MTIME cannot both be defined at once. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef portasmHAS_CLINT
|
||||||
|
#warning The portasmHAS_CLINT constant has been deprecated. Please replace it with portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT. For now portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT are derived from portasmHAS_CLINT. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
|
||||||
|
#define portasmHAS_MTIME portasmHAS_CLINT
|
||||||
|
#define portasmHAS_SIFIVE_CLINT portasmHAS_CLINT
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef portasmHAS_MTIME
|
||||||
|
#error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_MTIME to either 1 (MTIME clock present) or 0 (MTIME clock not present). See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef portasmHANDLE_INTERRUPT /* don't need this define */
|
||||||
|
# #error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts. portasmHANDLE_INTERRUPT can be defined on the assembler command line or in the appropriate freertos_risc_v_chip_specific_extensions.h header file. https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef portasmHAS_SIFIVE_CLINT
|
||||||
|
#define portasmHAS_SIFIVE_CLINT 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Only the standard core registers are stored by default. Any additional
|
||||||
|
registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and
|
||||||
|
portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip
|
||||||
|
specific version of freertos_risc_v_chip_specific_extensions.h. See the notes
|
||||||
|
at the top of this file. */
|
||||||
|
#define portCONTEXT_SIZE ( 30 * portWORD_SIZE )
|
||||||
|
|
||||||
|
.global xPortStartFirstTask
|
||||||
|
.global SW_Handler
|
||||||
|
.global pxPortInitialiseStack
|
||||||
|
|
||||||
|
.extern pxCurrentTCB
|
||||||
|
.extern vTaskSwitchContext
|
||||||
|
.extern xISRStackTop
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
.align 8
|
||||||
|
.func
|
||||||
|
SW_Handler:
|
||||||
|
addi sp, sp, -portCONTEXT_SIZE
|
||||||
|
store_x x1, 1 * portWORD_SIZE( sp )
|
||||||
|
store_x x5, 2 * portWORD_SIZE( sp )
|
||||||
|
store_x x6, 3 * portWORD_SIZE( sp )
|
||||||
|
store_x x7, 4 * portWORD_SIZE( sp )
|
||||||
|
store_x x8, 5 * portWORD_SIZE( sp )
|
||||||
|
store_x x9, 6 * portWORD_SIZE( sp )
|
||||||
|
store_x x10, 7 * portWORD_SIZE( sp )
|
||||||
|
store_x x11, 8 * portWORD_SIZE( sp )
|
||||||
|
store_x x12, 9 * portWORD_SIZE( sp )
|
||||||
|
store_x x13, 10 * portWORD_SIZE( sp )
|
||||||
|
store_x x14, 11 * portWORD_SIZE( sp )
|
||||||
|
store_x x15, 12 * portWORD_SIZE( sp )
|
||||||
|
store_x x16, 13 * portWORD_SIZE( sp )
|
||||||
|
store_x x17, 14 * portWORD_SIZE( sp )
|
||||||
|
store_x x18, 15 * portWORD_SIZE( sp )
|
||||||
|
store_x x19, 16 * portWORD_SIZE( sp )
|
||||||
|
store_x x20, 17 * portWORD_SIZE( sp )
|
||||||
|
store_x x21, 18 * portWORD_SIZE( sp )
|
||||||
|
store_x x22, 19 * portWORD_SIZE( sp )
|
||||||
|
store_x x23, 20 * portWORD_SIZE( sp )
|
||||||
|
store_x x24, 21 * portWORD_SIZE( sp )
|
||||||
|
store_x x25, 22 * portWORD_SIZE( sp )
|
||||||
|
store_x x26, 23 * portWORD_SIZE( sp )
|
||||||
|
store_x x27, 24 * portWORD_SIZE( sp )
|
||||||
|
store_x x28, 25 * portWORD_SIZE( sp )
|
||||||
|
store_x x29, 26 * portWORD_SIZE( sp )
|
||||||
|
store_x x30, 27 * portWORD_SIZE( sp )
|
||||||
|
store_x x31, 28 * portWORD_SIZE( sp )
|
||||||
|
|
||||||
|
csrr t0, mstatus /* Required for MPIE bit. */
|
||||||
|
store_x t0, 29 * portWORD_SIZE( sp )
|
||||||
|
|
||||||
|
portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
|
||||||
|
|
||||||
|
load_x t0, pxCurrentTCB /* Load pxCurrentTCB. */
|
||||||
|
store_x sp, 0( t0 ) /* Write sp to first TCB member. */
|
||||||
|
|
||||||
|
csrr a1, mepc
|
||||||
|
store_x a1, 0( sp ) /* Save updated exception return address. */
|
||||||
|
|
||||||
|
addi a1, x0, 0x20
|
||||||
|
csrs 0x804, a1
|
||||||
|
|
||||||
|
load_x sp, xISRStackTop /* Switch to ISR stack before function call. */
|
||||||
|
jal vTaskSwitchContext
|
||||||
|
|
||||||
|
processed_source:
|
||||||
|
load_x t1, pxCurrentTCB /* Load pxCurrentTCB. */
|
||||||
|
load_x sp, 0( t1 ) /* Read sp from first TCB member. */
|
||||||
|
|
||||||
|
/* Load mret with the address of the next instruction in the task to run next. */
|
||||||
|
load_x t0, 0( sp )
|
||||||
|
csrw mepc, t0
|
||||||
|
|
||||||
|
portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
|
||||||
|
|
||||||
|
/* Load mstatus with the interrupt enable bits used by the task. */
|
||||||
|
load_x t0, 29 * portWORD_SIZE( sp )
|
||||||
|
csrw mstatus, t0 /* Required for MPIE bit. */
|
||||||
|
|
||||||
|
load_x x1, 1 * portWORD_SIZE( sp )
|
||||||
|
load_x x5, 2 * portWORD_SIZE( sp ) /* t0 */
|
||||||
|
load_x x6, 3 * portWORD_SIZE( sp ) /* t1 */
|
||||||
|
load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */
|
||||||
|
load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
|
||||||
|
load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
|
||||||
|
load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */
|
||||||
|
load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */
|
||||||
|
load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */
|
||||||
|
load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */
|
||||||
|
load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */
|
||||||
|
load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */
|
||||||
|
load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */
|
||||||
|
load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */
|
||||||
|
load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */
|
||||||
|
load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */
|
||||||
|
load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */
|
||||||
|
load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */
|
||||||
|
load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */
|
||||||
|
load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */
|
||||||
|
load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */
|
||||||
|
load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */
|
||||||
|
load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */
|
||||||
|
load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */
|
||||||
|
load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */
|
||||||
|
load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */
|
||||||
|
load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */
|
||||||
|
load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */
|
||||||
|
addi sp, sp, portCONTEXT_SIZE
|
||||||
|
|
||||||
|
mret
|
||||||
|
.endfunc
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
.align 8
|
||||||
|
.func
|
||||||
|
xPortStartFirstTask:
|
||||||
|
|
||||||
|
/* if it is an assembly entry code, the SP offset value is determined by the assembly code,
|
||||||
|
but the C code is determined by the compiler, so we subtract 512 here as a reservation.
|
||||||
|
When entering the interrupt function of C code, the compiler automatically presses the stack
|
||||||
|
into the task stack. We can only change the SP value used by the calling function after switching
|
||||||
|
the interrupt stack.This problem can be solved by modifying the interrupt to the assembly entry,
|
||||||
|
and there is no need to reserve 512 bytes. You only need to switch the interrupt stack at the
|
||||||
|
beginning of the interrupt function */
|
||||||
|
lw t0, xISRStackTop
|
||||||
|
addi t0, t0, -512
|
||||||
|
csrw mscratch,t0
|
||||||
|
|
||||||
|
load_x sp, pxCurrentTCB /* Load pxCurrentTCB. */
|
||||||
|
load_x sp, 0( sp ) /* Read sp from first TCB member. */
|
||||||
|
|
||||||
|
load_x x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
|
||||||
|
|
||||||
|
portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
|
||||||
|
|
||||||
|
load_x x6, 3 * portWORD_SIZE( sp ) /* t1 */
|
||||||
|
load_x x7, 4 * portWORD_SIZE( sp ) /* t2 */
|
||||||
|
load_x x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
|
||||||
|
load_x x9, 6 * portWORD_SIZE( sp ) /* s1 */
|
||||||
|
load_x x10, 7 * portWORD_SIZE( sp ) /* a0 */
|
||||||
|
load_x x11, 8 * portWORD_SIZE( sp ) /* a1 */
|
||||||
|
load_x x12, 9 * portWORD_SIZE( sp ) /* a2 */
|
||||||
|
load_x x13, 10 * portWORD_SIZE( sp ) /* a3 */
|
||||||
|
load_x x14, 11 * portWORD_SIZE( sp ) /* a4 */
|
||||||
|
load_x x15, 12 * portWORD_SIZE( sp ) /* a5 */
|
||||||
|
load_x x16, 13 * portWORD_SIZE( sp ) /* a6 */
|
||||||
|
load_x x17, 14 * portWORD_SIZE( sp ) /* a7 */
|
||||||
|
load_x x18, 15 * portWORD_SIZE( sp ) /* s2 */
|
||||||
|
load_x x19, 16 * portWORD_SIZE( sp ) /* s3 */
|
||||||
|
load_x x20, 17 * portWORD_SIZE( sp ) /* s4 */
|
||||||
|
load_x x21, 18 * portWORD_SIZE( sp ) /* s5 */
|
||||||
|
load_x x22, 19 * portWORD_SIZE( sp ) /* s6 */
|
||||||
|
load_x x23, 20 * portWORD_SIZE( sp ) /* s7 */
|
||||||
|
load_x x24, 21 * portWORD_SIZE( sp ) /* s8 */
|
||||||
|
load_x x25, 22 * portWORD_SIZE( sp ) /* s9 */
|
||||||
|
load_x x26, 23 * portWORD_SIZE( sp ) /* s10 */
|
||||||
|
load_x x27, 24 * portWORD_SIZE( sp ) /* s11 */
|
||||||
|
load_x x28, 25 * portWORD_SIZE( sp ) /* t3 */
|
||||||
|
load_x x29, 26 * portWORD_SIZE( sp ) /* t4 */
|
||||||
|
load_x x30, 27 * portWORD_SIZE( sp ) /* t5 */
|
||||||
|
load_x x31, 28 * portWORD_SIZE( sp ) /* t6 */
|
||||||
|
|
||||||
|
load_x x5, 29 * portWORD_SIZE( sp ) /* Initial mstatus into x5 (t0) */
|
||||||
|
addi x5, x5, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */
|
||||||
|
csrrw x0, mstatus, x5 /* Interrupts enabled from here! */
|
||||||
|
load_x x5, 2 * portWORD_SIZE( sp ) /* Initial x5 (t0) value. */
|
||||||
|
|
||||||
|
addi sp, sp, portCONTEXT_SIZE
|
||||||
|
ret
|
||||||
|
.endfunc
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Unlike other ports pxPortInitialiseStack() is written in assembly code as it
|
||||||
|
* needs access to the portasmADDITIONAL_CONTEXT_SIZE constant. The prototype
|
||||||
|
* for the function is as per the other ports:
|
||||||
|
* StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters );
|
||||||
|
*
|
||||||
|
* As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in
|
||||||
|
* a1, and pvParameters in a2. The new top of stack is passed out in a0.
|
||||||
|
*
|
||||||
|
* RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
|
||||||
|
* for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
|
||||||
|
*
|
||||||
|
* Register ABI Name Description Saver
|
||||||
|
* x0 zero Hard-wired zero -
|
||||||
|
* x1 ra Return address Caller
|
||||||
|
* x2 sp Stack pointer Callee
|
||||||
|
* x3 gp Global pointer -
|
||||||
|
* x4 tp Thread pointer -
|
||||||
|
* x5-7 t0-2 Temporaries Caller
|
||||||
|
* x8 s0/fp Saved register/Frame pointer Callee
|
||||||
|
* x9 s1 Saved register Callee
|
||||||
|
* x10-11 a0-1 Function Arguments/return values Caller
|
||||||
|
* x12-17 a2-7 Function arguments Caller
|
||||||
|
* x18-27 s2-11 Saved registers Callee
|
||||||
|
* x28-31 t3-6 Temporaries Caller
|
||||||
|
*
|
||||||
|
* The RISC-V context is saved t FreeRTOS tasks in the following stack frame,
|
||||||
|
* where the global and thread pointers are currently assumed to be constant so
|
||||||
|
* are not saved:
|
||||||
|
*
|
||||||
|
* mstatus
|
||||||
|
* x31
|
||||||
|
* x30
|
||||||
|
* x29
|
||||||
|
* x28
|
||||||
|
* x27
|
||||||
|
* x26
|
||||||
|
* x25
|
||||||
|
* x24
|
||||||
|
* x23
|
||||||
|
* x22
|
||||||
|
* x21
|
||||||
|
* x20
|
||||||
|
* x19
|
||||||
|
* x18
|
||||||
|
* x17
|
||||||
|
* x16
|
||||||
|
* x15
|
||||||
|
* x14
|
||||||
|
* x13
|
||||||
|
* x12
|
||||||
|
* x11
|
||||||
|
* pvParameters
|
||||||
|
* x9
|
||||||
|
* x8
|
||||||
|
* x7
|
||||||
|
* x6
|
||||||
|
* x5
|
||||||
|
* portTASK_RETURN_ADDRESS
|
||||||
|
* [chip specific registers go here]
|
||||||
|
* pxCode
|
||||||
|
*/
|
||||||
|
.align 8
|
||||||
|
.func
|
||||||
|
pxPortInitialiseStack:
|
||||||
|
|
||||||
|
csrr t0, mstatus /* Obtain current mstatus value. */
|
||||||
|
andi t0, t0, ~0x8 /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the schedulre has been started, otherwise interrupts would be disabled anyway. */
|
||||||
|
addi t1, x0, 0x788 /* Generate the value 0x7880, which are the MPIE, MPP and FS bits to set in mstatus. */
|
||||||
|
slli t1, t1, 4
|
||||||
|
or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */
|
||||||
|
|
||||||
|
addi a0, a0, -portWORD_SIZE
|
||||||
|
store_x t0, 0(a0) /* mstatus onto the stack. */
|
||||||
|
addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x11-x31. */
|
||||||
|
store_x a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
|
||||||
|
addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9. */
|
||||||
|
store_x x0, 0(a0) /* Return address onto the stack, could be portTASK_RETURN_ADDRESS */
|
||||||
|
addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
|
||||||
|
chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */
|
||||||
|
beq t0, x0, 1f /* No more chip specific registers to save. */
|
||||||
|
addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */
|
||||||
|
store_x x0, 0(a0) /* Give the chip specific register an initial value of zero. */
|
||||||
|
addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */
|
||||||
|
j chip_specific_stack_frame /* Until no more chip specific registers. */
|
||||||
|
1:
|
||||||
|
addi a0, a0, -portWORD_SIZE
|
||||||
|
store_x a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */
|
||||||
|
ret
|
||||||
|
.endfunc
|
||||||
|
|
||||||
|
|
||||||
194
FreeRTOS/portable/GCC/RISC-V/portmacro.h
Normal file
194
FreeRTOS/portable/GCC/RISC-V/portmacro.h
Normal file
@@ -0,0 +1,194 @@
|
|||||||
|
/*
|
||||||
|
* FreeRTOS Kernel V10.4.6
|
||||||
|
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: MIT
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* https://www.FreeRTOS.org
|
||||||
|
* https://github.com/FreeRTOS
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
#ifndef PORTMACRO_H
|
||||||
|
#define PORTMACRO_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------
|
||||||
|
* Port specific definitions.
|
||||||
|
*
|
||||||
|
* The settings in this file configure FreeRTOS correctly for the
|
||||||
|
* given hardware and compiler.
|
||||||
|
*
|
||||||
|
* These settings should not be altered.
|
||||||
|
*-----------------------------------------------------------
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Type definitions. */
|
||||||
|
#if __riscv_xlen == 64
|
||||||
|
#define portSTACK_TYPE uint64_t
|
||||||
|
#define portBASE_TYPE int64_t
|
||||||
|
#define portUBASE_TYPE uint64_t
|
||||||
|
#define portMAX_DELAY ( TickType_t ) 0xffffffffffffffffUL
|
||||||
|
#define portPOINTER_SIZE_TYPE uint64_t
|
||||||
|
#elif __riscv_xlen == 32
|
||||||
|
#define portSTACK_TYPE uint32_t
|
||||||
|
#define portBASE_TYPE int32_t
|
||||||
|
#define portUBASE_TYPE uint32_t
|
||||||
|
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
|
||||||
|
#else
|
||||||
|
#error Assembler did not define __riscv_xlen
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
typedef portSTACK_TYPE StackType_t;
|
||||||
|
typedef portBASE_TYPE BaseType_t;
|
||||||
|
typedef portUBASE_TYPE UBaseType_t;
|
||||||
|
typedef portUBASE_TYPE TickType_t;
|
||||||
|
|
||||||
|
/* Legacy type definitions. */
|
||||||
|
#define portCHAR char
|
||||||
|
#define portFLOAT float
|
||||||
|
#define portDOUBLE double
|
||||||
|
#define portLONG long
|
||||||
|
#define portSHORT short
|
||||||
|
|
||||||
|
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
|
||||||
|
not need to be guarded with a critical section. */
|
||||||
|
#define portTICK_TYPE_IS_ATOMIC 1
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Architecture specifics. */
|
||||||
|
#define portSTACK_GROWTH ( -1 )
|
||||||
|
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
|
||||||
|
#ifdef __riscv64
|
||||||
|
#error This is the RV32 port that has not yet been adapted for 64.
|
||||||
|
#define portBYTE_ALIGNMENT 16
|
||||||
|
#else
|
||||||
|
#define portBYTE_ALIGNMENT 16
|
||||||
|
#endif
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Scheduler utilities. */
|
||||||
|
extern void vTaskSwitchContext( void );
|
||||||
|
#define portYIELD() NVIC_SetPendingIRQ(Software_IRQn)
|
||||||
|
#define portEND_SWITCHING_ISR( xSwitchRequired ) do { if( xSwitchRequired ) portYIELD(); } while( 0 )
|
||||||
|
#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Critical section management. */
|
||||||
|
extern void vPortEnterCritical( void );
|
||||||
|
extern void vPortExitCritical( void );
|
||||||
|
extern portUBASE_TYPE xPortSetInterruptMask(void);
|
||||||
|
extern void vPortClearInterruptMask(portUBASE_TYPE uvalue);
|
||||||
|
|
||||||
|
#define portSET_INTERRUPT_MASK_FROM_ISR() xPortSetInterruptMask()
|
||||||
|
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) vPortClearInterruptMask(uxSavedStatusValue)
|
||||||
|
#define portDISABLE_INTERRUPTS() __asm volatile( "csrw mstatus,%0" ::"r"(0x7800) )
|
||||||
|
#define portENABLE_INTERRUPTS() __asm volatile( "csrw mstatus,%0" ::"r"(0x7888) )
|
||||||
|
#define portENTER_CRITICAL() vPortEnterCritical()
|
||||||
|
#define portEXIT_CRITICAL() vPortExitCritical()
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* switch interrupt sp, sp is saved at first task switch. */
|
||||||
|
|
||||||
|
#define GET_INT_SP() __asm volatile("csrrw sp,mscratch,sp")
|
||||||
|
#define FREE_INT_SP() __asm volatile("csrrw sp,mscratch,sp")
|
||||||
|
/*-------------------------------------------------------------*/
|
||||||
|
|
||||||
|
|
||||||
|
/* Architecture specific optimisations. */
|
||||||
|
#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
|
||||||
|
#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
|
||||||
|
|
||||||
|
/* Check the configuration. */
|
||||||
|
#if( configMAX_PRIORITIES > 32 )
|
||||||
|
#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32. It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Store/clear the ready priorities in a bit map. */
|
||||||
|
#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
|
||||||
|
#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - __builtin_clz( uxReadyPriorities ) )
|
||||||
|
|
||||||
|
#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
|
||||||
|
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* Task function macros as described on the FreeRTOS.org WEB site. These are
|
||||||
|
not necessary for to use this port. They are defined so the common demo files
|
||||||
|
(which build with all the ports) will build. */
|
||||||
|
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||||
|
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
#define portNOP() __asm volatile ( " nop " )
|
||||||
|
|
||||||
|
#define portINLINE __inline
|
||||||
|
|
||||||
|
#ifndef portFORCE_INLINE
|
||||||
|
#define portFORCE_INLINE inline __attribute__(( always_inline))
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
|
||||||
|
/* configCLINT_BASE_ADDRESS is a legacy definition that was replaced by the
|
||||||
|
configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions. For
|
||||||
|
backward compatibility derive the newer definitions from the old if the old
|
||||||
|
definition is found. */
|
||||||
|
#if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 )
|
||||||
|
/* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate
|
||||||
|
there was no CLINT. Equivalent now is to set the MTIME and MTIMECMP
|
||||||
|
addresses to 0. */
|
||||||
|
#define configMTIME_BASE_ADDRESS ( 0 )
|
||||||
|
#define configMTIMECMP_BASE_ADDRESS ( 0 )
|
||||||
|
#elif defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS )
|
||||||
|
/* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of
|
||||||
|
the CLINT. Equivalent now is to derive the MTIME and MTIMECMP addresses
|
||||||
|
from the CLINT address. */
|
||||||
|
#define configMTIME_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL )
|
||||||
|
#define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL )
|
||||||
|
#elif !defined( configMTIME_BASE_ADDRESS ) || !defined( configMTIMECMP_BASE_ADDRESS )
|
||||||
|
#error configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h. Set them to zero if there is no MTIME (machine time) clock. See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* PORTMACRO_H */
|
||||||
|
|
||||||
23
FreeRTOS/portable/GCC/RISC-V/readme.txt
Normal file
23
FreeRTOS/portable/GCC/RISC-V/readme.txt
Normal file
@@ -0,0 +1,23 @@
|
|||||||
|
/*
|
||||||
|
* The FreeRTOS kernel's RISC-V port is split between the the code that is
|
||||||
|
* common across all currently supported RISC-V chips (implementations of the
|
||||||
|
* RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
|
||||||
|
*
|
||||||
|
* + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
|
||||||
|
* is common to all currently supported RISC-V chips. There is only one
|
||||||
|
* portASM.S file because the same file is built for all RISC-V target chips.
|
||||||
|
*
|
||||||
|
* + Header files called freertos_risc_v_chip_specific_extensions.h contain the
|
||||||
|
* code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
|
||||||
|
* chip. There are multiple freertos_risc_v_chip_specific_extensions.h files
|
||||||
|
* as there are multiple RISC-V chip implementations.
|
||||||
|
*
|
||||||
|
* !!!NOTE!!!
|
||||||
|
* TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
|
||||||
|
* HEADER FILE FOR THE CHIP IN USE. This is done using the assembler's (not the
|
||||||
|
* compiler's!) include path. For example, if the chip in use includes a core
|
||||||
|
* local interrupter (CLINT) and does not include any chip specific register
|
||||||
|
* extensions then add the path below to the assembler's include path:
|
||||||
|
* FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
|
||||||
|
*
|
||||||
|
*/
|
||||||
5
FreeRTOS/portable/MemMang/ReadMe.url
Normal file
5
FreeRTOS/portable/MemMang/ReadMe.url
Normal file
@@ -0,0 +1,5 @@
|
|||||||
|
[{000214A0-0000-0000-C000-000000000046}]
|
||||||
|
Prop3=19,2
|
||||||
|
[InternetShortcut]
|
||||||
|
URL=https://www.FreeRTOS.org/a00111.html
|
||||||
|
IDList=
|
||||||
504
FreeRTOS/portable/MemMang/heap_4.c
Normal file
504
FreeRTOS/portable/MemMang/heap_4.c
Normal file
@@ -0,0 +1,504 @@
|
|||||||
|
/*
|
||||||
|
* FreeRTOS Kernel V10.4.6
|
||||||
|
* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
|
||||||
|
*
|
||||||
|
* SPDX-License-Identifier: MIT
|
||||||
|
*
|
||||||
|
* Permission is hereby granted, free of charge, to any person obtaining a copy of
|
||||||
|
* this software and associated documentation files (the "Software"), to deal in
|
||||||
|
* the Software without restriction, including without limitation the rights to
|
||||||
|
* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
||||||
|
* the Software, and to permit persons to whom the Software is furnished to do so,
|
||||||
|
* subject to the following conditions:
|
||||||
|
*
|
||||||
|
* The above copyright notice and this permission notice shall be included in all
|
||||||
|
* copies or substantial portions of the Software.
|
||||||
|
*
|
||||||
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||||
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
|
||||||
|
* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
|
||||||
|
* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
|
||||||
|
* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||||
|
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||||
|
*
|
||||||
|
* https://www.FreeRTOS.org
|
||||||
|
* https://github.com/FreeRTOS
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* A sample implementation of pvPortMalloc() and vPortFree() that combines
|
||||||
|
* (coalescences) adjacent memory blocks as they are freed, and in so doing
|
||||||
|
* limits memory fragmentation.
|
||||||
|
*
|
||||||
|
* See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the
|
||||||
|
* memory management pages of https://www.FreeRTOS.org for more information.
|
||||||
|
*/
|
||||||
|
#include <stdlib.h>
|
||||||
|
|
||||||
|
/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
|
||||||
|
* all the API functions to use the MPU wrappers. That should only be done when
|
||||||
|
* task.h is included from an application file. */
|
||||||
|
#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
|
||||||
|
|
||||||
|
#include "FreeRTOS.h"
|
||||||
|
#include "task.h"
|
||||||
|
|
||||||
|
#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
|
||||||
|
|
||||||
|
#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
|
||||||
|
#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Block sizes must not get too small. */
|
||||||
|
#define heapMINIMUM_BLOCK_SIZE ( ( size_t ) ( xHeapStructSize << 1 ) )
|
||||||
|
|
||||||
|
/* Assumes 8bit bytes! */
|
||||||
|
#define heapBITS_PER_BYTE ( ( size_t ) 8 )
|
||||||
|
|
||||||
|
/* Allocate the memory for the heap. */
|
||||||
|
#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
|
||||||
|
|
||||||
|
/* The application writer has already defined the array used for the RTOS
|
||||||
|
* heap - probably so it can be placed in a special segment or address. */
|
||||||
|
extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
|
||||||
|
#else
|
||||||
|
PRIVILEGED_DATA static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
|
||||||
|
#endif /* configAPPLICATION_ALLOCATED_HEAP */
|
||||||
|
|
||||||
|
/* Define the linked list structure. This is used to link free blocks in order
|
||||||
|
* of their memory address. */
|
||||||
|
typedef struct A_BLOCK_LINK
|
||||||
|
{
|
||||||
|
struct A_BLOCK_LINK * pxNextFreeBlock; /*<< The next free block in the list. */
|
||||||
|
size_t xBlockSize; /*<< The size of the free block. */
|
||||||
|
} BlockLink_t;
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Inserts a block of memory that is being freed into the correct position in
|
||||||
|
* the list of free memory blocks. The block being freed will be merged with
|
||||||
|
* the block in front it and/or the block behind it if the memory blocks are
|
||||||
|
* adjacent to each other.
|
||||||
|
*/
|
||||||
|
static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Called automatically to setup the required heap structures the first time
|
||||||
|
* pvPortMalloc() is called.
|
||||||
|
*/
|
||||||
|
static void prvHeapInit( void ) PRIVILEGED_FUNCTION;
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
/* The size of the structure placed at the beginning of each allocated memory
|
||||||
|
* block must by correctly byte aligned. */
|
||||||
|
static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
|
||||||
|
|
||||||
|
/* Create a couple of list links to mark the start and end of the list. */
|
||||||
|
PRIVILEGED_DATA static BlockLink_t xStart, * pxEnd = NULL;
|
||||||
|
|
||||||
|
/* Keeps track of the number of calls to allocate and free memory as well as the
|
||||||
|
* number of free bytes remaining, but says nothing about fragmentation. */
|
||||||
|
PRIVILEGED_DATA static size_t xFreeBytesRemaining = 0U;
|
||||||
|
PRIVILEGED_DATA static size_t xMinimumEverFreeBytesRemaining = 0U;
|
||||||
|
PRIVILEGED_DATA static size_t xNumberOfSuccessfulAllocations = 0;
|
||||||
|
PRIVILEGED_DATA static size_t xNumberOfSuccessfulFrees = 0;
|
||||||
|
|
||||||
|
/* Gets set to the top bit of an size_t type. When this bit in the xBlockSize
|
||||||
|
* member of an BlockLink_t structure is set then the block belongs to the
|
||||||
|
* application. When the bit is free the block is still part of the free heap
|
||||||
|
* space. */
|
||||||
|
PRIVILEGED_DATA static size_t xBlockAllocatedBit = 0;
|
||||||
|
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
void * pvPortMalloc( size_t xWantedSize )
|
||||||
|
{
|
||||||
|
BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink;
|
||||||
|
void * pvReturn = NULL;
|
||||||
|
|
||||||
|
vTaskSuspendAll();
|
||||||
|
{
|
||||||
|
/* If this is the first call to malloc then the heap will require
|
||||||
|
* initialisation to setup the list of free blocks. */
|
||||||
|
if( pxEnd == NULL )
|
||||||
|
{
|
||||||
|
prvHeapInit();
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
mtCOVERAGE_TEST_MARKER();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check the requested block size is not so large that the top bit is
|
||||||
|
* set. The top bit of the block size member of the BlockLink_t structure
|
||||||
|
* is used to determine who owns the block - the application or the
|
||||||
|
* kernel, so it must be free. */
|
||||||
|
if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
|
||||||
|
{
|
||||||
|
/* The wanted size must be increased so it can contain a BlockLink_t
|
||||||
|
* structure in addition to the requested amount of bytes. */
|
||||||
|
if( ( xWantedSize > 0 ) &&
|
||||||
|
( ( xWantedSize + xHeapStructSize ) > xWantedSize ) ) /* Overflow check */
|
||||||
|
{
|
||||||
|
xWantedSize += xHeapStructSize;
|
||||||
|
|
||||||
|
/* Ensure that blocks are always aligned. */
|
||||||
|
if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
|
||||||
|
{
|
||||||
|
/* Byte alignment required. Check for overflow. */
|
||||||
|
if( ( xWantedSize + ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ) )
|
||||||
|
> xWantedSize )
|
||||||
|
{
|
||||||
|
xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
|
||||||
|
configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
xWantedSize = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
mtCOVERAGE_TEST_MARKER();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
xWantedSize = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
|
||||||
|
{
|
||||||
|
/* Traverse the list from the start (lowest address) block until
|
||||||
|
* one of adequate size is found. */
|
||||||
|
pxPreviousBlock = &xStart;
|
||||||
|
pxBlock = xStart.pxNextFreeBlock;
|
||||||
|
|
||||||
|
while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
|
||||||
|
{
|
||||||
|
pxPreviousBlock = pxBlock;
|
||||||
|
pxBlock = pxBlock->pxNextFreeBlock;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* If the end marker was reached then a block of adequate size
|
||||||
|
* was not found. */
|
||||||
|
if( pxBlock != pxEnd )
|
||||||
|
{
|
||||||
|
/* Return the memory space pointed to - jumping over the
|
||||||
|
* BlockLink_t structure at its start. */
|
||||||
|
pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
|
||||||
|
|
||||||
|
/* This block is being returned for use so must be taken out
|
||||||
|
* of the list of free blocks. */
|
||||||
|
pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
|
||||||
|
|
||||||
|
/* If the block is larger than required it can be split into
|
||||||
|
* two. */
|
||||||
|
if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
|
||||||
|
{
|
||||||
|
/* This block is to be split into two. Create a new
|
||||||
|
* block following the number of bytes requested. The void
|
||||||
|
* cast is used to prevent byte alignment warnings from the
|
||||||
|
* compiler. */
|
||||||
|
pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
|
||||||
|
configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
|
||||||
|
|
||||||
|
/* Calculate the sizes of two blocks split from the
|
||||||
|
* single block. */
|
||||||
|
pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
|
||||||
|
pxBlock->xBlockSize = xWantedSize;
|
||||||
|
|
||||||
|
/* Insert the new block into the list of free blocks. */
|
||||||
|
prvInsertBlockIntoFreeList( pxNewBlockLink );
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
mtCOVERAGE_TEST_MARKER();
|
||||||
|
}
|
||||||
|
|
||||||
|
xFreeBytesRemaining -= pxBlock->xBlockSize;
|
||||||
|
|
||||||
|
if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
|
||||||
|
{
|
||||||
|
xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
mtCOVERAGE_TEST_MARKER();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* The block is being returned - it is allocated and owned
|
||||||
|
* by the application and has no "next" block. */
|
||||||
|
pxBlock->xBlockSize |= xBlockAllocatedBit;
|
||||||
|
pxBlock->pxNextFreeBlock = NULL;
|
||||||
|
xNumberOfSuccessfulAllocations++;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
mtCOVERAGE_TEST_MARKER();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
mtCOVERAGE_TEST_MARKER();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
mtCOVERAGE_TEST_MARKER();
|
||||||
|
}
|
||||||
|
|
||||||
|
traceMALLOC( pvReturn, xWantedSize );
|
||||||
|
}
|
||||||
|
( void ) xTaskResumeAll();
|
||||||
|
|
||||||
|
#if ( configUSE_MALLOC_FAILED_HOOK == 1 )
|
||||||
|
{
|
||||||
|
if( pvReturn == NULL )
|
||||||
|
{
|
||||||
|
extern void vApplicationMallocFailedHook( void );
|
||||||
|
vApplicationMallocFailedHook();
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
mtCOVERAGE_TEST_MARKER();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif /* if ( configUSE_MALLOC_FAILED_HOOK == 1 ) */
|
||||||
|
|
||||||
|
configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
|
||||||
|
return pvReturn;
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
void vPortFree( void * pv )
|
||||||
|
{
|
||||||
|
uint8_t * puc = ( uint8_t * ) pv;
|
||||||
|
BlockLink_t * pxLink;
|
||||||
|
|
||||||
|
if( pv != NULL )
|
||||||
|
{
|
||||||
|
/* The memory being freed will have an BlockLink_t structure immediately
|
||||||
|
* before it. */
|
||||||
|
puc -= xHeapStructSize;
|
||||||
|
|
||||||
|
/* This casting is to keep the compiler from issuing warnings. */
|
||||||
|
pxLink = ( void * ) puc;
|
||||||
|
|
||||||
|
/* Check the block is actually allocated. */
|
||||||
|
configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
|
||||||
|
configASSERT( pxLink->pxNextFreeBlock == NULL );
|
||||||
|
|
||||||
|
if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
|
||||||
|
{
|
||||||
|
if( pxLink->pxNextFreeBlock == NULL )
|
||||||
|
{
|
||||||
|
/* The block is being returned to the heap - it is no longer
|
||||||
|
* allocated. */
|
||||||
|
pxLink->xBlockSize &= ~xBlockAllocatedBit;
|
||||||
|
|
||||||
|
vTaskSuspendAll();
|
||||||
|
{
|
||||||
|
/* Add this block to the list of free blocks. */
|
||||||
|
xFreeBytesRemaining += pxLink->xBlockSize;
|
||||||
|
traceFREE( pv, pxLink->xBlockSize );
|
||||||
|
prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
|
||||||
|
xNumberOfSuccessfulFrees++;
|
||||||
|
}
|
||||||
|
( void ) xTaskResumeAll();
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
mtCOVERAGE_TEST_MARKER();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
mtCOVERAGE_TEST_MARKER();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
size_t xPortGetFreeHeapSize( void )
|
||||||
|
{
|
||||||
|
return xFreeBytesRemaining;
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
size_t xPortGetMinimumEverFreeHeapSize( void )
|
||||||
|
{
|
||||||
|
return xMinimumEverFreeBytesRemaining;
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
void vPortInitialiseBlocks( void )
|
||||||
|
{
|
||||||
|
/* This just exists to keep the linker quiet. */
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */
|
||||||
|
{
|
||||||
|
BlockLink_t * pxFirstFreeBlock;
|
||||||
|
uint8_t * pucAlignedHeap;
|
||||||
|
size_t uxAddress;
|
||||||
|
size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
|
||||||
|
|
||||||
|
/* Ensure the heap starts on a correctly aligned boundary. */
|
||||||
|
uxAddress = ( size_t ) ucHeap;
|
||||||
|
|
||||||
|
if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
|
||||||
|
{
|
||||||
|
uxAddress += ( portBYTE_ALIGNMENT - 1 );
|
||||||
|
uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
|
||||||
|
xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
|
||||||
|
}
|
||||||
|
|
||||||
|
pucAlignedHeap = ( uint8_t * ) uxAddress;
|
||||||
|
|
||||||
|
/* xStart is used to hold a pointer to the first item in the list of free
|
||||||
|
* blocks. The void cast is used to prevent compiler warnings. */
|
||||||
|
xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
|
||||||
|
xStart.xBlockSize = ( size_t ) 0;
|
||||||
|
|
||||||
|
/* pxEnd is used to mark the end of the list of free blocks and is inserted
|
||||||
|
* at the end of the heap space. */
|
||||||
|
uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
|
||||||
|
uxAddress -= xHeapStructSize;
|
||||||
|
uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
|
||||||
|
pxEnd = ( void * ) uxAddress;
|
||||||
|
pxEnd->xBlockSize = 0;
|
||||||
|
pxEnd->pxNextFreeBlock = NULL;
|
||||||
|
|
||||||
|
/* To start with there is a single free block that is sized to take up the
|
||||||
|
* entire heap space, minus the space taken by pxEnd. */
|
||||||
|
pxFirstFreeBlock = ( void * ) pucAlignedHeap;
|
||||||
|
pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
|
||||||
|
pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
|
||||||
|
|
||||||
|
/* Only one block exists - and it covers the entire usable heap space. */
|
||||||
|
xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
|
||||||
|
xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
|
||||||
|
|
||||||
|
/* Work out the position of the top bit in a size_t variable. */
|
||||||
|
xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) /* PRIVILEGED_FUNCTION */
|
||||||
|
{
|
||||||
|
BlockLink_t * pxIterator;
|
||||||
|
uint8_t * puc;
|
||||||
|
|
||||||
|
/* Iterate through the list until a block is found that has a higher address
|
||||||
|
* than the block being inserted. */
|
||||||
|
for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
|
||||||
|
{
|
||||||
|
/* Nothing to do here, just iterate to the right position. */
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Do the block being inserted, and the block it is being inserted after
|
||||||
|
* make a contiguous block of memory? */
|
||||||
|
puc = ( uint8_t * ) pxIterator;
|
||||||
|
|
||||||
|
if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
|
||||||
|
{
|
||||||
|
pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
|
||||||
|
pxBlockToInsert = pxIterator;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
mtCOVERAGE_TEST_MARKER();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Do the block being inserted, and the block it is being inserted before
|
||||||
|
* make a contiguous block of memory? */
|
||||||
|
puc = ( uint8_t * ) pxBlockToInsert;
|
||||||
|
|
||||||
|
if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
|
||||||
|
{
|
||||||
|
if( pxIterator->pxNextFreeBlock != pxEnd )
|
||||||
|
{
|
||||||
|
/* Form one big block from the two blocks. */
|
||||||
|
pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
|
||||||
|
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
pxBlockToInsert->pxNextFreeBlock = pxEnd;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* If the block being inserted plugged a gab, so was merged with the block
|
||||||
|
* before and the block after, then it's pxNextFreeBlock pointer will have
|
||||||
|
* already been set, and should not be set here as that would make it point
|
||||||
|
* to itself. */
|
||||||
|
if( pxIterator != pxBlockToInsert )
|
||||||
|
{
|
||||||
|
pxIterator->pxNextFreeBlock = pxBlockToInsert;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
mtCOVERAGE_TEST_MARKER();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/*-----------------------------------------------------------*/
|
||||||
|
|
||||||
|
void vPortGetHeapStats( HeapStats_t * pxHeapStats )
|
||||||
|
{
|
||||||
|
BlockLink_t * pxBlock;
|
||||||
|
size_t xBlocks = 0, xMaxSize = 0, xMinSize = portMAX_DELAY; /* portMAX_DELAY used as a portable way of getting the maximum value. */
|
||||||
|
|
||||||
|
vTaskSuspendAll();
|
||||||
|
{
|
||||||
|
pxBlock = xStart.pxNextFreeBlock;
|
||||||
|
|
||||||
|
/* pxBlock will be NULL if the heap has not been initialised. The heap
|
||||||
|
* is initialised automatically when the first allocation is made. */
|
||||||
|
if( pxBlock != NULL )
|
||||||
|
{
|
||||||
|
do
|
||||||
|
{
|
||||||
|
/* Increment the number of blocks and record the largest block seen
|
||||||
|
* so far. */
|
||||||
|
xBlocks++;
|
||||||
|
|
||||||
|
if( pxBlock->xBlockSize > xMaxSize )
|
||||||
|
{
|
||||||
|
xMaxSize = pxBlock->xBlockSize;
|
||||||
|
}
|
||||||
|
|
||||||
|
if( pxBlock->xBlockSize < xMinSize )
|
||||||
|
{
|
||||||
|
xMinSize = pxBlock->xBlockSize;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Move to the next block in the chain until the last block is
|
||||||
|
* reached. */
|
||||||
|
pxBlock = pxBlock->pxNextFreeBlock;
|
||||||
|
} while( pxBlock != pxEnd );
|
||||||
|
}
|
||||||
|
}
|
||||||
|
( void ) xTaskResumeAll();
|
||||||
|
|
||||||
|
pxHeapStats->xSizeOfLargestFreeBlockInBytes = xMaxSize;
|
||||||
|
pxHeapStats->xSizeOfSmallestFreeBlockInBytes = xMinSize;
|
||||||
|
pxHeapStats->xNumberOfFreeBlocks = xBlocks;
|
||||||
|
|
||||||
|
taskENTER_CRITICAL();
|
||||||
|
{
|
||||||
|
pxHeapStats->xAvailableHeapSpaceInBytes = xFreeBytesRemaining;
|
||||||
|
pxHeapStats->xNumberOfSuccessfulAllocations = xNumberOfSuccessfulAllocations;
|
||||||
|
pxHeapStats->xNumberOfSuccessfulFrees = xNumberOfSuccessfulFrees;
|
||||||
|
pxHeapStats->xMinimumEverFreeBytesRemaining = xMinimumEverFreeBytesRemaining;
|
||||||
|
}
|
||||||
|
taskEXIT_CRITICAL();
|
||||||
|
}
|
||||||
20
FreeRTOS/portable/readme.txt
Normal file
20
FreeRTOS/portable/readme.txt
Normal file
@@ -0,0 +1,20 @@
|
|||||||
|
Each real time kernel port consists of three files that contain the core kernel
|
||||||
|
components and are common to every port, and one or more files that are
|
||||||
|
specific to a particular microcontroller and/or compiler.
|
||||||
|
|
||||||
|
|
||||||
|
+ The FreeRTOS/Source/Portable/MemMang directory contains the five sample
|
||||||
|
memory allocators as described on the https://www.FreeRTOS.org WEB site.
|
||||||
|
|
||||||
|
+ The other directories each contain files specific to a particular
|
||||||
|
microcontroller or compiler, where the directory name denotes the compiler
|
||||||
|
specific files the directory contains.
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
For example, if you are interested in the [compiler] port for the [architecture]
|
||||||
|
microcontroller, then the port specific files are contained in
|
||||||
|
FreeRTOS/Source/Portable/[compiler]/[architecture] directory. If this is the
|
||||||
|
only port you are interested in then all the other directories can be
|
||||||
|
ignored.
|
||||||
|
|
||||||
3075
FreeRTOS/queue.c
Normal file
3075
FreeRTOS/queue.c
Normal file
File diff suppressed because it is too large
Load Diff
1307
FreeRTOS/stream_buffer.c
Normal file
1307
FreeRTOS/stream_buffer.c
Normal file
File diff suppressed because it is too large
Load Diff
5442
FreeRTOS/tasks.c
Normal file
5442
FreeRTOS/tasks.c
Normal file
File diff suppressed because it is too large
Load Diff
1119
FreeRTOS/timers.c
Normal file
1119
FreeRTOS/timers.c
Normal file
File diff suppressed because it is too large
Load Diff
186
Ld/Link.ld
Normal file
186
Ld/Link.ld
Normal file
@@ -0,0 +1,186 @@
|
|||||||
|
ENTRY( _start )
|
||||||
|
|
||||||
|
__stack_size = 2048;
|
||||||
|
|
||||||
|
PROVIDE( _stack_size = __stack_size );
|
||||||
|
|
||||||
|
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
/* CH32V30x_D8C - CH32V305RB-CH32V305FB
|
||||||
|
CH32V30x_D8 - CH32V303CB-CH32V303RB
|
||||||
|
*/
|
||||||
|
/**/
|
||||||
|
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 192K
|
||||||
|
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
|
||||||
|
|
||||||
|
|
||||||
|
/* CH32V30x_D8C - CH32V307VC-CH32V307WC-CH32V307RC-CH32V305CC
|
||||||
|
CH32V30x_D8 - CH32V303VC-CH32V303RC
|
||||||
|
FLASH + RAM supports the following configuration
|
||||||
|
For specific choices, please refer :CH32FV2x_V3xRM.PDF\Table 32-3
|
||||||
|
FLASH-192K + RAM-128K
|
||||||
|
FLASH-224K + RAM-96K
|
||||||
|
FLASH-256K + RAM-64K
|
||||||
|
FLASH-288K + RAM-32K
|
||||||
|
FLASH-128K + RAM-192K
|
||||||
|
|
||||||
|
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 288K
|
||||||
|
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K*/
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
|
||||||
|
.init :
|
||||||
|
{
|
||||||
|
_sinit = .;
|
||||||
|
. = ALIGN(4);
|
||||||
|
KEEP(*(SORT_NONE(.init)))
|
||||||
|
. = ALIGN(4);
|
||||||
|
_einit = .;
|
||||||
|
} >FLASH AT>FLASH
|
||||||
|
|
||||||
|
.vector :
|
||||||
|
{
|
||||||
|
*(.vector);
|
||||||
|
. = ALIGN(64);
|
||||||
|
} >FLASH AT>FLASH
|
||||||
|
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
*(.text)
|
||||||
|
*(.text.*)
|
||||||
|
*(.rodata)
|
||||||
|
*(.rodata*)
|
||||||
|
*(.gnu.linkonce.t.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH AT>FLASH
|
||||||
|
|
||||||
|
.fini :
|
||||||
|
{
|
||||||
|
KEEP(*(SORT_NONE(.fini)))
|
||||||
|
. = ALIGN(4);
|
||||||
|
} >FLASH AT>FLASH
|
||||||
|
|
||||||
|
PROVIDE( _etext = . );
|
||||||
|
PROVIDE( _eitcm = . );
|
||||||
|
|
||||||
|
.preinit_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP (*(.preinit_array))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
} >FLASH AT>FLASH
|
||||||
|
|
||||||
|
.init_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||||
|
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
} >FLASH AT>FLASH
|
||||||
|
|
||||||
|
.fini_array :
|
||||||
|
{
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||||
|
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
} >FLASH AT>FLASH
|
||||||
|
|
||||||
|
.ctors :
|
||||||
|
{
|
||||||
|
/* gcc uses crtbegin.o to find the start of
|
||||||
|
the constructors, so we make sure it is
|
||||||
|
first. Because this is a wildcard, it
|
||||||
|
doesn't matter if the user does not
|
||||||
|
actually link against crtbegin.o; the
|
||||||
|
linker won't look for a file to match a
|
||||||
|
wildcard. The wildcard also means that it
|
||||||
|
doesn't matter which directory crtbegin.o
|
||||||
|
is in. */
|
||||||
|
KEEP (*crtbegin.o(.ctors))
|
||||||
|
KEEP (*crtbegin?.o(.ctors))
|
||||||
|
/* We don't want to include the .ctor section from
|
||||||
|
the crtend.o file until after the sorted ctors.
|
||||||
|
The .ctor section from the crtend file contains the
|
||||||
|
end of ctors marker and it must be last */
|
||||||
|
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||||
|
KEEP (*(SORT(.ctors.*)))
|
||||||
|
KEEP (*(.ctors))
|
||||||
|
} >FLASH AT>FLASH
|
||||||
|
|
||||||
|
.dtors :
|
||||||
|
{
|
||||||
|
KEEP (*crtbegin.o(.dtors))
|
||||||
|
KEEP (*crtbegin?.o(.dtors))
|
||||||
|
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||||
|
KEEP (*(SORT(.dtors.*)))
|
||||||
|
KEEP (*(.dtors))
|
||||||
|
} >FLASH AT>FLASH
|
||||||
|
|
||||||
|
.dalign :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE(_data_vma = .);
|
||||||
|
} >RAM AT>FLASH
|
||||||
|
|
||||||
|
.dlalign :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE(_data_lma = .);
|
||||||
|
} >FLASH AT>FLASH
|
||||||
|
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
*(.gnu.linkonce.r.*)
|
||||||
|
*(.data .data.*)
|
||||||
|
*(.gnu.linkonce.d.*)
|
||||||
|
. = ALIGN(8);
|
||||||
|
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||||
|
*(.sdata .sdata.*)
|
||||||
|
*(.sdata2.*)
|
||||||
|
*(.gnu.linkonce.s.*)
|
||||||
|
. = ALIGN(8);
|
||||||
|
*(.srodata.cst16)
|
||||||
|
*(.srodata.cst8)
|
||||||
|
*(.srodata.cst4)
|
||||||
|
*(.srodata.cst2)
|
||||||
|
*(.srodata .srodata.*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE( _edata = .);
|
||||||
|
} >RAM AT>FLASH
|
||||||
|
|
||||||
|
.bss :
|
||||||
|
{
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE( _sbss = .);
|
||||||
|
*(.sbss*)
|
||||||
|
*(.gnu.linkonce.sb.*)
|
||||||
|
*(.bss*)
|
||||||
|
*(.gnu.linkonce.b.*)
|
||||||
|
*(COMMON*)
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE( _ebss = .);
|
||||||
|
} >RAM AT>FLASH
|
||||||
|
|
||||||
|
PROVIDE( _end = _ebss);
|
||||||
|
PROVIDE( end = . );
|
||||||
|
|
||||||
|
.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
|
||||||
|
{
|
||||||
|
PROVIDE( _heap_end = . );
|
||||||
|
. = ALIGN(4);
|
||||||
|
PROVIDE(_susrstack = . );
|
||||||
|
. = . + __stack_size;
|
||||||
|
PROVIDE( _eusrstack = .);
|
||||||
|
__freertos_irq_stack_top = .;
|
||||||
|
} >RAM
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
6637
Peripheral/inc/ch32v30x.h
Normal file
6637
Peripheral/inc/ch32v30x.h
Normal file
File diff suppressed because it is too large
Load Diff
230
Peripheral/inc/ch32v30x_adc.h
Normal file
230
Peripheral/inc/ch32v30x_adc.h
Normal file
@@ -0,0 +1,230 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_adc.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* ADC firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_ADC_H
|
||||||
|
#define __CH32V30x_ADC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
|
||||||
|
/* ADC Init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t ADC_Mode; /* Configures the ADC to operate in independent or
|
||||||
|
dual mode.
|
||||||
|
This parameter can be a value of @ref ADC_mode */
|
||||||
|
|
||||||
|
FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in
|
||||||
|
Scan (multichannels) or Single (one channel) mode.
|
||||||
|
This parameter can be set to ENABLE or DISABLE */
|
||||||
|
|
||||||
|
FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in
|
||||||
|
Continuous or Single mode.
|
||||||
|
This parameter can be set to ENABLE or DISABLE. */
|
||||||
|
|
||||||
|
uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog
|
||||||
|
to digital conversion of regular channels. This parameter
|
||||||
|
can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
|
||||||
|
|
||||||
|
uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right.
|
||||||
|
This parameter can be a value of @ref ADC_data_align */
|
||||||
|
|
||||||
|
uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted
|
||||||
|
using the sequencer for regular channel group.
|
||||||
|
This parameter must range from 1 to 16. */
|
||||||
|
|
||||||
|
uint32_t ADC_OutputBuffer; /* Specifies whether the ADC channel output buffer is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref ADC_OutputBuffer */
|
||||||
|
|
||||||
|
uint32_t ADC_Pga; /* Specifies the PGA gain multiple.
|
||||||
|
This parameter can be a value of @ref ADC_Pga */
|
||||||
|
}ADC_InitTypeDef;
|
||||||
|
|
||||||
|
/* ADC_mode */
|
||||||
|
#define ADC_Mode_Independent ((uint32_t)0x00000000)
|
||||||
|
#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)
|
||||||
|
#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)
|
||||||
|
#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)
|
||||||
|
#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)
|
||||||
|
#define ADC_Mode_InjecSimult ((uint32_t)0x00050000)
|
||||||
|
#define ADC_Mode_RegSimult ((uint32_t)0x00060000)
|
||||||
|
#define ADC_Mode_FastInterl ((uint32_t)0x00070000)
|
||||||
|
#define ADC_Mode_SlowInterl ((uint32_t)0x00080000)
|
||||||
|
#define ADC_Mode_AlterTrig ((uint32_t)0x00090000)
|
||||||
|
|
||||||
|
/* ADC_external_trigger_sources_for_regular_channels_conversion */
|
||||||
|
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)
|
||||||
|
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000)
|
||||||
|
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000)
|
||||||
|
#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000)
|
||||||
|
#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000)
|
||||||
|
#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000)
|
||||||
|
|
||||||
|
#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000)
|
||||||
|
#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000)
|
||||||
|
|
||||||
|
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000)
|
||||||
|
#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000)
|
||||||
|
#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000)
|
||||||
|
#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000)
|
||||||
|
#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000)
|
||||||
|
#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000)
|
||||||
|
|
||||||
|
|
||||||
|
/* ADC_data_align */
|
||||||
|
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
|
||||||
|
#define ADC_DataAlign_Left ((uint32_t)0x00000800)
|
||||||
|
|
||||||
|
/* ADC_channels */
|
||||||
|
#define ADC_Channel_0 ((uint8_t)0x00)
|
||||||
|
#define ADC_Channel_1 ((uint8_t)0x01)
|
||||||
|
#define ADC_Channel_2 ((uint8_t)0x02)
|
||||||
|
#define ADC_Channel_3 ((uint8_t)0x03)
|
||||||
|
#define ADC_Channel_4 ((uint8_t)0x04)
|
||||||
|
#define ADC_Channel_5 ((uint8_t)0x05)
|
||||||
|
#define ADC_Channel_6 ((uint8_t)0x06)
|
||||||
|
#define ADC_Channel_7 ((uint8_t)0x07)
|
||||||
|
#define ADC_Channel_8 ((uint8_t)0x08)
|
||||||
|
#define ADC_Channel_9 ((uint8_t)0x09)
|
||||||
|
#define ADC_Channel_10 ((uint8_t)0x0A)
|
||||||
|
#define ADC_Channel_11 ((uint8_t)0x0B)
|
||||||
|
#define ADC_Channel_12 ((uint8_t)0x0C)
|
||||||
|
#define ADC_Channel_13 ((uint8_t)0x0D)
|
||||||
|
#define ADC_Channel_14 ((uint8_t)0x0E)
|
||||||
|
#define ADC_Channel_15 ((uint8_t)0x0F)
|
||||||
|
#define ADC_Channel_16 ((uint8_t)0x10)
|
||||||
|
#define ADC_Channel_17 ((uint8_t)0x11)
|
||||||
|
|
||||||
|
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
|
||||||
|
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
|
||||||
|
|
||||||
|
/*ADC_output_buffer*/
|
||||||
|
#define ADC_OutputBuffer_Enable ((uint32_t)0x04000000)
|
||||||
|
#define ADC_OutputBuffer_Disable ((uint32_t)0x00000000)
|
||||||
|
|
||||||
|
/*ADC_pga*/
|
||||||
|
#define ADC_Pga_1 ((uint32_t)0x00000000)
|
||||||
|
#define ADC_Pga_4 ((uint32_t)0x08000000)
|
||||||
|
#define ADC_Pga_16 ((uint32_t)0x10000000)
|
||||||
|
#define ADC_Pga_64 ((uint32_t)0x18000000)
|
||||||
|
|
||||||
|
/* ADC_sampling_time */
|
||||||
|
#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)
|
||||||
|
#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)
|
||||||
|
#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)
|
||||||
|
#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03)
|
||||||
|
#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04)
|
||||||
|
#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05)
|
||||||
|
#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06)
|
||||||
|
#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07)
|
||||||
|
|
||||||
|
/* ADC_external_trigger_sources_for_injected_channels_conversion */
|
||||||
|
#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000)
|
||||||
|
#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000)
|
||||||
|
#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000)
|
||||||
|
#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000)
|
||||||
|
#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000)
|
||||||
|
|
||||||
|
#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000)
|
||||||
|
#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000)
|
||||||
|
#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000)
|
||||||
|
|
||||||
|
#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000)
|
||||||
|
#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000)
|
||||||
|
#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000)
|
||||||
|
#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000)
|
||||||
|
#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000)
|
||||||
|
|
||||||
|
|
||||||
|
/* ADC_injected_channel_selection */
|
||||||
|
#define ADC_InjectedChannel_1 ((uint8_t)0x14)
|
||||||
|
#define ADC_InjectedChannel_2 ((uint8_t)0x18)
|
||||||
|
#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
|
||||||
|
#define ADC_InjectedChannel_4 ((uint8_t)0x20)
|
||||||
|
|
||||||
|
/* ADC_analog_watchdog_selection */
|
||||||
|
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
|
||||||
|
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
|
||||||
|
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
|
||||||
|
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
|
||||||
|
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
|
||||||
|
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
|
||||||
|
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
|
||||||
|
|
||||||
|
/* ADC_interrupts_definition */
|
||||||
|
#define ADC_IT_EOC ((uint16_t)0x0220)
|
||||||
|
#define ADC_IT_AWD ((uint16_t)0x0140)
|
||||||
|
#define ADC_IT_JEOC ((uint16_t)0x0480)
|
||||||
|
|
||||||
|
/* ADC_flags_definition */
|
||||||
|
#define ADC_FLAG_AWD ((uint8_t)0x01)
|
||||||
|
#define ADC_FLAG_EOC ((uint8_t)0x02)
|
||||||
|
#define ADC_FLAG_JEOC ((uint8_t)0x04)
|
||||||
|
#define ADC_FLAG_JSTRT ((uint8_t)0x08)
|
||||||
|
#define ADC_FLAG_STRT ((uint8_t)0x10)
|
||||||
|
|
||||||
|
|
||||||
|
void ADC_DeInit(ADC_TypeDef* ADCx);
|
||||||
|
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
|
||||||
|
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
|
||||||
|
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
|
||||||
|
void ADC_ResetCalibration(ADC_TypeDef* ADCx);
|
||||||
|
FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef* ADCx);
|
||||||
|
void ADC_StartCalibration(ADC_TypeDef* ADCx);
|
||||||
|
FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef* ADCx);
|
||||||
|
void ADC_SoftwareStartConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
|
||||||
|
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
|
||||||
|
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||||
|
void ADC_ExternalTrigConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
|
||||||
|
uint32_t ADC_GetDualModeConversionValue(void);
|
||||||
|
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
|
||||||
|
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
|
||||||
|
void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||||
|
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
|
||||||
|
void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
|
||||||
|
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
|
||||||
|
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
|
||||||
|
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
|
||||||
|
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
|
||||||
|
void ADC_TempSensorVrefintCmd(FunctionalState NewState);
|
||||||
|
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
|
||||||
|
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
|
||||||
|
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
|
||||||
|
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
|
||||||
|
s32 TempSensor_Volt_To_Temper(s32 Value);
|
||||||
|
void ADC_BufferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||||
|
int16_t Get_CalibrationValue(ADC_TypeDef* ADCx);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
99
Peripheral/inc/ch32v30x_bkp.h
Normal file
99
Peripheral/inc/ch32v30x_bkp.h
Normal file
@@ -0,0 +1,99 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_bkp.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* BKP firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_BKP_H
|
||||||
|
#define __CH32V30x_BKP_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* Tamper_Pin_active_level */
|
||||||
|
#define BKP_TamperPinLevel_High ((uint16_t)0x0000)
|
||||||
|
#define BKP_TamperPinLevel_Low ((uint16_t)0x0001)
|
||||||
|
|
||||||
|
/* RTC_output_source_to_output_on_the_Tamper_pin */
|
||||||
|
#define BKP_RTCOutputSource_None ((uint16_t)0x0000)
|
||||||
|
#define BKP_RTCOutputSource_CalibClock ((uint16_t)0x0080)
|
||||||
|
#define BKP_RTCOutputSource_Alarm ((uint16_t)0x0100)
|
||||||
|
#define BKP_RTCOutputSource_Second ((uint16_t)0x0300)
|
||||||
|
|
||||||
|
/* Data_Backup_Register */
|
||||||
|
#define BKP_DR1 ((uint16_t)0x0004)
|
||||||
|
#define BKP_DR2 ((uint16_t)0x0008)
|
||||||
|
#define BKP_DR3 ((uint16_t)0x000C)
|
||||||
|
#define BKP_DR4 ((uint16_t)0x0010)
|
||||||
|
#define BKP_DR5 ((uint16_t)0x0014)
|
||||||
|
#define BKP_DR6 ((uint16_t)0x0018)
|
||||||
|
#define BKP_DR7 ((uint16_t)0x001C)
|
||||||
|
#define BKP_DR8 ((uint16_t)0x0020)
|
||||||
|
#define BKP_DR9 ((uint16_t)0x0024)
|
||||||
|
#define BKP_DR10 ((uint16_t)0x0028)
|
||||||
|
#define BKP_DR11 ((uint16_t)0x0040)
|
||||||
|
#define BKP_DR12 ((uint16_t)0x0044)
|
||||||
|
#define BKP_DR13 ((uint16_t)0x0048)
|
||||||
|
#define BKP_DR14 ((uint16_t)0x004C)
|
||||||
|
#define BKP_DR15 ((uint16_t)0x0050)
|
||||||
|
#define BKP_DR16 ((uint16_t)0x0054)
|
||||||
|
#define BKP_DR17 ((uint16_t)0x0058)
|
||||||
|
#define BKP_DR18 ((uint16_t)0x005C)
|
||||||
|
#define BKP_DR19 ((uint16_t)0x0060)
|
||||||
|
#define BKP_DR20 ((uint16_t)0x0064)
|
||||||
|
#define BKP_DR21 ((uint16_t)0x0068)
|
||||||
|
#define BKP_DR22 ((uint16_t)0x006C)
|
||||||
|
#define BKP_DR23 ((uint16_t)0x0070)
|
||||||
|
#define BKP_DR24 ((uint16_t)0x0074)
|
||||||
|
#define BKP_DR25 ((uint16_t)0x0078)
|
||||||
|
#define BKP_DR26 ((uint16_t)0x007C)
|
||||||
|
#define BKP_DR27 ((uint16_t)0x0080)
|
||||||
|
#define BKP_DR28 ((uint16_t)0x0084)
|
||||||
|
#define BKP_DR29 ((uint16_t)0x0088)
|
||||||
|
#define BKP_DR30 ((uint16_t)0x008C)
|
||||||
|
#define BKP_DR31 ((uint16_t)0x0090)
|
||||||
|
#define BKP_DR32 ((uint16_t)0x0094)
|
||||||
|
#define BKP_DR33 ((uint16_t)0x0098)
|
||||||
|
#define BKP_DR34 ((uint16_t)0x009C)
|
||||||
|
#define BKP_DR35 ((uint16_t)0x00A0)
|
||||||
|
#define BKP_DR36 ((uint16_t)0x00A4)
|
||||||
|
#define BKP_DR37 ((uint16_t)0x00A8)
|
||||||
|
#define BKP_DR38 ((uint16_t)0x00AC)
|
||||||
|
#define BKP_DR39 ((uint16_t)0x00B0)
|
||||||
|
#define BKP_DR40 ((uint16_t)0x00B4)
|
||||||
|
#define BKP_DR41 ((uint16_t)0x00B8)
|
||||||
|
#define BKP_DR42 ((uint16_t)0x00BC)
|
||||||
|
|
||||||
|
|
||||||
|
void BKP_DeInit(void);
|
||||||
|
void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel);
|
||||||
|
void BKP_TamperPinCmd(FunctionalState NewState);
|
||||||
|
void BKP_ITConfig(FunctionalState NewState);
|
||||||
|
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource);
|
||||||
|
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue);
|
||||||
|
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data);
|
||||||
|
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR);
|
||||||
|
FlagStatus BKP_GetFlagStatus(void);
|
||||||
|
void BKP_ClearFlag(void);
|
||||||
|
ITStatus BKP_GetITStatus(void);
|
||||||
|
void BKP_ClearITPendingBit(void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
376
Peripheral/inc/ch32v30x_can.h
Normal file
376
Peripheral/inc/ch32v30x_can.h
Normal file
@@ -0,0 +1,376 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_can.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* CAN firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_CAN_H
|
||||||
|
#define __CH32V30x_CAN_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* CAN init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t CAN_Prescaler; /* Specifies the length of a time quantum.
|
||||||
|
It ranges from 1 to 1024. */
|
||||||
|
|
||||||
|
uint8_t CAN_Mode; /* Specifies the CAN operating mode.
|
||||||
|
This parameter can be a value of
|
||||||
|
@ref CAN_operating_mode */
|
||||||
|
|
||||||
|
uint8_t CAN_SJW; /* Specifies the maximum number of time quanta
|
||||||
|
the CAN hardware is allowed to lengthen or
|
||||||
|
shorten a bit to perform resynchronization.
|
||||||
|
This parameter can be a value of
|
||||||
|
@ref CAN_synchronisation_jump_width */
|
||||||
|
|
||||||
|
uint8_t CAN_BS1; /* Specifies the number of time quanta in Bit
|
||||||
|
Segment 1. This parameter can be a value of
|
||||||
|
@ref CAN_time_quantum_in_bit_segment_1 */
|
||||||
|
|
||||||
|
uint8_t CAN_BS2; /* Specifies the number of time quanta in Bit
|
||||||
|
Segment 2.
|
||||||
|
This parameter can be a value of
|
||||||
|
@ref CAN_time_quantum_in_bit_segment_2 */
|
||||||
|
|
||||||
|
FunctionalState CAN_TTCM; /* Enable or disable the time triggered
|
||||||
|
communication mode. This parameter can be set
|
||||||
|
either to ENABLE or DISABLE. */
|
||||||
|
|
||||||
|
FunctionalState CAN_ABOM; /* Enable or disable the automatic bus-off
|
||||||
|
management. This parameter can be set either
|
||||||
|
to ENABLE or DISABLE. */
|
||||||
|
|
||||||
|
FunctionalState CAN_AWUM; /* Enable or disable the automatic wake-up mode.
|
||||||
|
This parameter can be set either to ENABLE or
|
||||||
|
DISABLE. */
|
||||||
|
|
||||||
|
FunctionalState CAN_NART; /* Enable or disable the no-automatic
|
||||||
|
retransmission mode. This parameter can be
|
||||||
|
set either to ENABLE or DISABLE. */
|
||||||
|
|
||||||
|
FunctionalState CAN_RFLM; /* Enable or disable the Receive FIFO Locked mode.
|
||||||
|
This parameter can be set either to ENABLE
|
||||||
|
or DISABLE. */
|
||||||
|
|
||||||
|
FunctionalState CAN_TXFP; /* Enable or disable the transmit FIFO priority.
|
||||||
|
This parameter can be set either to ENABLE
|
||||||
|
or DISABLE. */
|
||||||
|
} CAN_InitTypeDef;
|
||||||
|
|
||||||
|
/* CAN filter init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t CAN_FilterIdHigh; /* Specifies the filter identification number (MSBs for a 32-bit
|
||||||
|
configuration, first one for a 16-bit configuration).
|
||||||
|
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||||
|
|
||||||
|
uint16_t CAN_FilterIdLow; /* Specifies the filter identification number (LSBs for a 32-bit
|
||||||
|
configuration, second one for a 16-bit configuration).
|
||||||
|
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||||
|
|
||||||
|
uint16_t CAN_FilterMaskIdHigh; /* Specifies the filter mask number or identification number,
|
||||||
|
according to the mode (MSBs for a 32-bit configuration,
|
||||||
|
first one for a 16-bit configuration).
|
||||||
|
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||||
|
|
||||||
|
uint16_t CAN_FilterMaskIdLow; /* Specifies the filter mask number or identification number,
|
||||||
|
according to the mode (LSBs for a 32-bit configuration,
|
||||||
|
second one for a 16-bit configuration).
|
||||||
|
This parameter can be a value between 0x0000 and 0xFFFF */
|
||||||
|
|
||||||
|
uint16_t CAN_FilterFIFOAssignment; /* Specifies the FIFO (0 or 1) which will be assigned to the filter.
|
||||||
|
This parameter can be a value of @ref CAN_filter_FIFO */
|
||||||
|
|
||||||
|
uint8_t CAN_FilterNumber; /* Specifies the filter which will be initialized. It ranges from 0 to 13. */
|
||||||
|
|
||||||
|
uint8_t CAN_FilterMode; /* Specifies the filter mode to be initialized.
|
||||||
|
This parameter can be a value of @ref CAN_filter_mode */
|
||||||
|
|
||||||
|
uint8_t CAN_FilterScale; /* Specifies the filter scale.
|
||||||
|
This parameter can be a value of @ref CAN_filter_scale */
|
||||||
|
|
||||||
|
FunctionalState CAN_FilterActivation; /* Enable or disable the filter.
|
||||||
|
This parameter can be set either to ENABLE or DISABLE. */
|
||||||
|
} CAN_FilterInitTypeDef;
|
||||||
|
|
||||||
|
/* CAN Tx message structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t StdId; /* Specifies the standard identifier.
|
||||||
|
This parameter can be a value between 0 to 0x7FF. */
|
||||||
|
|
||||||
|
uint32_t ExtId; /* Specifies the extended identifier.
|
||||||
|
This parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||||
|
|
||||||
|
uint8_t IDE; /* Specifies the type of identifier for the message that
|
||||||
|
will be transmitted. This parameter can be a value
|
||||||
|
of @ref CAN_identifier_type */
|
||||||
|
|
||||||
|
uint8_t RTR; /* Specifies the type of frame for the message that will
|
||||||
|
be transmitted. This parameter can be a value of
|
||||||
|
@ref CAN_remote_transmission_request */
|
||||||
|
|
||||||
|
uint8_t DLC; /* Specifies the length of the frame that will be
|
||||||
|
transmitted. This parameter can be a value between
|
||||||
|
0 to 8 */
|
||||||
|
|
||||||
|
uint8_t Data[8]; /* Contains the data to be transmitted. It ranges from 0
|
||||||
|
to 0xFF. */
|
||||||
|
} CanTxMsg;
|
||||||
|
|
||||||
|
/* CAN Rx message structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t StdId; /* Specifies the standard identifier.
|
||||||
|
This parameter can be a value between 0 to 0x7FF. */
|
||||||
|
|
||||||
|
uint32_t ExtId; /* Specifies the extended identifier.
|
||||||
|
This parameter can be a value between 0 to 0x1FFFFFFF. */
|
||||||
|
|
||||||
|
uint8_t IDE; /* Specifies the type of identifier for the message that
|
||||||
|
will be received. This parameter can be a value of
|
||||||
|
@ref CAN_identifier_type */
|
||||||
|
|
||||||
|
uint8_t RTR; /* Specifies the type of frame for the received message.
|
||||||
|
This parameter can be a value of
|
||||||
|
@ref CAN_remote_transmission_request */
|
||||||
|
|
||||||
|
uint8_t DLC; /* Specifies the length of the frame that will be received.
|
||||||
|
This parameter can be a value between 0 to 8 */
|
||||||
|
|
||||||
|
uint8_t Data[8]; /* Contains the data to be received. It ranges from 0 to
|
||||||
|
0xFF. */
|
||||||
|
|
||||||
|
uint8_t FMI; /* Specifies the index of the filter the message stored in
|
||||||
|
the mailbox passes through. This parameter can be a
|
||||||
|
value between 0 to 0xFF */
|
||||||
|
} CanRxMsg;
|
||||||
|
|
||||||
|
/* CAN_sleep_constants */
|
||||||
|
#define CAN_InitStatus_Failed ((uint8_t)0x00) /* CAN initialization failed */
|
||||||
|
#define CAN_InitStatus_Success ((uint8_t)0x01) /* CAN initialization OK */
|
||||||
|
|
||||||
|
/* CAN_Mode */
|
||||||
|
#define CAN_Mode_Normal ((uint8_t)0x00) /* normal mode */
|
||||||
|
#define CAN_Mode_LoopBack ((uint8_t)0x01) /* loopback mode */
|
||||||
|
#define CAN_Mode_Silent ((uint8_t)0x02) /* silent mode */
|
||||||
|
#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /* loopback combined with silent mode */
|
||||||
|
|
||||||
|
/* CAN_Operating_Mode */
|
||||||
|
#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /* Initialization mode */
|
||||||
|
#define CAN_OperatingMode_Normal ((uint8_t)0x01) /* Normal mode */
|
||||||
|
#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /* sleep mode */
|
||||||
|
|
||||||
|
/* CAN_Mode_Status */
|
||||||
|
#define CAN_ModeStatus_Failed ((uint8_t)0x00) /* CAN entering the specific mode failed */
|
||||||
|
#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /* CAN entering the specific mode Succeed */
|
||||||
|
|
||||||
|
/* CAN_synchronisation_jump_width */
|
||||||
|
#define CAN_SJW_1tq ((uint8_t)0x00) /* 1 time quantum */
|
||||||
|
#define CAN_SJW_2tq ((uint8_t)0x01) /* 2 time quantum */
|
||||||
|
#define CAN_SJW_3tq ((uint8_t)0x02) /* 3 time quantum */
|
||||||
|
#define CAN_SJW_4tq ((uint8_t)0x03) /* 4 time quantum */
|
||||||
|
|
||||||
|
/* CAN_time_quantum_in_bit_segment_1 */
|
||||||
|
#define CAN_BS1_1tq ((uint8_t)0x00) /* 1 time quantum */
|
||||||
|
#define CAN_BS1_2tq ((uint8_t)0x01) /* 2 time quantum */
|
||||||
|
#define CAN_BS1_3tq ((uint8_t)0x02) /* 3 time quantum */
|
||||||
|
#define CAN_BS1_4tq ((uint8_t)0x03) /* 4 time quantum */
|
||||||
|
#define CAN_BS1_5tq ((uint8_t)0x04) /* 5 time quantum */
|
||||||
|
#define CAN_BS1_6tq ((uint8_t)0x05) /* 6 time quantum */
|
||||||
|
#define CAN_BS1_7tq ((uint8_t)0x06) /* 7 time quantum */
|
||||||
|
#define CAN_BS1_8tq ((uint8_t)0x07) /* 8 time quantum */
|
||||||
|
#define CAN_BS1_9tq ((uint8_t)0x08) /* 9 time quantum */
|
||||||
|
#define CAN_BS1_10tq ((uint8_t)0x09) /* 10 time quantum */
|
||||||
|
#define CAN_BS1_11tq ((uint8_t)0x0A) /* 11 time quantum */
|
||||||
|
#define CAN_BS1_12tq ((uint8_t)0x0B) /* 12 time quantum */
|
||||||
|
#define CAN_BS1_13tq ((uint8_t)0x0C) /* 13 time quantum */
|
||||||
|
#define CAN_BS1_14tq ((uint8_t)0x0D) /* 14 time quantum */
|
||||||
|
#define CAN_BS1_15tq ((uint8_t)0x0E) /* 15 time quantum */
|
||||||
|
#define CAN_BS1_16tq ((uint8_t)0x0F) /* 16 time quantum */
|
||||||
|
|
||||||
|
/* CAN_time_quantum_in_bit_segment_2 */
|
||||||
|
#define CAN_BS2_1tq ((uint8_t)0x00) /* 1 time quantum */
|
||||||
|
#define CAN_BS2_2tq ((uint8_t)0x01) /* 2 time quantum */
|
||||||
|
#define CAN_BS2_3tq ((uint8_t)0x02) /* 3 time quantum */
|
||||||
|
#define CAN_BS2_4tq ((uint8_t)0x03) /* 4 time quantum */
|
||||||
|
#define CAN_BS2_5tq ((uint8_t)0x04) /* 5 time quantum */
|
||||||
|
#define CAN_BS2_6tq ((uint8_t)0x05) /* 6 time quantum */
|
||||||
|
#define CAN_BS2_7tq ((uint8_t)0x06) /* 7 time quantum */
|
||||||
|
#define CAN_BS2_8tq ((uint8_t)0x07) /* 8 time quantum */
|
||||||
|
|
||||||
|
/* CAN_filter_mode */
|
||||||
|
#define CAN_FilterMode_IdMask ((uint8_t)0x00) /* identifier/mask mode */
|
||||||
|
#define CAN_FilterMode_IdList ((uint8_t)0x01) /* identifier list mode */
|
||||||
|
|
||||||
|
/* CAN_filter_scale */
|
||||||
|
#define CAN_FilterScale_16bit ((uint8_t)0x00) /* Two 16-bit filters */
|
||||||
|
#define CAN_FilterScale_32bit ((uint8_t)0x01) /* One 32-bit filter */
|
||||||
|
|
||||||
|
/* CAN_filter_FIFO */
|
||||||
|
#define CAN_Filter_FIFO0 ((uint8_t)0x00) /* Filter FIFO 0 assignment for filter x */
|
||||||
|
#define CAN_Filter_FIFO1 ((uint8_t)0x01) /* Filter FIFO 1 assignment for filter x */
|
||||||
|
|
||||||
|
/* CAN_identifier_type */
|
||||||
|
#define CAN_Id_Standard ((uint32_t)0x00000000) /* Standard Id */
|
||||||
|
#define CAN_Id_Extended ((uint32_t)0x00000004) /* Extended Id */
|
||||||
|
|
||||||
|
/* CAN_remote_transmission_request */
|
||||||
|
#define CAN_RTR_Data ((uint32_t)0x00000000) /* Data frame */
|
||||||
|
#define CAN_RTR_Remote ((uint32_t)0x00000002) /* Remote frame */
|
||||||
|
|
||||||
|
/* CAN_transmit_constants */
|
||||||
|
#define CAN_TxStatus_Failed ((uint8_t)0x00)/* CAN transmission failed */
|
||||||
|
#define CAN_TxStatus_Ok ((uint8_t)0x01) /* CAN transmission succeeded */
|
||||||
|
#define CAN_TxStatus_Pending ((uint8_t)0x02) /* CAN transmission pending */
|
||||||
|
#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /* CAN cell did not provide an empty mailbox */
|
||||||
|
|
||||||
|
/* CAN_receive_FIFO_number_constants */
|
||||||
|
#define CAN_FIFO0 ((uint8_t)0x00) /* CAN FIFO 0 used to receive */
|
||||||
|
#define CAN_FIFO1 ((uint8_t)0x01) /* CAN FIFO 1 used to receive */
|
||||||
|
|
||||||
|
/* CAN_sleep_constants */
|
||||||
|
#define CAN_Sleep_Failed ((uint8_t)0x00) /* CAN did not enter the sleep mode */
|
||||||
|
#define CAN_Sleep_Ok ((uint8_t)0x01) /* CAN entered the sleep mode */
|
||||||
|
|
||||||
|
/* CAN_wake_up_constants */
|
||||||
|
#define CAN_WakeUp_Failed ((uint8_t)0x00) /* CAN did not leave the sleep mode */
|
||||||
|
#define CAN_WakeUp_Ok ((uint8_t)0x01) /* CAN leaved the sleep mode */
|
||||||
|
|
||||||
|
/* CAN_Error_Code_constants */
|
||||||
|
#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /* No Error */
|
||||||
|
#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /* Stuff Error */
|
||||||
|
#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /* Form Error */
|
||||||
|
#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /* Acknowledgment Error */
|
||||||
|
#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /* Bit Recessive Error */
|
||||||
|
#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /* Bit Dominant Error */
|
||||||
|
#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /* CRC Error */
|
||||||
|
#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /* Software Set Error */
|
||||||
|
|
||||||
|
|
||||||
|
/* CAN_flags */
|
||||||
|
/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
|
||||||
|
* and CAN_ClearFlag() functions.
|
||||||
|
* If the flag is 0x1XXXXXXX, it means that it can only be used with CAN_GetFlagStatus() function.
|
||||||
|
*/
|
||||||
|
/* Transmit Flags */
|
||||||
|
#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /* Request MailBox0 Flag */
|
||||||
|
#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /* Request MailBox1 Flag */
|
||||||
|
#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /* Request MailBox2 Flag */
|
||||||
|
|
||||||
|
/* Receive Flags */
|
||||||
|
#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /* FIFO 0 Message Pending Flag */
|
||||||
|
#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /* FIFO 0 Full Flag */
|
||||||
|
#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /* FIFO 0 Overrun Flag */
|
||||||
|
#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /* FIFO 1 Message Pending Flag */
|
||||||
|
#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /* FIFO 1 Full Flag */
|
||||||
|
#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /* FIFO 1 Overrun Flag */
|
||||||
|
|
||||||
|
/* Operating Mode Flags */
|
||||||
|
#define CAN_FLAG_WKU ((uint32_t)0x31000008) /* Wake up Flag */
|
||||||
|
#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /* Sleep acknowledge Flag */
|
||||||
|
/* Note:
|
||||||
|
*When SLAK intterupt is disabled (SLKIE=0), no polling on SLAKI is possible.
|
||||||
|
*In this case the SLAK bit can be polled.
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Error Flags */
|
||||||
|
#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /* Error Warning Flag */
|
||||||
|
#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /* Error Passive Flag */
|
||||||
|
#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /* Bus-Off Flag */
|
||||||
|
#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /* Last error code Flag */
|
||||||
|
|
||||||
|
|
||||||
|
/* CAN_interrupts */
|
||||||
|
#define CAN_IT_TME ((uint32_t)0x00000001) /* Transmit mailbox empty Interrupt*/
|
||||||
|
|
||||||
|
/* Receive Interrupts */
|
||||||
|
#define CAN_IT_FMP0 ((uint32_t)0x00000002) /* FIFO 0 message pending Interrupt*/
|
||||||
|
#define CAN_IT_FF0 ((uint32_t)0x00000004) /* FIFO 0 full Interrupt*/
|
||||||
|
#define CAN_IT_FOV0 ((uint32_t)0x00000008) /* FIFO 0 overrun Interrupt*/
|
||||||
|
#define CAN_IT_FMP1 ((uint32_t)0x00000010) /* FIFO 1 message pending Interrupt*/
|
||||||
|
#define CAN_IT_FF1 ((uint32_t)0x00000020) /* FIFO 1 full Interrupt*/
|
||||||
|
#define CAN_IT_FOV1 ((uint32_t)0x00000040) /* FIFO 1 overrun Interrupt*/
|
||||||
|
|
||||||
|
/* Operating Mode Interrupts */
|
||||||
|
#define CAN_IT_WKU ((uint32_t)0x00010000) /* Wake-up Interrupt*/
|
||||||
|
#define CAN_IT_SLK ((uint32_t)0x00020000) /* Sleep acknowledge Interrupt*/
|
||||||
|
|
||||||
|
/* Error Interrupts */
|
||||||
|
#define CAN_IT_EWG ((uint32_t)0x00000100) /* Error warning Interrupt*/
|
||||||
|
#define CAN_IT_EPV ((uint32_t)0x00000200) /* Error passive Interrupt*/
|
||||||
|
#define CAN_IT_BOF ((uint32_t)0x00000400) /* Bus-off Interrupt*/
|
||||||
|
#define CAN_IT_LEC ((uint32_t)0x00000800) /* Last error code Interrupt*/
|
||||||
|
#define CAN_IT_ERR ((uint32_t)0x00008000) /* Error Interrupt*/
|
||||||
|
|
||||||
|
/* Flags named as Interrupts : kept only for FW compatibility */
|
||||||
|
#define CAN_IT_RQCP0 CAN_IT_TME
|
||||||
|
#define CAN_IT_RQCP1 CAN_IT_TME
|
||||||
|
#define CAN_IT_RQCP2 CAN_IT_TME
|
||||||
|
|
||||||
|
/* CAN_Legacy */
|
||||||
|
#define CANINITFAILED CAN_InitStatus_Failed
|
||||||
|
#define CANINITOK CAN_InitStatus_Success
|
||||||
|
#define CAN_FilterFIFO0 CAN_Filter_FIFO0
|
||||||
|
#define CAN_FilterFIFO1 CAN_Filter_FIFO1
|
||||||
|
#define CAN_ID_STD CAN_Id_Standard
|
||||||
|
#define CAN_ID_EXT CAN_Id_Extended
|
||||||
|
#define CAN_RTR_DATA CAN_RTR_Data
|
||||||
|
#define CAN_RTR_REMOTE CAN_RTR_Remote
|
||||||
|
#define CANTXFAILE CAN_TxStatus_Failed
|
||||||
|
#define CANTXOK CAN_TxStatus_Ok
|
||||||
|
#define CANTXPENDING CAN_TxStatus_Pending
|
||||||
|
#define CAN_NO_MB CAN_TxStatus_NoMailBox
|
||||||
|
#define CANSLEEPFAILED CAN_Sleep_Failed
|
||||||
|
#define CANSLEEPOK CAN_Sleep_Ok
|
||||||
|
#define CANWAKEUPFAILED CAN_WakeUp_Failed
|
||||||
|
#define CANWAKEUPOK CAN_WakeUp_Ok
|
||||||
|
|
||||||
|
|
||||||
|
void CAN_DeInit(CAN_TypeDef* CANx);
|
||||||
|
uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
|
||||||
|
void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
|
||||||
|
void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
|
||||||
|
void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
|
||||||
|
void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
|
||||||
|
void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
|
||||||
|
uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
|
||||||
|
uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
|
||||||
|
void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
|
||||||
|
void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
|
||||||
|
void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
|
||||||
|
uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
|
||||||
|
uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
|
||||||
|
uint8_t CAN_Sleep(CAN_TypeDef* CANx);
|
||||||
|
uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
|
||||||
|
uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
|
||||||
|
uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
|
||||||
|
uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
|
||||||
|
void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
|
||||||
|
FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
|
||||||
|
void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
|
||||||
|
ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
|
||||||
|
void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
39
Peripheral/inc/ch32v30x_crc.h
Normal file
39
Peripheral/inc/ch32v30x_crc.h
Normal file
@@ -0,0 +1,39 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_crc.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* CRC firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_CRC_H
|
||||||
|
#define __CH32V30x_CRC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
|
||||||
|
void CRC_ResetDR(void);
|
||||||
|
uint32_t CRC_CalcCRC(uint32_t Data);
|
||||||
|
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
|
||||||
|
uint32_t CRC_GetCRC(void);
|
||||||
|
void CRC_SetIDRegister(uint8_t IDValue);
|
||||||
|
uint8_t CRC_GetIDRegister(void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
122
Peripheral/inc/ch32v30x_dac.h
Normal file
122
Peripheral/inc/ch32v30x_dac.h
Normal file
@@ -0,0 +1,122 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_dac.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* DAC firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_DAC_H
|
||||||
|
#define __CH32V30x_DAC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* DAC Init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t DAC_Trigger; /* Specifies the external trigger for the selected DAC channel.
|
||||||
|
This parameter can be a value of @ref DAC_trigger_selection */
|
||||||
|
|
||||||
|
uint32_t DAC_WaveGeneration; /* Specifies whether DAC channel noise waves or triangle waves
|
||||||
|
are generated, or whether no wave is generated.
|
||||||
|
This parameter can be a value of @ref DAC_wave_generation */
|
||||||
|
|
||||||
|
uint32_t DAC_LFSRUnmask_TriangleAmplitude; /* Specifies the LFSR mask for noise wave generation or
|
||||||
|
the maximum amplitude triangle generation for the DAC channel.
|
||||||
|
This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
|
||||||
|
|
||||||
|
uint32_t DAC_OutputBuffer; /* Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref DAC_output_buffer */
|
||||||
|
}DAC_InitTypeDef;
|
||||||
|
|
||||||
|
|
||||||
|
/* DAC_trigger_selection */
|
||||||
|
#define DAC_Trigger_None ((uint32_t)0x00000000) /* Conversion is automatic once the DAC1_DHRxxxx register
|
||||||
|
has been loaded, and not by external trigger */
|
||||||
|
#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /* TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||||
|
#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /* TIM8 TRGO selected as external conversion trigger for DAC channel
|
||||||
|
only in High-density devices*/
|
||||||
|
#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /* TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||||
|
#define DAC_Trigger_T5_TRGO ((uint32_t)0x0000001C) /* TIM5 TRGO selected as external conversion trigger for DAC channel */
|
||||||
|
#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /* TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||||
|
#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /* TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||||
|
#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /* EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||||
|
#define DAC_Trigger_Software ((uint32_t)0x0000003C) /* Conversion started by software trigger for DAC channel */
|
||||||
|
|
||||||
|
/* DAC_wave_generation */
|
||||||
|
#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
|
||||||
|
#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
|
||||||
|
#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
|
||||||
|
|
||||||
|
|
||||||
|
/* DAC_lfsrunmask_triangleamplitude */
|
||||||
|
#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /* Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /* Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /* Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /* Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /* Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /* Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /* Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /* Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /* Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /* Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /* Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||||
|
#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /* Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||||
|
#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /* Select max triangle amplitude of 1 */
|
||||||
|
#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /* Select max triangle amplitude of 3 */
|
||||||
|
#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /* Select max triangle amplitude of 7 */
|
||||||
|
#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /* Select max triangle amplitude of 15 */
|
||||||
|
#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /* Select max triangle amplitude of 31 */
|
||||||
|
#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /* Select max triangle amplitude of 63 */
|
||||||
|
#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /* Select max triangle amplitude of 127 */
|
||||||
|
#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /* Select max triangle amplitude of 255 */
|
||||||
|
#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /* Select max triangle amplitude of 511 */
|
||||||
|
#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /* Select max triangle amplitude of 1023 */
|
||||||
|
#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /* Select max triangle amplitude of 2047 */
|
||||||
|
#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /* Select max triangle amplitude of 4095 */
|
||||||
|
|
||||||
|
/* DAC_output_buffer */
|
||||||
|
#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
|
||||||
|
#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
|
||||||
|
|
||||||
|
/* DAC_Channel_selection */
|
||||||
|
#define DAC_Channel_1 ((uint32_t)0x00000000)
|
||||||
|
#define DAC_Channel_2 ((uint32_t)0x00000010)
|
||||||
|
|
||||||
|
/* DAC_data_alignment */
|
||||||
|
#define DAC_Align_12b_R ((uint32_t)0x00000000)
|
||||||
|
#define DAC_Align_12b_L ((uint32_t)0x00000004)
|
||||||
|
#define DAC_Align_8b_R ((uint32_t)0x00000008)
|
||||||
|
|
||||||
|
/* DAC_wave_generation */
|
||||||
|
#define DAC_Wave_Noise ((uint32_t)0x00000040)
|
||||||
|
#define DAC_Wave_Triangle ((uint32_t)0x00000080)
|
||||||
|
|
||||||
|
|
||||||
|
void DAC_DeInit(void);
|
||||||
|
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
|
||||||
|
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
|
||||||
|
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||||
|
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||||
|
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||||
|
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
|
||||||
|
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
|
||||||
|
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
|
||||||
|
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
|
||||||
|
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
|
||||||
|
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
60
Peripheral/inc/ch32v30x_dbgmcu.h
Normal file
60
Peripheral/inc/ch32v30x_dbgmcu.h
Normal file
@@ -0,0 +1,60 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_dbgmcu.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* DBGMCU firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_DBGMCU_H
|
||||||
|
#define __CH32V30x_DBGMCU_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
#define DBGMCU_SLEEP ((uint32_t)0x00000001)
|
||||||
|
#define DBGMCU_STOP ((uint32_t)0x00000002)
|
||||||
|
#define DBGMCU_STANDBY ((uint32_t)0x00000004)
|
||||||
|
#define DBGMCU_IWDG_STOP ((uint32_t)0x00000100)
|
||||||
|
#define DBGMCU_WWDG_STOP ((uint32_t)0x00000200)
|
||||||
|
#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00000400)
|
||||||
|
#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00000800)
|
||||||
|
#define DBGMCU_TIM1_STOP ((uint32_t)0x00001000)
|
||||||
|
#define DBGMCU_TIM2_STOP ((uint32_t)0x00002000)
|
||||||
|
#define DBGMCU_TIM3_STOP ((uint32_t)0x00004000)
|
||||||
|
#define DBGMCU_TIM4_STOP ((uint32_t)0x00008000)
|
||||||
|
#define DBGMCU_TIM5_STOP ((uint32_t)0x00010000)
|
||||||
|
#define DBGMCU_TIM6_STOP ((uint32_t)0x00020000)
|
||||||
|
#define DBGMCU_TIM7_STOP ((uint32_t)0x00040000)
|
||||||
|
#define DBGMCU_TIM8_STOP ((uint32_t)0x00080000)
|
||||||
|
#define DBGMCU_CAN1_STOP ((uint32_t)0x00100000)
|
||||||
|
#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)
|
||||||
|
#define DBGMCU_TIM9_STOP ((uint32_t)0x00400000)
|
||||||
|
#define DBGMCU_TIM10_STOP ((uint32_t)0x00800000)
|
||||||
|
|
||||||
|
uint32_t DBGMCU_GetREVID(void);
|
||||||
|
uint32_t DBGMCU_GetDEVID(void);
|
||||||
|
uint32_t __get_DEBUG_CR(void);
|
||||||
|
void __set_DEBUG_CR(uint32_t value);
|
||||||
|
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||||
|
uint32_t DBGMCU_GetCHIPID( void );
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
270
Peripheral/inc/ch32v30x_dma.h
Normal file
270
Peripheral/inc/ch32v30x_dma.h
Normal file
@@ -0,0 +1,270 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_dma.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* DMA firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_DMA_H
|
||||||
|
#define __CH32V30x_DMA_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* DMA Init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */
|
||||||
|
|
||||||
|
uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */
|
||||||
|
|
||||||
|
uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination.
|
||||||
|
This parameter can be a value of @ref DMA_data_transfer_direction */
|
||||||
|
|
||||||
|
uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel.
|
||||||
|
The data unit is equal to the configuration set in DMA_PeripheralDataSize
|
||||||
|
or DMA_MemoryDataSize members depending in the transfer direction. */
|
||||||
|
|
||||||
|
uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not.
|
||||||
|
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
|
||||||
|
|
||||||
|
uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not.
|
||||||
|
This parameter can be a value of @ref DMA_memory_incremented_mode */
|
||||||
|
|
||||||
|
uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width.
|
||||||
|
This parameter can be a value of @ref DMA_peripheral_data_size */
|
||||||
|
|
||||||
|
uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width.
|
||||||
|
This parameter can be a value of @ref DMA_memory_data_size */
|
||||||
|
|
||||||
|
uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx.
|
||||||
|
This parameter can be a value of @ref DMA_circular_normal_mode.
|
||||||
|
@note: The circular buffer mode cannot be used if the memory-to-memory
|
||||||
|
data transfer is configured on the selected Channel */
|
||||||
|
|
||||||
|
uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx.
|
||||||
|
This parameter can be a value of @ref DMA_priority_level */
|
||||||
|
|
||||||
|
uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
|
||||||
|
This parameter can be a value of @ref DMA_memory_to_memory */
|
||||||
|
}DMA_InitTypeDef;
|
||||||
|
|
||||||
|
/* DMA_data_transfer_direction */
|
||||||
|
#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
|
||||||
|
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
|
||||||
|
|
||||||
|
/* DMA_peripheral_incremented_mode */
|
||||||
|
#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
|
||||||
|
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
|
||||||
|
|
||||||
|
/* DMA_memory_incremented_mode */
|
||||||
|
#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
|
||||||
|
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
|
||||||
|
|
||||||
|
/* DMA_peripheral_data_size */
|
||||||
|
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
|
||||||
|
#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
|
||||||
|
#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
|
||||||
|
|
||||||
|
/* DMA_memory_data_size */
|
||||||
|
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
|
||||||
|
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
|
||||||
|
#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
|
||||||
|
|
||||||
|
/* DMA_circular_normal_mode */
|
||||||
|
#define DMA_Mode_Circular ((uint32_t)0x00000020)
|
||||||
|
#define DMA_Mode_Normal ((uint32_t)0x00000000)
|
||||||
|
|
||||||
|
/* DMA_priority_level */
|
||||||
|
#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
|
||||||
|
#define DMA_Priority_High ((uint32_t)0x00002000)
|
||||||
|
#define DMA_Priority_Medium ((uint32_t)0x00001000)
|
||||||
|
#define DMA_Priority_Low ((uint32_t)0x00000000)
|
||||||
|
|
||||||
|
/* DMA_memory_to_memory */
|
||||||
|
#define DMA_M2M_Enable ((uint32_t)0x00004000)
|
||||||
|
#define DMA_M2M_Disable ((uint32_t)0x00000000)
|
||||||
|
|
||||||
|
/* DMA_interrupts_definition */
|
||||||
|
#define DMA_IT_TC ((uint32_t)0x00000002)
|
||||||
|
#define DMA_IT_HT ((uint32_t)0x00000004)
|
||||||
|
#define DMA_IT_TE ((uint32_t)0x00000008)
|
||||||
|
|
||||||
|
#define DMA1_IT_GL1 ((uint32_t)0x00000001)
|
||||||
|
#define DMA1_IT_TC1 ((uint32_t)0x00000002)
|
||||||
|
#define DMA1_IT_HT1 ((uint32_t)0x00000004)
|
||||||
|
#define DMA1_IT_TE1 ((uint32_t)0x00000008)
|
||||||
|
#define DMA1_IT_GL2 ((uint32_t)0x00000010)
|
||||||
|
#define DMA1_IT_TC2 ((uint32_t)0x00000020)
|
||||||
|
#define DMA1_IT_HT2 ((uint32_t)0x00000040)
|
||||||
|
#define DMA1_IT_TE2 ((uint32_t)0x00000080)
|
||||||
|
#define DMA1_IT_GL3 ((uint32_t)0x00000100)
|
||||||
|
#define DMA1_IT_TC3 ((uint32_t)0x00000200)
|
||||||
|
#define DMA1_IT_HT3 ((uint32_t)0x00000400)
|
||||||
|
#define DMA1_IT_TE3 ((uint32_t)0x00000800)
|
||||||
|
#define DMA1_IT_GL4 ((uint32_t)0x00001000)
|
||||||
|
#define DMA1_IT_TC4 ((uint32_t)0x00002000)
|
||||||
|
#define DMA1_IT_HT4 ((uint32_t)0x00004000)
|
||||||
|
#define DMA1_IT_TE4 ((uint32_t)0x00008000)
|
||||||
|
#define DMA1_IT_GL5 ((uint32_t)0x00010000)
|
||||||
|
#define DMA1_IT_TC5 ((uint32_t)0x00020000)
|
||||||
|
#define DMA1_IT_HT5 ((uint32_t)0x00040000)
|
||||||
|
#define DMA1_IT_TE5 ((uint32_t)0x00080000)
|
||||||
|
#define DMA1_IT_GL6 ((uint32_t)0x00100000)
|
||||||
|
#define DMA1_IT_TC6 ((uint32_t)0x00200000)
|
||||||
|
#define DMA1_IT_HT6 ((uint32_t)0x00400000)
|
||||||
|
#define DMA1_IT_TE6 ((uint32_t)0x00800000)
|
||||||
|
#define DMA1_IT_GL7 ((uint32_t)0x01000000)
|
||||||
|
#define DMA1_IT_TC7 ((uint32_t)0x02000000)
|
||||||
|
#define DMA1_IT_HT7 ((uint32_t)0x04000000)
|
||||||
|
#define DMA1_IT_TE7 ((uint32_t)0x08000000)
|
||||||
|
|
||||||
|
#define DMA2_IT_GL1 ((uint32_t)0x10000001)
|
||||||
|
#define DMA2_IT_TC1 ((uint32_t)0x10000002)
|
||||||
|
#define DMA2_IT_HT1 ((uint32_t)0x10000004)
|
||||||
|
#define DMA2_IT_TE1 ((uint32_t)0x10000008)
|
||||||
|
#define DMA2_IT_GL2 ((uint32_t)0x10000010)
|
||||||
|
#define DMA2_IT_TC2 ((uint32_t)0x10000020)
|
||||||
|
#define DMA2_IT_HT2 ((uint32_t)0x10000040)
|
||||||
|
#define DMA2_IT_TE2 ((uint32_t)0x10000080)
|
||||||
|
#define DMA2_IT_GL3 ((uint32_t)0x10000100)
|
||||||
|
#define DMA2_IT_TC3 ((uint32_t)0x10000200)
|
||||||
|
#define DMA2_IT_HT3 ((uint32_t)0x10000400)
|
||||||
|
#define DMA2_IT_TE3 ((uint32_t)0x10000800)
|
||||||
|
#define DMA2_IT_GL4 ((uint32_t)0x10001000)
|
||||||
|
#define DMA2_IT_TC4 ((uint32_t)0x10002000)
|
||||||
|
#define DMA2_IT_HT4 ((uint32_t)0x10004000)
|
||||||
|
#define DMA2_IT_TE4 ((uint32_t)0x10008000)
|
||||||
|
#define DMA2_IT_GL5 ((uint32_t)0x10010000)
|
||||||
|
#define DMA2_IT_TC5 ((uint32_t)0x10020000)
|
||||||
|
#define DMA2_IT_HT5 ((uint32_t)0x10040000)
|
||||||
|
#define DMA2_IT_TE5 ((uint32_t)0x10080000)
|
||||||
|
#define DMA2_IT_GL6 ((uint32_t)0x10100000)
|
||||||
|
#define DMA2_IT_TC6 ((uint32_t)0x10200000)
|
||||||
|
#define DMA2_IT_HT6 ((uint32_t)0x10400000)
|
||||||
|
#define DMA2_IT_TE6 ((uint32_t)0x10800000)
|
||||||
|
#define DMA2_IT_GL7 ((uint32_t)0x11000000)
|
||||||
|
#define DMA2_IT_TC7 ((uint32_t)0x12000000)
|
||||||
|
#define DMA2_IT_HT7 ((uint32_t)0x14000000)
|
||||||
|
#define DMA2_IT_TE7 ((uint32_t)0x18000000)
|
||||||
|
|
||||||
|
#define DMA2_IT_GL8 ((uint32_t)0x20000001)
|
||||||
|
#define DMA2_IT_TC8 ((uint32_t)0x20000002)
|
||||||
|
#define DMA2_IT_HT8 ((uint32_t)0x20000004)
|
||||||
|
#define DMA2_IT_TE8 ((uint32_t)0x20000008)
|
||||||
|
#define DMA2_IT_GL9 ((uint32_t)0x20000010)
|
||||||
|
#define DMA2_IT_TC9 ((uint32_t)0x20000020)
|
||||||
|
#define DMA2_IT_HT9 ((uint32_t)0x20000040)
|
||||||
|
#define DMA2_IT_TE9 ((uint32_t)0x20000080)
|
||||||
|
#define DMA2_IT_GL10 ((uint32_t)0x20000100)
|
||||||
|
#define DMA2_IT_TC10 ((uint32_t)0x20000200)
|
||||||
|
#define DMA2_IT_HT10 ((uint32_t)0x20000400)
|
||||||
|
#define DMA2_IT_TE10 ((uint32_t)0x20000800)
|
||||||
|
#define DMA2_IT_GL11 ((uint32_t)0x20001000)
|
||||||
|
#define DMA2_IT_TC11 ((uint32_t)0x20002000)
|
||||||
|
#define DMA2_IT_HT11 ((uint32_t)0x20004000)
|
||||||
|
#define DMA2_IT_TE11 ((uint32_t)0x20008000)
|
||||||
|
|
||||||
|
/* DMA_flags_definition */
|
||||||
|
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
|
||||||
|
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
|
||||||
|
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
|
||||||
|
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
|
||||||
|
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
|
||||||
|
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
|
||||||
|
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
|
||||||
|
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
|
||||||
|
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
|
||||||
|
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
|
||||||
|
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
|
||||||
|
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
|
||||||
|
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
|
||||||
|
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
|
||||||
|
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
|
||||||
|
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
|
||||||
|
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
|
||||||
|
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
|
||||||
|
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
|
||||||
|
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
|
||||||
|
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
|
||||||
|
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
|
||||||
|
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
|
||||||
|
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
|
||||||
|
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
|
||||||
|
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
|
||||||
|
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
|
||||||
|
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
|
||||||
|
|
||||||
|
#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
|
||||||
|
#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
|
||||||
|
#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
|
||||||
|
#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
|
||||||
|
#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
|
||||||
|
#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
|
||||||
|
#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
|
||||||
|
#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
|
||||||
|
#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
|
||||||
|
#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
|
||||||
|
#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
|
||||||
|
#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
|
||||||
|
#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
|
||||||
|
#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
|
||||||
|
#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
|
||||||
|
#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
|
||||||
|
#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
|
||||||
|
#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
|
||||||
|
#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
|
||||||
|
#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
|
||||||
|
#define DMA2_FLAG_GL6 ((uint32_t)0x10100000)
|
||||||
|
#define DMA2_FLAG_TC6 ((uint32_t)0x10200000)
|
||||||
|
#define DMA2_FLAG_HT6 ((uint32_t)0x10400000)
|
||||||
|
#define DMA2_FLAG_TE6 ((uint32_t)0x10800000)
|
||||||
|
#define DMA2_FLAG_GL7 ((uint32_t)0x11000000)
|
||||||
|
#define DMA2_FLAG_TC7 ((uint32_t)0x12000000)
|
||||||
|
#define DMA2_FLAG_HT7 ((uint32_t)0x14000000)
|
||||||
|
#define DMA2_FLAG_TE7 ((uint32_t)0x18000000)
|
||||||
|
|
||||||
|
#define DMA2_FLAG_GL8 ((uint32_t)0x20000001)
|
||||||
|
#define DMA2_FLAG_TC8 ((uint32_t)0x20000002)
|
||||||
|
#define DMA2_FLAG_HT8 ((uint32_t)0x20000004)
|
||||||
|
#define DMA2_FLAG_TE8 ((uint32_t)0x20000008)
|
||||||
|
#define DMA2_FLAG_GL9 ((uint32_t)0x20000010)
|
||||||
|
#define DMA2_FLAG_TC9 ((uint32_t)0x20000020)
|
||||||
|
#define DMA2_FLAG_HT9 ((uint32_t)0x20000040)
|
||||||
|
#define DMA2_FLAG_TE9 ((uint32_t)0x20000080)
|
||||||
|
#define DMA2_FLAG_GL10 ((uint32_t)0x20000100)
|
||||||
|
#define DMA2_FLAG_TC10 ((uint32_t)0x20000200)
|
||||||
|
#define DMA2_FLAG_HT10 ((uint32_t)0x20000400)
|
||||||
|
#define DMA2_FLAG_TE10 ((uint32_t)0x20000800)
|
||||||
|
#define DMA2_FLAG_GL11 ((uint32_t)0x20001000)
|
||||||
|
#define DMA2_FLAG_TC11 ((uint32_t)0x20002000)
|
||||||
|
#define DMA2_FLAG_HT11 ((uint32_t)0x20004000)
|
||||||
|
#define DMA2_FLAG_TE11 ((uint32_t)0x20008000)
|
||||||
|
|
||||||
|
|
||||||
|
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
|
||||||
|
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
|
||||||
|
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
|
||||||
|
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
|
||||||
|
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
|
||||||
|
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
|
||||||
|
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
|
||||||
|
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
|
||||||
|
void DMA_ClearFlag(uint32_t DMAy_FLAG);
|
||||||
|
ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
|
||||||
|
void DMA_ClearITPendingBit(uint32_t DMAy_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
69
Peripheral/inc/ch32v30x_dvp.h
Normal file
69
Peripheral/inc/ch32v30x_dvp.h
Normal file
@@ -0,0 +1,69 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_dvp.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* DVP firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_DVP_H
|
||||||
|
#define __CH32V30x_DVP_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* DVP Data Mode */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
Video_Mode = 0,
|
||||||
|
JPEG_Mode,
|
||||||
|
}DVP_Data_ModeTypeDef;
|
||||||
|
|
||||||
|
|
||||||
|
/* DVP DMA */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
DVP_DMA_Disable = 0,
|
||||||
|
DVP_DMA_Enable,
|
||||||
|
}DVP_DMATypeDef;
|
||||||
|
|
||||||
|
/* DVP FLAG and FIFO Reset */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
DVP_FLAG_FIFO_RESET_Disable = 0,
|
||||||
|
DVP_FLAG_FIFO_RESET_Enable,
|
||||||
|
}DVP_FLAG_FIFO_RESETTypeDef;
|
||||||
|
|
||||||
|
/* DVP RX Reset */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
DVP_RX_RESET_Disable = 0,
|
||||||
|
DVP_RX_RESET_Enable,
|
||||||
|
}DVP_RX_RESETTypeDef;
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
void DVP_INTCfg( uint8_t s, uint8_t i );
|
||||||
|
void DVP_Mode( uint8_t s, DVP_Data_ModeTypeDef i);
|
||||||
|
void DVP_Cfg( DVP_DMATypeDef s, DVP_FLAG_FIFO_RESETTypeDef i, DVP_RX_RESETTypeDef j);
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
1338
Peripheral/inc/ch32v30x_eth.h
Normal file
1338
Peripheral/inc/ch32v30x_eth.h
Normal file
File diff suppressed because it is too large
Load Diff
92
Peripheral/inc/ch32v30x_exti.h
Normal file
92
Peripheral/inc/ch32v30x_exti.h
Normal file
@@ -0,0 +1,92 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_exti.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* EXTI firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_EXTI_H
|
||||||
|
#define __CH32V30x_EXTI_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* EXTI mode enumeration */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
EXTI_Mode_Interrupt = 0x00,
|
||||||
|
EXTI_Mode_Event = 0x04
|
||||||
|
}EXTIMode_TypeDef;
|
||||||
|
|
||||||
|
/* EXTI Trigger enumeration */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
EXTI_Trigger_Rising = 0x08,
|
||||||
|
EXTI_Trigger_Falling = 0x0C,
|
||||||
|
EXTI_Trigger_Rising_Falling = 0x10
|
||||||
|
}EXTITrigger_TypeDef;
|
||||||
|
|
||||||
|
/* EXTI Init Structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled.
|
||||||
|
This parameter can be any combination of @ref EXTI_Lines */
|
||||||
|
|
||||||
|
EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines.
|
||||||
|
This parameter can be a value of @ref EXTIMode_TypeDef */
|
||||||
|
|
||||||
|
EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines.
|
||||||
|
This parameter can be a value of @ref EXTIMode_TypeDef */
|
||||||
|
|
||||||
|
FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines.
|
||||||
|
This parameter can be set either to ENABLE or DISABLE */
|
||||||
|
}EXTI_InitTypeDef;
|
||||||
|
|
||||||
|
|
||||||
|
/* EXTI_Lines */
|
||||||
|
#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */
|
||||||
|
#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */
|
||||||
|
#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */
|
||||||
|
#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */
|
||||||
|
#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */
|
||||||
|
#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */
|
||||||
|
#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */
|
||||||
|
#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */
|
||||||
|
#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */
|
||||||
|
#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */
|
||||||
|
#define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */
|
||||||
|
#define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */
|
||||||
|
#define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */
|
||||||
|
#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */
|
||||||
|
#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */
|
||||||
|
#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */
|
||||||
|
#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */
|
||||||
|
#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */
|
||||||
|
#define EXTI_Line18 ((uint32_t)0x40000) /* External interrupt line 18 Connected to the USBD/USBFS OTG
|
||||||
|
Wakeup from suspend event */
|
||||||
|
#define EXTI_Line19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the Ethernet Wakeup event */
|
||||||
|
#define EXTI_Line20 ((uint32_t)0x100000) /* External interrupt line 20 Connected to the USBHS Wakeup event */
|
||||||
|
|
||||||
|
void EXTI_DeInit(void);
|
||||||
|
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||||
|
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||||
|
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
|
||||||
|
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
|
||||||
|
void EXTI_ClearFlag(uint32_t EXTI_Line);
|
||||||
|
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
|
||||||
|
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
148
Peripheral/inc/ch32v30x_flash.h
Normal file
148
Peripheral/inc/ch32v30x_flash.h
Normal file
@@ -0,0 +1,148 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_flash.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2024/05/24
|
||||||
|
* Description : This file contains all the functions prototypes for the FLASH
|
||||||
|
* firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_FLASH_H
|
||||||
|
#define __CH32V30x_FLASH_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* FLASH Status */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
FLASH_BUSY = 1,
|
||||||
|
FLASH_ERROR_PG,
|
||||||
|
FLASH_ERROR_WRP,
|
||||||
|
FLASH_COMPLETE,
|
||||||
|
FLASH_TIMEOUT,
|
||||||
|
FLASH_OP_RANGE_ERROR = 0xFD,
|
||||||
|
FLASH_ALIGN_ERROR = 0xFE,
|
||||||
|
FLASH_ADR_RANGE_ERROR = 0xFF,
|
||||||
|
}FLASH_Status;
|
||||||
|
|
||||||
|
|
||||||
|
/* Write Protect */
|
||||||
|
#define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of setor 0 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of setor 1 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of setor 2 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of setor 3 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of setor 4 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of setor 5 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of setor 6 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of setor 7 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of setor 8 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of setor 9 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of setor 10 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of setor 11 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of setor 12 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of setor 13 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of setor 14 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of setor 15 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of setor 16 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of setor 17 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of setor 18 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of setor 19 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of setor 20 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of setor 21 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of setor 22 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of setor 23 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of setor 24 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of setor 25 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of setor 26 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of setor 27 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of setor 28 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of setor 29 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of setor 30 ,4K bytes/sector */
|
||||||
|
#define FLASH_WRProt_Sectors31to127 ((uint32_t)0x80000000) /* Write protection of page 31 to 127 */
|
||||||
|
|
||||||
|
#define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */
|
||||||
|
|
||||||
|
/* Option_Bytes_IWatchdog */
|
||||||
|
#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */
|
||||||
|
#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */
|
||||||
|
|
||||||
|
/* Option_Bytes_nRST_STOP */
|
||||||
|
#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */
|
||||||
|
#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */
|
||||||
|
|
||||||
|
/* Option_Bytes_nRST_STDBY */
|
||||||
|
#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */
|
||||||
|
#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */
|
||||||
|
|
||||||
|
/* FLASH_Interrupts */
|
||||||
|
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */
|
||||||
|
#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */
|
||||||
|
#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */
|
||||||
|
#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */
|
||||||
|
|
||||||
|
/* FLASH_Flags */
|
||||||
|
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */
|
||||||
|
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */
|
||||||
|
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */
|
||||||
|
#define FLASH_FLAG_OPTERR ((uint32_t)0x80000001) /* FLASH Option Byte error flag */
|
||||||
|
|
||||||
|
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/
|
||||||
|
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */
|
||||||
|
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */
|
||||||
|
|
||||||
|
/* FLASH_Access_CLK */
|
||||||
|
#define FLASH_Access_SYSTEM_HALF ((uint32_t)0x00000000) /* FLASH Access Clock = SYSTEM/2 */
|
||||||
|
#define FLASH_Access_SYSTEM ((uint32_t)0x02000000) /* FLASH Access Clock = SYSTEM */
|
||||||
|
|
||||||
|
|
||||||
|
/*Functions used for all devices*/
|
||||||
|
void FLASH_Unlock(void);
|
||||||
|
void FLASH_Lock(void);
|
||||||
|
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
|
||||||
|
FLASH_Status FLASH_EraseAllPages(void);
|
||||||
|
FLASH_Status FLASH_EraseOptionBytes(void);
|
||||||
|
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
|
||||||
|
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
|
||||||
|
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
|
||||||
|
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors);
|
||||||
|
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
|
||||||
|
FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
|
||||||
|
uint32_t FLASH_GetUserOptionByte(void);
|
||||||
|
uint32_t FLASH_GetWriteProtectionOptionByte(void);
|
||||||
|
FlagStatus FLASH_GetReadOutProtectionStatus(void);
|
||||||
|
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
|
||||||
|
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
|
||||||
|
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
|
||||||
|
FLASH_Status FLASH_GetStatus(void);
|
||||||
|
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||||
|
void FLASH_Unlock_Fast(void);
|
||||||
|
void FLASH_Lock_Fast(void);
|
||||||
|
void FLASH_ErasePage_Fast(uint32_t Page_Address);
|
||||||
|
void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address);
|
||||||
|
void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t* pbuf);
|
||||||
|
void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK);
|
||||||
|
void FLASH_Enhance_Mode(FunctionalState NewState);
|
||||||
|
|
||||||
|
/* New function used for all devices */
|
||||||
|
void FLASH_UnlockBank1(void);
|
||||||
|
void FLASH_LockBank1(void);
|
||||||
|
FLASH_Status FLASH_EraseAllBank1Pages(void);
|
||||||
|
FLASH_Status FLASH_GetBank1Status(void);
|
||||||
|
FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
|
||||||
|
FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length);
|
||||||
|
FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
268
Peripheral/inc/ch32v30x_fsmc.h
Normal file
268
Peripheral/inc/ch32v30x_fsmc.h
Normal file
@@ -0,0 +1,268 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_fsmc.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.1
|
||||||
|
* Date : 2025/03/06
|
||||||
|
* Description : This file contains all the functions prototypes for the FSMC
|
||||||
|
* firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_FSMC_H
|
||||||
|
#define __CH32V30x_FSMC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
|
||||||
|
/* FSMC Init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t FSMC_AddressSetupTime; /* Defines the number of HCLK cycles to configure
|
||||||
|
the duration of the address setup time.
|
||||||
|
This parameter can be a value between 0 and 0xF.
|
||||||
|
@note: It is not used with synchronous NOR Flash memories. */
|
||||||
|
|
||||||
|
uint32_t FSMC_AddressHoldTime; /* Defines the number of HCLK cycles to configure
|
||||||
|
the duration of the address hold time.
|
||||||
|
This parameter can be a value between 0 and 0xF.
|
||||||
|
@note: It is not used with synchronous NOR Flash memories.*/
|
||||||
|
|
||||||
|
uint32_t FSMC_DataSetupTime; /* Defines the number of HCLK cycles to configure
|
||||||
|
the duration of the data setup time.
|
||||||
|
This parameter can be a value between 0 and 0xFF.
|
||||||
|
@note: It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
|
||||||
|
|
||||||
|
uint32_t FSMC_BusTurnAroundDuration; /* Defines the number of HCLK cycles to configure
|
||||||
|
the duration of the bus turnaround.
|
||||||
|
This parameter can be a value between 0 and 0xF.
|
||||||
|
@note: It is only used for multiplexed NOR Flash memories. */
|
||||||
|
|
||||||
|
uint32_t FSMC_CLKDivision; /* Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
|
||||||
|
This parameter can be a value between 1 and 0xF.
|
||||||
|
@note: This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
|
||||||
|
|
||||||
|
uint32_t FSMC_DataLatency; /* Defines the number of memory clock cycles to issue
|
||||||
|
to the memory before getting the first data.
|
||||||
|
The value of this parameter depends on the memory type as shown below:
|
||||||
|
- It must be set to 0 in case of a CRAM
|
||||||
|
- It is don't care in asynchronous NOR, SRAM or ROM accesses
|
||||||
|
- It may assume a value between 0 and 0xF in NOR Flash memories
|
||||||
|
with synchronous burst mode enable */
|
||||||
|
|
||||||
|
uint32_t FSMC_AccessMode; /* Specifies the asynchronous access mode.
|
||||||
|
This parameter can be a value of @ref FSMC_Access_Mode */
|
||||||
|
}FSMC_NORSRAMTimingInitTypeDef;
|
||||||
|
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t FSMC_Bank; /* Specifies the NOR/SRAM memory bank that will be used.
|
||||||
|
This parameter can be a value of @ref FSMC_NORSRAM_Bank */
|
||||||
|
|
||||||
|
uint32_t FSMC_DataAddressMux; /* Specifies whether the address and data values are
|
||||||
|
multiplexed on the databus or not.
|
||||||
|
This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
|
||||||
|
|
||||||
|
uint32_t FSMC_MemoryType; /* Specifies the type of external memory attached to
|
||||||
|
the corresponding memory bank.
|
||||||
|
This parameter can be a value of @ref FSMC_Memory_Type */
|
||||||
|
|
||||||
|
uint32_t FSMC_MemoryDataWidth; /* Specifies the external memory device width.
|
||||||
|
This parameter can be a value of @ref FSMC_Data_Width */
|
||||||
|
|
||||||
|
uint32_t FSMC_BurstAccessMode; /* Enables or disables the burst access mode for Flash memory,
|
||||||
|
valid only with synchronous burst Flash memories.
|
||||||
|
This parameter can be a value of @ref FSMC_Burst_Access_Mode */
|
||||||
|
|
||||||
|
uint32_t FSMC_AsynchronousWait; /* Enables or disables wait signal during asynchronous transfers,
|
||||||
|
valid only with asynchronous Flash memories.
|
||||||
|
This parameter can be a value of @ref FSMC_AsynchronousWait */
|
||||||
|
|
||||||
|
uint32_t FSMC_WaitSignalPolarity; /* Specifies the wait signal polarity, valid only when accessing
|
||||||
|
the Flash memory in burst mode.
|
||||||
|
This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
|
||||||
|
|
||||||
|
uint32_t FSMC_WaitSignalActive; /* Specifies if the wait signal is asserted by the memory one
|
||||||
|
clock cycle before the wait state or during the wait state,
|
||||||
|
valid only when accessing memories in burst mode.
|
||||||
|
This parameter can be a value of @ref FSMC_Wait_Timing */
|
||||||
|
|
||||||
|
uint32_t FSMC_WriteOperation; /* Enables or disables the write operation in the selected bank by the FSMC.
|
||||||
|
This parameter can be a value of @ref FSMC_Write_Operation */
|
||||||
|
|
||||||
|
uint32_t FSMC_WaitSignal; /* Enables or disables the wait-state insertion via wait
|
||||||
|
signal, valid for Flash memory access in burst mode.
|
||||||
|
This parameter can be a value of @ref FSMC_Wait_Signal */
|
||||||
|
|
||||||
|
uint32_t FSMC_ExtendedMode; /* Enables or disables the extended mode.
|
||||||
|
This parameter can be a value of @ref FSMC_Extended_Mode */
|
||||||
|
|
||||||
|
uint32_t FSMC_WriteBurst; /* Enables or disables the write burst operation.
|
||||||
|
This parameter can be a value of @ref FSMC_Write_Burst */
|
||||||
|
|
||||||
|
FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /* Timing Parameters for write and read access if the ExtendedMode is not used*/
|
||||||
|
|
||||||
|
FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /* Timing Parameters for write access if the ExtendedMode is used*/
|
||||||
|
}FSMC_NORSRAMInitTypeDef;
|
||||||
|
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t FSMC_SetupTime; /* Defines the number of HCLK cycles to setup address before
|
||||||
|
the command assertion for NAND-Flash read or write access
|
||||||
|
to common/Attribute or I/O memory space (depending on
|
||||||
|
the memory space timing to be configured).
|
||||||
|
This parameter can be a value between 0 and 0xFF.*/
|
||||||
|
|
||||||
|
uint32_t FSMC_WaitSetupTime; /* Defines the minimum number of HCLK cycles to assert the
|
||||||
|
command for NAND-Flash read or write access to
|
||||||
|
common/Attribute or I/O memory space (depending on the
|
||||||
|
memory space timing to be configured).
|
||||||
|
This parameter can be a number between 0x00 and 0xFF */
|
||||||
|
|
||||||
|
uint32_t FSMC_HoldSetupTime; /* Defines the number of HCLK clock cycles to hold address
|
||||||
|
(and data for write access) after the command deassertion
|
||||||
|
for NAND-Flash read or write access to common/Attribute
|
||||||
|
or I/O memory space (depending on the memory space timing
|
||||||
|
to be configured).
|
||||||
|
This parameter can be a number between 0x00 and 0xFF */
|
||||||
|
|
||||||
|
uint32_t FSMC_HiZSetupTime; /* Defines the number of HCLK clock cycles during which the
|
||||||
|
databus is kept in HiZ after the start of a NAND-Flash
|
||||||
|
write access to common/Attribute or I/O memory space (depending
|
||||||
|
on the memory space timing to be configured).
|
||||||
|
This parameter can be a number between 0x00 and 0xFF */
|
||||||
|
}FSMC_NAND_PCCARDTimingInitTypeDef;
|
||||||
|
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t FSMC_Bank; /* Specifies the NAND memory bank that will be used.
|
||||||
|
This parameter can be a value of @ref FSMC_NAND_Bank */
|
||||||
|
|
||||||
|
uint32_t FSMC_Waitfeature; /* Enables or disables the Wait feature for the NAND Memory Bank.
|
||||||
|
This parameter can be any value of @ref FSMC_Wait_feature */
|
||||||
|
|
||||||
|
uint32_t FSMC_MemoryDataWidth; /* Specifies the external memory device width.
|
||||||
|
This parameter can be any value of @ref FSMC_Data_Width */
|
||||||
|
|
||||||
|
uint32_t FSMC_ECC; /* Enables or disables the ECC computation.
|
||||||
|
This parameter can be any value of @ref FSMC_ECC */
|
||||||
|
|
||||||
|
uint32_t FSMC_ECCPageSize; /* Defines the page size for the extended ECC.
|
||||||
|
This parameter can be any value of @ref FSMC_ECC_Page_Size */
|
||||||
|
|
||||||
|
uint32_t FSMC_TCLRSetupTime; /* Defines the number of HCLK cycles to configure the
|
||||||
|
delay between CLE low and RE low.
|
||||||
|
This parameter can be a value between 0 and 0xFF. */
|
||||||
|
|
||||||
|
uint32_t FSMC_TARSetupTime; /* Defines the number of HCLK cycles to configure the
|
||||||
|
delay between ALE low and RE low.
|
||||||
|
This parameter can be a number between 0x0 and 0xFF */
|
||||||
|
|
||||||
|
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_CommonSpaceTimingStruct; /* FSMC Common Space Timing */
|
||||||
|
|
||||||
|
FSMC_NAND_PCCARDTimingInitTypeDef* FSMC_AttributeSpaceTimingStruct; /* FSMC Attribute Space Timing */
|
||||||
|
}FSMC_NANDInitTypeDef;
|
||||||
|
|
||||||
|
|
||||||
|
/* FSMC_NORSRAM_Bank */
|
||||||
|
#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
|
||||||
|
|
||||||
|
/* FSMC_NAND_Bank */
|
||||||
|
#define FSMC_Bank2_NAND ((uint32_t)0x00000010)
|
||||||
|
|
||||||
|
/* FSMC_Data_Address_Bus_Multiplexing */
|
||||||
|
#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
|
||||||
|
|
||||||
|
/* FSMC_Memory_Type */
|
||||||
|
#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
|
||||||
|
#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
|
||||||
|
|
||||||
|
/* FSMC_Data_Width */
|
||||||
|
#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
|
||||||
|
|
||||||
|
/* FSMC_Burst_Access_Mode */
|
||||||
|
#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
|
||||||
|
|
||||||
|
/* FSMC_AsynchronousWait */
|
||||||
|
#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
|
||||||
|
|
||||||
|
/* FSMC_Wait_Signal_Polarity */
|
||||||
|
#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
|
||||||
|
|
||||||
|
/* FSMC_Wait_Timing */
|
||||||
|
#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
|
||||||
|
|
||||||
|
/* FSMC_Write_Operation */
|
||||||
|
#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
|
||||||
|
|
||||||
|
/* FSMC_Wait_Signal */
|
||||||
|
#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
|
||||||
|
|
||||||
|
/* FSMC_Extended_Mode */
|
||||||
|
#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
|
||||||
|
|
||||||
|
/* FSMC_Write_Burst */
|
||||||
|
#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
|
||||||
|
|
||||||
|
/* FSMC_Access_Mode */
|
||||||
|
#define FSMC_AccessMode_A ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_AccessMode_B ((uint32_t)0x10000000)
|
||||||
|
#define FSMC_AccessMode_C ((uint32_t)0x20000000)
|
||||||
|
#define FSMC_AccessMode_D ((uint32_t)0x30000000)
|
||||||
|
|
||||||
|
/* FSMC_Wait_feature */
|
||||||
|
#define FSMC_Waitfeature_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_Waitfeature_Enable ((uint32_t)0x00000002)
|
||||||
|
|
||||||
|
/* FSMC_ECC */
|
||||||
|
#define FSMC_ECC_Disable ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_ECC_Enable ((uint32_t)0x00000040)
|
||||||
|
|
||||||
|
/* FSMC_ECC_Page_Size */
|
||||||
|
#define FSMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
|
||||||
|
#define FSMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
|
||||||
|
#define FSMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
|
||||||
|
#define FSMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
|
||||||
|
#define FSMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
|
||||||
|
#define FSMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
|
||||||
|
|
||||||
|
#define FSMC_FLAG_FEMPT ((uint32_t)0x00000040)
|
||||||
|
|
||||||
|
|
||||||
|
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
|
||||||
|
void FSMC_NANDDeInit(uint32_t FSMC_Bank);
|
||||||
|
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
|
||||||
|
void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
|
||||||
|
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
|
||||||
|
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
|
||||||
|
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
|
||||||
|
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
|
||||||
|
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
|
||||||
|
uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
|
||||||
|
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
196
Peripheral/inc/ch32v30x_gpio.h
Normal file
196
Peripheral/inc/ch32v30x_gpio.h
Normal file
@@ -0,0 +1,196 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_gpio.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.1
|
||||||
|
* Date : 2025/04/09
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* GPIO firmware library.
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_GPIO_H
|
||||||
|
#define __CH32V30x_GPIO_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* Output Maximum frequency selection */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
GPIO_Speed_10MHz = 1,
|
||||||
|
GPIO_Speed_2MHz,
|
||||||
|
GPIO_Speed_50MHz
|
||||||
|
}GPIOSpeed_TypeDef;
|
||||||
|
|
||||||
|
/* Configuration Mode enumeration */
|
||||||
|
typedef enum
|
||||||
|
{ GPIO_Mode_AIN = 0x0,
|
||||||
|
GPIO_Mode_IN_FLOATING = 0x04,
|
||||||
|
GPIO_Mode_IPD = 0x28,
|
||||||
|
GPIO_Mode_IPU = 0x48,
|
||||||
|
GPIO_Mode_Out_OD = 0x14,
|
||||||
|
GPIO_Mode_Out_PP = 0x10,
|
||||||
|
GPIO_Mode_AF_OD = 0x1C,
|
||||||
|
GPIO_Mode_AF_PP = 0x18
|
||||||
|
}GPIOMode_TypeDef;
|
||||||
|
|
||||||
|
/* GPIO Init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured.
|
||||||
|
This parameter can be any value of @ref GPIO_pins_define */
|
||||||
|
|
||||||
|
GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins.
|
||||||
|
This parameter can be a value of @ref GPIOSpeed_TypeDef */
|
||||||
|
|
||||||
|
GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins.
|
||||||
|
This parameter can be a value of @ref GPIOMode_TypeDef */
|
||||||
|
}GPIO_InitTypeDef;
|
||||||
|
|
||||||
|
/* Bit_SET and Bit_RESET enumeration */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
Bit_RESET = 0,
|
||||||
|
Bit_SET
|
||||||
|
}BitAction;
|
||||||
|
|
||||||
|
/* GPIO_pins_define */
|
||||||
|
#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */
|
||||||
|
#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */
|
||||||
|
#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */
|
||||||
|
#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */
|
||||||
|
#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */
|
||||||
|
#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */
|
||||||
|
#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */
|
||||||
|
#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */
|
||||||
|
#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */
|
||||||
|
#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */
|
||||||
|
#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */
|
||||||
|
#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */
|
||||||
|
#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */
|
||||||
|
#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */
|
||||||
|
#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */
|
||||||
|
#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */
|
||||||
|
#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */
|
||||||
|
|
||||||
|
/* GPIO_Remap_define */
|
||||||
|
/* PCFR1 */
|
||||||
|
#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */
|
||||||
|
#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */
|
||||||
|
#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /* USART1 Alternate Function mapping low bit */
|
||||||
|
#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /* USART2 Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /* USART3 Partial Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap1_USART3 ((uint32_t)0x00140020) /* USART3 Partial1 Alternate Function mapping */
|
||||||
|
#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */
|
||||||
|
#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */
|
||||||
|
#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */
|
||||||
|
#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */
|
||||||
|
#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */
|
||||||
|
#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */
|
||||||
|
#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */
|
||||||
|
#define GPIO_Remap_PD0PD1 ((uint32_t)0x00008000) /* PD0 and PD1 Alternate Function mapping */
|
||||||
|
#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */
|
||||||
|
#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */
|
||||||
|
#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */
|
||||||
|
#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */
|
||||||
|
#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */
|
||||||
|
#define GPIO_Remap_ETH ((uint32_t)0x00200020) /* Ethernet remapping (only for Connectivity line devices) */
|
||||||
|
#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /* CAN2 remapping (only for Connectivity line devices) */
|
||||||
|
#define GPIO_Remap_MII_RMII_SEL ((uint32_t)0x00200080) /* MII or RMII selection */
|
||||||
|
#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled */
|
||||||
|
#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /* SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
|
||||||
|
#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected
|
||||||
|
to TIM2 Internal Trigger 1 for calibration
|
||||||
|
(only for Connectivity line devices) */
|
||||||
|
#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /* Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
|
||||||
|
#define GPIO_Remap_PD01 GPIO_Remap_PD0PD1
|
||||||
|
|
||||||
|
/* PCFR2 */
|
||||||
|
#define GPIO_Remap_TIM8 ((uint32_t)0x80000004) /* TIM8 Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap_TIM9 ((uint32_t)0x80130008) /* TIM9 Partial Alternate Function mapping */
|
||||||
|
#define GPIO_FullRemap_TIM9 ((uint32_t)0x80130010) /* TIM9 Full Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap_TIM10 ((uint32_t)0x80150020) /* TIM10 Partial Alternate Function mapping */
|
||||||
|
#define GPIO_FullRemap_TIM10 ((uint32_t)0x80150040) /* TIM10 Full Alternate Function mapping */
|
||||||
|
#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /* FSMC_NADV Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap_USART4 ((uint32_t)0x80300001) /* USART4 Partial Alternate Function mapping */
|
||||||
|
#define GPIO_FullRemap_USART4 ((uint32_t)0x80300002) /* USART4 Full Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap_USART5 ((uint32_t)0x80320004) /* USART5 Partial Alternate Function mapping */
|
||||||
|
#define GPIO_FullRemap_USART5 ((uint32_t)0x80320008) /* USART5 Full Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap_USART6 ((uint32_t)0x80340010) /* USART6 Partial Alternate Function mapping */
|
||||||
|
#define GPIO_FullRemap_USART6 ((uint32_t)0x80340020) /* USART6 Full Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap_USART7 ((uint32_t)0x80360040) /* USART7 Partial Alternate Function mapping */
|
||||||
|
#define GPIO_FullRemap_USART7 ((uint32_t)0x80360080) /* USART7 Full Alternate Function mapping */
|
||||||
|
#define GPIO_PartialRemap_USART8 ((uint32_t)0x80380100) /* USART8 Partial Alternate Function mapping */
|
||||||
|
#define GPIO_FullRemap_USART8 ((uint32_t)0x80380200) /* USART8 Full Alternate Function mapping */
|
||||||
|
#define GPIO_Remap_USART1_HighBit ((uint32_t)0x80200400) /* USART1 Alternate Function mapping high bit */
|
||||||
|
|
||||||
|
|
||||||
|
/* GPIO_Port_Sources */
|
||||||
|
#define GPIO_PortSourceGPIOA ((uint8_t)0x00)
|
||||||
|
#define GPIO_PortSourceGPIOB ((uint8_t)0x01)
|
||||||
|
#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
|
||||||
|
#define GPIO_PortSourceGPIOD ((uint8_t)0x03)
|
||||||
|
#define GPIO_PortSourceGPIOE ((uint8_t)0x04)
|
||||||
|
|
||||||
|
/* GPIO_Pin_sources */
|
||||||
|
#define GPIO_PinSource0 ((uint8_t)0x00)
|
||||||
|
#define GPIO_PinSource1 ((uint8_t)0x01)
|
||||||
|
#define GPIO_PinSource2 ((uint8_t)0x02)
|
||||||
|
#define GPIO_PinSource3 ((uint8_t)0x03)
|
||||||
|
#define GPIO_PinSource4 ((uint8_t)0x04)
|
||||||
|
#define GPIO_PinSource5 ((uint8_t)0x05)
|
||||||
|
#define GPIO_PinSource6 ((uint8_t)0x06)
|
||||||
|
#define GPIO_PinSource7 ((uint8_t)0x07)
|
||||||
|
#define GPIO_PinSource8 ((uint8_t)0x08)
|
||||||
|
#define GPIO_PinSource9 ((uint8_t)0x09)
|
||||||
|
#define GPIO_PinSource10 ((uint8_t)0x0A)
|
||||||
|
#define GPIO_PinSource11 ((uint8_t)0x0B)
|
||||||
|
#define GPIO_PinSource12 ((uint8_t)0x0C)
|
||||||
|
#define GPIO_PinSource13 ((uint8_t)0x0D)
|
||||||
|
#define GPIO_PinSource14 ((uint8_t)0x0E)
|
||||||
|
#define GPIO_PinSource15 ((uint8_t)0x0F)
|
||||||
|
|
||||||
|
/* Ethernet_Media_Interface */
|
||||||
|
#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000)
|
||||||
|
#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001)
|
||||||
|
|
||||||
|
|
||||||
|
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
|
||||||
|
void GPIO_AFIODeInit(void);
|
||||||
|
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
|
||||||
|
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
|
||||||
|
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||||
|
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
|
||||||
|
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||||
|
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
|
||||||
|
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||||
|
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||||
|
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
|
||||||
|
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
|
||||||
|
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||||
|
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
|
||||||
|
void GPIO_EventOutputCmd(FunctionalState NewState);
|
||||||
|
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
|
||||||
|
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
|
||||||
|
void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
439
Peripheral/inc/ch32v30x_i2c.h
Normal file
439
Peripheral/inc/ch32v30x_i2c.h
Normal file
@@ -0,0 +1,439 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_i2c.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* I2C firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_I2C_H
|
||||||
|
#define __CH32V30x_I2C_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* I2C Init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t I2C_ClockSpeed; /* Specifies the clock frequency.
|
||||||
|
This parameter must be set to a value lower than 400kHz */
|
||||||
|
|
||||||
|
uint16_t I2C_Mode; /* Specifies the I2C mode.
|
||||||
|
This parameter can be a value of @ref I2C_mode */
|
||||||
|
|
||||||
|
uint16_t I2C_DutyCycle; /* Specifies the I2C fast mode duty cycle.
|
||||||
|
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
|
||||||
|
|
||||||
|
uint16_t I2C_OwnAddress1; /* Specifies the first device own address.
|
||||||
|
This parameter can be a 7-bit or 10-bit address. */
|
||||||
|
|
||||||
|
uint16_t I2C_Ack; /* Enables or disables the acknowledgement.
|
||||||
|
This parameter can be a value of @ref I2C_acknowledgement */
|
||||||
|
|
||||||
|
uint16_t I2C_AcknowledgedAddress; /* Specifies if 7-bit or 10-bit address is acknowledged.
|
||||||
|
This parameter can be a value of @ref I2C_acknowledged_address */
|
||||||
|
}I2C_InitTypeDef;
|
||||||
|
|
||||||
|
/* I2C_mode */
|
||||||
|
#define I2C_Mode_I2C ((uint16_t)0x0000)
|
||||||
|
#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
|
||||||
|
#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
|
||||||
|
|
||||||
|
/* I2C_duty_cycle_in_fast_mode */
|
||||||
|
#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */
|
||||||
|
#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */
|
||||||
|
|
||||||
|
/* I2C_acknowledgement */
|
||||||
|
#define I2C_Ack_Enable ((uint16_t)0x0400)
|
||||||
|
#define I2C_Ack_Disable ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* I2C_transfer_direction */
|
||||||
|
#define I2C_Direction_Transmitter ((uint8_t)0x00)
|
||||||
|
#define I2C_Direction_Receiver ((uint8_t)0x01)
|
||||||
|
|
||||||
|
/* I2C_acknowledged_address */
|
||||||
|
#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
|
||||||
|
#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
|
||||||
|
|
||||||
|
/* I2C_registers */
|
||||||
|
#define I2C_Register_CTLR1 ((uint8_t)0x00)
|
||||||
|
#define I2C_Register_CTLR2 ((uint8_t)0x04)
|
||||||
|
#define I2C_Register_OADDR1 ((uint8_t)0x08)
|
||||||
|
#define I2C_Register_OADDR2 ((uint8_t)0x0C)
|
||||||
|
#define I2C_Register_DATAR ((uint8_t)0x10)
|
||||||
|
#define I2C_Register_STAR1 ((uint8_t)0x14)
|
||||||
|
#define I2C_Register_STAR2 ((uint8_t)0x18)
|
||||||
|
#define I2C_Register_CKCFGR ((uint8_t)0x1C)
|
||||||
|
#define I2C_Register_RTR ((uint8_t)0x20)
|
||||||
|
|
||||||
|
/* I2C_SMBus_alert_pin_level */
|
||||||
|
#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
|
||||||
|
#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
|
||||||
|
|
||||||
|
/* I2C_PEC_position */
|
||||||
|
#define I2C_PECPosition_Next ((uint16_t)0x0800)
|
||||||
|
#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
|
||||||
|
|
||||||
|
/* I2C_NACK_position */
|
||||||
|
#define I2C_NACKPosition_Next ((uint16_t)0x0800)
|
||||||
|
#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
|
||||||
|
|
||||||
|
/* I2C_interrupts_definition */
|
||||||
|
#define I2C_IT_BUF ((uint16_t)0x0400)
|
||||||
|
#define I2C_IT_EVT ((uint16_t)0x0200)
|
||||||
|
#define I2C_IT_ERR ((uint16_t)0x0100)
|
||||||
|
|
||||||
|
/* I2C_interrupts_definition */
|
||||||
|
#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
|
||||||
|
#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
|
||||||
|
#define I2C_IT_PECERR ((uint32_t)0x01001000)
|
||||||
|
#define I2C_IT_OVR ((uint32_t)0x01000800)
|
||||||
|
#define I2C_IT_AF ((uint32_t)0x01000400)
|
||||||
|
#define I2C_IT_ARLO ((uint32_t)0x01000200)
|
||||||
|
#define I2C_IT_BERR ((uint32_t)0x01000100)
|
||||||
|
#define I2C_IT_TXE ((uint32_t)0x06000080)
|
||||||
|
#define I2C_IT_RXNE ((uint32_t)0x06000040)
|
||||||
|
#define I2C_IT_STOPF ((uint32_t)0x02000010)
|
||||||
|
#define I2C_IT_ADD10 ((uint32_t)0x02000008)
|
||||||
|
#define I2C_IT_BTF ((uint32_t)0x02000004)
|
||||||
|
#define I2C_IT_ADDR ((uint32_t)0x02000002)
|
||||||
|
#define I2C_IT_SB ((uint32_t)0x02000001)
|
||||||
|
|
||||||
|
/* SR2 register flags */
|
||||||
|
#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
|
||||||
|
#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
|
||||||
|
#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
|
||||||
|
#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
|
||||||
|
#define I2C_FLAG_TRA ((uint32_t)0x00040000)
|
||||||
|
#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
|
||||||
|
#define I2C_FLAG_MSL ((uint32_t)0x00010000)
|
||||||
|
|
||||||
|
/* SR1 register flags */
|
||||||
|
#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
|
||||||
|
#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
|
||||||
|
#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
|
||||||
|
#define I2C_FLAG_OVR ((uint32_t)0x10000800)
|
||||||
|
#define I2C_FLAG_AF ((uint32_t)0x10000400)
|
||||||
|
#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
|
||||||
|
#define I2C_FLAG_BERR ((uint32_t)0x10000100)
|
||||||
|
#define I2C_FLAG_TXE ((uint32_t)0x10000080)
|
||||||
|
#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
|
||||||
|
#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
|
||||||
|
#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
|
||||||
|
#define I2C_FLAG_BTF ((uint32_t)0x10000004)
|
||||||
|
#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
|
||||||
|
#define I2C_FLAG_SB ((uint32_t)0x10000001)
|
||||||
|
|
||||||
|
|
||||||
|
/****************I2C Master Events (Events grouped in order of communication)********************/
|
||||||
|
|
||||||
|
/********************************************************************************************************************
|
||||||
|
* @brief Start communicate
|
||||||
|
*
|
||||||
|
* After master use I2C_GenerateSTART() function sending the START condition,the master
|
||||||
|
* has to wait for event 5(the Start condition has been correctly
|
||||||
|
* released on the I2C bus ).
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
/* EVT5 */
|
||||||
|
#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
|
||||||
|
|
||||||
|
/********************************************************************************************************************
|
||||||
|
* @brief Address Acknowledge
|
||||||
|
*
|
||||||
|
* When start condition correctly released on the bus(check EVT5), the
|
||||||
|
* master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate
|
||||||
|
* it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges
|
||||||
|
* his address. If an acknowledge is sent on the bus, one of the following events will be set:
|
||||||
|
*
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
|
||||||
|
* event is set.
|
||||||
|
*
|
||||||
|
* 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
|
||||||
|
* is set
|
||||||
|
*
|
||||||
|
* 3) In case of 10-Bit addressing mode, the master (after generating the START
|
||||||
|
* and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode.
|
||||||
|
* Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent
|
||||||
|
* on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part
|
||||||
|
* of the 10-bit address (LSB) . Then master should wait for event 6.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* EVT6 */
|
||||||
|
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
|
||||||
|
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
|
||||||
|
/*EVT9 */
|
||||||
|
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
|
||||||
|
|
||||||
|
/********************************************************************************************************************
|
||||||
|
* @brief Communication events
|
||||||
|
*
|
||||||
|
* If START condition has generated and slave address
|
||||||
|
* been acknowledged. then the master has to check one of the following events for
|
||||||
|
* communication procedures:
|
||||||
|
*
|
||||||
|
* 1) Master Receiver mode: The master has to wait on the event EVT7 then use
|
||||||
|
* I2C_ReceiveData() function to read the data received from the slave .
|
||||||
|
*
|
||||||
|
* 2) Master Transmitter mode: The master use I2C_SendData() function to send data
|
||||||
|
* then to wait on event EVT8 or EVT8_2.
|
||||||
|
* These two events are similar:
|
||||||
|
* - EVT8 means that the data has been written in the data register and is
|
||||||
|
* being shifted out.
|
||||||
|
* - EVT8_2 means that the data has been physically shifted out and output
|
||||||
|
* on the bus.
|
||||||
|
* In most cases, using EVT8 is sufficient for the application.
|
||||||
|
* Using EVT8_2 will leads to a slower communication speed but will more reliable .
|
||||||
|
* EVT8_2 is also more suitable than EVT8 for testing on the last data transmission
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Note:
|
||||||
|
* In case the user software does not guarantee that this event EVT7 is managed before
|
||||||
|
* the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED
|
||||||
|
* and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Master Receive mode */
|
||||||
|
/* EVT7 */
|
||||||
|
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
|
||||||
|
|
||||||
|
/* Master Transmitter mode*/
|
||||||
|
/* EVT8 */
|
||||||
|
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
|
||||||
|
/* EVT8_2 */
|
||||||
|
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
|
||||||
|
|
||||||
|
|
||||||
|
/******************I2C Slave Events (Events grouped in order of communication)******************/
|
||||||
|
|
||||||
|
/********************************************************************************************************************
|
||||||
|
* @brief Start Communicate events
|
||||||
|
*
|
||||||
|
* Wait on one of these events at the start of the communication. It means that
|
||||||
|
* the I2C peripheral detected a start condition of master device generate on the bus.
|
||||||
|
* If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* a) In normal case (only one address managed by the slave), when the address
|
||||||
|
* sent by the master matches the own address of the peripheral (configured by
|
||||||
|
* I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
|
||||||
|
* (where XXX could be TRANSMITTER or RECEIVER).
|
||||||
|
*
|
||||||
|
* b) In case the address sent by the master matches the second address of the
|
||||||
|
* peripheral (configured by the function I2C_OwnAddress2Config() and enabled
|
||||||
|
* by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
|
||||||
|
* (where XXX could be TRANSMITTER or RECEIVER) are set.
|
||||||
|
*
|
||||||
|
* c) In case the address sent by the master is General Call (address 0x00) and
|
||||||
|
* if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
|
||||||
|
* the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* EVT1 */
|
||||||
|
/* a) Case of One Single Address managed by the slave */
|
||||||
|
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
|
||||||
|
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
|
||||||
|
|
||||||
|
/* b) Case of Dual address managed by the slave */
|
||||||
|
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
|
||||||
|
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
|
||||||
|
|
||||||
|
/* c) Case of General Call enabled for the slave */
|
||||||
|
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
|
||||||
|
|
||||||
|
/********************************************************************************************************************
|
||||||
|
* @brief Communication events
|
||||||
|
*
|
||||||
|
* Wait on one of these events when EVT1 has already been checked :
|
||||||
|
*
|
||||||
|
* - Slave Receiver mode:
|
||||||
|
* - EVT2--The device is expecting to receive a data byte .
|
||||||
|
* - EVT4--The device is expecting the end of the communication: master
|
||||||
|
* sends a stop condition and data transmission is stopped.
|
||||||
|
*
|
||||||
|
* - Slave Transmitter mode:
|
||||||
|
* - EVT3--When a byte has been transmitted by the slave and the Master is expecting
|
||||||
|
* the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
|
||||||
|
* I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee
|
||||||
|
* the EVT3 is managed before the current byte end of transfer The second one can optionally
|
||||||
|
* be used.
|
||||||
|
* - EVT3_2--When the master sends a NACK to tell slave device that data transmission
|
||||||
|
* shall end . The slave device has to stop sending
|
||||||
|
* data bytes and wait a Stop condition from bus.
|
||||||
|
*
|
||||||
|
* Note:
|
||||||
|
* If the user software does not guarantee that the event 2 is
|
||||||
|
* managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED
|
||||||
|
* and I2C_FLAG_BTF flag at the same time .
|
||||||
|
* In this case the communication will be slower.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Slave Receiver mode*/
|
||||||
|
/* EVT2 */
|
||||||
|
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
|
||||||
|
/* EVT4 */
|
||||||
|
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
|
||||||
|
|
||||||
|
/* Slave Transmitter mode*/
|
||||||
|
/* EVT3 */
|
||||||
|
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
|
||||||
|
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
|
||||||
|
/*EVT3_2 */
|
||||||
|
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
|
||||||
|
|
||||||
|
|
||||||
|
void I2C_DeInit(I2C_TypeDef* I2Cx);
|
||||||
|
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
|
||||||
|
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
|
||||||
|
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
|
||||||
|
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
|
||||||
|
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
|
||||||
|
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
|
||||||
|
void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
|
||||||
|
uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
|
||||||
|
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
|
||||||
|
void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
|
||||||
|
void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
|
||||||
|
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
|
||||||
|
void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||||
|
void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
|
||||||
|
|
||||||
|
|
||||||
|
/*****************************************************************************************
|
||||||
|
*
|
||||||
|
* I2C State Monitoring Functions
|
||||||
|
*
|
||||||
|
****************************************************************************************
|
||||||
|
* This I2C driver provides three different ways for I2C state monitoring
|
||||||
|
* profit the application requirements and constraints:
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* a) First way:
|
||||||
|
* Using I2C_CheckEvent() function:
|
||||||
|
* It compares the status registers (STARR1 and STAR2) content to a given event
|
||||||
|
* (can be the combination of more flags).
|
||||||
|
* If the current status registers includes the given flags will return SUCCESS.
|
||||||
|
* and if the current status registers miss flags will returns ERROR.
|
||||||
|
* - When to use:
|
||||||
|
* - This function is suitable for most applications as well as for startup
|
||||||
|
* activity since the events are fully described in the product reference manual
|
||||||
|
* (CH32FV2x-V3xRM).
|
||||||
|
* - It is also suitable for users who need to define their own events.
|
||||||
|
* - Limitations:
|
||||||
|
* - If an error occurs besides to the monitored error,
|
||||||
|
* the I2C_CheckEvent() function may return SUCCESS despite the communication
|
||||||
|
* in corrupted state. it is suggeted to use error interrupts to monitor the error
|
||||||
|
* events and handle them in IRQ handler.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* Note:
|
||||||
|
* The following functions are recommended for error management: :
|
||||||
|
* - I2C_ITConfig() main function of configure and enable the error interrupts.
|
||||||
|
* - I2Cx_ER_IRQHandler() will be called when the error interrupt happen.
|
||||||
|
* Where x is the peripheral instance (I2C1, I2C2 ...)
|
||||||
|
* - I2Cx_ER_IRQHandler() will call I2C_GetFlagStatus() or I2C_GetITStatus() functions
|
||||||
|
* to determine which error occurred.
|
||||||
|
* - I2C_ClearFlag() \ I2C_ClearITPendingBit() \ I2C_SoftwareResetCmd()
|
||||||
|
* \ I2C_GenerateStop() will be use to clear the error flag and source,
|
||||||
|
* and return to correct communication status.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* b) Second way:
|
||||||
|
* Using the function to get a single word(uint32_t) composed of status register 1 and register 2.
|
||||||
|
* (Status Register 2 value is shifted left by 16 bits and concatenated to Status Register 1).
|
||||||
|
* - When to use:
|
||||||
|
*
|
||||||
|
* - This function is suitable for the same applications above but it
|
||||||
|
* don't have the limitations of I2C_GetFlagStatus() function .
|
||||||
|
* The returned value could be compared to events already defined in the
|
||||||
|
* library (CH32V30x_i2c.h) or to custom values defined by user.
|
||||||
|
* - This function can be used to monitor the status of multiple flags simultaneously.
|
||||||
|
* - Contrary to the I2C_CheckEvent () function, this function can choose the time to
|
||||||
|
* accept the event according to the user's needs (when all event flags are set and
|
||||||
|
* no other flags are set, or only when the required flags are set)
|
||||||
|
*
|
||||||
|
* - Limitations:
|
||||||
|
* - User may need to define his own events.
|
||||||
|
* - Same remark concerning the error management is applicable for this
|
||||||
|
* function if user decides to check only regular communication flags (and
|
||||||
|
* ignores error flags).
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* c) Third way:
|
||||||
|
* Using the function I2C_GetFlagStatus() get the status of
|
||||||
|
* one single flag .
|
||||||
|
* - When to use:
|
||||||
|
* - This function could be used for specific applications or in debug phase.
|
||||||
|
* - It is suitable when only one flag checking is needed .
|
||||||
|
*
|
||||||
|
* - Limitations:
|
||||||
|
* - Call this function to access the status register. Some flag bits may be cleared.
|
||||||
|
* - Function may need to be called twice or more in order to monitor one single event.
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*********************************************************
|
||||||
|
*
|
||||||
|
* a) Basic state monitoring(First way)
|
||||||
|
********************************************************
|
||||||
|
*/
|
||||||
|
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
|
||||||
|
/*********************************************************
|
||||||
|
*
|
||||||
|
* b) Advanced state monitoring(Second way:)
|
||||||
|
********************************************************
|
||||||
|
*/
|
||||||
|
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
|
||||||
|
/*********************************************************
|
||||||
|
*
|
||||||
|
* c) Flag-based state monitoring(Third way)
|
||||||
|
*********************************************************
|
||||||
|
*/
|
||||||
|
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
||||||
|
|
||||||
|
void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
||||||
|
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
|
||||||
|
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
58
Peripheral/inc/ch32v30x_iwdg.h
Normal file
58
Peripheral/inc/ch32v30x_iwdg.h
Normal file
@@ -0,0 +1,58 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_iwdg.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* IWDG firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_IWDG_H
|
||||||
|
#define __CH32V30x_IWDG_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* IWDG_WriteAccess */
|
||||||
|
#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
|
||||||
|
#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* IWDG_prescaler */
|
||||||
|
#define IWDG_Prescaler_4 ((uint8_t)0x00)
|
||||||
|
#define IWDG_Prescaler_8 ((uint8_t)0x01)
|
||||||
|
#define IWDG_Prescaler_16 ((uint8_t)0x02)
|
||||||
|
#define IWDG_Prescaler_32 ((uint8_t)0x03)
|
||||||
|
#define IWDG_Prescaler_64 ((uint8_t)0x04)
|
||||||
|
#define IWDG_Prescaler_128 ((uint8_t)0x05)
|
||||||
|
#define IWDG_Prescaler_256 ((uint8_t)0x06)
|
||||||
|
|
||||||
|
/* IWDG_Flag */
|
||||||
|
#define IWDG_FLAG_PVU ((uint16_t)0x0001)
|
||||||
|
#define IWDG_FLAG_RVU ((uint16_t)0x0002)
|
||||||
|
|
||||||
|
|
||||||
|
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
|
||||||
|
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
|
||||||
|
void IWDG_SetReload(uint16_t Reload);
|
||||||
|
void IWDG_ReloadCounter(void);
|
||||||
|
void IWDG_Enable(void);
|
||||||
|
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
93
Peripheral/inc/ch32v30x_misc.h
Normal file
93
Peripheral/inc/ch32v30x_misc.h
Normal file
@@ -0,0 +1,93 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_misc.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2024/03/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* miscellaneous firmware library functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30X_MISC_H
|
||||||
|
#define __CH32V30X_MISC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* CSR_INTSYSCR_INEST_definition */
|
||||||
|
#define INTSYSCR_INEST_NoEN 0x00 /* interrupt nesting disable(CSR-0x804 bit1 = 0) */
|
||||||
|
#define INTSYSCR_INEST_EN_2Level 0x01 /* interrupt nesting enable-2 Level(CSR-0x804 bit1 = 1 bit[3:2] = 1) */
|
||||||
|
#define INTSYSCR_INEST_EN_4Level 0x02 /* interrupt nesting enable-4 Level(CSR-0x804 bit1 = 1 bit[3:2] = 2) */
|
||||||
|
#define INTSYSCR_INEST_EN_8Level 0x03 /* interrupt nesting enable-8 Level(CSR-0x804 bit1 = 1 bit[3:2] = 3) */
|
||||||
|
|
||||||
|
/* Check the configuration of CSR(0x804) in the startup file(.S)
|
||||||
|
* interrupt nesting enable-8 Level(CSR-0x804 bit1 = 1 bit[3:2] = 3)
|
||||||
|
* priority - bit[7:5] - Preemption Priority
|
||||||
|
* bit[4:0] - Reserve
|
||||||
|
* interrupt nesting enable-4 Level(CSR-0x804 bit1 = 1 bit[3:2] = 2)
|
||||||
|
* priority - bit[7:6] - Preemption Priority
|
||||||
|
* bit[5] - Sub priority
|
||||||
|
* bit[4:0] - Reserve
|
||||||
|
* interrupt nesting enable-2 Level(CSR-0x804 bit1 = 1 bit[3:2] = 1)
|
||||||
|
* priority - bit[7] - Preemption Priority
|
||||||
|
* bit[6:5] - Sub priority
|
||||||
|
* bit[4:0] - Reserve
|
||||||
|
* interrupt nesting disable(CSR-0x804 bit1 = 0)
|
||||||
|
* priority - bit[7:5] - Sub priority
|
||||||
|
* bit[4:0] - Reserve
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef INTSYSCR_INEST
|
||||||
|
#define INTSYSCR_INEST INTSYSCR_INEST_EN_4Level
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* NVIC Init Structure definition
|
||||||
|
* interrupt nesting disable(CSR-0x804 bit1 = 0)
|
||||||
|
* NVIC_IRQChannelPreemptionPriority - range is 0.
|
||||||
|
* NVIC_IRQChannelSubPriority - range from 0 to 7.
|
||||||
|
*
|
||||||
|
* interrupt nesting enable-2 Level(CSR-0x804 bit1 = 1 bit[3:2] = 1)
|
||||||
|
* NVIC_IRQChannelPreemptionPriority - range from 0 to 1.
|
||||||
|
* NVIC_IRQChannelSubPriority - range from 0 to 3.
|
||||||
|
*
|
||||||
|
* interrupt nesting enable-4 Level(CSR-0x804 bit1 = 1 bit[3:2] = 2)
|
||||||
|
* NVIC_IRQChannelPreemptionPriority - range from 0 to 3.
|
||||||
|
* NVIC_IRQChannelSubPriority - range from 0 to 1.
|
||||||
|
*
|
||||||
|
* interrupt nesting enable-8 Level(CSR-0x804 bit1 = 1 bit[3:2] = 3)
|
||||||
|
* NVIC_IRQChannelPreemptionPriority - range from 0 to 7.
|
||||||
|
* NVIC_IRQChannelSubPriority - range range is 0.
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint8_t NVIC_IRQChannel;
|
||||||
|
uint8_t NVIC_IRQChannelPreemptionPriority;
|
||||||
|
uint8_t NVIC_IRQChannelSubPriority;
|
||||||
|
FunctionalState NVIC_IRQChannelCmd;
|
||||||
|
} NVIC_InitTypeDef;
|
||||||
|
|
||||||
|
/* Preemption_Priority_Group */
|
||||||
|
#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN)
|
||||||
|
#define NVIC_PriorityGroup_0 ((uint32_t)0x00) /* interrupt nesting disable(CSR-0x804 bit1 = 0) */
|
||||||
|
#elif (INTSYSCR_INEST == INTSYSCR_INEST_EN_2Level)
|
||||||
|
#define NVIC_PriorityGroup_1 ((uint32_t)0x01) /* interrupt nesting enable-2 Level(CSR-0x804 bit1 = 1 bit[3:2] = 1) */
|
||||||
|
#elif (INTSYSCR_INEST == INTSYSCR_INEST_EN_8Level)
|
||||||
|
#define NVIC_PriorityGroup_3 ((uint32_t)0x03) /* interrupt nesting enable-8 Level(CSR-0x804 bit1 = 1 bit[3:2] = 3) */
|
||||||
|
#else
|
||||||
|
#define NVIC_PriorityGroup_2 ((uint32_t)0x02) /* interrupt nesting enable-4 Level(CSR-0x804 bit1 = 1 bit[3:2] = 2) */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
|
||||||
|
void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
77
Peripheral/inc/ch32v30x_opa.h
Normal file
77
Peripheral/inc/ch32v30x_opa.h
Normal file
@@ -0,0 +1,77 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_opa.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* OPA firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_OPA_H
|
||||||
|
#define __CH32V30x_OPA_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
#define OPA_PSEL_OFFSET 3
|
||||||
|
#define OPA_NSEL_OFFSET 2
|
||||||
|
#define OPA_MODE_OFFSET 1
|
||||||
|
|
||||||
|
|
||||||
|
/* OPA member enumeration */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
OPA1=0,
|
||||||
|
OPA2,
|
||||||
|
OPA3,
|
||||||
|
OPA4
|
||||||
|
}OPA_Num_TypeDef;
|
||||||
|
|
||||||
|
/* OPA PSEL enumeration */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
CHP0=0,
|
||||||
|
CHP1
|
||||||
|
}OPA_PSEL_TypeDef;
|
||||||
|
|
||||||
|
/* OPA NSEL enumeration */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
CHN0=0,
|
||||||
|
CHN1
|
||||||
|
}OPA_NSEL_TypeDef;
|
||||||
|
|
||||||
|
/* OPA out channel enumeration */
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
OUT_IO_OUT0=0,
|
||||||
|
OUT_IO_OUT1
|
||||||
|
}OPA_Mode_TypeDef;
|
||||||
|
|
||||||
|
/* OPA Init Structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
OPA_Num_TypeDef OPA_NUM; /* Specifies the members of OPA */
|
||||||
|
OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */
|
||||||
|
OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */
|
||||||
|
OPA_Mode_TypeDef Mode; /* Specifies the mode of OPA */
|
||||||
|
}OPA_InitTypeDef;
|
||||||
|
|
||||||
|
|
||||||
|
void OPA_DeInit(void);
|
||||||
|
void OPA_Init(OPA_InitTypeDef* OPA_InitStruct);
|
||||||
|
void OPA_StructInit(OPA_InitTypeDef* OPA_InitStruct);
|
||||||
|
void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
77
Peripheral/inc/ch32v30x_pwr.h
Normal file
77
Peripheral/inc/ch32v30x_pwr.h
Normal file
@@ -0,0 +1,77 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_pwr.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the PWR
|
||||||
|
* firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_PWR_H
|
||||||
|
#define __CH32V30x_PWR_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* PVD_detection_level */
|
||||||
|
#define PWR_PVDLevel_MODE0 ((uint32_t)0x00000000)
|
||||||
|
#define PWR_PVDLevel_MODE1 ((uint32_t)0x00000020)
|
||||||
|
#define PWR_PVDLevel_MODE2 ((uint32_t)0x00000040)
|
||||||
|
#define PWR_PVDLevel_MODE3 ((uint32_t)0x00000060)
|
||||||
|
#define PWR_PVDLevel_MODE4 ((uint32_t)0x00000080)
|
||||||
|
#define PWR_PVDLevel_MODE5 ((uint32_t)0x000000A0)
|
||||||
|
#define PWR_PVDLevel_MODE6 ((uint32_t)0x000000C0)
|
||||||
|
#define PWR_PVDLevel_MODE7 ((uint32_t)0x000000E0)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
#define PWR_PVDLevel_2V2 PWR_PVDLevel_MODE0
|
||||||
|
#define PWR_PVDLevel_2V3 PWR_PVDLevel_MODE1
|
||||||
|
#define PWR_PVDLevel_2V4 PWR_PVDLevel_MODE2
|
||||||
|
#define PWR_PVDLevel_2V5 PWR_PVDLevel_MODE3
|
||||||
|
#define PWR_PVDLevel_2V6 PWR_PVDLevel_MODE4
|
||||||
|
#define PWR_PVDLevel_2V7 PWR_PVDLevel_MODE5
|
||||||
|
#define PWR_PVDLevel_2V8 PWR_PVDLevel_MODE6
|
||||||
|
#define PWR_PVDLevel_2V9 PWR_PVDLevel_MODE7
|
||||||
|
|
||||||
|
/* Regulator_state_is_STOP_mode */
|
||||||
|
#define PWR_Regulator_ON ((uint32_t)0x00000000)
|
||||||
|
#define PWR_Regulator_LowPower ((uint32_t)0x00000001)
|
||||||
|
|
||||||
|
/* STOP_mode_entry */
|
||||||
|
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
|
||||||
|
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
|
||||||
|
|
||||||
|
/* PWR_Flag */
|
||||||
|
#define PWR_FLAG_WU ((uint32_t)0x00000001)
|
||||||
|
#define PWR_FLAG_SB ((uint32_t)0x00000002)
|
||||||
|
#define PWR_FLAG_PVDO ((uint32_t)0x00000004)
|
||||||
|
|
||||||
|
|
||||||
|
void PWR_DeInit(void);
|
||||||
|
void PWR_BackupAccessCmd(FunctionalState NewState);
|
||||||
|
void PWR_PVDCmd(FunctionalState NewState);
|
||||||
|
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
|
||||||
|
void PWR_WakeUpPinCmd(FunctionalState NewState);
|
||||||
|
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
|
||||||
|
void PWR_EnterSTANDBYMode(void);
|
||||||
|
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
|
||||||
|
void PWR_ClearFlag(uint32_t PWR_FLAG);
|
||||||
|
void PWR_EnterSTANDBYMode_RAM(void);
|
||||||
|
void PWR_EnterSTANDBYMode_RAM_LV(void);
|
||||||
|
void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void);
|
||||||
|
void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void);
|
||||||
|
void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
464
Peripheral/inc/ch32v30x_rcc.h
Normal file
464
Peripheral/inc/ch32v30x_rcc.h
Normal file
@@ -0,0 +1,464 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_rcc.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2024/03/06
|
||||||
|
* Description : This file provides all the RCC firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_RCC_H
|
||||||
|
#define __CH32V30x_RCC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* RCC_Exported_Types */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */
|
||||||
|
uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */
|
||||||
|
uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */
|
||||||
|
uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */
|
||||||
|
uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */
|
||||||
|
}RCC_ClocksTypeDef;
|
||||||
|
|
||||||
|
/* HSE_configuration */
|
||||||
|
#define RCC_HSE_OFF ((uint32_t)0x00000000)
|
||||||
|
#define RCC_HSE_ON ((uint32_t)0x00010000)
|
||||||
|
#define RCC_HSE_Bypass ((uint32_t)0x00040000)
|
||||||
|
|
||||||
|
/* PLL_entry_clock_source */
|
||||||
|
#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)
|
||||||
|
|
||||||
|
#ifdef CH32V30x_D8
|
||||||
|
#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)
|
||||||
|
#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)
|
||||||
|
|
||||||
|
#else
|
||||||
|
#define RCC_PLLSource_PREDIV1 ((uint32_t)0x00010000)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* PLL_multiplication_factor */
|
||||||
|
#ifdef CH32V30x_D8
|
||||||
|
#define RCC_PLLMul_2 ((uint32_t)0x00000000)
|
||||||
|
#define RCC_PLLMul_3 ((uint32_t)0x00040000)
|
||||||
|
#define RCC_PLLMul_4 ((uint32_t)0x00080000)
|
||||||
|
#define RCC_PLLMul_5 ((uint32_t)0x000C0000)
|
||||||
|
#define RCC_PLLMul_6 ((uint32_t)0x00100000)
|
||||||
|
#define RCC_PLLMul_7 ((uint32_t)0x00140000)
|
||||||
|
#define RCC_PLLMul_8 ((uint32_t)0x00180000)
|
||||||
|
#define RCC_PLLMul_9 ((uint32_t)0x001C0000)
|
||||||
|
#define RCC_PLLMul_10 ((uint32_t)0x00200000)
|
||||||
|
#define RCC_PLLMul_11 ((uint32_t)0x00240000)
|
||||||
|
#define RCC_PLLMul_12 ((uint32_t)0x00280000)
|
||||||
|
#define RCC_PLLMul_13 ((uint32_t)0x002C0000)
|
||||||
|
#define RCC_PLLMul_14 ((uint32_t)0x00300000)
|
||||||
|
#define RCC_PLLMul_15 ((uint32_t)0x00340000)
|
||||||
|
#define RCC_PLLMul_16 ((uint32_t)0x00380000)
|
||||||
|
#define RCC_PLLMul_18 ((uint32_t)0x003C0000)
|
||||||
|
|
||||||
|
#else
|
||||||
|
#define RCC_PLLMul_18_EXTEN ((uint32_t)0x00000000)
|
||||||
|
#define RCC_PLLMul_3_EXTEN ((uint32_t)0x00040000)
|
||||||
|
#define RCC_PLLMul_4_EXTEN ((uint32_t)0x00080000)
|
||||||
|
#define RCC_PLLMul_5_EXTEN ((uint32_t)0x000C0000)
|
||||||
|
#define RCC_PLLMul_6_EXTEN ((uint32_t)0x00100000)
|
||||||
|
#define RCC_PLLMul_7_EXTEN ((uint32_t)0x00140000)
|
||||||
|
#define RCC_PLLMul_8_EXTEN ((uint32_t)0x00180000)
|
||||||
|
#define RCC_PLLMul_9_EXTEN ((uint32_t)0x001C0000)
|
||||||
|
#define RCC_PLLMul_10_EXTEN ((uint32_t)0x00200000)
|
||||||
|
#define RCC_PLLMul_11_EXTEN ((uint32_t)0x00240000)
|
||||||
|
#define RCC_PLLMul_12_EXTEN ((uint32_t)0x00280000)
|
||||||
|
#define RCC_PLLMul_13_EXTEN ((uint32_t)0x002C0000)
|
||||||
|
#define RCC_PLLMul_14_EXTEN ((uint32_t)0x00300000)
|
||||||
|
#define RCC_PLLMul_6_5_EXTEN ((uint32_t)0x00340000)
|
||||||
|
#define RCC_PLLMul_15_EXTEN ((uint32_t)0x00380000)
|
||||||
|
#define RCC_PLLMul_16_EXTEN ((uint32_t)0x003C0000)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* PREDIV1_division_factor */
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_PREDIV1_Div1 ((uint32_t)0x00000000)
|
||||||
|
#define RCC_PREDIV1_Div2 ((uint32_t)0x00000001)
|
||||||
|
#define RCC_PREDIV1_Div3 ((uint32_t)0x00000002)
|
||||||
|
#define RCC_PREDIV1_Div4 ((uint32_t)0x00000003)
|
||||||
|
#define RCC_PREDIV1_Div5 ((uint32_t)0x00000004)
|
||||||
|
#define RCC_PREDIV1_Div6 ((uint32_t)0x00000005)
|
||||||
|
#define RCC_PREDIV1_Div7 ((uint32_t)0x00000006)
|
||||||
|
#define RCC_PREDIV1_Div8 ((uint32_t)0x00000007)
|
||||||
|
#define RCC_PREDIV1_Div9 ((uint32_t)0x00000008)
|
||||||
|
#define RCC_PREDIV1_Div10 ((uint32_t)0x00000009)
|
||||||
|
#define RCC_PREDIV1_Div11 ((uint32_t)0x0000000A)
|
||||||
|
#define RCC_PREDIV1_Div12 ((uint32_t)0x0000000B)
|
||||||
|
#define RCC_PREDIV1_Div13 ((uint32_t)0x0000000C)
|
||||||
|
#define RCC_PREDIV1_Div14 ((uint32_t)0x0000000D)
|
||||||
|
#define RCC_PREDIV1_Div15 ((uint32_t)0x0000000E)
|
||||||
|
#define RCC_PREDIV1_Div16 ((uint32_t)0x0000000F)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* PREDIV1_clock_source */
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
|
||||||
|
#define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* PREDIV2_division_factor */
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_PREDIV2_Div1 ((uint32_t)0x00000000)
|
||||||
|
#define RCC_PREDIV2_Div2 ((uint32_t)0x00000010)
|
||||||
|
#define RCC_PREDIV2_Div3 ((uint32_t)0x00000020)
|
||||||
|
#define RCC_PREDIV2_Div4 ((uint32_t)0x00000030)
|
||||||
|
#define RCC_PREDIV2_Div5 ((uint32_t)0x00000040)
|
||||||
|
#define RCC_PREDIV2_Div6 ((uint32_t)0x00000050)
|
||||||
|
#define RCC_PREDIV2_Div7 ((uint32_t)0x00000060)
|
||||||
|
#define RCC_PREDIV2_Div8 ((uint32_t)0x00000070)
|
||||||
|
#define RCC_PREDIV2_Div9 ((uint32_t)0x00000080)
|
||||||
|
#define RCC_PREDIV2_Div10 ((uint32_t)0x00000090)
|
||||||
|
#define RCC_PREDIV2_Div11 ((uint32_t)0x000000A0)
|
||||||
|
#define RCC_PREDIV2_Div12 ((uint32_t)0x000000B0)
|
||||||
|
#define RCC_PREDIV2_Div13 ((uint32_t)0x000000C0)
|
||||||
|
#define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0)
|
||||||
|
#define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0)
|
||||||
|
#define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* PLL2_multiplication_factor */
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_PLL2Mul_2_5 ((uint32_t)0x00000000)
|
||||||
|
#define RCC_PLL2Mul_12_5 ((uint32_t)0x00000100)
|
||||||
|
#define RCC_PLL2Mul_4 ((uint32_t)0x00000200)
|
||||||
|
#define RCC_PLL2Mul_5 ((uint32_t)0x00000300)
|
||||||
|
#define RCC_PLL2Mul_6 ((uint32_t)0x00000400)
|
||||||
|
#define RCC_PLL2Mul_7 ((uint32_t)0x00000500)
|
||||||
|
#define RCC_PLL2Mul_8 ((uint32_t)0x00000600)
|
||||||
|
#define RCC_PLL2Mul_9 ((uint32_t)0x00000700)
|
||||||
|
#define RCC_PLL2Mul_10 ((uint32_t)0x00000800)
|
||||||
|
#define RCC_PLL2Mul_11 ((uint32_t)0x00000900)
|
||||||
|
#define RCC_PLL2Mul_12 ((uint32_t)0x00000A00)
|
||||||
|
#define RCC_PLL2Mul_13 ((uint32_t)0x00000B00)
|
||||||
|
#define RCC_PLL2Mul_14 ((uint32_t)0x00000C00)
|
||||||
|
#define RCC_PLL2Mul_15 ((uint32_t)0x00000D00)
|
||||||
|
#define RCC_PLL2Mul_16 ((uint32_t)0x00000E00)
|
||||||
|
#define RCC_PLL2Mul_20 ((uint32_t)0x00000F00)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* PLL3_multiplication_factor */
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_PLL3Mul_2_5 ((uint32_t)0x00000000)
|
||||||
|
#define RCC_PLL3Mul_12_5 ((uint32_t)0x00001000)
|
||||||
|
#define RCC_PLL3Mul_4 ((uint32_t)0x00002000)
|
||||||
|
#define RCC_PLL3Mul_5 ((uint32_t)0x00003000)
|
||||||
|
#define RCC_PLL3Mul_6 ((uint32_t)0x00004000)
|
||||||
|
#define RCC_PLL3Mul_7 ((uint32_t)0x00005000)
|
||||||
|
#define RCC_PLL3Mul_8 ((uint32_t)0x00006000)
|
||||||
|
#define RCC_PLL3Mul_9 ((uint32_t)0x00007000)
|
||||||
|
#define RCC_PLL3Mul_10 ((uint32_t)0x00008000)
|
||||||
|
#define RCC_PLL3Mul_11 ((uint32_t)0x00009000)
|
||||||
|
#define RCC_PLL3Mul_12 ((uint32_t)0x0000A000)
|
||||||
|
#define RCC_PLL3Mul_13 ((uint32_t)0x0000B000)
|
||||||
|
#define RCC_PLL3Mul_14 ((uint32_t)0x0000C000)
|
||||||
|
#define RCC_PLL3Mul_15 ((uint32_t)0x0000D000)
|
||||||
|
#define RCC_PLL3Mul_16 ((uint32_t)0x0000E000)
|
||||||
|
#define RCC_PLL3Mul_20 ((uint32_t)0x0000F000)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* System_clock_source */
|
||||||
|
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
|
||||||
|
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
|
||||||
|
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
|
||||||
|
|
||||||
|
/* AHB_clock_source */
|
||||||
|
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
|
||||||
|
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
|
||||||
|
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
|
||||||
|
#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
|
||||||
|
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
|
||||||
|
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
|
||||||
|
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
|
||||||
|
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
|
||||||
|
#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
|
||||||
|
|
||||||
|
/* APB1_APB2_clock_source */
|
||||||
|
#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
|
||||||
|
#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
|
||||||
|
#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
|
||||||
|
#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
|
||||||
|
#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
|
||||||
|
|
||||||
|
/* RCC_Interrupt_source */
|
||||||
|
#define RCC_IT_LSIRDY ((uint8_t)0x01)
|
||||||
|
#define RCC_IT_LSERDY ((uint8_t)0x02)
|
||||||
|
#define RCC_IT_HSIRDY ((uint8_t)0x04)
|
||||||
|
#define RCC_IT_HSERDY ((uint8_t)0x08)
|
||||||
|
#define RCC_IT_PLLRDY ((uint8_t)0x10)
|
||||||
|
#define RCC_IT_CSS ((uint8_t)0x80)
|
||||||
|
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_IT_PLL2RDY ((uint8_t)0x20)
|
||||||
|
#define RCC_IT_PLL3RDY ((uint8_t)0x40)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* USBFS_clock_source */
|
||||||
|
#define RCC_USBFSCLKSource_PLLCLK_Div1 ((uint8_t)0x00)
|
||||||
|
#define RCC_USBFSCLKSource_PLLCLK_Div2 ((uint8_t)0x01)
|
||||||
|
#define RCC_USBFSCLKSource_PLLCLK_Div3 ((uint8_t)0x02)
|
||||||
|
|
||||||
|
#define RCC_OTGFSCLKSource_PLLCLK_Div1 RCC_USBFSCLKSource_PLLCLK_Div1
|
||||||
|
#define RCC_OTGFSCLKSource_PLLCLK_Div2 RCC_USBFSCLKSource_PLLCLK_Div2
|
||||||
|
#define RCC_OTGFSCLKSource_PLLCLK_Div3 RCC_USBFSCLKSource_PLLCLK_Div3
|
||||||
|
|
||||||
|
/* I2S2_clock_source */
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_I2S2CLKSource_SYSCLK ((uint8_t)0x00)
|
||||||
|
#define RCC_I2S2CLKSource_PLL3_VCO ((uint8_t)0x01)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* I2S3_clock_source */
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_I2S3CLKSource_SYSCLK ((uint8_t)0x00)
|
||||||
|
#define RCC_I2S3CLKSource_PLL3_VCO ((uint8_t)0x01)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ADC_clock_source */
|
||||||
|
#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
|
||||||
|
#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
|
||||||
|
#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
|
||||||
|
#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
|
||||||
|
|
||||||
|
/* LSE_configuration */
|
||||||
|
#define RCC_LSE_OFF ((uint8_t)0x00)
|
||||||
|
#define RCC_LSE_ON ((uint8_t)0x01)
|
||||||
|
#define RCC_LSE_Bypass ((uint8_t)0x04)
|
||||||
|
|
||||||
|
/* RTC_clock_source */
|
||||||
|
#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
|
||||||
|
#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
|
||||||
|
#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
|
||||||
|
|
||||||
|
/* AHB_peripheral */
|
||||||
|
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
|
||||||
|
#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
|
||||||
|
#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
|
||||||
|
#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
|
||||||
|
#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
|
||||||
|
#define RCC_AHBPeriph_RNG ((uint32_t)0x00000200)
|
||||||
|
#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
|
||||||
|
#define RCC_AHBPeriph_USBHS ((uint32_t)0x00000800)
|
||||||
|
#define RCC_AHBPeriph_USBFS ((uint32_t)0x00001000)
|
||||||
|
#define RCC_AHBPeriph_DVP ((uint32_t)0x00002000)
|
||||||
|
#define RCC_AHBPeriph_ETH_MAC ((uint32_t)0x00004000)
|
||||||
|
#define RCC_AHBPeriph_ETH_MAC_Tx ((uint32_t)0x00008000)
|
||||||
|
#define RCC_AHBPeriph_ETH_MAC_Rx ((uint32_t)0x00010000)
|
||||||
|
#define RCC_AHBPeriph_OTG_FS RCC_AHBPeriph_USBFS
|
||||||
|
|
||||||
|
/* APB2_peripheral */
|
||||||
|
#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
|
||||||
|
#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
|
||||||
|
#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
|
||||||
|
#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
|
||||||
|
#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
|
||||||
|
#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
|
||||||
|
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
|
||||||
|
#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
|
||||||
|
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
|
||||||
|
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
|
||||||
|
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
|
||||||
|
#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
|
||||||
|
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)
|
||||||
|
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)
|
||||||
|
|
||||||
|
/* APB1_peripheral */
|
||||||
|
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
|
||||||
|
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
|
||||||
|
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
|
||||||
|
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
|
||||||
|
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
|
||||||
|
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
|
||||||
|
#define RCC_APB1Periph_UART6 ((uint32_t)0x00000040)
|
||||||
|
#define RCC_APB1Periph_UART7 ((uint32_t)0x00000080)
|
||||||
|
#define RCC_APB1Periph_UART8 ((uint32_t)0x00000100)
|
||||||
|
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
|
||||||
|
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
|
||||||
|
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
|
||||||
|
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
|
||||||
|
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
|
||||||
|
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
|
||||||
|
#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
|
||||||
|
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
|
||||||
|
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
|
||||||
|
#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
|
||||||
|
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
|
||||||
|
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
|
||||||
|
#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
|
||||||
|
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
|
||||||
|
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
|
||||||
|
|
||||||
|
/* Clock_source_to_output_on_MCO_pin */
|
||||||
|
#define RCC_MCO_NoClock ((uint8_t)0x00)
|
||||||
|
#define RCC_MCO_SYSCLK ((uint8_t)0x04)
|
||||||
|
#define RCC_MCO_HSI ((uint8_t)0x05)
|
||||||
|
#define RCC_MCO_HSE ((uint8_t)0x06)
|
||||||
|
#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)
|
||||||
|
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_MCO_PLL2CLK ((uint8_t)0x08)
|
||||||
|
#define RCC_MCO_PLL3CLK_Div2 ((uint8_t)0x09)
|
||||||
|
#define RCC_MCO_XT1 ((uint8_t)0x0A)
|
||||||
|
#define RCC_MCO_PLL3CLK ((uint8_t)0x0B)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* RCC_Flag */
|
||||||
|
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
|
||||||
|
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
|
||||||
|
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
|
||||||
|
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
|
||||||
|
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
|
||||||
|
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
|
||||||
|
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
|
||||||
|
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
|
||||||
|
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
|
||||||
|
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
|
||||||
|
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
|
||||||
|
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_FLAG_PLL2RDY ((uint8_t)0x3B)
|
||||||
|
#define RCC_FLAG_PLL3RDY ((uint8_t)0x3D)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* SysTick_clock_source */
|
||||||
|
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
|
||||||
|
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
|
||||||
|
|
||||||
|
/* RNG_clock_source */
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_RNGCLKSource_SYSCLK ((uint32_t)0x00)
|
||||||
|
#define RCC_RNGCLKSource_PLL3_VCO ((uint32_t)0x01)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* ETH1G_clock_source */
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_ETH1GCLKSource_PLL2_VCO ((uint32_t)0x00)
|
||||||
|
#define RCC_ETH1GCLKSource_PLL3_VCO ((uint32_t)0x01)
|
||||||
|
#define RCC_ETH1GCLKSource_PB1_IN ((uint32_t)0x02)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* USBFS_clock_source */
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_USBPLL_Div1 ((uint32_t)0x00)
|
||||||
|
#define RCC_USBPLL_Div2 ((uint32_t)0x01)
|
||||||
|
#define RCC_USBPLL_Div3 ((uint32_t)0x02)
|
||||||
|
#define RCC_USBPLL_Div4 ((uint32_t)0x03)
|
||||||
|
#define RCC_USBPLL_Div5 ((uint32_t)0x04)
|
||||||
|
#define RCC_USBPLL_Div6 ((uint32_t)0x05)
|
||||||
|
#define RCC_USBPLL_Div7 ((uint32_t)0x06)
|
||||||
|
#define RCC_USBPLL_Div8 ((uint32_t)0x07)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* USBHSPLL_clock_source */
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_HSBHSPLLCLKSource_HSE ((uint32_t)0x00)
|
||||||
|
#define RCC_HSBHSPLLCLKSource_HSI ((uint32_t)0x01)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* USBHSPLLCKREF_clock_select */
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
#define RCC_USBHSPLLCKREFCLK_3M ((uint32_t)0x00)
|
||||||
|
#define RCC_USBHSPLLCKREFCLK_4M ((uint32_t)0x01)
|
||||||
|
#define RCC_USBHSPLLCKREFCLK_8M ((uint32_t)0x02)
|
||||||
|
#define RCC_USBHSPLLCKREFCLK_5M ((uint32_t)0x03)
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* OTGUSBCLK48M_clock_source */
|
||||||
|
#define RCC_USBCLK48MCLKSource_PLLCLK ((uint32_t)0x00)
|
||||||
|
#define RCC_USBCLK48MCLKSource_USBPHY ((uint32_t)0x01)
|
||||||
|
|
||||||
|
|
||||||
|
void RCC_DeInit(void);
|
||||||
|
void RCC_HSEConfig(uint32_t RCC_HSE);
|
||||||
|
ErrorStatus RCC_WaitForHSEStartUp(void);
|
||||||
|
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
|
||||||
|
void RCC_HSICmd(FunctionalState NewState);
|
||||||
|
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
|
||||||
|
void RCC_PLLCmd(FunctionalState NewState);
|
||||||
|
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
|
||||||
|
uint8_t RCC_GetSYSCLKSource(void);
|
||||||
|
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
|
||||||
|
void RCC_PCLK1Config(uint32_t RCC_HCLK);
|
||||||
|
void RCC_PCLK2Config(uint32_t RCC_HCLK);
|
||||||
|
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
|
||||||
|
void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
|
||||||
|
void RCC_LSEConfig(uint8_t RCC_LSE);
|
||||||
|
void RCC_LSICmd(FunctionalState NewState);
|
||||||
|
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
|
||||||
|
void RCC_RTCCLKCmd(FunctionalState NewState);
|
||||||
|
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
|
||||||
|
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
|
||||||
|
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||||
|
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||||
|
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||||
|
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||||
|
void RCC_BackupResetCmd(FunctionalState NewState);
|
||||||
|
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
|
||||||
|
void RCC_MCOConfig(uint8_t RCC_MCO);
|
||||||
|
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
|
||||||
|
void RCC_ClearFlag(void);
|
||||||
|
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
|
||||||
|
void RCC_ClearITPendingBit(uint8_t RCC_IT);
|
||||||
|
void RCC_ADCCLKADJcmd(FunctionalState NewState);
|
||||||
|
void RCC_USBFSCLKConfig(uint32_t RCC_USBFSCLKSource);
|
||||||
|
void RCC_USBCLK48MConfig(uint32_t RCC_USBCLK48MSource);
|
||||||
|
#define RCC_OTGFSCLKConfig RCC_USBFSCLKConfig
|
||||||
|
|
||||||
|
#ifdef CH32V30x_D8C
|
||||||
|
void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Source, uint32_t RCC_PREDIV1_Div);
|
||||||
|
void RCC_PREDIV2Config(uint32_t RCC_PREDIV2_Div);
|
||||||
|
void RCC_PLL2Config(uint32_t RCC_PLL2Mul);
|
||||||
|
void RCC_PLL2Cmd(FunctionalState NewState);
|
||||||
|
void RCC_PLL3Config(uint32_t RCC_PLL3Mul);
|
||||||
|
void RCC_PLL3Cmd(FunctionalState NewState);
|
||||||
|
void RCC_I2S2CLKConfig(uint32_t RCC_I2S2CLKSource);
|
||||||
|
void RCC_I2S3CLKConfig(uint32_t RCC_I2S3CLKSource);
|
||||||
|
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
|
||||||
|
void RCC_RNGCLKConfig(uint32_t RCC_RNGCLKSource);
|
||||||
|
void RCC_ETH1GCLKConfig(uint32_t RCC_ETH1GCLKSource);
|
||||||
|
void RCC_ETH1G_125Mcmd(FunctionalState NewState);
|
||||||
|
void RCC_USBHSConfig(uint32_t RCC_USBHS);
|
||||||
|
void RCC_USBHSPLLCLKConfig(uint32_t RCC_USBHSPLLCLKSource);
|
||||||
|
void RCC_USBHSPLLCKREFCLKConfig(uint32_t RCC_USBHSPLLCKREFCLKSource);
|
||||||
|
void RCC_USBHSPHYPLLALIVEcmd(FunctionalState NewState);
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
43
Peripheral/inc/ch32v30x_rng.h
Normal file
43
Peripheral/inc/ch32v30x_rng.h
Normal file
@@ -0,0 +1,43 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_rng.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* RNG firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_RNG_H
|
||||||
|
#define __CH32V30x_RNG_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* RNG_flags_definition*/
|
||||||
|
#define RNG_FLAG_DRDY ((uint8_t)0x0001) /* Data ready */
|
||||||
|
#define RNG_FLAG_CECS ((uint8_t)0x0002) /* Clock error current status */
|
||||||
|
#define RNG_FLAG_SECS ((uint8_t)0x0004) /* Seed error current status */
|
||||||
|
|
||||||
|
/* RNG_interrupts_definition */
|
||||||
|
#define RNG_IT_CEI ((uint8_t)0x20) /* Clock error interrupt */
|
||||||
|
#define RNG_IT_SEI ((uint8_t)0x40) /* Seed error interrupt */
|
||||||
|
|
||||||
|
|
||||||
|
void RNG_Cmd(FunctionalState NewState);
|
||||||
|
uint32_t RNG_GetRandomNumber(void);
|
||||||
|
void RNG_ITConfig(FunctionalState NewState);
|
||||||
|
FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG);
|
||||||
|
void RNG_ClearFlag(uint8_t RNG_FLAG);
|
||||||
|
ITStatus RNG_GetITStatus(uint8_t RNG_IT);
|
||||||
|
void RNG_ClearITPendingBit(uint8_t RNG_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
56
Peripheral/inc/ch32v30x_rtc.h
Normal file
56
Peripheral/inc/ch32v30x_rtc.h
Normal file
@@ -0,0 +1,56 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_rtc.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the RTC
|
||||||
|
* firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_RTC_H
|
||||||
|
#define __CH32V30x_RTC_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
|
||||||
|
/* RTC_interrupts_define */
|
||||||
|
#define RTC_IT_OW ((uint16_t)0x0004) /* Overflow interrupt */
|
||||||
|
#define RTC_IT_ALR ((uint16_t)0x0002) /* Alarm interrupt */
|
||||||
|
#define RTC_IT_SEC ((uint16_t)0x0001) /* Second interrupt */
|
||||||
|
|
||||||
|
/* RTC_interrupts_flags */
|
||||||
|
#define RTC_FLAG_RTOFF ((uint16_t)0x0020) /* RTC Operation OFF flag */
|
||||||
|
#define RTC_FLAG_RSF ((uint16_t)0x0008) /* Registers Synchronized flag */
|
||||||
|
#define RTC_FLAG_OW ((uint16_t)0x0004) /* Overflow flag */
|
||||||
|
#define RTC_FLAG_ALR ((uint16_t)0x0002) /* Alarm flag */
|
||||||
|
#define RTC_FLAG_SEC ((uint16_t)0x0001) /* Second flag */
|
||||||
|
|
||||||
|
|
||||||
|
void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState);
|
||||||
|
void RTC_EnterConfigMode(void);
|
||||||
|
void RTC_ExitConfigMode(void);
|
||||||
|
uint32_t RTC_GetCounter(void);
|
||||||
|
void RTC_SetCounter(uint32_t CounterValue);
|
||||||
|
void RTC_SetPrescaler(uint32_t PrescalerValue);
|
||||||
|
void RTC_SetAlarm(uint32_t AlarmValue);
|
||||||
|
uint32_t RTC_GetDivider(void);
|
||||||
|
void RTC_WaitForLastTask(void);
|
||||||
|
void RTC_WaitForSynchro(void);
|
||||||
|
FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG);
|
||||||
|
void RTC_ClearFlag(uint16_t RTC_FLAG);
|
||||||
|
ITStatus RTC_GetITStatus(uint16_t RTC_IT);
|
||||||
|
void RTC_ClearITPendingBit(uint16_t RTC_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
266
Peripheral/inc/ch32v30x_sdio.h
Normal file
266
Peripheral/inc/ch32v30x_sdio.h
Normal file
@@ -0,0 +1,266 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_sdio.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the SDIO
|
||||||
|
* firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_SDIO_H
|
||||||
|
#define __CH32V30x_SDIO_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* SDIO Init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t SDIO_ClockEdge; /* Specifies the clock transition on which the bit capture is made.
|
||||||
|
This parameter can be a value of @ref SDIO_Clock_Edge */
|
||||||
|
|
||||||
|
uint32_t SDIO_ClockBypass; /* Specifies whether the SDIO Clock divider bypass is
|
||||||
|
enabled or disabled.
|
||||||
|
This parameter can be a value of @ref SDIO_Clock_Bypass */
|
||||||
|
|
||||||
|
uint32_t SDIO_ClockPowerSave; /* Specifies whether SDIO Clock output is enabled or
|
||||||
|
disabled when the bus is idle.
|
||||||
|
This parameter can be a value of @ref SDIO_Clock_Power_Save */
|
||||||
|
|
||||||
|
uint32_t SDIO_BusWide; /* Specifies the SDIO bus width.
|
||||||
|
This parameter can be a value of @ref SDIO_Bus_Wide */
|
||||||
|
|
||||||
|
uint32_t SDIO_HardwareFlowControl; /* Specifies whether the SDIO hardware flow control is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
|
||||||
|
|
||||||
|
uint8_t SDIO_ClockDiv; /* Specifies the clock frequency of the SDIO controller.
|
||||||
|
This parameter can be a value between 0x00 and 0xFF. */
|
||||||
|
|
||||||
|
} SDIO_InitTypeDef;
|
||||||
|
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t SDIO_Argument; /* Specifies the SDIO command argument which is sent
|
||||||
|
to a card as part of a command message. If a command
|
||||||
|
contains an argument, it must be loaded into this register
|
||||||
|
before writing the command to the command register */
|
||||||
|
|
||||||
|
uint32_t SDIO_CmdIndex; /* Specifies the SDIO command index. It must be lower than 0x40. */
|
||||||
|
|
||||||
|
uint32_t SDIO_Response; /* Specifies the SDIO response type.
|
||||||
|
This parameter can be a value of @ref SDIO_Response_Type */
|
||||||
|
|
||||||
|
uint32_t SDIO_Wait; /* Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
|
||||||
|
|
||||||
|
uint32_t SDIO_CPSM; /* Specifies whether SDIO Command path state machine (CPSM)
|
||||||
|
is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref SDIO_CPSM_State */
|
||||||
|
} SDIO_CmdInitTypeDef;
|
||||||
|
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t SDIO_DataTimeOut; /* Specifies the data timeout period in card bus clock periods. */
|
||||||
|
|
||||||
|
uint32_t SDIO_DataLength; /* Specifies the number of data bytes to be transferred. */
|
||||||
|
|
||||||
|
uint32_t SDIO_DataBlockSize; /* Specifies the data block size for block transfer.
|
||||||
|
This parameter can be a value of @ref SDIO_Data_Block_Size */
|
||||||
|
|
||||||
|
uint32_t SDIO_TransferDir; /* Specifies the data transfer direction, whether the transfer
|
||||||
|
is a read or write.
|
||||||
|
This parameter can be a value of @ref SDIO_Transfer_Direction */
|
||||||
|
|
||||||
|
uint32_t SDIO_TransferMode; /* Specifies whether data transfer is in stream or block mode.
|
||||||
|
This parameter can be a value of @ref SDIO_Transfer_Type */
|
||||||
|
|
||||||
|
uint32_t SDIO_DPSM; /* Specifies whether SDIO Data path state machine (DPSM)
|
||||||
|
is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref SDIO_DPSM_State */
|
||||||
|
} SDIO_DataInitTypeDef;
|
||||||
|
|
||||||
|
|
||||||
|
/* SDIO_Clock_Edge */
|
||||||
|
#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
|
||||||
|
|
||||||
|
/* SDIO_Clock_Bypass */
|
||||||
|
#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
|
||||||
|
|
||||||
|
/* SDIO_Clock_Power_Save */
|
||||||
|
#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
|
||||||
|
|
||||||
|
/* SDIO_Bus_Wide */
|
||||||
|
#define SDIO_BusWide_1b ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_BusWide_4b ((uint32_t)0x00000800)
|
||||||
|
#define SDIO_BusWide_8b ((uint32_t)0x00001000)
|
||||||
|
|
||||||
|
/* SDIO_Hardware_Flow_Control */
|
||||||
|
#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
|
||||||
|
|
||||||
|
/* SDIO_Power_State */
|
||||||
|
#define SDIO_PowerState_OFF ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_PowerState_ON ((uint32_t)0x00000003)
|
||||||
|
|
||||||
|
/* SDIO_Interrupt_sources */
|
||||||
|
#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
|
||||||
|
#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
|
||||||
|
#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
|
||||||
|
#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
|
||||||
|
#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
|
||||||
|
#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
|
||||||
|
#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
|
||||||
|
#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
|
||||||
|
#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
|
||||||
|
#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
|
||||||
|
#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
|
||||||
|
#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
|
||||||
|
#define SDIO_IT_TXACT ((uint32_t)0x00001000)
|
||||||
|
#define SDIO_IT_RXACT ((uint32_t)0x00002000)
|
||||||
|
#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
|
||||||
|
#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
|
||||||
|
#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
|
||||||
|
#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
|
||||||
|
#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
|
||||||
|
#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
|
||||||
|
#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
|
||||||
|
#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
|
||||||
|
#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
|
||||||
|
#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
|
||||||
|
|
||||||
|
/* SDIO_Response_Type */
|
||||||
|
#define SDIO_Response_No ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_Response_Short ((uint32_t)0x00000040)
|
||||||
|
#define SDIO_Response_Long ((uint32_t)0x000000C0)
|
||||||
|
|
||||||
|
/* SDIO_Wait_Interrupt_State */
|
||||||
|
#define SDIO_Wait_No ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_Wait_IT ((uint32_t)0x00000100)
|
||||||
|
#define SDIO_Wait_Pend ((uint32_t)0x00000200)
|
||||||
|
|
||||||
|
/* SDIO_CPSM_State */
|
||||||
|
#define SDIO_CPSM_Disable ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_CPSM_Enable ((uint32_t)0x00000400)
|
||||||
|
|
||||||
|
/* SDIO_Response_Registers */
|
||||||
|
#define SDIO_RESP1 ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_RESP2 ((uint32_t)0x00000004)
|
||||||
|
#define SDIO_RESP3 ((uint32_t)0x00000008)
|
||||||
|
#define SDIO_RESP4 ((uint32_t)0x0000000C)
|
||||||
|
|
||||||
|
/* SDIO_Data_Block_Size */
|
||||||
|
#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
|
||||||
|
#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
|
||||||
|
#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)
|
||||||
|
#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
|
||||||
|
#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
|
||||||
|
#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
|
||||||
|
#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
|
||||||
|
#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
|
||||||
|
#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
|
||||||
|
#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
|
||||||
|
#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
|
||||||
|
#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
|
||||||
|
#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
|
||||||
|
#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
|
||||||
|
|
||||||
|
/* SDIO_Transfer_Direction */
|
||||||
|
#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)
|
||||||
|
|
||||||
|
/* SDIO_Transfer_Type */
|
||||||
|
#define SDIO_TransferMode_Block ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)
|
||||||
|
|
||||||
|
/* SDIO_DPSM_State */
|
||||||
|
#define SDIO_DPSM_Disable ((uint32_t)0x00000000)
|
||||||
|
#define SDIO_DPSM_Enable ((uint32_t)0x00000001)
|
||||||
|
|
||||||
|
/* SDIO_Flags */
|
||||||
|
#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
|
||||||
|
#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
|
||||||
|
#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
|
||||||
|
#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
|
||||||
|
#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
|
||||||
|
#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
|
||||||
|
#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
|
||||||
|
#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
|
||||||
|
#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
|
||||||
|
#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
|
||||||
|
#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
|
||||||
|
#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
|
||||||
|
#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
|
||||||
|
#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
|
||||||
|
#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
|
||||||
|
#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
|
||||||
|
#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
|
||||||
|
#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
|
||||||
|
#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
|
||||||
|
#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
|
||||||
|
#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
|
||||||
|
#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
|
||||||
|
#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
|
||||||
|
#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
|
||||||
|
|
||||||
|
/* SDIO_Read_Wait_Mode */
|
||||||
|
#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)
|
||||||
|
#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)
|
||||||
|
|
||||||
|
#define SDIO_DataControl_DTEN ((uint32_t)0x00000001)
|
||||||
|
#define SDIO_DataControl_DTDIR ((uint32_t)0x00000002)
|
||||||
|
#define SDIO_DataControl_DTMODE ((uint32_t)0x00000004)
|
||||||
|
#define SDIO_DataControl_DMAEN ((uint32_t)0x00000008)
|
||||||
|
#define SDIO_DataControl_DBLOCKSIZE ((uint32_t)0x000000F0)
|
||||||
|
#define SDIO_DataControl_RWSTART ((uint32_t)0x00000100)
|
||||||
|
#define SDIO_DataControl_RWSTOP ((uint32_t)0x00000200)
|
||||||
|
#define SDIO_DataControl_RWMOD ((uint32_t)0x00000400)
|
||||||
|
#define SDIO_DataControl_SDIOEN ((uint32_t)0x00000800)
|
||||||
|
|
||||||
|
|
||||||
|
void SDIO_DeInit(void);
|
||||||
|
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
|
||||||
|
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
|
||||||
|
void SDIO_ClockCmd(FunctionalState NewState);
|
||||||
|
void SDIO_SetPowerState(uint32_t SDIO_PowerState);
|
||||||
|
uint32_t SDIO_GetPowerState(void);
|
||||||
|
void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
|
||||||
|
void SDIO_DMACmd(FunctionalState NewState);
|
||||||
|
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
|
||||||
|
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
|
||||||
|
uint8_t SDIO_GetCommandResponse(void);
|
||||||
|
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
|
||||||
|
void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
|
||||||
|
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
|
||||||
|
uint32_t SDIO_GetDataCounter(void);
|
||||||
|
uint32_t SDIO_ReadData(void);
|
||||||
|
void SDIO_WriteData(uint32_t Data);
|
||||||
|
uint32_t SDIO_GetFIFOCount(void);
|
||||||
|
void SDIO_StartSDIOReadWait(FunctionalState NewState);
|
||||||
|
void SDIO_StopSDIOReadWait(FunctionalState NewState);
|
||||||
|
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
|
||||||
|
void SDIO_SetSDIOOperation(FunctionalState NewState);
|
||||||
|
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
|
||||||
|
void SDIO_CommandCompletionCmd(FunctionalState NewState);
|
||||||
|
void SDIO_CEATAITCmd(FunctionalState NewState);
|
||||||
|
void SDIO_SendCEATACmd(FunctionalState NewState);
|
||||||
|
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
|
||||||
|
void SDIO_ClearFlag(uint32_t SDIO_FLAG);
|
||||||
|
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
|
||||||
|
void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
231
Peripheral/inc/ch32v30x_spi.h
Normal file
231
Peripheral/inc/ch32v30x_spi.h
Normal file
@@ -0,0 +1,231 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_spi.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* SPI firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_SPI_H
|
||||||
|
#define __CH32V30x_SPI_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* SPI Init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode.
|
||||||
|
This parameter can be a value of @ref SPI_data_direction */
|
||||||
|
|
||||||
|
uint16_t SPI_Mode; /* Specifies the SPI operating mode.
|
||||||
|
This parameter can be a value of @ref SPI_mode */
|
||||||
|
|
||||||
|
uint16_t SPI_DataSize; /* Specifies the SPI data size.
|
||||||
|
This parameter can be a value of @ref SPI_data_size */
|
||||||
|
|
||||||
|
uint16_t SPI_CPOL; /* Specifies the serial clock steady state.
|
||||||
|
This parameter can be a value of @ref SPI_Clock_Polarity */
|
||||||
|
|
||||||
|
uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture.
|
||||||
|
This parameter can be a value of @ref SPI_Clock_Phase */
|
||||||
|
|
||||||
|
uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by
|
||||||
|
hardware (NSS pin) or by software using the SSI bit.
|
||||||
|
This parameter can be a value of @ref SPI_Slave_Select_management */
|
||||||
|
|
||||||
|
uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be
|
||||||
|
used to configure the transmit and receive SCK clock.
|
||||||
|
This parameter can be a value of @ref SPI_BaudRate_Prescaler.
|
||||||
|
@note The communication clock is derived from the master
|
||||||
|
clock. The slave clock does not need to be set. */
|
||||||
|
|
||||||
|
uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit.
|
||||||
|
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
|
||||||
|
|
||||||
|
uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */
|
||||||
|
}SPI_InitTypeDef;
|
||||||
|
|
||||||
|
/* I2S Init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
|
||||||
|
uint16_t I2S_Mode; /* Specifies the I2S operating mode.
|
||||||
|
This parameter can be a value of @ref I2S_Mode */
|
||||||
|
|
||||||
|
uint16_t I2S_Standard; /* Specifies the standard used for the I2S communication.
|
||||||
|
This parameter can be a value of @ref I2S_Standard */
|
||||||
|
|
||||||
|
uint16_t I2S_DataFormat; /* Specifies the data format for the I2S communication.
|
||||||
|
This parameter can be a value of @ref I2S_Data_Format */
|
||||||
|
|
||||||
|
uint16_t I2S_MCLKOutput; /* Specifies whether the I2S MCLK output is enabled or not.
|
||||||
|
This parameter can be a value of @ref I2S_MCLK_Output */
|
||||||
|
|
||||||
|
uint32_t I2S_AudioFreq; /* Specifies the frequency selected for the I2S communication.
|
||||||
|
This parameter can be a value of @ref I2S_Audio_Frequency */
|
||||||
|
|
||||||
|
uint16_t I2S_CPOL; /* Specifies the idle state of the I2S clock.
|
||||||
|
This parameter can be a value of @ref I2S_Clock_Polarity */
|
||||||
|
}I2S_InitTypeDef;
|
||||||
|
|
||||||
|
/* SPI_data_direction */
|
||||||
|
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
|
||||||
|
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
|
||||||
|
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
|
||||||
|
#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
|
||||||
|
|
||||||
|
/* SPI_mode */
|
||||||
|
#define SPI_Mode_Master ((uint16_t)0x0104)
|
||||||
|
#define SPI_Mode_Slave ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* SPI_data_size */
|
||||||
|
#define SPI_DataSize_16b ((uint16_t)0x0800)
|
||||||
|
#define SPI_DataSize_8b ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* SPI_Clock_Polarity */
|
||||||
|
#define SPI_CPOL_Low ((uint16_t)0x0000)
|
||||||
|
#define SPI_CPOL_High ((uint16_t)0x0002)
|
||||||
|
|
||||||
|
/* SPI_Clock_Phase */
|
||||||
|
#define SPI_CPHA_1Edge ((uint16_t)0x0000)
|
||||||
|
#define SPI_CPHA_2Edge ((uint16_t)0x0001)
|
||||||
|
|
||||||
|
/* SPI_Slave_Select_management */
|
||||||
|
#define SPI_NSS_Soft ((uint16_t)0x0200)
|
||||||
|
#define SPI_NSS_Hard ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* SPI_BaudRate_Prescaler */
|
||||||
|
#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
|
||||||
|
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
|
||||||
|
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
|
||||||
|
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
|
||||||
|
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
|
||||||
|
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
|
||||||
|
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
|
||||||
|
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
|
||||||
|
|
||||||
|
/* SPI_MSB_LSB_transmission */
|
||||||
|
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
|
||||||
|
#define SPI_FirstBit_LSB ((uint16_t)0x0080)
|
||||||
|
|
||||||
|
/* I2S_Mode */
|
||||||
|
#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
|
||||||
|
#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
|
||||||
|
#define I2S_Mode_MasterTx ((uint16_t)0x0200)
|
||||||
|
#define I2S_Mode_MasterRx ((uint16_t)0x0300)
|
||||||
|
|
||||||
|
/* I2S_Standard */
|
||||||
|
#define I2S_Standard_Phillips ((uint16_t)0x0000)
|
||||||
|
#define I2S_Standard_MSB ((uint16_t)0x0010)
|
||||||
|
#define I2S_Standard_LSB ((uint16_t)0x0020)
|
||||||
|
#define I2S_Standard_PCMShort ((uint16_t)0x0030)
|
||||||
|
#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
|
||||||
|
|
||||||
|
/* I2S_Data_Format */
|
||||||
|
#define I2S_DataFormat_16b ((uint16_t)0x0000)
|
||||||
|
#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
|
||||||
|
#define I2S_DataFormat_24b ((uint16_t)0x0003)
|
||||||
|
#define I2S_DataFormat_32b ((uint16_t)0x0005)
|
||||||
|
|
||||||
|
/* I2S_MCLK_Output */
|
||||||
|
#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
|
||||||
|
#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* I2S_Audio_Frequency */
|
||||||
|
#define I2S_AudioFreq_192k ((uint32_t)192000)
|
||||||
|
#define I2S_AudioFreq_96k ((uint32_t)96000)
|
||||||
|
#define I2S_AudioFreq_48k ((uint32_t)48000)
|
||||||
|
#define I2S_AudioFreq_44k ((uint32_t)44100)
|
||||||
|
#define I2S_AudioFreq_32k ((uint32_t)32000)
|
||||||
|
#define I2S_AudioFreq_22k ((uint32_t)22050)
|
||||||
|
#define I2S_AudioFreq_16k ((uint32_t)16000)
|
||||||
|
#define I2S_AudioFreq_11k ((uint32_t)11025)
|
||||||
|
#define I2S_AudioFreq_8k ((uint32_t)8000)
|
||||||
|
#define I2S_AudioFreq_Default ((uint32_t)2)
|
||||||
|
|
||||||
|
/* I2S_Clock_Polarity */
|
||||||
|
#define I2S_CPOL_Low ((uint16_t)0x0000)
|
||||||
|
#define I2S_CPOL_High ((uint16_t)0x0008)
|
||||||
|
|
||||||
|
/* SPI_I2S_DMA_transfer_requests */
|
||||||
|
#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
|
||||||
|
#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
|
||||||
|
|
||||||
|
/* SPI_NSS_internal_software_management */
|
||||||
|
#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
|
||||||
|
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
|
||||||
|
|
||||||
|
/* SPI_CRC_Transmit_Receive */
|
||||||
|
#define SPI_CRC_Tx ((uint8_t)0x00)
|
||||||
|
#define SPI_CRC_Rx ((uint8_t)0x01)
|
||||||
|
|
||||||
|
/* SPI_direction_transmit_receive */
|
||||||
|
#define SPI_Direction_Rx ((uint16_t)0xBFFF)
|
||||||
|
#define SPI_Direction_Tx ((uint16_t)0x4000)
|
||||||
|
|
||||||
|
/* SPI_I2S_interrupts_definition */
|
||||||
|
#define SPI_I2S_IT_TXE ((uint8_t)0x71)
|
||||||
|
#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
|
||||||
|
#define SPI_I2S_IT_ERR ((uint8_t)0x50)
|
||||||
|
#define SPI_I2S_IT_OVR ((uint8_t)0x56)
|
||||||
|
#define SPI_IT_MODF ((uint8_t)0x55)
|
||||||
|
#define SPI_IT_CRCERR ((uint8_t)0x54)
|
||||||
|
#define I2S_IT_UDR ((uint8_t)0x53)
|
||||||
|
|
||||||
|
/* SPI_I2S_flags_definition */
|
||||||
|
#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
|
||||||
|
#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
|
||||||
|
#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
|
||||||
|
#define I2S_FLAG_UDR ((uint16_t)0x0008)
|
||||||
|
#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
|
||||||
|
#define SPI_FLAG_MODF ((uint16_t)0x0020)
|
||||||
|
#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
|
||||||
|
#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
|
||||||
|
|
||||||
|
|
||||||
|
void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
|
||||||
|
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
|
||||||
|
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
|
||||||
|
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
|
||||||
|
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
|
||||||
|
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||||
|
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||||
|
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
|
||||||
|
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
|
||||||
|
void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
|
||||||
|
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
|
||||||
|
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
|
||||||
|
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||||
|
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
|
||||||
|
void SPI_TransmitCRC(SPI_TypeDef* SPIx);
|
||||||
|
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||||
|
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
|
||||||
|
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
|
||||||
|
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
|
||||||
|
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
|
||||||
|
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
|
||||||
|
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
|
||||||
|
void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
517
Peripheral/inc/ch32v30x_tim.h
Normal file
517
Peripheral/inc/ch32v30x_tim.h
Normal file
@@ -0,0 +1,517 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_tim.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* TIM firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_TIM_H
|
||||||
|
#define __CH32V30x_TIM_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
/* TIM Time Base Init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock.
|
||||||
|
This parameter can be a number between 0x0000 and 0xFFFF */
|
||||||
|
|
||||||
|
uint16_t TIM_CounterMode; /* Specifies the counter mode.
|
||||||
|
This parameter can be a value of @ref TIM_Counter_Mode */
|
||||||
|
|
||||||
|
uint16_t TIM_Period; /* Specifies the period value to be loaded into the active
|
||||||
|
Auto-Reload Register at the next update event.
|
||||||
|
This parameter must be a number between 0x0000 and 0xFFFF. */
|
||||||
|
|
||||||
|
uint16_t TIM_ClockDivision; /* Specifies the clock division.
|
||||||
|
This parameter can be a value of @ref TIM_Clock_Division_CKD */
|
||||||
|
|
||||||
|
uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter
|
||||||
|
reaches zero, an update event is generated and counting restarts
|
||||||
|
from the RCR value (N).
|
||||||
|
This means in PWM mode that (N+1) corresponds to:
|
||||||
|
- the number of PWM periods in edge-aligned mode
|
||||||
|
- the number of half PWM period in center-aligned mode
|
||||||
|
This parameter must be a number between 0x00 and 0xFF.
|
||||||
|
@note This parameter is valid only for TIM1 and TIM8. */
|
||||||
|
} TIM_TimeBaseInitTypeDef;
|
||||||
|
|
||||||
|
/* TIM Output Compare Init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t TIM_OCMode; /* Specifies the TIM mode.
|
||||||
|
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
|
||||||
|
|
||||||
|
uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state.
|
||||||
|
This parameter can be a value of @ref TIM_Output_Compare_state */
|
||||||
|
|
||||||
|
uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state.
|
||||||
|
This parameter can be a value of @ref TIM_Output_Compare_N_state
|
||||||
|
@note This parameter is valid only for TIM1 and TIM8. */
|
||||||
|
|
||||||
|
uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register.
|
||||||
|
This parameter can be a number between 0x0000 and 0xFFFF */
|
||||||
|
|
||||||
|
uint16_t TIM_OCPolarity; /* Specifies the output polarity.
|
||||||
|
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
|
||||||
|
|
||||||
|
uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity.
|
||||||
|
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
|
||||||
|
@note This parameter is valid only for TIM1 and TIM8. */
|
||||||
|
|
||||||
|
uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
|
||||||
|
This parameter can be a value of @ref TIM_Output_Compare_Idle_State
|
||||||
|
@note This parameter is valid only for TIM1 and TIM8. */
|
||||||
|
|
||||||
|
uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
|
||||||
|
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
|
||||||
|
@note This parameter is valid only for TIM1 and TIM8. */
|
||||||
|
} TIM_OCInitTypeDef;
|
||||||
|
|
||||||
|
/* TIM Input Capture Init structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t TIM_Channel; /* Specifies the TIM channel.
|
||||||
|
This parameter can be a value of @ref TIM_Channel */
|
||||||
|
|
||||||
|
uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal.
|
||||||
|
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
|
||||||
|
|
||||||
|
uint16_t TIM_ICSelection; /* Specifies the input.
|
||||||
|
This parameter can be a value of @ref TIM_Input_Capture_Selection */
|
||||||
|
|
||||||
|
uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler.
|
||||||
|
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
|
||||||
|
|
||||||
|
uint16_t TIM_ICFilter; /* Specifies the input capture filter.
|
||||||
|
This parameter can be a number between 0x0 and 0xF */
|
||||||
|
} TIM_ICInitTypeDef;
|
||||||
|
|
||||||
|
/* BDTR structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode.
|
||||||
|
This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
|
||||||
|
|
||||||
|
uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state.
|
||||||
|
This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
|
||||||
|
|
||||||
|
uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters.
|
||||||
|
This parameter can be a value of @ref Lock_level */
|
||||||
|
|
||||||
|
uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the
|
||||||
|
switching-on of the outputs.
|
||||||
|
This parameter can be a number between 0x00 and 0xFF */
|
||||||
|
|
||||||
|
uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not.
|
||||||
|
This parameter can be a value of @ref Break_Input_enable_disable */
|
||||||
|
|
||||||
|
uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity.
|
||||||
|
This parameter can be a value of @ref Break_Polarity */
|
||||||
|
|
||||||
|
uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not.
|
||||||
|
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
|
||||||
|
} TIM_BDTRInitTypeDef;
|
||||||
|
|
||||||
|
/* TIM_Output_Compare_and_PWM_modes */
|
||||||
|
#define TIM_OCMode_Timing ((uint16_t)0x0000)
|
||||||
|
#define TIM_OCMode_Active ((uint16_t)0x0010)
|
||||||
|
#define TIM_OCMode_Inactive ((uint16_t)0x0020)
|
||||||
|
#define TIM_OCMode_Toggle ((uint16_t)0x0030)
|
||||||
|
#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
|
||||||
|
#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
|
||||||
|
|
||||||
|
/* TIM_One_Pulse_Mode */
|
||||||
|
#define TIM_OPMode_Single ((uint16_t)0x0008)
|
||||||
|
#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* TIM_Channel */
|
||||||
|
#define TIM_Channel_1 ((uint16_t)0x0000)
|
||||||
|
#define TIM_Channel_2 ((uint16_t)0x0004)
|
||||||
|
#define TIM_Channel_3 ((uint16_t)0x0008)
|
||||||
|
#define TIM_Channel_4 ((uint16_t)0x000C)
|
||||||
|
|
||||||
|
/* TIM_Clock_Division_CKD */
|
||||||
|
#define TIM_CKD_DIV1 ((uint16_t)0x0000)
|
||||||
|
#define TIM_CKD_DIV2 ((uint16_t)0x0100)
|
||||||
|
#define TIM_CKD_DIV4 ((uint16_t)0x0200)
|
||||||
|
|
||||||
|
/* TIM_Counter_Mode */
|
||||||
|
#define TIM_CounterMode_Up ((uint16_t)0x0000)
|
||||||
|
#define TIM_CounterMode_Down ((uint16_t)0x0010)
|
||||||
|
#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
|
||||||
|
#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
|
||||||
|
#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
|
||||||
|
|
||||||
|
/* TIM_Output_Compare_Polarity */
|
||||||
|
#define TIM_OCPolarity_High ((uint16_t)0x0000)
|
||||||
|
#define TIM_OCPolarity_Low ((uint16_t)0x0002)
|
||||||
|
|
||||||
|
/* TIM_Output_Compare_N_Polarity */
|
||||||
|
#define TIM_OCNPolarity_High ((uint16_t)0x0000)
|
||||||
|
#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
|
||||||
|
|
||||||
|
/* TIM_Output_Compare_state */
|
||||||
|
#define TIM_OutputState_Disable ((uint16_t)0x0000)
|
||||||
|
#define TIM_OutputState_Enable ((uint16_t)0x0001)
|
||||||
|
|
||||||
|
/* TIM_Output_Compare_N_state */
|
||||||
|
#define TIM_OutputNState_Disable ((uint16_t)0x0000)
|
||||||
|
#define TIM_OutputNState_Enable ((uint16_t)0x0004)
|
||||||
|
|
||||||
|
/* TIM_Capture_Compare_state */
|
||||||
|
#define TIM_CCx_Enable ((uint16_t)0x0001)
|
||||||
|
#define TIM_CCx_Disable ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* TIM_Capture_Compare_N_state */
|
||||||
|
#define TIM_CCxN_Enable ((uint16_t)0x0004)
|
||||||
|
#define TIM_CCxN_Disable ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* Break_Input_enable_disable */
|
||||||
|
#define TIM_Break_Enable ((uint16_t)0x1000)
|
||||||
|
#define TIM_Break_Disable ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* Break_Polarity */
|
||||||
|
#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
|
||||||
|
#define TIM_BreakPolarity_High ((uint16_t)0x2000)
|
||||||
|
|
||||||
|
/* TIM_AOE_Bit_Set_Reset */
|
||||||
|
#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
|
||||||
|
#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* Lock_level */
|
||||||
|
#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
|
||||||
|
#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
|
||||||
|
#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
|
||||||
|
#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
|
||||||
|
|
||||||
|
/* OSSI_Off_State_Selection_for_Idle_mode_state */
|
||||||
|
#define TIM_OSSIState_Enable ((uint16_t)0x0400)
|
||||||
|
#define TIM_OSSIState_Disable ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* OSSR_Off_State_Selection_for_Run_mode_state */
|
||||||
|
#define TIM_OSSRState_Enable ((uint16_t)0x0800)
|
||||||
|
#define TIM_OSSRState_Disable ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* TIM_Output_Compare_Idle_State */
|
||||||
|
#define TIM_OCIdleState_Set ((uint16_t)0x0100)
|
||||||
|
#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* TIM_Output_Compare_N_Idle_State */
|
||||||
|
#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
|
||||||
|
#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* TIM_Input_Capture_Polarity */
|
||||||
|
#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
|
||||||
|
#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
|
||||||
|
#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
|
||||||
|
|
||||||
|
/* TIM_Input_Capture_Selection */
|
||||||
|
#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be
|
||||||
|
connected to IC1, IC2, IC3 or IC4, respectively */
|
||||||
|
#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be
|
||||||
|
connected to IC2, IC1, IC4 or IC3, respectively. */
|
||||||
|
#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
|
||||||
|
|
||||||
|
/* TIM_Input_Capture_Prescaler */
|
||||||
|
#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */
|
||||||
|
#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */
|
||||||
|
#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */
|
||||||
|
#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */
|
||||||
|
|
||||||
|
/* TIM_interrupt_sources */
|
||||||
|
#define TIM_IT_Update ((uint16_t)0x0001)
|
||||||
|
#define TIM_IT_CC1 ((uint16_t)0x0002)
|
||||||
|
#define TIM_IT_CC2 ((uint16_t)0x0004)
|
||||||
|
#define TIM_IT_CC3 ((uint16_t)0x0008)
|
||||||
|
#define TIM_IT_CC4 ((uint16_t)0x0010)
|
||||||
|
#define TIM_IT_COM ((uint16_t)0x0020)
|
||||||
|
#define TIM_IT_Trigger ((uint16_t)0x0040)
|
||||||
|
#define TIM_IT_Break ((uint16_t)0x0080)
|
||||||
|
|
||||||
|
/* TIM_DMA_Base_address */
|
||||||
|
#define TIM_DMABase_CR1 ((uint16_t)0x0000)
|
||||||
|
#define TIM_DMABase_CR2 ((uint16_t)0x0001)
|
||||||
|
#define TIM_DMABase_SMCR ((uint16_t)0x0002)
|
||||||
|
#define TIM_DMABase_DIER ((uint16_t)0x0003)
|
||||||
|
#define TIM_DMABase_SR ((uint16_t)0x0004)
|
||||||
|
#define TIM_DMABase_EGR ((uint16_t)0x0005)
|
||||||
|
#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
|
||||||
|
#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
|
||||||
|
#define TIM_DMABase_CCER ((uint16_t)0x0008)
|
||||||
|
#define TIM_DMABase_CNT ((uint16_t)0x0009)
|
||||||
|
#define TIM_DMABase_PSC ((uint16_t)0x000A)
|
||||||
|
#define TIM_DMABase_ARR ((uint16_t)0x000B)
|
||||||
|
#define TIM_DMABase_RCR ((uint16_t)0x000C)
|
||||||
|
#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
|
||||||
|
#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
|
||||||
|
#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
|
||||||
|
#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
|
||||||
|
#define TIM_DMABase_BDTR ((uint16_t)0x0011)
|
||||||
|
#define TIM_DMABase_DCR ((uint16_t)0x0012)
|
||||||
|
|
||||||
|
/* TIM_DMA_Burst_Length */
|
||||||
|
#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
|
||||||
|
#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
|
||||||
|
#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
|
||||||
|
#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
|
||||||
|
#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
|
||||||
|
#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
|
||||||
|
#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
|
||||||
|
#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
|
||||||
|
#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
|
||||||
|
#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
|
||||||
|
#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
|
||||||
|
#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
|
||||||
|
#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
|
||||||
|
#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
|
||||||
|
#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
|
||||||
|
#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
|
||||||
|
#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
|
||||||
|
#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
|
||||||
|
|
||||||
|
/* TIM_DMA_sources */
|
||||||
|
#define TIM_DMA_Update ((uint16_t)0x0100)
|
||||||
|
#define TIM_DMA_CC1 ((uint16_t)0x0200)
|
||||||
|
#define TIM_DMA_CC2 ((uint16_t)0x0400)
|
||||||
|
#define TIM_DMA_CC3 ((uint16_t)0x0800)
|
||||||
|
#define TIM_DMA_CC4 ((uint16_t)0x1000)
|
||||||
|
#define TIM_DMA_COM ((uint16_t)0x2000)
|
||||||
|
#define TIM_DMA_Trigger ((uint16_t)0x4000)
|
||||||
|
|
||||||
|
/* TIM_External_Trigger_Prescaler */
|
||||||
|
#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
|
||||||
|
#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
|
||||||
|
#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
|
||||||
|
#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
|
||||||
|
|
||||||
|
/* TIM_Internal_Trigger_Selection */
|
||||||
|
#define TIM_TS_ITR0 ((uint16_t)0x0000)
|
||||||
|
#define TIM_TS_ITR1 ((uint16_t)0x0010)
|
||||||
|
#define TIM_TS_ITR2 ((uint16_t)0x0020)
|
||||||
|
#define TIM_TS_ITR3 ((uint16_t)0x0030)
|
||||||
|
#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
|
||||||
|
#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
|
||||||
|
#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
|
||||||
|
#define TIM_TS_ETRF ((uint16_t)0x0070)
|
||||||
|
|
||||||
|
/* TIM_TIx_External_Clock_Source */
|
||||||
|
#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
|
||||||
|
#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
|
||||||
|
#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
|
||||||
|
|
||||||
|
/* TIM_External_Trigger_Polarity */
|
||||||
|
#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
|
||||||
|
#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* TIM_Prescaler_Reload_Mode */
|
||||||
|
#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
|
||||||
|
#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
|
||||||
|
|
||||||
|
/* TIM_Forced_Action */
|
||||||
|
#define TIM_ForcedAction_Active ((uint16_t)0x0050)
|
||||||
|
#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
|
||||||
|
|
||||||
|
/* TIM_Encoder_Mode */
|
||||||
|
#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
|
||||||
|
#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
|
||||||
|
#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
|
||||||
|
|
||||||
|
/* TIM_Event_Source */
|
||||||
|
#define TIM_EventSource_Update ((uint16_t)0x0001)
|
||||||
|
#define TIM_EventSource_CC1 ((uint16_t)0x0002)
|
||||||
|
#define TIM_EventSource_CC2 ((uint16_t)0x0004)
|
||||||
|
#define TIM_EventSource_CC3 ((uint16_t)0x0008)
|
||||||
|
#define TIM_EventSource_CC4 ((uint16_t)0x0010)
|
||||||
|
#define TIM_EventSource_COM ((uint16_t)0x0020)
|
||||||
|
#define TIM_EventSource_Trigger ((uint16_t)0x0040)
|
||||||
|
#define TIM_EventSource_Break ((uint16_t)0x0080)
|
||||||
|
|
||||||
|
/* TIM_Update_Source */
|
||||||
|
#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow
|
||||||
|
or the setting of UG bit, or an update generation
|
||||||
|
through the slave mode controller. */
|
||||||
|
#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */
|
||||||
|
|
||||||
|
/* TIM_Output_Compare_Preload_State */
|
||||||
|
#define TIM_OCPreload_Enable ((uint16_t)0x0008)
|
||||||
|
#define TIM_OCPreload_Disable ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* TIM_Output_Compare_Fast_State */
|
||||||
|
#define TIM_OCFast_Enable ((uint16_t)0x0004)
|
||||||
|
#define TIM_OCFast_Disable ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* TIM_Output_Compare_Clear_State */
|
||||||
|
#define TIM_OCClear_Enable ((uint16_t)0x0080)
|
||||||
|
#define TIM_OCClear_Disable ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* TIM_Trigger_Output_Source */
|
||||||
|
#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
|
||||||
|
#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
|
||||||
|
#define TIM_TRGOSource_Update ((uint16_t)0x0020)
|
||||||
|
#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
|
||||||
|
#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
|
||||||
|
#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
|
||||||
|
#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
|
||||||
|
#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
|
||||||
|
|
||||||
|
/* TIM_Slave_Mode */
|
||||||
|
#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
|
||||||
|
#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
|
||||||
|
#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
|
||||||
|
#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
|
||||||
|
|
||||||
|
/* TIM_Master_Slave_Mode */
|
||||||
|
#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
|
||||||
|
#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* TIM_Flags */
|
||||||
|
#define TIM_FLAG_Update ((uint16_t)0x0001)
|
||||||
|
#define TIM_FLAG_CC1 ((uint16_t)0x0002)
|
||||||
|
#define TIM_FLAG_CC2 ((uint16_t)0x0004)
|
||||||
|
#define TIM_FLAG_CC3 ((uint16_t)0x0008)
|
||||||
|
#define TIM_FLAG_CC4 ((uint16_t)0x0010)
|
||||||
|
#define TIM_FLAG_COM ((uint16_t)0x0020)
|
||||||
|
#define TIM_FLAG_Trigger ((uint16_t)0x0040)
|
||||||
|
#define TIM_FLAG_Break ((uint16_t)0x0080)
|
||||||
|
#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
|
||||||
|
#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
|
||||||
|
#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
|
||||||
|
#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
|
||||||
|
|
||||||
|
/* TIM_Legacy */
|
||||||
|
#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
|
||||||
|
#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
|
||||||
|
#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
|
||||||
|
#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
|
||||||
|
#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
|
||||||
|
#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
|
||||||
|
#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
|
||||||
|
#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
|
||||||
|
#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
|
||||||
|
#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
|
||||||
|
#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
|
||||||
|
#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
|
||||||
|
#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
|
||||||
|
#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
|
||||||
|
#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
|
||||||
|
#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
|
||||||
|
#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
|
||||||
|
#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
|
||||||
|
|
||||||
|
|
||||||
|
void TIM_DeInit(TIM_TypeDef* TIMx);
|
||||||
|
void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
|
||||||
|
void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
|
||||||
|
void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
|
||||||
|
void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
|
||||||
|
void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
|
||||||
|
void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
|
||||||
|
void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
|
||||||
|
void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
|
||||||
|
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
|
||||||
|
void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
|
||||||
|
void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
|
||||||
|
void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
|
||||||
|
void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||||
|
void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||||
|
void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
|
||||||
|
void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
|
||||||
|
void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
|
||||||
|
void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
|
||||||
|
void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
|
||||||
|
void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
|
||||||
|
void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
|
||||||
|
uint16_t TIM_ICPolarity, uint16_t ICFilter);
|
||||||
|
void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
|
||||||
|
uint16_t ExtTRGFilter);
|
||||||
|
void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
|
||||||
|
uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
|
||||||
|
void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
|
||||||
|
uint16_t ExtTRGFilter);
|
||||||
|
void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
|
||||||
|
void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
|
||||||
|
void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
|
||||||
|
void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
|
||||||
|
uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
|
||||||
|
void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
|
||||||
|
void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
|
||||||
|
void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
|
||||||
|
void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
|
||||||
|
void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||||
|
void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||||
|
void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||||
|
void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||||
|
void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
|
||||||
|
void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
|
||||||
|
void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
|
||||||
|
void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
|
||||||
|
void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
|
||||||
|
void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
|
||||||
|
void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
|
||||||
|
void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
|
||||||
|
void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
|
||||||
|
void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
|
||||||
|
void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
|
||||||
|
void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
|
||||||
|
void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
|
||||||
|
void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
|
||||||
|
void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
|
||||||
|
void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
|
||||||
|
void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
|
||||||
|
void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
|
||||||
|
void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
|
||||||
|
void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
|
||||||
|
void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
|
||||||
|
void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
|
||||||
|
void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||||
|
void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
|
||||||
|
void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||||
|
void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
|
||||||
|
void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
|
||||||
|
void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
|
||||||
|
void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
|
||||||
|
void TIM_SetCounter(TIM_TypeDef* TIMx, uint16_t Counter);
|
||||||
|
void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint16_t Autoreload);
|
||||||
|
void TIM_SetCompare1(TIM_TypeDef* TIMx, uint16_t Compare1);
|
||||||
|
void TIM_SetCompare2(TIM_TypeDef* TIMx, uint16_t Compare2);
|
||||||
|
void TIM_SetCompare3(TIM_TypeDef* TIMx, uint16_t Compare3);
|
||||||
|
void TIM_SetCompare4(TIM_TypeDef* TIMx, uint16_t Compare4);
|
||||||
|
void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
|
||||||
|
void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
|
||||||
|
void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
|
||||||
|
void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
|
||||||
|
void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
|
||||||
|
uint16_t TIM_GetCapture1(TIM_TypeDef* TIMx);
|
||||||
|
uint16_t TIM_GetCapture2(TIM_TypeDef* TIMx);
|
||||||
|
uint16_t TIM_GetCapture3(TIM_TypeDef* TIMx);
|
||||||
|
uint16_t TIM_GetCapture4(TIM_TypeDef* TIMx);
|
||||||
|
uint16_t TIM_GetCounter(TIM_TypeDef* TIMx);
|
||||||
|
uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
|
||||||
|
FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
|
||||||
|
void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
|
||||||
|
ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
|
||||||
|
void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
195
Peripheral/inc/ch32v30x_usart.h
Normal file
195
Peripheral/inc/ch32v30x_usart.h
Normal file
@@ -0,0 +1,195 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_usart.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2024/03/06
|
||||||
|
* Description : This file contains all the functions prototypes for the
|
||||||
|
* USART firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_USART_H
|
||||||
|
#define __CH32V30x_USART_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
|
||||||
|
/* USART Init Structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t USART_BaudRate; /* This member configures the USART communication baud rate.
|
||||||
|
The baud rate is computed using the following formula:
|
||||||
|
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
|
||||||
|
- FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
|
||||||
|
|
||||||
|
uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame.
|
||||||
|
This parameter can be a value of @ref USART_Word_Length */
|
||||||
|
|
||||||
|
uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted.
|
||||||
|
This parameter can be a value of @ref USART_Stop_Bits */
|
||||||
|
|
||||||
|
uint16_t USART_Parity; /* Specifies the parity mode.
|
||||||
|
This parameter can be a value of @ref USART_Parity
|
||||||
|
@note When parity is enabled, the computed parity is inserted
|
||||||
|
at the MSB position of the transmitted data (9th bit when
|
||||||
|
the word length is set to 9 data bits; 8th bit when the
|
||||||
|
word length is set to 8 data bits). */
|
||||||
|
|
||||||
|
uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref USART_Mode */
|
||||||
|
|
||||||
|
uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled
|
||||||
|
or disabled.
|
||||||
|
This parameter can be a value of @ref USART_Hardware_Flow_Control */
|
||||||
|
} USART_InitTypeDef;
|
||||||
|
|
||||||
|
/* USART Clock Init Structure definition */
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
|
||||||
|
uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled.
|
||||||
|
This parameter can be a value of @ref USART_Clock */
|
||||||
|
|
||||||
|
uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock.
|
||||||
|
This parameter can be a value of @ref USART_Clock_Polarity */
|
||||||
|
|
||||||
|
uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made.
|
||||||
|
This parameter can be a value of @ref USART_Clock_Phase */
|
||||||
|
|
||||||
|
uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted
|
||||||
|
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||||
|
This parameter can be a value of @ref USART_Last_Bit */
|
||||||
|
} USART_ClockInitTypeDef;
|
||||||
|
|
||||||
|
/* USART_Word_Length */
|
||||||
|
#define USART_WordLength_8b ((uint16_t)0x0000)
|
||||||
|
#define USART_WordLength_9b ((uint16_t)0x1000)
|
||||||
|
|
||||||
|
/* USART_Stop_Bits */
|
||||||
|
#define USART_StopBits_1 ((uint16_t)0x0000)
|
||||||
|
#define USART_StopBits_0_5 ((uint16_t)0x1000)
|
||||||
|
#define USART_StopBits_2 ((uint16_t)0x2000)
|
||||||
|
#define USART_StopBits_1_5 ((uint16_t)0x3000)
|
||||||
|
|
||||||
|
/* USART_Parity */
|
||||||
|
#define USART_Parity_No ((uint16_t)0x0000)
|
||||||
|
#define USART_Parity_Even ((uint16_t)0x0400)
|
||||||
|
#define USART_Parity_Odd ((uint16_t)0x0600)
|
||||||
|
|
||||||
|
/* USART_Mode */
|
||||||
|
#define USART_Mode_Rx ((uint16_t)0x0004)
|
||||||
|
#define USART_Mode_Tx ((uint16_t)0x0008)
|
||||||
|
|
||||||
|
/* USART_Hardware_Flow_Control */
|
||||||
|
#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
|
||||||
|
#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
|
||||||
|
#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
|
||||||
|
#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
|
||||||
|
|
||||||
|
/* USART_Clock */
|
||||||
|
#define USART_Clock_Disable ((uint16_t)0x0000)
|
||||||
|
#define USART_Clock_Enable ((uint16_t)0x0800)
|
||||||
|
|
||||||
|
/* USART_Clock_Polarity */
|
||||||
|
#define USART_CPOL_Low ((uint16_t)0x0000)
|
||||||
|
#define USART_CPOL_High ((uint16_t)0x0400)
|
||||||
|
|
||||||
|
/* USART_Clock_Phase */
|
||||||
|
#define USART_CPHA_1Edge ((uint16_t)0x0000)
|
||||||
|
#define USART_CPHA_2Edge ((uint16_t)0x0200)
|
||||||
|
|
||||||
|
/* USART_Last_Bit */
|
||||||
|
#define USART_LastBit_Disable ((uint16_t)0x0000)
|
||||||
|
#define USART_LastBit_Enable ((uint16_t)0x0100)
|
||||||
|
|
||||||
|
/* USART_Interrupt_definition */
|
||||||
|
#define USART_IT_PE ((uint16_t)0x0028)
|
||||||
|
#define USART_IT_TXE ((uint16_t)0x0727)
|
||||||
|
#define USART_IT_TC ((uint16_t)0x0626)
|
||||||
|
#define USART_IT_RXNE ((uint16_t)0x0525)
|
||||||
|
#define USART_IT_ORE_RX ((uint16_t)0x0325)
|
||||||
|
#define USART_IT_IDLE ((uint16_t)0x0424)
|
||||||
|
#define USART_IT_LBD ((uint16_t)0x0846)
|
||||||
|
#define USART_IT_CTS ((uint16_t)0x096A)
|
||||||
|
#define USART_IT_ERR ((uint16_t)0x0060)
|
||||||
|
#define USART_IT_ORE_ER ((uint16_t)0x0360)
|
||||||
|
#define USART_IT_NE ((uint16_t)0x0260)
|
||||||
|
#define USART_IT_FE ((uint16_t)0x0160)
|
||||||
|
|
||||||
|
#define USART_IT_ORE USART_IT_ORE_ER
|
||||||
|
|
||||||
|
/* USART_DMA_Requests */
|
||||||
|
#define USART_DMAReq_Tx ((uint16_t)0x0080)
|
||||||
|
#define USART_DMAReq_Rx ((uint16_t)0x0040)
|
||||||
|
|
||||||
|
/* USART_WakeUp_methods */
|
||||||
|
#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
|
||||||
|
#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
|
||||||
|
|
||||||
|
/* USART_LIN_Break_Detection_Length */
|
||||||
|
#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
|
||||||
|
#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
|
||||||
|
|
||||||
|
/* USART_IrDA_Low_Power */
|
||||||
|
#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
|
||||||
|
#define USART_IrDAMode_Normal ((uint16_t)0x0000)
|
||||||
|
|
||||||
|
/* USART_Flags */
|
||||||
|
#define USART_FLAG_CTS ((uint16_t)0x0200)
|
||||||
|
#define USART_FLAG_LBD ((uint16_t)0x0100)
|
||||||
|
#define USART_FLAG_TXE ((uint16_t)0x0080)
|
||||||
|
#define USART_FLAG_TC ((uint16_t)0x0040)
|
||||||
|
#define USART_FLAG_RXNE ((uint16_t)0x0020)
|
||||||
|
#define USART_FLAG_IDLE ((uint16_t)0x0010)
|
||||||
|
#define USART_FLAG_ORE ((uint16_t)0x0008)
|
||||||
|
#define USART_FLAG_NE ((uint16_t)0x0004)
|
||||||
|
#define USART_FLAG_FE ((uint16_t)0x0002)
|
||||||
|
#define USART_FLAG_PE ((uint16_t)0x0001)
|
||||||
|
|
||||||
|
|
||||||
|
void USART_DeInit(USART_TypeDef* USARTx);
|
||||||
|
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
|
||||||
|
void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
|
||||||
|
void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
|
||||||
|
void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
|
||||||
|
void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||||
|
void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
|
||||||
|
void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
|
||||||
|
void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
|
||||||
|
void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
|
||||||
|
void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||||
|
void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
|
||||||
|
void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||||
|
void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
|
||||||
|
uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
|
||||||
|
void USART_SendBreak(USART_TypeDef* USARTx);
|
||||||
|
void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
|
||||||
|
void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
|
||||||
|
void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||||
|
void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||||
|
void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||||
|
void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
|
||||||
|
void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||||
|
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
|
||||||
|
void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
|
||||||
|
ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
|
||||||
|
void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
834
Peripheral/inc/ch32v30x_usb.h
Normal file
834
Peripheral/inc/ch32v30x_usb.h
Normal file
@@ -0,0 +1,834 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : system_ch32v30x.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2024/05/22
|
||||||
|
* Description : CH32V30x Device Peripheral Access Layer System Header File.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
#ifndef __CH32V30x_USB_H
|
||||||
|
#define __CH32V30x_USB_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*******************************************************************************/
|
||||||
|
/* Header File */
|
||||||
|
#include "stdint.h"
|
||||||
|
|
||||||
|
/*******************************************************************************/
|
||||||
|
/* USB Communication Related Macro Definition */
|
||||||
|
/* USB Endpoint0 Size */
|
||||||
|
#ifndef DEFAULT_ENDP0_SIZE
|
||||||
|
#define DEFAULT_ENDP0_SIZE 8 // default maximum packet size for endpoint 0
|
||||||
|
#endif
|
||||||
|
#ifndef MAX_PACKET_SIZE
|
||||||
|
#define MAX_PACKET_SIZE 64 // maximum packet size
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* USB PID */
|
||||||
|
#ifndef USB_PID_SETUP
|
||||||
|
#define USB_PID_NULL 0x00
|
||||||
|
#define USB_PID_SOF 0x05
|
||||||
|
#define USB_PID_SETUP 0x0D
|
||||||
|
#define USB_PID_IN 0x09
|
||||||
|
#define USB_PID_OUT 0x01
|
||||||
|
#define USB_PID_NYET 0x06
|
||||||
|
#define USB_PID_ACK 0x02
|
||||||
|
#define USB_PID_NAK 0x0A
|
||||||
|
#define USB_PID_STALL 0x0E
|
||||||
|
#define USB_PID_DATA0 0x03
|
||||||
|
#define USB_PID_DATA1 0x0B
|
||||||
|
#define USB_PID_DATA2 0x07
|
||||||
|
#define USB_PID_MDATA 0x0F
|
||||||
|
#define USB_PID_PRE 0x0C
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* USB standard device request code */
|
||||||
|
#ifndef USB_GET_DESCRIPTOR
|
||||||
|
#define USB_GET_STATUS 0x00
|
||||||
|
#define USB_CLEAR_FEATURE 0x01
|
||||||
|
#define USB_SET_FEATURE 0x03
|
||||||
|
#define USB_SET_ADDRESS 0x05
|
||||||
|
#define USB_GET_DESCRIPTOR 0x06
|
||||||
|
#define USB_SET_DESCRIPTOR 0x07
|
||||||
|
#define USB_GET_CONFIGURATION 0x08
|
||||||
|
#define USB_SET_CONFIGURATION 0x09
|
||||||
|
#define USB_GET_INTERFACE 0x0A
|
||||||
|
#define USB_SET_INTERFACE 0x0B
|
||||||
|
#define USB_SYNCH_FRAME 0x0C
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define DEF_STRING_DESC_LANG 0x00
|
||||||
|
#define DEF_STRING_DESC_MANU 0x01
|
||||||
|
#define DEF_STRING_DESC_PROD 0x02
|
||||||
|
#define DEF_STRING_DESC_SERN 0x03
|
||||||
|
|
||||||
|
/* USB hub class request code */
|
||||||
|
#ifndef HUB_GET_DESCRIPTOR
|
||||||
|
#define HUB_GET_STATUS 0x00
|
||||||
|
#define HUB_CLEAR_FEATURE 0x01
|
||||||
|
#define HUB_GET_STATE 0x02
|
||||||
|
#define HUB_SET_FEATURE 0x03
|
||||||
|
#define HUB_GET_DESCRIPTOR 0x06
|
||||||
|
#define HUB_SET_DESCRIPTOR 0x07
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* USB HID class request code */
|
||||||
|
#ifndef HID_GET_REPORT
|
||||||
|
#define HID_GET_REPORT 0x01
|
||||||
|
#define HID_GET_IDLE 0x02
|
||||||
|
#define HID_GET_PROTOCOL 0x03
|
||||||
|
#define HID_SET_REPORT 0x09
|
||||||
|
#define HID_SET_IDLE 0x0A
|
||||||
|
#define HID_SET_PROTOCOL 0x0B
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* USB CDC Class request code */
|
||||||
|
#ifndef CDC_GET_LINE_CODING
|
||||||
|
#define CDC_GET_LINE_CODING 0x21 /* This request allows the host to find out the currently configured line coding */
|
||||||
|
#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */
|
||||||
|
#define CDC_SET_LINE_CTLSTE 0x22 /* This request generates RS-232/V.24 style control signals */
|
||||||
|
#define CDC_SEND_BREAK 0x23 /* Sends special carrier modulation used to specify RS-232 style break */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Bit Define for USB Request Type */
|
||||||
|
#ifndef USB_REQ_TYP_MASK
|
||||||
|
#define USB_REQ_TYP_IN 0x80
|
||||||
|
#define USB_REQ_TYP_OUT 0x00
|
||||||
|
#define USB_REQ_TYP_READ 0x80
|
||||||
|
#define USB_REQ_TYP_WRITE 0x00
|
||||||
|
#define USB_REQ_TYP_MASK 0x60
|
||||||
|
#define USB_REQ_TYP_STANDARD 0x00
|
||||||
|
#define USB_REQ_TYP_CLASS 0x20
|
||||||
|
#define USB_REQ_TYP_VENDOR 0x40
|
||||||
|
#define USB_REQ_TYP_RESERVED 0x60
|
||||||
|
#define USB_REQ_RECIP_MASK 0x1F
|
||||||
|
#define USB_REQ_RECIP_DEVICE 0x00
|
||||||
|
#define USB_REQ_RECIP_INTERF 0x01
|
||||||
|
#define USB_REQ_RECIP_ENDP 0x02
|
||||||
|
#define USB_REQ_RECIP_OTHER 0x03
|
||||||
|
#define USB_REQ_FEAT_REMOTE_WAKEUP 0x01
|
||||||
|
#define USB_REQ_FEAT_ENDP_HALT 0x00
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* USB Descriptor Type */
|
||||||
|
#ifndef USB_DESCR_TYP_DEVICE
|
||||||
|
#define USB_DESCR_TYP_DEVICE 0x01
|
||||||
|
#define USB_DESCR_TYP_CONFIG 0x02
|
||||||
|
#define USB_DESCR_TYP_STRING 0x03
|
||||||
|
#define USB_DESCR_TYP_INTERF 0x04
|
||||||
|
#define USB_DESCR_TYP_ENDP 0x05
|
||||||
|
#define USB_DESCR_TYP_QUALIF 0x06
|
||||||
|
#define USB_DESCR_TYP_SPEED 0x07
|
||||||
|
#define USB_DESCR_TYP_OTG 0x09
|
||||||
|
#define USB_DESCR_TYP_BOS 0X0F
|
||||||
|
#define USB_DESCR_TYP_HID 0x21
|
||||||
|
#define USB_DESCR_TYP_REPORT 0x22
|
||||||
|
#define USB_DESCR_TYP_PHYSIC 0x23
|
||||||
|
#define USB_DESCR_TYP_CS_INTF 0x24
|
||||||
|
#define USB_DESCR_TYP_CS_ENDP 0x25
|
||||||
|
#define USB_DESCR_TYP_HUB 0x29
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* USB Device Class */
|
||||||
|
#ifndef USB_DEV_CLASS_HUB
|
||||||
|
#define USB_DEV_CLASS_RESERVED 0x00
|
||||||
|
#define USB_DEV_CLASS_AUDIO 0x01
|
||||||
|
#define USB_DEV_CLASS_COMMUNIC 0x02
|
||||||
|
#define USB_DEV_CLASS_HID 0x03
|
||||||
|
#define USB_DEV_CLASS_MONITOR 0x04
|
||||||
|
#define USB_DEV_CLASS_PHYSIC_IF 0x05
|
||||||
|
#define USB_DEV_CLASS_POWER 0x06
|
||||||
|
#define USB_DEV_CLASS_IMAGE 0x06
|
||||||
|
#define USB_DEV_CLASS_PRINTER 0x07
|
||||||
|
#define USB_DEV_CLASS_STORAGE 0x08
|
||||||
|
#define USB_DEV_CLASS_HUB 0x09
|
||||||
|
#define USB_DEV_CLASS_VEN_SPEC 0xFF
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* USB Hub Class Request */
|
||||||
|
#ifndef HUB_GET_HUB_DESCRIPTOR
|
||||||
|
#define HUB_CLEAR_HUB_FEATURE 0x20
|
||||||
|
#define HUB_CLEAR_PORT_FEATURE 0x23
|
||||||
|
#define HUB_GET_BUS_STATE 0xA3
|
||||||
|
#define HUB_GET_HUB_DESCRIPTOR 0xA0
|
||||||
|
#define HUB_GET_HUB_STATUS 0xA0
|
||||||
|
#define HUB_GET_PORT_STATUS 0xA3
|
||||||
|
#define HUB_SET_HUB_DESCRIPTOR 0x20
|
||||||
|
#define HUB_SET_HUB_FEATURE 0x20
|
||||||
|
#define HUB_SET_PORT_FEATURE 0x23
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Hub Class Feature Selectors */
|
||||||
|
#ifndef HUB_PORT_RESET
|
||||||
|
#define HUB_C_HUB_LOCAL_POWER 0
|
||||||
|
#define HUB_C_HUB_OVER_CURRENT 1
|
||||||
|
#define HUB_PORT_CONNECTION 0
|
||||||
|
#define HUB_PORT_ENABLE 1
|
||||||
|
#define HUB_PORT_SUSPEND 2
|
||||||
|
#define HUB_PORT_OVER_CURRENT 3
|
||||||
|
#define HUB_PORT_RESET 4
|
||||||
|
#define HUB_PORT_POWER 8
|
||||||
|
#define HUB_PORT_LOW_SPEED 9
|
||||||
|
#define HUB_C_PORT_CONNECTION 16
|
||||||
|
#define HUB_C_PORT_ENABLE 17
|
||||||
|
#define HUB_C_PORT_SUSPEND 18
|
||||||
|
#define HUB_C_PORT_OVER_CURRENT 19
|
||||||
|
#define HUB_C_PORT_RESET 20
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* USB UDisk */
|
||||||
|
#ifndef USB_BO_CBW_SIZE
|
||||||
|
#define USB_BO_CBW_SIZE 0x1F
|
||||||
|
#define USB_BO_CSW_SIZE 0x0D
|
||||||
|
#endif
|
||||||
|
#ifndef USB_BO_CBW_SIG0
|
||||||
|
#define USB_BO_CBW_SIG0 0x55
|
||||||
|
#define USB_BO_CBW_SIG1 0x53
|
||||||
|
#define USB_BO_CBW_SIG2 0x42
|
||||||
|
#define USB_BO_CBW_SIG3 0x43
|
||||||
|
#define USB_BO_CSW_SIG0 0x55
|
||||||
|
#define USB_BO_CSW_SIG1 0x53
|
||||||
|
#define USB_BO_CSW_SIG2 0x42
|
||||||
|
#define USB_BO_CSW_SIG3 0x53
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
/* USBHS Clock Configuration Related Macro Definition */
|
||||||
|
#define USB_CLK_SRC 0x80000000
|
||||||
|
#define USBHS_PLL_ALIVE 0x40000000
|
||||||
|
#define USBHS_PLL_CKREF_MASK 0x30000000
|
||||||
|
#define USBHS_PLL_CKREF_3M 0x00000000
|
||||||
|
#define USBHS_PLL_CKREF_4M 0x10000000
|
||||||
|
#define USBHS_PLL_CKREF_8M 0x20000000
|
||||||
|
#define USBHS_PLL_CKREF_5M 0x30000000
|
||||||
|
#define USBHS_PLL_SRC 0x08000000
|
||||||
|
#define USBHS_PLL_SRC_PRE_MASK 0x07000000
|
||||||
|
#define USBHS_PLL_SRC_PRE_DIV1 0x00000000
|
||||||
|
#define USBHS_PLL_SRC_PRE_DIV2 0x01000000
|
||||||
|
#define USBHS_PLL_SRC_PRE_DIV3 0x02000000
|
||||||
|
#define USBHS_PLL_SRC_PRE_DIV4 0x03000000
|
||||||
|
#define USBHS_PLL_SRC_PRE_DIV5 0x04000000
|
||||||
|
#define USBHS_PLL_SRC_PRE_DIV6 0x05000000
|
||||||
|
#define USBHS_PLL_SRC_PRE_DIV7 0x06000000
|
||||||
|
#define USBHS_PLL_SRC_PRE_DIV8 0x07000000
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************/
|
||||||
|
/* USBHS Related Register Macro Definition */
|
||||||
|
|
||||||
|
/* R8_USB_CTRL */
|
||||||
|
#define USBHS_UC_HOST_MODE 0x80
|
||||||
|
#define USBHS_UC_SPEED_TYPE 0x60
|
||||||
|
#define USBHS_UC_SPEED_LOW 0x40
|
||||||
|
#define USBHS_UC_SPEED_FULL 0x00
|
||||||
|
#define USBHS_UC_SPEED_HIGH 0x20
|
||||||
|
#define USBHS_UC_DEV_PU_EN 0x10
|
||||||
|
#define USBHS_UC_INT_BUSY 0x08
|
||||||
|
#define USBHS_UC_RESET_SIE 0x04
|
||||||
|
#define USBHS_UC_CLR_ALL 0x02
|
||||||
|
#define USBHS_UC_DMA_EN 0x01
|
||||||
|
|
||||||
|
/* R8_USB_INT_EN */
|
||||||
|
#define USBHS_UIE_DEV_NAK 0x80
|
||||||
|
#define USBHS_UIE_ISO_ACT 0x40
|
||||||
|
#define USBHS_UIE_SETUP_ACT 0x20
|
||||||
|
#define USBHS_UIE_FIFO_OV 0x10
|
||||||
|
#define USBHS_UIE_SOF_ACT 0x08
|
||||||
|
#define USBHS_UIE_SUSPEND 0x04
|
||||||
|
#define USBHS_UIE_TRANSFER 0x02
|
||||||
|
#define USBHS_UIE_DETECT 0x01
|
||||||
|
#define USBHS_UIE_BUS_RST 0x01
|
||||||
|
|
||||||
|
/* R16_USB_DEV_AD */
|
||||||
|
#define USBHS_MASK_USB_ADDR 0x7F
|
||||||
|
|
||||||
|
/* R16_USB_FRAME_NO */
|
||||||
|
#define USBHS_MICRO_FRAME_NUM 0xE000
|
||||||
|
#define USBHS_SOF_FRAME_NUM 0x07FF
|
||||||
|
|
||||||
|
/* R8_USB_SUSPEND */
|
||||||
|
#define USBHS_USB_LINESTATE 0x30
|
||||||
|
#define USBHS_USB_WAKEUP_ST 0x04
|
||||||
|
#define USBHS_USB_SYS_MOD 0x03
|
||||||
|
|
||||||
|
/* R8_USB_SPEED_TYPE */
|
||||||
|
#define USBHS_USB_SPEED_TYPE 0x03
|
||||||
|
#define USBHS_USB_SPEED_LOW 0x02
|
||||||
|
#define USBHS_USB_SPEED_FULL 0x00
|
||||||
|
#define USBHS_USB_SPEED_HIGH 0x01
|
||||||
|
|
||||||
|
/* R8_USB_MIS_ST */
|
||||||
|
#define USBHS_UMS_SOF_PRES 0x80
|
||||||
|
#define USBHS_UMS_SOF_ACT 0x40
|
||||||
|
#define USBHS_UMS_SIE_FREE 0x20
|
||||||
|
#define USBHS_UMS_R_FIFO_RDY 0x10
|
||||||
|
#define USBHS_UMS_BUS_RESET 0x08
|
||||||
|
#define USBHS_UMS_SUSPEND 0x04
|
||||||
|
#define USBHS_UMS_DEV_ATTACH 0x02
|
||||||
|
#define USBHS_UMS_SPLIT_CAN 0x01
|
||||||
|
|
||||||
|
/* R8_USB_INT_FG */
|
||||||
|
#define USBHS_UIF_ISO_ACT 0x40
|
||||||
|
#define USBHS_UIF_SETUP_ACT 0x20
|
||||||
|
#define USBHS_UIF_FIFO_OV 0x10
|
||||||
|
#define USBHS_UIF_HST_SOF 0x08
|
||||||
|
#define USBHS_UIF_SUSPEND 0x04
|
||||||
|
#define USBHS_UIF_TRANSFER 0x02
|
||||||
|
#define USBHS_UIF_DETECT 0x01
|
||||||
|
#define USBHS_UIF_BUS_RST 0x01
|
||||||
|
|
||||||
|
/* R8_USB_INT_ST */
|
||||||
|
#define USBHS_UIS_IS_NAK 0x80
|
||||||
|
#define USBHS_UIS_TOG_OK 0x40
|
||||||
|
#define USBHS_UIS_TOKEN_MASK 0x30
|
||||||
|
#define USBHS_UIS_TOKEN_OUT 0x00
|
||||||
|
#define USBHS_UIS_TOKEN_SOF 0x10
|
||||||
|
#define USBHS_UIS_TOKEN_IN 0x20
|
||||||
|
#define USBHS_UIS_TOKEN_SETUP 0x30
|
||||||
|
#define USBHS_UIS_ENDP_MASK 0x0F
|
||||||
|
#define USBHS_UIS_H_RES_MASK 0x0F
|
||||||
|
|
||||||
|
/* R16_USB_RX_LEN */
|
||||||
|
#define USBHS_USB_RX_LEN 0xFFFF
|
||||||
|
|
||||||
|
/* R32_UEP_CONFIG */
|
||||||
|
#define USBHS_UEP15_R_EN 0x80000000
|
||||||
|
#define USBHS_UEP14_R_EN 0x40000000
|
||||||
|
#define USBHS_UEP13_R_EN 0x20000000
|
||||||
|
#define USBHS_UEP12_R_EN 0x10000000
|
||||||
|
#define USBHS_UEP11_R_EN 0x08000000
|
||||||
|
#define USBHS_UEP10_R_EN 0x04000000
|
||||||
|
#define USBHS_UEP9_R_EN 0x02000000
|
||||||
|
#define USBHS_UEP8_R_EN 0x01000000
|
||||||
|
#define USBHS_UEP7_R_EN 0x00800000
|
||||||
|
#define USBHS_UEP6_R_EN 0x00400000
|
||||||
|
#define USBHS_UEP5_R_EN 0x00200000
|
||||||
|
#define USBHS_UEP4_R_EN 0x00100000
|
||||||
|
#define USBHS_UEP3_R_EN 0x00080000
|
||||||
|
#define USBHS_UEP2_R_EN 0x00040000
|
||||||
|
#define USBHS_UEP1_R_EN 0x00020000
|
||||||
|
#define USBHS_UEP0_R_EN 0x00010000
|
||||||
|
#define USBHS_UEP15_T_EN 0x00008000
|
||||||
|
#define USBHS_UEP14_T_EN 0x00004000
|
||||||
|
#define USBHS_UEP13_T_EN 0x00002000
|
||||||
|
#define USBHS_UEP12_T_EN 0x00001000
|
||||||
|
#define USBHS_UEP11_T_EN 0x00000800
|
||||||
|
#define USBHS_UEP10_T_EN 0x00000400
|
||||||
|
#define USBHS_UEP9_T_EN 0x00000200
|
||||||
|
#define USBHS_UEP8_T_EN 0x00000100
|
||||||
|
#define USBHS_UEP7_T_EN 0x00000080
|
||||||
|
#define USBHS_UEP6_T_EN 0x00000040
|
||||||
|
#define USBHS_UEP5_T_EN 0x00000020
|
||||||
|
#define USBHS_UEP4_T_EN 0x00000010
|
||||||
|
#define USBHS_UEP3_T_EN 0x00000008
|
||||||
|
#define USBHS_UEP2_T_EN 0x00000004
|
||||||
|
#define USBHS_UEP1_T_EN 0x00000002
|
||||||
|
#define USBHS_UEP0_T_EN 0x00000001
|
||||||
|
|
||||||
|
/* R32_UEP_TYPE */
|
||||||
|
#define USBHS_UEP15_R_TYPE 0x80000000
|
||||||
|
#define USBHS_UEP14_R_TYPE 0x40000000
|
||||||
|
#define USBHS_UEP13_R_TYPE 0x20000000
|
||||||
|
#define USBHS_UEP12_R_TYPE 0x10000000
|
||||||
|
#define USBHS_UEP11_R_TYPE 0x08000000
|
||||||
|
#define USBHS_UEP10_R_TYPE 0x04000000
|
||||||
|
#define USBHS_UEP9_R_TYPE 0x02000000
|
||||||
|
#define USBHS_UEP8_R_TYPE 0x01000000
|
||||||
|
#define USBHS_UEP7_R_TYPE 0x00800000
|
||||||
|
#define USBHS_UEP6_R_TYPE 0x00400000
|
||||||
|
#define USBHS_UEP5_R_TYPE 0x00200000
|
||||||
|
#define USBHS_UEP4_R_TYPE 0x00100000
|
||||||
|
#define USBHS_UEP3_R_TYPE 0x00080000
|
||||||
|
#define USBHS_UEP2_R_TYPE 0x00040000
|
||||||
|
#define USBHS_UEP1_R_TYPE 0x00020000
|
||||||
|
#define USBHS_UEP0_R_TYPE 0x00010000
|
||||||
|
#define USBHS_UEP15_T_TYPE 0x00008000
|
||||||
|
#define USBHS_UEP14_T_TYPE 0x00004000
|
||||||
|
#define USBHS_UEP13_T_TYPE 0x00002000
|
||||||
|
#define USBHS_UEP12_T_TYPE 0x00001000
|
||||||
|
#define USBHS_UEP11_T_TYPE 0x00000800
|
||||||
|
#define USBHS_UEP10_T_TYPE 0x00000400
|
||||||
|
#define USBHS_UEP9_T_TYPE 0x00000200
|
||||||
|
#define USBHS_UEP8_T_TYPE 0x00000100
|
||||||
|
#define USBHS_UEP7_T_TYPE 0x00000080
|
||||||
|
#define USBHS_UEP6_T_TYPE 0x00000040
|
||||||
|
#define USBHS_UEP5_T_TYPE 0x00000020
|
||||||
|
#define USBHS_UEP4_T_TYPE 0x00000010
|
||||||
|
#define USBHS_UEP3_T_TYPE 0x00000008
|
||||||
|
#define USBHS_UEP2_T_TYPE 0x00000004
|
||||||
|
#define USBHS_UEP1_T_TYPE 0x00000002
|
||||||
|
#define USBHS_UEP0_T_TYPE 0x00000001
|
||||||
|
|
||||||
|
/* R32_UEP_BUF_MOD */
|
||||||
|
#define USBHS_UEP15_ISO_BUF_MOD 0x80000000
|
||||||
|
#define USBHS_UEP14_ISO_BUF_MOD 0x40000000
|
||||||
|
#define USBHS_UEP13_ISO_BUF_MOD 0x20000000
|
||||||
|
#define USBHS_UEP12_ISO_BUF_MOD 0x10000000
|
||||||
|
#define USBHS_UEP11_ISO_BUF_MOD 0x08000000
|
||||||
|
#define USBHS_UEP10_ISO_BUF_MOD 0x04000000
|
||||||
|
#define USBHS_UEP9_ISO_BUF_MOD 0x02000000
|
||||||
|
#define USBHS_UEP8_ISO_BUF_MOD 0x01000000
|
||||||
|
#define USBHS_UEP7_ISO_BUF_MOD 0x00800000
|
||||||
|
#define USBHS_UEP6_ISO_BUF_MOD 0x00400000
|
||||||
|
#define USBHS_UEP5_ISO_BUF_MOD 0x00200000
|
||||||
|
#define USBHS_UEP4_ISO_BUF_MOD 0x00100000
|
||||||
|
#define USBHS_UEP3_ISO_BUF_MOD 0x00080000
|
||||||
|
#define USBHS_UEP2_ISO_BUF_MOD 0x00040000
|
||||||
|
#define USBHS_UEP1_ISO_BUF_MOD 0x00020000
|
||||||
|
#define USBHS_UEP0_ISO_BUF_MOD 0x00010000
|
||||||
|
#define USBHS_UEP15_BUF_MOD 0x00008000
|
||||||
|
#define USBHS_UEP14_BUF_MOD 0x00004000
|
||||||
|
#define USBHS_UEP13_BUF_MOD 0x00002000
|
||||||
|
#define USBHS_UEP12_BUF_MOD 0x00001000
|
||||||
|
#define USBHS_UEP11_BUF_MOD 0x00000800
|
||||||
|
#define USBHS_UEP10_BUF_MOD 0x00000400
|
||||||
|
#define USBHS_UEP9_BUF_MOD 0x00000200
|
||||||
|
#define USBHS_UEP8_BUF_MOD 0x00000100
|
||||||
|
#define USBHS_UEP7_BUF_MOD 0x00000080
|
||||||
|
#define USBHS_UEP6_BUF_MOD 0x00000040
|
||||||
|
#define USBHS_UEP5_BUF_MOD 0x00000020
|
||||||
|
#define USBHS_UEP4_BUF_MOD 0x00000010
|
||||||
|
#define USBHS_UEP3_BUF_MOD 0x00000008
|
||||||
|
#define USBHS_UEP2_BUF_MOD 0x00000004
|
||||||
|
#define USBHS_UEP1_BUF_MOD 0x00000002
|
||||||
|
#define USBHS_UEP0_BUF_MOD 0x00000001
|
||||||
|
|
||||||
|
/* R32_UEP0_DMA */
|
||||||
|
#define USBHS_UEP0_DMA 0x0000FFFF
|
||||||
|
|
||||||
|
/* R32_UEPn_TX_DMA, n=1-15 */
|
||||||
|
#define USBHS_UEPn_TX_DMA 0x0000FFFF
|
||||||
|
|
||||||
|
/* R32_UEPn_RX_DMA, n=1-15 */
|
||||||
|
#define USBHS_UEPn_RX_DMA 0x0000FFFF
|
||||||
|
|
||||||
|
/* R16_UEPn_MAX_LEN, n=0-15 */
|
||||||
|
#define USBHS_UEPn_MAX_LEN 0x07FF
|
||||||
|
|
||||||
|
/* R16_UEPn_T_LEN, n=0-15 */
|
||||||
|
#define USBHS_UEPn_T_LEN 0x07FF
|
||||||
|
|
||||||
|
/* R8_UEPn_TX_CTRL, n=0-15 */
|
||||||
|
#define USBHS_UEP_T_TOG_AUTO 0x20
|
||||||
|
#define USBHS_UEP_T_TOG_MASK 0x18
|
||||||
|
#define USBHS_UEP_T_TOG_DATA0 0x00
|
||||||
|
#define USBHS_UEP_T_TOG_DATA1 0x08
|
||||||
|
#define USBHS_UEP_T_TOG_DATA2 0x10
|
||||||
|
#define USBHS_UEP_T_TOG_MDATA 0x18
|
||||||
|
#define USBHS_UEP_T_RES_MASK 0x03
|
||||||
|
#define USBHS_UEP_T_RES_ACK 0x00
|
||||||
|
#define USBHS_UEP_T_RES_NYET 0x01
|
||||||
|
#define USBHS_UEP_T_RES_NAK 0x02
|
||||||
|
#define USBHS_UEP_T_RES_STALL 0x03
|
||||||
|
|
||||||
|
/* R8_UEPn_TX_CTRL, n=0-15 */
|
||||||
|
#define USBHS_UEP_R_TOG_AUTO 0x20
|
||||||
|
#define USBHS_UEP_R_TOG_MASK 0x18
|
||||||
|
#define USBHS_UEP_R_TOG_DATA0 0x00
|
||||||
|
#define USBHS_UEP_R_TOG_DATA1 0x08
|
||||||
|
#define USBHS_UEP_R_TOG_DATA2 0x10
|
||||||
|
#define USBHS_UEP_R_TOG_MDATA 0x18
|
||||||
|
#define USBHS_UEP_R_RES_MASK 0x03
|
||||||
|
#define USBHS_UEP_R_RES_ACK 0x00
|
||||||
|
#define USBHS_UEP_R_RES_NYET 0x01
|
||||||
|
#define USBHS_UEP_R_RES_NAK 0x02
|
||||||
|
#define USBHS_UEP_R_RES_STALL 0x03
|
||||||
|
|
||||||
|
/* R8_UHOST_CTRL */
|
||||||
|
#define USBHS_UH_SOF_EN 0x80
|
||||||
|
#define USBHS_UH_SOF_FREE 0x40
|
||||||
|
#define USBHS_UH_PHY_SUSPENDM 0x10
|
||||||
|
#define USBHS_UH_REMOTE_WKUP 0x08
|
||||||
|
#define USBHS_UH_TX_BUS_RESUME 0x04
|
||||||
|
#define USBHS_UH_TX_BUS_SUSPEND 0x02
|
||||||
|
#define USBHS_UH_TX_BUS_RESET 0x01
|
||||||
|
|
||||||
|
/* R32_UH_CONFIG */
|
||||||
|
#define USBHS_UH_EP_RX_EN 0x00040000
|
||||||
|
#define USBHS_UH_EP_TX_EN 0x00000008
|
||||||
|
|
||||||
|
/* R32_UH_EP_TYPE */
|
||||||
|
#define USBHS_UH_EP_RX_TYPE 0x00040000
|
||||||
|
#define USBHS_UH_EP_TX_TYPE 0x00000008
|
||||||
|
|
||||||
|
/* R32_UH_RX_DMA */
|
||||||
|
#define USBHS_UH_RX_DMA 0x0000FFFC
|
||||||
|
|
||||||
|
/* R32_UH_TX_DMA */
|
||||||
|
#define USBHS_UH_TX_DMA 0x0000FFFF
|
||||||
|
|
||||||
|
/* R16_UH_RX_MAX_LEN */
|
||||||
|
#define USBHS_UH_RX_MAX_LEN 0x07FF
|
||||||
|
|
||||||
|
/* R8_UH_EP_PID */
|
||||||
|
#define USBHS_UH_TOKEN_MASK 0xF0
|
||||||
|
#define USBHS_UH_ENDP_MASK 0x0F
|
||||||
|
|
||||||
|
/* R8_UH_RX_CTRL */
|
||||||
|
#define USBHS_UH_R_DATA_NO 0x40
|
||||||
|
#define USBHS_UH_R_TOG_AUTO 0x20
|
||||||
|
#define USBHS_UH_R_TOG_MASK 0x18
|
||||||
|
#define USBHS_UH_R_TOG_DATA0 0x00
|
||||||
|
#define USBHS_UH_R_TOG_DATA1 0x08
|
||||||
|
#define USBHS_UH_R_TOG_DATA2 0x10
|
||||||
|
#define USBHS_UH_R_TOG_MDATA 0x18
|
||||||
|
#define USBHS_UH_R_RES_NO 0x04
|
||||||
|
#define USBHS_UH_R_RES_MASK 0x03
|
||||||
|
#define USBHS_UH_R_RES_ACK 0x00
|
||||||
|
#define USBHS_UH_R_RES_NYET 0x01
|
||||||
|
#define USBHS_UH_R_RES_NAK 0x02
|
||||||
|
#define USBHS_UH_R_RES_STALL 0x03
|
||||||
|
|
||||||
|
/* R16_UH_TX_LEN */
|
||||||
|
#define USBHS_UH_TX_LEN 0x07FF
|
||||||
|
|
||||||
|
/* R8_UH_TX_CTRL */
|
||||||
|
#define USBHS_UH_T_DATA_NO 0x40
|
||||||
|
#define USBHS_UH_T_AUTO_TOG 0x20
|
||||||
|
#define USBHS_UH_T_TOG_MASK 0x18
|
||||||
|
#define USBHS_UH_T_TOG_DATA0 0x00
|
||||||
|
#define USBHS_UH_T_TOG_DATA1 0x08
|
||||||
|
#define USBHS_UH_T_TOG_DATA2 0x10
|
||||||
|
#define USBHS_UH_T_TOG_MDATA 0x18
|
||||||
|
#define USBHS_UH_T_RES_NO 0x04
|
||||||
|
#define USBHS_UH_T_RES_MASK 0x03
|
||||||
|
#define USBHS_UH_T_RES_ACK 0x00
|
||||||
|
#define USBHS_UH_T_RES_NYET 0x01
|
||||||
|
#define USBHS_UH_T_RES_NAK 0x02
|
||||||
|
#define USBHS_UH_T_RES_STALL 0x03
|
||||||
|
|
||||||
|
/* R16_UH_SPLIT_DATA */
|
||||||
|
#define USBHS_UH_SPLIT_DATA 0x0FFF
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************/
|
||||||
|
/* USBFS Related Register Macro Definition */
|
||||||
|
|
||||||
|
/* R8_USB_CTRL */
|
||||||
|
#define USBFS_UC_HOST_MODE 0x80
|
||||||
|
#define USBFS_UC_LOW_SPEED 0x40
|
||||||
|
#define USBFS_UC_DEV_PU_EN 0x20
|
||||||
|
#define USBFS_UC_SYS_CTRL_MASK 0x30
|
||||||
|
#define USBFS_UC_SYS_CTRL0 0x00
|
||||||
|
#define USBFS_UC_SYS_CTRL1 0x10
|
||||||
|
#define USBFS_UC_SYS_CTRL2 0x20
|
||||||
|
#define USBFS_UC_SYS_CTRL3 0x30
|
||||||
|
#define USBFS_UC_INT_BUSY 0x08
|
||||||
|
#define USBFS_UC_RESET_SIE 0x04
|
||||||
|
#define USBFS_UC_CLR_ALL 0x02
|
||||||
|
#define USBFS_UC_DMA_EN 0x01
|
||||||
|
|
||||||
|
/* R8_USB_INT_EN */
|
||||||
|
#define USBFS_UIE_DEV_SOF 0x80
|
||||||
|
#define USBFS_UIE_DEV_NAK 0x40
|
||||||
|
#define USBFS_1WIRE_MODE 0x20
|
||||||
|
#define USBFS_UIE_FIFO_OV 0x10
|
||||||
|
#define USBFS_UIE_HST_SOF 0x08
|
||||||
|
#define USBFS_UIE_SUSPEND 0x04
|
||||||
|
#define USBFS_UIE_TRANSFER 0x02
|
||||||
|
#define USBFS_UIE_DETECT 0x01
|
||||||
|
#define USBFS_UIE_BUS_RST 0x01
|
||||||
|
|
||||||
|
/* R8_USB_DEV_AD */
|
||||||
|
#define USBFS_UDA_GP_BIT 0x80
|
||||||
|
#define USBFS_USB_ADDR_MASK 0x7F
|
||||||
|
|
||||||
|
/* R8_USB_MIS_ST */
|
||||||
|
#define USBFS_UMS_SOF_PRES 0x80
|
||||||
|
#define USBFS_UMS_SOF_ACT 0x40
|
||||||
|
#define USBFS_UMS_SIE_FREE 0x20
|
||||||
|
#define USBFS_UMS_R_FIFO_RDY 0x10
|
||||||
|
#define USBFS_UMS_BUS_RESET 0x08
|
||||||
|
#define USBFS_UMS_SUSPEND 0x04
|
||||||
|
#define USBFS_UMS_DM_LEVEL 0x02
|
||||||
|
#define USBFS_UMS_DEV_ATTACH 0x01
|
||||||
|
|
||||||
|
/* R8_USB_INT_FG */
|
||||||
|
#define USBFS_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received
|
||||||
|
#define USBFS_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK
|
||||||
|
#define USBFS_U_SIE_FREE 0x20 // RO, indicate USB SIE free status
|
||||||
|
#define USBFS_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
|
||||||
|
#define USBFS_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
|
||||||
|
#define USBFS_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
|
||||||
|
#define USBFS_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
|
||||||
|
#define USBFS_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear
|
||||||
|
#define USBFS_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear
|
||||||
|
|
||||||
|
/* R8_USB_INT_ST */
|
||||||
|
#define USBFS_UIS_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode
|
||||||
|
#define USBFS_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK
|
||||||
|
#define USBFS_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode
|
||||||
|
#define USBFS_UIS_TOKEN_OUT 0x00
|
||||||
|
#define USBFS_UIS_TOKEN_SOF 0x10
|
||||||
|
#define USBFS_UIS_TOKEN_IN 0x20
|
||||||
|
#define USBFS_UIS_TOKEN_SETUP 0x30
|
||||||
|
// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode
|
||||||
|
// 00: OUT token PID received
|
||||||
|
// 01: SOF token PID received
|
||||||
|
// 10: IN token PID received
|
||||||
|
// 11: SETUP token PID received
|
||||||
|
#define USBFS_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode
|
||||||
|
#define USBFS_UIS_H_RES_MASK 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received
|
||||||
|
|
||||||
|
/* R32_USB_OTG_CR */
|
||||||
|
#define USBFS_CR_SESS_VTH 0x20
|
||||||
|
#define USBFS_CR_VBUS_VTH 0x10
|
||||||
|
#define USBFS_CR_OTG_EN 0x08
|
||||||
|
#define USBFS_CR_IDPU 0x04
|
||||||
|
#define USBFS_CR_CHARGE_VBUS 0x02
|
||||||
|
#define USBFS_CR_DISCHAR_VBUS 0x01
|
||||||
|
|
||||||
|
/* R32_USB_OTG_SR */
|
||||||
|
#define USBFS_SR_ID_DIG 0x08
|
||||||
|
#define USBFS_SR_SESS_END 0x04
|
||||||
|
#define USBFS_SR_SESS_VLD 0x02
|
||||||
|
#define USBFS_SR_VBUS_VLD 0x01
|
||||||
|
|
||||||
|
/* R8_UDEV_CTRL */
|
||||||
|
#define USBFS_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
|
||||||
|
#define USBFS_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level
|
||||||
|
#define USBFS_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level
|
||||||
|
#define USBFS_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed
|
||||||
|
#define USBFS_UD_GP_BIT 0x02 // general purpose bit
|
||||||
|
#define USBFS_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable
|
||||||
|
|
||||||
|
/* R8_UEP4_1_MOD */
|
||||||
|
#define USBFS_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT)
|
||||||
|
#define USBFS_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN)
|
||||||
|
#define USBFS_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1
|
||||||
|
#define USBFS_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT)
|
||||||
|
#define USBFS_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN)
|
||||||
|
#define USBFS_UEP4_BUF_MOD 0x01
|
||||||
|
|
||||||
|
/* R8_UEP2_3_MOD */
|
||||||
|
#define USBFS_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT)
|
||||||
|
#define USBFS_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN)
|
||||||
|
#define USBFS_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3
|
||||||
|
#define USBFS_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT)
|
||||||
|
#define USBFS_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN)
|
||||||
|
#define USBFS_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2
|
||||||
|
|
||||||
|
/* R8_UEP5_6_MOD */
|
||||||
|
#define USBFS_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT)
|
||||||
|
#define USBFS_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN)
|
||||||
|
#define USBFS_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6
|
||||||
|
#define USBFS_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT)
|
||||||
|
#define USBFS_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN)
|
||||||
|
#define USBFS_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5
|
||||||
|
|
||||||
|
/* R8_UEP7_MOD */
|
||||||
|
#define USBFS_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT)
|
||||||
|
#define USBFS_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN)
|
||||||
|
#define USBFS_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7
|
||||||
|
|
||||||
|
/* R8_UEPn_TX_CTRL */
|
||||||
|
#define USBFS_UEP_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
|
||||||
|
#define USBFS_UEP_T_TOG 0x04 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
|
||||||
|
#define USBFS_UEP_T_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN)
|
||||||
|
#define USBFS_UEP_T_RES_ACK 0x00
|
||||||
|
#define USBFS_UEP_T_RES_NONE 0x01
|
||||||
|
#define USBFS_UEP_T_RES_NAK 0x02
|
||||||
|
#define USBFS_UEP_T_RES_STALL 0x03
|
||||||
|
// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN)
|
||||||
|
// 00: DATA0 or DATA1 then expecting ACK (ready)
|
||||||
|
// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions
|
||||||
|
// 10: NAK (busy)
|
||||||
|
// 11: STALL (error)
|
||||||
|
// host aux setup
|
||||||
|
|
||||||
|
/* R8_UEPn_RX_CTRL, n=0-7 */
|
||||||
|
#define USBFS_UEP_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
|
||||||
|
#define USBFS_UEP_R_TOG 0x04 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
|
||||||
|
#define USBFS_UEP_R_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X receiving (OUT)
|
||||||
|
#define USBFS_UEP_R_RES_ACK 0x00
|
||||||
|
#define USBFS_UEP_R_RES_NONE 0x01
|
||||||
|
#define USBFS_UEP_R_RES_NAK 0x02
|
||||||
|
#define USBFS_UEP_R_RES_STALL 0x03
|
||||||
|
// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT)
|
||||||
|
// 00: ACK (ready)
|
||||||
|
// 01: no response, time out to host, for non-zero endpoint isochronous transactions
|
||||||
|
// 10: NAK (busy)
|
||||||
|
// 11: STALL (error)
|
||||||
|
|
||||||
|
/* R8_UHOST_CTRL */
|
||||||
|
#define USBFS_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
|
||||||
|
#define USBFS_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level
|
||||||
|
#define USBFS_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level
|
||||||
|
#define USBFS_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed
|
||||||
|
#define USBFS_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset
|
||||||
|
#define USBFS_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached
|
||||||
|
|
||||||
|
/* R32_UH_EP_MOD */
|
||||||
|
#define USBFS_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal
|
||||||
|
#define USBFS_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint
|
||||||
|
// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA
|
||||||
|
// 0 x: disable endpoint and disable buffer
|
||||||
|
// 1 0: 64 bytes buffer for transmittal (OUT endpoint)
|
||||||
|
// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes
|
||||||
|
#define USBFS_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving
|
||||||
|
#define USBFS_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint
|
||||||
|
// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA
|
||||||
|
// 0 x: disable endpoint and disable buffer
|
||||||
|
// 1 0: 64 bytes buffer for receiving (IN endpoint)
|
||||||
|
// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes
|
||||||
|
|
||||||
|
/* R16_UH_SETUP */
|
||||||
|
#define USBFS_UH_PRE_PID_EN 0x0400 // USB host PRE PID enable for low speed device via hub
|
||||||
|
#define USBFS_UH_SOF_EN 0x0004 // USB host automatic SOF enable
|
||||||
|
|
||||||
|
/* R8_UH_EP_PID */
|
||||||
|
#define USBFS_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer
|
||||||
|
#define USBFS_UH_ENDP_MASK 0x0F // bit mask of endpoint number for USB host transfer
|
||||||
|
|
||||||
|
/* R8_UH_RX_CTRL */
|
||||||
|
#define USBFS_UH_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
|
||||||
|
#define USBFS_UH_R_TOG 0x04 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1
|
||||||
|
#define USBFS_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions
|
||||||
|
|
||||||
|
/* R8_UH_TX_CTRL */
|
||||||
|
#define USBFS_UH_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
|
||||||
|
#define USBFS_UH_T_TOG 0x04 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1
|
||||||
|
#define USBFS_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions
|
||||||
|
|
||||||
|
|
||||||
|
/*******************************************************************************/
|
||||||
|
/* Struct Definition */
|
||||||
|
|
||||||
|
/* USB Setup Request */
|
||||||
|
typedef struct __attribute__((packed)) _USB_SETUP_REQ
|
||||||
|
{
|
||||||
|
uint8_t bRequestType;
|
||||||
|
uint8_t bRequest;
|
||||||
|
uint16_t wValue;
|
||||||
|
uint16_t wIndex;
|
||||||
|
uint16_t wLength;
|
||||||
|
} USB_SETUP_REQ, *PUSB_SETUP_REQ;
|
||||||
|
|
||||||
|
/* USB Device Descriptor */
|
||||||
|
typedef struct __attribute__((packed)) _USB_DEVICE_DESCR
|
||||||
|
{
|
||||||
|
uint8_t bLength;
|
||||||
|
uint8_t bDescriptorType;
|
||||||
|
uint16_t bcdUSB;
|
||||||
|
uint8_t bDeviceClass;
|
||||||
|
uint8_t bDeviceSubClass;
|
||||||
|
uint8_t bDeviceProtocol;
|
||||||
|
uint8_t bMaxPacketSize0;
|
||||||
|
uint16_t idVendor;
|
||||||
|
uint16_t idProduct;
|
||||||
|
uint16_t bcdDevice;
|
||||||
|
uint8_t iManufacturer;
|
||||||
|
uint8_t iProduct;
|
||||||
|
uint8_t iSerialNumber;
|
||||||
|
uint8_t bNumConfigurations;
|
||||||
|
} USB_DEV_DESCR, *PUSB_DEV_DESCR;
|
||||||
|
|
||||||
|
/* USB Configuration Descriptor */
|
||||||
|
typedef struct __attribute__((packed)) _USB_CONFIG_DESCR
|
||||||
|
{
|
||||||
|
uint8_t bLength;
|
||||||
|
uint8_t bDescriptorType;
|
||||||
|
uint16_t wTotalLength;
|
||||||
|
uint8_t bNumInterfaces;
|
||||||
|
uint8_t bConfigurationValue;
|
||||||
|
uint8_t iConfiguration;
|
||||||
|
uint8_t bmAttributes;
|
||||||
|
uint8_t MaxPower;
|
||||||
|
} USB_CFG_DESCR, *PUSB_CFG_DESCR;
|
||||||
|
|
||||||
|
/* USB Interface Descriptor */
|
||||||
|
typedef struct __attribute__((packed)) _USB_INTERF_DESCR
|
||||||
|
{
|
||||||
|
uint8_t bLength;
|
||||||
|
uint8_t bDescriptorType;
|
||||||
|
uint8_t bInterfaceNumber;
|
||||||
|
uint8_t bAlternateSetting;
|
||||||
|
uint8_t bNumEndpoints;
|
||||||
|
uint8_t bInterfaceClass;
|
||||||
|
uint8_t bInterfaceSubClass;
|
||||||
|
uint8_t bInterfaceProtocol;
|
||||||
|
uint8_t iInterface;
|
||||||
|
} USB_ITF_DESCR, *PUSB_ITF_DESCR;
|
||||||
|
|
||||||
|
/* USB Endpoint Descriptor */
|
||||||
|
typedef struct __attribute__((packed)) _USB_ENDPOINT_DESCR
|
||||||
|
{
|
||||||
|
uint8_t bLength;
|
||||||
|
uint8_t bDescriptorType;
|
||||||
|
uint8_t bEndpointAddress;
|
||||||
|
uint8_t bmAttributes;
|
||||||
|
uint8_t wMaxPacketSizeL;
|
||||||
|
uint8_t wMaxPacketSizeH;
|
||||||
|
uint8_t bInterval;
|
||||||
|
} USB_ENDP_DESCR, *PUSB_ENDP_DESCR;
|
||||||
|
|
||||||
|
/* USB Configuration Descriptor Set */
|
||||||
|
typedef struct __attribute__((packed)) _USB_CONFIG_DESCR_LONG
|
||||||
|
{
|
||||||
|
USB_CFG_DESCR cfg_descr;
|
||||||
|
USB_ITF_DESCR itf_descr;
|
||||||
|
USB_ENDP_DESCR endp_descr[ 1 ];
|
||||||
|
} USB_CFG_DESCR_LONG, *PUSB_CFG_DESCR_LONG;
|
||||||
|
|
||||||
|
/* USB HUB Descriptor */
|
||||||
|
typedef struct __attribute__((packed)) _USB_HUB_DESCR
|
||||||
|
{
|
||||||
|
uint8_t bDescLength;
|
||||||
|
uint8_t bDescriptorType;
|
||||||
|
uint8_t bNbrPorts;
|
||||||
|
uint8_t wHubCharacteristicsL;
|
||||||
|
uint8_t wHubCharacteristicsH;
|
||||||
|
uint8_t bPwrOn2PwrGood;
|
||||||
|
uint8_t bHubContrCurrent;
|
||||||
|
uint8_t DeviceRemovable;
|
||||||
|
uint8_t PortPwrCtrlMask;
|
||||||
|
} USB_HUB_DESCR, *PUSB_HUB_DESCR;
|
||||||
|
|
||||||
|
/* USB HID Descriptor */
|
||||||
|
typedef struct __attribute__((packed)) _USB_HID_DESCR
|
||||||
|
{
|
||||||
|
uint8_t bLength;
|
||||||
|
uint8_t bDescriptorType;
|
||||||
|
uint16_t bcdHID;
|
||||||
|
uint8_t bCountryCode;
|
||||||
|
uint8_t bNumDescriptors;
|
||||||
|
uint8_t bDescriptorTypeX;
|
||||||
|
uint8_t wDescriptorLengthL;
|
||||||
|
uint8_t wDescriptorLengthH;
|
||||||
|
} USB_HID_DESCR, *PUSB_HID_DESCR;
|
||||||
|
|
||||||
|
/* USB UDisk */
|
||||||
|
typedef struct __attribute__((packed)) _UDISK_BOC_CBW
|
||||||
|
{
|
||||||
|
uint32_t mCBW_Sig;
|
||||||
|
uint32_t mCBW_Tag;
|
||||||
|
uint32_t mCBW_DataLen;
|
||||||
|
uint8_t mCBW_Flag;
|
||||||
|
uint8_t mCBW_LUN;
|
||||||
|
uint8_t mCBW_CB_Len;
|
||||||
|
uint8_t mCBW_CB_Buf[ 16 ];
|
||||||
|
} UDISK_BOC_CBW, *PXUDISK_BOC_CBW;
|
||||||
|
|
||||||
|
/* USB UDisk */
|
||||||
|
typedef struct __attribute__((packed)) _UDISK_BOC_CSW
|
||||||
|
{
|
||||||
|
uint32_t mCBW_Sig;
|
||||||
|
uint32_t mCBW_Tag;
|
||||||
|
uint32_t mCSW_Residue;
|
||||||
|
uint8_t mCSW_Status;
|
||||||
|
} UDISK_BOC_CSW, *PXUDISK_BOC_CSW;
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __CH32V30x_USB_H */
|
||||||
44
Peripheral/inc/ch32v30x_wwdg.h
Normal file
44
Peripheral/inc/ch32v30x_wwdg.h
Normal file
@@ -0,0 +1,44 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_wwdg.h
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file contains all the functions prototypes for the WWDG
|
||||||
|
* firmware library.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#ifndef __CH32V30x_WWDG_H
|
||||||
|
#define __CH32V30x_WWDG_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "ch32v30x.h"
|
||||||
|
|
||||||
|
|
||||||
|
/* WWDG_Prescaler */
|
||||||
|
#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
|
||||||
|
#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
|
||||||
|
#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
|
||||||
|
#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
|
||||||
|
|
||||||
|
|
||||||
|
void WWDG_DeInit(void);
|
||||||
|
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
|
||||||
|
void WWDG_SetWindowValue(uint8_t WindowValue);
|
||||||
|
void WWDG_EnableIT(void);
|
||||||
|
void WWDG_SetCounter(uint8_t Counter);
|
||||||
|
void WWDG_Enable(uint8_t Counter);
|
||||||
|
FlagStatus WWDG_GetFlagStatus(void);
|
||||||
|
void WWDG_ClearFlag(void);
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
1182
Peripheral/src/ch32v30x_adc.c
Normal file
1182
Peripheral/src/ch32v30x_adc.c
Normal file
File diff suppressed because it is too large
Load Diff
244
Peripheral/src/ch32v30x_bkp.c
Normal file
244
Peripheral/src/ch32v30x_bkp.c
Normal file
@@ -0,0 +1,244 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_bkp.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2024/03/06
|
||||||
|
* Description : This file provides all the BKP firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_bkp.h"
|
||||||
|
#include "ch32v30x_rcc.h"
|
||||||
|
|
||||||
|
/* BKP registers bit mask */
|
||||||
|
|
||||||
|
/* OCTLR register bit mask */
|
||||||
|
#define OCTLR_CAL_MASK ((uint16_t)0xFF80)
|
||||||
|
#define OCTLR_MASK ((uint16_t)0xFC7F)
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn BKP_DeInit
|
||||||
|
*
|
||||||
|
* @brief Deinitializes the BKP peripheral registers to their default reset values.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void BKP_DeInit(void)
|
||||||
|
{
|
||||||
|
RCC_BackupResetCmd(ENABLE);
|
||||||
|
RCC_BackupResetCmd(DISABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn BKP_TamperPinLevelConfig
|
||||||
|
*
|
||||||
|
* @brief Configures the Tamper Pin active level.
|
||||||
|
*
|
||||||
|
* @param BKP_TamperPinLevel: specifies the Tamper Pin active level.
|
||||||
|
* BKP_TamperPinLevel_High - Tamper pin active on high level.
|
||||||
|
* BKP_TamperPinLevel_Low - Tamper pin active on low level.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void BKP_TamperPinLevelConfig(uint16_t BKP_TamperPinLevel)
|
||||||
|
{
|
||||||
|
if(BKP_TamperPinLevel)
|
||||||
|
{
|
||||||
|
BKP->TPCTLR |= (1 << 1);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
BKP->TPCTLR &= ~(1 << 1);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn BKP_TamperPinCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the Tamper Pin activation.
|
||||||
|
*
|
||||||
|
* @param NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void BKP_TamperPinCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
{
|
||||||
|
BKP->TPCTLR |= (1 << 0);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
BKP->TPCTLR &= ~(1 << 0);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn BKP_ITConfig
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the Tamper Pin Interrupt.
|
||||||
|
*
|
||||||
|
* @param NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void BKP_ITConfig(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
{
|
||||||
|
BKP->TPCSR |= (1 << 2);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
BKP->TPCSR &= ~(1 << 2);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn BKP_RTCOutputConfig
|
||||||
|
*
|
||||||
|
* @brief Select the RTC output source to output on the Tamper pin.
|
||||||
|
*
|
||||||
|
* @param BKP_RTCOutputSource - specifies the RTC output source.
|
||||||
|
* BKP_RTCOutputSource_None - no RTC output on the Tamper pin.
|
||||||
|
* BKP_RTCOutputSource_CalibClock - output the RTC clock with
|
||||||
|
* frequency divided by 64 on the Tamper pin.
|
||||||
|
* BKP_RTCOutputSource_Alarm - output the RTC Alarm pulse signal
|
||||||
|
* on the Tamper pin.
|
||||||
|
* BKP_RTCOutputSource_Second - output the RTC Second pulse
|
||||||
|
* signal on the Tamper pin.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void BKP_RTCOutputConfig(uint16_t BKP_RTCOutputSource)
|
||||||
|
{
|
||||||
|
uint16_t tmpreg = 0;
|
||||||
|
|
||||||
|
tmpreg = BKP->OCTLR;
|
||||||
|
tmpreg &= OCTLR_MASK;
|
||||||
|
tmpreg |= BKP_RTCOutputSource;
|
||||||
|
BKP->OCTLR = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn BKP_SetRTCCalibrationValue
|
||||||
|
*
|
||||||
|
* @brief Sets RTC Clock Calibration value.
|
||||||
|
*
|
||||||
|
* @param CalibrationValue - specifies the RTC Clock Calibration value.
|
||||||
|
* This parameter must be a number between 0 and 0x7F.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void BKP_SetRTCCalibrationValue(uint8_t CalibrationValue)
|
||||||
|
{
|
||||||
|
uint16_t tmpreg = 0;
|
||||||
|
|
||||||
|
tmpreg = BKP->OCTLR;
|
||||||
|
tmpreg &= OCTLR_CAL_MASK;
|
||||||
|
tmpreg |= CalibrationValue;
|
||||||
|
BKP->OCTLR = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn BKP_WriteBackupRegister
|
||||||
|
*
|
||||||
|
* @brief Writes user data to the specified Data Backup Register.
|
||||||
|
*
|
||||||
|
* @param BKP_DR - specifies the Data Backup Register.
|
||||||
|
* Data - data to write.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void BKP_WriteBackupRegister(uint16_t BKP_DR, uint16_t Data)
|
||||||
|
{
|
||||||
|
__IO uint32_t tmp = 0;
|
||||||
|
|
||||||
|
tmp = (uint32_t)BKP_BASE;
|
||||||
|
tmp += BKP_DR;
|
||||||
|
*(__IO uint32_t *)tmp = Data;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn BKP_ReadBackupRegister
|
||||||
|
*
|
||||||
|
* @brief Reads data from the specified Data Backup Register.
|
||||||
|
*
|
||||||
|
* @param BKP_DR - specifies the Data Backup Register.
|
||||||
|
* This parameter can be BKP_DRx where x=[1, 42].
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
uint16_t BKP_ReadBackupRegister(uint16_t BKP_DR)
|
||||||
|
{
|
||||||
|
__IO uint32_t tmp = 0;
|
||||||
|
|
||||||
|
tmp = (uint32_t)BKP_BASE;
|
||||||
|
tmp += BKP_DR;
|
||||||
|
|
||||||
|
return (*(__IO uint16_t *)tmp);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn BKP_GetFlagStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the Tamper Pin Event flag is set or not.
|
||||||
|
*
|
||||||
|
* @return FlagStatus - SET or RESET.
|
||||||
|
*/
|
||||||
|
FlagStatus BKP_GetFlagStatus(void)
|
||||||
|
{
|
||||||
|
if(BKP->TPCSR & (1 << 8))
|
||||||
|
{
|
||||||
|
return SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return RESET;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn BKP_ClearFlag
|
||||||
|
*
|
||||||
|
* @brief Clears Tamper Pin Event pending flag.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void BKP_ClearFlag(void)
|
||||||
|
{
|
||||||
|
BKP->TPCSR |= BKP_CTE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn BKP_GetITStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the Tamper Pin Interrupt has occurred or not.
|
||||||
|
*
|
||||||
|
* @return ITStatus - SET or RESET.
|
||||||
|
*/
|
||||||
|
ITStatus BKP_GetITStatus(void)
|
||||||
|
{
|
||||||
|
if(BKP->TPCSR & (1 << 9))
|
||||||
|
{
|
||||||
|
return SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return RESET;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn BKP_ClearITPendingBit
|
||||||
|
*
|
||||||
|
* @brief Clears Tamper Pin Interrupt pending bit.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void BKP_ClearITPendingBit(void)
|
||||||
|
{
|
||||||
|
BKP->TPCSR |= BKP_CTI;
|
||||||
|
}
|
||||||
1297
Peripheral/src/ch32v30x_can.c
Normal file
1297
Peripheral/src/ch32v30x_can.c
Normal file
File diff suppressed because it is too large
Load Diff
100
Peripheral/src/ch32v30x_crc.c
Normal file
100
Peripheral/src/ch32v30x_crc.c
Normal file
@@ -0,0 +1,100 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_crc.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file provides all the CRC firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_crc.h"
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn CRC_ResetDR
|
||||||
|
*
|
||||||
|
* @brief Resets the CRC Data register (DR).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void CRC_ResetDR(void)
|
||||||
|
{
|
||||||
|
CRC->CTLR = CRC_CTLR_RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn CRC_CalcCRC
|
||||||
|
*
|
||||||
|
* @brief Computes the 32-bit CRC of a given data word(32-bit).
|
||||||
|
*
|
||||||
|
* @param Data - data word(32-bit) to compute its CRC.
|
||||||
|
*
|
||||||
|
* @return 32-bit CRC.
|
||||||
|
*/
|
||||||
|
uint32_t CRC_CalcCRC(uint32_t Data)
|
||||||
|
{
|
||||||
|
CRC->DATAR = Data;
|
||||||
|
|
||||||
|
return (CRC->DATAR);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn CRC_CalcBlockCRC
|
||||||
|
*
|
||||||
|
* @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
|
||||||
|
*
|
||||||
|
* @param pBuffer - pointer to the buffer containing the data to be computed.
|
||||||
|
* BufferLength - length of the buffer to be computed.
|
||||||
|
*
|
||||||
|
* @return 32-bit CRC.
|
||||||
|
*/
|
||||||
|
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
|
||||||
|
{
|
||||||
|
uint32_t index = 0;
|
||||||
|
|
||||||
|
for(index = 0; index < BufferLength; index++)
|
||||||
|
{
|
||||||
|
CRC->DATAR = pBuffer[index];
|
||||||
|
}
|
||||||
|
|
||||||
|
return (CRC->DATAR);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn CRC_GetCRC
|
||||||
|
*
|
||||||
|
* @brief Returns the current CRC value.
|
||||||
|
*
|
||||||
|
* @return 32-bit CRC.
|
||||||
|
*/
|
||||||
|
uint32_t CRC_GetCRC(void)
|
||||||
|
{
|
||||||
|
return (CRC->DATAR);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn CRC_SetIDRegister
|
||||||
|
*
|
||||||
|
* @brief Stores a 8-bit data in the Independent Data(ID) register.
|
||||||
|
*
|
||||||
|
* @param IDValue - 8-bit value to be stored in the ID register.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void CRC_SetIDRegister(uint8_t IDValue)
|
||||||
|
{
|
||||||
|
CRC->IDATAR = IDValue;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn CRC_GetIDRegister
|
||||||
|
*
|
||||||
|
* @brief Returns the 8-bit data stored in the Independent Data(ID) register.
|
||||||
|
*
|
||||||
|
* @return 8-bit value of the ID register.
|
||||||
|
*/
|
||||||
|
uint8_t CRC_GetIDRegister(void)
|
||||||
|
{
|
||||||
|
return (CRC->IDATAR);
|
||||||
|
}
|
||||||
304
Peripheral/src/ch32v30x_dac.c
Normal file
304
Peripheral/src/ch32v30x_dac.c
Normal file
@@ -0,0 +1,304 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_dac.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file provides all the DAC firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_dac.h"
|
||||||
|
#include "ch32v30x_rcc.h"
|
||||||
|
|
||||||
|
/* CTLR register Mask */
|
||||||
|
#define CTLR_CLEAR_MASK ((uint32_t)0x00000FFE)
|
||||||
|
|
||||||
|
/* DAC Dual Channels SWTR masks */
|
||||||
|
#define DUAL_SWTR_SET ((uint32_t)0x00000003)
|
||||||
|
#define DUAL_SWTR_RESET ((uint32_t)0xFFFFFFFC)
|
||||||
|
|
||||||
|
/* DHR registers offsets */
|
||||||
|
#define DHR12R1_OFFSET ((uint32_t)0x00000008)
|
||||||
|
#define DHR12R2_OFFSET ((uint32_t)0x00000014)
|
||||||
|
#define DHR12RD_OFFSET ((uint32_t)0x00000020)
|
||||||
|
|
||||||
|
/* DOR register offset */
|
||||||
|
#define DOR_OFFSET ((uint32_t)0x0000002C)
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DAC_DeInit
|
||||||
|
*
|
||||||
|
* @brief Deinitializes the DAC peripheral registers to their default reset values.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DAC_DeInit(void)
|
||||||
|
{
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DAC_Init
|
||||||
|
*
|
||||||
|
* @brief Initializes the DAC peripheral according to the specified parameters in
|
||||||
|
* the DAC_InitStruct.
|
||||||
|
*
|
||||||
|
* @param DAC_Channel - the selected DAC channel.
|
||||||
|
* DAC_Channel_1 - DAC Channel1 selected
|
||||||
|
* DAC_Channel_2 - DAC Channel2 selected
|
||||||
|
* DAC_InitStruct - pointer to a DAC_InitTypeDef structure.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef *DAC_InitStruct)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg1 = 0, tmpreg2 = 0;
|
||||||
|
|
||||||
|
tmpreg1 = DAC->CTLR;
|
||||||
|
tmpreg1 &= ~(CTLR_CLEAR_MASK << DAC_Channel);
|
||||||
|
tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
|
||||||
|
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
|
||||||
|
tmpreg1 |= tmpreg2 << DAC_Channel;
|
||||||
|
DAC->CTLR = tmpreg1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DAC_StructInit
|
||||||
|
*
|
||||||
|
* @brief Fills each DAC_InitStruct member with its default value.
|
||||||
|
*
|
||||||
|
* @param DAC_InitStruct - pointer to a DAC_InitTypeDef structure which will be initialized.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DAC_StructInit(DAC_InitTypeDef *DAC_InitStruct)
|
||||||
|
{
|
||||||
|
DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
|
||||||
|
DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
|
||||||
|
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
|
||||||
|
DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DAC_Cmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the specified DAC channel.
|
||||||
|
*
|
||||||
|
* @param DAC_Channel - the selected DAC channel.
|
||||||
|
* DAC_Channel_1 - DAC Channel1 selected
|
||||||
|
* DAC_Channel_2 - DAC Channel2 selected
|
||||||
|
* NewState - new state of the DAC channel(ENABLE or DISABLE).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
DAC->CTLR |= (DAC_EN1 << DAC_Channel);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DAC->CTLR &= ~(DAC_EN1 << DAC_Channel);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DAC_DMACmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the specified DAC channel DMA request.
|
||||||
|
*
|
||||||
|
* @param DAC_Channel - the selected DAC channel.
|
||||||
|
* DAC_Channel_1 - DAC Channel1 selected
|
||||||
|
* DAC_Channel_2 - DAC Channel2 selected
|
||||||
|
* NewState - new state of the DAC channel(ENABLE or DISABLE).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
DAC->CTLR |= (DAC_DMAEN1 << DAC_Channel);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DAC->CTLR &= ~(DAC_DMAEN1 << DAC_Channel);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DAC_SoftwareTriggerCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the selected DAC channel software trigger.
|
||||||
|
*
|
||||||
|
* @param DAC_Channel - the selected DAC channel.
|
||||||
|
* DAC_Channel_1 - DAC Channel1 selected
|
||||||
|
* DAC_Channel_2 - DAC Channel2 selected
|
||||||
|
* NewState - new state of the DAC channel(ENABLE or DISABLE).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
DAC->SWTR |= (uint32_t)DAC_SWTRIG1 << (DAC_Channel >> 4);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DAC->SWTR &= ~((uint32_t)DAC_SWTRIG1 << (DAC_Channel >> 4));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DAC_DualSoftwareTriggerCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the two DAC channel software trigger.
|
||||||
|
*
|
||||||
|
* @param NewState - new state of the DAC channel(ENABLE or DISABLE).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
DAC->SWTR |= DUAL_SWTR_SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DAC->SWTR &= DUAL_SWTR_RESET;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DAC_WaveGenerationCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the selected DAC channel wave generation.
|
||||||
|
*
|
||||||
|
* @param DAC_Channel - the selected DAC channel.
|
||||||
|
* DAC_Channel_1 - DAC Channel1 selected
|
||||||
|
* DAC_Channel_2 - DAC Channel2 selected
|
||||||
|
* DAC_Wave - Specifies the wave type to enable or disable.
|
||||||
|
* DAC_Wave_Noise - noise wave generation
|
||||||
|
* DAC_Wave_Triangle - triangle wave generation
|
||||||
|
* NewState - new state of the DAC channel(ENABLE or DISABLE).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
DAC->CTLR |= DAC_Wave << DAC_Channel;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DAC->CTLR &= ~(DAC_Wave << DAC_Channel);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DAC_SetChannel1Data
|
||||||
|
*
|
||||||
|
* @brief Set the specified data holding register value for DAC channel1.
|
||||||
|
*
|
||||||
|
* @param DAC_Align - Specifies the data alignment for DAC channel1.
|
||||||
|
* DAC_Align_8b_R - 8bit right data alignment selected
|
||||||
|
* DAC_Align_12b_L - 12bit left data alignment selected
|
||||||
|
* DAC_Align_12b_R - 12bit right data alignment selected
|
||||||
|
* Data - Data to be loaded in the selected data holding register.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
|
||||||
|
{
|
||||||
|
__IO uint32_t tmp = 0;
|
||||||
|
|
||||||
|
tmp = (uint32_t)DAC_BASE;
|
||||||
|
tmp += DHR12R1_OFFSET + DAC_Align;
|
||||||
|
|
||||||
|
*(__IO uint32_t *)tmp = Data;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DAC_SetChannel2Data
|
||||||
|
*
|
||||||
|
* @brief Set the specified data holding register value for DAC channel2.
|
||||||
|
*
|
||||||
|
* @param DAC_Align - Specifies the data alignment for DAC channel1.
|
||||||
|
* DAC_Align_8b_R - 8bit right data alignment selected
|
||||||
|
* DAC_Align_12b_L - 12bit left data alignment selected
|
||||||
|
* DAC_Align_12b_R - 12bit right data alignment selected
|
||||||
|
* Data - Data to be loaded in the selected data holding register.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
|
||||||
|
{
|
||||||
|
__IO uint32_t tmp = 0;
|
||||||
|
|
||||||
|
tmp = (uint32_t)DAC_BASE;
|
||||||
|
tmp += DHR12R2_OFFSET + DAC_Align;
|
||||||
|
|
||||||
|
*(__IO uint32_t *)tmp = Data;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DAC_SetDualChannelData
|
||||||
|
*
|
||||||
|
* @brief Set the specified data holding register value for two DAC.
|
||||||
|
*
|
||||||
|
* @param DAC_Align - Specifies the data alignment for DAC channel1.
|
||||||
|
* DAC_Align_8b_R - 8bit right data alignment selected
|
||||||
|
* DAC_Align_12b_L - 12bit left data alignment selected
|
||||||
|
* DAC_Align_12b_R - 12bit right data alignment selected
|
||||||
|
* Data - Data to be loaded in the selected data holding register.
|
||||||
|
* Data1 - Data for DAC Channel1.
|
||||||
|
* Data2 - Data for DAC Channel2
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
|
||||||
|
{
|
||||||
|
uint32_t data = 0, tmp = 0;
|
||||||
|
|
||||||
|
if(DAC_Align == DAC_Align_8b_R)
|
||||||
|
{
|
||||||
|
data = ((uint32_t)Data2 << 8) | Data1;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
data = ((uint32_t)Data2 << 16) | Data1;
|
||||||
|
}
|
||||||
|
|
||||||
|
tmp = (uint32_t)DAC_BASE;
|
||||||
|
tmp += DHR12RD_OFFSET + DAC_Align;
|
||||||
|
|
||||||
|
*(__IO uint32_t *)tmp = data;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DAC_GetDataOutputValue
|
||||||
|
*
|
||||||
|
* @brief Returns the last data output value of the selected DAC channel.
|
||||||
|
*
|
||||||
|
* @param DAC_Channel - the selected DAC channel.
|
||||||
|
* DAC_Channel_1 - DAC Channel1 selected
|
||||||
|
* DAC_Channel_2 - DAC Channel2 selected
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
|
||||||
|
{
|
||||||
|
__IO uint32_t tmp = 0;
|
||||||
|
|
||||||
|
tmp = (uint32_t)DAC_BASE;
|
||||||
|
tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
|
||||||
|
|
||||||
|
return (uint16_t)(*(__IO uint32_t *)tmp);
|
||||||
|
}
|
||||||
129
Peripheral/src/ch32v30x_dbgmcu.c
Normal file
129
Peripheral/src/ch32v30x_dbgmcu.c
Normal file
@@ -0,0 +1,129 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_dbgmcu.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2024/05/28
|
||||||
|
* Description : This file provides all the DBGMCU firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_dbgmcu.h"
|
||||||
|
|
||||||
|
#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF)
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DBGMCU_GetREVID
|
||||||
|
*
|
||||||
|
* @brief Returns the device revision identifier.
|
||||||
|
*
|
||||||
|
* @return Revision identifier.
|
||||||
|
*/
|
||||||
|
uint32_t DBGMCU_GetREVID(void)
|
||||||
|
{
|
||||||
|
return ((*(uint32_t *)0x1FFFF704) & IDCODE_DEVID_MASK);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DBGMCU_GetDEVID
|
||||||
|
*
|
||||||
|
* @brief Returns the device identifier.
|
||||||
|
*
|
||||||
|
* @return Device identifier.
|
||||||
|
*/
|
||||||
|
uint32_t DBGMCU_GetDEVID(void)
|
||||||
|
{
|
||||||
|
return ((*(uint32_t *)0x1FFFF704) >> 16);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __get_DEBUG_CR
|
||||||
|
*
|
||||||
|
* @brief Return the DEBUGE Control Register
|
||||||
|
*
|
||||||
|
* @return DEBUGE Control value
|
||||||
|
*/
|
||||||
|
uint32_t __get_DEBUG_CR(void)
|
||||||
|
{
|
||||||
|
uint32_t result;
|
||||||
|
|
||||||
|
__asm volatile("csrr %0,""0x7C0" : "=r"(result));
|
||||||
|
return (result);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn __set_DEBUG_CR
|
||||||
|
*
|
||||||
|
* @brief Set the DEBUGE Control Register
|
||||||
|
*
|
||||||
|
* @param value - set DEBUGE Control value
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void __set_DEBUG_CR(uint32_t value)
|
||||||
|
{
|
||||||
|
__asm volatile("csrw 0x7C0, %0" : : "r"(value));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DBGMCU_Config
|
||||||
|
*
|
||||||
|
* @brief Configures the specified peripheral and low power mode behavior
|
||||||
|
* when the MCU under Debug mode.
|
||||||
|
*
|
||||||
|
* @param DBGMCU_Periph - specifies the peripheral and low power mode.
|
||||||
|
* DBGMCU_IWDG_STOP - Debug IWDG stopped when Core is halted
|
||||||
|
* DBGMCU_WWDG_STOP - Debug WWDG stopped when Core is halted
|
||||||
|
* DBGMCU_TIM1_STOP - TIM1 counter stopped when Core is halted
|
||||||
|
* DBGMCU_TIM2_STOP - TIM2 counter stopped when Core is halted
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
uint32_t val;
|
||||||
|
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
__set_DEBUG_CR(DBGMCU_Periph);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
val = __get_DEBUG_CR();
|
||||||
|
val &= ~(uint32_t)DBGMCU_Periph;
|
||||||
|
__set_DEBUG_CR(val);
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DBGMCU_GetCHIPID
|
||||||
|
*
|
||||||
|
* @brief Returns the CHIP identifier.
|
||||||
|
*
|
||||||
|
* @return Device identifier.
|
||||||
|
* ChipID List-
|
||||||
|
* CH32V303CBT6-0x303305x4
|
||||||
|
* CH32V303RBT6-0x303205x4
|
||||||
|
* CH32V303RCT6-0x303105x4
|
||||||
|
* CH32V303VCT6-0x303005x4
|
||||||
|
* CH32V305FBP6-0x305205x8
|
||||||
|
* CH32V305RBT6-0x305005x8
|
||||||
|
* CH32V305GBU6-0x305B05x8
|
||||||
|
* CH32V305CCT6-0x305C05x8
|
||||||
|
* CH32V307WCU6-0x307305x8
|
||||||
|
* CH32V307FBP6-0x307205x8
|
||||||
|
* CH32V307RCT6-0x307105x8
|
||||||
|
* CH32V307VCT6-0x307005x8
|
||||||
|
* CH32V317VCT6-0x3170B5X8
|
||||||
|
* CH32V317WCU6-0x3173B5X8
|
||||||
|
* CH32V317TCU6-0x3175B5X8
|
||||||
|
*/
|
||||||
|
uint32_t DBGMCU_GetCHIPID( void )
|
||||||
|
{
|
||||||
|
return( *( uint32_t * )0x1FFFF704 );
|
||||||
|
}
|
||||||
|
|
||||||
692
Peripheral/src/ch32v30x_dma.c
Normal file
692
Peripheral/src/ch32v30x_dma.c
Normal file
@@ -0,0 +1,692 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_dma.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file provides all the DMA firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_dma.h"
|
||||||
|
#include "ch32v30x_rcc.h"
|
||||||
|
|
||||||
|
/* DMA1 Channelx interrupt pending bit masks */
|
||||||
|
#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
|
||||||
|
#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
|
||||||
|
#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
|
||||||
|
#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
|
||||||
|
#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
|
||||||
|
#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
|
||||||
|
#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
|
||||||
|
|
||||||
|
/* DMA2 Channelx interrupt pending bit masks */
|
||||||
|
#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
|
||||||
|
#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
|
||||||
|
#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
|
||||||
|
#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
|
||||||
|
#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
|
||||||
|
#define DMA2_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
|
||||||
|
#define DMA2_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
|
||||||
|
#define DMA2_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8))
|
||||||
|
#define DMA2_Channel9_IT_Mask ((uint32_t)(DMA_GIF9 | DMA_TCIF9 | DMA_HTIF9 | DMA_TEIF9))
|
||||||
|
#define DMA2_Channel10_IT_Mask ((uint32_t)(DMA_GIF10 | DMA_TCIF10 | DMA_HTIF10 | DMA_TEIF10))
|
||||||
|
#define DMA2_Channel11_IT_Mask ((uint32_t)(DMA_GIF11 | DMA_TCIF11 | DMA_HTIF11 | DMA_TEIF11))
|
||||||
|
|
||||||
|
/* DMA2 FLAG mask */
|
||||||
|
#define FLAG_Mask ((uint32_t)0x10000000)
|
||||||
|
#define DMA2_EXTEN_FLAG_Mask ((uint32_t)0x20000000)
|
||||||
|
|
||||||
|
/* DMA registers Masks */
|
||||||
|
#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F)
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DMA_DeInit
|
||||||
|
*
|
||||||
|
* @brief Deinitializes the DMAy Channelx registers to their default
|
||||||
|
* reset values.
|
||||||
|
*
|
||||||
|
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||||
|
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx)
|
||||||
|
{
|
||||||
|
DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
|
||||||
|
DMAy_Channelx->CFGR = 0;
|
||||||
|
DMAy_Channelx->CNTR = 0;
|
||||||
|
DMAy_Channelx->PADDR = 0;
|
||||||
|
DMAy_Channelx->MADDR = 0;
|
||||||
|
if(DMAy_Channelx == DMA1_Channel1)
|
||||||
|
{
|
||||||
|
DMA1->INTFCR |= DMA1_Channel1_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA1_Channel2)
|
||||||
|
{
|
||||||
|
DMA1->INTFCR |= DMA1_Channel2_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA1_Channel3)
|
||||||
|
{
|
||||||
|
DMA1->INTFCR |= DMA1_Channel3_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA1_Channel4)
|
||||||
|
{
|
||||||
|
DMA1->INTFCR |= DMA1_Channel4_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA1_Channel5)
|
||||||
|
{
|
||||||
|
DMA1->INTFCR |= DMA1_Channel5_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA1_Channel6)
|
||||||
|
{
|
||||||
|
DMA1->INTFCR |= DMA1_Channel6_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA1_Channel7)
|
||||||
|
{
|
||||||
|
DMA1->INTFCR |= DMA1_Channel7_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA2_Channel1)
|
||||||
|
{
|
||||||
|
DMA2->INTFCR |= DMA2_Channel1_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA2_Channel2)
|
||||||
|
{
|
||||||
|
DMA2->INTFCR |= DMA2_Channel2_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA2_Channel3)
|
||||||
|
{
|
||||||
|
DMA2->INTFCR |= DMA2_Channel3_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA2_Channel4)
|
||||||
|
{
|
||||||
|
DMA2->INTFCR |= DMA2_Channel4_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA2_Channel5)
|
||||||
|
{
|
||||||
|
DMA2->INTFCR |= DMA2_Channel5_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA2_Channel6)
|
||||||
|
{
|
||||||
|
DMA2->INTFCR |= DMA2_Channel6_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA2_Channel7)
|
||||||
|
{
|
||||||
|
DMA2->INTFCR |= DMA2_Channel7_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA2_Channel8)
|
||||||
|
{
|
||||||
|
DMA2_EXTEN->INTFCR |= DMA2_Channel8_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA2_Channel9)
|
||||||
|
{
|
||||||
|
DMA2_EXTEN->INTFCR |= DMA2_Channel9_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA2_Channel10)
|
||||||
|
{
|
||||||
|
DMA2_EXTEN->INTFCR |= DMA2_Channel10_IT_Mask;
|
||||||
|
}
|
||||||
|
else if(DMAy_Channelx == DMA2_Channel11)
|
||||||
|
{
|
||||||
|
DMA2_EXTEN->INTFCR |= DMA2_Channel11_IT_Mask;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DMA_Init
|
||||||
|
*
|
||||||
|
* @brief Initializes the DMAy Channelx according to the specified
|
||||||
|
* parameters in the DMA_InitStruct.
|
||||||
|
*
|
||||||
|
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||||
|
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
|
||||||
|
* DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
|
||||||
|
* contains the configuration information for the specified DMA Channel.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
|
||||||
|
tmpreg = DMAy_Channelx->CFGR;
|
||||||
|
tmpreg &= CFGR_CLEAR_Mask;
|
||||||
|
tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
|
||||||
|
DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
|
||||||
|
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
|
||||||
|
DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
|
||||||
|
|
||||||
|
DMAy_Channelx->CFGR = tmpreg;
|
||||||
|
DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize;
|
||||||
|
DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr;
|
||||||
|
DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DMA_StructInit
|
||||||
|
*
|
||||||
|
* @brief Fills each DMA_InitStruct member with its default value.
|
||||||
|
*
|
||||||
|
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||||
|
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
|
||||||
|
* DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
|
||||||
|
* contains the configuration information for the specified DMA Channel.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct)
|
||||||
|
{
|
||||||
|
DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
|
||||||
|
DMA_InitStruct->DMA_MemoryBaseAddr = 0;
|
||||||
|
DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
|
||||||
|
DMA_InitStruct->DMA_BufferSize = 0;
|
||||||
|
DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
||||||
|
DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
|
||||||
|
DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
||||||
|
DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
|
||||||
|
DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
|
||||||
|
DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
|
||||||
|
DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DMA_Cmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the specified DMAy Channelx.
|
||||||
|
*
|
||||||
|
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||||
|
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
|
||||||
|
* NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
DMAy_Channelx->CFGR |= DMA_CFGR1_EN;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DMA_ITConfig
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the specified DMAy Channelx interrupts.
|
||||||
|
*
|
||||||
|
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||||
|
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
|
||||||
|
* DMA_IT - specifies the DMA interrupts sources to be enabled
|
||||||
|
* or disabled.
|
||||||
|
* DMA_IT_TC - Transfer complete interrupt mask
|
||||||
|
* DMA_IT_HT - Half transfer interrupt mask
|
||||||
|
* DMA_IT_TE - Transfer error interrupt mask
|
||||||
|
* NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
DMAy_Channelx->CFGR |= DMA_IT;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DMAy_Channelx->CFGR &= ~DMA_IT;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DMA_SetCurrDataCounter
|
||||||
|
*
|
||||||
|
* @brief Sets the number of data units in the current DMAy Channelx transfer.
|
||||||
|
*
|
||||||
|
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||||
|
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
|
||||||
|
* DataNumber - The number of data units in the current DMAy Channelx
|
||||||
|
* transfer.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber)
|
||||||
|
{
|
||||||
|
DMAy_Channelx->CNTR = DataNumber;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DMA_GetCurrDataCounter
|
||||||
|
*
|
||||||
|
* @brief Returns the number of remaining data units in the current
|
||||||
|
* DMAy Channelx transfer.
|
||||||
|
*
|
||||||
|
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||||
|
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
|
||||||
|
*
|
||||||
|
* @return DataNumber - The number of remaining data units in the current
|
||||||
|
* DMAy Channelx transfer.
|
||||||
|
*/
|
||||||
|
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx)
|
||||||
|
{
|
||||||
|
return ((uint16_t)(DMAy_Channelx->CNTR));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DMA_GetFlagStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified DMAy Channelx flag is set or not.
|
||||||
|
*
|
||||||
|
* @param DMAy_FLAG - specifies the flag to check.
|
||||||
|
* DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
|
||||||
|
* DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
|
||||||
|
* DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
|
||||||
|
* DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
|
||||||
|
* DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
|
||||||
|
* DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
|
||||||
|
* DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
|
||||||
|
* DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
|
||||||
|
* DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
|
||||||
|
* DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
|
||||||
|
* DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
|
||||||
|
* DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
|
||||||
|
* DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
|
||||||
|
* DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL1 - DMA2 Channel1 global flag.
|
||||||
|
* DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL2 - DMA2 Channel2 global flag.
|
||||||
|
* DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL3 - DMA2 Channel3 global flag.
|
||||||
|
* DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL4 - DMA2 Channel4 global flag.
|
||||||
|
* DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL5 - DMA2 Channel5 global flag.
|
||||||
|
* DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL6 - DMA2 Channel6 global flag.
|
||||||
|
* DMA2_FLAG_TC6 - DMA2 Channel6 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT6 - DMA2 Channel6 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE6 - DMA2 Channel6 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL7 - DMA2 Channel7 global flag.
|
||||||
|
* DMA2_FLAG_TC7 - DMA2 Channel7 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT7 - DMA2 Channel7 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE7 - DMA2 Channel7 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL8 - DMA2 Channel8 global flag.
|
||||||
|
* DMA2_FLAG_TC8 - DMA2 Channel8 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT8 - DMA2 Channel8 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE8 - DMA2 Channel8 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL9 - DMA2 Channel9 global flag.
|
||||||
|
* DMA2_FLAG_TC9 - DMA2 Channel9 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT9 - DMA2 Channel9 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE9 - DMA2 Channel9 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL10 - DMA2 Channel10 global flag.
|
||||||
|
* DMA2_FLAG_TC10 - DMA2 Channel10 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT10 - DMA2 Channel10 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE10 - DMA2 Channel10 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL11 - DMA2 Channel11 global flag.
|
||||||
|
* DMA2_FLAG_TC11 - DMA2 Channel11 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT11 - DMA2 Channel11 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE11 - DMA2 Channel11 transfer error flag.
|
||||||
|
*
|
||||||
|
* @return The new state of DMAy_FLAG (SET or RESET).
|
||||||
|
*/
|
||||||
|
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
|
||||||
|
if((DMAy_FLAG & FLAG_Mask) == FLAG_Mask)
|
||||||
|
{
|
||||||
|
tmpreg = DMA2->INTFR;
|
||||||
|
}
|
||||||
|
else if((DMAy_FLAG & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask)
|
||||||
|
{
|
||||||
|
tmpreg = DMA2_EXTEN->INTFR;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
tmpreg = DMA1->INTFR;
|
||||||
|
}
|
||||||
|
|
||||||
|
if((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DMA_ClearFlag
|
||||||
|
*
|
||||||
|
* @brief Clears the DMAy Channelx's pending flags.
|
||||||
|
*
|
||||||
|
* @param DMAy_FLAG - specifies the flag to check.
|
||||||
|
* DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
|
||||||
|
* DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
|
||||||
|
* DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
|
||||||
|
* DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
|
||||||
|
* DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
|
||||||
|
* DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
|
||||||
|
* DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
|
||||||
|
* DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
|
||||||
|
* DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
|
||||||
|
* DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
|
||||||
|
* DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
|
||||||
|
* DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
|
||||||
|
* DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
|
||||||
|
* DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
|
||||||
|
* DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
|
||||||
|
* DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL1 - DMA2 Channel1 global flag.
|
||||||
|
* DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL2 - DMA2 Channel2 global flag.
|
||||||
|
* DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL3 - DMA2 Channel3 global flag.
|
||||||
|
* DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL4 - DMA2 Channel4 global flag.
|
||||||
|
* DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL5 - DMA2 Channel5 global flag.
|
||||||
|
* DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL6 - DMA2 Channel6 global flag.
|
||||||
|
* DMA2_FLAG_TC6 - DMA2 Channel6 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT6 - DMA2 Channel6 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE6 - DMA2 Channel6 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL7 - DMA2 Channel7 global flag.
|
||||||
|
* DMA2_FLAG_TC7 - DMA2 Channel7 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT7 - DMA2 Channel7 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE7 - DMA2 Channel7 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL8 - DMA2 Channel8 global flag.
|
||||||
|
* DMA2_FLAG_TC8 - DMA2 Channel8 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT8 - DMA2 Channel8 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE8 - DMA2 Channel8 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL9 - DMA2 Channel9 global flag.
|
||||||
|
* DMA2_FLAG_TC9 - DMA2 Channel9 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT9 - DMA2 Channel9 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE9 - DMA2 Channel9 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL10 - DMA2 Channel10 global flag.
|
||||||
|
* DMA2_FLAG_TC10 - DMA2 Channel10 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT10 - DMA2 Channel10 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE10 - DMA2 Channel10 transfer error flag.
|
||||||
|
* DMA2_FLAG_GL11 - DMA2 Channel11 global flag.
|
||||||
|
* DMA2_FLAG_TC11 - DMA2 Channel11 transfer complete flag.
|
||||||
|
* DMA2_FLAG_HT11 - DMA2 Channel11 half transfer flag.
|
||||||
|
* DMA2_FLAG_TE11 - DMA2 Channel11 transfer error flag.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DMA_ClearFlag(uint32_t DMAy_FLAG)
|
||||||
|
{
|
||||||
|
if((DMAy_FLAG & FLAG_Mask) == FLAG_Mask)
|
||||||
|
{
|
||||||
|
DMA2->INTFCR = DMAy_FLAG;
|
||||||
|
}
|
||||||
|
else if((DMAy_FLAG & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask)
|
||||||
|
{
|
||||||
|
DMA2_EXTEN->INTFCR = DMAy_FLAG;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DMA1->INTFCR = DMAy_FLAG;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DMA_GetITStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified DMAy Channelx interrupt has
|
||||||
|
* occurred or not.
|
||||||
|
*
|
||||||
|
* @param DMAy_IT - specifies the DMAy interrupt source to check.
|
||||||
|
* DMA1_IT_GL1 - DMA1 Channel1 global flag.
|
||||||
|
* DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
|
||||||
|
* DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
|
||||||
|
* DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
|
||||||
|
* DMA1_IT_GL2 - DMA1 Channel2 global flag.
|
||||||
|
* DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
|
||||||
|
* DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
|
||||||
|
* DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
|
||||||
|
* DMA1_IT_GL3 - DMA1 Channel3 global flag.
|
||||||
|
* DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
|
||||||
|
* DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
|
||||||
|
* DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
|
||||||
|
* DMA1_IT_GL4 - DMA1 Channel4 global flag.
|
||||||
|
* DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
|
||||||
|
* DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
|
||||||
|
* DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
|
||||||
|
* DMA1_IT_GL5 - DMA1 Channel5 global flag.
|
||||||
|
* DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
|
||||||
|
* DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
|
||||||
|
* DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
|
||||||
|
* DMA1_IT_GL6 - DMA1 Channel6 global flag.
|
||||||
|
* DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
|
||||||
|
* DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
|
||||||
|
* DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
|
||||||
|
* DMA1_IT_GL7 - DMA1 Channel7 global flag.
|
||||||
|
* DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
|
||||||
|
* DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
|
||||||
|
* DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
|
||||||
|
* DMA2_IT_GL1 - DMA2 Channel1 global flag.
|
||||||
|
* DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag.
|
||||||
|
* DMA2_IT_HT1 - DMA2 Channel1 half transfer flag.
|
||||||
|
* DMA2_IT_TE1 - DMA2 Channel1 transfer error flag.
|
||||||
|
* DMA2_IT_GL2 - DMA2 Channel2 global flag.
|
||||||
|
* DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag.
|
||||||
|
* DMA2_IT_HT2 - DMA2 Channel2 half transfer flag.
|
||||||
|
* DMA2_IT_TE2 - DMA2 Channel2 transfer error flag.
|
||||||
|
* DMA2_IT_GL3 - DMA2 Channel3 global flag.
|
||||||
|
* DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag.
|
||||||
|
* DMA2_IT_HT3 - DMA2 Channel3 half transfer flag.
|
||||||
|
* DMA2_IT_TE3 - DMA2 Channel3 transfer error flag.
|
||||||
|
* DMA2_IT_GL4 - DMA2 Channel4 global flag.
|
||||||
|
* DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag.
|
||||||
|
* DMA2_IT_HT4 - DMA2 Channel4 half transfer flag.
|
||||||
|
* DMA2_IT_TE4 - DMA2 Channel4 transfer error flag.
|
||||||
|
* DMA2_IT_GL5 - DMA2 Channel5 global flag.
|
||||||
|
* DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag.
|
||||||
|
* DMA2_IT_HT5 - DMA2 Channel5 half transfer flag.
|
||||||
|
* DMA2_IT_TE5 - DMA2 Channel5 transfer error flag.
|
||||||
|
* DMA2_IT_GL6 - DMA2 Channel6 global flag.
|
||||||
|
* DMA2_IT_TC6 - DMA2 Channel6 transfer complete flag.
|
||||||
|
* DMA2_IT_HT6 - DMA2 Channel6 half transfer flag.
|
||||||
|
* DMA2_IT_TE6 - DMA2 Channel6 transfer error flag.
|
||||||
|
* DMA2_IT_GL7 - DMA2 Channel7 global flag.
|
||||||
|
* DMA2_IT_TC7 - DMA2 Channel7 transfer complete flag.
|
||||||
|
* DMA2_IT_HT7 - DMA2 Channel7 half transfer flag.
|
||||||
|
* DMA2_IT_TE7 - DMA2 Channel7 transfer error flag.
|
||||||
|
* DMA2_IT_GL8 - DMA2 Channel8 global flag.
|
||||||
|
* DMA2_IT_TC8 - DMA2 Channel8 transfer complete flag.
|
||||||
|
* DMA2_IT_HT8 - DMA2 Channel8 half transfer flag.
|
||||||
|
* DMA2_IT_TE8 - DMA2 Channel8 transfer error flag.
|
||||||
|
* DMA2_IT_GL9 - DMA2 Channel9 global flag.
|
||||||
|
* DMA2_IT_TC9 - DMA2 Channel9 transfer complete flag.
|
||||||
|
* DMA2_IT_HT9 - DMA2 Channel9 half transfer flag.
|
||||||
|
* DMA2_IT_TE9 - DMA2 Channel9 transfer error flag.
|
||||||
|
* DMA2_IT_GL10 - DMA2 Channel10 global flag.
|
||||||
|
* DMA2_IT_TC10 - DMA2 Channel10 transfer complete flag.
|
||||||
|
* DMA2_IT_HT10 - DMA2 Channel10 half transfer flag.
|
||||||
|
* DMA2_IT_TE10 - DMA2 Channel10 transfer error flag.
|
||||||
|
* DMA2_IT_GL11 - DMA2 Channel11 global flag.
|
||||||
|
* DMA2_IT_TC11 - DMA2 Channel11 transfer complete flag.
|
||||||
|
* DMA2_IT_HT11 - DMA2 Channel11 half transfer flag.
|
||||||
|
* DMA2_IT_TE11 - DMA2 Channel11 transfer error flag.
|
||||||
|
*
|
||||||
|
* @return The new state of DMAy_IT (SET or RESET).
|
||||||
|
*/
|
||||||
|
ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
|
||||||
|
{
|
||||||
|
ITStatus bitstatus = RESET;
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
|
||||||
|
if((DMAy_IT & FLAG_Mask) == FLAG_Mask)
|
||||||
|
{
|
||||||
|
tmpreg = DMA2->INTFR;
|
||||||
|
}
|
||||||
|
else if((DMAy_IT & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask)
|
||||||
|
{
|
||||||
|
tmpreg = DMA2_EXTEN->INTFR;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
tmpreg = DMA1->INTFR;
|
||||||
|
}
|
||||||
|
|
||||||
|
if((tmpreg & DMAy_IT) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DMA_ClearITPendingBit
|
||||||
|
*
|
||||||
|
* @brief Clears the DMAy Channelx's interrupt pending bits.
|
||||||
|
*
|
||||||
|
* @param DMAy_IT - specifies the DMAy interrupt source to check.
|
||||||
|
* DMA1_IT_GL1 - DMA1 Channel1 global flag.
|
||||||
|
* DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
|
||||||
|
* DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
|
||||||
|
* DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
|
||||||
|
* DMA1_IT_GL2 - DMA1 Channel2 global flag.
|
||||||
|
* DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
|
||||||
|
* DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
|
||||||
|
* DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
|
||||||
|
* DMA1_IT_GL3 - DMA1 Channel3 global flag.
|
||||||
|
* DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
|
||||||
|
* DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
|
||||||
|
* DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
|
||||||
|
* DMA1_IT_GL4 - DMA1 Channel4 global flag.
|
||||||
|
* DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
|
||||||
|
* DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
|
||||||
|
* DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
|
||||||
|
* DMA1_IT_GL5 - DMA1 Channel5 global flag.
|
||||||
|
* DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
|
||||||
|
* DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
|
||||||
|
* DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
|
||||||
|
* DMA1_IT_GL6 - DMA1 Channel6 global flag.
|
||||||
|
* DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
|
||||||
|
* DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
|
||||||
|
* DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
|
||||||
|
* DMA1_IT_GL7 - DMA1 Channel7 global flag.
|
||||||
|
* DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
|
||||||
|
* DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
|
||||||
|
* DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
|
||||||
|
* DMA2_IT_GL1 - DMA2 Channel1 global flag.
|
||||||
|
* DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag.
|
||||||
|
* DMA2_IT_HT1 - DMA2 Channel1 half transfer flag.
|
||||||
|
* DMA2_IT_TE1 - DMA2 Channel1 transfer error flag.
|
||||||
|
* DMA2_IT_GL2 - DMA2 Channel2 global flag.
|
||||||
|
* DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag.
|
||||||
|
* DMA2_IT_HT2 - DMA2 Channel2 half transfer flag.
|
||||||
|
* DMA2_IT_TE2 - DMA2 Channel2 transfer error flag.
|
||||||
|
* DMA2_IT_GL3 - DMA2 Channel3 global flag.
|
||||||
|
* DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag.
|
||||||
|
* DMA2_IT_HT3 - DMA2 Channel3 half transfer flag.
|
||||||
|
* DMA2_IT_TE3 - DMA2 Channel3 transfer error flag.
|
||||||
|
* DMA2_IT_GL4 - DMA2 Channel4 global flag.
|
||||||
|
* DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag.
|
||||||
|
* DMA2_IT_HT4 - DMA2 Channel4 half transfer flag.
|
||||||
|
* DMA2_IT_TE4 - DMA2 Channel4 transfer error flag.
|
||||||
|
* DMA2_IT_GL5 - DMA2 Channel5 global flag.
|
||||||
|
* DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag.
|
||||||
|
* DMA2_IT_HT5 - DMA2 Channel5 half transfer flag.
|
||||||
|
* DMA2_IT_TE5 - DMA2 Channel5 transfer error flag.
|
||||||
|
* DMA2_IT_GL6 - DMA2 Channel6 global flag.
|
||||||
|
* DMA2_IT_TC6 - DMA2 Channel6 transfer complete flag.
|
||||||
|
* DMA2_IT_HT6 - DMA2 Channel6 half transfer flag.
|
||||||
|
* DMA2_IT_TE6 - DMA2 Channel6 transfer error flag.
|
||||||
|
* DMA2_IT_GL7 - DMA2 Channel7 global flag.
|
||||||
|
* DMA2_IT_TC7 - DMA2 Channel7 transfer complete flag.
|
||||||
|
* DMA2_IT_HT7 - DMA2 Channel7 half transfer flag.
|
||||||
|
* DMA2_IT_TE7 - DMA2 Channel7 transfer error flag.
|
||||||
|
* DMA2_IT_GL8 - DMA2 Channel8 global flag.
|
||||||
|
* DMA2_IT_TC8 - DMA2 Channel8 transfer complete flag.
|
||||||
|
* DMA2_IT_HT8 - DMA2 Channel8 half transfer flag.
|
||||||
|
* DMA2_IT_TE8 - DMA2 Channel8 transfer error flag.
|
||||||
|
* DMA2_IT_GL9 - DMA2 Channel9 global flag.
|
||||||
|
* DMA2_IT_TC9 - DMA2 Channel9 transfer complete flag.
|
||||||
|
* DMA2_IT_HT9 - DMA2 Channel9 half transfer flag.
|
||||||
|
* DMA2_IT_TE9 - DMA2 Channel9 transfer error flag.
|
||||||
|
* DMA2_IT_GL10 - DMA2 Channel10 global flag.
|
||||||
|
* DMA2_IT_TC10 - DMA2 Channel10 transfer complete flag.
|
||||||
|
* DMA2_IT_HT10 - DMA2 Channel10 half transfer flag.
|
||||||
|
* DMA2_IT_TE10 - DMA2 Channel10 transfer error flag.
|
||||||
|
* DMA2_IT_GL11 - DMA2 Channel11 global flag.
|
||||||
|
* DMA2_IT_TC11 - DMA2 Channel11 transfer complete flag.
|
||||||
|
* DMA2_IT_HT11 - DMA2 Channel11 half transfer flag.
|
||||||
|
* DMA2_IT_TE11 - DMA2 Channel11 transfer error flag.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DMA_ClearITPendingBit(uint32_t DMAy_IT)
|
||||||
|
{
|
||||||
|
if((DMAy_IT & FLAG_Mask) == FLAG_Mask)
|
||||||
|
{
|
||||||
|
DMA2->INTFCR = DMAy_IT;
|
||||||
|
}
|
||||||
|
else if((DMAy_IT & DMA2_EXTEN_FLAG_Mask) == DMA2_EXTEN_FLAG_Mask)
|
||||||
|
{
|
||||||
|
DMA2_EXTEN->INTFCR = DMAy_IT;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DMA1->INTFCR = DMAy_IT;
|
||||||
|
}
|
||||||
|
}
|
||||||
135
Peripheral/src/ch32v30x_dvp.c
Normal file
135
Peripheral/src/ch32v30x_dvp.c
Normal file
@@ -0,0 +1,135 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_dvp.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file provides all the DVP firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_dvp.h"
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DVP_INTCfg
|
||||||
|
*
|
||||||
|
* @brief DVP interrupt configuration
|
||||||
|
*
|
||||||
|
* @param s - interrupt enable
|
||||||
|
* ENABLE
|
||||||
|
* DISABLE
|
||||||
|
* i - interrupt type
|
||||||
|
* RB_DVP_IE_STP_FRM
|
||||||
|
* RB_DVP_IE_FIFO_OV
|
||||||
|
* RB_DVP_IE_FRM_DONE
|
||||||
|
* RB_DVP_IE_ROW_DONE
|
||||||
|
* RB_DVP_IE_STR_FRM
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DVP_INTCfg(uint8_t s, uint8_t i)
|
||||||
|
{
|
||||||
|
if(s)
|
||||||
|
{
|
||||||
|
DVP->IER |= i;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DVP->IER &= ~i;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DVP_Mode
|
||||||
|
*
|
||||||
|
* @brief DVP mode
|
||||||
|
*
|
||||||
|
* @param s - data bit width
|
||||||
|
* RB_DVP_D8_MOD
|
||||||
|
* RB_DVP_D10_MOD
|
||||||
|
* RB_DVP_D12_MOD
|
||||||
|
* i - interrupt type
|
||||||
|
* Video_Mode
|
||||||
|
* JPEG_Mode
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DVP_Mode(uint8_t s, DVP_Data_ModeTypeDef i)
|
||||||
|
{
|
||||||
|
DVP->CR0 &= ~RB_DVP_MSK_DAT_MOD;
|
||||||
|
|
||||||
|
if(s)
|
||||||
|
{
|
||||||
|
DVP->CR0 |= s;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DVP->CR0 &= ~(3 << 4);
|
||||||
|
}
|
||||||
|
|
||||||
|
if(i)
|
||||||
|
{
|
||||||
|
DVP->CR0 |= RB_DVP_JPEG;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
DVP->CR0 &= ~RB_DVP_JPEG;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn DVP_Cfg
|
||||||
|
*
|
||||||
|
* @brief DVP configuration
|
||||||
|
*
|
||||||
|
* @param s - DMA enable control
|
||||||
|
* DVP_DMA_Enable
|
||||||
|
* DVP_DMA_Disable
|
||||||
|
* i - DVP all clear
|
||||||
|
* DVP_FLAG_FIFO_RESET_Enable
|
||||||
|
* DVP_FLAG_FIFO_RESET_Disable
|
||||||
|
* j - receive reset enable
|
||||||
|
* DVP_RX_RESET_Enable
|
||||||
|
* DVP_RX_RESET_Disable
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void DVP_Cfg(DVP_DMATypeDef s, DVP_FLAG_FIFO_RESETTypeDef i, DVP_RX_RESETTypeDef j)
|
||||||
|
{
|
||||||
|
switch(s)
|
||||||
|
{
|
||||||
|
case DVP_DMA_Enable:
|
||||||
|
DVP->CR1 |= RB_DVP_DMA_EN;
|
||||||
|
break;
|
||||||
|
case DVP_DMA_Disable:
|
||||||
|
DVP->CR1 &= ~RB_DVP_DMA_EN;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
switch(i)
|
||||||
|
{
|
||||||
|
case DVP_RX_RESET_Enable:
|
||||||
|
DVP->CR1 |= RB_DVP_ALL_CLR;
|
||||||
|
break;
|
||||||
|
case DVP_RX_RESET_Disable:
|
||||||
|
DVP->CR1 &= ~RB_DVP_ALL_CLR;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
switch(j)
|
||||||
|
{
|
||||||
|
case DVP_RX_RESET_Enable:
|
||||||
|
DVP->CR1 |= RB_DVP_RCV_CLR;
|
||||||
|
break;
|
||||||
|
case DVP_RX_RESET_Disable:
|
||||||
|
DVP->CR1 &= ~RB_DVP_RCV_CLR;
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
2524
Peripheral/src/ch32v30x_eth.c
Normal file
2524
Peripheral/src/ch32v30x_eth.c
Normal file
File diff suppressed because it is too large
Load Diff
182
Peripheral/src/ch32v30x_exti.c
Normal file
182
Peripheral/src/ch32v30x_exti.c
Normal file
@@ -0,0 +1,182 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_exti.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file provides all the EXTI firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_exti.h"
|
||||||
|
|
||||||
|
/* No interrupt selected */
|
||||||
|
#define EXTI_LINENONE ((uint32_t)0x00000)
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn EXTI_DeInit
|
||||||
|
*
|
||||||
|
* @brief Deinitializes the EXTI peripheral registers to their default
|
||||||
|
* reset values.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void EXTI_DeInit(void)
|
||||||
|
{
|
||||||
|
EXTI->INTENR = 0x00000000;
|
||||||
|
EXTI->EVENR = 0x00000000;
|
||||||
|
EXTI->RTENR = 0x00000000;
|
||||||
|
EXTI->FTENR = 0x00000000;
|
||||||
|
EXTI->INTFR = 0x000FFFFF;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn EXTI_Init
|
||||||
|
*
|
||||||
|
* @brief Initializes the EXTI peripheral according to the specified
|
||||||
|
* parameters in the EXTI_InitStruct.
|
||||||
|
*
|
||||||
|
* @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct)
|
||||||
|
{
|
||||||
|
uint32_t tmp = 0;
|
||||||
|
|
||||||
|
tmp = (uint32_t)EXTI_BASE;
|
||||||
|
if(EXTI_InitStruct->EXTI_LineCmd != DISABLE)
|
||||||
|
{
|
||||||
|
EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line;
|
||||||
|
EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line;
|
||||||
|
tmp += EXTI_InitStruct->EXTI_Mode;
|
||||||
|
*(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
|
||||||
|
EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line;
|
||||||
|
EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line;
|
||||||
|
if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
|
||||||
|
{
|
||||||
|
EXTI->RTENR |= EXTI_InitStruct->EXTI_Line;
|
||||||
|
EXTI->FTENR |= EXTI_InitStruct->EXTI_Line;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
tmp = (uint32_t)EXTI_BASE;
|
||||||
|
tmp += EXTI_InitStruct->EXTI_Trigger;
|
||||||
|
*(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
tmp += EXTI_InitStruct->EXTI_Mode;
|
||||||
|
*(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn EXTI_StructInit
|
||||||
|
*
|
||||||
|
* @brief Fills each EXTI_InitStruct member with its reset value.
|
||||||
|
*
|
||||||
|
* @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct)
|
||||||
|
{
|
||||||
|
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
|
||||||
|
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
|
||||||
|
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
|
||||||
|
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn EXTI_GenerateSWInterrupt
|
||||||
|
*
|
||||||
|
* @brief Generates a Software interrupt.
|
||||||
|
*
|
||||||
|
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
|
||||||
|
*
|
||||||
|
* @return none.
|
||||||
|
*/
|
||||||
|
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
|
||||||
|
{
|
||||||
|
EXTI->SWIEVR |= EXTI_Line;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn EXTI_GetFlagStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified EXTI line flag is set or not.
|
||||||
|
*
|
||||||
|
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
|
||||||
|
*
|
||||||
|
* @return The new state of EXTI_Line (SET or RESET).
|
||||||
|
*/
|
||||||
|
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn EXTI_ClearFlag
|
||||||
|
*
|
||||||
|
* @brief Clears the EXTI's line pending flags.
|
||||||
|
*
|
||||||
|
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void EXTI_ClearFlag(uint32_t EXTI_Line)
|
||||||
|
{
|
||||||
|
EXTI->INTFR = EXTI_Line;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn EXTI_GetITStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified EXTI line is asserted or not.
|
||||||
|
*
|
||||||
|
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
|
||||||
|
*
|
||||||
|
* @return The new state of EXTI_Line (SET or RESET).
|
||||||
|
*/
|
||||||
|
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
|
||||||
|
{
|
||||||
|
ITStatus bitstatus = RESET;
|
||||||
|
uint32_t enablestatus = 0;
|
||||||
|
|
||||||
|
enablestatus = EXTI->INTENR & EXTI_Line;
|
||||||
|
if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn EXTI_ClearITPendingBit
|
||||||
|
*
|
||||||
|
* @brief Clears the EXTI's line pending bits.
|
||||||
|
*
|
||||||
|
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
|
||||||
|
{
|
||||||
|
EXTI->INTFR = EXTI_Line;
|
||||||
|
}
|
||||||
1226
Peripheral/src/ch32v30x_flash.c
Normal file
1226
Peripheral/src/ch32v30x_flash.c
Normal file
File diff suppressed because it is too large
Load Diff
378
Peripheral/src/ch32v30x_fsmc.c
Normal file
378
Peripheral/src/ch32v30x_fsmc.c
Normal file
@@ -0,0 +1,378 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_fsmc.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.1
|
||||||
|
* Date : 2025/04/06
|
||||||
|
* Description : This file provides all the FSMC firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_fsmc.h"
|
||||||
|
#include "ch32v30x_rcc.h"
|
||||||
|
|
||||||
|
/* FSMC BCRx Mask */
|
||||||
|
#define BCR_MBKEN_Set ((uint32_t)0x00000001)
|
||||||
|
#define BCR_MBKEN_Reset ((uint32_t)0x000FFFFE)
|
||||||
|
#define BCR_FACCEN_Set ((uint32_t)0x00000040)
|
||||||
|
|
||||||
|
/* FSMC PCRx Mask */
|
||||||
|
#define PCR_PBKEN_Set ((uint32_t)0x00000004)
|
||||||
|
#define PCR_PBKEN_Reset ((uint32_t)0x000FFFFB)
|
||||||
|
#define PCR_ECCEN_Set ((uint32_t)0x00000040)
|
||||||
|
#define PCR_ECCEN_Reset ((uint32_t)0x000FFFBF)
|
||||||
|
#define PCR_MemoryType_NAND ((uint32_t)0x00000008)
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn FSMC_NORSRAMDeInit
|
||||||
|
*
|
||||||
|
* @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
|
||||||
|
* reset values.
|
||||||
|
*
|
||||||
|
* @param FSMC_Bank-
|
||||||
|
* FSMC_Bank1_NORSRAM1 - FSMC Bank1 NOR/SRAM1.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
|
||||||
|
{
|
||||||
|
if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
|
||||||
|
{
|
||||||
|
FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
|
||||||
|
}
|
||||||
|
FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
|
||||||
|
FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn FSMC_NANDDeInit
|
||||||
|
*
|
||||||
|
* @brief Deinitializes the FSMC NAND Banks registers to their default
|
||||||
|
* reset values.
|
||||||
|
*
|
||||||
|
* @param FSMC_Bank -
|
||||||
|
* FSMC_Bank2_NAND - FSMC Bank2 NAND.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void FSMC_NANDDeInit(uint32_t FSMC_Bank)
|
||||||
|
{
|
||||||
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
FSMC_Bank2->PCR2 = 0x00000018;
|
||||||
|
FSMC_Bank2->SR2 = 0x00000040;
|
||||||
|
FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
|
||||||
|
FSMC_Bank2->PATT2 = 0xFCFCFCFC;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn FSMC_NORSRAMInit
|
||||||
|
*
|
||||||
|
* @brief Initializes the FSMC NOR/SRAM Banks according to the specified
|
||||||
|
* parameters in the FSMC_NORSRAMInitStruct.
|
||||||
|
*
|
||||||
|
* @param SMC_NORSRAMInitStruct:pointer to a FSMC_NORSRAMInitTypeDef
|
||||||
|
* structure that contains the configuration information for the FSMC NOR/SRAM
|
||||||
|
* specified Banks.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
|
||||||
|
{
|
||||||
|
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
|
||||||
|
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_MemoryType |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
|
||||||
|
|
||||||
|
if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
|
||||||
|
{
|
||||||
|
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_Set;
|
||||||
|
}
|
||||||
|
|
||||||
|
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank + 1] =
|
||||||
|
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
|
||||||
|
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
|
||||||
|
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
|
||||||
|
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
|
||||||
|
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
|
||||||
|
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
|
||||||
|
|
||||||
|
if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
|
||||||
|
{
|
||||||
|
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
|
||||||
|
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
|
||||||
|
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4) |
|
||||||
|
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn FSMC_NANDInit
|
||||||
|
*
|
||||||
|
* @brief Initializes the FSMC NAND Banks according to the specified
|
||||||
|
* parameters in the FSMC_NANDInitStruct.
|
||||||
|
*
|
||||||
|
* @param FSMC_NANDInitStruct - pointer to a FSMC_NANDInitTypeDef
|
||||||
|
* structure that contains the configuration information for the FSMC
|
||||||
|
* NAND specified Banks.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void FSMC_NANDInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
|
||||||
|
{
|
||||||
|
uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
|
||||||
|
|
||||||
|
tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
|
||||||
|
PCR_MemoryType_NAND |
|
||||||
|
FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
|
||||||
|
FSMC_NANDInitStruct->FSMC_ECC |
|
||||||
|
FSMC_NANDInitStruct->FSMC_ECCPageSize |
|
||||||
|
(FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9) |
|
||||||
|
(FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
|
||||||
|
|
||||||
|
tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
|
||||||
|
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||||||
|
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16) |
|
||||||
|
(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||||||
|
|
||||||
|
tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
|
||||||
|
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
|
||||||
|
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16) |
|
||||||
|
(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
|
||||||
|
|
||||||
|
if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
FSMC_Bank2->PCR2 = tmppcr;
|
||||||
|
FSMC_Bank2->PMEM2 = tmppmem;
|
||||||
|
FSMC_Bank2->PATT2 = tmppatt;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn FSMC_NORSRAMStructInit
|
||||||
|
*
|
||||||
|
* @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
|
||||||
|
*
|
||||||
|
* @param FSMC_NORSRAMInitStruct - pointer to a FSMC_NORSRAMInitTypeDef
|
||||||
|
* structure which will be initialized.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef *FSMC_NORSRAMInitStruct)
|
||||||
|
{
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
|
||||||
|
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn FSMC_NANDStructInit
|
||||||
|
*
|
||||||
|
* @brief Fills each FSMC_NANDInitStruct member with its default value.
|
||||||
|
*
|
||||||
|
* @param FSMC_NANDInitStruct - pointer to a FSMC_NANDInitTypeDef
|
||||||
|
* structure which will be initialized.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void FSMC_NANDStructInit(FSMC_NANDInitTypeDef *FSMC_NANDInitStruct)
|
||||||
|
{
|
||||||
|
FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
|
||||||
|
FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
|
||||||
|
FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
|
||||||
|
FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
|
||||||
|
FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
|
||||||
|
FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
|
||||||
|
FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
|
||||||
|
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||||||
|
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||||||
|
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||||||
|
FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||||||
|
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
|
||||||
|
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
|
||||||
|
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
|
||||||
|
FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn FSMC_NORSRAMCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the specified NOR/SRAM Memory Bank.
|
||||||
|
*
|
||||||
|
* @param FSMC_Bank - specifies the FSMC Bank to be used
|
||||||
|
* FSMC_Bank1_NORSRAM1 - FSMC Bank1 NOR/SRAM1
|
||||||
|
* FSMC_Bank1_NORSRAM2 - FSMC Bank1 NOR/SRAM2
|
||||||
|
* FSMC_Bank1_NORSRAM3 - FSMC Bank1 NOR/SRAM3
|
||||||
|
* FSMC_Bank1_NORSRAM4 - FSMC Bank1 NOR/SRAM4
|
||||||
|
* NewState:ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn FSMC_NANDCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the specified NAND Memory Bank.
|
||||||
|
*
|
||||||
|
* @param FSMC_Bank - specifies the FSMC Bank to be used
|
||||||
|
* FSMC_Bank2_NAND - FSMC Bank2 NAND
|
||||||
|
* NewStat - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
FSMC_Bank2->PCR2 |= PCR_PBKEN_Set;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
FSMC_Bank2->PCR2 &= PCR_PBKEN_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn FSMC_NANDECCCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the FSMC NAND ECC feature.
|
||||||
|
*
|
||||||
|
* @param FSMC_Bank - specifies the FSMC Bank to be used
|
||||||
|
* FSMC_Bank2_NAND - FSMC Bank2 NAND
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
FSMC_Bank2->PCR2 |= PCR_ECCEN_Set;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
FSMC_Bank2->PCR2 &= PCR_ECCEN_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn FSMC_GetECC
|
||||||
|
*
|
||||||
|
* @brief Returns the error correction code register value.
|
||||||
|
*
|
||||||
|
* @param FSMC_Bank - specifies the FSMC Bank to be used
|
||||||
|
* FSMC_Bank2_NAND - FSMC Bank2 NAND
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return eccval - The Error Correction Code (ECC) value.
|
||||||
|
*/
|
||||||
|
uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
|
||||||
|
{
|
||||||
|
uint32_t eccval = 0x00000000;
|
||||||
|
|
||||||
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
eccval = FSMC_Bank2->ECCR2;
|
||||||
|
}
|
||||||
|
|
||||||
|
return (eccval);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn FSMC_GetFlagStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified FSMC flag is set or not.
|
||||||
|
*
|
||||||
|
* @param FSMC_Bank - specifies the FSMC Bank to be used
|
||||||
|
* FSMC_Bank2_NAND - FSMC Bank2 NAND
|
||||||
|
* FSMC_FLAG - specifies the flag to check.
|
||||||
|
* FSMC_FLAG_FEMPT - Fifo empty Flag.
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return FlagStatus - The new state of FSMC_FLAG (SET or RESET).
|
||||||
|
*/
|
||||||
|
FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
uint32_t tmpsr = 0x00000000;
|
||||||
|
|
||||||
|
if(FSMC_Bank == FSMC_Bank2_NAND)
|
||||||
|
{
|
||||||
|
tmpsr = FSMC_Bank2->SR2;
|
||||||
|
}
|
||||||
|
|
||||||
|
if((tmpsr & FSMC_FLAG) != (uint16_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
895
Peripheral/src/ch32v30x_gpio.c
Normal file
895
Peripheral/src/ch32v30x_gpio.c
Normal file
@@ -0,0 +1,895 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_gpio.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2024/05/06
|
||||||
|
* Description : This file provides all the GPIO firmware functions.
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_gpio.h"
|
||||||
|
#include "ch32v30x_rcc.h"
|
||||||
|
|
||||||
|
/* MASK */
|
||||||
|
#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)
|
||||||
|
#define LSB_MASK ((uint16_t)0xFFFF)
|
||||||
|
#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
|
||||||
|
#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)
|
||||||
|
#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
|
||||||
|
#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_DeInit
|
||||||
|
*
|
||||||
|
* @brief Deinitializes the GPIOx peripheral registers to their default
|
||||||
|
* reset values.
|
||||||
|
*
|
||||||
|
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_DeInit(GPIO_TypeDef *GPIOx)
|
||||||
|
{
|
||||||
|
if(GPIOx == GPIOA)
|
||||||
|
{
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
|
||||||
|
}
|
||||||
|
else if(GPIOx == GPIOB)
|
||||||
|
{
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
|
||||||
|
}
|
||||||
|
else if(GPIOx == GPIOC)
|
||||||
|
{
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
|
||||||
|
}
|
||||||
|
else if(GPIOx == GPIOD)
|
||||||
|
{
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
|
||||||
|
}
|
||||||
|
else if(GPIOx == GPIOE)
|
||||||
|
{
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_AFIODeInit
|
||||||
|
*
|
||||||
|
* @brief Deinitializes the Alternate Functions (remap, event control
|
||||||
|
* and EXTI configuration) registers to their default reset values.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_AFIODeInit(void)
|
||||||
|
{
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_Init
|
||||||
|
*
|
||||||
|
* @brief GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
*
|
||||||
|
* @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that
|
||||||
|
* contains the configuration information for the specified GPIO peripheral.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
|
||||||
|
{
|
||||||
|
uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
|
||||||
|
uint32_t tmpreg = 0x00, pinmask = 0x00;
|
||||||
|
|
||||||
|
currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
|
||||||
|
|
||||||
|
if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
|
||||||
|
{
|
||||||
|
currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
|
||||||
|
{
|
||||||
|
tmpreg = GPIOx->CFGLR;
|
||||||
|
|
||||||
|
for(pinpos = 0x00; pinpos < 0x08; pinpos++)
|
||||||
|
{
|
||||||
|
pos = ((uint32_t)0x01) << pinpos;
|
||||||
|
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
|
||||||
|
|
||||||
|
if(currentpin == pos)
|
||||||
|
{
|
||||||
|
pos = pinpos << 2;
|
||||||
|
pinmask = ((uint32_t)0x0F) << pos;
|
||||||
|
tmpreg &= ~pinmask;
|
||||||
|
tmpreg |= (currentmode << pos);
|
||||||
|
|
||||||
|
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
|
||||||
|
{
|
||||||
|
GPIOx->BCR = (((uint32_t)0x01) << pinpos);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
|
||||||
|
{
|
||||||
|
GPIOx->BSHR = (((uint32_t)0x01) << pinpos);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
GPIOx->CFGLR = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(GPIO_InitStruct->GPIO_Pin > 0x00FF)
|
||||||
|
{
|
||||||
|
tmpreg = GPIOx->CFGHR;
|
||||||
|
|
||||||
|
for(pinpos = 0x00; pinpos < 0x08; pinpos++)
|
||||||
|
{
|
||||||
|
pos = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||||
|
currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
|
||||||
|
|
||||||
|
if(currentpin == pos)
|
||||||
|
{
|
||||||
|
pos = pinpos << 2;
|
||||||
|
pinmask = ((uint32_t)0x0F) << pos;
|
||||||
|
tmpreg &= ~pinmask;
|
||||||
|
tmpreg |= (currentmode << pos);
|
||||||
|
|
||||||
|
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
|
||||||
|
{
|
||||||
|
GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||||
|
}
|
||||||
|
|
||||||
|
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
|
||||||
|
{
|
||||||
|
GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
GPIOx->CFGHR = tmpreg;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_StructInit
|
||||||
|
*
|
||||||
|
* @brief Fills each GPIO_InitStruct member with its default
|
||||||
|
*
|
||||||
|
* @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure
|
||||||
|
* which will be initialized.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct)
|
||||||
|
{
|
||||||
|
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
|
||||||
|
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
|
||||||
|
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_ReadInputDataBit
|
||||||
|
*
|
||||||
|
* @brief GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
*
|
||||||
|
* @param GPIO_Pin - specifies the port bit to read.
|
||||||
|
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||||
|
*
|
||||||
|
* @return The input port pin value.
|
||||||
|
*/
|
||||||
|
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||||
|
{
|
||||||
|
uint8_t bitstatus = 0x00;
|
||||||
|
|
||||||
|
if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||||
|
{
|
||||||
|
bitstatus = (uint8_t)Bit_SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = (uint8_t)Bit_RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_ReadInputData
|
||||||
|
*
|
||||||
|
* @brief Reads the specified GPIO input data port.
|
||||||
|
*
|
||||||
|
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
*
|
||||||
|
* @return The output port pin value.
|
||||||
|
*/
|
||||||
|
uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx)
|
||||||
|
{
|
||||||
|
return ((uint16_t)GPIOx->INDR);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_ReadOutputDataBit
|
||||||
|
*
|
||||||
|
* @brief Reads the specified output data port bit.
|
||||||
|
*
|
||||||
|
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
* GPIO_Pin - specifies the port bit to read.
|
||||||
|
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||||
|
{
|
||||||
|
uint8_t bitstatus = 0x00;
|
||||||
|
|
||||||
|
if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||||
|
{
|
||||||
|
bitstatus = (uint8_t)Bit_SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = (uint8_t)Bit_RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_ReadOutputData
|
||||||
|
*
|
||||||
|
* @brief Reads the specified GPIO output data port.
|
||||||
|
*
|
||||||
|
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
*
|
||||||
|
* @return GPIO output port pin value.
|
||||||
|
*/
|
||||||
|
uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx)
|
||||||
|
{
|
||||||
|
return ((uint16_t)GPIOx->OUTDR);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_SetBits
|
||||||
|
*
|
||||||
|
* @brief Sets the selected data port bits.
|
||||||
|
*
|
||||||
|
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
* GPIO_Pin - specifies the port bits to be written.
|
||||||
|
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||||
|
{
|
||||||
|
GPIOx->BSHR = GPIO_Pin;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_ResetBits
|
||||||
|
*
|
||||||
|
* @brief Clears the selected data port bits.
|
||||||
|
*
|
||||||
|
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
* GPIO_Pin - specifies the port bits to be written.
|
||||||
|
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||||
|
{
|
||||||
|
GPIOx->BCR = GPIO_Pin;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_WriteBit
|
||||||
|
*
|
||||||
|
* @brief Sets or clears the selected data port bit.
|
||||||
|
*
|
||||||
|
* @param GPIO_Pin - specifies the port bit to be written.
|
||||||
|
* This parameter can be one of GPIO_Pin_x where x can be (0..15).
|
||||||
|
* BitVal - specifies the value to be written to the selected bit.
|
||||||
|
* Bit_RESET - to clear the port pin.
|
||||||
|
* Bit_SET - to set the port pin.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
|
||||||
|
{
|
||||||
|
if(BitVal != Bit_RESET)
|
||||||
|
{
|
||||||
|
GPIOx->BSHR = GPIO_Pin;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
GPIOx->BCR = GPIO_Pin;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_Write
|
||||||
|
*
|
||||||
|
* @brief Writes data to the specified GPIO data port.
|
||||||
|
*
|
||||||
|
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
* PortVal - specifies the value to be written to the port output data register.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal)
|
||||||
|
{
|
||||||
|
GPIOx->OUTDR = PortVal;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_PinLockConfig
|
||||||
|
*
|
||||||
|
* @brief Locks GPIO Pins configuration registers.
|
||||||
|
*
|
||||||
|
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||||
|
* GPIO_Pin - specifies the port bit to be written.
|
||||||
|
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||||
|
{
|
||||||
|
uint32_t tmp = 0x00010000;
|
||||||
|
|
||||||
|
tmp |= GPIO_Pin;
|
||||||
|
GPIOx->LCKR = tmp;
|
||||||
|
GPIOx->LCKR = GPIO_Pin;
|
||||||
|
GPIOx->LCKR = tmp;
|
||||||
|
tmp = GPIOx->LCKR;
|
||||||
|
tmp = GPIOx->LCKR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_EventOutputConfig
|
||||||
|
*
|
||||||
|
* @brief Selects the GPIO pin used as Event output.
|
||||||
|
*
|
||||||
|
* @param GPIO_PortSource - selects the GPIO port to be used as source
|
||||||
|
* for Event output.
|
||||||
|
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
|
||||||
|
* GPIO_PinSource - specifies the pin for the Event output.
|
||||||
|
* This parameter can be GPIO_PinSourcex where x can be (0..15).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0x00;
|
||||||
|
|
||||||
|
tmpreg = AFIO->ECR;
|
||||||
|
tmpreg &= ECR_PORTPINCONFIG_MASK;
|
||||||
|
tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
|
||||||
|
tmpreg |= GPIO_PinSource;
|
||||||
|
AFIO->ECR = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_EventOutputCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the Event Output.
|
||||||
|
*
|
||||||
|
* @param NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_EventOutputCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
{
|
||||||
|
AFIO->ECR |= (1 << 7);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
AFIO->ECR &= ~(1 << 7);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_PinRemapConfig
|
||||||
|
*
|
||||||
|
* @brief Changes the mapping of the specified pin.
|
||||||
|
*
|
||||||
|
* @param GPIO_Remap - selects the pin to remap.
|
||||||
|
* GPIO_Remap_SPI1 - SPI1 Alternate Function mapping
|
||||||
|
* GPIO_Remap_SPI3 - SPI3 Alternate Function mapping(CH32V30X_D8,CH32V30X_D8C)
|
||||||
|
* GPIO_Remap_I2C1 - I2C1 Alternate Function mapping
|
||||||
|
* GPIO_Remap_USART1 - USART1 Alternate Function mapping
|
||||||
|
* GPIO_Remap_USART2 - USART2 Alternate Function mapping
|
||||||
|
* GPIO_PartialRemap_USART3 - USART3 Partial Alternate Function mapping
|
||||||
|
* GPIO_PartialRemap1_USART3 - USART3 Partial1 Alternate Function mapping
|
||||||
|
* GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping
|
||||||
|
* GPIO_PartialRemap_TIM1 - TIM1 Partial Alternate Function mapping
|
||||||
|
* GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping
|
||||||
|
* GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping
|
||||||
|
* GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping
|
||||||
|
* GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping
|
||||||
|
* GPIO_PartialRemap_TIM3 - TIM3 Partial Alternate Function mapping
|
||||||
|
* GPIO_FullRemap_TIM3 - TIM3 Full Alternate Function mapping
|
||||||
|
* GPIO_Remap_TIM4 - TIM4 Alternate Function mapping
|
||||||
|
* GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping
|
||||||
|
* GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping
|
||||||
|
* GPIO_Remap_PD0PD1 - PD0 and PD1 Alternate Function mapping
|
||||||
|
* GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping
|
||||||
|
* GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping
|
||||||
|
* GPIO_Remap_ADC2_ETRGINJ - ADC2 External Trigger Injected Conversion remapping
|
||||||
|
* GPIO_Remap_ADC2_ETRGREG - ADC2 External Trigger Regular Conversion remapping
|
||||||
|
* GPIO_Remap_ETH - Ethernet remapping
|
||||||
|
* GPIO_Remap_CAN2 - CAN2 remapping
|
||||||
|
* GPIO_Remap_MII_RMII_SEL - MII or RMII selection
|
||||||
|
* GPIO_Remap_SWJ_Disable - Full SWJ Disabled
|
||||||
|
* GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) connected
|
||||||
|
* to TIM2 Internal Trigger 1 for calibration
|
||||||
|
* GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame)
|
||||||
|
* GPIO_Remap_TIM8 - TIM8 Alternate Function mapping
|
||||||
|
* GPIO_PartialRemap_TIM9 - TIM9 Partial Alternate Function mapping
|
||||||
|
* GPIO_FullRemap_TIM9 - TIM9 Full Alternate Function mapping
|
||||||
|
* GPIO_PartialRemap_TIM10 - TIM10 Partial Alternate Function mapping
|
||||||
|
* GPIO_FullRemap_TIM10 - TIM10 Full Alternate Function mapping
|
||||||
|
* GPIO_Remap_FSMC_NADV - FSMC_NADV Alternate Function mapping
|
||||||
|
* GPIO_PartialRemap_USART4 - USART4 Partial Alternate Function mapping
|
||||||
|
* GPIO_FullRemap_USART4 - USART4 Full Alternate Function mapping
|
||||||
|
* GPIO_PartialRemap_USART5 - USART5 Partial Alternate Function mapping
|
||||||
|
* GPIO_FullRemap_USART5 - USART5 Full Alternate Function mapping
|
||||||
|
* GPIO_PartialRemap_USART6 - USART6 Partial Alternate Function mapping
|
||||||
|
* GPIO_FullRemap_USART6 - USART6 Full Alternate Function mapping
|
||||||
|
* GPIO_PartialRemap_USART7 - USART7 Partial Alternate Function mapping
|
||||||
|
* GPIO_FullRemap_USART7 - USART7 Full Alternate Function mapping
|
||||||
|
* GPIO_PartialRemap_USART8 - USART8 Partial Alternate Function mapping
|
||||||
|
* GPIO_FullRemap_USART8 - USART8 Full Alternate Function mapping
|
||||||
|
* GPIO_Remap_USART1_HighBit - USART1 Alternate Function mapping high bit
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
|
||||||
|
|
||||||
|
if((GPIO_Remap & 0x80000000) == 0x80000000)
|
||||||
|
{
|
||||||
|
tmpreg = AFIO->PCFR2;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
tmpreg = AFIO->PCFR1;
|
||||||
|
}
|
||||||
|
|
||||||
|
tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
|
||||||
|
tmp = GPIO_Remap & LSB_MASK;
|
||||||
|
|
||||||
|
/* Clear bit */
|
||||||
|
if((GPIO_Remap & 0x80000000) == 0x80000000)
|
||||||
|
{ /* PCFR2 */
|
||||||
|
if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [31:16] 2bit */
|
||||||
|
{
|
||||||
|
tmp1 = ((uint32_t)0x03) << (tmpmask + 0x10);
|
||||||
|
tmpreg &= ~tmp1;
|
||||||
|
}
|
||||||
|
else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */
|
||||||
|
{
|
||||||
|
tmp1 = ((uint32_t)0x03) << tmpmask;
|
||||||
|
tmpreg &= ~tmp1;
|
||||||
|
}
|
||||||
|
else /* [31:0] 1bit */
|
||||||
|
{
|
||||||
|
tmpreg &= ~(tmp << (((GPIO_Remap & 0x7FFFFFFF)>> 0x15) * 0x10));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{ /* PCFR1 */
|
||||||
|
if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [26:24] 3bit SWD_JTAG */
|
||||||
|
{
|
||||||
|
tmpreg &= DBGAFR_SWJCFG_MASK;
|
||||||
|
AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK;
|
||||||
|
}
|
||||||
|
else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */
|
||||||
|
{
|
||||||
|
tmp1 = ((uint32_t)0x03) << tmpmask;
|
||||||
|
tmpreg &= ~tmp1;
|
||||||
|
tmpreg |= ~DBGAFR_SWJCFG_MASK;
|
||||||
|
}
|
||||||
|
else /* [31:0] 1bit */
|
||||||
|
{
|
||||||
|
tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10));
|
||||||
|
tmpreg |= ~DBGAFR_SWJCFG_MASK;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set bit */
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
tmpreg |= (tmp << (((GPIO_Remap & 0x7FFFFFFF)>> 0x15) * 0x10));
|
||||||
|
}
|
||||||
|
|
||||||
|
if((GPIO_Remap & 0x80000000) == 0x80000000)
|
||||||
|
{
|
||||||
|
AFIO->PCFR2 = tmpreg;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
AFIO->PCFR1 = tmpreg;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_EXTILineConfig
|
||||||
|
*
|
||||||
|
* @brief Selects the GPIO pin used as EXTI Line.
|
||||||
|
*
|
||||||
|
* @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines.
|
||||||
|
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
|
||||||
|
* GPIO_PinSource - specifies the EXTI line to be configured.
|
||||||
|
* This parameter can be GPIO_PinSourcex where x can be (0..15).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
|
||||||
|
{
|
||||||
|
uint32_t tmp = 0x00;
|
||||||
|
|
||||||
|
tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
|
||||||
|
AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
|
||||||
|
AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_ETH_MediaInterfaceConfig
|
||||||
|
*
|
||||||
|
* @brief Selects the Ethernet media interface.
|
||||||
|
*
|
||||||
|
* @param GPIO_ETH_MediaInterface - specifies the Media Interface mode.
|
||||||
|
* GPIO_ETH_MediaInterface_MII - MII mode
|
||||||
|
* GPIO_ETH_MediaInterface_RMII - RMII mode
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface)
|
||||||
|
{
|
||||||
|
if(GPIO_ETH_MediaInterface)
|
||||||
|
{
|
||||||
|
AFIO->PCFR1 |= (1 << 23);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
AFIO->PCFR1 &= ~(1 << 23);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn GPIO_IPD_Unused
|
||||||
|
*
|
||||||
|
* @brief Configure unused GPIO as input pull-down.
|
||||||
|
*
|
||||||
|
* @param none
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void GPIO_IPD_Unused(void)
|
||||||
|
{
|
||||||
|
GPIO_InitTypeDef GPIO_InitStructure = {0};
|
||||||
|
uint32_t chip = 0;
|
||||||
|
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC|\
|
||||||
|
RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOE, ENABLE);
|
||||||
|
chip = *( uint32_t * )0x1FFFF704 & (~0x000000F0);
|
||||||
|
switch(chip)
|
||||||
|
{
|
||||||
|
#ifdef CH32V30x_D8
|
||||||
|
case 0x30330504: //CH32V303CBT6
|
||||||
|
{
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_2|GPIO_Pin_3\
|
||||||
|
|GPIO_Pin_4|GPIO_Pin_5\
|
||||||
|
|GPIO_Pin_6|GPIO_Pin_7\
|
||||||
|
|GPIO_Pin_8|GPIO_Pin_9\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_2|GPIO_Pin_3\
|
||||||
|
|GPIO_Pin_4|GPIO_Pin_5\
|
||||||
|
|GPIO_Pin_6|GPIO_Pin_7\
|
||||||
|
|GPIO_Pin_8|GPIO_Pin_9\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_13\
|
||||||
|
|GPIO_Pin_14|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_2|GPIO_Pin_3\
|
||||||
|
|GPIO_Pin_4|GPIO_Pin_5\
|
||||||
|
|GPIO_Pin_6|GPIO_Pin_7\
|
||||||
|
|GPIO_Pin_8|GPIO_Pin_9\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_13\
|
||||||
|
|GPIO_Pin_14|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case 0x30320504: //CH32V303RBT6
|
||||||
|
{
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_3|GPIO_Pin_4\
|
||||||
|
|GPIO_Pin_5|GPIO_Pin_6\
|
||||||
|
|GPIO_Pin_7|GPIO_Pin_8\
|
||||||
|
|GPIO_Pin_9|GPIO_Pin_10\
|
||||||
|
|GPIO_Pin_11|GPIO_Pin_12\
|
||||||
|
|GPIO_Pin_13|GPIO_Pin_14\
|
||||||
|
|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_2|GPIO_Pin_3\
|
||||||
|
|GPIO_Pin_4|GPIO_Pin_5\
|
||||||
|
|GPIO_Pin_6|GPIO_Pin_7\
|
||||||
|
|GPIO_Pin_8|GPIO_Pin_9\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_13\
|
||||||
|
|GPIO_Pin_14|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case 0x30310504: //CH32V303RCT6
|
||||||
|
{
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_3|GPIO_Pin_4\
|
||||||
|
|GPIO_Pin_5|GPIO_Pin_6\
|
||||||
|
|GPIO_Pin_7|GPIO_Pin_8\
|
||||||
|
|GPIO_Pin_9|GPIO_Pin_10\
|
||||||
|
|GPIO_Pin_11|GPIO_Pin_12\
|
||||||
|
|GPIO_Pin_13|GPIO_Pin_14\
|
||||||
|
|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_2|GPIO_Pin_3\
|
||||||
|
|GPIO_Pin_4|GPIO_Pin_5\
|
||||||
|
|GPIO_Pin_6|GPIO_Pin_7\
|
||||||
|
|GPIO_Pin_8|GPIO_Pin_9\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_13\
|
||||||
|
|GPIO_Pin_14|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case 0x30300504: //CH32V303VCT6
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
#elif defined (CH32V30x_D8C)
|
||||||
|
case 0x30520508: //CH32V305FBP6
|
||||||
|
{
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_2\
|
||||||
|
|GPIO_Pin_3|GPIO_Pin_4\
|
||||||
|
|GPIO_Pin_6|GPIO_Pin_7\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
|
||||||
|
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_3\
|
||||||
|
|GPIO_Pin_4|GPIO_Pin_5\
|
||||||
|
|GPIO_Pin_8|GPIO_Pin_9;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_2|GPIO_Pin_3\
|
||||||
|
|GPIO_Pin_4|GPIO_Pin_5\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_13\
|
||||||
|
|GPIO_Pin_14|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_2|GPIO_Pin_3\
|
||||||
|
|GPIO_Pin_4|GPIO_Pin_5\
|
||||||
|
|GPIO_Pin_6|GPIO_Pin_7\
|
||||||
|
|GPIO_Pin_8|GPIO_Pin_9\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_13\
|
||||||
|
|GPIO_Pin_14|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_2|GPIO_Pin_3\
|
||||||
|
|GPIO_Pin_4|GPIO_Pin_5\
|
||||||
|
|GPIO_Pin_6|GPIO_Pin_7\
|
||||||
|
|GPIO_Pin_8|GPIO_Pin_9\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_13\
|
||||||
|
|GPIO_Pin_14|GPIO_Pin_15;
|
||||||
|
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case 0x305C0508: //CH32V305CCT6
|
||||||
|
{
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_7|GPIO_Pin_8\
|
||||||
|
|GPIO_Pin_9|GPIO_Pin_10\
|
||||||
|
|GPIO_Pin_11|GPIO_Pin_12\
|
||||||
|
|GPIO_Pin_13|GPIO_Pin_14\
|
||||||
|
|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_2|GPIO_Pin_3\
|
||||||
|
|GPIO_Pin_4|GPIO_Pin_5\
|
||||||
|
|GPIO_Pin_6|GPIO_Pin_7\
|
||||||
|
|GPIO_Pin_8|GPIO_Pin_9\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_13\
|
||||||
|
|GPIO_Pin_14|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_2|GPIO_Pin_3\
|
||||||
|
|GPIO_Pin_4|GPIO_Pin_5\
|
||||||
|
|GPIO_Pin_6|GPIO_Pin_7\
|
||||||
|
|GPIO_Pin_8|GPIO_Pin_9\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_13\
|
||||||
|
|GPIO_Pin_14|GPIO_Pin_15;
|
||||||
|
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case 0x30500508: //CH32V305RBT6
|
||||||
|
{
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_3|GPIO_Pin_4\
|
||||||
|
|GPIO_Pin_5|GPIO_Pin_6\
|
||||||
|
|GPIO_Pin_7|GPIO_Pin_8\
|
||||||
|
|GPIO_Pin_9|GPIO_Pin_10\
|
||||||
|
|GPIO_Pin_11|GPIO_Pin_12\
|
||||||
|
|GPIO_Pin_13|GPIO_Pin_14\
|
||||||
|
|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_2|GPIO_Pin_3\
|
||||||
|
|GPIO_Pin_4|GPIO_Pin_5\
|
||||||
|
|GPIO_Pin_6|GPIO_Pin_7\
|
||||||
|
|GPIO_Pin_8|GPIO_Pin_9\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_13\
|
||||||
|
|GPIO_Pin_14|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case 0x30710508: //CH32V307RCT6
|
||||||
|
{
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_3|GPIO_Pin_4\
|
||||||
|
|GPIO_Pin_5|GPIO_Pin_6\
|
||||||
|
|GPIO_Pin_7|GPIO_Pin_8\
|
||||||
|
|GPIO_Pin_9|GPIO_Pin_10\
|
||||||
|
|GPIO_Pin_11|GPIO_Pin_12\
|
||||||
|
|GPIO_Pin_13|GPIO_Pin_14\
|
||||||
|
|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_2|GPIO_Pin_3\
|
||||||
|
|GPIO_Pin_4|GPIO_Pin_5\
|
||||||
|
|GPIO_Pin_6|GPIO_Pin_7\
|
||||||
|
|GPIO_Pin_8|GPIO_Pin_9\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_13\
|
||||||
|
|GPIO_Pin_14|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case 0x30730508: //CH32V307WCU6
|
||||||
|
{
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_3|GPIO_Pin_4\
|
||||||
|
|GPIO_Pin_5|GPIO_Pin_6\
|
||||||
|
|GPIO_Pin_7|GPIO_Pin_10\
|
||||||
|
|GPIO_Pin_11|GPIO_Pin_12\
|
||||||
|
|GPIO_Pin_13|GPIO_Pin_14\
|
||||||
|
|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1|GPIO_Pin_2\
|
||||||
|
|GPIO_Pin_3|GPIO_Pin_4\
|
||||||
|
|GPIO_Pin_5|GPIO_Pin_6\
|
||||||
|
|GPIO_Pin_7|GPIO_Pin_8\
|
||||||
|
|GPIO_Pin_9|GPIO_Pin_10\
|
||||||
|
|GPIO_Pin_11|GPIO_Pin_12\
|
||||||
|
|GPIO_Pin_13|GPIO_Pin_14\
|
||||||
|
|GPIO_Pin_15;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case 0x3173B508: //CH32V317WCU6
|
||||||
|
{
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6|GPIO_Pin_7\
|
||||||
|
|GPIO_Pin_8|GPIO_Pin_9;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_13\
|
||||||
|
|GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_3|GPIO_Pin_4\
|
||||||
|
|GPIO_Pin_5|GPIO_Pin_6\
|
||||||
|
|GPIO_Pin_7;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1|GPIO_Pin_2\
|
||||||
|
|GPIO_Pin_3|GPIO_Pin_4\
|
||||||
|
|GPIO_Pin_5|GPIO_Pin_6;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case 0x3175B508: //CH32V317TCU6
|
||||||
|
{
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9|GPIO_Pin_10;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9|GPIO_Pin_10\
|
||||||
|
|GPIO_Pin_11;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||||
|
|GPIO_Pin_5|GPIO_Pin_6\
|
||||||
|
|GPIO_Pin_7|GPIO_Pin_8\
|
||||||
|
|GPIO_Pin_9|GPIO_Pin_10\
|
||||||
|
|GPIO_Pin_11|GPIO_Pin_12\
|
||||||
|
|GPIO_Pin_13;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9\
|
||||||
|
|GPIO_Pin_10|GPIO_Pin_11\
|
||||||
|
|GPIO_Pin_12|GPIO_Pin_13\
|
||||||
|
|GPIO_Pin_14|GPIO_Pin_15\
|
||||||
|
|GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\
|
||||||
|
|GPIO_Pin_3|GPIO_Pin_4\
|
||||||
|
|GPIO_Pin_5|GPIO_Pin_6\
|
||||||
|
|GPIO_Pin_7;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||||
|
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2\
|
||||||
|
|GPIO_Pin_3|GPIO_Pin_4\
|
||||||
|
|GPIO_Pin_5|GPIO_Pin_6;
|
||||||
|
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||||
|
GPIO_Init(GPIOE, &GPIO_InitStructure);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case 0x30700508: //CH32V307VCT6
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
case 0x3170B508: //CH32V317VCT6
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
default:
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
1012
Peripheral/src/ch32v30x_i2c.c
Normal file
1012
Peripheral/src/ch32v30x_i2c.c
Normal file
File diff suppressed because it is too large
Load Diff
123
Peripheral/src/ch32v30x_iwdg.c
Normal file
123
Peripheral/src/ch32v30x_iwdg.c
Normal file
@@ -0,0 +1,123 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_iwdg.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2024/03/06
|
||||||
|
* Description : This file provides all the IWDG firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_iwdg.h"
|
||||||
|
|
||||||
|
/* CTLR register bit mask */
|
||||||
|
#define CTLR_KEY_Reload ((uint16_t)0xAAAA)
|
||||||
|
#define CTLR_KEY_Enable ((uint16_t)0xCCCC)
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn IWDG_WriteAccessCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers.
|
||||||
|
*
|
||||||
|
* @param WDG_WriteAccess - new state of write access to IWDG_PSCR and
|
||||||
|
* IWDG_RLDR registers.
|
||||||
|
* IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and
|
||||||
|
* IWDG_RLDR registers.
|
||||||
|
* IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR
|
||||||
|
* and IWDG_RLDR registers.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
|
||||||
|
{
|
||||||
|
IWDG->CTLR = IWDG_WriteAccess;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn IWDG_SetPrescaler
|
||||||
|
*
|
||||||
|
* @brief Sets IWDG Prescaler value.
|
||||||
|
*
|
||||||
|
* @param IWDG_Prescaler - specifies the IWDG Prescaler value.
|
||||||
|
* IWDG_Prescaler_4 - IWDG prescaler set to 4.
|
||||||
|
* IWDG_Prescaler_8 - IWDG prescaler set to 8.
|
||||||
|
* IWDG_Prescaler_16 - IWDG prescaler set to 16.
|
||||||
|
* IWDG_Prescaler_32 - IWDG prescaler set to 32.
|
||||||
|
* IWDG_Prescaler_64 - IWDG prescaler set to 64.
|
||||||
|
* IWDG_Prescaler_128 - IWDG prescaler set to 128.
|
||||||
|
* IWDG_Prescaler_256 - IWDG prescaler set to 256.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
|
||||||
|
{
|
||||||
|
IWDG->PSCR = IWDG_Prescaler;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn IWDG_SetReload
|
||||||
|
*
|
||||||
|
* @brief Sets IWDG Reload value.
|
||||||
|
*
|
||||||
|
* @param Reload - specifies the IWDG Reload value.
|
||||||
|
* This parameter must be a number between 0 and 0x0FFF.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void IWDG_SetReload(uint16_t Reload)
|
||||||
|
{
|
||||||
|
IWDG->RLDR = Reload;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn IWDG_ReloadCounter
|
||||||
|
*
|
||||||
|
* @brief Reloads IWDG counter with value defined in the reload register.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void IWDG_ReloadCounter(void)
|
||||||
|
{
|
||||||
|
IWDG->CTLR = CTLR_KEY_Reload;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn IWDG_Enable
|
||||||
|
*
|
||||||
|
* @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void IWDG_Enable(void)
|
||||||
|
{
|
||||||
|
IWDG->CTLR = CTLR_KEY_Enable;
|
||||||
|
while((RCC->RSTSCKR & 0x2)==RESET);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn IWDG_GetFlagStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified IWDG flag is set or not.
|
||||||
|
*
|
||||||
|
* @param IWDG_FLAG - specifies the flag to check.
|
||||||
|
* IWDG_FLAG_PVU - Prescaler Value Update on going.
|
||||||
|
* IWDG_FLAG_RVU - Reload Value Update on going.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
|
||||||
|
if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
105
Peripheral/src/ch32v30x_misc.c
Normal file
105
Peripheral/src/ch32v30x_misc.c
Normal file
@@ -0,0 +1,105 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_misc.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2024/03/06
|
||||||
|
* Description : This file provides all the miscellaneous firmware functions .
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_misc.h"
|
||||||
|
|
||||||
|
__IO uint32_t NVIC_Priority_Group = 0;
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn NVIC_PriorityGroupConfig
|
||||||
|
*
|
||||||
|
* @brief Configures the priority grouping - pre-emption priority and subpriority.
|
||||||
|
*
|
||||||
|
* @param NVIC_PriorityGroup - specifies the priority grouping bits length.
|
||||||
|
* NVIC_PriorityGroup_0 - 0 bits for pre-emption priority
|
||||||
|
* 3 bits for subpriority
|
||||||
|
* NVIC_PriorityGroup_1 - 1 bits for pre-emption priority
|
||||||
|
* 2 bits for subpriority
|
||||||
|
* NVIC_PriorityGroup_2 - 2 bits for pre-emption priority
|
||||||
|
* 1 bits for subpriority
|
||||||
|
* NVIC_PriorityGroup_3 - 3 bits for pre-emption priority
|
||||||
|
* 0 bits for subpriority
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
|
||||||
|
{
|
||||||
|
NVIC_Priority_Group = NVIC_PriorityGroup;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn NVIC_Init
|
||||||
|
*
|
||||||
|
* @brief Initializes the NVIC peripheral according to the specified parameters in
|
||||||
|
* the NVIC_InitStruct.
|
||||||
|
*
|
||||||
|
* @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the
|
||||||
|
* configuration information for the specified NVIC peripheral.
|
||||||
|
* interrupt nesting disable(CSR-0x804 bit1 = 0)
|
||||||
|
* NVIC_IRQChannelPreemptionPriority - range is 0.
|
||||||
|
* NVIC_IRQChannelSubPriority - range from 0 to 7.
|
||||||
|
*
|
||||||
|
* interrupt nesting enable-2 Level(CSR-0x804 bit1 = 1 bit[3:2] = 1)
|
||||||
|
* NVIC_IRQChannelPreemptionPriority - range from 0 to 1.
|
||||||
|
* NVIC_IRQChannelSubPriority - range from 0 to 3.
|
||||||
|
*
|
||||||
|
* interrupt nesting enable-4 Level(CSR-0x804 bit1 = 1 bit[3:2] = 2)
|
||||||
|
* NVIC_IRQChannelPreemptionPriority - range from 0 to 3.
|
||||||
|
* NVIC_IRQChannelSubPriority - range from 0 to 1.
|
||||||
|
*
|
||||||
|
* interrupt nesting enable-8 Level(CSR-0x804 bit1 = 1 bit[3:2] = 3)
|
||||||
|
* NVIC_IRQChannelPreemptionPriority - range from 0 to 7.
|
||||||
|
* NVIC_IRQChannelSubPriority - range range is 0.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct)
|
||||||
|
{
|
||||||
|
#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN)
|
||||||
|
if(NVIC_Priority_Group == NVIC_PriorityGroup_0)
|
||||||
|
{
|
||||||
|
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4);
|
||||||
|
}
|
||||||
|
#elif (INTSYSCR_INEST == INTSYSCR_INEST_EN_2Level)
|
||||||
|
if(NVIC_Priority_Group == NVIC_PriorityGroup_1)
|
||||||
|
{
|
||||||
|
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority < 2)
|
||||||
|
{
|
||||||
|
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#elif (INTSYSCR_INEST == INTSYSCR_INEST_EN_4Level)
|
||||||
|
if(NVIC_Priority_Group == NVIC_PriorityGroup_2)
|
||||||
|
{
|
||||||
|
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority < 4)
|
||||||
|
{
|
||||||
|
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 6) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#elif (INTSYSCR_INEST == INTSYSCR_INEST_EN_8Level)
|
||||||
|
if(NVIC_Priority_Group == NVIC_PriorityGroup_3)
|
||||||
|
{
|
||||||
|
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority < 8)
|
||||||
|
{
|
||||||
|
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << 5) );
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
|
||||||
|
{
|
||||||
|
NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
|
||||||
|
}
|
||||||
|
}
|
||||||
86
Peripheral/src/ch32v30x_opa.c
Normal file
86
Peripheral/src/ch32v30x_opa.c
Normal file
@@ -0,0 +1,86 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_opa.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file provides all the OPA firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_opa.h"
|
||||||
|
|
||||||
|
#define OPA_MASK ((uint32_t)0x000F)
|
||||||
|
#define OPA_Total_NUM 4
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn OPA_DeInit
|
||||||
|
*
|
||||||
|
* @brief Deinitializes the OPA peripheral registers to their default
|
||||||
|
* reset values.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void OPA_DeInit(void)
|
||||||
|
{
|
||||||
|
OPA->CR = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn OPA_Init
|
||||||
|
*
|
||||||
|
* @brief Initializes the OPA peripheral according to the specified
|
||||||
|
* parameters in the OPA_InitStruct.
|
||||||
|
*
|
||||||
|
* @param OPA_InitStruct - pointer to a OPA_InitTypeDef structure
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void OPA_Init(OPA_InitTypeDef *OPA_InitStruct)
|
||||||
|
{
|
||||||
|
uint32_t tmp = 0;
|
||||||
|
tmp = OPA->CR;
|
||||||
|
tmp &= ~(OPA_MASK << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM));
|
||||||
|
tmp |= (((OPA_InitStruct->PSEL << OPA_PSEL_OFFSET) | (OPA_InitStruct->NSEL << OPA_NSEL_OFFSET) | (OPA_InitStruct->Mode << OPA_MODE_OFFSET)) << (OPA_InitStruct->OPA_NUM * OPA_Total_NUM));
|
||||||
|
OPA->CR = tmp;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn OPA_StructInit
|
||||||
|
*
|
||||||
|
* @brief Fills each OPA_StructInit member with its reset value.
|
||||||
|
*
|
||||||
|
* @param OPA_StructInit - pointer to a OPA_InitTypeDef structure
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void OPA_StructInit(OPA_InitTypeDef *OPA_InitStruct)
|
||||||
|
{
|
||||||
|
OPA_InitStruct->Mode = OUT_IO_OUT1;
|
||||||
|
OPA_InitStruct->PSEL = CHP0;
|
||||||
|
OPA_InitStruct->NSEL = CHN0;
|
||||||
|
OPA_InitStruct->OPA_NUM = OPA1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn OPA_Cmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the specified OPA peripheral.
|
||||||
|
*
|
||||||
|
* @param OPA_NUM - Select OPA
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void OPA_Cmd(OPA_Num_TypeDef OPA_NUM, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState == ENABLE)
|
||||||
|
{
|
||||||
|
OPA->CR |= (1 << (OPA_NUM * OPA_Total_NUM));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
OPA->CR &= ~(1 << (OPA_NUM * OPA_Total_NUM));
|
||||||
|
}
|
||||||
|
}
|
||||||
361
Peripheral/src/ch32v30x_pwr.c
Normal file
361
Peripheral/src/ch32v30x_pwr.c
Normal file
@@ -0,0 +1,361 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_pwr.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file provides all the PWR firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_pwr.h"
|
||||||
|
#include "ch32v30x_rcc.h"
|
||||||
|
|
||||||
|
/* PWR registers bit mask */
|
||||||
|
/* CTLR register bit mask */
|
||||||
|
#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFC)
|
||||||
|
#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F)
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_DeInit
|
||||||
|
*
|
||||||
|
* @brief Deinitializes the PWR peripheral registers to their default
|
||||||
|
* reset values.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void PWR_DeInit(void)
|
||||||
|
{
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_BackupAccessCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables access to the RTC and backup registers.
|
||||||
|
*
|
||||||
|
* @param NewState - new state of the access to the RTC and backup registers,
|
||||||
|
* This parameter can be: ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void PWR_BackupAccessCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
{
|
||||||
|
PWR->CTLR |= (1 << 8);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
PWR->CTLR &= ~(1 << 8);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_PVDCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the Power Voltage Detector(PVD).
|
||||||
|
*
|
||||||
|
* @param NewState - new state of the PVD(ENABLE or DISABLE).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void PWR_PVDCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
{
|
||||||
|
PWR->CTLR |= (1 << 4);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
PWR->CTLR &= ~(1 << 4);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_PVDLevelConfig
|
||||||
|
*
|
||||||
|
* @brief Configures the voltage threshold detected by the Power Voltage
|
||||||
|
* Detector(PVD).
|
||||||
|
*
|
||||||
|
* @param PWR_PVDLevel - specifies the PVD detection level
|
||||||
|
* PWR_PVDLevel_MODE0 - PVD detection level set to mode 0.
|
||||||
|
* PWR_PVDLevel_MODE1 - PVD detection level set to mode 1.
|
||||||
|
* PWR_PVDLevel_MODE2 - PVD detection level set to mode 2.
|
||||||
|
* PWR_PVDLevel_MODE3 - PVD detection level set to mode 3.
|
||||||
|
* PWR_PVDLevel_MODE4 - PVD detection level set to mode 4.
|
||||||
|
* PWR_PVDLevel_MODE5 - PVD detection level set to mode 5.
|
||||||
|
* PWR_PVDLevel_MODE6 - PVD detection level set to mode 6.
|
||||||
|
* PWR_PVDLevel_MODE7 - PVD detection level set to mode 7.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
tmpreg = PWR->CTLR;
|
||||||
|
tmpreg &= CTLR_PLS_MASK;
|
||||||
|
tmpreg |= PWR_PVDLevel;
|
||||||
|
PWR->CTLR = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_WakeUpPinCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the WakeUp Pin functionality.
|
||||||
|
*
|
||||||
|
* @param NewState - new state of the WakeUp Pin functionality
|
||||||
|
* (ENABLE or DISABLE).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void PWR_WakeUpPinCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
{
|
||||||
|
PWR->CSR |= (1 << 8);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
PWR->CSR &= ~(1 << 8);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_EnterSTOPMode
|
||||||
|
*
|
||||||
|
* @brief Enters STOP mode.
|
||||||
|
*
|
||||||
|
* @param PWR_Regulator - specifies the regulator state in STOP mode.
|
||||||
|
* PWR_Regulator_ON - STOP mode with regulator ON
|
||||||
|
* PWR_Regulator_LowPower - STOP mode with regulator in low power mode
|
||||||
|
* PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction.
|
||||||
|
* PWR_STOPEntry_WFI - enter STOP mode with WFI instruction
|
||||||
|
* PWR_STOPEntry_WFE - enter STOP mode with WFE instruction
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
tmpreg = PWR->CTLR;
|
||||||
|
tmpreg &= CTLR_DS_MASK;
|
||||||
|
tmpreg |= PWR_Regulator;
|
||||||
|
PWR->CTLR = tmpreg;
|
||||||
|
|
||||||
|
NVIC->SCTLR |= (1 << 2);
|
||||||
|
|
||||||
|
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
|
||||||
|
{
|
||||||
|
__WFI();
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
__WFE();
|
||||||
|
}
|
||||||
|
|
||||||
|
NVIC->SCTLR &= ~(1 << 2);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_EnterSTANDBYMode
|
||||||
|
*
|
||||||
|
* @brief Enters STANDBY mode.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void PWR_EnterSTANDBYMode(void)
|
||||||
|
{
|
||||||
|
PWR->CTLR |= PWR_CTLR_CWUF;
|
||||||
|
PWR->CTLR |= PWR_CTLR_PDDS;
|
||||||
|
NVIC->SCTLR |= (1 << 2);
|
||||||
|
|
||||||
|
__WFI();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_GetFlagStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified PWR flag is set or not.
|
||||||
|
*
|
||||||
|
* @param PWR_FLAG - specifies the flag to check.
|
||||||
|
* PWR_FLAG_WU - Wake Up flag
|
||||||
|
* PWR_FLAG_SB - StandBy flag
|
||||||
|
* PWR_FLAG_PVDO - PVD Output
|
||||||
|
*
|
||||||
|
* @return The new state of PWR_FLAG (SET or RESET).
|
||||||
|
*/
|
||||||
|
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
|
||||||
|
if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_ClearFlag
|
||||||
|
*
|
||||||
|
* @brief Clears the PWR's pending flags.
|
||||||
|
*
|
||||||
|
* @param PWR_FLAG - specifies the flag to clear.
|
||||||
|
* PWR_FLAG_WU - Wake Up flag
|
||||||
|
* PWR_FLAG_SB - StandBy flag
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void PWR_ClearFlag(uint32_t PWR_FLAG)
|
||||||
|
{
|
||||||
|
PWR->CTLR |= PWR_FLAG << 2;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_EnterSTANDBYMode_RAM
|
||||||
|
*
|
||||||
|
* @brief Enters STANDBY mode with RAM data retention function on.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void PWR_EnterSTANDBYMode_RAM(void)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
tmpreg = PWR->CTLR;
|
||||||
|
|
||||||
|
tmpreg |= PWR_CTLR_CWUF;
|
||||||
|
tmpreg |= PWR_CTLR_PDDS;
|
||||||
|
|
||||||
|
//2K+30K in standby w power.
|
||||||
|
tmpreg |= (0x1 << 16) | (0x1 << 17);
|
||||||
|
|
||||||
|
PWR->CTLR = tmpreg;
|
||||||
|
|
||||||
|
NVIC->SCTLR |= (1 << 2);
|
||||||
|
|
||||||
|
__WFI();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_EnterSTANDBYMode_RAM_LV
|
||||||
|
*
|
||||||
|
* @brief Enters STANDBY mode with RAM data retention function and LV mode on.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void PWR_EnterSTANDBYMode_RAM_LV(void)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
tmpreg = PWR->CTLR;
|
||||||
|
|
||||||
|
tmpreg |= PWR_CTLR_CWUF;
|
||||||
|
tmpreg |= PWR_CTLR_PDDS;
|
||||||
|
|
||||||
|
//2K+30K in standby power.
|
||||||
|
tmpreg |= (0x1 << 16) | (0x1 << 17);
|
||||||
|
//2K+30K in standby LV .
|
||||||
|
tmpreg |= (0x1 << 20);
|
||||||
|
|
||||||
|
PWR->CTLR = tmpreg;
|
||||||
|
|
||||||
|
NVIC->SCTLR |= (1 << 2);
|
||||||
|
|
||||||
|
__WFI();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_EnterSTANDBYMode_RAM_VBAT_EN
|
||||||
|
*
|
||||||
|
* @brief Enters STANDBY mode with RAM data retention function on (VBAT Enable).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
tmpreg = PWR->CTLR;
|
||||||
|
|
||||||
|
tmpreg |= PWR_CTLR_CWUF;
|
||||||
|
tmpreg |= PWR_CTLR_PDDS;
|
||||||
|
|
||||||
|
//2K+30K in standby power (VBAT Enable).
|
||||||
|
tmpreg |= (0x1 << 18) | (0x1 << 19);
|
||||||
|
|
||||||
|
PWR->CTLR = tmpreg;
|
||||||
|
|
||||||
|
NVIC->SCTLR |= (1 << 2);
|
||||||
|
|
||||||
|
__WFI();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN
|
||||||
|
*
|
||||||
|
* @brief Enters STANDBY mode with RAM data retention function and LV mode on(VBAT Enable).
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
tmpreg = PWR->CTLR;
|
||||||
|
|
||||||
|
tmpreg |= PWR_CTLR_CWUF;
|
||||||
|
tmpreg |= PWR_CTLR_PDDS;
|
||||||
|
|
||||||
|
//2K+30K in standby power (VBAT Enable).
|
||||||
|
tmpreg |= (0x1 << 18) | (0x1 << 19);
|
||||||
|
//2K+30K in standby LV .
|
||||||
|
tmpreg |= (0x1 << 20);
|
||||||
|
|
||||||
|
PWR->CTLR = tmpreg;
|
||||||
|
|
||||||
|
NVIC->SCTLR |= (1 << 2);
|
||||||
|
|
||||||
|
__WFI();
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn PWR_EnterSTOPMode_RAM_LV
|
||||||
|
*
|
||||||
|
* @brief Enters STOP mode with RAM data retention function and LV mode on.
|
||||||
|
*
|
||||||
|
* @param PWR_Regulator - specifies the regulator state in STOP mode.
|
||||||
|
* PWR_Regulator_LowPower - STOP mode with regulator in low power mode
|
||||||
|
* PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction.
|
||||||
|
* PWR_STOPEntry_WFI - enter STOP mode with WFI instruction
|
||||||
|
* PWR_STOPEntry_WFE - enter STOP mode with WFE instruction
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
tmpreg = PWR->CTLR;
|
||||||
|
tmpreg &= CTLR_DS_MASK;
|
||||||
|
tmpreg |= PWR_Regulator;
|
||||||
|
|
||||||
|
tmpreg |= (0x1 << 20);
|
||||||
|
PWR->CTLR = tmpreg;
|
||||||
|
|
||||||
|
NVIC->SCTLR |= (1 << 2);
|
||||||
|
|
||||||
|
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
|
||||||
|
{
|
||||||
|
__WFI();
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
__WFE();
|
||||||
|
}
|
||||||
|
|
||||||
|
NVIC->SCTLR &= ~(1 << 2);
|
||||||
|
}
|
||||||
1477
Peripheral/src/ch32v30x_rcc.c
Normal file
1477
Peripheral/src/ch32v30x_rcc.c
Normal file
File diff suppressed because it is too large
Load Diff
154
Peripheral/src/ch32v30x_rng.c
Normal file
154
Peripheral/src/ch32v30x_rng.c
Normal file
@@ -0,0 +1,154 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_rng.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file provides all the RNG firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_rng.h"
|
||||||
|
#include "ch32v30x_rcc.h"
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RNG_Cmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the RNG peripheral.
|
||||||
|
*
|
||||||
|
* @param NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void RNG_Cmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
RNG->CR |= RNG_CR_RNGEN;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
RNG->CR &= ~RNG_CR_RNGEN;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RNG_GetRandomNumber
|
||||||
|
*
|
||||||
|
* @brief Returns a 32-bit random number.
|
||||||
|
*
|
||||||
|
* @return 32-bit random number.
|
||||||
|
*/
|
||||||
|
uint32_t RNG_GetRandomNumber(void)
|
||||||
|
{
|
||||||
|
return RNG->DR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RNG_ITConfig
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the RNG interrupt.
|
||||||
|
*
|
||||||
|
* @param NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return 32-bit random number.
|
||||||
|
*/
|
||||||
|
void RNG_ITConfig(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
RNG->CR |= RNG_CR_IE;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
RNG->CR &= ~RNG_CR_IE;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RNG_GetFlagStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified RNG flag is set or not.
|
||||||
|
*
|
||||||
|
* @param RNG_FLAG - specifies the RNG flag to check.
|
||||||
|
* RNG_FLAG_DRDY - Data Ready flag.
|
||||||
|
* RNG_FLAG_CECS - Clock Error Current flag.
|
||||||
|
* RNG_FLAG_SECS - Seed Error Current flag.
|
||||||
|
*
|
||||||
|
* @return 32-bit random number.
|
||||||
|
*/
|
||||||
|
FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
|
||||||
|
if((RNG->SR & RNG_FLAG) != (uint8_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RNG_ClearFlag
|
||||||
|
*
|
||||||
|
* @brief Clears the RNG flags.
|
||||||
|
*
|
||||||
|
* @param RNG_FLAG - specifies the flag to clear.
|
||||||
|
* RNG_FLAG_CECS - Clock Error Current flag.
|
||||||
|
* RNG_FLAG_SECS - Seed Error Current flag.
|
||||||
|
*
|
||||||
|
* @return 32-bit random number.
|
||||||
|
*/
|
||||||
|
void RNG_ClearFlag(uint8_t RNG_FLAG)
|
||||||
|
{
|
||||||
|
RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RNG_GetFlagStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified RNG interrupt has occurred or not.
|
||||||
|
*
|
||||||
|
* @param RNG_IT - specifies the RNG interrupt source to check.
|
||||||
|
* RNG_IT_CEI - Clock Error Interrupt.
|
||||||
|
* RNG_IT_SEI - Seed Error Interrupt.
|
||||||
|
*
|
||||||
|
* @return bitstatus:SET or RESET.
|
||||||
|
*/
|
||||||
|
ITStatus RNG_GetITStatus(uint8_t RNG_IT)
|
||||||
|
{
|
||||||
|
ITStatus bitstatus = RESET;
|
||||||
|
|
||||||
|
if((RNG->SR & RNG_IT) != (uint8_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RNG_ClearITPendingBit
|
||||||
|
*
|
||||||
|
* @brief Clears the RNG interrupt pending bit(s).
|
||||||
|
*
|
||||||
|
* @param RNG_IT - specifies the RNG interrupt pending bit(s) to clear.
|
||||||
|
* RNG_IT_CEI - Clock Error Interrupt.
|
||||||
|
* RNG_IT_SEI - Seed Error Interrupt.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void RNG_ClearITPendingBit(uint8_t RNG_IT)
|
||||||
|
{
|
||||||
|
RNG->SR = (uint8_t)~RNG_IT;
|
||||||
|
}
|
||||||
315
Peripheral/src/ch32v30x_rtc.c
Normal file
315
Peripheral/src/ch32v30x_rtc.c
Normal file
@@ -0,0 +1,315 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_rtc.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file provides all the RTC firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_rtc.h"
|
||||||
|
|
||||||
|
/* RTC_Private_Defines */
|
||||||
|
#define RTC_LSB_MASK ((uint32_t)0x0000FFFF) /* RTC LSB Mask */
|
||||||
|
#define PRLH_MSB_MASK ((uint32_t)0x000F0000) /* RTC Prescaler MSB Mask */
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_ITConfig
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the specified RTC interrupts.
|
||||||
|
*
|
||||||
|
* @param RTC_IT - specifies the RTC interrupts sources to be enabled or disabled.
|
||||||
|
* RTC_IT_OW - Overflow interrupt
|
||||||
|
* RTC_IT_ALR - Alarm interrupt
|
||||||
|
* RTC_IT_SEC - Second interrupt
|
||||||
|
*
|
||||||
|
* @return NewState - new state of the specified RTC interrupts(ENABLE or DISABLE).
|
||||||
|
*/
|
||||||
|
void RTC_ITConfig(uint16_t RTC_IT, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
RTC->CTLRH |= RTC_IT;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
RTC->CTLRH &= (uint16_t)~RTC_IT;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_EnterConfigMode
|
||||||
|
*
|
||||||
|
* @brief Enters the RTC configuration mode.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void RTC_EnterConfigMode(void)
|
||||||
|
{
|
||||||
|
RTC->CTLRL |= RTC_CTLRL_CNF;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_ExitConfigMode
|
||||||
|
*
|
||||||
|
* @brief Exits from the RTC configuration mode.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void RTC_ExitConfigMode(void)
|
||||||
|
{
|
||||||
|
RTC->CTLRL &= (uint16_t) ~((uint16_t)RTC_CTLRL_CNF);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_GetCounter
|
||||||
|
*
|
||||||
|
* @brief Gets the RTC counter value
|
||||||
|
*
|
||||||
|
* @return RTC counter value
|
||||||
|
*/
|
||||||
|
uint32_t RTC_GetCounter(void)
|
||||||
|
{
|
||||||
|
uint16_t high1a = 0, high1b = 0, high2a = 0, high2b = 0;
|
||||||
|
uint16_t low1 = 0, low2 = 0;
|
||||||
|
|
||||||
|
do{
|
||||||
|
high1a = RTC->CNTH;
|
||||||
|
high1b = RTC->CNTH;
|
||||||
|
}while( high1a != high1b );
|
||||||
|
|
||||||
|
do{
|
||||||
|
low1 = RTC->CNTL;
|
||||||
|
low2 = RTC->CNTL;
|
||||||
|
}while( low1 != low2 );
|
||||||
|
|
||||||
|
do{
|
||||||
|
high2a = RTC->CNTH;
|
||||||
|
high2b = RTC->CNTH;
|
||||||
|
}while( high2a != high2b );
|
||||||
|
|
||||||
|
if(high1b != high2b)
|
||||||
|
{
|
||||||
|
do{
|
||||||
|
low1 = RTC->CNTL;
|
||||||
|
low2 = RTC->CNTL;
|
||||||
|
}while( low1 != low2 );
|
||||||
|
}
|
||||||
|
|
||||||
|
return (((uint32_t)high2b << 16) | low2);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_SetCounter
|
||||||
|
*
|
||||||
|
* @brief Sets the RTC counter value.
|
||||||
|
*
|
||||||
|
* @param CounterValue - RTC counter new value.
|
||||||
|
*
|
||||||
|
* @return RTC counter value
|
||||||
|
*/
|
||||||
|
void RTC_SetCounter(uint32_t CounterValue)
|
||||||
|
{
|
||||||
|
RTC_EnterConfigMode();
|
||||||
|
RTC->CNTH = CounterValue >> 16;
|
||||||
|
RTC->CNTL = (CounterValue & RTC_LSB_MASK);
|
||||||
|
RTC_ExitConfigMode();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_SetPrescaler
|
||||||
|
*
|
||||||
|
* @brief Sets the RTC prescaler value
|
||||||
|
*
|
||||||
|
* @param PrescalerValue - RTC prescaler new value
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void RTC_SetPrescaler(uint32_t PrescalerValue)
|
||||||
|
{
|
||||||
|
RTC_EnterConfigMode();
|
||||||
|
RTC->PSCRH = (PrescalerValue & PRLH_MSB_MASK) >> 16;
|
||||||
|
RTC->PSCRL = (PrescalerValue & RTC_LSB_MASK);
|
||||||
|
RTC_ExitConfigMode();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_SetAlarm
|
||||||
|
*
|
||||||
|
* @brief Sets the RTC alarm value
|
||||||
|
*
|
||||||
|
* @param AlarmValue - RTC alarm new value
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void RTC_SetAlarm(uint32_t AlarmValue)
|
||||||
|
{
|
||||||
|
RTC_EnterConfigMode();
|
||||||
|
RTC->ALRMH = AlarmValue >> 16;
|
||||||
|
RTC->ALRML = (AlarmValue & RTC_LSB_MASK);
|
||||||
|
RTC_ExitConfigMode();
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_GetDivider
|
||||||
|
*
|
||||||
|
* @brief Gets the RTC divider value
|
||||||
|
*
|
||||||
|
* @return RTC Divider value
|
||||||
|
*/
|
||||||
|
uint32_t RTC_GetDivider(void)
|
||||||
|
{
|
||||||
|
uint16_t high1a = 0, high1b = 0, high2a = 0, high2b = 0;
|
||||||
|
uint16_t low1 = 0, low2 = 0;
|
||||||
|
|
||||||
|
do{
|
||||||
|
high1a = RTC->DIVH;
|
||||||
|
high1b = RTC->DIVH;
|
||||||
|
}while( high1a != high1b );
|
||||||
|
|
||||||
|
do{
|
||||||
|
low1 = RTC->DIVL;
|
||||||
|
low2 = RTC->DIVL;
|
||||||
|
}while( low1 != low2 );
|
||||||
|
|
||||||
|
do{
|
||||||
|
high2a = RTC->DIVH;
|
||||||
|
high2b = RTC->DIVH;
|
||||||
|
}while( high2a != high2b );
|
||||||
|
|
||||||
|
if(high1b != high2b)
|
||||||
|
{
|
||||||
|
do{
|
||||||
|
low1 = RTC->DIVL;
|
||||||
|
low2 = RTC->DIVL;
|
||||||
|
}while( low1 != low2 );
|
||||||
|
}
|
||||||
|
|
||||||
|
return ((((uint32_t)high2b & (uint32_t)0x000F) << 16) | low2);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_WaitForLastTask
|
||||||
|
*
|
||||||
|
* @brief Waits until last write operation on RTC registers has finished
|
||||||
|
* Note-
|
||||||
|
* This function must be called before any write to RTC registers.
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void RTC_WaitForLastTask(void)
|
||||||
|
{
|
||||||
|
while((RTC->CTLRL & RTC_FLAG_RTOFF) == (uint16_t)RESET)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_WaitForSynchro
|
||||||
|
*
|
||||||
|
* @brief Waits until the RTC registers are synchronized with RTC APB clock
|
||||||
|
* Note-
|
||||||
|
* This function must be called before any read operation after an APB reset
|
||||||
|
* or an APB clock stop.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void RTC_WaitForSynchro(void)
|
||||||
|
{
|
||||||
|
RTC->CTLRL &= (uint16_t)~RTC_FLAG_RSF;
|
||||||
|
while((RTC->CTLRL & RTC_FLAG_RSF) == (uint16_t)RESET)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_GetFlagStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified RTC flag is set or not
|
||||||
|
*
|
||||||
|
* @param RTC_FLAG- specifies the flag to check
|
||||||
|
* RTC_FLAG_RTOFF - RTC Operation OFF flag
|
||||||
|
* RTC_FLAG_RSF - Registers Synchronized flag
|
||||||
|
* RTC_FLAG_OW - Overflow flag
|
||||||
|
* RTC_FLAG_ALR - Alarm flag
|
||||||
|
* RTC_FLAG_SEC - Second flag
|
||||||
|
*
|
||||||
|
* @return The new state of RTC_FLAG (SET or RESET)
|
||||||
|
*/
|
||||||
|
FlagStatus RTC_GetFlagStatus(uint16_t RTC_FLAG)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
if((RTC->CTLRL & RTC_FLAG) != (uint16_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_ClearFlag
|
||||||
|
*
|
||||||
|
* @brief Clears the RTC's pending flags
|
||||||
|
*
|
||||||
|
* @param RTC_FLAG - specifies the flag to clear
|
||||||
|
* RTC_FLAG_RSF - Registers Synchronized flag
|
||||||
|
* RTC_FLAG_OW - Overflow flag
|
||||||
|
* RTC_FLAG_ALR - Alarm flag
|
||||||
|
* RTC_FLAG_SEC - Second flag
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void RTC_ClearFlag(uint16_t RTC_FLAG)
|
||||||
|
{
|
||||||
|
RTC->CTLRL &= (uint16_t)~RTC_FLAG;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_GetITStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified RTC interrupt has occurred or not
|
||||||
|
*
|
||||||
|
* @param RTC_IT - specifies the RTC interrupts sources to check
|
||||||
|
* RTC_FLAG_OW - Overflow interrupt
|
||||||
|
* RTC_FLAG_ALR - Alarm interrupt
|
||||||
|
* RTC_FLAG_SEC - Second interrupt
|
||||||
|
*
|
||||||
|
* @return The new state of the RTC_IT (SET or RESET)
|
||||||
|
*/
|
||||||
|
ITStatus RTC_GetITStatus(uint16_t RTC_IT)
|
||||||
|
{
|
||||||
|
ITStatus bitstatus = RESET;
|
||||||
|
|
||||||
|
bitstatus = (ITStatus)(RTC->CTLRL & RTC_IT);
|
||||||
|
if(((RTC->CTLRH & RTC_IT) != (uint16_t)RESET) && (bitstatus != (uint16_t)RESET))
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn RTC_ClearITPendingBit
|
||||||
|
*
|
||||||
|
* @brief Clears the RTC's interrupt pending bits
|
||||||
|
*
|
||||||
|
* @param RTC_IT - specifies the interrupt pending bit to clear
|
||||||
|
* RTC_FLAG_OW - Overflow interrupt
|
||||||
|
* RTC_FLAG_ALR - Alarm interrupt
|
||||||
|
* RTC_FLAG_SEC - Second interrupt
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void RTC_ClearITPendingBit(uint16_t RTC_IT)
|
||||||
|
{
|
||||||
|
RTC->CTLRL &= (uint16_t)~RTC_IT;
|
||||||
|
}
|
||||||
672
Peripheral/src/ch32v30x_sdio.c
Normal file
672
Peripheral/src/ch32v30x_sdio.c
Normal file
@@ -0,0 +1,672 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_SDIO.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file provides all the SDIO firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_sdio.h"
|
||||||
|
#include "ch32v30x_rcc.h"
|
||||||
|
|
||||||
|
#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
|
||||||
|
|
||||||
|
/* CLKCR register clear mask */
|
||||||
|
#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
|
||||||
|
|
||||||
|
/* SDIO PWRCTRL Mask */
|
||||||
|
#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
|
||||||
|
|
||||||
|
/* SDIO DCTRL Clear Mask */
|
||||||
|
#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
|
||||||
|
|
||||||
|
/* CMD Register clear mask */
|
||||||
|
#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
|
||||||
|
|
||||||
|
/* SDIO RESP Registers Address */
|
||||||
|
#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_DeInit
|
||||||
|
*
|
||||||
|
* @brief Deinitializes the SDIO peripheral registers to their default
|
||||||
|
* reset values.
|
||||||
|
*
|
||||||
|
* @return RTC counter value
|
||||||
|
*/
|
||||||
|
void SDIO_DeInit(void)
|
||||||
|
{
|
||||||
|
SDIO->POWER = 0x00000000;
|
||||||
|
SDIO->CLKCR = 0x00000000;
|
||||||
|
SDIO->ARG = 0x00000000;
|
||||||
|
SDIO->CMD = 0x00000000;
|
||||||
|
SDIO->DTIMER = 0x00000000;
|
||||||
|
SDIO->DLEN = 0x00000000;
|
||||||
|
SDIO->DCTRL = 0x00000000;
|
||||||
|
SDIO->ICR = 0x00C007FF;
|
||||||
|
SDIO->MASK = 0x00000000;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_Init
|
||||||
|
*
|
||||||
|
* @brief Initializes the SDIO peripheral according to the specified
|
||||||
|
* parameters in the SDIO_InitStruct.
|
||||||
|
*
|
||||||
|
* @param SDIO_InitStruct - pointer to a SDIO_InitTypeDef structure
|
||||||
|
* that contains the configuration information for the SDIO peripheral.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void SDIO_Init(SDIO_InitTypeDef *SDIO_InitStruct)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
|
||||||
|
tmpreg = SDIO->CLKCR;
|
||||||
|
tmpreg &= CLKCR_CLEAR_MASK;
|
||||||
|
tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
|
||||||
|
SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
|
||||||
|
SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
|
||||||
|
|
||||||
|
SDIO->CLKCR = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_StructInit
|
||||||
|
*
|
||||||
|
* @brief Fills each SDIO_InitStruct member with its default value.
|
||||||
|
*
|
||||||
|
* @param SDIO_InitStruct - pointer to an SDIO_InitTypeDef structure which
|
||||||
|
* will be initialized.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_StructInit(SDIO_InitTypeDef *SDIO_InitStruct)
|
||||||
|
{
|
||||||
|
SDIO_InitStruct->SDIO_ClockDiv = 0x00;
|
||||||
|
SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
|
||||||
|
SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
|
||||||
|
SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
|
||||||
|
SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
|
||||||
|
SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_ClockCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the SDIO Clock.
|
||||||
|
*
|
||||||
|
* @param SDIO_InitStruct - pointer to an SDIO_InitTypeDef structure which
|
||||||
|
* will be initialized.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_ClockCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
SDIO->CLKCR |= (1 << 8);
|
||||||
|
else
|
||||||
|
SDIO->CLKCR &= ~(1 << 8);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_SetPowerState
|
||||||
|
*
|
||||||
|
* @brief Sets the power status of the controller.
|
||||||
|
*
|
||||||
|
* @param SDIO_PowerState - new state of the Power state.
|
||||||
|
* SDIO_PowerState_OFF
|
||||||
|
* SDIO_PowerState_ON
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_SetPowerState(uint32_t SDIO_PowerState)
|
||||||
|
{
|
||||||
|
SDIO->POWER &= PWR_PWRCTRL_MASK;
|
||||||
|
SDIO->POWER |= SDIO_PowerState;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_GetPowerState
|
||||||
|
*
|
||||||
|
* @brief Gets the power status of the controller.
|
||||||
|
*
|
||||||
|
* @param CounterValue - RTC counter new value.
|
||||||
|
*
|
||||||
|
* @return power state -
|
||||||
|
* 0x00 - Power OFF
|
||||||
|
* 0x02 - Power UP
|
||||||
|
* 0x03 - Power ON
|
||||||
|
*/
|
||||||
|
uint32_t SDIO_GetPowerState(void)
|
||||||
|
{
|
||||||
|
return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_ITConfig
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the SDIO interrupts.
|
||||||
|
*
|
||||||
|
* @param DIO_IT - specifies the SDIO interrupt sources to be enabled or disabled.
|
||||||
|
* SDIO_IT_CCRCFAIL
|
||||||
|
* SDIO_IT_DCRCFAIL
|
||||||
|
* SDIO_IT_CTIMEOUT
|
||||||
|
* SDIO_IT_DTIMEOUT
|
||||||
|
* SDIO_IT_TXUNDERR
|
||||||
|
* SDIO_IT_RXOVERR
|
||||||
|
* SDIO_IT_CMDREND
|
||||||
|
* SDIO_IT_CMDSENT
|
||||||
|
* SDIO_IT_DATAEND
|
||||||
|
* SDIO_IT_STBITERR
|
||||||
|
* SDIO_IT_DBCKEND
|
||||||
|
* SDIO_IT_CMDACT
|
||||||
|
* SDIO_IT_TXACT
|
||||||
|
* SDIO_IT_RXACT
|
||||||
|
* SDIO_IT_TXFIFOHE
|
||||||
|
* SDIO_IT_RXFIFOHF
|
||||||
|
* SDIO_IT_TXFIFOF
|
||||||
|
* SDIO_IT_RXFIFOF
|
||||||
|
* SDIO_IT_TXFIFOE
|
||||||
|
* SDIO_IT_RXFIFOE
|
||||||
|
* SDIO_IT_TXDAVL
|
||||||
|
* SDIO_IT_RXDAVL
|
||||||
|
* SDIO_IT_SDIOIT
|
||||||
|
* SDIO_IT_CEATAEND
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
SDIO->MASK |= SDIO_IT;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SDIO->MASK &= ~SDIO_IT;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_DMACmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the SDIO DMA request.
|
||||||
|
*
|
||||||
|
* @param NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_DMACmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
SDIO->DCTRL |= (1 << 3);
|
||||||
|
else
|
||||||
|
SDIO->DCTRL &= ~(1 << 3);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_SendCommand
|
||||||
|
*
|
||||||
|
* @brief Initializes the SDIO Command according to the specified
|
||||||
|
* parameters in the SDIO_CmdInitStruct and send the command.
|
||||||
|
* @param SDIO_CmdInitStruct - pointer to a SDIO_CmdInitTypeDef
|
||||||
|
* structure that contains the configuration information for
|
||||||
|
* ddthe SDIO command.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
|
||||||
|
SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
|
||||||
|
|
||||||
|
tmpreg = SDIO->CMD;
|
||||||
|
tmpreg &= CMD_CLEAR_MASK;
|
||||||
|
tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
|
||||||
|
|
||||||
|
SDIO->CMD = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_CmdStructInit
|
||||||
|
*
|
||||||
|
* @brief Fills each SDIO_CmdInitStruct member with its default value.
|
||||||
|
*
|
||||||
|
* @param SDIO_CmdInitStruct - pointer to an SDIO_CmdInitTypeDef
|
||||||
|
* structure which will be initialized.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
|
||||||
|
{
|
||||||
|
SDIO_CmdInitStruct->SDIO_Argument = 0x00;
|
||||||
|
SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
|
||||||
|
SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
|
||||||
|
SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
|
||||||
|
SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_GetCommandResponse
|
||||||
|
*
|
||||||
|
* @brief Returns command index of last command for which response received.
|
||||||
|
*
|
||||||
|
* @return Returns the command index of the last command response received.
|
||||||
|
*/
|
||||||
|
uint8_t SDIO_GetCommandResponse(void)
|
||||||
|
{
|
||||||
|
return (uint8_t)(SDIO->RESPCMD);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_GetResponse
|
||||||
|
*
|
||||||
|
* @brief Returns response received from the card for the last command.
|
||||||
|
*
|
||||||
|
* @param SDIO_RESP - Specifies the SDIO response register.
|
||||||
|
* SDIO_RESP1 - Response Register 1
|
||||||
|
* SDIO_RESP2 - Response Register 2
|
||||||
|
* SDIO_RESP3 - Response Register 3
|
||||||
|
* SDIO_RESP4 - Response Register 4
|
||||||
|
*
|
||||||
|
* @return Returns the command index of the last command response received.
|
||||||
|
*/
|
||||||
|
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
|
||||||
|
{
|
||||||
|
__IO uint32_t tmp = 0;
|
||||||
|
|
||||||
|
tmp = SDIO_RESP_ADDR + SDIO_RESP;
|
||||||
|
|
||||||
|
return (*(__IO uint32_t *)tmp);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_DataConfig
|
||||||
|
*
|
||||||
|
* @brief Initializes the SDIO data path according to the specified
|
||||||
|
*
|
||||||
|
* @param SDIO_DataInitStruct - pointer to a SDIO_DataInitTypeDef structure that
|
||||||
|
* contains the configuration information for the SDIO command.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_DataConfig(SDIO_DataInitTypeDef *SDIO_DataInitStruct)
|
||||||
|
{
|
||||||
|
uint32_t tmpreg = 0;
|
||||||
|
|
||||||
|
SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
|
||||||
|
SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
|
||||||
|
tmpreg = SDIO->DCTRL;
|
||||||
|
tmpreg &= DCTRL_CLEAR_MASK;
|
||||||
|
tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
|
||||||
|
|
||||||
|
SDIO->DCTRL = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_DataStructInit
|
||||||
|
*
|
||||||
|
* @brief Fills each SDIO_DataInitStruct member with its default value.
|
||||||
|
*
|
||||||
|
* @param SDIO_DataInitStruct - pointer to an SDIO_DataInitTypeDef
|
||||||
|
* structure which will be initialized.
|
||||||
|
*
|
||||||
|
* @return RTC counter value
|
||||||
|
*/
|
||||||
|
void SDIO_DataStructInit(SDIO_DataInitTypeDef *SDIO_DataInitStruct)
|
||||||
|
{
|
||||||
|
SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
|
||||||
|
SDIO_DataInitStruct->SDIO_DataLength = 0x00;
|
||||||
|
SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
|
||||||
|
SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
|
||||||
|
SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
|
||||||
|
SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_GetDataCounter
|
||||||
|
*
|
||||||
|
* @brief Returns number of remaining data bytes to be transferred.
|
||||||
|
*
|
||||||
|
* @return Number of remaining data bytes to be transferred
|
||||||
|
*/
|
||||||
|
uint32_t SDIO_GetDataCounter(void)
|
||||||
|
{
|
||||||
|
return SDIO->DCOUNT;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_ReadData
|
||||||
|
*
|
||||||
|
* @brief Read one data word from Rx FIFO.
|
||||||
|
*
|
||||||
|
* @return Data received
|
||||||
|
*/
|
||||||
|
uint32_t SDIO_ReadData(void)
|
||||||
|
{
|
||||||
|
return SDIO->FIFO;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_WriteData
|
||||||
|
*
|
||||||
|
* @brief Write one data word to Tx FIFO.
|
||||||
|
*
|
||||||
|
* @param Data - 32-bit data word to write.
|
||||||
|
*
|
||||||
|
* @return RTC counter value
|
||||||
|
*/
|
||||||
|
void SDIO_WriteData(uint32_t Data)
|
||||||
|
{
|
||||||
|
SDIO->FIFO = Data;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_GetFIFOCount
|
||||||
|
*
|
||||||
|
* @brief Returns the number of words left to be written to or read from FIFO.
|
||||||
|
*
|
||||||
|
* @return Remaining number of words.
|
||||||
|
*/
|
||||||
|
uint32_t SDIO_GetFIFOCount(void)
|
||||||
|
{
|
||||||
|
return SDIO->FIFOCNT;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_StartSDIOReadWait
|
||||||
|
*
|
||||||
|
* @brief Starts the SD I/O Read Wait operation.
|
||||||
|
*
|
||||||
|
* @param NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_StartSDIOReadWait(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
SDIO->DCTRL |= (1 << 8);
|
||||||
|
else
|
||||||
|
SDIO->DCTRL &= ~(1 << 8);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_StopSDIOReadWait
|
||||||
|
*
|
||||||
|
* @brief Stops the SD I/O Read Wait operation.
|
||||||
|
*
|
||||||
|
* @param NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_StopSDIOReadWait(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
SDIO->DCTRL |= (1 << 9);
|
||||||
|
else
|
||||||
|
SDIO->DCTRL &= ~(1 << 9);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_SetSDIOReadWaitMode
|
||||||
|
*
|
||||||
|
* @brief Sets one of the two options of inserting read wait interval.
|
||||||
|
*
|
||||||
|
* @param SDIO_ReadWaitMode - SD I/O Read Wait operation mode.
|
||||||
|
* SDIO_ReadWaitMode_CLK - Read Wait control by stopping SDIOCLK
|
||||||
|
* SDIO_ReadWaitMode_DATA2 - Read Wait control using SDIO_DATA2
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
|
||||||
|
{
|
||||||
|
if(SDIO_ReadWaitMode)
|
||||||
|
SDIO->DCTRL |= (1 << 10);
|
||||||
|
else
|
||||||
|
SDIO->DCTRL &= ~(1 << 10);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_SetSDIOOperation
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the SD I/O Mode Operation.
|
||||||
|
*
|
||||||
|
* @param NewState: ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_SetSDIOOperation(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
SDIO->DCTRL |= (1 << 11);
|
||||||
|
else
|
||||||
|
SDIO->DCTRL &= ~(1 << 11);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_SendSDIOSuspendCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the SD I/O Mode suspend command sending.
|
||||||
|
*
|
||||||
|
* @param NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
SDIO->CMD |= (1 << 11);
|
||||||
|
else
|
||||||
|
SDIO->CMD &= ~(1 << 11);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_CommandCompletionCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the command completion signal.
|
||||||
|
*
|
||||||
|
* @param NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_CommandCompletionCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
SDIO->CMD |= (1 << 12);
|
||||||
|
else
|
||||||
|
SDIO->CMD &= ~(1 << 12);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_CEATAITCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the CE-ATA interrupt.
|
||||||
|
*
|
||||||
|
* @param NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_CEATAITCmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
SDIO->CMD |= (1 << 13);
|
||||||
|
else
|
||||||
|
SDIO->CMD &= ~(1 << 13);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_SendCEATACmd
|
||||||
|
*
|
||||||
|
* @brief Sends CE-ATA command (CMD61).
|
||||||
|
*
|
||||||
|
* @param NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return RTC counter value
|
||||||
|
*/
|
||||||
|
void SDIO_SendCEATACmd(FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState)
|
||||||
|
SDIO->CMD |= (1 << 14);
|
||||||
|
else
|
||||||
|
SDIO->CMD &= ~(1 << 14);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_GetFlagStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified SDIO flag is set or not.
|
||||||
|
*
|
||||||
|
* @param SDIO_FLAG - specifies the flag to check.
|
||||||
|
* SDIO_FLAG_CCRCFAIL - Command response received (CRC check failed)
|
||||||
|
* SDIO_FLAG_DCRCFAIL - Data block sent/received (CRC check failed)
|
||||||
|
* SDIO_FLAG_CTIMEOUT - Command response timeout
|
||||||
|
* SDIO_FLAG_DTIMEOUT - Data timeout
|
||||||
|
* SDIO_FLAG_TXUNDERR - Transmit FIFO underrun error
|
||||||
|
* SDIO_FLAG_RXOVERR - Received FIFO overrun error
|
||||||
|
* SDIO_FLAG_CMDREND - Command response received (CRC check passed)
|
||||||
|
* SDIO_FLAG_CMDSENT - Command sent (no response required)
|
||||||
|
* SDIO_FLAG_DATAEND - Data end (data counter, SDIDCOUNT, is zero)
|
||||||
|
* SDIO_FLAG_STBITERR - Start bit not detected on all data signals
|
||||||
|
* in wide bus mode.
|
||||||
|
* SDIO_FLAG_DBCKEND - Data block sent/received (CRC check passed)
|
||||||
|
* SDIO_FLAG_CMDACT - Command transfer in progress
|
||||||
|
* SDIO_FLAG_TXACT - Data transmit in progress
|
||||||
|
* SDIO_FLAG_RXACT - Data receive in progress
|
||||||
|
* SDIO_FLAG_TXFIFOHE - Transmit FIFO Half Empty
|
||||||
|
* SDIO_FLAG_RXFIFOHF - Receive FIFO Half Full
|
||||||
|
* SDIO_FLAG_TXFIFOF - Transmit FIFO full
|
||||||
|
* SDIO_FLAG_RXFIFOF - Receive FIFO full
|
||||||
|
* SDIO_FLAG_TXFIFOE - Transmit FIFO empty
|
||||||
|
* SDIO_FLAG_RXFIFOE - Receive FIFO empty
|
||||||
|
* SDIO_FLAG_TXDAVL - Data available in transmit FIFO
|
||||||
|
* SDIO_FLAG_RXDAVL - Data available in receive FIFO
|
||||||
|
* SDIO_FLAG_SDIOIT - SD I/O interrupt received
|
||||||
|
* SDIO_FLAG_CEATAEND - CE-ATA command completion signal received
|
||||||
|
* for CMD61
|
||||||
|
*
|
||||||
|
* @return ITStatus - SET or RESET
|
||||||
|
*/
|
||||||
|
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
|
||||||
|
if((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_ClearFlag
|
||||||
|
*
|
||||||
|
* @brief Clears the SDIO's pending flags.
|
||||||
|
*
|
||||||
|
* @param SDIO_FLAG - specifies the flag to clear.
|
||||||
|
* SDIO_FLAG_CCRCFAIL - Command response received (CRC check failed)
|
||||||
|
* SDIO_FLAG_DCRCFAIL - Data block sent/received (CRC check failed)
|
||||||
|
* SDIO_FLAG_CTIMEOUT - Command response timeout
|
||||||
|
* SDIO_FLAG_DTIMEOUT - Data timeout
|
||||||
|
* SDIO_FLAG_TXUNDERR - Transmit FIFO underrun error
|
||||||
|
* SDIO_FLAG_RXOVERR - Received FIFO overrun error
|
||||||
|
* SDIO_FLAG_CMDREND - Command response received (CRC check passed)
|
||||||
|
* SDIO_FLAG_CMDSENT - Command sent (no response required)
|
||||||
|
* SDIO_FLAG_DATAEND - Data end (data counter, SDIDCOUNT, is zero)
|
||||||
|
* SDIO_FLAG_STBITERR - Start bit not detected on all data signals
|
||||||
|
* in wide bus mode
|
||||||
|
* SDIO_FLAG_DBCKEND - Data block sent/received (CRC check passed)
|
||||||
|
* SDIO_FLAG_SDIOIT - SD I/O interrupt received
|
||||||
|
* SDIO_FLAG_CEATAEND - CE-ATA command completion signal received for CMD61
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SDIO_ClearFlag(uint32_t SDIO_FLAG)
|
||||||
|
{
|
||||||
|
SDIO->ICR = SDIO_FLAG;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_GetITStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified SDIO interrupt has occurred or not.
|
||||||
|
*
|
||||||
|
* @param SDIO_IT: specifies the SDIO interrupt source to check.
|
||||||
|
* SDIO_IT_CCRCFAIL - Command response received (CRC check failed) interrupt
|
||||||
|
* SDIO_IT_DCRCFAIL - Data block sent/received (CRC check failed) interrupt
|
||||||
|
* SDIO_IT_CTIMEOUT - Command response timeout interrupt
|
||||||
|
* SDIO_IT_DTIMEOUT - Data timeout interrupt
|
||||||
|
* SDIO_IT_TXUNDERR - Transmit FIFO underrun error interrupt
|
||||||
|
* SDIO_IT_RXOVERR - Received FIFO overrun error interrupt
|
||||||
|
* SDIO_IT_CMDREND - Command response received (CRC check passed) interrupt
|
||||||
|
* SDIO_IT_CMDSENT - Command sent (no response required) interrupt
|
||||||
|
* SDIO_IT_DATAEND - Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||||
|
* SDIO_IT_STBITERR - Start bit not detected on all data signals in wide
|
||||||
|
* bus mode interrupt
|
||||||
|
* SDIO_IT_DBCKEND - Data block sent/received (CRC check passed) interrupt
|
||||||
|
* SDIO_IT_CMDACT - Command transfer in progress interrupt
|
||||||
|
* SDIO_IT_TXACT - Data transmit in progress interrupt
|
||||||
|
* SDIO_IT_RXACT - Data receive in progress interrupt
|
||||||
|
* SDIO_IT_TXFIFOHE - Transmit FIFO Half Empty interrupt
|
||||||
|
* SDIO_IT_RXFIFOHF - Receive FIFO Half Full interrupt
|
||||||
|
* SDIO_IT_TXFIFOF - Transmit FIFO full interrupt
|
||||||
|
* SDIO_IT_RXFIFOF - Receive FIFO full interrupt
|
||||||
|
* SDIO_IT_TXFIFOE - Transmit FIFO empty interrupt
|
||||||
|
* SDIO_IT_RXFIFOE - Receive FIFO empty interrupt
|
||||||
|
* SDIO_IT_TXDAVL - Data available in transmit FIFO interrupt
|
||||||
|
* SDIO_IT_RXDAVL - Data available in receive FIFO interrupt
|
||||||
|
* SDIO_IT_SDIOIT - SD I/O interrupt received interrupt
|
||||||
|
* SDIO_IT_CEATAEND - CE-ATA command completion signal received for CMD61 interrupt
|
||||||
|
*
|
||||||
|
* @return ITStatus:SET or RESET
|
||||||
|
*/
|
||||||
|
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
|
||||||
|
{
|
||||||
|
ITStatus bitstatus = RESET;
|
||||||
|
|
||||||
|
if((SDIO->STA & SDIO_IT) != (uint32_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SDIO_ClearITPendingBit
|
||||||
|
*
|
||||||
|
* @brief Clears the SDIO's interrupt pending bits.
|
||||||
|
*
|
||||||
|
* @param SDIO_IT - specifies the interrupt pending bit to clear.
|
||||||
|
* SDIO_IT_CCRCFAIL - Command response received (CRC check failed) interrupt
|
||||||
|
* SDIO_IT_DCRCFAIL - Data block sent/received (CRC check failed) interrupt
|
||||||
|
* SDIO_IT_CTIMEOUT - Command response timeout interrupt
|
||||||
|
* SDIO_IT_DTIMEOUT - Data timeout interrupt
|
||||||
|
* SDIO_IT_TXUNDERR - Transmit FIFO underrun error interrupt
|
||||||
|
* SDIO_IT_RXOVERR - Received FIFO overrun error interrupt
|
||||||
|
* SDIO_IT_CMDREND - Command response received (CRC check passed) interrupt
|
||||||
|
* SDIO_IT_CMDSENT - Command sent (no response required) interrupt
|
||||||
|
* SDIO_IT_DATAEND - Data end (data counter, SDIDCOUNT, is zero) interrupt
|
||||||
|
* SDIO_IT_STBITERR - Start bit not detected on all data signals in wide
|
||||||
|
* bus mode interrupt
|
||||||
|
* SDIO_IT_SDIOIT - SD I/O interrupt received interrupt
|
||||||
|
* SDIO_IT_CEATAEND - CE-ATA command completion signal received for CMD61
|
||||||
|
*
|
||||||
|
* @return RTC counter value
|
||||||
|
*/
|
||||||
|
void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
|
||||||
|
{
|
||||||
|
SDIO->ICR = SDIO_IT;
|
||||||
|
}
|
||||||
668
Peripheral/src/ch32v30x_spi.c
Normal file
668
Peripheral/src/ch32v30x_spi.c
Normal file
@@ -0,0 +1,668 @@
|
|||||||
|
/********************************** (C) COPYRIGHT *******************************
|
||||||
|
* File Name : ch32v30x_spi.c
|
||||||
|
* Author : WCH
|
||||||
|
* Version : V1.0.0
|
||||||
|
* Date : 2021/06/06
|
||||||
|
* Description : This file provides all the SPI firmware functions.
|
||||||
|
*********************************************************************************
|
||||||
|
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||||
|
* Attention: This software (modified or not) and binary are used for
|
||||||
|
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||||
|
*******************************************************************************/
|
||||||
|
#include "ch32v30x_spi.h"
|
||||||
|
#include "ch32v30x_rcc.h"
|
||||||
|
|
||||||
|
/* SPI SPE mask */
|
||||||
|
#define CTLR1_SPE_Set ((uint16_t)0x0040)
|
||||||
|
#define CTLR1_SPE_Reset ((uint16_t)0xFFBF)
|
||||||
|
|
||||||
|
/* I2S I2SE mask */
|
||||||
|
#define I2SCFGR_I2SE_Set ((uint16_t)0x0400)
|
||||||
|
#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF)
|
||||||
|
|
||||||
|
/* SPI CRCNext mask */
|
||||||
|
#define CTLR1_CRCNext_Set ((uint16_t)0x1000)
|
||||||
|
|
||||||
|
/* SPI CRCEN mask */
|
||||||
|
#define CTLR1_CRCEN_Set ((uint16_t)0x2000)
|
||||||
|
#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF)
|
||||||
|
|
||||||
|
/* SPI SSOE mask */
|
||||||
|
#define CTLR2_SSOE_Set ((uint16_t)0x0004)
|
||||||
|
#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB)
|
||||||
|
|
||||||
|
/* SPI registers Masks */
|
||||||
|
#define CTLR1_CLEAR_Mask ((uint16_t)0x3040)
|
||||||
|
#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)
|
||||||
|
|
||||||
|
/* SPI or I2S mode selection masks */
|
||||||
|
#define SPI_Mode_Select ((uint16_t)0xF7FF)
|
||||||
|
#define I2S_Mode_Select ((uint16_t)0x0800)
|
||||||
|
|
||||||
|
/* I2S clock source selection masks */
|
||||||
|
#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000))
|
||||||
|
#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000))
|
||||||
|
#define I2S_MUL_MASK ((uint32_t)(0x0000F000))
|
||||||
|
#define I2S_DIV_MASK ((uint32_t)(0x000000F0))
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_I2S_DeInit
|
||||||
|
*
|
||||||
|
* @brief Deinitializes the SPIx peripheral registers to their default
|
||||||
|
* reset values (Affects also the I2Ss).
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_I2S_DeInit(SPI_TypeDef *SPIx)
|
||||||
|
{
|
||||||
|
if(SPIx == SPI1)
|
||||||
|
{
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
|
||||||
|
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
|
||||||
|
}
|
||||||
|
else if(SPIx == SPI2)
|
||||||
|
{
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if(SPIx == SPI3)
|
||||||
|
{
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
|
||||||
|
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_Init
|
||||||
|
*
|
||||||
|
* @brief Initializes the SPIx peripheral according to the specified
|
||||||
|
* parameters in the SPI_InitStruct.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* SPI_InitStruct - pointer to a SPI_InitTypeDef structure that
|
||||||
|
* contains the configuration information for the specified SPI peripheral.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
|
||||||
|
{
|
||||||
|
uint16_t tmpreg = 0;
|
||||||
|
|
||||||
|
tmpreg = SPIx->CTLR1;
|
||||||
|
tmpreg &= CTLR1_CLEAR_Mask;
|
||||||
|
tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
|
||||||
|
SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
|
||||||
|
SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
|
||||||
|
SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
|
||||||
|
|
||||||
|
SPIx->CTLR1 = tmpreg;
|
||||||
|
SPIx->I2SCFGR &= SPI_Mode_Select;
|
||||||
|
SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn I2S_Init
|
||||||
|
*
|
||||||
|
* @brief Initializes the SPIx peripheral according to the specified
|
||||||
|
* parameters in the I2S_InitStruct.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* (configured in I2S mode).
|
||||||
|
* I2S_InitStruct - pointer to an I2S_InitTypeDef structure that
|
||||||
|
* contains the configuration information for the specified SPI peripheral
|
||||||
|
* configured in I2S mode.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct)
|
||||||
|
{
|
||||||
|
uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
|
||||||
|
uint32_t tmp = 0;
|
||||||
|
RCC_ClocksTypeDef RCC_Clocks;
|
||||||
|
uint32_t sourceclock = 0;
|
||||||
|
|
||||||
|
SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
|
||||||
|
SPIx->I2SPR = 0x0002;
|
||||||
|
tmpreg = SPIx->I2SCFGR;
|
||||||
|
|
||||||
|
if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
|
||||||
|
{
|
||||||
|
i2sodd = (uint16_t)0;
|
||||||
|
i2sdiv = (uint16_t)2;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
|
||||||
|
{
|
||||||
|
packetlength = 1;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
packetlength = 2;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(((uint32_t)SPIx) == SPI2_BASE)
|
||||||
|
{
|
||||||
|
tmp = I2S2_CLOCK_SRC;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
tmp = I2S3_CLOCK_SRC;
|
||||||
|
}
|
||||||
|
|
||||||
|
RCC_GetClocksFreq(&RCC_Clocks);
|
||||||
|
|
||||||
|
sourceclock = RCC_Clocks.SYSCLK_Frequency;
|
||||||
|
|
||||||
|
if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
|
||||||
|
{
|
||||||
|
tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
|
||||||
|
}
|
||||||
|
|
||||||
|
tmp = tmp / 10;
|
||||||
|
i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
|
||||||
|
i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
|
||||||
|
i2sodd = (uint16_t)(i2sodd << 8);
|
||||||
|
}
|
||||||
|
|
||||||
|
if((i2sdiv < 2) || (i2sdiv > 0xFF))
|
||||||
|
{
|
||||||
|
i2sdiv = 2;
|
||||||
|
i2sodd = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
|
||||||
|
tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode |
|
||||||
|
(uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat |
|
||||||
|
(uint16_t)I2S_InitStruct->I2S_CPOL))));
|
||||||
|
SPIx->I2SCFGR = tmpreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_StructInit
|
||||||
|
*
|
||||||
|
* @brief Fills each SPI_InitStruct member with its default value.
|
||||||
|
*
|
||||||
|
* @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which
|
||||||
|
* will be initialized.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct)
|
||||||
|
{
|
||||||
|
SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
|
||||||
|
SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
|
||||||
|
SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
|
||||||
|
SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
|
||||||
|
SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
|
||||||
|
SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
|
||||||
|
SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
|
||||||
|
SPI_InitStruct->SPI_CRCPolynomial = 7;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn I2S_StructInit
|
||||||
|
*
|
||||||
|
* @brief Fills each I2S_InitStruct member with its default value.
|
||||||
|
*
|
||||||
|
* @param I2S_InitStruct - pointer to a I2S_InitTypeDef structure which
|
||||||
|
* will be initialized.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct)
|
||||||
|
{
|
||||||
|
I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
|
||||||
|
I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
|
||||||
|
I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
|
||||||
|
I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
|
||||||
|
I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
|
||||||
|
I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_Cmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the specified SPI peripheral.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
SPIx->CTLR1 |= CTLR1_SPE_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SPIx->CTLR1 &= CTLR1_SPE_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn I2S_Cmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the specified SPI peripheral (in I2S mode).
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_I2S_ITConfig
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the specified SPI/I2S interrupts.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be
|
||||||
|
* - 1, 2 or 3 in SPI mode.
|
||||||
|
* - 2 or 3 in I2S mode.
|
||||||
|
* SPI_I2S_IT - specifies the SPI/I2S interrupt source to be
|
||||||
|
* enabled or disabled.
|
||||||
|
* SPI_I2S_IT_TXE - Tx buffer empty interrupt mask.
|
||||||
|
* SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask.
|
||||||
|
* SPI_I2S_IT_ERR - Error interrupt mask.
|
||||||
|
* NewState: ENABLE or DISABLE.
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
uint16_t itpos = 0, itmask = 0;
|
||||||
|
|
||||||
|
itpos = SPI_I2S_IT >> 4;
|
||||||
|
itmask = (uint16_t)1 << (uint16_t)itpos;
|
||||||
|
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
SPIx->CTLR2 |= itmask;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SPIx->CTLR2 &= (uint16_t)~itmask;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_I2S_DMACmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the SPIx/I2Sx DMA interface.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be
|
||||||
|
* - 1, 2 or 3 in SPI mode.
|
||||||
|
* - 2 or 3 in I2S mode.
|
||||||
|
* SPI_I2S_DMAReq - specifies the SPI/I2S DMA transfer request to
|
||||||
|
* be enabled or disabled.
|
||||||
|
* SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request.
|
||||||
|
* SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request.
|
||||||
|
* NewState - ENABLE or DISABLE.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
SPIx->CTLR2 |= SPI_I2S_DMAReq;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_I2S_SendData
|
||||||
|
*
|
||||||
|
* @brief Transmits a Data through the SPIx/I2Sx peripheral.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be
|
||||||
|
* - 1, 2 or 3 in SPI mode.
|
||||||
|
* - 2 or 3 in I2S mode.
|
||||||
|
* Data - Data to be transmitted.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data)
|
||||||
|
{
|
||||||
|
SPIx->DATAR = Data;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_I2S_ReceiveData
|
||||||
|
*
|
||||||
|
* @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be
|
||||||
|
* - 1, 2 or 3 in SPI mode.
|
||||||
|
* - 2 or 3 in I2S mode.
|
||||||
|
* Data - Data to be transmitted.
|
||||||
|
*
|
||||||
|
* @return SPIx->DATAR - The value of the received data.
|
||||||
|
*/
|
||||||
|
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx)
|
||||||
|
{
|
||||||
|
return SPIx->DATAR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_NSSInternalSoftwareConfig
|
||||||
|
*
|
||||||
|
* @brief Configures internally by software the NSS pin for the selected SPI.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* SPI_NSSInternalSoft -
|
||||||
|
* SPI_NSSInternalSoft_Set - Set NSS pin internally.
|
||||||
|
* SPI_NSSInternalSoft_Reset - Reset NSS pin internally.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft)
|
||||||
|
{
|
||||||
|
if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
|
||||||
|
{
|
||||||
|
SPIx->CTLR1 |= SPI_NSSInternalSoft_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_SSOutputCmd
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the SS output for the selected SPI.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* NewState - new state of the SPIx SS output.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
SPIx->CTLR2 |= CTLR2_SSOE_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SPIx->CTLR2 &= CTLR2_SSOE_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_DataSizeConfig
|
||||||
|
*
|
||||||
|
* @brief Configures the data size for the selected SPI.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* SPI_DataSize - specifies the SPI data size.
|
||||||
|
* SPI_DataSize_16b - Set data frame format to 16bit.
|
||||||
|
* SPI_DataSize_8b - Set data frame format to 8bit.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize)
|
||||||
|
{
|
||||||
|
SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b;
|
||||||
|
SPIx->CTLR1 |= SPI_DataSize;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_TransmitCRC
|
||||||
|
*
|
||||||
|
* @brief Transmit the SPIx CRC value.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_TransmitCRC(SPI_TypeDef *SPIx)
|
||||||
|
{
|
||||||
|
SPIx->CTLR1 |= CTLR1_CRCNext_Set;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_CalculateCRC
|
||||||
|
*
|
||||||
|
* @brief Enables or disables the CRC value calculation of the transferred bytes.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* NewState - new state of the SPIx CRC value calculation.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState)
|
||||||
|
{
|
||||||
|
if(NewState != DISABLE)
|
||||||
|
{
|
||||||
|
SPIx->CTLR1 |= CTLR1_CRCEN_Set;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SPIx->CTLR1 &= CTLR1_CRCEN_Reset;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_GetCRC
|
||||||
|
*
|
||||||
|
* @brief Returns the transmit or the receive CRC register value for the specified SPI.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* SPI_CRC - specifies the CRC register to be read.
|
||||||
|
* SPI_CRC_Tx - Selects Tx CRC register.
|
||||||
|
* SPI_CRC_Rx - Selects Rx CRC register.
|
||||||
|
*
|
||||||
|
* @return crcreg: The selected CRC register value.
|
||||||
|
*/
|
||||||
|
uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC)
|
||||||
|
{
|
||||||
|
uint16_t crcreg = 0;
|
||||||
|
|
||||||
|
if(SPI_CRC != SPI_CRC_Rx)
|
||||||
|
{
|
||||||
|
crcreg = SPIx->TCRCR;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
crcreg = SPIx->RCRCR;
|
||||||
|
}
|
||||||
|
|
||||||
|
return crcreg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_GetCRCPolynomial
|
||||||
|
*
|
||||||
|
* @brief Returns the CRC Polynomial register value for the specified SPI.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
*
|
||||||
|
* @return SPIx->CRCR - The CRC Polynomial register value.
|
||||||
|
*/
|
||||||
|
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
|
||||||
|
{
|
||||||
|
return SPIx->CRCR;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_BiDirectionalLineConfig
|
||||||
|
*
|
||||||
|
* @brief Selects the data transfer direction in bi-directional mode
|
||||||
|
* for the specified SPI.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
|
||||||
|
* SPI_Direction - specifies the data transfer direction in
|
||||||
|
* bi-directional mode.
|
||||||
|
* SPI_Direction_Tx - Selects Tx transmission direction.
|
||||||
|
* SPI_Direction_Rx - Selects Rx receive direction.
|
||||||
|
*
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction)
|
||||||
|
{
|
||||||
|
if(SPI_Direction == SPI_Direction_Tx)
|
||||||
|
{
|
||||||
|
SPIx->CTLR1 |= SPI_Direction_Tx;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SPIx->CTLR1 &= SPI_Direction_Rx;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_I2S_GetFlagStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified SPI/I2S flag is set or not.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be
|
||||||
|
* - 1, 2 or 3 in SPI mode.
|
||||||
|
* - 2 or 3 in I2S mode.
|
||||||
|
* SPI_I2S_FLAG - specifies the SPI/I2S flag to check.
|
||||||
|
* SPI_I2S_FLAG_TXE - Transmit buffer empty flag.
|
||||||
|
* SPI_I2S_FLAG_RXNE - Receive buffer not empty flag.
|
||||||
|
* SPI_I2S_FLAG_BSY - Busy flag.
|
||||||
|
* SPI_I2S_FLAG_OVR - Overrun flag.
|
||||||
|
* SPI_FLAG_MODF - Mode Fault flag.
|
||||||
|
* SPI_FLAG_CRCERR - CRC Error flag.
|
||||||
|
* I2S_FLAG_UDR - Underrun Error flag.
|
||||||
|
* I2S_FLAG_CHSIDE - Channel Side flag.
|
||||||
|
*
|
||||||
|
* @return FlagStatus: SET or RESET.
|
||||||
|
*/
|
||||||
|
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
|
||||||
|
{
|
||||||
|
FlagStatus bitstatus = RESET;
|
||||||
|
|
||||||
|
if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_I2S_ClearFlag
|
||||||
|
*
|
||||||
|
* @brief Clears the SPIx CRC Error (CRCERR) flag.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be
|
||||||
|
* - 1, 2 or 3 in SPI mode.
|
||||||
|
* - 2 or 3 in I2S mode.
|
||||||
|
* SPI_I2S_FLAG - specifies the SPI flag to clear.
|
||||||
|
* SPI_FLAG_CRCERR - CRC Error flag.
|
||||||
|
* Note-
|
||||||
|
* - OVR (OverRun error) flag is cleared by software sequence: a read
|
||||||
|
* operation to SPI_DATAR register (SPI_I2S_ReceiveData()) followed by a read
|
||||||
|
* operation to SPI_STATR register (SPI_I2S_GetFlagStatus()).
|
||||||
|
* - UDR (UnderRun error) flag is cleared by a read operation to
|
||||||
|
* SPI_STATR register (SPI_I2S_GetFlagStatus()).
|
||||||
|
* - MODF (Mode Fault) flag is cleared by software sequence: a read/write
|
||||||
|
* operation to SPI_STATR register (SPI_I2S_GetFlagStatus()) followed by a
|
||||||
|
* write operation to SPI_CTLR1 register (SPI_Cmd() to enable the SPI).
|
||||||
|
* @return FlagStatus: SET or RESET.
|
||||||
|
*/
|
||||||
|
void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
|
||||||
|
{
|
||||||
|
SPIx->STATR = (uint16_t)~SPI_I2S_FLAG;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_I2S_GetITStatus
|
||||||
|
*
|
||||||
|
* @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be
|
||||||
|
* - 1, 2 or 3 in SPI mode.
|
||||||
|
* - 2 or 3 in I2S mode.
|
||||||
|
* SPI_I2S_IT - specifies the SPI/I2S interrupt source to check..
|
||||||
|
* SPI_I2S_IT_TXE - Transmit buffer empty interrupt.
|
||||||
|
* SPI_I2S_IT_RXNE - Receive buffer not empty interrupt.
|
||||||
|
* SPI_I2S_IT_OVR - Overrun interrupt.
|
||||||
|
* SPI_IT_MODF - Mode Fault interrupt.
|
||||||
|
* SPI_IT_CRCERR - CRC Error interrupt.
|
||||||
|
* I2S_IT_UDR - Underrun Error interrupt.
|
||||||
|
*
|
||||||
|
* @return FlagStatus: SET or RESET.
|
||||||
|
*/
|
||||||
|
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
|
||||||
|
{
|
||||||
|
ITStatus bitstatus = RESET;
|
||||||
|
uint16_t itpos = 0, itmask = 0, enablestatus = 0;
|
||||||
|
|
||||||
|
itpos = 0x01 << (SPI_I2S_IT & 0x0F);
|
||||||
|
itmask = SPI_I2S_IT >> 4;
|
||||||
|
itmask = 0x01 << itmask;
|
||||||
|
enablestatus = (SPIx->CTLR2 & itmask);
|
||||||
|
|
||||||
|
if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus)
|
||||||
|
{
|
||||||
|
bitstatus = SET;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
bitstatus = RESET;
|
||||||
|
}
|
||||||
|
|
||||||
|
return bitstatus;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*********************************************************************
|
||||||
|
* @fn SPI_I2S_ClearITPendingBit
|
||||||
|
*
|
||||||
|
* @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
|
||||||
|
*
|
||||||
|
* @param SPIx - where x can be
|
||||||
|
* - 1, 2 or 3 in SPI mode.
|
||||||
|
* SPI_I2S_IT - specifies the SPI interrupt pending bit to clear.
|
||||||
|
* SPI_IT_CRCERR - CRC Error interrupt.
|
||||||
|
* Note-
|
||||||
|
* - OVR (OverRun Error) interrupt pending bit is cleared by software
|
||||||
|
* sequence: a read operation to SPI_DATAR register (SPI_I2S_ReceiveData())
|
||||||
|
* followed by a read operation to SPI_STATR register (SPI_I2S_GetITStatus()).
|
||||||
|
* - UDR (UnderRun Error) interrupt pending bit is cleared by a read
|
||||||
|
* operation to SPI_STATR register (SPI_I2S_GetITStatus()).
|
||||||
|
* - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
|
||||||
|
* a read/write operation to SPI_STATR register (SPI_I2S_GetITStatus())
|
||||||
|
* followed by a write operation to SPI_CTLR1 register (SPI_Cmd() to enable
|
||||||
|
* the SPI).
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
|
||||||
|
{
|
||||||
|
uint16_t itpos = 0;
|
||||||
|
|
||||||
|
itpos = 0x01 << (SPI_I2S_IT & 0x0F);
|
||||||
|
SPIx->STATR = (uint16_t)~itpos;
|
||||||
|
}
|
||||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user